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11862631 | DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described with reference to the drawings as appropriate. First Embodiment: Radiation Resistant Circuit Device A radiation resistant circuit device1A according to a first embodiment of the invention will be described with reference toFIGS.1and3B. FIG.1is a diagram showing a configuration example of a cross section of the radiation resistant circuit device1A according to the first embodiment of the invention. InFIG.1, the radiation resistant circuit device1A includes a SiC semiconductor element10, a printed board21, and an insulating material13. A conductive wiring22and a covering material23are constituent elements provided in the printed board21in the present embodiment as to be described later. In addition, a SiC integrated circuit11is a constituent element provided in the SiC semiconductor element10in the present embodiment as to be described later. <<SiC Semiconductor Element10>> InFIG.1, in a portion shown in a cross section, the SiC semiconductor element10includes the SiC integrated circuit11, electrodes (Cu electrodes)12A,12B and12C, wire bondings14A and14B, and a molding resin15. However, the SiC semiconductor element10also includes a plurality of electrodes and wire bondings in a portion that is not shown. The SiC integrated circuit11includes an operational amplifier of an analog circuit, a logic circuit, or the like, using SiC (silicon carbide) that is resistant to radiation or a high temperature. Although a metal oxide semiconductor field effect transistor (MOSFET) is also used for the SiC integrated circuit11, in a case of configuring the operational amplifier of the analog circuit, when a bipolar transistor, a diode, or a resistor, a capacitor, and a wiring are mainly used, a resistance to the radiation is extremely strong. In addition, terminals of the SiC integrated circuit11are electrically connected to the electrodes12A and12B of the SiC semiconductor element10by the wire bondings14A and14B. The electrode (substrate electrode)12C of a substrate inFIG.1is connected to a positive power supply (Vdd) potential electrode (not shown) of the SiC semiconductor element10by a wire bonding (not shown). Then, the SiC integrated circuit11and the electrodes12A,12B and12C are shielded by the molding resin15. The SiC semiconductor element10is an electronic component equipped on the printed board21by adopting the above configuration. <<Printed Board21>> The printed board21includes a plurality of layer configurations, and on a front surface or a back surface thereof, the above SiC semiconductor element10or various electronic components (not shown) are equipped. In addition, a plurality of wirings are provided in a plurality of layers inside the printed board21, and configure circuit wirings together with wirings passing through through holes to interlayers, the front surface or the back surface. InFIG.1, the SiC semiconductor element10is provided on the front surface of the printed board21, and the conductive wiring22is provided below the SiC semiconductor element10with the insulating material13(insulating means) and the covering material23interposed therebetween. At least a part of the conductive wiring22is provided directly below the SiC integrated circuit11that is equipped on the SiC semiconductor element10. Therefore, a bottom surface of the electrode (the substrate electrode)12C of the substrate of the SiC integrated circuit11and a part of an upper surface (a predetermined surface) of the conductive wiring22face each other. In addition, the conductive wiring22is, for example, connected to a wiring of a fixed voltage (for example, the Vdd or a negative power supply potential Vss) such as a power supply wiring. In addition, as described above, the insulating material13is provided directly below the SiC integrated circuit11. Accordingly, between the bottom surface of the electrode (the substrate electrode)12C of the substrate forming the SiC integrated circuit11and the part of the upper surface (the predetermined surface) of the conductive wiring22of the printed board21, a parasitic capacitance (a parasitic electrostatic capacitance)20having a large value is formed via the insulating material13and the covering material23. As the insulating material13, for example, a resin material, a rubber material, or the like is used. <<Parasitic Capacitance and Noise Resistance>> According to the above configuration, the electrode12C of the substrate connected to the Vdd of the SiC integrated circuit11and the conductive wiring22to which a fixed potential (for example, the Vdd) is supplied are coupled via the insulating material13and the covering material23with the parasitic capacitance (the parasitic electrostatic capacitance)20having the large value, so that a potential of the substrate (the electrode12C) of the SiC integrated circuit11is stabilized. Therefore, an operation of the SiC integrated circuit11(the SiC semiconductor element10) against noise or drift in a radiation environment is stabilized. In the configuration ofFIG.1, it is desirable that the conductive wiring22is the wiring of the fixed voltage such as the power supply wiring as described above. Further, it is desirable that the conductive wiring22is the wiring of the positive power supply potential (the Vdd). The reasons are that the parasitic capacitance between the conductive wiring22and a bottom of the SiC integrated circuit11(the SiC semiconductor element10) is stabilized and can be easily secured to a predetermined value, and that since the power supply wiring is generally less affected by the noise, a drive voltage applied to the SiC integrated circuit11(the SiC semiconductor element10) can be more stabilized. Overview of First Embodiment The radiation resistant circuit device1A of the first embodiment uses the SiC integrated circuit11that is resistant to the radiation. Further, by forming the parasitic capacitance (the parasitic electrostatic capacitance)20having the large value, the potential of the substrate forming the SiC integrated circuit11is stabilized. Therefore, the SiC integrated circuit11and the SiC semiconductor element10operate stably even with respect to radiation irradiation, or noise generated by the operation of the SiC integrated circuit11, or turning on/off of power supply of other devices. That is, the SiC integrated circuit11and the SiC semiconductor element10reduce characteristic deterioration caused by the radiation irradiation, output an accurate value even when the SiC semiconductor element10, a circuit using the same, and a measuring instrument are irradiated with the radiation, and operate normally even in the radiation environment. Since the analog circuit such as the operational amplifier (not shown) in the SiC integrated circuit11is also easily affected by drift or weak noise caused by the radiation irradiation during the operation, the above noise countermeasures are particularly effective for the SiC integrated circuit11including the analog circuit. Although the SiC integrated circuit11uses the SiC as an element, an n-type substrate is generally used as a SiC substrate. Therefore, it is difficult to obtain a SiC p-type substrate. In such a situation, an effect of a stable operation obtained by the configuration including the large value of parasitic capacitance20is important. The stable operation of the SiC integrated circuit11against this noise will be described in detail later with reference toFIGS.3A and3B. Modification 1 of First Embodiment FIG.1shows an example in which the conductive wiring22connected to the wiring of the fixed voltage is arranged such that the predetermined surface of the upper surface thereof is directly below the entire bottom surface of the electrode (the substrate electrode)12C of the substrate of the SiC integrated circuit11. In other words, an example is shown in which the entire area of the electrode (the substrate electrode)12C of the substrate is accommodated within a region of the conductive wiring22in a plan view. However, even when the predetermined surface of the upper surface of the conductive wiring22is only arranged so as to be directly below a part of the bottom surface of the electrode (the substrate electrode)12C of the substrate of the SiC integrated circuit11, an effect of reducing the noise is obtained. Modification 2 of First Embodiment As described above,FIG.1shows the example in which the conductive wiring22connected to the wiring of the fixed voltage is arranged such that the predetermined surface of the upper surface thereof is directly below the entire bottom surface of the electrode (the substrate electrode)12C of the substrate of the SiC integrated circuit11. However, when the conductive wiring22is arranged so as to be directly below the entire SiC semiconductor element10, that is, when all the constituent elements of the SiC semiconductor element10are accommodated within the region of the conductive wiring22in a plan view, there is a possibility that not only the noise of the SiC integrated circuit11is further reduced, but also the noise of each component and wiring of the SiC semiconductor element10is reduced. Effect of First Embodiment With the configuration in which the parasitic capacitance20having the large value is provided between the substrate forming the SiC integrated circuit11and the predetermined surface of the upper surface of the conductive wiring22of the printed board21via the insulating material13and the covering material23, an effect may be obtained that the SiC integrated circuit11and the SiC semiconductor element10operate stably with resistance with respect to noise or drift caused by operation of the SiC integrated circuit11and generated in the radiation irradiation or during the operation. Second Embodiment: Radiation Resistant Circuit Device Next, a radiation resistant circuit device1B according to a second embodiment of the invention will be described with reference toFIG.2. FIG.2is a diagram showing a configuration example of a cross section of the radiation resistant circuit device1B according to the second embodiment of the invention. InFIG.2, the radiation resistant circuit device1B includes the SiC semiconductor element10, the printed board21, and second metal electrodes (solders)16A and16B, and a space17. The printed board21includes a plurality of layer configurations, as inFIG.1in the first embodiment, on the front surface or the back surface, the SiC semiconductor element10and various electronic components (not shown) are equipped, but since the SiC semiconductor element10and the electronic components are not directly related to the noise under the radiation which is the problem to be solved by the invention, descriptions thereof are omitted. InFIG.2, the second metal electrodes16A and16B are provided in order to connect the electrodes12A and12B and an electric wiring of the printed board21. By providing the second metal electrodes16A and16B, the space17is formed between the electrode12C of the substrate of the SiC integrated circuit11and the printed board21. A function of the space17(insulation means) inFIG.2is electrical isolation, which is the same as the insulating material13inFIG.1. According to the above configuration, the bottom surface of the electrode (the substrate electrode)12C of the substrate of the SiC integrated circuit11and a part of the upper surface (the predetermined surface) of the conductive wiring22face each other. In addition, the conductive wiring22is, for example, connected to a wiring of a fixed voltage (for example, Vdd or Vss) such as a power supply wiring. In addition, as described above, the space17is provided directly below the SiC integrated circuit11. According to the configuration, between the bottom surface of the electrode (the substrate electrode)12C of the substrate forming the SiC integrated circuit11and the part of the upper surface (the predetermined surface) of the conductive wiring22of the printed board21, a parasitic capacitance (a parasitic electrostatic capacitance)20B having a large value is formed via the space17and the covering material23. By forming the parasitic capacitance20B between the electrode (the substrate electrode)12C of the substrate forming the SiC integrated circuit11and the conductive wiring22connected to the fixed voltage such as the power supply wiring, the SiC integrated circuit11and the SiC semiconductor element10operate stably even with respect to the radiation irradiation, or noise generated by the operation of the SiC integrated circuit11, and turning on/off of the power supply of the other devices. Since a distance in the space17between the electrode12C of the substrate and the printed board21(the covering material23) has a trade-off relationship between an insulating property and a capacitance value of the parasitic capacitance20B, the distance is appropriately determined according to a situation of a manufacturing process. In addition, the electrode12C, which is the substrate electrode, may also be sealed with the molding resin, but it is desirable to use a metal electrode in consideration of heat dissipation. Effect of Second Embodiment The radiation resistant circuit device1B according to the second embodiment of the invention does not use the insulating material13(FIG.1) of the first embodiment, which may contribute to a cost reduction or a process reduction. In addition, the radiation resistant circuit device1B according to the second embodiment of the invention is similar to the radiation resistant circuit device1A according to the first embodiment, and due to the operation of the SiC integrated circuit11, and has an effect that the SiC integrated circuit11and the SiC semiconductor element10operate stably with resistance with respect to noise or drift caused by operation of the SiC integrated circuit11and generated in the radiation irradiation or during the operation. <Substrates in SiC Integrated Circuit and Si Integrated Circuit> Substrates in the SiC integrated circuit and Si integrated circuit will be described with reference toFIGS.3A and3B. <<Substrate in Si Integrated Circuit>> FIG.3Ais a diagram showing a structural example of a cross section including a substrate in a Si integrated circuit101. In the Si integrated circuit101of a Si semiconductor shown inFIG.3A, a p substrate has been widely used. That is, as an integrated circuit using the Si (silicon), the p substrate is versatile and can be easily procured. InFIG.3A, in the Si integrated circuit101, a substrate111is formed by the p substrate (p-Si) which is a p-type semiconductor, and a p-type epitaxial layer112is formed thereon. Then, an n-well (121) and a p-well (122) are provided in an upper layer portion of the p-type epitaxial layer112. In addition, a p-type MOSFET123is formed on the n-well (121), and a drain electrode and a source electrode located below a gate electrode of the p-type MOSFET123are provided in the n-well (121). In addition, an n-type MOSFET124is formed on the p-well (122), and a drain electrode and a source electrode located below a gate electrode of the n-type MOSFET124are provided in the p-well (122). Then, a complementary MOS (CMOS) circuit configured by such as the p-type MOSFET123made of the Si, the n-type MOSFET124made of the Si, or the Si integrated circuit101including a plurality of MOSFETs is configured. Although not shown inFIG.3A, the Si integrated circuit101may include a diode, a bipolar transistor, a capacitor, a resistance element, a wiring, or the like. InFIG.3A, since the substrate111is formed by the p-type semiconductor, the p-type substrate111is connected to a GND potential which is a negative potential so that a parasitic diode does not conduct. That is, a substrate potential of the Si integrated circuit101, which is an IC of a p-type substrate, is GND. <<Substrate in SiC Integrated Circuit>> FIG.3Bis a diagram showing a structural example of a cross section including a substrate in a SiC integrated circuit201. The SiC integrated circuit201inFIG.3Buses an n substrate. Since the SiC is generally used as a power semiconductor, the n substrate occupies most of usage, and it is generally difficult to procure the p substrate. Therefore, in the SiC integrated circuit201ofFIG.3B, a substrate211is formed by the n substrate (n-Si) which is an n-type semiconductor, and an n-type epitaxial layer212is formed thereon. Then, an n-well (221) and a p-well (222) are provided in an upper layer portion of the n-type epitaxial layer212. In addition, a p-type MOSFET223is formed on the n-well (221), and a drain electrode and a source electrode located below a gate electrode of the p-type MOSFET223are provided in the n-well (221). In addition, an n-type MOSFET224is formed on the p-well (222), and a drain electrode and a source electrode located below a gate electrode of the n-type MOSFET224are provided in the p-well (222). Then, a CMOS circuit configured by such as the p-type MOSFET223made of the SiC, the n-type MOSFET224made of the SiC, or the SiC integrated circuit201including a plurality of MOSFETs is configured. Although not shown inFIG.3B, the SiC integrated circuit201may include a diode, a bipolar transistor, a capacitor, a resistance element, a wiring, or the like. As described above, in the SiC integrated circuit201, since the substrate (the n substrate)211is formed by the n-type semiconductor, the negative potential (the Vss) serving as the GND cannot be set on the substrate (the n substrate)211. That is, it is because that when the negative potential (the Vss) is supplied to the n substrate, a parasitic diode in the SiC integrated circuit201is set to a forward direction and a current flows through. Therefore, it is necessary to apply the Vdd, which is the positive power source potential to the n-type substrate211so that the parasitic diode does not conduct. Therefore, with the negative power supply potential being set to the Vss, the Vdd potential is applied to the n-type substrate211with respect to the GND via a potential of Vdd-Vss corresponding to the drive voltage. When the operational amplifier of the analog circuit is used in the SiC integrated circuit201, a +Vdd power supply and a −Vss power supply may be used with respect to the GND with the GND interposed therebetween. In addition, the −Vss power supply may be simply connected to the GND for use. Since there are two cases, a voltage applied between the GND and the substrate211is represented as (Vdd-Vss) inFIG.3B. For example, when ±4V as a power supply voltage is applied to a SiC operational amplifier, the drive voltage is 8V. In this case, inFIG.3B, the GND potential may be set to 0V and may be set to −4V. A voltage represented by Vdd-Vss is applied from the GND to the n-type substrate211so that the two cases can also be represented. However, as compared with a case where the substrate (the p substrate)111having the Vss potential is set to the GND (FIG.3A), when the substrate (the n substrate)211having the Vdd potential is not directly connected to the GND, characteristics of the SiC integrated circuit201are easily affected by fluctuation of the drive voltage. As described above, in a configuration of the SiC integrated circuit201ofFIG.3B, when the drive voltage (Vdd-Vss) fluctuates due to an effect of the radiation irradiation, external noise such as turning on/off of other devices, IC characteristics of each element in the SiC integrated circuit201may also change. That is, the SiC integrated circuit201in which the Vdd potential is applied to the n-type substrate211is more easily affected by the radiation irradiation or the external noise as compared with the Si integrated circuit101, so that a countermeasure is necessary. <<Operation Stabilization of SiC Integrated Circuit201>> Therefore, as in the first embodiment (FIG.1) and the second embodiment (FIG.2) described above, by providing the conductive wiring22directly below the SiC integrated circuit201and forming the parasitic capacitance20between the electrode12C of the substrate of the SiC integrated circuit201and the conductive wiring22, the effect of radiation irradiation or external noise such as turning on/off of other devices is reduced. Then, the fluctuation of the drive voltage (Vdd-Vss) of the SiC integrated circuit201is prevented and the stable operation is obtained. Third Embodiment: Pressure Transmission Device Next, a pressure transmission device including the radiation resistant circuit device according to the first or second embodiment in an amplifier circuit will be described as a third embodiment. FIG.4is a diagram showing a configuration example of a pressure transmission device301according to the third embodiment of the invention. InFIG.4, the pressure transmission device301includes an amplifier circuit311, a center diaphragm312, seal diaphragms314A and314B, a pressure sensor315, and a pressure guide passage316. The pressure transmission device301transmits a pressure to the pressure sensor315by a sealed liquid (silicone oil)313inside the pressure guide passage316by a pair of two seal diaphragms314A and314B for receiving the pressure and the center diaphragm.312. The seal diaphragm314A is on a high pressure side, and the seal diaphragm314B is on a low pressure side. Then, a pressure signal is sent to the amplifier circuit311through a signal line317, and an amplified output signal is output from the pressure transmission device301. In a configuration ofFIG.4, the amplifier circuit311is an electric circuit including a semiconductor element, and a product in the related art uses a Si semiconductor element, and thus is relatively vulnerable to the radiation. Therefore, it is effective to apply a semiconductor that is resistant to the radiation such as the SiC. Further, when the SiC integrated circuit (11) adopts a structure such as the SiC semiconductor elements (1A,1B) as shown inFIGS.1and2, then, a semiconductor element or an integrated circuit that is resistant to the radiation can be obtained. <Amplifier Circuit> Next, the amplifier circuit311provided in the pressure transmission device301of the third embodiment will be described in detail with reference toFIG.5. FIG.5is a diagram showing a configuration example of the amplifier circuit311provided in the pressure transmission device301according to the third embodiment of the invention. InFIG.5, the amplifier circuit311includes printed boards21and21B, bolts444, a SiC operational amplifier (a SiC integrated circuit)411, and SiC integrated circuits412and413. The SiC integrated circuits412and413may also be SiC operational amplifiers. As shown inFIG.5, the amplifier circuit311includes a configuration in which the SiC integrated circuits (411to413) and other various elements (not shown) are provided on the printed board21. The printed board21B is also provided with circuits corresponding to the SiC semiconductor elements (411to413). As described above, it is expected that radiation resistance is greatly improved by replacing the Si semiconductor element that is relatively vulnerable to the radiation with the SiC semiconductor element. However, when the SiC integrated circuit is provided without any countermeasures, a performance of the integrated circuit itself is deteriorated by the external noise such as wraparound from a front surface of the printed board as described above. In a configuration of the amplifier circuit311including a plurality of SiC integrated circuits (411to413) shown in FIG.5, by providing pseudo capacitances (20,20B) formed by the insulating means (13,17) described in the first and second embodiments of the invention and the conductive wiring22(FIG.1) provided in the printed board, the effect of the radiation and the external noise is reduced, and stable operation and measurement of the pressure transmission device301can be provided. <Result of Gamma Ray Irradiation Test> FIG.6is a diagram showing an example of a result of a gamma ray irradiation test in the pressure transmission device301to which the radiation resistant circuit device1A is applied according to the third embodiment of the invention. InFIG.6, a vertical axis represents an output of the pressure transmission device, and a unit of the output is voltage [V]. A horizontal axis represents a cumulative radiation dose of gamma rays, and a unit of the cumulative radiation dose is [kGy]. The horizontal axis is logarithmic display. InFIG.6, a characteristic line1001indicates characteristics of a related-art product (a Si transmitter) using the Si semiconductor element equipped with the integrated circuit made of Si (the Si integrated circuit). A characteristic line1002indicates characteristics of the pressure transmission device (the SiC transmitter)301of the invention using the SiC semiconductor element (1A) having a configuration in which the SiC integrated circuit (11) having the configuration shown inFIG.1is used and the insulating material (13) is provided between the substrate electrode (12C) and the conductive wiring (22). Since the Si transmitter (the pressure transmission device) of the related-art product uses an element made of Si that is relatively vulnerable to radiation, as indicated by the characteristic line1001, a measured value drifts from a start of gamma ray irradiation, and drifts greatly near a cumulative value exceeding 1 kGy, leading to a failure. On the other hand, it is experimentally shown that, as indicated by the characteristic line1002, the pressure transmission device (the SiC transmission device)301to which a SiC element of the invention is applied almost has no fluctuation in output from irradiation to about 30 kGy, and can operate up to about 450 kGy which largely exceeds that of the Si transmitter (the pressure transmission device) of the related-art product. From a test result shown inFIG.6, it can be seen that by applying the radiation resistant circuit device1A according to the embodiment of the invention, it is possible to provide a measuring instrument having excellent radiation resistance. Effect of Third Embodiment By applying the radiation resistant circuit device1A according to the first embodiment of the invention to the pressure transmission device301according to the third embodiment, it is possible to provide the measuring instrument having excellent radiation resistance. In addition, a highly reliable system can be provided since stable measurement can be performed not only during normal measurement, but also during a severe accident when a radiation dose greatly increases. Fourth Embodiment: Nuclear Power Plant Measurement System Next, an outline of a system configuration of a nuclear power plant measurement system will be described with reference toFIGS.7A and7B. FIG.7Ais a diagram showing an outline of a system configuration example of the nuclear power plant measurement system according to a fourth embodiment of the invention. FIG.7Bis a diagram showing a configuration example of a vicinity of a drain tank and a pressure transmission device of the nuclear power plant measurement system according to the fourth embodiment of the invention in an enlarged view, together with a control device. InFIGS.7A and7B, a nuclear power plant measurement system500includes a pressure vessel511, a main steam pipe513, a high pressure turbine514, a low pressure turbine515, a generator516, a moisture separator and heater517, a drain tank518, a drainpipe519, a water supply pump520, and a water supply heater521, a condensate pump522, a condenser523, a cooling water pipe524, a water supply pipe525, a drain tank526, a control device712, and a central control device713. A region600showing a vicinity of the drain tank526inFIG.7Ais enlarged and details are shown in a region601inFIG.7B. However, inFIGS.7A and7B, for example, a member of the drain tank526is deformed and shown. As shown inFIG.7B, a configuration of a portion indicated in the region601includes the drain tank526, the water supply pipe525, the drain pipe527, and the pressure transmission device301described with reference toFIG.4. As shown inFIG.4, the pressure transmission device301shown inFIG.7Bincludes the amplifier circuit311, the center diaphragm312, the sealed liquid313, the seal diaphragms314A and314B, the pressure sensor315, and the pressure guide passage316. The above nuclear power plant measurement system500(a nuclear power generation system) shown inFIGS.7A and7Bis characterized by using the pressure transmission device301described in the third embodiment. Therefore, a detailed description of the nuclear power plant measurement system500shown inFIGS.7A and7Bis omitted, and events and operations related to the pressure transmission device301will be briefly described. In the nuclear power plant measurement system (the nuclear power generation system)500shown inFIG.7B(FIG.7A), an installation situation of the pressure transmission device301used for measuring a water level of the drain tank526is shown as an example. InFIG.7B, the pressure transmission device301includes the tubular pressure guide passage316provided at a position where a measurement fluid in a primary system of a nuclear power plant is measured, and the sealed liquid313filled in the pressure guide passage. In addition, the pressure transmission device301includes the seal diaphragms314A and314B provided in a state of closing one opening in the pressure guide passage316and receiving a pressure of the measurement fluid, the center diaphragm312, and the pressure sensor315converting the detected pressure into an electric signal. In addition, the pressure transmission device301includes the amplifier circuit311provided with the SiC semiconductor element10(FIG.1) amplifying an output signal of the pressure sensor315. In the pressure transmission device301including the above configuration, the seal diaphragms314A and314B and the center diaphragm312, which are diaphragms that are membranes displaced under an action of the pressure, receive pressures from a high pressure side and a low pressure side of the drain tank526via the sealed liquid313filled in the pressure guide passage316, so that the pressure sensor315converts the pressure into a water level and converts the water level into an electric signal. This electric signal is transmitted by a control line (a signal line)711to the central control device (a central control room)713via the control device712as the measured value. InFIG.7B, the radiation dose is high especially when the nuclear power generation system is in operation, and when the same device is used for a long period of time, a radiation deterioration is a concern. In addition, when an accident such as a pipe breakage occurs, the radiation dose around the pressure transmission device greatly increases, so that there is a risk that the pressure transmission device in the related art fails in a short time. With respect to the radiation that greatly increases, as described above, it is effective to apply the radiation resistant circuit device1A or1B to the amplifier circuit311of the pressure transmission device301of the present application. Accordingly, it is possible to provide a safe and highly reliable measurement system (the nuclear power plant measurement system500) capable of maintaining measurement error accuracy for a long period of time even in an environment with a high radiation dose such as a water supply system and a condensate system of the nuclear power generation system. Effect of Fourth Embodiment Accordingly, it is possible to provide a safe and highly reliable measurement system capable of maintaining a measurement error accuracy for a long period of time even in an environment with a high radiation dose such as the water supply system and the condensate system of the nuclear power generation system by the nuclear power plant measurement system (nuclear power generation system)500shown inFIGS.7A and7B. Other Embodiments The invention is not limited to the embodiments described above, and further includes various modifications. For example, the embodiments described above have been described in detail for easy understanding of the invention, and the invention is not necessarily limited to those including all the configurations described above. In addition, a part of the configuration of one embodiment can be replaced with a part of the configuration of another embodiment, and a part or all of the configuration of one embodiment can be added to, deleted from, and replaced with the configuration of another embodiment. Hereinafter, other embodiments or modifications will be further described. <<Electrodes12A,12B and12C>> Although the electrodes12A,12B, and12C are described as copper (Cu) electrodes inFIG.1of the first embodiment andFIG.2of the second embodiment, the electrodes are not limited to copper. For example, aluminum, silver, gold, or an alloy may be used. <<Conductive Wiring22>> InFIG.1of the first embodiment, the conductive wiring22faces the electrode12C of the substrate of the SiC integrated circuit11, or it is sufficient as long as the conductive wiring22has a portion facing the electrode12C. Therefore, a shape of the conductive wiring22does not need to be exactly the same as a shape of the electrode12C of the substrate of the SiC integrated circuit11. The shape of the conductive wiring22can be variously set depending on the wiring of the conductive wiring22on the printed board21. <<Second Metal Electrodes16A and16B>> Although inFIG.2of the second embodiment, the “solders” are illustrated as the second metal electrodes16A and16B, the second metal electrodes16A and16B may be formed of a material other than the “solder” since the second metal electrodes16A and16B are provided to separate the SiC semiconductor element10from the printed board21to form the space17. <<Analog Circuit>> Although it is described that in the SiC integrated circuit in the first embodiment, radiation countermeasures or the noise countermeasures are effective in an example of the operational amplifier serving as the analog circuit, the invention is not limited to the operational amplifier. The noise countermeasures in the present application are also effective with respect to the analog circuit such as an amplifier circuit, a comparison circuit, or an oscillation circuit. In addition, even in a logic circuit, the radiation countermeasures or the noise countermeasures in the present application are also effective with respect to a circuit having a high clock frequency or a circuit operating at a low voltage. <<Other Application Examples of Radiation Resistant Circuit Device>> In the third embodiment of the invention, the pressure transmission device is shown as an application example of the radiation resistant circuit device. However, the application example of the radiation resistant circuit device is not limited to the pressure transmission device. For example, the radiation resistant circuit device can be applied to various devices that may be used in the radiation environment such as a flow meter, various gas detectors, or a preamplifier. <<Application Example of System>> In the nuclear power plant measurement system according to the fourth embodiment of the invention, the system configuration that may be affected by the radiation in nuclear power generation is described. However, the invention is not limited to this example. It is possible and effective to use the above radiation resistant circuit device of the invention even in various systems of radiation equipment and facilities under the radiation environment such as a radiation distribution measurement system measuring the radiation. In addition, although an application example of applying the radiation resistant circuit device to devices or systems related to the nuclear power generation is described, the invention is not limited to those related to the nuclear power generation. The radiation resistant circuit device of the present application is also useful in an environment related to an aerospace (for example, an artificial satellite) as an environment in which the effect of the radiation cannot be ignored. | 36,412 |
11862632 | DETAILED DESCRIPTION OF THE EMBODIMENTS In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology is employed for sake of clarity. However, the present disclosure is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents which operate in a similar manner. FIG.1is a diagram illustrating a semiconductor device according to embodiments of the present disclosure.FIGS.2and3are exemplary diagrams in which a portion P ofFIG.1is enlarged, respectively. Referring toFIGS.1to3, the semiconductor device according to embodiments of the present disclosure may include a first gate electrode structure115and a second gate electrode structure215. The substrate100may include a first region I and a second region II. The first region I and the second region II may be regions spaced apart from each other or may be regions connected to each other. For example, the first region I and the second region II may be high-voltage operating regions. For example, the first region I and the second region II may be low-voltage operating regions. For example, one of the first region I and the second region II may be a high-voltage operating region and the other one may be a low-voltage operating region. For example, the first region I and the second region II may be PMOS formation regions. For example, either the first region I or the second region II may be PMOS formation regions. For example, one of the first region I and the second region II may be a PMOS formation region, and the other one may be an NMOS formation region. The substrate100may be a silicon substrate or an SOI (silicon-on-insulator). The substrate100may include, but is not necessarily limited to including, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide. In the following explanation, the substrate100will be explained as a silicon substrate. An element isolation layer105may be disposed in the substrate100. The element isolation layer105may define an active region. The element isolation layer105may be formed as a shallow trench isolation (STI) structure, which has excellent element isolation characteristics, occupies a small area, and thus is well suited for high integration. The element isolation layer105may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof. Although the element isolation layer105is shown as a single layer, this is only for convenience of explanation, and the embodiment is not necessarily limited thereto. A first gate stack G1may be disposed in the first region I of the substrate100. The first gate stack G1may include a first gate electrode structure115, a first spacer structure140, and a first gate mask pattern145. The first gate electrode structure115may include a first gate insulating layer110, a first metallic gate electrode120, and a first polycrystalline semiconductor electrode130. The first gate insulating layer110may be disposed on the substrate100. The first gate insulating layer110may include a first interfacial layer111and a first high-dielectric constant insulating layer112sequentially disposed on the substrate100. The first interfacial layer111may be disposed between the substrate100and the first high-dielectric constant insulating layer112. The first interfacial layer111may include, for example, but is not necessarily limited to including, a silicon oxide layer. The first interfacial layer111may vary depending on the material of the substrate100on which the first interfacial layer111is formed. The first high-dielectric constant insulating layer112may include, for example, a high-dielectric constant material having a higher dielectric constant than silicon oxide. The high-dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. The first metallic gate electrode120may be disposed on the first gate insulating layer110. The first metallic gate electrode120may include a lower face120BS and an upper face120US opposite to each other. The first metallic gate electrode120includes side walls120_S which connect the lower face120BS of the first metallic gate electrode120and the upper face120US of the first metallic gate electrode120. The lower face120BS of the first metallic gate electrode120may face the first gate insulating layer110. According to some embodiments of the present disclosure, the first high-dielectric constant insulating layer112does not extend along the side walls120_S of the first metallic gate electrode120. For example, the first high-dielectric constant insulating layer112does not cover the side walls120_S of the first metallic gate electrode120. The first metallic gate electrode120may include, for example, at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAI), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt) niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. The first polycrystalline semiconductor electrode130may be disposed on the first metallic gate electrode120. According to some embodiments of the present disclosure, the first high-dielectric constant insulating layer112does not extend along the side walls130_S of the first polycrystalline semiconductor electrode130. For example, the first high-dielectric constant insulating layer112does not cover the side walls130_S of the first polycrystalline semiconductor electrode130. The first polycrystalline semiconductor electrode130may include a polycrystalline semiconductor material, and may include, for example, but is not necessarily limited to including, polysilicon (poly-Si), polysilicon germanium (poly-SiGe), polysilicon doped with impurities, polysilicon germanium doped with impurities, and combinations thereof. In the semiconductor device according to embodiments of the present disclosure, the first polycrystalline semiconductor electrode130may include polysilicon or polysilicon doped with impurities. For example, the first polycrystalline semiconductor electrode130may be a polysilicon electrode. The first gate mask pattern145may be disposed on the first gate electrode structure115. The first gate mask pattern145may be disposed on the first polycrystalline semiconductor electrode130. The first gate mask pattern145may include an insulating material, and may include, for example, but is not necessarily limited to including, silicon oxide, silicon oxynitride, silicon nitride, or the like. The first spacer structure140may be disposed on the side walls of the first gate electrode structure115. The first gate mask pattern145may be disposed between the first spacer structures140. The first spacer structure140covers at least a part of the side walls of the first gate mask pattern145. The first spacer structure140may include a first_1 spacer141, a first_2 spacer142, and a first_3 spacer143sequentially disposed on the side walls of the first gate electrode structure115. The first_1 spacer141may be disposed between the first gate electrode structure115and the first_2 spacer142. The first_1 spacer141may be disposed on the side walls130_S of the first polycrystalline semiconductor electrode130. The first_1 spacer141extends along the entire side walls130_S of the first polycrystalline semiconductor electrode130. The first_1 spacer141may be in contact with the first polycrystalline semiconductor electrode130. The first_1 spacer141may extend to the upper face120US of the first metallic gate electrode120. The first_1 spacer141may be disposed on the upper face120US of the first metallic gate electrode120. The first_1 spacer141may be in contact with the upper face120US of the first metallic gate electrode120. According to one example, the first_1 spacer141is not disposed on the side walls120_S of the first metallic gate electrode120and the first_1 spacer141does not cover the side walls120_S of the first metallic gate electrode120. A boundary between the first_1 spacer141and the first_2 spacer142may be aligned with the side walls120_S of the first metallic gate electrode120. For example, the first_1 spacer141may include an inner side wall facing the side walls130_S of the first polycrystalline semiconductor electrode130, and an outer side wall facing the first_2 spacer142. The outer side wall of the first_1 spacer141may be aligned with the side walls120_S of the first metallic gate electrode120. For example, on the upper face120US of the first metallic gate electrode120, a width of the first metallic gate electrode120may be the same as widths of the first polycrystalline semiconductor electrode130and the first_1 spacer141. The first_2 spacer142may be disposed on the first_1 spacer141. The first_2 spacer142may be disposed between the first_1 spacer141and the first_3 spacer143. The first_2 spacer142may extend along the side walls130_S of the first polycrystalline semiconductor electrode130and the side walls120_S of the first metallic gate electrode120. The first_2 spacer142may cover the entire side walls of the first gate electrode structure115. The first_2 spacer142may extend to the upper face of the substrate100. The first_3 spacer143may be disposed on the first_2 spacer142. The first_3 spacer143may cover the entire side walls of the first gate electrode structure115. The first_1 spacer141, the first_2 spacer142and the first_3 spacer143may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN) and silicon oxycarbide (SiOC). A first source/drain region150may be disposed on opposite sides of the first gate electrode structure115. The first source/drain region150may be formed inside the substrate100. The first source/drain region150may include a first low-concentration impurity region151and a first high-concentration impurity region152. The concentration of the dopant of the first high-concentration impurity region152is higher than the concentration of the dopant of the first low-concentration impurity region151. In the semiconductor device according to embodiments of the present disclosure, a depth of the first high-concentration impurity region152may be deeper than a depth of the first low-concentration impurity region151with respect to the upper face of the substrate100. A second gate stack G2may be disposed in the second region II of the substrate100. The second gate stack G2may include a second gate electrode structure215, a second spacer structure240, and a second gate mask pattern245. The second gate electrode structure215may include a second gate insulating layer210, a second metallic gate electrode220, and a second polycrystalline semiconductor electrode230. The second gate insulating layer210may be disposed on the substrate100. The second gate insulating layer210may include a second interfacial layer211and a second high-dielectric constant insulating layer212sequentially disposed on the substrate100. The second interfacial layer211may be disposed between the substrate100and the second high-dielectric constant insulating layer212. The second interfacial layer211may include, for example, but is not necessarily limited to including, a silicon oxide layer. The second interfacial layer211may vary depending on the material of the substrate100on which the second interfacial layer211is formed. The second high-dielectric constant insulating layer212may include, for example, a high-dielectric constant material having a higher dielectric constant than silicon oxide. The second high-dielectric constant insulating layer212may include the same material as the first high-dielectric constant insulating layer112. The second metallic gate electrode220may be disposed on the second gate insulating layer210. The second metallic gate electrode220may include a lower face220BS and an upper face220US opposite to each other. The second metallic gate electrode220includes side walls220_S which connect the lower face220BS of the second metallic gate electrode220and the upper face220US of the second metallic gate electrode220. The lower face220BS of the second metallic gate electrode220may face the second gate insulating layer210. According to embodiment of the present disclosure, the second high-dielectric constant insulating layer212does not extend along the side walls220_S of the second metallic gate electrode220. For example, the second high-dielectric constant insulating layer212does not cover the side walls220_S of the second metallic gate electrode220. For example, the second metallic gate electrode220may include the same material as the first metallic gate electrode120. The second polycrystalline semiconductor electrode230may be disposed on the second metallic gate electrode220. The second polycrystalline semiconductor electrode230includes a lower part230BP of the second polycrystalline semiconductor electrode230, and an upper part230UP of the second polycrystalline semiconductor electrode230. The upper part230UP of the second polycrystalline semiconductor electrode230is disposed on the lower part230BP of the second polycrystalline semiconductor electrode230. The lower part230BP of the second polycrystalline semiconductor electrode230and the upper part230UP of the second polycrystalline semiconductor electrode230may be divided by a second_1 spacer241to be explained below. According to some embodiments of the present disclosure, the second high-dielectric constant insulating layer212does not extend along the side walls230BP_S and230UP_S of the second polycrystalline semiconductor electrode230. For example, the second high-dielectric constant insulating layer212does not cover the side walls230BP_S and230UP_S of the second polycrystalline semiconductor electrode230. A lower side wall230BP_S of the second polycrystalline semiconductor electrode230may be aligned with the side wall220_S of the second metallic gate electrode220. For example, the width of the upper face220US of the second metallic gate electrode220may be the same as the width of the lower face of the second polycrystalline semiconductor electrode230facing the upper face220US of the second metallic gate electrode220. The second polycrystalline semiconductor electrode230includes a polycrystalline semiconductor material, and may include, for example, but is not necessarily limited to, polysilicon (poly-Si), polysilicon germanium (poly-SiGe), polysilicon doped with impurities, polysilicon germanium doped with impurities, and combinations thereof. In the semiconductor device according to embodiments of the present disclosure, the second polycrystalline semiconductor electrode230may include polysilicon or polysilicon doped with impurities. For example, the second polycrystalline semiconductor electrode230may be a polysilicon electrode. The second gate mask pattern245may be disposed on the second gate electrode structure215. The second gate mask pattern245may be disposed on the second polycrystalline semiconductor electrode230. The second gate mask pattern245may include the same material as the first gate mask pattern145. The second spacer structure240may be disposed on the side walls of the second gate electrode structure215. The second gate mask pattern245may be disposed between the second spacer structures240. The second spacer structure240covers at least a part of the side walls of the second gate mask pattern245. The second spacer structure240may include a second_1 spacer241, a second_2 spacer242, and a second_3 spacer243, which are sequentially disposed on the side walls of the second gate electrode structure215. The second spacer structure240may have the same stacked layer structure as the first spacer structure140. The second_1 spacer241may correspond to the first_1 spacer141. The second_2 spacer242may correspond to the first_2 spacer142. The second_3 spacer243may correspond to the first_3 spacer143. The second_1 spacer241may be disposed between the second gate electrode structure215and the second_2 spacer242. The second_1 spacer241may be disposed on the side walls of the second polycrystalline semiconductor electrode230. The second_1 spacer241extends along a part of the side walls of the second polycrystalline semiconductor electrode230. The second_1 spacer241is disposed on the upper side wall230UP_S of the second polycrystalline semiconductor electrode230. According to some embodiments of the present disclosure, the second_1 spacer241is not disposed on the lower side wall230BP_S of the second polycrystalline semiconductor electrode230. According to some embodiments of the present disclosure, the second_1 spacer241covers the upper side wall230UP_S of the second polycrystalline semiconductor electrode230, but does not cover the lower side wall230BP_S of the second polycrystalline semiconductor electrode230. The second_1 spacer241may be in contact with the second polycrystalline semiconductor electrode230. The second_1 spacer241is in contact with the upper side wall230UP_S of the second polycrystalline semiconductor electrode230. According to some embodiments of the present disclosure, the second_1 spacer241is not in contact with the lower side wall230BP_S of the second polycrystalline semiconductor electrode230. The second_1 spacer241may be disposed on the upper face220US of the second metallic gate electrode220. According to some embodiments of the present disclosure, the second_1 spacer241does not extend to the upper face220US of the second metallic gate electrode220. According to some embodiments of the present disclosure, the second_1 spacer241is not in contact with the upper face220US of the second metallic gate electrode220. According to some embodiments of the present disclosure, the second_1 spacer241is not disposed on the side walls220_S of the second metallic gate electrode220. According to some embodiments of the present disclosure, the second_1 spacer241does not cover the side walls220_S of the second metallic gate electrode220. The second_2 spacer242may be disposed on the second_1 spacer241. The second_2 spacer242may be disposed between the second_1 spacer241and the second_3 spacer243. The second_2 spacer242may extend along the upper side wall230US_S of the second polycrystalline semiconductor electrode230, the lower side wall230BP_S of the second polycrystalline semiconductor electrode230, and the side wall220_S of the second metallic gate electrode220. The second_2 spacer242may cover the entire side walls of the second gate electrode structure215. The second_2 spacer242may extend to the upper face of the substrate100. The second_3 spacer243may be disposed on the second_2 spacer242. The second_3 spacer243may cover the entire side walls of the second gate electrode structure215. The second_1 spacer241includes the same material as the first_1 spacer141. The second_2 spacer242includes the same material as the first_2 spacer142. The second_3 spacer243may include the same material as the first_3 spacer143. A second source/drain region250may be disposed on both sides of the second gate electrode structure215. The second source/drain region250may be formed inside the substrate100. The second source/drain region250may include a second low-concentration impurity region251and a second high-concentration impurity region252. The concentration of dopant of the second high-concentration impurity region252is higher than the concentration of dopant of the second low-concentration impurity region251. In the semiconductor device according to embodiments of the present disclosure, the depth of the second high-concentration impurity region252may be deeper than the depth of the second low-concentration impurity region251with respect to the upper face of the substrate100. A height or a thickness (H21+H22+H23) of the second gate electrode structure215is greater than a height or a thickness (H11+H12+H13) of the first gate electrode structure115. In the following explanation, the height of the first gate electrode structure115and the height of the second gate electrode structure215will be explained. For example, a height H11of the first gate insulating layer110may be the same as a height H21of the second gate insulating layer210. A height H12of the first metallic gate electrode120may be the same as a height H22of the second metallic gate electrode220. A height H13of the first polycrystalline semiconductor electrode130is smaller than a height H23of the second polycrystalline semiconductor electrode230. For example, a difference between the height of the first gate electrode structure115and the height of the second gate electrode structure215may be a difference between the height H13of the first polycrystalline semiconductor electrode130and the height H23of the second polycrystalline semiconductor electrode230. For example, the height H11of the first gate insulating layer110may be different from the height H21of the second gate insulating layer210. The difference between the height of the first gate electrode structure115and the height of the second gate electrode structure215may be equal to the sum of the difference between the height H13of the first polycrystalline semiconductor electrode130and the height H23of the second polycrystalline semiconductor electrode230, and the difference between the height H11of the first gate insulating layer110and the height H21of the second gate insulating layer210. However, the difference between the height H13of the first polycrystalline semiconductor electrode130and the height H23of the second polycrystalline semiconductor electrode230may be much greater than the difference between the height H11of the first gate insulating layer110and the height H21of the second gate insulating layer210. Therefore, the difference between the height of the first gate electrode structure115and the height of the second gate electrode structure215may be substantially the same as the difference between the height H13of the first polycrystalline semiconductor electrode130and the height H23of the second polycrystalline semiconductor electrode230. For example, the height H23of the second polycrystalline semiconductor electrode230may be equal to the sum of a height H23aof the upper part230UP of the second polycrystalline semiconductor electrode230and a height H23bof the lower part230BP of the second polycrystalline semiconductor electrode230. The height H23bof the lower part230BP of the second polycrystalline semiconductor electrode230may be a height from the upper face220US of the second metallic gate electrode220to the lowermost part241LMP of the second_1 spacer. For example, the height H12from the upper face of the first gate insulating layer110to the lowermost part of the first_1 spacer141is smaller than a height (H22+H23b) from the upper face of the second gate insulating layer210to the lowermost part241LMP of the second_1 spacer. In the semiconductor device according to embodiments of the present disclosure, the height H23aof the upper part230UP of the second polycrystalline semiconductor electrode230may be the same as the height1113of the first polycrystalline semiconductor electrode130. The height H13of the first polycrystalline semiconductor electrode130may be a height from the lowermost part of the first_1 spacer141to the upper face of the first polycrystalline semiconductor electrode130. The height H23aof the upper part230UP of the second polycrystalline semiconductor electrode230may be a height from the lowermost part241LMP of the second_1 spacer to the upper face of the second polycrystalline semiconductor electrode230. In the semiconductor device according to embodiments of the present disclosure, a thickness t11of the first_) spacer141on the side walls130_S of the first polycrystalline semiconductor electrode130may be the same as a thickness t12of the second_1 spacer241on the upper side wall230UP_S of the second polycrystalline semiconductor electrode230. In the semiconductor device according to embodiments of the present disclosure, at the lowermost part241LMP of the second_1 spacer241, the width W11of the upper part230UP of the second polycrystalline semiconductor electrode230may be different from the width W12of the lower part230BP of the second polycrystalline semiconductor. For example, the width W12of the lower part230BP of the second polycrystalline semiconductor electrode230may be greater than the width W11of the upper part230UP of the second polycrystalline semiconductor electrode230. InFIG.2, the lowermost part241LMP of the second_1 spacer241may entirely extend over the lower part230BP of the second polycrystalline semiconductor electrode230. The boundary between the second_1 spacer241and the second_2 spacer242may be aligned with the lower side wall230BP_S of the second polycrystalline semiconductor electrode230. InFIG.3, a part of the lowermost part241LMP of the second_1 spacer may extend over the lower part230BP of the second polycrystalline semiconductor electrode230. According to some embodiments of the present disclosure, the boundary between the second_1 spacer241and the second_2 spacer242is not aligned with the lower side wall230BP_S of the second polycrystalline semiconductor electrode230. The semiconductor device according to embodiments of the present disclosure may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the first high-dielectric constant insulating layer112and the second high-dielectric constant insulating layer212may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties. The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance becomes decrease compared to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than an absolute value of each individual capacitance, while having a positive value. When the ferroelectric material layer having the negative capacitance and the paraelectric material layer having the positive capacitance are connected in series, the entire capacitance values of the ferroelectric material layer and the paraelectric material layer connected in series may increase. Taking advantage of the increased overall capacitance value, a transistor including the ferroelectric material layer may have a subthreshold swing (SS) of less than 60 mV/decade at room temperature. The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide and lead zirconium titanium oxide. Here, for example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). For example, the hafnium zirconium oxide may also be a compound of hafnium (H), zirconium (Zr) and oxygen (O). The ferroelectric material layer may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the ferroelectric material included in the ferroelectric material layer. When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material layer may contain 3 to 8 at % (atomic %) aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material layer may contain 2 to 10 at % silicon. When the dopant is yttrium (Y), the ferroelectric material layer may contain 2 to 10 at % yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may contain 1 to 7 at % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may contain 50 to 80 at % zirconium. The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and a metal oxide having a high-dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, but is not necessarily limited to, at least one of hafnium oxide, zirconium oxide and aluminum oxide. The ferroelectric material layer and the paraelectric material layer may include the same material. Although the ferroelectric material layer has ferroelectric properties, the paraelectric material layer might not have the ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer. The ferroelectric material layer may have a thickness with ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, but is not necessarily limited to, 0.5 to 10 nm. Since each ferroelectric material may have a different critical thickness that exhibits the ferroelectric properties, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material. For example, the gate insulating layer may include one ferroelectric material layer. For example, the gate insulating layer may include a plurality of ferroelectric material layers separated from each other. The gate insulating layer may have a stacked layer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked. FIG.4is a diagram illustrating the semiconductor device according to embodiments of the present disclosure.FIG.5is an enlarged view of a portion P ofFIG.4. For convenience of explanation, differences from contents explained usingFIGS.1to3will be mainly described. Referring toFIGS.4and5, in the semiconductor device according to embodiments of the present disclosure, at the lowermost part241LMP of the second_1 spacer, the width W11of the upper part230UP of the second polycrystalline semiconductor electrode230may be the same as the width W12of the lower part230BP of the second polycrystalline semiconductor electrode230. According to some embodiments of the present disclosure, the lowermost part241LMP of the second_1 spacer241does not entirely extend over the lower part230BP of the second polycrystalline semiconductor electrode230. The lowermost part241LMP of the second_1 spacer may entirely extend over the second_2 spacer242. The lower side wall230BP_S of the second polycrystalline semiconductor electrode230may be aligned with the upper side wall230UP_S of the second polycrystalline semiconductor electrode230. FIG.6is a diagram illustrating the semiconductor device according to embodiments of the present disclosure.FIG.7is an enlarged view of a portion P ofFIG.6. For convenience of explanation, differences from contents explained usingFIGS.1to3will be mainly described. Referring toFIGS.6and7, in the semiconductor device according to embodiments of the present disclosure, at the lowermost part241LMP of the second_1 spacer241, the width W11of the upper part230UP of the second polycrystalline semiconductor electrode230may be greater than the width W12of the lower part230BP of the second polycrystalline semiconductor electrode230. A part of the upper part230UP of the second polycrystalline semiconductor electrode230may extend over the second_2 spacer242. According to some embodiments of the present disclosure, the lower side wall230BP_S of the second polycrystalline semiconductor electrode230is not aligned with the upper side wall230UP_S of the second polycrystalline semiconductor electrode230. FIG.8is a diagram illustrating the semiconductor device according to embodiments of the present disclosure.FIG.9is a diagram illustrating the semiconductor device according to embodiments of the present disclosure. For convenience of explanation, differences from contents explained usingFIGS.1to3will be mainly described. Referring toFIG.8, in the semiconductor device according to embodiments of the present disclosure, the width of the lower face of the second polycrystalline semiconductor electrode230facing the upper face220US of the second metallic gate electrode220may differ from the width of the lower part230BP of the second polycrystalline semiconductor electrode230at the lowermost part of the second_1 spacer241. For example, as it goes away from the upper face220US of the second metallic gate electrode220, the width of the lower part230BP of the second polycrystalline semiconductor electrode230may increase. The width of the upper face220US of the second metallic gate electrode220may be the same as the width of the lower face of the second polycrystalline semiconductor electrode230facing the upper face220US of the second metallic gate electrode220. Referring toFIG.9, in the semiconductor device according to embodiments of the present disclosure, a height H23aof the upper part230UP of the second polycrystalline semiconductor electrode230is greater than the height H13of the first polycrystalline semiconductor electrode130. The height H13from the lowermost part of the first_1 spacer141to the upper face of the first polycrystalline semiconductor electrode130is smaller than the height H23afrom the lowermost part of the second_1 spacer241to the upper face of the second polycrystalline semiconductor electrode230. FIG.10is a diagram illustrating the semiconductor device according to embodiments of the present disclosure. For convenience of explanation, differences from contents explained usingFIG.9will be mainly described. Referring toFIG.10, in the semiconductor device according to embodiments of the present disclosure, the thickness t11of the first_1 spacer141on the side walls130_S of the first polycrystalline semiconductor electrode130is greater than the thickness t12of the second_1 spacer241on the upper side wall230UP_S of the second polycrystalline semiconductor electrode230. At the boundary between the first polycrystalline semiconductor electrode130and the first gate mask pattern145, the width of the first polycrystalline semiconductor electrode130may be smaller than the width of the first gate mask pattern145. FIG.11is a diagram illustrating the semiconductor device according to embodiments of the present disclosure.FIG.12is a diagram illustrating the semiconductor device according to embodiments of the present disclosure.FIG.13is a diagram illustrating the semiconductor device according to embodiments of the present disclosure. For convenience of explanation, differences from contents explained usingFIGS.1to3will be mainly described. Referring toFIG.11, the semiconductor devices according to embodiments of the present disclosure may further include a first semiconductor channel layer115CH disposed in the first region I and a second semiconductor channel layer215CH disposed in the second region II. The first semiconductor channel layer115CH may be disposed below the first gate insulating layer110. The second semiconductor channel layer215CH may be disposed below the second gate insulating layer210. The first semiconductor channel layer115CH and the second semiconductor channel layer215CH may include, for example, a material having a lattice constant greater than the substrate100. For example, when the substrate100is a silicon substrate, the first semiconductor channel layer115CH and the second semiconductor channel layer215CH may each include a silicon germanium layer. For example, the first region I and the second region II may be regions in which the PMOS is formed. Unlike the shown case, the first semiconductor channel layer115CH and the second semiconductor channel layer215CH may extend to the element isolation layer105. A part of the first source/drain region150may be formed inside the first semiconductor channel layer115CH. The second source/drain region250may be formed inside the second semiconductor channel layer215CH. Unlike the shown case, for example, the first semiconductor channel layer115CH may be disposed in the first region I, and the second semiconductor channel layer215CH might not be disposed in the second region II. At this time, the second region II may be a region in which the PMOS is formed or a region in which the NMOS is formed. Unlike the shown case, for example, the second semiconductor channel layer215CH may be disposed in the second region II, and the first semiconductor channel layer115CH might not be formed in the first region I. At this time, the first region I may be a region in which the PMOS is formed or a region in which the NMOS is formed. Referring toFIG.12, in the semiconductor device according to embodiments of the present disclosure, the depth of the first high-concentration impurity region152may be shallower than the depth of the first low-concentration impurity region151with respect to the upper face of the substrate100. For example, the first high-concentration impurity region152may be formed in the first low-concentration impurity region151. The depth of the second high-concentration impurity region252may be shallower than the depth of the second low-concentration impurity region251with respect to the upper face of the substrate100. For example, the second high-concentration impurity region252may be formed in the second low-concentration impurity region251. Unlike the shown case, for example, in the second source/drain region250, asFIG.1, the depth of the second high-concentration impurity region252may be deeper than the depth of the second low-concentration impurity region251. For example, in the first source/drain region150, as inFIG.1, the depth of the first high-concentration impurity region152may be deeper than the depth of the first low-concentration impurity region151. Referring toFIG.13, in the semiconductor device according to embodiments of the present disclosure, the first source/drain region150may include a first epitaxial semiconductor pattern152P, and the second source/drain region250may include a second epitaxial semiconductor pattern252P. The first epitaxial semiconductor pattern152P and the second epitaxial semiconductor pattern252P may be formed to fill a recess formed in the substrate100, respectively. When the first region I and the second region are NMOS formation regions, each of the first epitaxial semiconductor pattern152P and the second epitaxial semiconductor pattern252P may be the same materials as the substrate100or a tensile stress material. For example, when the substrate100is silicon, each of the first epitaxial semiconductor pattern152P and the second epitaxial semiconductor pattern252P may be silicon or a material (for example, silicon carbide) having a lattice constant smaller than silicon. When the first region I and the second region are PMOS formation regions, each of the first epitaxial semiconductor pattern152P and the second epitaxial semiconductor pattern252P may include the substrate100and a compressive stress material. For example, the compressive stress material may be a material having a lattice constant greater than Si, for example, SiGe. When one of the first region I and the second region II is a PMOS formation region, and the other one is an NMOS formation region, the first epitaxial semiconductor pattern152P and the second epitaxial semiconductor pattern252P may include materials different from each other. Unlike the shown case, the epitaxial semiconductor pattern described above might not be formed in one of the first region I or the second region II. FIGS.14to20are diagrams illustrating intermediate steps in a method of fabricating a semiconductor device according to embodiments of the present disclosure. Referring toFIG.14, a first pre gate insulating layer110pand a first pre metallic gate electrode120pmay be sequentially formed on the substrate100of the first region I. A second pre gate insulating layer210pand a second pre metallic gate electrode220pmay be sequentially formed on the substrate100of the second region II. The first pre gate insulating layer110pmay include a first pre interfacial layer111pand a first pre high-dielectric constant insulating layer112p. The second pre gate insulating layer210pmay include a second pre interfacial layer211pand a second pre high-dielectric constant insulating layer212p. Although the first pre interfacial layer111pand the second pre interfacial layer211pare shown as not being formed on the upper face of the element isolation layer105, the present disclosure is not necessarily limited thereto. Depending on the method of forming the first pre interfacial layer111pand the second pre interfacial layer211p, the first pre interfacial layer111pand/or the second pre interfacial layer211pmay extend along the upper face of the element isolation layer105p. The first pre high-dielectric constant insulating layer112pand the second pre high-dielectric constant insulating layer212pmay be formed at the same level. Here, the term “same level” means that the insulating layers are formed by the same fabricating process. A pre high-dielectric constant insulating layer including the first pre high-dielectric constant insulating layer112pand the second pre high-dielectric constant insulating layer212pis formed in the first region I and the second region II of the substrate100. The first pre high-dielectric constant insulating layer112pand the second pre high-dielectric constant insulating layer212pmay include the same material. The thickness of the first pre high-dielectric constant insulating layer112pon the first pre interfacial layer111pmay be equal to the thickness of the second pre high-dielectric constant insulating layer212pon the second pre interfacial layer211p. The first pre metallic gate electrode120pmay be formed at the same level as the second pre metallic gate electrode220p. A pre metallic gate electrode including the first pre metallic gate electrode120pand the second pre metallic gate electrode220pare formed in the first region I and the second region II of the substrate100. Subsequently, a first pre polycrystalline semiconductor layer130pmay be formed on the first pre metallic gate electrode120p. The first pre polycrystalline semiconductor layer130pmay have a first height H13. A second pre polycrystalline semiconductor layer230pmay be formed on the second pre metallic gate electrode220p. The second pre polycrystalline semiconductor layer230pmay have a second height1123. For example, the first pre polycrystalline semiconductor layer130pmay be formed at the same time as the second pre polycrystalline semiconductor layer230p. For example, when there is a structure having a step on the substrate100, pre polycrystalline semiconductor layers having different thicknesses from each other may be formed around the step. For example, the first pre polycrystalline semiconductor layer130pmay be formed through a process different from that of the second pre polycrystalline semiconductor layer230p. Subsequently, a first pre gate mask145pmay be formed on the first pre polycrystalline semiconductor layer130p. A second pre gate mask245pmay be formed on the second pre polycrystalline semiconductor electrode230p. A mask pattern MASK may be formed on the first pre gate mask145pand the second pre gate mask245p. Referring toFIG.15, by patterning the first pre gate mask145pand the first pre polycrystalline semiconductor layer130p, using the mask pattern MASK, a first gate mask pattern145and a first polycrystalline semiconductor electrode130may be formed in the first region I. The first pre metallic gate electrode120pis exposed, while the first polycrystalline semiconductor electrode130is formed. When a part of the second pre gate mask245pand the second pre polycrystalline semiconductor electrode230pis patterned using the mask pattern MASK, the second gate mask pattern245and the upper part230UP of the second polycrystalline semiconductor electrode230may be formed in the second region II. After the upper part230UP of the second polycrystalline semiconductor electrode230is formed, a rest230p_R of the second polycrystalline semiconductor layer remains on the second pre metallic gate electrode220p. Some of the first pre polycrystalline semiconductor layer130pand the second pre polycrystalline semiconductor electrode230pare simultaneously patterned, and the first polycrystalline semiconductor electrode130and the upper part230UP of the second polycrystalline semiconductor electrode230may be formed at the same time. Subsequently, the mask pattern MASK may be removed. Referring toFIG.16, a first_1 spacer141may be formed on the side walls of the first polycrystalline semiconductor electrode130. A second_1 spacer241may be formed on the side walls of the upper part230UP of the second polycrystalline semiconductor electrode230. For example, the first_1 spacer141and the second_1 spacer241may be formed at the same time. While the second_1 spacer241is formed, the first_1 spacer141is formed. The first_1 spacer141may be in contact with the first pre metallic gate electrode120p. Referring toFIG.17, a rest230p_R of the second polycrystalline semiconductor layer may be patterned, using the upper part230UP and the second_1 spacer241of the second polycrystalline semiconductor electrode230as an etching mask. The lower part230BP of the second polycrystalline semiconductor electrode230is formed through patterning of the rest230p_R of the second polycrystalline semiconductor layer. Accordingly, the second polycrystalline semiconductor electrode230is formed on the second pre metallic gate electrode220p. Referring toFIG.18, the first pre metallic gate electrode120pand the first pre gate insulating layer110pmay be patterned, using the first gate mask pattern145, the first_1 spacer141and the first polycrystalline semiconductor electrode130. Accordingly, the first metallic gate electrode120and the first gate insulating layer110are formed. The second pre metallic gate electrode220pand the second pre gate insulating layer210pmay be patterned, using the second gate mask pattern245, the second_1 spacer241and the second polycrystalline semiconductor electrode230. Accordingly, the second metallic gate electrode220and the second gate insulating layer210are formed. The first gate electrode structure115is formed in the first region I, and the second gate electrode structure215is formed in the second region II. Referring toFIG.19, the first_2 spacer142is formed on the side walls of the first gate electrode structure115. The second_2 spacer242is formed on the side walls of the second gate electrode structure215. The first_2 spacer142is disposed on the first_1 spacer141, and the second_2 spacer242is disposed on the second_1 spacer241. After forming the first_2 spacer142and the second_2 spacer242, the first low-concentration impurity region151and the second low-concentration impurity region251may be formed in the substrate100. Referring toFIG.20, by forming the first_3 spacer143on the first_2 spacer142, the first spacer structure140may be formed. By forming the second_3 spacer243on the second_2 spacer242, the second spacer structure240may be formed. Subsequently, the first high-concentration impurity region152and the second high-concentration impurity region252may be formed in the substrate100. In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the described embodiments without substantially departing from the principles of the present disclosure. | 49,785 |
11862633 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some embodiments, a nanosheet field effect transistor (NSFET) may comprise nanosheet channel structures that extend in parallel from a first source/drain region to a second source/drain region. The nanosheet channel structures may be continuously surrounded by gate electrode layers to form a gate electrode structure. Thus, the nanosheet channel structures may be turned “ON” to allow mobile charge carriers to travel from the first source/drain region to the second source/drain region by applying a voltage bias across the gate electrode structure that exceeds a threshold voltage of the NSFET. The threshold voltage of the NSFET depends on the work function of the gate electrode structure, which can be controlled by, for example, the material of the gate electrode layers, doping concentration of the gate electrode layers, dipole engineering of the gate dielectric layers, and/or the length of the gate electrode structure. However, in an NSFET device, the vertical spacing between nanosheet channel structures may limit the effectiveness of doping of the gate dielectric layers, and dipole engineering may not provide a large enough change in work function. Further, the vertical spacing between nanosheet channel structures and process limitations may reduce the number of gate electrode layers in the gate electrode structure. Thus, in some embodiments, the vertical spacing between nanosheet channel structures is increased to accommodate more gate electrode layers in the gate electrode structure to achieve desired work function of the gate electrode structure. However, increasing the vertical spacing between nanosheet channel structures negatively increases the overall height of the NSFET device. For example, in a static random access memory (SRAM) device, one SRAM cell comprises at least 4 transistors, and thus, an increase in spacing of each transistor may significantly increase each SRAM cell size, thereby impacting the storage per space capability of the SRAM device. Various embodiments of the present disclosure are directed towards a method of forming a first NSFET having a first gate electrode structure beside a second NSFET having a second gate electrode structure that is beside a third NSFET having a third gate electrode structure without sacrificing device density. In some embodiments, the first gate electrode structure may comprise a first gate electrode layer continuously surrounding first nanosheet channel structures of the first NSFET; the second gate electrode structure may comprise a second gate electrode layer continuously surrounding second nanosheet channel structures of the second NSFET; and the third gate electrode structure may comprise a third gate electrode layer continuously surrounding third nanosheet channel structures of the third NSFET, wherein the first, second, and third gate electrode layers are different from one another. In some embodiments to form the at least first, second, and third NSFETs, a first dummy masking structure may be formed directly between the first nanosheet channel structures of the first NSFET; a second dummy masking structure may be formed directly between the second nanosheet channel structures of the second NSFET; and a third dummy masking structure may be formed directly between the third nanosheet channel structures of the third NSFET. In some embodiments, the first dummy masking structure may be removed, and the first gate electrode layer may be formed over the first, second, and third nanosheet channel structures. Then, the first gate electrode layer may be selectively removed from the second and third nanosheet channel structures. The second and third dummy masking structures prevent the formation of the first gate electrode layer vertically between the second nanosheet channel structure and vertically between the third nanosheet channel structures, thereby reducing the maximum dimensions of the first gate electrode layer to be removed from the second and third nanosheet channel structures to prevent inadvertent over-etching of the first gate electrode layer on the first nanosheet channel structures. The method may continue to form a second gate electrode layer on the second nanosheet channel structures and to form a third gate electrode layer on the third nanosheet channel structures, wherein the second and/or third dummy masking structures aid in preventing over-etching of the second and/or third gate electrode layers. Thus, because of the first, second, and third dummy masking structures, the first NSFET may be formed laterally beside the second NSFET, and the third NSFET may be formed laterally beside the second NSFET without sacrificing device density or device reliability. FIG.1illustrates a perspective view100of some embodiments of a second nanosheet field effect transistor (NSFET) arranged between a first NSFET and a third NSFET, wherein the first, second, and third NSFETs have different threshold voltages. The perspective view100illustrates a first NSFET102, a second NSFET104, and a third NSFET106arranged on a substrate108. It will be appreciated that in some instances, the NSFETs (e.g.,102,104,106) may be also known as, for example, a gate-all-around FET, a gate surrounding transistor, a multi-bridge channel (MBC) transistor, a nanowire FET, or the like. In some embodiments, the substrate108comprises a first fin structure112, a second fin structure114, and a third fin structure116that protrude from the substrate108through a lower isolation structure110a. In some embodiments, the second fin structure114is arranged between the first fin structure112and the third fin structure116, and the first, second, and third fin structures112,114,116are spaced apart from one another by the lower isolation structure110a. In some embodiments, the first NSFET102comprises a first source/drain region118and a second source/drain region120that are embedded in an upper isolation structure110band that are arranged over the first fin structure112. The second source/drain region120is illustrated with a hashed line because in some embodiments, the second source/drain region120is not visible from the perspective view100ofFIG.1. A first gate electrode structure130is arranged directly over the first fin structure112, extends from the first source/drain region118to the second source/drain region120, and surrounds first nanosheet channel structures (see,202ofFIG.2) that also extend from the first source/drain region118to the second source/drain region120. In some embodiments, the second NSFET104comprises a third source/drain region122and a fourth source/drain region124that are embedded in the upper isolation structure110band that are arranged over the second fin structure114. The fourth source/drain region124is illustrated with a hashed line because in some embodiments, the fourth source/drain region124is not visible from the perspective view100ofFIG.1. A second gate electrode structure132is arranged directly over the second fin structure114, extends from the third source/drain region122to the fourth source/drain region124, and surrounds second nanosheet channel structures (see,204ofFIG.2) that also extend from the third source/drain region122to the fourth source/drain region124. In some embodiments, the third NSFET106comprises a fifth source/drain region126and a sixth source/drain region128that are embedded in the upper isolation structure110band that are arranged over the third fin structure116. The sixth source/drain region128is illustrated with a hashed line because in some embodiments, the sixth source/drain region128is not visible from the perspective view100ofFIG.1. A third gate electrode structure134is arranged directly over the third fin structure116, extends from the fifth source/drain region126to the sixth source/drain region128, and surrounds third nanosheet channel structures (see,206ofFIG.2) that also extend from the fifth source/drain region126to the sixth source/drain region128. Further, in some embodiments, a filler layer138may be arranged over the lower isolation structure110aand surround the first, second, and third gate electrode structures130,132,134. It will be appreciated that the filler layer138is illustrated as somewhat transparent such that the first, second, and third gate electrode structures130,132,134may be visible inFIG.1, and thus, in some embodiments, the filler layer138is not transparent or is not somewhat transparent. In some embodiments, the substrate108, the first fin structure112, the second fin structure114, the third fin structure116, the first nanosheet channel structures (see,202ofFIG.2), the second nanosheet channel structures (see,204ofFIG.2), the third nanosheet channel structures (see,206ofFIG.2) comprise an intrinsic semiconductor material, such as, for example, silicon, germanium, or the like. In some embodiments, the first and second source/drain regions118,120may have a first doping type and a first doping concentration; the third and fourth source/drain regions122,124may have a second doping type and a second doping concentration; and the fifth and sixth source/drain regions126,128may have a third doping type and a third doping concentration. In some embodiments, the first, second, and/or third doping types are different from one another, whereas in other embodiments, the first, second, and/or third doping types may be the same as one another. Similarly, in some embodiments, the first, second, and/or third doping concentrations may be different from one another, whereas in other embodiments, the first, second, and/or third doping concentrations may be the same as one another. The doping type and/or concentrations may influence the threshold voltages of each of the first, second, and third NSFETs102,104,106. Further, in some embodiments, the first gate electrode structure130, the second gate electrode structure132, and the third gate electrode structure134respectively influence the first threshold voltage of the first NSFET102, the second threshold voltage of the second NSFET104, and the third threshold voltage of the third NSFET106. In some embodiments, the first, second, and third gate electrode structures130,132,134comprise various gate electrode layers136, which will be described in more detail inFIG.2. Nevertheless, due to dummy masking structures formed during the formation of the first, second, and third gate electrode structures130,132,134, the first NSFET102, the second NSFET104, and the third NSFET106may be formed over a same substrate and have different threshold voltages from one another without sacrificing the reliability or the device density of the overall device. FIG.2illustrates a cross-sectional view200of some embodiments of the second NSFET104arranged between the first NSFET102and the third NSFET106. In some embodiments, the cross-sectional view200ofFIG.2may correspond to cross-section line BB′ ofFIG.1. As illustrated inFIG.2, in some embodiments, the first NSFET102comprises first nanosheet channel structures202arranged over the first fin structure112; the second NSFET104comprises second nanosheet channel structures204arranged over the second fin structure114; and the third NSFET106comprises third nanosheet channel structures206arranged over the third fin structure116. It will be appreciated that in some other embodiments, the NSFETs (102,104,106) may each comprise more or less than four nanosheet channel structures (202,204,206). Further, in some embodiments, the vertically arranged first nanosheet channel structures202may be spaced apart from one another in the vertical direction by a first distance d1; the vertically arranged second nanosheet channel structures204may be spaced apart from one another in the vertical direction by the first distance d1; and the vertically arranged third nanosheet channel structures206may be spaced apart from one another in the vertical direction by the first distance d1. In some embodiments, the first distance d1may be less than or equal to approximately 12 nanometers. In other embodiments, the first distance d1may be greater than approximately 12 nanometers. Further, in some embodiments, the first fin structure112may be spaced apart from the second fin structure114by a second distance d2, and the second fin structure114may be spaced apart from the third fin structure116by the second distance d2. In other embodiments, the second distance d2between the first and second fin structures112,114may be different from the second distance d2between the second and third fin structures114,116. In some embodiments, the second distance d2may be in a range of between approximately 10 nanometers and approximately 50 nanometers, for example. It will be appreciated that other values for the second distance d2are also within the scope of the disclosure. In some embodiments, the first nanosheet channel structures202are embedded in the first gate electrode structure130; the second nanosheet channel structures204are embedded in the second gate electrode structure132; and the third nanosheet channel structures206are embedded in the third gate electrode structure134. In some embodiments, the first, second, and third gate electrode structures130,132,134comprise an interfacial layer210and a gate dielectric layer212. In some embodiments, the interfacial layer210comprises multiple ring-like structures that continuously surround and contact each of the first, second, and third nanosheet channel structures202,204,206. Further, the gate dielectric layer212may also comprise ring-like structures that continuously surround each of the first, second, and third nanosheet channel structures202,204,206and contact the interfacial layer210. In such embodiments, the gate dielectric layer212and the interfacial layer210are not continuously connect layers. Instead the gate dielectric layer212and the interfacial layer210have multiple ring-like portions that are disconnected from one another from the cross-sectional view200ofFIG.2. In some embodiments, the gate dielectric layer212high-k dielectric material, such as, for example, hafnium dioxide, zirconium dioxide, hafnium silicon oxide, or some other suitable dielectric material. In some embodiments, the gate dielectric layer212may also be used to tune the work functions and thus, threshold voltages of the first, second, and third NSFETs102,104,106through dipole engineering. In such embodiments, the gate dielectric layer212may comprise lanthanum, magnesium, yttrium, aluminum, niobium, titanium, or some other suitable material used for dipole engineering in the gate dielectric layer212. For example, in some embodiments of a p-type NSFET, wherein mobile charge carriers are positive (e.g., holes), the gate dielectric layer212may comprise aluminum, niobium, or titanium, whereas in embodiment of an n-type NSFET, wherein mobile charge carriers are negative (e.g., electrons), the gate dielectric layer212may comprise lanthanum, magnesium, or yttrium. Further, in some embodiments, the interfacial layer210may comprise an oxide, such as, for example, silicon dioxide. It will be appreciated that other materials for the interfacial layer210and the gate dielectric layer212are also within the scope of this disclosure. Further, in some embodiments, the first gate electrode structure130comprises a first gate electrode layer214that is a continuously connected layer fully surrounding each of the first nanosheet channel structures202. Thus, the first gate electrode layer214is arranged directly between each of the first nanosheet channel structures202. Further, the first gate electrode layer214is arranged directly between a lowermost one of the first nanosheet channel structures202and the first fin structure112. The first gate electrode layer214has a first thickness t1that is less than the first distance d1, in some embodiments. In some embodiments, the second gate electrode structure132comprises a second gate electrode layer216that is a continuously connected layer fully surrounding each of the second nanosheet channel structures204. Thus, the second gate electrode layer216is arranged directly between each of the second nanosheet channel structures204. Further, the second gate electrode layer216is arranged directly between a lowermost one of the second nanosheet channel structures204and the second fin structure114. The second gate electrode layer216has a second thickness t2that is less than the first distance d1, in some embodiments. In some embodiments, the second gate electrode layer216may also be arranged over outer surfaces of the first gate electrode layer214. However, in such embodiments, the second gate electrode layer216may not contribute to or may not significantly contribute to the first threshold voltage of the first NSFET102. Instead, the first threshold voltage of the first NSFET102is dominated at least by the first gate electrode layer214continuously surrounding each of the first nanosheet channel structures202. In some embodiments, the third gate electrode structure134comprises a third gate electrode layer218that is a continuously connected layer fully surrounding each of the third nanosheet channel structures206. Thus, the third gate electrode layer218is arranged directly between each of the third nanosheet channel structures206. Further, the third gate electrode layer218is arranged directly between a lowermost one of the third nanosheet channel structures206and the third fin structure116. The third gate electrode layer218has a third thickness t3that is less than the first distance d1, in some embodiments. In some embodiments, the third gate electrode layer218may also be arranged over outer surfaces of the second gate electrode layer216of the second NSFET104and the first NSFET102. However, in such embodiments, the third gate electrode layer218may not contribute to or may not significantly contribute to the first threshold voltage of the first NSFET102or the second NSFET104. Instead, the first threshold voltage of the first NSFET102is dominated at least by the first gate electrode layer214continuously surrounding each of the first nanosheet channel structures202, and the second threshold voltage of the second NSFET104is dominated at least by the second gate electrode layer216continuously surrounding each of the second nanosheet channel structures204. In some embodiments, the first, second, and third gate electrode layers214,216,218may comprise different materials, and thus, the first NSFET102, the second NSFET104, and the third NSFET106may have different threshold voltages. For example, in some embodiments, the first NSFET102may be an n-type NSFET, wherein the mobile charge carriers are electrons and the first threshold voltage is positive. In such embodiments, the first gate electrode layer214may comprise, for example, titanium aluminum, titanium aluminum carbon, titanium silicon aluminum carbon, or some other suitable conductive material. Further, for example, in some embodiments, the third NSFET106may be, for example, a p-type NSFET, wherein the mobile charge carriers are electrons and the third threshold voltage is negative. In such embodiments, the third gate electrode layer218may comprise, for example, titanium nitride, tungsten carbon nitride, tungsten, tantalum nitride, or some other suitable conductive material. Even further, for example, the second NSFET104may be a p-type, an n-type or some mid-gap type NSFET. In such embodiments, the second gate electrode layer216may comprise, for example, titanium aluminum nitride, titanium silicon nitride, titanium nitride, silicon, or some other suitable conductive material. Further, in some embodiments, the first, second, and/or third NSFETS102,104,106may comprise a passivation layer (not shown) directly contacting and surrounding the gate dielectric layer212. In such embodiments, the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material to further tune the work function and thus, threshold voltages of the NSFETs (102,104,106). It will be appreciated that other designs of multiple NSFETs over a same substrate (108ofFIG.1) are also within the scope of this disclosure. For example, in some embodiments, more or less than three NSFETs may be disposed over the same substrate (108ofFIG.1). Further, for example, in some embodiments, the first, second, and third NSFETs102,104,106may all be n-type NSFETs but still have different threshold voltages due to different first, second, and third gate electrode structures130,132,134. FIG.3illustrates a cross-sectional view300of some embodiments of the second NSFET104that may correspond to cross-section line CC′ ofFIG.1. As illustrated inFIG.3, in some embodiments, the second nanosheet channel structures204extend in parallel from the third source/drain region122to the fourth source/drain region124. Further, the second nanosheet channel structures204directly contact the third and fourth source/drain regions122,124, in some embodiments. In some embodiments, during the formation of the multiple gate electrode layers136, the multiple gate electrode layers136are formed on the second fin structure114, the second nanosheet channel structures204, the third source/drain region122, and the fourth source/drain region124. Thus, in some embodiments, from the cross-sectional view300ofFIG.3, some of the multiple gate electrode layers136, such as the interfacial layer210and the gate dielectric layer212, exhibit rectangular ring-like shapes. In other embodiments, the multiple gate electrode layers136may exhibit more oval-like or circular ring-like shapes from the cross-sectional view300ofFIG.3. During operation of the second NSFET104, a gate voltage VG may be applied to the second gate electrode structure132, a third source/drain voltage VSD3may be applied to the third source/drain region122, and a fourth source/drain voltage VSD4may be applied to the fourth source/drain region124. In some embodiments, when an absolute value of the gate voltage VG exceeds an absolute value of the second threshold voltage of the second NSFET104, the second NSFET104is turned “ON” such that mobile charge carriers (e.g., electrons, holes) between the third source/drain region122and the fourth source/drain region124. In some embodiments, contact vias couple the second gate electrode structure132, the third source/drain region122, and the fourth source/drain region124to a gate voltage source, a third source/drain voltage source, and a fourth source/drain voltage source, respectively. In some embodiments, the filler layer138comprises a conductive material, such as, for example, titanium nitride, tantalum nitride, or the like. Thus, the filler layer138may be electrically coupled to the second gate electrode structure132. Because of the compositions and thicknesses of the multiple gate electrode layers136of the second gate electrode structure132and the manufacturing thereof, the second threshold voltage of the second NSFET104may be designed to be a desired value. Therefore, when the gate voltage VG exceeds the second threshold voltage of the second NSFET104, the second nanosheet channel structures204may be simultaneously and reliably turned “ON.” FIGS.4-26illustrate various views400-2600of some embodiments of a method of forming first, second, and third NSFETs arranged over a substrate and having different threshold voltages AlthoughFIGS.4-26are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.4-26are not limited to such a method, but instead may stand alone as structures independent of the method. As shown in perspective view400ofFIG.4, a substrate108is provided. In some embodiments, the substrate108may be or comprise a semiconductor wafer, a semiconductor substrate, a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, the substrate108may comprise a first semiconductor material such as, for example, silicon, germanium, or some other suitable semiconductor material. In such embodiments, the substrate108may be an intrinsic (e.g., not doped) semiconductor. As shown in perspective view500ofFIG.5, in some embodiments, a stack of semiconductor layers501may be formed over the substrate108. The stack of semiconductor layers501may comprise spacer layers502and semiconductor layers506, wherein the spacer layers502and the semiconductor layers506are arranged in an alternating order in the stack of semiconductor layers501. In other words, each one of the semiconductor layers506is arranged between a lower one of the spacer layers502and an upper one of the spacer layers502. In some embodiments, the semiconductor layers506comprise the first semiconductor material, and the spacer layers502comprise a second semiconductor material that is different than the first semiconductor material. For example, in some embodiments, the first semiconductor material may comprise silicon, whereas the second semiconductor material may comprise germanium or silicon germanium. In some embodiments, the semiconductor layers506and the spacer layers502are formed by an epitaxy growth process. Further, in some embodiments, the semiconductor layers506have a fourth thickness t4, and the spacer layers502have a fifth thickness t5. In some embodiments, the spacer layers502are removed, and the semiconductor layers506eventually are formed into nanosheet channel structures (e.g., see,202,204,206ofFIG.15). Thus, the fifth thickness t5of the spacer layers502may determine the spacing of the nanosheet channel structures (e.g., see,202,204,206ofFIG.15). In some embodiments, the fourth thickness t4may be in a range of between, for example, approximately 4 nanometers and approximately 8 nanometers. In some embodiments, the fifth thickness t5may be in a range of between, for example, approximately 8 nanometers and approximately 15 nanometers. It will be appreciated that other values for the fourth and fifth thicknesses t4, t5are also within the scope of this disclosure. Further, in some embodiments, a topmost layer of the stack of semiconductor layers501may be one of the spacer layers502to protect the semiconductor layers506during future processing steps. In some embodiments, it will be appreciated that although four semiconductor layers506are illustrated in the perspective view500ofFIG.5, the number of semiconductor layers506in the stack of semiconductor layers501may be less than or greater than four. As shown in perspective view600ofFIG.6, in some embodiments, a first masking structure610, a second masking structure612, and a third masking structure614are arranged over the stack of semiconductor layers (501ofFIG.5). In some embodiments, the first, second, and third masking structures610,612,614may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, the first, second, and third masking structures610,612,614may comprise photoresist materials or hard mask materials. Further, as shown in perspective view600ofFIG.6, in some embodiments, a first removal process may be performed according to the first, second, and third masking structures610,612,614to form a first fin structure112, a second fin structure114, and a third fin structure116from the substrate108. In some embodiments, the first removal process may be or comprise a dry, vertical etch. The first fin structure112, the second fin structure114, and the third fin structure116are continuously connected to one another through the substrate108. The first fin structure112, the second fin structure114, and the third fin structure116directly underlie the first masking structure610, the second masking structure612, and the third masking structure614, respectively. In some embodiments, the first fin structure112is spaced apart from the second fin structure114by a second distance d2, and the second fin structure114is spaced apart from the third fin structure116by the second distance d2. In some embodiments, the second distance d2may be in a range of between, for example, approximately 10 nanometers and approximately 50 nanometers. In some embodiments, the first removal process removes portions of the semiconductor layers (506ofFIG.5) and the spacer layers (502ofFIG.5) that are uncovered by the first, second, and third masking structures610,612,614. Therefore, after the first removal process, a first stack of semiconductor layers601comprising patterned spacer layers602and patterned semiconductor layers606is arranged over the first fin structure112; a second stack of semiconductor layers603comprising patterned spacer layers602and patterned semiconductor layers606is arranged over the second fin structure114; and a third stack of semiconductor layers605comprising patterned spacer layers602and patterned semiconductor layers606is arranged over the third fin structure116. It will be appreciated that in other embodiments, more or less than three nanosheet field effect transistors (NSFETs) may be formed, and thus, more or less than the first, second, and third masking structures610,612,614may be used. As shown in perspective view700ofFIG.7, in some embodiments, a lower isolation structure110amay be formed over the substrate108and between the first, second, and third fin structures112,114,116. The lower isolation structure110amay provide electrical isolation between the first, second, and third fin structures112,114,116, in some embodiments. In some embodiments, the lower isolation structure110amay comprise a dielectric material such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. In some embodiments, the lower isolation structure110ais formed through various steps comprising a thermal oxidation or deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), and removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.). For example, in some embodiments, a dielectric material is deposited over the substrate108and the first, second, and third masking structures (610,612,614ofFIG.6). Then, in some embodiments, a removal process, such as CMP, is used to remove portions of the dielectric material and the first, second, and third masking structures (610,612,614ofFIG.6), thereby exposing the first, second, and third stacks of semiconductor layers601,603,605. Then, in some embodiments, another removal process, such as a vertical, dry etch, may be performed to remove portions of the dielectric material surrounding the first, second, and third stacks of semiconductor layers601,603,605to form the lower isolation structure110a. It will be appreciated that other processes and/or order of steps to form the lower isolation structure110aare also within the scope of the disclosure. As shown in perspective view800ofFIG.8, a dummy gate structure804may be formed over the first, second, and third stacks of semiconductor layers601,603,605. In some embodiments, a dummy interfacial layer802separates the first, second, and third stacks of semiconductor layers601,603,605from the dummy gate structure804, and a fourth masking structure806is arranged over the dummy gate structure804. In some embodiments, to form the dummy gate structure804, a dummy interfacial material of the dummy interfacial layer802is first formed over the first, second, and third stacks of semiconductor layers601,603,605. In some embodiments, the dummy interfacial layer802may comprise, for example, a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or some other suitable material. Then, in some embodiments, a dummy gate material of the dummy gate structure804, such as, for example, polysilicon, is formed over the dummy interfacial material. The dummy gate material and/or the dummy interfacial material may be formed by way of a thermal oxidation process and/or a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the fourth masking structure806is formed over the dummy gate material and directly overlies the first, second, and third stacks of semiconductor layers601,603,605. In some embodiments, the fourth masking structure806may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, the fourth masking structure806may comprise photoresist materials or hard mask materials. After the formation of the fourth masking structure806, a removal process (e.g., etching) may be performed to remove portions of the dummy gate material and the dummy interfacial material that do not directly underlie the fourth masking structure806, thereby forming the dummy gate structure804and the dummy interfacial layer802, respectively. As shown in perspective view900ofFIG.9, in some embodiments, a gate spacer layer902may be formed over the lower isolation structure110a, the first stack of semiconductor layers601, the second stack of semiconductor layers603, the third stack of semiconductor layers605, and the dummy gate structure (804ofFIG.8). In some embodiments, the gate spacer layer902may be or comprise a dielectric material such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. Further, in some embodiments, the gate spacer layer902may be deposited by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). It will be appreciated that other materials and/or ways of forming the gate spacer layer902are also within the scope of the disclosure. As shown in perspective view1000ofFIG.10, in some embodiments, a second removal process may be performed to remove portions of the gate spacer layer902, the first stack of semiconductor layers601, the second stack of semiconductor layers603, and the third stack of semiconductor layers605that do not directly underlie the fourth masking structure806. In some embodiments, the second removal process may be or comprise an etching process. In some embodiments, a single etchant may be used to remove the gate spacer layer902, the first stack of semiconductor layers601, the second stack of semiconductor layers603, and the third stack of semiconductor layers605, whereas in other embodiments, multiple etchants may be used to perform the second removal process. After the second removal process, the first fin structure112, the second fin structure114, and the third fin structure116are exposed. In some embodiments, upper portions of the lower isolation structure110a, the first fin structure112, the second fin structure114, the third fin structure116, and/or the fourth masking structure806may be residually removed by the second removal process. Thus, in some embodiments, after the second removal process, the first fin structure112, the second fin structure114, and the third fin structure116may have upper surfaces below an upper surface of the lower isolation structure110a. As shown in perspective view1100ofFIG.11, in some embodiments, an epitaxial growth process may be performed to form a first source/drain region110and a second source/drain region (not shown) on the first fin structure112, to form a third source/drain region122and a fourth source/drain region (not shown) on the second fin structure114, and to form a fifth source/drain region126and a sixth source/drain region128on the third fin structure116. The first source/drain region118, the second source/drain region (not shown), the third source/drain region122, the fourth source/drain region (not shown), the fifth source/drain region126, and the sixth source/drain region128may comprise a third semiconductor material. In some embodiments, the third semiconductor material may be doped silicon, for example. In some embodiments, the first source/drain region118and the second source/drain region (not shown) may have a first doping type and first doping concentration, the third source/drain region122and the fourth source/drain region (not shown) may have a second doping type and second doping concentration, and the fifth source/drain region126and the sixth source/drain region128may have a third doping type and third doping concentration. Thus, in some embodiments, the first, second, and/or third doping types may be the same or different from one another. In some embodiments, due to the epitaxial growth process, the first source/drain region118, the second source/drain region (not shown), the third source/drain region122, the fourth source/drain region (not shown), the fifth source/drain region126, and the sixth source/drain region128may exhibit a hexagonal shape, a diamond shape, or some other geometric shape. Further, in some embodiments, the first source/drain region118, the second source/drain region (not shown), the third source/drain region122, the fourth source/drain region (not shown), the fifth source/drain region126, and the sixth source/drain region128do not directly contact one another. As shown in the perspective view1200ofFIG.12, in some embodiments, an upper isolation structure110bis formed over the lower isolation structure110a, the first source/drain region118, the second source/drain region (not shown), the third source/drain region122, the fourth source/drain region (not shown), the fifth source/drain region126, and the sixth source/drain region (not shown). In some embodiments, the upper isolation structure110bcomprises a dielectric material such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. The upper isolation structure110bmay provide electrical isolation between first source/drain region118, the second source/drain region (not shown), the third source/drain region122, the fourth source/drain region (not shown), the fifth source/drain region126, and the sixth source/drain region (not shown), in some embodiments. In some embodiments, the upper isolation structure110bis formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). Further, in some embodiments, prior to the formation of the upper isolation structure110b, an etch stop layer (not shown) may be formed over the lower isolation structure110a, first source/drain region118, the second source/drain region (not shown), the third source/drain region122, the fourth source/drain region (not shown), the fifth source/drain region126, and the sixth source/drain region (not shown). As shown in perspective view1300ofFIG.13, in some embodiments, a third removal process is performed to remove the fourth masking structure (806ofFIG.8), the dummy gate structure (804ofFIG.8), and the dummy interfacial layer (802ofFIG.8) from the first stack of semiconductor layers601, the second stack of semiconductor layers603, and the third stack of semiconductor layers605. In some embodiments, the third removal process comprises a CMP step and/or an etching step. For example, in some embodiments, the third removal process first includes a CMP step to remove upper portions of the upper isolation structure110band to completely remove the fourth masking structure (806ofFIG.8) to expose the dummy gate structure (804ofFIG.8). In some embodiments, the third removal process further includes performing an etching step to completely remove the dummy gate structure (804ofFIG.8) to expose the first stack of semiconductor layers601, the second stack of semiconductor layers603, and the third stack of semiconductor layers605. It will be appreciated that the second source/drain region120, the fourth source/drain region124, and the sixth source/drain region128are arranged behind the gate spacer layer902and thus, are illustrated with dotted lines. As shown in perspective view1400ofFIG.14, in some embodiments, a fourth removal process is performed to remove the patterned spacer layers (602ofFIG.13) from the first, second, and third stacks of semiconductor layers (601,603,605ofFIG.13). In some embodiments, the fourth removal process comprises an isotropic etching step such that the patterned spacer layers (602ofFIG.13) from the first, second, and third stacks of semiconductor layers (601,603,605ofFIG.13) can be completely removed from between the patterned semiconductor layers (606ofFIG.13). In some embodiments, the fourth removal process may comprise a wet etchant or a dry etchant. After the fourth removal process, in some embodiments, first nanosheet channel structures (see,202ofFIG.15) comprising the patterned semiconductor layers (606ofFIG.13) extend from the first source/drain region118to the second source/drain region120; second nanosheet channel structures (see,204ofFIG.15) comprising the patterned semiconductor layers (606ofFIG.13) extend from the third source/drain region122to the fourth source/drain region124; and third nanosheet channel structures206comprising the patterned semiconductor layers (606ofFIG.13) extend from the fifth source/drain region126to the sixth source/drain region128. FIG.15illustrates a cross-sectional view1500of some embodiments that may correspond to cross-section line BB′ ofFIG.14. As shown in the cross-sectional view1500ofFIG.15, in some embodiments, after the fourth removal process, first nanosheet channel structures202are arranged directly over the first fin structure112; second nanosheet channel structures204are arranged directly over the second fin structure114; and third nanosheet channel structures206are arranged directly over the third fin structure116. In the cross-sectional view1500ofFIG.15, each of the first, second, and third nanosheet channel structures202,204,206exhibit an elongated oval-like shape or rectangular shape with rounded corners. In some embodiments, the rounded corners are a result of the fourth removal process. In other embodiments, the first, second, and third nanosheet channel structures202,204,206may exhibit a circle, square, rectangle, hexagon, oval, diamond, or some other shape from the cross-sectional view1500after the fourth removal process. In some embodiments, each of the first nanosheet channel structures202, the second nanosheet channel structures204, and the third nanosheet channel structures206are vertically spaced apart from one another by a first distance d1. For example, the first distance d1is the distance between an upper surface of a lowermost one of the first nanosheet channel structures202and a lower surface of a second lowermost one of the first nanosheet channel structures202, wherein the second lowermost one of the first nanosheet channel structures202is nearest neighbors with the lowermost one of the first nanosheet channel structures202. In some embodiments, the fifth thickness (t5ofFIG.5) of the spacer layers (502ofFIG.5) determines the first distance d1. Thus, in some embodiments, the first distance d1may be in a range of between, for example, approximately 8 nanometers and approximately 15 nanometers. Further, in some embodiments, each of the first, second, and third nanosheet channel structures202,204,206have the fourth thickness t4as determined by the fourth thickness t4of the semiconductor layers (506ofFIG.5). Thus, in some embodiments, the fourth thickness t4of the first, second, and third nanosheet channel structures202,204,206is in a range of between, approximately 4 nanometers and approximately 8 nanometers, for example. In some embodiments, each of the first, second, and third nanosheet channel structures202,204,206may have a first width w1that is in a range of between, for example, approximately 10 nanometers and approximately 70 nanometers. It will be appreciated that other values for the first distance d1, the fourth thickness t4, and the first width w1are also within the scope of the disclosure. It will be appreciated that for ease of illustration, a generic layer1502is illustrated behind the first, second, and third nanosheet channel structures202,204,206and in front of the second, fourth, and sixth source/drain regions120,124,128. For example, from the perspective view1400ofFIG.14, it can be understood that the generic layer1502represents the gate spacer layer902, in some embodiments. The generic layer1502is illustrated as a white box with a hashed outline. This way, in future processing steps, layers formed around the first, second, and third nanosheet channel structures202,204,206may be more easily visible. As shown in cross-sectional view1600ofFIG.16, in some embodiments, an interfacial layer210is formed over the first, second, and third fin structures112,114,116and around each nanosheet channel structure of the first, second, and third nano sheet channel structures202,204,206. In some embodiments, the interfacial layer210may comprise, for example, an oxide such as silicon dioxide. In such embodiments, the interfacial layer210may be formed by way of a thermal oxidation process or by other deposition processes (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). In some embodiments the interfacial layer210may have a thickness in a range of between approximately 8 angstroms and approximately 15 angstroms, for example. In some embodiments, from the cross-sectional view1600, the interfacial layer210may comprise ring-like structures that surround and directly contact each of the first, second, and third nanosheet channel structures202,204,206. Further, in some embodiments, a gate dielectric layer212is formed over the interfacial layer210. In some embodiments, the gate dielectric layer212may comprise a high-k dielectric material, such as, for example, hafnium dioxide, zirconium dioxide, hafnium silicon oxide, or some other suitable dielectric material. In some embodiments, the gate dielectric layer212may also comprise lanthanum, magnesium, yttrium, aluminum, niobium, titanium, or some other suitable material used for dipole engineering in the gate dielectric layer212. For example, in some embodiments of a p-type NSFET, wherein mobile charge carriers are positive (e.g., holes), the gate dielectric layer212may comprise aluminum, niobium, or titanium, whereas in embodiment of an n-type NSFET, wherein mobile charge carriers are negative (e.g., electrons), the gate dielectric layer212may comprise lanthanum, magnesium, or yttrium. The gate dielectric layer212may comprise the same composition on each of the first, second, and third nanosheet channel structures202,204,206, in some embodiments. In some embodiments, the gate dielectric layer212may be formed by way of a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). In some embodiments the gate dielectric layer212may have a thickness in a range of between approximately 10 angstroms and approximately 20 angstroms, for example. In some embodiments, from the cross-sectional view1600, the gate dielectric layer212may also comprise ring-like structures that surround each of the first, second, and third nanosheet channel structures202,204,206. The interfacial layer210may separate the gate dielectric layer212from directly contacting the first, second, and third nano sheet channel structures202,204,206. After the formation of the interfacial layer210and the gate dielectric layer212, in some embodiments, a third distance d3remains between nearest neighboring ring-like structures of the gate dielectric layer212. Thus, the thickness of the interfacial layer210and the thickness of the gate dielectric layer212are small enough to allow the third distance d3to remain between the first, second, and third nanosheet channel structures202,204,206. In some embodiments, the third distance d3is in a range of between, for example, approximately 4 nanometers and approximately 6 nanometers. It will be appreciated that other values of the third distance d3are also within the scope of this disclosure. As shown in cross-sectional view1700ofFIG.17, in some embodiments, a dummy masking layer1702is formed over the first, second, and third fin structures112,114,116and over and around the first, second, and third nanosheet channel structures202,204,206. In some embodiments, the dummy masking layer1702comprises aluminum oxide, titanium nitride, or some other suitable hard mask material. In some embodiments, the dummy masking layer1702may be formed by way of a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). The dummy masking layer1702is formed to completely cover the first fin structure112, the second fin structure114, and the third fin structure116, and to completely surround each of the first, second, and third nanosheet channel structures202,204,206. In some embodiments, the dummy masking layer1702has a sixth thickness t6, and the sixth thickness t6is at least equal to one-half of the third distance d3. Thus, the dummy masking layer1702completely fills in the space directly between the nearest first, second, and third nanosheet channel structures202,204,206. The dummy masking layer1702also fills in the space directly between the first fin structure112and a lowermost one of the first nanosheet channel structures202, directly between the second fin structure114and a lowermost one of the second nanosheet channel structures204, and directly between the third fin structure116and a lowermost one of the third nanosheet channel structures206. As shown in cross-sectional view1800ofFIG.18, in some embodiments, a fifth removal process is performed to remove outer portions of the dummy masking layer (1702ofFIG.17), thereby forming a first dummy masking structure1802directly overlying the first fin structure112, a second dummy masking structure1804directly overlying the second fin structure114, and a third dummy masking structure1806directly overlying the third fin structure116. Further, the first dummy masking structure1802, the second dummy masking structure1804, and the third dummy masking structure1806are respectively arranged directly between the first nanosheet channel structures202, the second nanosheet channel structures204, and the third nanosheet channel structures206. In some embodiments, the fifth removal process may comprise a wet or dry etch. The etchant used for the fifth removal process to form the first, second, and third dummy masking structures1802,1804,1806selectively removes the material of the dummy masking layer (1702ofFIG.17) without removing the gate dielectric layer212. Thus, in some embodiments, the material of the dummy masking layer (1702ofFIG.17) is a material that may be selectively removed by a certain etchant, while that certain etchant does not remove the material of the gate dielectric layer212. For example, in some embodiments, the dummy masking layer (1702ofFIG.17) may comprise aluminum oxide and the etchant of the fifth removal process comprises an ammonium hydroxide solution. It will be appreciated that other materials of the dummy masking layer (1702ofFIG.17) and etchants are also within the scope of this disclosure. Further, in some embodiments, the fifth removal process is performed for a time period that removes at least the sixth thickness (t6ofFIG.17) of the dummy masking layer (1702ofFIG.17) while majority of the dummy masking layer (1702ofFIG.17) still remains directly between the vertically arranged first, second, and third nanosheet channel structures202,204,206to form the first, second, and third dummy masking structures1802,1804,1806, respectively. As shown in cross-sectional view1900ofFIG.19, in some embodiments, a fifth masking structure1902is formed over the second and third fin structures114,116and over the second and third nanosheet channel structures204,206. The fifth masking structure1902does not directly overlie the first fin structure112or the first nanosheet channel structures202. In some embodiments, the fifth masking structure1902may be formed using deposition (e.g., spin-coating), photolithography and removal (e.g., etching) processes. For example, in some embodiments, the fifth masking structure1902may be or comprise a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), or some other suitable photoresist material. In other embodiments, the fifth masking structure1902may be or comprise a hard mask material. After the formation of the fifth masking structure1902, in some embodiments, a sixth removal process is performed to completely remove the first dummy masking structure (1802ofFIG.18) that is uncovered by the fifth masking structure1902. In some embodiments, the sixth removal process may comprise the same etchant as the fifth removal process because the same dummy masking material is being removed without removing the gate dielectric material of the gate dielectric layer212. As shown in cross-sectional view2000ofFIG.20, in some embodiments, the fifth masking structure (1902ofFIG.19) is removed, and a first conductive layer2002is formed over and completely surrounding each of the first nanosheet channel structures202and is formed over the second and third nanosheet channel structures204,206. Because of the second dummy masking structure1804and the third dummy masking structure1806, the first conductive layer2002does not completely surround each of the second and third nanosheet channel structures204,206. In some embodiments, the first conductive layer2002is formed to have a first thickness t1. In some embodiments, the first thickness t1is at least equal to one half of the third distance (d3ofFIG.16) such that the first conductive layer2002is a continuously connected layer from the cross-sectional view2000and completely surrounds each of the first nanosheet channel structures202. In some embodiments, the first conductive layer2002is formed by way of a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In some embodiments, the first conductive layer2002comprises a conductive material that is an n-type work function metal (e.g., titanium aluminum, titanium aluminum carbide, tantalum aluminum carbide, titanium silicon aluminum carbide, etc.), that is a p-type work function metal (e.g., titanium nitride, tungsten carbon nitride, tungsten, tantalum nitride, etc.), or that is a mid-gap type work function metal (e.g., titanium aluminum nitride, titanium silicon nitride, titanium nitride and silicon, etc.). Further, in some embodiments, prior to the formation of the first conductive layer2002, a passivation layer may be formed surrounding each of the first nanosheet channel structures202. In such embodiments (not shown), the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material. As shown in cross-sectional view2100ofFIG.21, in some embodiments, a sixth masking structure2102is formed over the first fin structure112and the first nanosheet channel structures202. The sixth masking structure2102does not directly overlie the second or third fin structures114,116. In some embodiments, the sixth masking structure2102may be formed using deposition (e.g., spin-coating), photolithography and removal (e.g., etching) processes. For example, in some embodiments, the sixth masking structure2102may be or comprise a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), or some other suitable photoresist material. In some other embodiments, the sixth masking structure2102may be or comprise a hard mask material. After the formation of the sixth masking structure2102, in some embodiments, a seventh removal process is performed to remove portions of the first conductive layer (2002ofFIG.20) that are uncovered by the sixth masking structure2102leaving behind a first gate electrode layer214over the first fin structure112. Thus, the seventh removal process completely removes the first conductive layer (2002ofFIG.20) from the second and third nanosheet channel structures204,206. In some embodiments, the seventh removal process comprises a wet or dry etch process. The etchant used by the seventh removal process removes the first conductive layer (2002ofFIG.20) without removing the second dummy masking structure1804, the third dummy masking structure1806, or the gate dielectric layer212. After the seventh removal process, a first nanosheet field effect transistor (NSFET)102is formed comprising the first nanosheet channel structures202embedded in a first gate electrode structure130, wherein the first gate electrode structure130includes the first gate electrode layer214, the gate dielectric layer212, and the interfacial layer210. The first NSFET102may have a first threshold voltage that is at least influenced by the materials and/or thicknesses of the first gate electrode layer214and the gate dielectric layer212. During the seventh removal process, the second dummy masking structure1804and the third dummy masking structure1806reduce a maximum dimension of the first conductive layer (2002ofFIG.20) to be removed by the seventh removal process by at least a fourth distance d4. In some embodiments, the width of the second and third dummy masking structures1804,1806are equal to two times of the fourth distance d4. In some embodiments, because of the second and third dummy masking structures1804,1806, the maximum dimension of the first conductive layer (2002ofFIG.20) to be removed by the seventh removal process is about equal to the first thickness t1, for example. In some embodiments, as a result of the reduction in the maximum dimensions of the first conductive layer (2002ofFIG.20) for removal by the seventh removal process, the etching time(s) of the seventh removal process may be reduced. Then, portions2104of the first conductive layer (2002ofFIG.20) that are arranged directly below the sixth masking structure2102and closest to the second fin structure114are not exposed to the seventh removal process as long. Therefore, removal of the portions2104of the first conductive layer (2002ofFIG.20) is prevented or at least mitigated. In other embodiments, without the first and second dummy masking structures1804,1806, it will be appreciated that over-etching by the seventh removal process could remove portions of the first gate electrode layer214arranged below the sixth masking structure2102, thereby compromising the reliability of the first NSFET102. Thus, because of the second and third dummy masking structures1804,1806, the seventh removal process is quicker and exposure of the portions2104of the first conductive layer (2002ofFIG.20) to the etchant(s) of the seventh removal process is reduced, thereby preventing damage to the first gate electrode structure130and corresponding first NSFET102. As illustrated in cross-sectional view2200ofFIG.22, in some embodiments, a seventh masking structure2202is formed over the third fin structure116and the third nanosheet channel structures206. In some embodiments, the sixth masking structure2102remains over the first fin structure112when the seventh masking structure2202is formed, whereas in other embodiments, the sixth masking structure2102may be removed, and then the seventh masking structure2202may be formed over the first and third fin structures112,116. Nevertheless, in the cross-sectional view2200ofFIG.22, the first and third fin structures112,116and the first and third nanosheet channel structures202,206are covered by masking structures (e.g.,2102,2202) while the second fin structure114and the second nanosheet channel structures204are uncovered. After the formation of the seventh masking structure2202, an eighth removal process is conducted to completely remove the second dummy masking structure (1804ofFIG.21) that is uncovered by the sixth and seventh masking structures2102,2202. In such embodiments, the eighth removal process may comprise the same etchant as the sixth removal process because the dummy masking material is being removed without removing the gate dielectric material of the gate dielectric layer212. Further, the etchant used in the eighth removal process does not remove the material of the first gate electrode layer214. Therefore, the second dummy masking structure (1804ofFIG.21) advantageously reduces over-etching of the first conductive layer (2002ofFIG.20) during the seventh removal process ofFIG.22without damaging other features (e.g., the first gate electrode layer214, the gate dielectric layer212). As shown in the cross-sectional view2300ofFIG.23, in some embodiments, the sixth and seventh masking structures (2102,2202ofFIG.22) are removed, and a second conductive layer2302is formed over and completely surrounding each of the second nanosheet channel structures204and is formed over the first and third nanosheet channel structures202,206. Because of the third dummy masking structure1806, the second conductive layer2302does not completely and continuously surround each of the third nanosheet channel structures206. In some embodiments, the second conductive layer2302is formed to a second thickness t2. In some embodiments, the second thickness t2is at least equal to one half of the third distance (d3ofFIG.16) such that the second conductive layer2302is a continuously connected layer from the cross-sectional view2300and completely surrounds each of the second nanosheet channel structures204. Further, in some embodiments, the second conductive layer2302is formed over outer surfaces of the first gate electrode layer214. In such embodiments, the second conductive layer2302is not arranged directly between the first nanosheet channel structures202or directly between a lowermost one of the nanosheet channel structures202and the first fin structure112. In such embodiments, the second conductive layer2302does not affect or does not significantly affect the first work function of the first NSFET102. In some embodiments, the second conductive layer2302is formed by way of a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In some embodiments, the second conductive layer2302comprises a conductive material that is an n-type work function metal (e.g., titanium aluminum, titanium aluminum carbide, tantalum aluminum carbide, titanium silicon aluminum carbide, etc.), that is a p-type work function metal (e.g., titanium nitride, tungsten carbon nitride, tungsten, tantalum nitride, etc.), or that is a mid-gap type work function metal (e.g., titanium aluminum nitride, titanium silicon nitride, titanium nitride and silicon, etc.). Further, in some embodiments, prior to the formation of the second conductive layer2302, a passivation layer may be formed surrounding each of the second nanosheet channel structures204. In such embodiments (not shown), the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material. As shown in cross-sectional view2400ofFIG.24, in some embodiments, eighth masking structure2402is formed over the first and second fin structures112,114and over the first and second nanosheet channel structures202,204. The eighth masking structure2402does not directly overlie the third fin structure116. In some embodiments, the eighth masking structure2402may be formed using deposition (e.g., spin-coating), photolithography and removal (e.g., etching) processes. For example, in some embodiments, the eighth masking structure2402may be or comprise a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), or some other suitable photoresist material. In some other embodiments, the eighth masking structure2402may be or comprise a hard mask material. After the formation of the eighth masking structure2402, in some embodiments, a ninth removal process is performed to remove portions of the second conductive layer (2302ofFIG.23) that are uncovered by the eighth masking structure2402thereby forming a second gate electrode layer216over the second fin structure114. Thus, the ninth removal process completely removes the second conductive layer (2302ofFIG.23) from the third nanosheet channel structures206. In some embodiments, the ninth removal process comprises a wet or dry etch process. The etchant used by the ninth removal process removes the second conductive layer (2302ofFIG.23) without removing the gate dielectric layer212. Further, in some embodiments, the ninth removal process does not remove the third dummy masking structure (1806ofFIG.23). During the ninth removal process, the third dummy masking structure (1806ofFIG.23) reduces a maximum dimension of the second conductive layer (2302ofFIG.23) to be removed by the ninth removal process. Thus, in some embodiments, as a result of the reduction in the maximum dimensions of the second conductive layer (2302ofFIG.23) for removal by the ninth removal process, the etching time(s) of the ninth removal process may be reduced. Then, portions2404of the second conductive layer (2302ofFIG.23) that are arranged directly below the eighth masking structure2402and closest to the third fin structures116are not exposed to the ninth removal process as long. Therefore, removal of the portions2404of the second conductive layer (2302ofFIG.23) is prevented or at least mitigated. In other embodiments, without the third dummy masking structure1806, it will be appreciated that over-etching by the ninth removal process could remove portions of the second gate electrode layer216arranged below the eighth masking structure2402, thereby compromising the reliability of the second gate electrode layer216. Thus, because of the third dummy masking structure1806, the ninth removal process is quicker and exposure of the portions2404of the second conductive layer (2302ofFIG.23) to the etchant(s) of the ninth removal process is reduced, thereby preventing damage to the second gate electrode layer216. Further, in some embodiments, after the second conductive layer (2302ofFIG.23) is removed from the third fin structure116and the third nanosheet channel structures206, a tenth removal process is conducted to completely remove the third dummy masking structure (1806ofFIG.23) that is uncovered by the eighth masking structure2402. In such embodiments, the tenth removal process may comprise the same etchant as the sixth and eighth removal processes used to remove the first and second dummy masking structures (1802,1804ofFIG.18), respectively. In such embodiments, the etchant used in the tenth removal process removes the dummy masking material without removing the gate dielectric material of the gate dielectric layer212and without removing the second gate electrode layer216. Therefore, the third dummy masking structure (1806ofFIG.23) advantageously reduces over-etching of the second conductive layer (2302ofFIG.23) during the ninth removal process without damaging other features (e.g., the second gate electrode layer216, the gate dielectric layer212) of the final device. After the ninth and tenth removal processes, a second nanosheet field effect transistor (NSFET)104is formed comprising the second nanosheet channel structures204embedded in a second gate electrode structure132, wherein the second gate electrode structure132includes the second gate electrode layer216, the gate dielectric layer212, and the interfacial layer210. The second NSFET104may have a second threshold voltage that is at least influenced by the materials and/or thicknesses of the second gate electrode layer216and the gate dielectric layer212. As shown in cross-sectional view2500ofFIG.25, in some embodiments, the eighth masking structure (2402ofFIG.24) is removed, and a third gate electrode layer218is formed over the third fin structure116and over and around the third nanosheet channel structures206. In some embodiments, the third gate electrode layer218is formed to have a third thickness t3. In some embodiments, the third thickness t3is at least equal to one half of the third distance (d3ofFIG.16) such that the third gate electrode layer218is a continuously connected layer from the cross-sectional view2500and completely surrounds each of the third nano sheet channel structures206. In some embodiments, the third gate electrode layer218is also formed over outer surfaces of the second gate electrode layer216, and thus, the third gate electrode layer218is arranged over the first and second fin structures112,114and over the first and second nanosheet channel structures202,204. In such embodiments, the third gate electrode layer218does not continuously surround each of the first and second nanosheet channel structures202,204and does not affect or does not significantly affect the first work function of the first NSFET102or the second work function of the second NSFET104. In some embodiments, the third gate electrode layer218is formed by way of a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In some embodiments, the third gate electrode layer218comprises a conductive material that is an n-type work function metal (e.g., titanium aluminum, titanium aluminum carbide, tantalum aluminum carbide, titanium silicon aluminum carbide, etc.), that is a p-type work function metal (e.g., titanium nitride, tungsten carbon nitride, tungsten, tantalum nitride, etc.), or that is a mid-gap type work function metal (e.g., titanium aluminum nitride, titanium silicon nitride, titanium nitride and silicon, etc.). Further, in some embodiments, prior to the formation of the third gate electrode layer218, a passivation layer may be formed surrounding each of the third nanosheet channel structures206. In such embodiments (not shown), the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material. After the formation of the third gate electrode layer218, a third nanosheet field effect transistor (NSFET)106is formed comprising the third nanosheet channel structures206embedded in a third gate electrode structure134, wherein the third gate electrode structure134includes the third gate electrode layer218, the gate dielectric layer212, and the interfacial layer210. The third NSFET106may have a third threshold voltage that is at least influenced by the materials and/or thicknesses of the third gate electrode layer218and the gate dielectric layer212. As shown in cross-sectional view2600ofFIG.26, in some embodiments, a filler layer138is formed over the first, second, and third NSFETs102,104,106. In some embodiments, the filler layer138comprises a conductive material such as, for example, titanium nitride, tantalum nitride, tungsten carbon nitride, or some other suitable material. In some embodiments, the filler layer138is formed by way of a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.). Further, in some embodiments, the filler layer138does not affect or does not significantly affect the first work function of the first gate electrode structure130, the second work function of the second gate electrode structure132, or the third work function of the third gate electrode structure134. Further, in some embodiments, a first contact via2602, a second contact via2604, and a third contact via2606may be formed within the filler layer138. In some embodiments, the first contact via2602, the second contact via2604, and the third contact via2606may respectively contact the first gate electrode structure130, the second gate electrode structure132, and the third gate electrode structure134. In some embodiments, the first, second, and third contact vias2602,2604,2606may comprise, for example, tungsten, aluminum, copper, or some other suitable conductive material. In some embodiments, the first, second, and third contact vias2602,2604,2606may be formed through various steps comprising deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and/or patterning processes (e.g., photolithography/etching). During operation, in some embodiments, the first, second, and third contact vias2602,2604,2606may be coupled to gate electrode sources to selectively control which of the first, second, and/or third NSFETs102,104,106may be turned “ON” according to their threshold voltages during operation. In some embodiments, the first NSFET102, the second NSFET104, and the third NSFET106may comprise different gate electrode structures (130,132,134) and thus, may comprise different threshold voltages. Nevertheless, because of the first, second, and third dummy masking structures (1802,1804,1806ofFIG.18), the first, second, and third NSFETs102,104,106may be reliably formed beside one another over a same substrate. It will be appreciated that the method depicted inFIGS.4-26may be modified to accommodate more or less than the first, second, and third NSFETs102,104,106. FIG.27illustrates a flow diagram of some embodiments of a method2700of forming a first NSFET having a first gate electrode layer beside a second NSFET having a second gate electrode layer that is different from the first gate electrode layer. While method2700is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At act2702, a first nanosheet channel structure and a second nanosheet channel structure are formed over a substrate and between first and second source/drain regions. At act2704, a third nanosheet channel structure and a fourth nanosheet channel structure are formed over the substrate, arranged laterally beside the first and second nanosheet channel structures, and between the third and fourth source/drain regions.FIG.15illustrates cross-sectional view1500of some embodiments corresponding to acts2702and2704. At act2706, a dummy masking layer is formed over and between the first, second third, and fourth nanosheet channel structures.FIG.17illustrates cross-sectional view1700of some embodiments corresponding to act2706. At act2708, portions of the dummy masking layer are removed to form a dummy masking structure arranged directly between the third and fourth nanosheet channel structures and directly between the third nanosheet channel structure and the substrate.FIG.18illustrates cross-sectional view1800of some embodiments corresponding to act2708. At act2710, a first gate electrode layer surrounding the first and second nanosheet channel structures is formed. The first gate electrode layer is also formed over the third and fourth nanosheet channel structures.FIG.20illustrates cross-sectional view2000of some embodiments corresponding to act2710. At act2712, the first and second nanosheet channel structures are covered with a masking structure. At act2714, the first gate electrode layer is removed from the third and fourth nanosheet channel structures.FIG.21illustrates cross-sectional view2100of some embodiments corresponding to acts2712and2714. At act2716, the dummy masking structure is removed from between the third and fourth nanosheet channel structures and from between the third nanosheet channel structure and the substrate.FIG.22illustrates cross-sectional view2200of some embodiments corresponding to act2716. At act2718, the masking structure is removed. At act2720, a second gate electrode layer is formed that surrounds the third and fourth nanosheet channel structure and over the first gate electrode layer.FIG.23illustrates cross-sectional view2300of some embodiments corresponding to act2720. Therefore, the present disclosure relates to a method of forming a first NSFET having a first gate electrode structure laterally beside a second NSFET having a second gate electrode structure using a dummy masking structure to increase device density while still maintaining reliability of the first and second NSFETs. Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising: a first nanosheet field effect transistor (NSFET) arranged over a substrate and having a first threshold voltage and comprising: a first gate electrode layer extending from a first source/drain region to a second source/drain region, and first nanosheet channel structures embedded in the first gate electrode layer and also extending from the first source/drain region to the second source/drain region; a second NSFET arranged laterally beside the first NSFET and over the substrate, having a second threshold voltage different from the first threshold voltage, and comprising: a second gate electrode layer extending from a third source/drain region to a fourth source/drain region, and second nanosheet channel structures embedded in the second gate electrode layer and also extending from the third source/drain region to the fourth source/drain region; and a third NSFET arranged laterally beside the second NSFET and over the substrate, having a third threshold voltage different from the second threshold voltage, and comprising: a third gate electrode layer extending from a fifth source/drain region to a sixth source/drain region, and third nanosheet channel structures embedded in the third gate electrode layer and also extending from the fifth source/drain region to the sixth source/drain region. In other embodiments, the present disclosure relates to an integrated chip comprising: a first nanosheet field effect transistor (NSFET) comprising: a first nanosheet channel structure arranged over a substrate; a second nanosheet channel structure arranged directly over the first nanosheet channel structure and extending in parallel from a first source/drain region to a second source/drain region; and a first gate electrode layer continuously surrounding the first and second nanosheet channel structures and arranged directly between the first and second nanosheet channel structures; a second NSFET comprising: a third nanosheet channel structure arranged over the substrate; a fourth nanosheet channel structure arranged directly over the third nanosheet channel structure and extending in parallel from a third source/drain region to a fourth source/drain region; and a second gate electrode layer continuously surrounding the third and fourth nanosheet channel structures and arranged directly between the third and fourth nanosheet channel structures, wherein the second gate electrode layer comprises a different material than the second gate electrode layer; and a third NSFET comprising: a fifth nanosheet channel structure arranged over the substrate; a sixth nanosheet channel structure arranged directly over the fifth nanosheet channel structure and extending in parallel from a fifth source/drain region to a sixth source/drain region; and a third gate electrode layer continuously surrounding the fifth and sixth nanosheet channel structures and arranged directly between the fifth and sixth nanosheet channel structures, wherein the third gate electrode layer comprises a different material than the first gate electrode layer and the second gate electrode layer. In yet other embodiments, the present disclosure relates to a method of forming an integrated chip comprising: forming a first nanosheet channel structure and a second nanosheet channel structure over a substrate and extending in parallel between first and second source/drain regions, wherein the second nanosheet channel structure is arranged directly over the first nanosheet channel structure; forming a third nanosheet channel structure and a fourth nanosheet channel structure over the substrate, arranged laterally beside the first nanosheet channel structure and the second nanosheet channel structure, and extending in parallel between third and fourth source/drain regions, wherein the fourth nanosheet channel structure is arranged directly over the third nanosheet channel structure; forming a dummy masking layer over and between the first, second, third, and fourth nanosheet channel structures; removing portions of the dummy masking layer from the first, second, third, and fourth nanosheet channel structures to form a dummy masking structure is arranged directly between the third nanosheet channel structure and the fourth nanosheet channel structure and directly between the third nanosheet channel structure and the substrate; forming a first gate electrode layer surrounding the first and second nanosheet channel structures and over the third and fourth nanosheet channel structures; covering the first and second nanosheet channel structures with a masking structure; removing the first gate electrode layer from the third and fourth nanosheet channel structures; removing the dummy masking structure; removing the masking structure; and forming a second gate electrode layer surrounding the third and fourth nanosheet channel structures. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 84,314 |
11862634 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure. FIGS.1-8B and10A-12Bare perspective views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.FIG.9is a cross-sectional view taken along a cross-sectional line ofFIG.8AorFIG.8B.FIG.13Ais a cross-sectional view taken along a cross-sectional line ofFIG.12A.FIG.13Bis a cross-sectional view taken along a cross-sectional line ofFIG.12B. Reference is made toFIGS.1,2A and2B. The semiconductor device10includes a substrate100and device features can be formed on, above or over the substrate100. The fin activation area10ais referred as a fin activation area with plural fins, e.g., in SRAM, random logic or input/output area, and the first fin activation area10bis referred as a fin activation area with a single fin, e.g., stand cell. The substrate100may be a bulk silicon substrate. Alternatively, the substrate100may include an elementary semiconductor, such as silicon (Si) or germanium (Ge) in a crystalline structure; a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); or combinations thereof. Possible substrates100also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate100, in a P-well structure, in an N-well structure, in a dual-well structure, and/or using a raised structure. The substrate100may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device and regions configured for a P-type metal-oxide-semiconductor transistor device. A series of nano epitaxy layers104and sacrificial nano epitaxy layers102are alternately epitaxially grown on the substrate100for fin structure to form a nano epitaxy layer stack. In some embodiments, the nano epitaxy layer104may be nano epitaxy Silicon (Si) layer, and the present disclosure is not limited in this respect. In some embodiments, the sacrificial nano epitaxy layer102may be a nano epitaxy Silicon (Si)-Germanium (Ge) layer, and the present disclosure is not limited in this respect. In some embodiments, the nano epitaxy layer104may have a thickness ranging from about 3 nm to about 7 nm, and the present disclosure is not limited in this respect. In some embodiments, the sacrificial nano epitaxy layer102may have a thickness ranging from about 2 nm to about 10 nm, and the present disclosure is not limited in this respect. In some embodiments, a pad oxide layer106, a pad nitride layer108and a mask layer110are deposited over the alternately-formed nano epitaxy layers104and sacrificial nano epitaxy layers102. In some embodiments, the pad oxide layer106may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer106may act as an adhesion layer between the nano epitaxy layers (102,104) and the pad nitride layer108. In some embodiments, the pad nitride layer108may be formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the mask layer110may be formed of thick silicon oxide for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer110is used as a hard mask during following processes, such as photolithography. Reference is made toFIGS.2A and2Bagain. The pad oxide layer106, the pad nitride layer108and the mask layer110are patterned to form mask structures with uniform widths both in the fin activation area10aand in the fin activation area10b, e.g., each combination of the pad oxide layer106a, the pad nitride layer108aand the mask layer110ain the fin activation area10ahas a uniform width that is substantially equal to that of the combination of the pad oxide layer106b, the pad nitride layer108band the mask layer110bin the fin activation area10b. Reference is made toFIGS.3A and3B. A spacer cap layer112is conformally formed over the patterned pad oxide layer106a, pad nitride layer108aand mask layer110ain the fin activation area10aand over the patterned pad oxide layer106b, pad nitride layer108band mask layer110bin the fin activation area10b. In some embodiments, the spacer cap layer112may be formed of thin silicon oxide for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Reference is made toFIGS.4A and4B. A photo resist layer113is deposited over the fin activation area10bas a mask structure and an etching process is performed both on the fin activation area10aand in the fin activation area10b. After the etching process, the spacer cap layer112in the fin activation area10ais removed while the spacer cap layer112in the fin activation area10bis protected by the photo resist layer113and not removed. In some embodiments, the photo resist layer113and the remained spacer cap layer112may have substantially the same width in the fin activation area10b. In some embodiments, the photo resist layer113may be removed before fin etching processes. In some embodiments, a portion of the remained spacer cap layer112in contact with the top sacrificial nano epitaxy layer102may be removed by a selective etching (i.e., etch the remained spacer cap layer112in the fin activation area10band not etch the top sacrificial nano epitaxy layer102in the fin activation area10a) before fin etching processes such that the spacer cap layer112is remained merely upon sidewalls of the patterned pad oxide layer106, pad nitride layer108and mask layer110as part of the mask structure when fin etching processes are performed. Reference is made toFIGS.5A and5B. One or more etching process(es) are performed to form multiple fin structures105ain a lengthwise direction130in the fin activation area10aand single fin structure105bin a lengthwise direction130in the fin activation area10b. Each fin structure105aincludes a base fin101aprotruding from the semiconductor substrate100aand multiple patterned nano epitaxy layers104aand sacrificial nano epitaxy layers102astacked above the base fin101a. Each fin structure105bincludes a base fin101bprotruding from the semiconductor substrate100aand multiple alternate nano epitaxy layers104band sacrificial nano epitaxy layers102bstacked above the base fin101b. In some embodiments, the fin structures105amay be etched by capping the patterned pad oxide layer106, pad nitride layer108and mask layer110on top of the fin structures105ain the fin activation area10a. And, the fin structure105bmay be etched by capping the patterned pad oxide layer106, pad nitride layer108, and mask layer110as well as the remained spacer cap layer112on top of the fin structures105bin the fin activation area10b. The remained spacer cap layer112is located on used to broaden a width of the mask layer in order to obtain the relatively wide fin structure105bduring the fin patterning process. After fin patterning process, the fin structures105aare formed under the patterned pad oxide layer106, pad nitride layer108and mask layer110in the fin activation area10awhile the fin structure105bis formed under the patterned pad oxide layer106, pad nitride layer108, and mask layer110as well as the remained spacer cap layer112in the fin activation area10b. In some embodiments, the etching process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. For example, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Fin structures are formed over the substrate100awithin different functional regions, e.g., a LOGIC region and/or a memory region. In some embodiments, the fin structures may be of the same type or of different types. For example, some of the fin structures are n-type semiconductor fins, and the others of the fin structures are p-type semiconductor fins, and the present disclosure is not limited in this respect. In some embodiments, each fin structure105ain the fin activation area10ais formed with a uniform width (W1) that is substantially equal to a uniform width (W1) of the other fin structure105ain the fin activation area10a. In some embodiments, the single fin structure105bin the fin activation area10bis formed with a uniform width (W2) that is greater than that (W1) of the fin structure105ain the fin activation area10a. The uniform width (W1) and width (W2) are measured in a direction that is perpendicular to the lengthwise direction130. Reference is made toFIGS.6A and6B. One or more etching process(es) are performed to remove the pad oxide layer106and pad nitride layer108on the fin structure105ain the fin activation area10aand to remove the remained pad oxide layer106b, pad nitride layer108band the spacer cap layer112bon the fin structure105bin the fin activation area10b. A field oxide layer114is formed to fill into trenches both in the fin activation area10aand the fin activation area10bto form a shallow trench isolation (STI). In some embodiments, at least the base fin101aof each fin structure105ais embedded within the field oxide layer114and at least the base fin101bof each fin structure105bis embedded within the field oxide layer114. In some embodiments, at least the multiple alternate nano epitaxy layers104aand sacrificial nano epitaxy layers102aof each fin structure105amay be located above the STI (i.e., the field oxide layer114) and at least the multiple alternate nano epitaxy layers104band sacrificial nano epitaxy layers102bof each fin structure105bmay be located above the STI (i.e., the field oxide layer114). Reference is made toFIGS.7A and7B. A thin oxide layer155is formed over the STI (i.e., the field oxide layer114) and the fin structures105aand105b. The oxide layer155may act as gate dielectric in later process. Plural dummy gates are formed over the oxide layer155, in which the dummy gate180acrosses the plural fin structures105ain a direction140, and the dummy gate180bcrosses the single fin structures105bin a direction140. In some embodiments, the direction140may be perpendicular to the lengthwise direction130. In some embodiments, mask layers182and184are formed over the dummy gates180aand180b. The mask layers182and184acts as a hard mask during the patterning process of the dummy gates180aand180band may act as a hard mask during the following processes, such as etching. In some embodiments, the mask layers182and184may include silicon oxide, silicon nitride and/or silicon oxynitride. In some embodiments, the dummy gates180aand180bmay include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gates may be doped poly-silicon with uniform or non-uniform doping. In some embodiments, the dummy gates180aand180bmay be formed by, for example, forming a dummy gate material layer over the oxide layer155. Patterned masks, such as mask layers182and184, are formed over the dummy gate material layer. Then, the dummy gate material layer may be patterned using one or more etching processes, such as one or more dry plasma etching processes or one or more wet etching processes. During the etching process, the patterned mask may act as an etching mask. At least one parameter, such as etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate, of the patterning (or etching) recipe can be tuned. For example, dry etching process, such as plasma etching, may be used to etch the dummy gate material layer and the oxide layer155until the fin structures105aand105bare exposed. Reference is made toFIGS.8A and8B. Gate spacer structures including plural gate spacers190on opposite sidewalls of the dummy gates180aand180bare formed. In some embodiments, at least one of the gate spacers190includes single or multiple layers. The gate spacers190can be formed by blanket depositing one or more dielectric layer(s) on the previously formed structure. The dielectric layer(s) may include silicon nitride (SiN), oxynitride, silicion carbon (SiC), silicon oxynitride (SiON), oxide, and the like. The gate spacers190may be formed by methods such as CVD, plasma enhanced CVD, sputter, or the like. The gate spacers190may then be patterned, such as by one or more etch processes to remove horizontal portions of the gate spacers190from the horizontal surfaces of the structure. The oxide layer155exposed from the dummy gates180aand180band the gate spacers190are removed by suitable process, such as etching. The remained portions of the oxide layer155are disposed under the dummy gates180aand180band the gate spacers190. Thus, the remained portions of the oxide layer155may be referred to as gate dielectric. Also, the dummy gate180aand180band the remained oxide layer155may collectively be referred to as a dummy gate structure. In some embodiments, the fin structures105aexposed from the dummy gates180aand the gate spacers190are removed by suitable process, such as etching, while the fin structures105bexposed from the dummy gates180band the gate spacers190are removed by suitable process, such as etching. Plural source/drain features200are respectively formed over the exposed base fins101aand101bof the substrate100. In some embodiments, the wider source/drain features200are respectively formed over the exposed base fins101a, in which each base fin101ais equipped with a relatively narrow width, i.e., compared with the base fin101b. In some embodiments, the thinner source/drain features200are respectively formed over the exposed base fin101bthat is equipped with a relatively large width, i.e., compared with the base fin101a. In some embodiments, the source/drain features200may be epitaxy structures, and may also be referred to as epitaxy features200. The source/drain features200may be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, and/or other suitable features can be formed in a crystalline state on the semiconductor base fins101aand101b. In some embodiments, the source/drain features200may be cladding over the semiconductor base fins101aand101b. In some embodiments, lattice constants of the source/drain features200are different from lattice constants of the semiconductor base fins101aand101b, such that channels in the semiconductor base fins101aand101bare strained or stressed to enable carrier mobility of the semiconductor device and enhance the device performance. In some embodiments, the source/drain features200may include semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), silicon carbide (SiC), or gallium arsenide phosphide (GaAsP). The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fins110(e.g., silicon). The source/drain features200may be in-situ doped. The doping species include P-type dopants, such as boron or BF2; N-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain features200are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the source/drain features200. One or more annealing processes may be performed to activate the source/drain features200. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes. In some embodiments, the source/drain features200over the semiconductor base fins101aand101bmay include the same doping-type, and the source/drain feature200over one of the semiconductor base fins101aand101bmay include different doping-types. For example, some source/drain features200may be n-type, and the other source/drain features200may be p-type, and vise versa. Reference is made toFIG.9, which is a cross-sectional view taken along a cross-sectional line ofFIG.8AorFIG.8B. In some embodiments, an inner spacer layer192is formed between the source/drain features200and the sacrificial nano epitaxy layers102a/102b. The inner spacer layer192may be formed after removing the fin structures105aexposed from the dummy gates180aand the gate spacers190. The inner spacer layer192may be formed of dielectric materials by methods such as CVD, plasma enhanced CVD, sputter, or the like. The nano epitaxy layers104a/104binterconnects the source/drain features200. Reference is made toFIGS.10A and10B. An etching stop layer215and interlayer dielectric220is formed over the source/drain features200. Then, a CMP process is performed to remove the excessive interlayer dielectric220, and the mask layers182and184(referring toFIGS.11A and11B) until the dummy gates180aand180bare exposed. In some embodiments, the interlayer dielectric220may include silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon germanium, or combinations thereof. The interlayer dielectric220may be formed by a suitable technique, such as CVD, ALD and spin-on coating. In some embodiments, air gaps may be created in the interlayer dielectric220. Then, a replacement gate (RPG) process scheme is employed. The dummy gates180aand180bare replaced with metal gates. For example, the dummy gates180aand180bare removed to from a plurality of gate trenches and expose the multiple alternate nano epitaxy layers and sacrificial nano epitaxy layers. The dummy gate gates180aand180bare removed by a selective etch process, including a selective wet etch or a selective dry etch, and carries a substantially vertical profile of the gate spacers190. Reference is made toFIGS.11A and11B. The sacrificial nano epitaxy layers102a/102bare removed by a selective etch process, including a selective wet etch or a selective dry etch, and the remained nano epitaxy layers104a/104bforms nano sheet fins or nano wire fins that are spaced from each other. That is, the nano epitaxy layers104a/104bmay be referred as nano sheet or nano wire104a/104b. Reference is made toFIGS.12A to13B.FIG.13Ais a cross-sectional view taken along a cross-sectional line ofFIG.12A.FIG.13Bis a cross-sectional view taken along a cross-sectional line ofFIG.12B. The gate structures230are formed respectively in the gate trenches to surround or wrap around the nano sheet fins or nano wire104a/104bsimultaneously. The gate structures230include an interfacial layer236, gate dielectrics232formed over the interfacial layer236, and gate metals234formed over the gate dielectrics232. The gate dielectrics232, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The gate metals234may include a metal, metal alloy, and/or metal silicide. In some embodiments, the gate structures230extend in a direction140crossing the direction130in which the nano sheet fins or nano wire104a/104bextend. The direction140may be perpendicular to the direction130. The gate structures230fill into the gate trenches to surround or wrap the nano sheet fins or nano wire104a/104brespectively. Reference is made toFIGS.13A to13B. In some embodiments, a quantity of the nano wires104aof each fin structure105ais equal to that of the nano wires104bof the fin structure105b. Each fin structure105aincludes a base fin101aand plural nano wires104alocated vertically aligned with the base fin101a. The nano wires104aare spaced from the base fin101aand from each other. Each fin structure105bincludes a base fin101band plural nano wires104blocated vertically aligned with the base fin101a. The nano wires104bare spaced from the base fin101band from each other. In some embodiments, the nano wires104aof at least one fin structure105ahave a uniform thickness (T) that is substantially equal to a uniform thickness (T) of the nano wires104bof at least one fin structure105b. The thickness (T) of the nano wires104aor104bis measured in a direction150that is perpendicular to the direction140. In some embodiments, a uniform pitch (S) between adjacent nano wires104aof at least one fin structure105ais substantially equal to a uniform pitch (S) between adjacent nano wires104bof at least one fin structure105b. The uniform pitch (S) of the fin structures105a/105bis measured in a direction150that is perpendicular to the direction140. In some embodiments, the nano wires104aof at least one fin structure105ahave a uniform width (D1) that is smaller than a uniform width (D2) of the nano wires104bof at least one fin structure105b. The widths (D1or D2) of the nano wires104aor104bare measured in the direction140. In some embodiments, the nano wires104aof at least one fin structure105ahave a uniform width (D1) ranging from about 3 nm to about 7 nm. In some embodiments, the nano wires104bof at least one fin structure105bhave a uniform width (D2) ranging from about 8 nm to about 16 nm. In some embodiments, the width (D2) of the nano wire104bmay be two times greater than the width (D1) of the nano wire104a, but may not be greater than three times the width (D1) of the nano wire104abecause the gate structure may not have enough width to warp around the nano wire104bwith such width. In some embodiments, the uniform pitch (S) between adjacent nano wires104aor between adjacent nano wires104branges from about 2 nm to about 10 nm. In some embodiments, the uniform thickness (T) of each nano wire104aor each nano wire104branges from about 3 nm to about 7 nm. In some embodiments, a quantity of the nano wires104aof each fin structure105ais from2to10and a quantity of the nano wires104bof each fin structure105bis from2to10. In some embodiments, each nano wire104aor104ais wrapped by the interfacial layer236, the gate dielectric232and the gate metal234. In some embodiments, the gate metals234included in the gate structures230may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide. For example, the gate metals234may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The work function layer(s) may be deposited by CVD, PVD, electro-plating and/or other suitable process. In some embodiments, the interfacial layer236may include a dielectric material such as silicon oxide (SiO2), HfSiO, and/or silicon oxynitride (SiON). The interfacial layer236may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. The gate dielectrics232may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the gate dielectric212may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The gate dielectrics232may be formed by ALD, PVD, CVD, oxidation, and/or other suitable methods. According to aforementioned embodiments, a semiconductor device includes a first fin structure and a second fin structure located over a substrate. The first fin structure has a single stack of first nano wires or sheets with larger width or diameter and the second fin structure has multiple stacks of second nano wires or sheets with smaller width or diameter for design flexibility. Because the first and second fin structures are concurrently formed, the single stack of first nano wires or sheets and multiple stacks of second nano wires or sheets all have equal sheet numbers and substantially the same pitch and thickness. With such configuration, the single stack of first nano wires or sheets with larger width or diameter may obtain speed gain and the multiple stacks of second nano wires or sheets need smaller width or diameter to aggress fin pitch shrinkage for even scaled down process. Embodiments for manufacturing semiconductor structures are provided. The method may include forming a first mask structure and a second mask structure over a semiconductor stack, and the second mask structure may have spacers formed on its sidewalls. The semiconductor stack may be patterned through the first mask structure, the second mask structure, and the spacers to form a first fin structure under the first mask structure and the second fin structure under the second mask structure and the spacers. That is, the fin structure with different widths may be formed concurrently and the design flexibility may be increased. An embodiment of the present disclosure is a semiconductor device having a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires located above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires located above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire. An embodiment of the present disclosure is that each first nano wire has a first thickness substantially equal to a second thickness of each second nano wire. An embodiment of the present disclosure is that a quantity of the first nano wires is equal to that of the second nano wires. An embodiment of the present disclosure is that a first pitch between immediately-adjacent two of the first nano wires is substantially equal to a second pitch between immediately-adjacent two of the second nano wires. An embodiment of the present disclosure is that the first and second fins and the at least two first and second nano wires are arranged in a first direction, and the first and second widths are measured in a second direction that is perpendicular to the first direction. An embodiment of the present disclosure is the semiconductor device further including a first gate structure extending in a third direction crossing the first direction and surrounding the at least two first nano wires. An embodiment of the present disclosure is the semiconductor device further including a second gate structure extending in a third direction crossing the first direction and surrounding the at least two second nano wires. An embodiment of the present disclosure is the semiconductor device further including a pair of first epitaxy structures, and the at least two first nano wires interconnect the pair of first epitaxy structures. An embodiment of the present disclosure is the semiconductor device further including a pair of second epitaxy structures, and the at least two second nano wires interconnect the pair of second epitaxy structures. An embodiment of the present disclosure is that the at least two first nano wires are spaced from the first fin, and the at least two second nano wires are spaced from the second fin. An embodiment of the present disclosure is a semiconductor device having semiconductor substrate, a first fin structure, a plurality of second fin structures, a first gate structure and a second gate structure. The first fin structure includes a first fin and at least two first nano wires arranged in a first direction, and the first fin protrudes from the semiconductor substrate. Each second fin structure includes a second fin and at least two second nano wires arranged in the first direction, and the second fin protrudes from the semiconductor substrate. The first gate structure extends in a second direction crossing the first direction and surrounding the at least two first nano wires of the first fin structure. The second gate structure extends in the second direction crossing the first direction and surrounding the second nano wires of the second fin structures. Each first nano wire has a first width greater than a second width of each second nano wire. An embodiment of the present disclosure is that the at least two first nano wires have a uniform first thickness. An embodiment of the present disclosure is that the at least two second nano wires have a uniform second thickness that is substantially equal to the uniform first thickness. An embodiment of the present disclosure is that the first and second widths are measured in the second direction. An embodiment of the present disclosure is that a first pitch between any immediately-adjacent two of the first nano wires is uniform. An embodiment of the present disclosure is that a second pitch between any immediately-adjacent two of the second nano wires is uniform and is substantially equal to the first pitch. An embodiment of the present disclosure is that the at least two first nano wires are spaced from each other, and the at least two second nano wires are spaced from each other. An embodiment of the present disclosure is a method for manufacturing a semiconductor device including epitaxially growing a sacrificial layer over a substrate; epitaxially growing a semiconductor layer over the sacrificial layer; depositing a mask layer over the semiconductor layer; patterning the mask layer to form a first mask structure and a second mask structure over the semiconductor layer; forming a spacer cap layer over the first mask structure and the second mask structure; etching the spacer cap layer over the first mask structure, wherein the etched spacer cap layer remains on a sidewall of the second mask structure; etching the semiconductor layer and the sacrificial layer exposed by the first mask structure, the second mask structure, and the etched spacer cap layer to form a first fin under the first mask structure and a second fin under the second mask structure and the etched spacer cap layer, wherein the second fin is wider than the first fin; etching the sacrificial layer in the first fin and the second fin; and forming a first gate structure wrapping around the semiconductor layer in the first fin and forming a second gate structure wrapping around the semiconductor layer in the second fin. An embodiment of the present disclosure is the method further including patterning the mask layer is performed such that a third mask structure is formed over the semiconductor layer and adjacent the first mask structure, wherein the first and third mask structures have substantially the same width. An embodiment of the present disclosure is the method further including forming the first gate structure and forming the second gate structure are performed simultaneously. In some embodiments, methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures. The method further includes forming a first gate structure around the first nanostructures and forming a second gate structure around the second nanostructures. In some embodiments, methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers over a substrate and forming a first mask structure over a first region of the substrate and a second mask structure over a second region of the substrate. The method further includes forming a spacer cap layer covering the first region and the second region of the substrate and removing the spacer cap layer over the first region to expose the first mask structure. The method further includes etching the spacer cap layer over the second region to form spacers on sidewalls of the second mask structure and etching the first epitaxy layers and second epitaxy layers not covered by the first mask, the second mask, and the spacers to form a first fin structure under the first mask and a second fin structure under the second mask and the spacers. The method further includes removing the first epitaxy layers in the first fin structure to form first gaps between the second epitaxy layers in the first fin structure and removing the first epitaxy layers in the second fin structure to form second gaps between the second epitaxy layers in the second fin structure. The method further includes forming a first gate structure in the first gaps to form a first transistor in the first region and forming a second gate structure in the second gaps to form a second transistor in the second region. In some embodiments, methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming a first spacer on a first sidewall of the second mask structure and a second spacer on a second sidewall of the second mask structure and patterning the semiconductor stack through the first mask structure to form a first fin structure so that the first fin structure has a first width substantially equal to a width of the first mask structure. The method further includes patterning the semiconductor stack through the second mask structure, the first spacer, and the second spacer to form a second fin structure so that the second fin structure has a second width substantially equal to a sum of widths of the second mask structure, the first spacer, and the second spacer. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures and forming a first gate structure wrapping around the first nanostructures. The method further includes forming a second gate structure wrapping around the second nano structures. FIGS.14A-1,14B-1,14C-1,14D-1,14E-1,14F-1,14G-1,14H-1,14I-1,14J-1,14K-1, and14L-1are perspective views of a method for manufacturing a first device region20in a semiconductor structure300at various stages in accordance with some embodiments of the present disclosure.FIGS.14A-2,14B-2,14C-2,14D-2,14E-2,14F-2,14G-2,14H-2,14I-2,14J-2,14K-2, and14L-2are perspective views of a method for manufacturing a second device region20′ in the semiconductor structure300at various stages in accordance with some embodiments of the present disclosure. The process and materials used in forming the semiconductor structure300may be similar to, or the same as, those used in forming the structures shown inFIGS.1to13B, which are described above and therefore not repeated herein. More specifically, similar elements in these figures are designated by the same numerals and can include the same or similar materials, and they can be formed by following the same or similar steps; therefore, such details are omitted in the interest of brevity. Similar toFIG.1, a series of nano epitaxy layers104and sacrificial nano epitaxy layers102are alternately grown on the substrate100to form a semiconductor stack, and the pad oxide layer106, the pad nitride layer108, and the mask layer110are deposited over the semiconductor stack in both the first device region20and the second device region20′, as shown inFIGS.14A-1and14A-2in accordance with some embodiments. In some embodiments, the number of sacrificial nano epitaxy layers102is the same as the number of nano epitaxy layers104. In some embodiments, the number of nano epitaxy layers104is in a range from about 2 to about 10. In some embodiments, each of the sacrificial nano epitaxy layers102has the same thickness and each of the nano epitaxy layers104has the same thickness. In some embodiments, the sacrificial nano epitaxy layers102and the nano epitaxy layers104have different thicknesses. In some embodiments, each of the sacrificial nano epitaxy layers102has a thickness in a range from about 2 nm to about 10 nm. In some embodiments, each of the nano epitaxy layers104has a thickness in a range from about 3 nm to about 7 nm. Next, the pad oxide layer106, the pad nitride layer108, and the mask layer110are patterned to form a first mask structure210aand a second mask structure210bin the first device region20and a third mask structure210cand a fourth mask structure210din the second device region20′, as shown inFIGS.14B-1and14B-2in accordance with some embodiments. In some embodiments, the first mask structure210a, the second mask structure210b, the third mask structure210c, and the fourth mask structure210dhave substantially the same width W. In some embodiments, the width W is in a range from about 3 nm to about 7 nm. In some embodiments, the distance D3between the first mask structure210aand the second mask structure210bis shorter than the distance D4between the third mask structure210cand the fourth mask structure210d. The distance and the width of the mask structures may affect the performance of the resulting semiconductor structure300and the details will be described afterwards. Next, the spacer cap layer112is conformally formed over the first mask structure210a, the second mask structure210b, the third mask structure210c, and the fourth mask structure210dand over the top surface of the semiconductor stack in both the first device region20and the second device region20′, as shown inFIGS.14C-1and14C-2in accordance with some embodiments. After the spacer cap layer112is formed, the photo resist layer113is formed over the second device region20′ as a mask structure, while exposing the first device region20in accordance with some embodiments. Next, the spacer cap layer112in the first device region20that is not covered by the photo resist layer113is removed to expose the first mask structure210aand the second mask structure210b, as shown inFIGS.14D-1and14D-2in accordance with some embodiments. In some embodiments, the spacer cap layer112in the first device region20is removed by performing an etching process. Afterwards, the photo resist layer113over the second device region20′ is removed and the remaining spacer cap layer112over the second device region20′ is etched, so that third spacers222care formed on the sidewalls of the third mask structure210cto form a widened third mask structure210c′ and fourth spacers222dare formed on the sidewalls of the fourth mask structure210dto form a widened fourth mask structure210d′, as shown inFIGS.14E-1and14E-2in accordance with some embodiments. In some embodiments, the mask layers110are removed. In some embodiments, the width W3of the widened third mask structure210c′ (i.e. the sum of the widths of the third mask structure210cand the third spacers222c) is substantially equal to the width W4of the widened fourth mask structure210d′ (i.e. the sum of the widths of the fourth mask structure210dand the fourth spacers222d). In some embodiments, the width W3of the widened third mask structure210c′ and the width W4of the widened fourth mask structure210d′ are in a range from about 8 nm to about 16 nm. In some embodiments, the ratio of the width W3of the widened third mask structure210c′ (or the width W4of the widened fourth mask structure210d′) to the width W of the first mask structure210a(or the width W of the second mask structure210b) is in a range from about 1.14 to about 5.3. In some embodiments, the distance D3between the first mask structure210aand the second mask structure210bis shorter than the distance D5between the widened third mask structure210c′ and the widened fourth mask structure210d′. In some embodiments, the ratio of the distance D5to the distance D3is in a range from about 1.15 to about 2. As described previously, the distance and the width of the mask structures may affect the performance of the resulting semiconductor structure300and the details will be described afterwards. After the third spacers222cand the fourth spacers222dare formed, the semiconductor stack and the substrate100are patterned using the first mask structure210a, the second mask structure210b, the widened third mask structure210c′, and the widened fourth mask structure210d′ to form a first fin structure205a, a second fin structure205b, a third fin structure205c, and a fourth fin structure205drespectively, as shown inFIGS.14E-1and14E-2in accordance with some embodiments. More specifically, the semiconductor stack and the substrate100not covered by the first mask structure210a, the second mask structure210b, the widened third mask structure210c′, and the widened fourth mask structure210d′ are etched to form recesses in accordance with some embodiments. As shown inFIG.14E-1, the sidewalls of the first mask structure210aare substantially aligned with the sidewalls of the first fin structures205a, and the sidewalls of the second mask structure210bare substantially aligned with the sidewalls of the second fin structures205bin accordance with some embodiments. In some embodiments, the first fin structure210aand the second fin structure210balso have the width W, and the distance between the first fin structure210aand the second fin structure210bis substantially equal to the distance D3. Similarly, the sidewalls of the widened third mask structure210c′ are substantially aligned with the sidewalls of the third fin structures205c, and the sidewalls of the widened fourth mask structure210d′ are substantially aligned with the sidewalls of the fourth fin structures205din accordance with some embodiments. In some embodiments, the third fin structure210cand the fourth fin structure210dalso have the width W3and the width W4respectively, and the distance between the third fin structure210cand the fourth fin structure210dis substantially equal to the distance D4. Next, the first mask structure210a, the second mask structure210b, the widened third mask structure210c′, and the widened fourth mask structure210d′ are removed, and the field oxide layer114is formed around the first fin structure205a, the second fin structure205b, the third fin structure205c, and the fourth fin structure205dto form a shallow trench isolation (STI), as shown inFIGS.14F-1and14F-2in accordance with some embodiments. After the field oxide layer114is formed, the thin oxide layer155is formed over the field oxide layer114and over the first fin structure205a, the second fin structure205b, the third fin structure205c, and the fourth fin structure205din accordance with some embodiments. Afterwards, a dummy gate280is formed across the first fin structure205aand the second fin structure205band a dummy gate280′ is formed across the third fin structure205cand the fourth fin structure205d, as shown inFIGS.14G-1and14G-2in accordance with some embodiments. In some embodiments, the mask layers182and184are formed over the dummy gates280and280′. Processes and materials for forming the dummy gates280and280′ may be similar to, or the same as, those for forming the dummy gates180aand180bdescribed above and are not repeated herein. Next, the gate spacers190are formed on the sidewalls of the dummy gates280and280′, and the oxide layer155exposed from the dummy gates280and280′ and the gate spacers190are removed, as shown inFIGS.14H-1and14H-2in accordance with some embodiments. Afterwards, inner spacers and source/drain features are formed in the first fin structure205a, the second fin structure205b, the third fin structure205c, and the fourth fin structure205d, as shown inFIGS.14H-1and14H-2in accordance with some embodiments. More specifically, the first fin structure205aand the second fin structure205bnot covered by the dummy gates280and the spacers190are recessed to form first recesses in the first fin structure205aand second recesses in the second fin structure205b, and the inner spacers (not shown, similar to the inner spacers192shown inFIG.9), first source/drain features200a, and second source/drain features200bare formed in the first recesses and the second recesses in accordance with some embodiments. In addition, the neighboring first source/drain feature200aand the second source/drain feature200bare merged into a large source/drain feature since the first fin structure205aand the second fin structure205bare relatively close to each other, as shown inFIG.14H-1in accordance with some embodiments. Similarly, the third fin structure205cand the fourth fin structure205dnot covered by the dummy gates280′ and the spacers190are recessed to form third recesses in the third fin structure205cand fourth recesses in the fourth fin structure205d, and the inner spacers (not shown, similar to the inner spacers192shown inFIG.9), third source/drain features200c, and fourth source/drain features200dare formed in the third recesses and the fourth recesses in accordance with some embodiments. In addition, the neighboring third source/drain feature200cis not in contact with the fourth source/drain feature200dsince the third fin structure205cand the fourth fin structure205dare relatively far from each other, as shown inFIG.14H-2in accordance with some embodiments. Processes and materials for forming the first, second, third, and fourth source/drain features200a,200b,200c, and200dmay be similar to, or the same as, those for forming the source/drain features200described above and are not repeated herein. Since the first source/drain feature200aand the second source/drain feature200bare merged to form a merged source/drain feature, the merged source/drain feature is wider than both the third source/drain feature200cand the fourth source/drain feature200d, although the third fin structure205cand the fourth fin structure205dare wider than the first fin structure205aand the second fin structure205bin accordance with some embodiments. In some embodiments, an air gap is formed between the merged source/drain feature and the isolation feature114. After the inner spacers and source/drain features are formed, the etching stop layer215and the interlayer dielectric220are formed over the first, second, third, and fourth source/drain features200a,200b,200c, and200d, as shown inFIGS.14I-1and14I-2in accordance with some embodiments. A CMP process may be performed to remove the excessive interlayer dielectric220and the mask layers182and184. Next, the dummy gates280and280′ are removed to from gate trenches and the multiple alternatively stacked nano epitaxy layers104and sacrificial nano epitaxy layers102are exposed, as shown inFIGS.14I-1and14I-2in accordance with some embodiments. After the dummy gates280and280′ are removed, the sacrificial nano epitaxy layers102of the first fin structure205a, the second fin structure205b, the third fin structure205c, and the fourth fin structure205dexposed by the gate trenches are removed to form first nanostructures204a, second nanostructures204b, third nanostructures204c, and fourth nanostructures204d, as shown inFIGS.14J-1and14J-2in accordance with some embodiments. After the first nanostructures204a, the second nanostructures204b, the third nanostructures204c, and the fourth nanostructures204dare formed, the gate structure230is formed in the first device region20and a gate structure230′ is formed in the second device region20′, as shown inFIGS.14K-1and14K-2in accordance with some embodiments. More specifically, the gate structure230wraps around the first nanostructures204aand the second nanostructures204b, and the gate structure230′ wraps around the third nanostructures204cand the fourth nanostructures204din accordance with some embodiments. FIG.15-1illustrates a cross-sectional view of the semiconductor structure300taken along a cross-sectional line A-A1shown inFIG.14K-1in accordance with some embodiments.FIG.15-2illustrates a cross-sectional view of the semiconductor structure300taken along a cross-sectional line A′-A1′ shown inFIG.14K-2in accordance with some embodiments.FIG.16-1illustrates a cross-sectional view of the semiconductor structure300taken along a cross-sectional line B-B1shown inFIG.14K-1in accordance with some embodiments.FIG.16-2illustrates a cross-sectional view of the semiconductor structure300taken along a cross-sectional line B′-B1′ shown inFIG.14K-2in accordance with some embodiments.FIG.17-1illustrates a cross-sectional view of the semiconductor structure300taken along a cross-sectional line C-C1shown inFIG.14K-1in accordance with some embodiments.FIG.17-2illustrates a cross-sectional view of the semiconductor structure300taken along a cross-sectional line C′-C1′ shown inFIG.14K-2in accordance with some embodiments. In some embodiments, both the gate structures230and230′ include an interfacial layer236, gate dielectrics232formed over the interfacial layer236, and gate metals234formed over the gate dielectrics232. As described above, since the first nanostructures204aand the second nanostructures204bare patterned through the first mask structure210aand the second mask structure210bwhile the third nanostructures204cand the fourth nanostructures204dare patterned through the widened third mask structure210c′ and the widened fourth mask structure210d′, the third nanostructures204cand the fourth nanostructures204dare wider than the first nanostructures204aand the second nanostructures204b. That is, the effective width of the third nanostructures204cand the fourth nanostructures204dare greater than that of the first nanostructures204aand the second nanostructures204b. Accordingly, the device in the second device region20′ may have a driven current than that in the first device region20. In some embodiments, the speed of the device in the second device region20′ is greater (e.g. over 10% higher) than that in the first device region20. In some embodiments, the first nanostructures204aand the second nanostructures204bhave the width W in a range from about 3 nm to about 7 nm. In some embodiments, the first nanostructures204aand the second nanostructures204bhas a pitch P1in a range from about 20 nm to about 26 nm. The pitch P1may be defined as the lateral distance between the lateral center of the first nanostructures204aand the lateral center of the second nanostructures204bor the lateral distance between the left-most point of the first nanostructures204aand the left-most point of the second nanostructures204b. In some embodiments, the third nanostructures204chave the width W3and the fourth nanostructures204dhave the width W4. In some embodiments, the width W3is substantially equal to the width W4and is in a range from about 8 nm to about 16 nm. In some embodiments, the ratio of the width W3to the width W is in a range from about 1.14 to about 2.3. In some embodiments, the third nanostructures204cand the fourth nanostructures204dhave a pitch P2in a range from about 30 nm to about 40 nm. The pitch P2may be defined as the lateral distance between the lateral center of the third nanostructures204cand the lateral center of the fourth nanostructures204dor the lateral distance between the left-most point of the third nanostructures204cand the left-most point of the fourth nanostructures204d. Meanwhile, since the first nanostructures204a, the second nanostructures204b, the third nanostructures204c, and the fourth nanostructures204dare all patterned from the semiconductor stack of the epitaxy layers102and104, each of the first nanostructures204a, the second nanostructures204b, the third nanostructures204c, and the fourth nanostructures204dare aligned with one another in accordance with some embodiments. In addition, all the first nanostructures204a, the second nanostructures204b, the third nanostructures204c, and the fourth nanostructures204dhave substantially the same thickness in a range from about 3 nm to about 7 nm in accordance with some embodiments. In some embodiments, the first nanostructures204a, the second nanostructures204b, the third nanostructures204c, and the fourth nanostructures204dhave substantially the same vertical spacing in a range from about 2 nm to about 10 nm The distance between the first nanostructures204aand the second nanostructures204bis substantially equal to the distance D3between the first fin structure205aand the second fin structure205b, and the distance between the third nanostructures204cand the fourth nanostructures204dis substantially equal to the distance D5between the third fin structure205cand the fourth fin structure205din accordance with some embodiments. The distance described above may be defined as the lateral distance between two nanostructures at the same height or the closest distance between the two sets of nanostructures. In some embodiments, the ratio of the distance D5to the distance D3is in a range from about 1.15 to about 2. In some embodiments, the isolation feature114formed around the first fin structure205a, the second fin structure205b, the third fin structure205c, and the fourth fin structure205dhas a curved top surface, as shown inFIGS.15-1,15-2,16-1,16-2(the perspective views have been simplified and therefore the curved top surface is not shown inFIGS.14A-1to14K-2). In some embodiments, the gate structure230has a first curved bottom surface between the first fin structure205aand the second fin structure205b, and the gate structure230′ has a second curved bottom surface between the third fin structure205cand the fourth fin structure205d. In addition, the lowest portion of the first curved bottom surface of the gate structure230is higher than the lowest portion of the second curved bottom surface of the gate structure230′ in accordance with some embodiments. Although two fin structures and one gate structure are shown in each of the first device region20and the second device region20′, they are only examples and the numbers of the fin structures and the gate structures are not intended to be limiting. For example, a semiconductor wafer may include a number of device regions including fin structures having various widths arranged in different pitches. FIG.18-1illustrates a layout including the first device region20of the semiconductor structures300andFIG.18-2illustrates a layout including the second device region20′ of the semiconductor structures300in accordance with some embodiments. As shown inFIG.18-1, the gate structures230are formed across the first fin structure205aand the second fin structure205cand conductive structures400and410are formed over the gate structures230in accordance with some embodiments. Similarly, the gate structures230′ are formed across the third fin structure205cand the fourth fin structure205dand conductive structures400′ and410′ are formed over the gate structures230′, as shown inFIG.18-2in accordance with some embodiments. In some embodiments, the conductive features400,410,400′, and410′ are made of conductive materials such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof. In addition, the conductive features400,410,400′, and410′ may include a liner and/or a barrier layer. The liner may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may be used as an alternative. The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. As described above, the width W3of the third fin structure205cand the width W4of the fourth fin structure205dmay be greater than the width W1of the first fin structure205aand the width W2of the second fin structure205b. In addition, the pitch P1may be smaller than the pitch P2. The device shown inFIG.18-2may provide higher driven current due to greater effective channel widths and therefore may be used in application requiring higher speed and/or performed such as High Performance Computing devices. On the other hand, the device shown inFIG.18-1may have better density and may be used in mobile devices. That is, devices with different characters may be manufactured over the same wafer without using complicated processes. As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values. Embodiments of a semiconductor structure and a method for forming the same may be provided. The semiconductor structure may include first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. In addition, a first gate structure may be formed surrounding the first nanostructures and the second nanostructures, and a second gate structure may be formed surrounding the third nanostructures and the fourth nanostructures. The first nanostructures and the second nanostructures may be narrower than the third nanostructures and the fourth nanostructures and the pitch between the first nanostructures and the second nanostructures may be smaller than the pitch between the third nanostructures and the fourth nanostructures. The device with wider nanostructures and wider widths may have improved performance and speed, while device with narrower nanostructures and narrower widths may have improved device density. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first device region formed over a substrate. In addition, the first device region includes first silicon-containing layers stacked and spaced apart from each other in a first direction and second silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the first silicon-containing layers in a second direction different from the first direction. the first device region further includes a first gate structure wrapping around the first silicon-containing layers and the second silicon-containing layers, and the first gate structure has a first curved bottom surface between the first silicon-containing layers and the second silicon-containing layers. The semiconductor structure includes a second device region formed over the substrate. In addition, the second device region includes third silicon-containing layers stacked and spaced apart from each other in the first direction and fourth silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the third silicon-containing layers in the second direction. The second device region further includes a second gate structure wrapping around the third silicon-containing layers and the fourth silicon-containing layers, and the second gate structure has a second curved bottom surface between the third silicon-containing layers and the fourth silicon-containing layers. In addition, a lowest portion of the first curved bottom surface of the first gate structure is higher than a lowest portion of the second curved bottom surface of the second gate structure. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes first silicon-containing layers and second silicon-containing layers extending lengthwise in a first direction over a substrate and a first gate structure extending lengthwise in a second direction different from the first direction and wrapping around the first silicon-containing layers and the second silicon-containing layers. The semiconductor structure further includes third silicon-containing layers and fourth silicon-containing layers extending lengthwise in the first direction over the substrate, and the first silicon-containing layers are narrower than the third silicon-containing layers in the second direction. The semiconductor structure further includes a second gate structure extending lengthwise in the second direction and wrapping around the third silicon-containing layers and the fourth silicon-containing layers. In addition, a first distance between the first silicon-containing layers and the second silicon-containing layers in the second direction is smaller than a second distance between the third silicon-containing layers and the fourth silicon-containing layers in the second direction. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures formed over the first fin structure, second nanostructures formed over the second fin structure, third nanostructures formed over the third fin structure, and fourth nanostructures formed over the fourth fin structure. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is smaller than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first device region formed over a substrate. The first device region includes first nanostructures and second nanostructures formed over the substrate and a first gate structure wrapping around the first nanostructures and the second nanostructures. The semiconductor structure further includes a second device region formed over the substrate. The second device region includes third nanostructures and fourth nanostructures formed over the substrate. In addition, the third nanostructures are wider than the first nanostructures, and the fourth nanostructures are wider than the second nanostructures. The second device region further includes a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a closest distance between one of the first nanostructures and one of the second nanostructures is smaller than a closest distance between one of the third nanostructures and one of the fourth nanostructures. A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack over a substrate and forming a first mask structure, a second mask structure, a third mask structure, and a fourth mask structure over the semiconductor stack. The method for manufacturing a semiconductor structure further includes forming third spacers on sidewalls of the third mask structure to form a widened third mask structure and fourth spacers on sidewalls of the fourth mask structure to form a widened fourth mask structure and patterning the semiconductor stack through the first mask structure, the second mask structure, the widened third mask structure, and the widened fourth mask structure to form a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure respectively. The method for manufacturing a semiconductor structure further includes removing the first epitaxy layers of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure to form first nanostructures, second nanostructures, third nanostructure, and fourth nanostructure respectively. In addition, a distance between the first mask structure and the second mask structure is smaller than a distance between the third mask structure and the fourth mask structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 71,869 |
11862635 | DESCRIPTION OF THE EMBODIMENTS Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires). Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL. Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing. One or more embodiments are directed to epitaxial region (EPI) splitting or separating or disjoining for multi-width (Wsi) ribbons having as-formed merged EPI regions. One or more embodiments are directed to neighboring semiconductor structures or devices having that are otherwise not separated by self-aligned gate endcap (SAGE) structures (e.g., on a die not including SAGE, or in a portion of a die not including SAGE formation). In a particular embodiment, a high temperature carbon hardmask (HTCHM) material is deposited on a merged or joined structure. A lithographic pattern is defined over an area that needs to be split or disjoined. An etch process is performed to split select merged EPI region. The split area is backfilled with dielectric material, and the HTCHM is optionally removed to enable further processing. In one or more embodiments, merged epitaxial regions are disjoined for gate-all-around structures, such as nano-ribbon/nano-wire technology. Particular embodiments may be directed to integration of multiple width (multi-Wsi) nanowires and nanoribbons in a non-SAGE architecture, or in neighboring regions of a SAGE architecture that are not immediately separated by a SAGE wall. In an embodiment, nanowires/nanoribbons are integrated with multiple Wsi in a non-SAGE architecture or non-SAGE portion of a front end process flow. Such a process flow may involve integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. To provide context, balancing non-uniform epitaxial growth across integrated circuit structures can be challenging. Embodiments described herein may address unwanted merged epitaxial growth associated with growing source or drain structures on silicon (Si) regions having differential nanoribbon/nanowire architectures. Epitaxial regions may be embedded (e.g., portions of nanowires removed and then source or drain (S/D) growth is performed) or formed by vertical merging (e.g., epitaxial regions are formed around existing wires), as described in greater detail below in association withFIGS.6A-6E. To provide further context, advantages of a self-aligned gate endcap (SAGE) architecture may include the enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing. However, certain application may not involve the use of SAGE, or regions of a structure may not include SAGE walls, yet high density may still be sought after. In such scenarios, undesirable merging of neighboring epitaxial regions may occur in high density locations. To provide illustrative comparison,FIG.1illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. Referring to the left-hand side (a) ofFIG.1, an integrated circuit structure100includes a substrate102having fins104protruding therefrom by an amount106above an isolation structure108laterally surrounding lower portions of the fins104. Corresponding nanowires105are over the fins104. A gate structure may be formed over the integrated circuit structure100to fabricate a device. However, breaks in such a gate structure may be accommodated for by increasing the spacing between fin104/nanowire105pairs. Alternatively, without increased spacing, merging of epitaxially grown source or drain structures can occur, as described in greater detail below. By contrast, referring to the right-hand side (b) ofFIG.1, an integrated circuit structure150includes a substrate152having fins154protruding therefrom by an amount156above an isolation structure158laterally surrounding lower portions of the fins154. Corresponding nanowires155are over the fins154. Isolating SAGE walls160(which may include a hardmask thereon, as depicted) are included within the isolation structure158and between adjacent fin154/nanowire155pairs. The distance between an isolating SAGE wall160and a nearest fin154/nanowire155pair defines the gate endcap spacing162. A gate structure may be formed over the integrated circuit structure150, between insolating SAGE walls to fabricate a device. Breaks in such a gate structure are imposed by the isolating SAGE walls. Since the isolating SAGE walls160are self-aligned, restrictions from conventional approaches can be minimized to enable more aggressive diffusion to diffusion spacing. Furthermore, since gate structures include breaks at all locations, individual gate structure portions may be layer connected by local interconnects formed over the isolating SAGE walls160. In an embodiment, as depicted, the SAGE walls160each include a lower dielectric portion and a dielectric cap on the lower dielectric portion. A self-aligned gate endcap (SAGE) processing scheme involves the formation of gate/trench contact endcaps self-aligned to fins without requiring an extra length to account for mask mis-registration. Thus, embodiments may be implemented to enable shrinking of transistor layout area. Embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls or self-aligned gate endcap (SAGE) walls. Other embodiments, however, involve applications, or regions of a die or architecture that include neighboring structures that are not separated by isolation gate walls or self-aligned gate endcap (SAGE) walls. In an exemplary processing scheme for structures having SAGE walls separating neighboring devices,FIG.2illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure. Referring to part (a) ofFIG.2, a starting structure includes a nanowire patterning stack204above a substrate202. A lithographic patterning stack206is formed above the nanowire patterning stack204. The nanowire patterning stack204includes alternating silicon germanium layers210and silicon layers212. A protective mask214is between the nanowire patterning stack204and the lithographic patterning stack206. In one embodiment, the lithographic patterning stack206is trilayer mask composed of a topographic masking portion220, an anti-reflective coating (ARC) layer222, and a photoresist layer224. In a particular such embodiment, the topographic masking portion220is a carbon hardmask (CHM) layer and the anti-reflective coating layer222is a silicon ARC layer. Referring to part (b) ofFIG.2, the stack of part (a) is lithographically patterned and then etched to provide an etched structure including a patterned substrate202and trenches230. Referring to part (c) ofFIG.2, the structure of part (b) has an isolation layer240and a SAGE material242formed in trenches230. The structure is then planarized to leave patterned topographic masking layer220′ as an exposed upper layer. Referring to part (d) ofFIG.2, the isolation layer240is recessed below an upper surface of the patterned substrate202, e.g., to define a protruding fin portion and to provide a trench isolation structure241beneath SAGE walls242. Referring to part (e) ofFIG.2, the silicon germanium layers210are removed at least in the channel region to release silicon nanowires212A and212B. Subsequent to the formation of the structure of part (e) ofFIG.2, a gate stacks may be formed around nanowires212B or212A, over protruding fins of substrate202, and between SAGE walls242. In one embodiment, prior to formation of the gate stacks, the remaining portion of protective mask214is removed. In another embodiment, the remaining portion of protective mask214is retained as an insulating fin hat as an artifact of the processing scheme. Referring again to part (e) ofFIG.2, it is to be appreciated that a channel view is depicted, with source or drain regions being locating into and out of the page. In an embodiment, the channel region including nanowires212B has a width less than the channel region including nanowires212A. Thus, in an embodiment, an integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although structures of212B and212A may be differentiated as nanowires and nanoribbons, respectively, both such structures are typically referred to herein as nanowires. It is also to be appreciated that reference to or depiction of a fin/nanowire pair throughout may refer to a structure including a fin and one or more overlying nanowires (e.g., two overlying nanowires are shown inFIG.2). In an exemplary process flow for structures having SAGE walls separating neighboring devices, a planarizing material is formed over structures having uneven epitaxial growth and a non-selective etch is used to recess the planarizing material and the structures having uneven epitaxial growth. For example,FIGS.3A-3Cillustrate cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices having epitaxial source or drain structures, in accordance with an embodiment of the present disclosure. Referring toFIG.3A, a method of fabricating an integrated circuit structure300includes forming a first vertical arrangement of nanowires306and a second vertical arrangement of nanowires304above a substrate302. The nanowires of the second vertical arrangement of nanowires304have a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires306(e.g., nanowires306may be referred to as nanowires, and nanowires304may be referred to as nanoribbons). A gate endcap isolation structure308is formed between the first vertical arrangement of nanowires306and the second vertical arrangement of nanowires304. First epitaxial source or drain structures312are formed at ends of the first vertical arrangement of nanowires306(only one end depicted inFIG.3A). Second epitaxial source or drain structures310are formed at ends of the second vertical arrangement of nanowires304(only one end depicted inFIG.3A). In an embodiment, the second epitaxial source or drain structures310have an uppermost surface above the uppermost surface of the gate endcap isolation structure308, as is depicted inFIG.3A. In one such embodiment, the first epitaxial source or drain structures312have an uppermost surface below the uppermost surface of the gate endcap isolation structure308, as is also depicted inFIG.3A. In an embodiment, the first vertical arrangement of nanowires306is over a first fin, and the second vertical arrangement of nanowires304is over a second fin, as exemplified inFIG.2. Referring toFIG.3B, a planarizing material314is formed over the structure ofFIG.3A. In one embodiment, the planarizing material314is a carbon hardmask material deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD) and then subjected to a chemical mechanical planarization process. In another embodiment, the planarizing material314is a flowable silicon oxide based material. In an embodiment, planarizing material314is flowable material and can be used to fill a narrow narrow trench. In some embodiment, the deposition leads to a relatively flat surface and, hence, an actual “planarization” operation may be optional. It is to be appreciated that a carbon hardmask may be used as a flowable material, however, a flowable oxide can also be used as well. Referring toFIG.3C, the uppermost surface of the second epitaxial source or drain structures310are recessed below the uppermost surface of the gate endcap isolation structure308to form integrated circuit structure350having recessed second epitaxial source or drain structures310′ and recessed planarizing material314′. In an embodiment, the recessing is performed using an etch process that is not selective between the planarizing material314and the second epitaxial source or drain structures310. The recessed planarizing material314′ may subsequently be removed to enable contact formation. In an embodiment, in the case that a selective etch is performed, a masking or inter-layer dielectric material is first recessed to prior to a pre-epitaxial etch in order to recess masking or inter-layer dielectric material separately. Referring again toFIG.3C, in an embodiment, as depicted, the recessing further involves recessing an uppermost surface of the first epitaxial source or drain structures312to form recessed first epitaxial source or drain structures312′. In an embodiment, the uppermost surfaces of the epitaxial source or drain structures are recessed below the uppermost surface of the gate endcap isolation structure308to inhibit shorting of devices due to conductive or semiconducting structures protruding above the gate endcap isolation structure308. By contrast, in an exemplary process flow for structures not having SAGE walls separating neighboring devices,FIGS.4A-4Eillustrate cross-sectional views representing various operations in a method of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, in accordance with an embodiment of the present disclosure. Referring toFIG.4A, a method of fabricating an integrated circuit structure400includes forming a first vertical arrangement of nanowires406and a second vertical arrangement of nanowires404above a substrate402. The nanowires of the second vertical arrangement of nanowires404have a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires406(e.g., nanowires406may be referred to as nanowires, and nanowires404may be referred to as nanoribbons). First epitaxial source or drain structures412are formed at ends of the first vertical arrangement of nanowires406(only one end depicted inFIG.3A). Second epitaxial source or drain structures410are formed at ends of the second vertical arrangement of nanowires404(only one end depicted inFIG.3A). Ones of the second epitaxial source or drain structures410and corresponding ones of the first epitaxial source or drain structures412have a merged region413there between. Referring again toFIG.4A, a hardmask414, such as a carbon hardmask is formed over the second epitaxial source or drain structures410and the first epitaxial source or drain structures412, and the merged region413there between. Referring toFIG.4B, hardmask414is used as a foundation together with a stack420to form a trilayer mask composed of a topographic masking portion (hardmask414), an anti-reflective coating (ARC) layer422, and a photoresist layer424patterned to have an opening426therein. In a particular such embodiment, the anti-reflective coating layer422is a silicon ARC layer. Referring toFIG.4C, the pattern of the opening426is extended through the underlying structure to form patterned hardmask414′ and to disjoin the ones of the second epitaxial source or drain structures410and the corresponding merged ones of the first epitaxial source or drain structures412. In an embodiment, the merged region413is removed to disjoin the ones of the second epitaxial source or drain structures410and the corresponding ones of the first epitaxial source or drain structures412, forming disjoined second epitaxial source or drain structures410′ and first epitaxial source or drain structures412′. In one embodiment, the merged region413is removed to disjoin the ones of the second epitaxial source or drain structures410and the corresponding ones of the first epitaxial source or drain structures412by anisotropically etching the merged region413. The patterned photoresist layer424may then be removed. Referring toFIG.4D, a dielectric material430is formed over the structure ofFIG.4C. Referring toFIG.4E, the dielectric material430is planarized (which may involve removal of layer422) to form an intervening dielectric structure432between the ones of the disjoined second epitaxial source or drain structures410′ and the corresponding ones of the first epitaxial source or drain structures412′. The patterned hardmask414′ may subsequently be removed to enable contact formation. Referring again toFIG.4E, in accordance with an embodiment of the present disclosure, an integrated circuit structure450includes a first vertical arrangement of nanowires406and a second vertical arrangement of nanowires404above a substrate402. The nanowires of the second vertical arrangement of nanowires404have a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires406. First epitaxial source or drain structures412′ are at ends of the first vertical arrangement of nanowires406. Second epitaxial source or drain structures410′ are at ends of the second vertical arrangement of nanowires404. An intervening dielectric structure432is between neighboring ones of the first epitaxial source or drain structures412′ and of the second epitaxial source or drain structures410′. In an embodiment, first epitaxial source or drain structures412′ and second epitaxial source or drain structures410′ are asymmetrical in the horizontal direction in the perspective taken inFIG.4E, as is depicted, e.g., as a result of separating a merged structure. Referring again toFIG.4E, in accordance with an embodiment of the present disclosure, a bottom portion of the first epitaxial source or drain structures412′ is tapered, and a bottom portion of the second epitaxial source or drain structures410′ is tapered. In an embodiment, the uppermost surface of the first epitaxial source or drain structures412′ is a first vertex, and the uppermost surface of the second epitaxial source or drain structures410′ is a second vertex, as is depicted. In an embodiment, the first and second epitaxial source or drain structures are vertically non-discrete first and second epitaxial source or drain structures, as depicted inFIG.4E, and as described in greater detail below. In another embodiment, the first and second epitaxial source or drain structures are vertically discrete first and second epitaxial source or drain structures, as is also described in greater detail below. Although not depicted in the view ofFIG.4E, but as exemplified in other embodiments described herein, a first gate stack is over the first vertical arrangement of nanowires, and a second gate stack is over the second vertical arrangement of nanowires. In a particular embodiment, a first gate structure is over a first nanowire or nanowire stack and a corresponding first fin along a first direction. The first gate structure has a longest dimension along a second direction, the second direction orthogonal to the first direction. A second gate structure is over a second nanowire or nanowire stack and over a corresponding second fin. The second gate structure has a longest dimension along the second direction. In one embodiment, the second gate structure is continuous with the first gate structure along the second direction, e.g., a SAGE wall does not separate the first and second gate structures. To highlight an exemplary integrated circuit structure having three vertically arranged nanowires,FIG.5Aillustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.FIG.5Billustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure ofFIG.5A, as taken along the a-a′ axis.FIG.5Cillustrates a cross-sectional channel view of the nanowire-based integrated circuit structure ofFIG.5A, as taken along the b-b′ axis. Referring toFIG.5A, an integrated circuit structure500includes one or more vertically stacked nanowires (504set) above a substrate502. An optional fin between the bottommost nanowire and the substrate502is not depicted for the sake of emphasizing the nanowire portion for illustrative purposes. Embodiments herein are targeted at both single wire devices and multiple wire devices. As an example, a three nanowire-based devices having nanowires504A,504B and504C is shown for illustrative purposes. For convenience of description, nanowire504A is used as an example where description is focused on one of the nanowires. It is to be appreciated that where attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or essentially the same attributes for each of the nanowires. Each of the nanowires504includes a channel region506in the nanowire. The channel region506has a length (L). Referring toFIG.5C, the channel region also has a perimeter (Pc) orthogonal to the length (L). Referring to bothFIGS.5A and5C, a gate electrode stack508surrounds the entire perimeter (Pc) of each of the channel regions506. The gate electrode stack508includes a gate electrode along with a gate dielectric layer between the channel region506and the gate electrode (not shown). In an embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack508without any intervening material such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments having a plurality of nanowires504, the channel regions506of the nanowires are also discrete relative to one another. Referring to bothFIGS.5A and5B, integrated circuit structure500includes a pair of non-discrete source or drain regions510/512. The pair of non-discrete source or drain regions510/512is on either side of the channel regions506of the plurality of vertically stacked nanowires504. Furthermore, the pair of non-discrete source or drain regions510/512is adjoining for the channel regions506of the plurality of vertically stacked nanowires504. In one such embodiment, not depicted, the pair of non-discrete source or drain regions510/512is directly vertically adjoining for the channel regions506in that epitaxial growth is on and between nanowire portions extending beyond the channel regions506(as exemplified inFIGS.3C and4E), where nanowire ends are shown within the source or drain structures. In another embodiment, as depicted inFIG.5A, the pair of non-discrete source or drain regions510/512is indirectly vertically adjoining for the channel regions506in that they are formed at the ends of the nanowires and not between the nanowires. In an embodiment, as depicted, the source or drain regions510/512are non-discrete in that there are not individual and discrete source or drain regions for each channel region506of a nanowire504. Accordingly, in embodiments having a plurality of nanowires504, the source or drain regions510/512of the nanowires are global or unified source or drain regions as opposed to discrete for each nanowire. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions506, each of the pair of non-discrete source or drain regions510/512is approximately rectangular in shape with a bottom tapered portion and a top vertex portion, as depicted inFIG.5B. In other embodiments, however, the source or drain regions510/512of the nanowires are relatively larger yet discrete non-vertically merged epitaxial structures. In accordance with an embodiment of the present disclosure, and as depicted inFIGS.5A and5B, integrated circuit structure500further includes a pair of contacts514, each contact514on one of the pair of non-discrete source or drain regions510/512. In one such embodiment, in a vertical sense, each contact514completely surrounds the respective non-discrete source or drain region510/512. In another aspect, the entire perimeter of the non-discrete source or drain regions510/512may not be accessible for contact with contacts514, and the contact514thus only partially surrounds the non-discrete source or drain regions510/512, as depicted inFIG.5B. In a contrasting embodiment, not depicted, the entire perimeter of the non-discrete source or drain regions510/512, as taken along the a-a′ axis, is surrounded by the contacts514. Referring toFIGS.5B and5C, the non-discrete source or drain regions510/512are global in the sense that a single unified feature is used as a source or drain region for a plurality (in this case, 3) of nanowires504and, more particularly, for more than one discrete channel region506. In an embodiment, the pair of non-discrete source or drain regions510/512is composed of a semiconductor material different than the semiconductor material of the discrete channel regions506, e.g., the pair of non-discrete source or drain regions510/512is composed of a silicon germanium while the discrete channel regions506are composed of silicon. In another embodiment, the pair of non-discrete source or drain regions510/512is composed of a semiconductor material the same or essentially the same as the semiconductor material of the discrete channel regions506, e.g., both the pair of non-discrete source or drain regions510/512and the discrete channel regions506are composed of silicon. Referring again toFIG.5A, in an embodiment, integrated circuit structure500further includes a pair of spacers516. As is depicted, outer portions of the pair of spacers516may overlap portions of the non-discrete source or drain regions510/512, providing for “embedded” portions of the non-discrete source or drain regions510/512beneath the pair of spacers516. As is also depicted, the embedded portions of the non-discrete source or drain regions510/512may not extend beneath the entirety of the pair of spacers516. Substrate502may be composed of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate502includes a lower bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride is on the lower bulk substrate. Thus, the structure500may be fabricated from a starting semiconductor-on-insulator substrate. Alternatively, the structure500is formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer. In another alternative embodiment, the structure500is formed directly from a bulk substrate and doping is used to form electrically isolated active regions, such as nanowires, thereon. In one such embodiment, the first nanowire (i.e., proximate the substrate) is in the form of an omega-FET type structure. In an embodiment, the nanowires504may be sized as wires or ribbons, as described below, and may have squared-off or rounder corners. In an embodiment, the nanowires504are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single-crystalline. For example, for a silicon nanowire504, a single-crystalline nanowire may be based from a (100) global orientation, e.g., with a <100> plane in the z-direction. As described below, other orientations may also be considered. In an embodiment, the dimensions of the nanowires504, from a cross-sectional perspective, are on the nano-scale. For example, in a specific embodiment, the smallest dimension of the nanowires504is less than approximately 20 nanometers. In an embodiment, the nanowires504are composed of a strained material, particularly in the channel regions506. Referring toFIGS.5C, in an embodiment, each of the channel regions506has a width (Wc) and a height (Hc), the width (Wc) approximately the same as the height (Hc). That is, in both cases, the channel regions506are square-like or, if corner-rounded, circle-like in cross-section profile. In another aspect, the width and height of the channel region need not be the same, such as the case for nanoribbbons as described throughout. In another aspect, methods of fabricating a nanowire portion of a fin/nanowire integrated circuit structure are provided. For example,FIGS.6A-6Eillustrate three-dimensional cross-sectional views representing various operations in a method of fabricating a nanowire portion of a fin/nanowire structure, in accordance with an embodiment of the present disclosure. It is to be appreciated that, for clarity, a laterally neighboring integrated circuit structure and an intervening dielectric structure implemented between disjoined neighboring source or drain regions are not depicted in association withFIGS.6A-6E. A method of fabricating a nanowire integrated circuit structure may include forming a nanowire above a substrate. In a specific example showing the formation of two silicon nanowires,FIG.6Aillustrates a substrate602(e.g., composed of a bulk substrate silicon substrate602A with an insulating silicon dioxide layer602B there on) having a silicon layer604/silicon germanium layer606/silicon layer608stack thereon. It is to be understood that, in another embodiment, a silicon germanium layer/silicon layer/silicon germanium layer stack may be used to ultimately form two silicon germanium nanowires. Referring toFIG.6B, a portion of the silicon layer604/silicon germanium layer606/silicon layer608stack as well as a top portion of the silicon dioxide layer602B is patterned into a fin-type structure610, e.g., with a mask and plasma etch process. It is to be appreciated that, for illustrative purposes, the etch forFIG.6Bis shown as forming two silicon nanowire precursor portions. Although the etch is shown for ease of illustration as ending within a bottom isolation layer, more complex stacks are contemplated within the context of embodiments of the present disclosure. For example, the process may be applied to a nanowire/fin stack as described in association withFIG.5. The method may also include forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length. In a specific example showing the formation of three gate structures over the two silicon nanowires,FIG.6Cillustrates the fin-type structure610with three sacrificial gates612A,612B, and612C thereon. In one such embodiment, the three sacrificial gates612A,612B, and612C are composed of a sacrificial gate oxide layer614and a sacrificial polysilicon gate layer616which are blanket deposited and patterned with a plasma etch process. Following patterning to form the three sacrificial gates612A,612B, and612C, spacers may be formed on the sidewalls of the three sacrificial gates612A,612B, and612C, doping may be performed (e.g., tip and/or source and drain type doping), and an interlayer dielectric layer may be formed to cover the three sacrificial gates612A,612B, and612C. The interlayer dielectric layer may be polished to expose the three sacrificial gates612A,612B, and612C for a replacement gate, or gate-last, process. Referring toFIG.6D, the three sacrificial gates612A,612B, and612C have been removed, leaving spacers618and a portion of the interlayer dielectric layer620remaining. Additionally, referring again toFIG.6Dthe portions of the silicon germanium layer606and the portion of the insulating silicon dioxide layer602B of the fin structure610are removed in the regions originally covered by the three sacrificial gates612A,612B, and612C. Discrete portions of the silicon layers604and608thus remain, as depicted inFIG.6D. The discrete portions of the silicon layers604and608shown inFIG.6Dwill, in one embodiment, ultimately become channel regions in a nanowire-based device. Thus, at the process stage depicted inFIG.6D, channel engineering or tuning may be performed. For example, in one embodiment, the discrete portions of the silicon layers604and608shown inFIG.6Dare thinned using oxidation and etch processes. Such an etch process may be performed at the same time the wires are separated by etching the silicon germanium layer606. Accordingly, the initial wires formed from silicon layers604and608begin thicker and are thinned to a size suitable for a channel region in a nanowire device, independent from the sizing of the source and drain regions of the device. Thus, in an embodiment, forming the channel region includes removing a portion of the nanowire, and the resulting perimeters of the source and drain regions (described below) are greater than the perimeter of the resulting channel region. The method may also include forming a gate electrode stack surrounding the entire perimeter of the channel region. In the specific example showing the formation of three gate structures over the two silicon nanowires,FIG.6Eillustrates the structure following deposition of a gate dielectric layer622(such as a high-k gate dielectric layer) and a gate electrode layer624(such as a metal gate electrode layer), and subsequent polishing, in between the spacers618. That is, gate structures are formed in the trenches621ofFIG.6D. Additionally,FIG.6Edepicts the result of the subsequent removal of the interlayer dielectric layer620after formation of the permanent gate stack. The portions of the silicon germanium layer606and the portion of the insulating silicon dioxide layer602B of the fin structure610are also removed in the regions originally covered by the portion of the interlayer dielectric layer620depicted inFIG.6D. Discrete portions of the silicon layers604and608thus remain, as depicted inFIG.6E. The method may also include forming a pair of source and drain regions in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region. Specifically, the discrete portions of the silicon layers604and608shown inFIG.6Ewill, in one embodiment, ultimately become at least a portion of the source and drain regions in a nanowire-based device. In one such embodiment, epitaxial source or drain structures are formed by merging epitaxial material around existing nanowires604and608. In another embodiment, epitaxial source or drain structures are embedded, e.g., portions of nanowires604and608are removed and then source or drain (S/D) growth is performed. In either case, in accordance with an embodiment of the present disclosure, such epitaxial source or drain structures are disjoined from corresponding epitaxial source or drain structures from a neighboring device, as exemplified in association withFIGS.4A-4E. The method may subsequently include forming a pair of contacts, a first of the pair of contacts completely or nearly completely surrounding the perimeter of the source region, and a second of the pair of contacts completely or nearly completely surrounding the perimeter of the drain region. Specifically, contacts are formed in the trenches625ofFIG.6Efollowing epitaxial growth and recess. In an embodiment, the contacts are formed from a metallic species. In one such embodiment, the metallic species is formed by conformally depositing a contact metal and then filling any remaining trench volume. The conformal aspect of the deposition may be performed by using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow. In an embodiment, as described throughout, an integrated circuit structure includes non-planar devices such as, but not limited to, a finFET or a tri-gate device with corresponding one or more overlying nanowire structures. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, the gate structures surround at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions. In an embodiment, as described throughout, a substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. A bulk substrate may alternatively be composed of a group III-V material. In an embodiment, a bulk substrate is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. In an embodiment, as described throughout, a trench isolation layer may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, a trench isolation layer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In an embodiment, as described throughout, self-aligned gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another. Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide. In an embodiment, as described throughout, gate structures may be composed of a gate electrode stack which includes a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer includes a high-K material. In an embodiment, the gate dielectric of region is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of a corresponding substrate. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In an embodiment, the top high-k portion consists of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In an embodiment, a gate dielectric of region includes a layer of non-native silicon oxide in addition to a layer of high-k material. The layer of non-native silicon oxide may be formed using a CVD process and may be formed below or above the layer of high-k material. In an exemplary embodiment, a layer of non-native silicon oxide is formed beneath a layer of high-k material. In an embodiment, a gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In an embodiment, as described throughout, local interconnects, gate contacts, overlying gate contact vias, and overlying metal interconnects may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). A common example is the use of copper structures that may or may not include barrier layers (such as Ta or TaN layers) between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc. In an embodiment (although not shown), a contact pattern which is essentially perfectly aligned to an existing gate pattern is formed while eliminating the use of a lithographic step with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts. Furthermore, gate structures described herein may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid. In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to fabricate an integrated circuit structure. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately 600 degrees Celsius. The anneal is performed prior to formation of the permanent contacts. In an embodiment, an integrated circuit structure has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for integrated circuit structure or semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features. In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods. In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect. In an embodiment, as is also used throughout the present description, hardmask materials, capping layers, or plugs are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer, capping or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hardmask, capping or plug layers known in the arts may be used depending upon the particular implementation. The hardmask, capping or plug layers maybe formed by CVD, PVD, or by other deposition methods. In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion litho (i193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer. Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein. FIG.7illustrates a computing device700in accordance with one implementation of an embodiment of the present disclosure. The computing device700houses a board702. The board702may include a number of components, including but not limited to a processor704and at least one communication chip706. The processor704is physically and electrically coupled to the board702. In some implementations the at least one communication chip706is also physically and electrically coupled to the board702. In further implementations, the communication chip706is part of the processor704. Depending on its applications, computing device700may include other components that may or may not be physically and electrically coupled to the board702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The communication chip706enables wireless communications for the transfer of data to and from the computing device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip706may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device700may include a plurality of communication chips706. For instance, a first communication chip706may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip706may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor704of the computing device700includes an integrated circuit die packaged within the processor704. The integrated circuit die of the processor704may include one or more structures, such as integrated circuit structures built in accordance with implementations of embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip706also includes an integrated circuit die packaged within the communication chip706. The integrated circuit die of the communication chip706may include one or more structures, such as integrated circuit structures built in accordance with implementations of embodiments of the present disclosure. In further implementations, another component housed within the computing device700may contain an integrated circuit die that includes one or structures, such as integrated circuit structures built in accordance with implementations of embodiments of the present disclosure. In various implementations, the computing device700may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device700may be any other electronic device that processes data. FIG.8illustrates an interposer800that includes one or more embodiments of the present disclosure. The interposer800is an intervening substrate used to bridge a first substrate802to a second substrate804. The first substrate802may be, for instance, an integrated circuit die. The second substrate804may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer800is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer800may couple an integrated circuit die to a ball grid array (BGA)806that can subsequently be coupled to the second substrate804. In some embodiments, the first and second substrates802/804are attached to opposing sides of the interposer800. In other embodiments, the first and second substrates802/804are attached to the same side of the interposer800. And in further embodiments, three or more substrates are interconnected by way of the interposer800. The interposer800may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer may include metal interconnects808and vias810, including but not limited to through-silicon vias (TSVs)812. The interposer800may further include embedded devices814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer800. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer800or in the fabrication of components included in the interposer800. Thus, embodiments of the present disclosure include neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions. The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.Example embodiment 1: An integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein the uppermost surface of the first epitaxial source or drain structures is a first vertex, and the uppermost surface of the second epitaxial source or drain structures is a second vertex.Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, wherein a bottom portion of the first epitaxial source or drain structures is tapered, and a bottom portion of the second epitaxial source or drain structures is tapered.Example embodiment 4: The integrated circuit structure of example embodiment 1, 2 or 3, wherein the first gate stack has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate stack, and wherein the second gate stack has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate stack.Example embodiment 5: The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.Example embodiment 6: The integrated circuit structure of example embodiment 1, 2, 3, 4 or 5, wherein the first vertical arrangement of nanowires is over a first fin, and the second vertical arrangement of nanowires is over a second fin.Example embodiment 7: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the first and second gate stacks each include a high-k gate dielectric layer and a metal gate electrode.Example embodiment 8: A method of fabricating an integrated circuit structure includes forming a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First epitaxial source or drain structures are formed at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are formed at ends of the second vertical arrangement of nanowires. Ones of the second epitaxial source or drain structures and corresponding ones of the first epitaxial source or drain structures have a merged region there between. The merged region is removed to disjoin the ones of the second epitaxial source or drain structures and the corresponding ones of the first epitaxial source or drain structures. An intervening dielectric structure is formed between the ones of the second epitaxial source or drain structures and the corresponding ones of the first epitaxial source or drain structures.Example embodiment 9: The method of example embodiment 8, wherein removing the merged region to disjoin the ones of the second epitaxial source or drain structures and the corresponding ones of the first epitaxial source or drain structures involves anisotropically etching the merged region.Example embodiment 10: The method of example embodiment 8 or 9, wherein the uppermost surface of the first epitaxial source or drain structures is a first vertex, and the uppermost surface of the second epitaxial source or drain structures is a second vertex.Example embodiment 11: The method of example embodiment 8, 9 or 10, wherein a bottom portion of the first epitaxial source or drain structures is tapered, and a bottom portion of the second epitaxial source or drain structures is tapered.Example embodiment 12: The method of example embodiment 8, 9, 10 or 11, wherein the first gate stack has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate stack, and wherein the second gate stack has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate stack.Example embodiment 13: The method of example embodiment 8, 9, 10, 11 or 12, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.Example embodiment 14: The method of example embodiment 8, 9, 10, 11, 12 or 13, wherein the first vertical arrangement of nanowires is over a first fin, and the second vertical arrangement of nanowires is over a second fin.Example embodiment 15: The method of example embodiment 8, 9, 10, 11, 12, 13 or 14, wherein the first and second gate stacks each include a high-k gate dielectric layer and a metal gate electrode.Example embodiment 16: An integrated circuit structure includes a first fin having a longest dimension along a first direction. A first nanowire is over the first fin. A second fin having a longest dimension is along the first direction. A second nanowire is over the second fin. The second nanowire is wider than the nanowire. A first gate structure is over the first nanowire and the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction. A second gate structure is over the second nanowire and over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure continuous with the first gate structure along the second direction. First epitaxial source or drain structures are at ends of the first nanowire. Second epitaxial source or drain structures are at ends of the second nanowire. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.Example embodiment 17: The integrated circuit structure of example embodiment 16, further including first dielectric sidewall spacers along the first gate structure, the first epitaxial source or drain structures extending beneath the first dielectric sidewalls spacers, and further including second dielectric sidewall spacers along the second gate structure, the second epitaxial source or drain structures extending beneath the second dielectric sidewalls spacers.Example embodiment 18: The integrated circuit structure of example embodiment 16 or 17, wherein the uppermost surface of the first epitaxial source or drain structures is a first vertex, and the uppermost surface of the second epitaxial source or drain structures is a second vertex.Example embodiment 19: The integrated circuit structure of example embodiment 16, 17 or 18, wherein a bottom portion of the first epitaxial source or drain structures is tapered, and a bottom portion of the second epitaxial source or drain structures is tapered.Example embodiment 20: The integrated circuit structure of example embodiment 16, 17, 18 or 19, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures. | 70,124 |
11862636 | DESCRIPTION OF THE EMBODIMENTS Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires). Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL. Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing. One or more embodiments described herein are directed to selective bottom-up approaches for nanowire transistor channel depopulation and nanoribbon transistor channel depopulation. Unless stated explicitly otherwise, reference to a nanowire structure can include nanowire structure and/or nanoribbon structures. Some embodiments are directed to selective depopulation of nanoribbon/wires in stacked n-/p-transistor devices. Embodiments can be implemented to allow depopulation of n+1 bottom nanowires in a stacked nanowire transistor device. In accordance with one or more embodiments described herein, selective recess and oxidation is used to change solubility of n+1 bottom wires/ribbons in a nanowire fin stack, to selectively etch the bottom wires/ribbons during wire release etch. Advantages for implementing embodiments described herein can include providing for flexibility in device performance metrics. Embodiments can be implemented to fabricate N-only, or p-only devices in a stacked n/-p-transistor architectures. To provide context, issues with state of the art approaches include: (i) flexibility needed to depopulate ribbons in nanoribbon transistors to control device performance, and/or (ii) there is a need for an approach to selectively remove nanoribbons from the bottom of the gate stack, while keeping the top ribbons in place. To address these issues, in accordance with embodiments described herein, selective depopulation of nanowires or nanoribbons with a recess and sacrificial oxidation approach is described. Embodiments may be implemented to allow removal of 1+n bottom ribbons in a 2+m nanoribbon transistor device using a patterned recess, selective oxidation and etch process. Different numbers of wires or ribbons can be removed by several operations of patterning, recess, oxidation, etch. The recess etch can determines the numbers of wires or ribbons removed. It is to be appreciated that embodiments may be implemented either post FIN patterning (as bulk stacks) or in the gate process loop (e.g., through openings formed during a replacement gate process). To provide additional context, integration of nanowire and/or nanoribbon complementary metal oxide semiconductor (CMOS) transistors is faced with the challenge of creating devices with different strengths. In the current FinFET technology, device strength granularity is achieved by varying the number of fins in the device channel. This option is unfortunately not easily available for nanowire and nanoribbon architectures since the channels are vertically stacked. This requirement is even more punishing for nanowire and/or nanoribbon (NW/NR) structures in a self-aligned stacked CMOS structure where NMOS and PMOS channels are patterned at the same width. Previous attempts to address the above issues have included (1) integrating NW/NR devices with different channel widths (an option only available for nanoribbon that requires complex patterning), or (2) subtractively removing wires/ribbon from source/drain or channel regions (an option challenging for stacked CMOS architectures). To provide further context, transistors with different drive currents may be needed for different circuit types. Embodiments disclosed herein are directed to achieving different drive currents by de-populating the number of nanowire transistor channels in device structures. One or more embodiments provide an approach for deleting discrete numbers of wires from a transistor structure. Approaches may be suitable for both ribbons and wires (RAW). Furthermore, transistor leakage current flowing through a sub-fin must be controlled for proper circuit function. Embodiments disclosed herein provide a method for sub-fin isolation for nanowire transistors. For de-population, technologies using FinFETs can de-populate the number of fins in each device to achieve different drive-current strengths. For sub-fin isolation, sub-fin implants are used to dope a sub-fin to reduce leakage. However, since nanowires are stacked and self-aligned, they cannot be de-populated the same ways as fins. Additionally, sub-fin dopants must be targeted and can back-diffuse into the channel, degrading carrier transport. In accordance with an embodiment of the present disclosure, described herein is a process flow for achieving selective bottom-up nanowire transistor channel de-population and/or sub-fin isolation. Embodiments may include channel de-population of nanowire transistors to provide for modulation of drive currents in different devices, which may be needed for different circuits. Embodiments may be implemented as a selective approach allowing deep-scaling for future nanowire technologies. In accordance with an embodiment of the present disclosure, nanowire processing of an alternating Si/SiGe stack includes patterning the stack into fins. Generic dummy gates (which may or may not be poly dummy gates) are patterned and etched. During a replacement gate process, select lower or bottom ones of NW/NR channels are exposed. A thin film oxidation catalyst layer (e.g., Al2O3) is deposited on the sides of the exposed lower or bottom ones of the NW/NR channels, e.g., using an atomic layer deposition (ALD) process. The bottommost one or more NW/NR channels are then selectively converted into an oxide (e.g., a silicon oxide from oxidizing silicon NW/NR channels), e.g., by subjecting them to a wet oxidation anneal. Since the oxidation catalyst layer (e.g., Al2O3) promotes oxygen diffusion into silicon (Si), the bottommost one or more NW/NR channels are rapidly converted to oxide (e.g., SiO2). The oxidation condition selected may be very mild such that little oxidation occurs on the upper ribbons that are not in contact with the oxidation catalysts layer. In this way, Si nanowires are oxidized from the bottom-up. The nanowires can then be released in a channel release process, where intervening sacrificial material is removed. Although some embodiments describe the use of Si (wire or ribbon) and SiGe (sacrificial) layers, other pairs of semiconductor materials which can be alloyed and grown epitaxially could be implemented to achieve various embodiments herein, for example, InAs and InGaAs, or SiGe and Ge. Embodiments described herein enable the fabrication of self-aligned stacked transistors with variable numbers of active nanowires or nanoribbons in the channel, and methods to achieve such structures. As a comparison of channel depopulation involving source or drain structure tuning,FIG.1illustrates cross-sectional views (gate cut on fin, and fin cut on gate) representing a gate-all-around integrated circuit structure having a depopulated channel structure. Referring toFIG.1, a CMOS integrated circuit structure100is formed above a substrate102and includes a lower PMOS region and an upper NMOS region. The lower PMOS region includes stacked nanoribbons104A,104B,104C and104D. P-type source or drain structures106are adjacent the stacked nanoribbons and above an insulating structure108. A lower gate structure includes a gate dielectric layer110having a P-type gate electrode112thereon. The upper NMOS region includes stacked nanoribbons114A,114B,114C and114D. N-type source or drain structures116are adjacent the stacked nanoribbons and above an insulating structure118. An upper gate structure includes a gate dielectric layer120having an N-type gate electrode122thereon. Spacers124may be adjacent to an uppermost portion of the upper gate structure. It is to be appreciated that the above specifically describes an NMOS on PMOS device, however, depolulation could be for an NMOS only device or a PMOS only device or a PMOS on NMOS device. It is also to be appreciated that for stacked devices, PMOS to NMOS ribbon spacing can be extended to provide etch variability for the defining partial hardmask etch. Referring again toFIG.1, all of the upper stacked nanoribbons114A,114B,114C and114D (e.g., in this case4) are coupled to the N-type source or drain structures116. However, only the upper two stacked nanoribbons104C and104D are coupled to the P-type source or drain structures106, while the lower two stacked nanoribbons104A and104B are not coupled to the P-type source or drain structures106. The resulting structure effectively depopulates two of the four channel regions of the P-type portion of the CMOS integrated circuit structure100. However, source or drain106depth engineering is required to fabricate CMOS integrated circuit structure100. It is to be appreciated that although the illustrative example of four upper wires and two lower wires and effectively two depopulated nanowires is depicted and described above, it is to be appreciated that all such wire counts may be varied. As a comparison of channel depopulation involving channel count tuning,FIG.2illustrates cross-sectional views (gate cut on fin, and fin cut on gate) representing another gate-all-around integrated circuit structure having a depopulated channel structure. Referring toFIG.2, a CMOS integrated circuit structure200is formed above a substrate202and includes a lower PMOS region and an upper NMOS region. The lower PMOS region includes stacked nanoribbons204A and204B above a raised substrate portion208. P-type source or drain structures206are adjacent the stacked nanoribbons. A lower gate structure includes a gate dielectric layer210having a P-type gate electrode212thereon. The upper NMOS region includes stacked nanoribbons214A,214B,214C and214D. N-type source or drain structures216are adjacent the stacked nanoribbons and above an insulating structure218. An upper gate structure includes a gate dielectric layer220having an N-type gate electrode222thereon. Spacers224may be adjacent to an uppermost portion of the upper gate structure. Referring again toFIG.2, all of the upper stacked nanoribbons214A,214B,214C and214D (e.g., in this case4) are coupled to the N-type source or drain structures216. Also, both of the nanoribbons204A and204B are coupled to the P-type source or drain structures206. However, the lower structure only includes two stacked nanoribbons104A and104B. The resulting structure effectively depopulates two of four channel regions of the P-type portion of the CMOS integrated circuit structure200. However, channel count engineering is required to fabricate CMOS integrated circuit structure200. It is to be appreciated that although the illustrative example of four upper wires and two lower wires and effectively two depopulated nanowires is depicted and described above, it is to be appreciated that all such wire counts may be varied. As an example of a selective bottom-up approach for channel depopulation,FIGS.3A-3Hillustrate cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure having a depopulated channel structure, in accordance with an embodiment of the present disclosure. Referring toFIG.3A, a method of fabricating an integrated circuit structure includes forming a starting structure300including vertical arrangements304of nanowires or nanoribbons306above a substrate302. In the example shown, four vertical arrangements304of “active” nanowires or nanoribbons306are depicted above substrate302. Each vertical arrangement304of active nanowires or nanoribbons306includes semiconductor channel material (306, such as silicon) separated by intervening layers of a sacrificial release material308, such as silicon germanium layers. An oxide layer310, such as a silicon oxide layer, is conformal with each vertical arrangement304of active nanowires or nanoribbons306. A sacrificial mask material312, such as a carbon hardmask material, is over the entire structure. Referring toFIG.3B, the sacrificial mask material312is etched through a patterning mask (not shown) to form a trench316in a patterned sacrificial mask material314. The patterned sacrificial mask material314exposes select ones304A of the vertical arrangement304of active nanowires or nanoribbons306are exposed, while other ones304B of the vertical arrangement304of active nanowires or nanoribbons306are not exposed. In particular, upper nanowires or nanoribbons of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons306are above a bottom of the trench316, while lower nanowires or nanoribbons of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons306are below the bottom of the trench316. Referring toFIG.3C, a conformal liner layer318is formed over the structure ofFIG.3B. In one embodiment, the conformal liner layer318is a dielectric liner such as a silicon nitride layer. In another embodiment, the conformal liner layer318is a metallic layer such as a titanium nitride layer. Referring toFIG.3D, the structure ofFIG.3Cis subjected to an anisotropic etch to portions of the conformal liner layer318to leave patterned conformal liner layer320adjacent to the upper nanowires or nanoribbons of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons306and along sides of the trench316. The process also further patterns the patterned sacrificial mask material314to form twice patterned sacrificial mask material322. It is to be appreciated that deposition characteristics of some materials may be tuned so that they do not deposit on the hardmask (TiN, for example), and therefore do not need to be etched back before the carbon hardmask is etched back. Referring toFIG.3E, exposed portions of the oxide layer310(i.e., those portions not protected by patterned conformal liner layer320and twice patterned sacrificial mask material322) are removed, leaving oxide layer portions310B along the sidewalls of the other ones304B of the vertical arrangement304of active nanowires or nanoribbons306, and leaving oxide layer portions310A along the upper sidewalls of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons306. The patterned conformal liner layer320and the twice patterned sacrificial mask material322are then removed. Referring toFIG.3F, the exposed bottom active nanowires or nanoribbons306A (seeFIG.3E) of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons are oxidized to form oxide nanowires or nanoribbons324. The upper active nanowires or nanoribbons306B (seeFIG.3E) of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons are protected against oxidation by the oxide layer portions310A along the upper sidewalls of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons. Additionally, all nanowires or nanoribbons306of the other ones304B of the vertical arrangement304of active nanowires or nanoribbons are protected against oxidation by the oxide layer portions310B along the sidewalls of the other ones304B of the vertical arrangement304of active nanowires or nanoribbons. In accordance with an embodiment of the present disclosure, oxidation of the exposed bottom active nanowires or nanoribbons306A (seeFIG.3E) of the select ones304A of the vertical arrangement304of active nanowires or nanoribbons is performed using an oxidation catalyst layer formed over the structure ofFIG.3E. In one embodiment, the oxidation catalyst layer is or includes aluminum oxide. In another embodiment, the oxidation catalyst layer is or includes lanthanum oxide. In an embodiment, the oxidation process is a process that can oxidize silicon but at a rate that is substantially enhanced by the presence of the oxidation catalyst. In one such embodiment, the oxidation process is enhanced to rapidly oxidize exposed bottom active nanowires or nanoribbons306A. In an embodiment, the oxidation process involves a wet oxidation anneal, e.g., heating the structure in the presence of water or water vapor. It is to be appreciated that while two upper nanowires are selected to remain active and two lower nanowires are selected for oxidation in the example ofFIG.3F, any suitable number of upper active nanowires may be retained while one or more lower nanowires are oxidized to form oxide nanowires. Referring toFIG.3G, oxide layer portions310A and oxide layer portions310B are removed. A new protective dielectric liner326, such as a new silicon oxide liner, is then formed over the remaining structure. It is also to be appreciated that following the processing described in association withFIG.3Fand/orFIG.3G, the nanowires or nanoribbons can be releases, and permanent gate structures may be fabricated. For example, referring to an integrated circuit structure350FIG.3H, in one exemplary embodiment, permanent gate structures include lower gate dielectrics and corresponding lower P-type gate electrodes thereon (shown as structures354), and upper gate dielectrics and corresponding upper N-type gate electrode thereon (shown as structures356). In another exemplary embodiment, permanent gate structures include lower gate dielectrics and corresponding lower N-type gate electrodes thereon (shown as structures354), and upper gate dielectrics and corresponding upper P-type gate electrode thereon (shown as structures356). Referring again toFIG.3H, nanowire stacks352A include only upper active nanowires306B. The bottom nanowires (shown as absent) are “deactivated” oxide nanowires or ribbons (such as324fromFIG.3G) or are altogether removed (e.g., etched out following the processing ofFIG.3F or3G) to actually be physically absent bottom nanowires. The nanowire stacks352B include all original active nanowires306. In an embodiment, the permanent gate structures are formed around all NW/NR channels, including the oxidized NW/NR channels. In a particular such embodiment, the oxidation catalyst layer is not removed, and the remainder is included in the final structure (e.g., at sides of the oxidized NW/NR channels). In other embodiments, however, the oxidation catalyst layer is removed prior to permanent gate structure fabrication. As mentioned above, in other embodiments, the oxidized NW/NR channels are also removed prior to permanent gate structure fabrication. With reference again toFIG.3H, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires. In an embodiment, the first gate stack includes an N-type gate electrode, and the second gate stack includes a P-type gate electrode. In another embodiment, the first gate stack includes a P-type gate electrode, and the second gate stack includes an N-type gate electrode. In an embodiment, the one or more oxide nanowires have an oxidation catalyst layer thereon, e.g., as a residual layer or artifact layer remaining from a bottom-up channel depopulation process, such as at the sides of the one or more oxide nanowires. In one embodiment, the oxidation catalyst layer includes aluminum oxide. In another embodiment, the oxidation catalyst layer includes lanthanum oxide. In an embodiment, the integrated circuit structure includes epitaxial source or drain structures at ends of the vertical arrangement of nanowires. In one such embodiment, the epitaxial source or drain structures are discrete epitaxial source or drain structures, structural examples of which are described below. In another such embodiment, the epitaxial source or drain structures are non-discrete epitaxial source or drain structures, structural examples of which are described below. In an embodiment, the gate stack has dielectric sidewall spacers, and the epitaxial source or drain structures are embedded epitaxial source or drain structures extending beneath the dielectric sidewall spacers of the gate stack, structural examples of which are described below. In an embodiment, the integrated circuit structure further includes a pair of conductive contact structures coupled to the epitaxial source or drain structures. In one such embodiment, the pair of conductive contact structures is an asymmetric pair of conductive contact structures, structural examples of which are described below. In an embodiment, the vertical arrangement of nanowires is over a fin, structural examples of which are described below. In an embodiment, the gate stack includes a high-k gate dielectric layer and a metal gate electrode. It is to be appreciated that embodiments described herein may be implemented to fabricate nanowire and/or nanoribbon structures having a different number of active wire/ribbon channel. It is to be appreciated that embodiments described herein may involve selective oxidation approaches to achieve such structures. Embodiments described herein may be implemented to enable the fabrication of nanowire/nanoribbon-based CMOS architectures. In an embodiment, in order to engineer different devices having different drive-current strengths, a selective depopulation flow can be patterned with lithography so that ribbons and wires (RAW) are de-populated only from specific devices. In an embodiment, the entire wafer may be de-populated uniformly so all devices have same number of RAW. It is to be appreciated that when de-population is performed through a gate trench, some an epitaxial (epi) source or drain (S/D) materials may be oxidized from the proximate the gate electrode, which is distinct from performing de-population through a S/D location. As mentioned above, nanowire release processing may be performed through a replacement gate trench. Examples of such release processes are described below. Additionally, in another aspect, backend (BE) interconnect scaling can result in lower performance and higher manufacturing cost due to patterning complexity. Embodiments described herein may be implemented to enable front and backside interconnect integration for nanowire transistors. Embodiments described herein may provide an approach to achieve a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance. One or more embodiments described herein are directed dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire/nanoribbon transistors which are partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain side enables direct contact to a backside interconnect level. In an exemplary process flow,FIGS.4A-4Jillustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure. Referring toFIG.4A, a method of fabricating an integrated circuit structure includes forming a starting stack400which includes alternating silicon germanium layer404and silicon layers406above a fin402, such as a silicon fin. The silicon layers406may be referred to as a vertical arrangement of silicon nanowires. A protective cap408may be formed above the alternating silicon germanium layer404and silicon layers406, as is depicted. Referring toFIG.4B, a gate stack410is formed over the vertical arrangement of nanowires406. Portions of the vertical arrangement of nanowires406are then released by removing portions of the silicon germanium layer404to provide recessed silicon germanium layers404′ and cavities412, as is depicted inFIG.4C. It is to be appreciated that the structure ofFIG.4Cmay be fabricated to completion without first performing the deep etch and asymmetric contact processing described below in association withFIG.4D. In either case (e.g., with or without asymmetric contact processing), in an embodiment, a fabrication process involves use of a process scheme that provides a gate-all-around integrated circuit structure having a depopulated channel structure, an example of which is described above in association withFIGS.3A-3H. Referring toFIG.4D, upper gate spacers414are formed at sidewalls of the gate structure410. Cavity spacers416are formed in the cavities412beneath the upper gate spacers414. A deep trench contact etch is then performed to form trenches418and to formed recessed nanowires406′. A sacrificial material420is then formed in the trenches418, as is depicted inFIG.4E. Referring toFIG.4F, a first epitaxial source or drain structure (e.g., left-hand features422) is formed at a first end of the vertical arrangement of nanowires406′. A second epitaxial source or drain structure (e.g., right-hand features422) is formed at a second end of the vertical arrangement of nanowires406′. An inter-layer dielectric (ILD) material424is then formed at the sides of the gate electrode410and adjacent to the source or drain structures422, as is depicted inFIG.4G. Referring toFIG.4H, a replacement gate process is used to form a permanent gate dielectric428and a permanent gate electrode426. In an embodiment, subsequent to removal of gate structure410and form a permanent gate dielectric428and a permanent gate electrode426, the recessed silicon germanium layers404′ are removed to leave upper active nanowires or nanoribbons406′. In an embodiment, the recessed silicon germanium layers404′ are removed selectively with a wet etch that selectively removes the silicon germanium while not etching the silicon layers. Etch chemistries such as carboxylic acid/nitric acid/HF chemistry, and citric acid/nitric acid/HF, for example, may be utilized to selectively etch the silicon germanium. Halide-based dry etches or plasma-enhanced vapor etches may also be used to achieve the embodiments herein. Referring again toFIG.4H, one or more of the bottommost nanowires or nanoribbons406′ is then oxidized to form one or more oxide nanowire or nanoribbons499, e.g., by an approach described in association withFIGS.3A-3H. The permanent gate dielectric428and a permanent gate electrode426is then formed to surround the nanowires or nanoribbons406′ and the one or more oxide nanowire or nanoribbons499. Referring toFIG.4I, the ILD material424is then removed. The sacrificial material420is then removed from one of the source drain locations (e.g., right-hand side) to form trench432, but is not removed from the other of the source drain locations to form trench430. Referring toFIG.4J, a first conductive contact structure434is formed coupled to the first epitaxial source or drain structure (e.g., left-hand features422). A second conductive contact structure436is formed coupled to the second epitaxial source or drain structure (e.g., right-hand features422). The second conductive contact structure436is formed deeper along the fin402than the first conductive contact structure434. In an embodiment, although not depicted inFIG.4J, the method further includes forming an exposed surface of the second conductive contact structure436at a bottom of the fin402. In an embodiment, the second conductive contact structure436is deeper along the fin402than the first conductive contact structure434, as is depicted. In one such embodiment, the first conductive contact structure434is not along the fin402, as is depicted. In another such embodiment, not depicted, the first conductive contact structure434is partially along the fin402. In an embodiment, the second conductive contact structure436is along an entirety of the fin402. In an embodiment, although not depicted, in the case that the bottom of the fin402is exposed by a backside substrate removal process, the second conductive contact structure436has an exposed surface at a bottom of the fin402. In another aspect, in order to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, integrated circuit structures described herein may be fabricated using a back-side reveal of front-side structures fabrication approach. In some exemplary embodiments, reveal of the back-side of a transistor or other device structure entails wafer-level back-side processing. In contrast to a conventional through-Silicon via TSV-type technology, a reveal of the back-side of a transistor as described herein may be performed at the density of the device cells, and even within sub-regions of a device. Furthermore, such a reveal of the back-side of a transistor may be performed to remove substantially all of a donor substrate upon which a device layer was disposed during front-side device processing. As such, a microns-deep TSV becomes unnecessary with the thickness of semiconductor in the device cells following a reveal of the back-side of a transistor potentially being only tens or hundreds of nanometers. Reveal techniques described herein may enable a paradigm shift from “bottom-up” device fabrication to “center-out” fabrication, where the “center” is any layer that is employed in front-side fabrication, revealed from the back side, and again employed in back-side fabrication. Processing of both a front side and revealed back side of a device structure may address many of the challenges associated with fabricating 3D ICs when primarily relying on front-side processing. A reveal of the back-side of a transistor approach may be employed for example to remove at least a portion of a carrier layer and intervening layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a carrier layer in the donor-host substrate is polished (e.g., CMP) and/or etched with a wet or dry (e.g., plasma) etch process. Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the carrier layer may be employed. For example, where the carrier layer is a group IV semiconductor (e.g., silicon) a CMP slurry known to be suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed. In some embodiments, the above is preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intervening layer. The cleaving or fracture process may be utilized to remove a substantial portion of the carrier layer as a bulk mass, reducing the polish or etch time needed to remove the carrier layer. For example, where a carrier layer is 400-900 μm in thickness, 100-700 μm may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly may then be polished or etched to complete removal. Alternatively, where the carrier layer is not fractured, the grind, polish and/or etch operation may be employed to remove a greater thickness of the carrier layer. Next, exposure of an intervening layer is detected. Detection is used to identify a point when the back-side surface of the donor substrate has advanced to nearly the device layer. Any endpoint detection technique known to be suitable for detecting a transition between the materials employed for the carrier layer and the intervening layer may be practiced. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorbance or emission of the back-side surface of the donor substrate during the polishing or etching performed. In some other embodiments, the endpoint criteria are associated with a change in optical absorbance or emission of byproducts during the polishing or etching of the donor substrate back-side surface. For example, absorbance or emission wavelengths associated with the carrier layer etch byproducts may change as a function of the different compositions of the carrier layer and intervening layer. In other embodiments, the endpoint criteria are associated with a change in mass of species in byproducts of polishing or etching the back-side surface of the donor substrate. For example, the byproducts of processing may be sampled through a quadrupole mass analyzer and a change in the species mass may be correlated to the different compositions of the carrier layer and intervening layer. In another exemplary embodiment, the endpoint criteria is associated with a change in friction between a back-side surface of the donor substrate and a polishing surface in contact with the back-side surface of the donor substrate. Detection of the intervening layer may be enhanced where the removal process is selective to the carrier layer relative to the intervening layer as non-uniformity in the carrier removal process may be mitigated by an etch rate delta between the carrier layer and intervening layer. Detection may even be skipped if the grind, polish and/or etch operation removes the intervening layer at a rate sufficiently below the rate at which the carrier layer is removed. If an endpoint criteria is not employed, a grind, polish and/or etch operation of a predetermined fixed duration may stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch. In some examples, the carrier etch rate: intervening layer etch rate is 3:1-10:1, or more. Upon exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be removed uniformly by a polish, for example. Alternatively, a thickness of the intervening layer may be removed with a masked or blanket etch process. The process may employ the same polish or etch process as that employed to thin the carrier, or may be a distinct process with distinct process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polish or etch process that favors removal of the intervening layer over removal of the device layer. Where less than a few hundred nanometers of intervening layer thickness is to be removed, the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled than that employed for removal of the carrier layer. A CHIP process employed may, for example employ a slurry that offers very high selectively (e.g., 100:1-300:1, or more) between semiconductor (e.g., silicon) and dielectric material (e.g., SiO) surrounding the device layer and embedded within the intervening layer, for example, as electrical isolation between adjacent device regions. For embodiments where the device layer is revealed through complete removal of the intervening layer, backside processing may commence on an exposed backside of the device layer or specific device regions there in. In some embodiments, the backside device layer processing includes a further polish or wet/dry etch through a thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region. In some embodiments where the carrier layer, intervening layer, or device layer backside is recessed with a wet and/or plasma etch, such an etch may be a patterned etch or a materially selective etch that imparts significant non-planarity or topography into the device layer back-side surface. As described further below, the patterning may be within a device cell (i.e., “intra-cell” patterning) or may be across device cells (i.e., “inter-cell” patterning). In some patterned etch embodiments, at least a partial thickness of the intervening layer is employed as a hard mask for back-side device layer patterning. Hence, a masked etch process may preface a correspondingly masked device layer etch. The above described processing scheme may result in a donor-host substrate assembly that includes IC devices that have a back side of an intervening layer, a back side of the device layer, and/or back side of one or more semiconductor regions within the device layer, and/or front-side metallization revealed. Additional backside processing of any of these revealed regions may then be performed during downstream processing. It is to be appreciated that the structures resulting from the above exemplary processing schemes may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as CMOS, PMOS and/or NMOS device fabrication. As an example of a completed device,FIG.5illustrate a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. Referring toFIG.5, a semiconductor structure or device500includes a non-planar active region (e.g., a fin structure including protruding fin portion504and sub-fin region505) within a trench isolation region506. In an embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires504A and504B) above sub-fin region505, as is represented by the dashed lines. In either case, for ease of description for non-planar integrated circuit structure500, a non-planar active region504is referenced below as a protruding fin portion. In an embodiment, a fabrication process involves use of a process scheme that provides active regions504as a depopulated channel structure, an example of which is described above in association withFIGS.3A-3H. For example, in one embodiment, lower nanowires504B are oxidized nanowires, and upper nanowires504A are active nanowires. In one embodiment, lower oxide nanowires504B include an oxidation catalyst layer thereon. A gate line508is disposed over the protruding portions504of the non-planar active region (including, if applicable, surrounding nanowires504A and504B), as well as over a portion of the trench isolation region506. As shown, gate line508includes a gate electrode550and a gate dielectric layer552. In one embodiment, gate line508may also include a dielectric cap layer554. A gate contact514, and overlying gate contact via516are also seen from this perspective, along with an overlying metal interconnect560, all of which are disposed in inter-layer dielectric stacks or layers570. Also seen from the perspective ofFIG.5, the gate contact514is, in one embodiment, disposed over trench isolation region506, but not over the non-planar active regions. In an embodiment, the semiconductor structure or device500is a non-planar device such as, but not limited to, a fin-FET device, a tri-gate device, a nano-ribbon device, or a nano-wire device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines508surround at least a top surface and a pair of sidewalls of the three-dimensional body. As is also depicted inFIG.5, in an embodiment, an interface580exists between a protruding fin portion504and sub-fin region505. The interface580can be a transition region between a doped sub-fin region505and a lightly or undoped upper fin portion504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and sub-fin dopants are supplied from an adjacent solid state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide. Although not depicted inFIG.5, it is to be appreciated that source or drain regions of or adjacent to the protruding fin portions504are on either side of the gate line508, i.e., into and out of the page. In one embodiment, the source or drain regions are doped portions of original material of the protruding fin portions504. In another embodiment, the material of the protruding fin portions504is removed and replaced with another semiconductor material, e.g., by epitaxial deposition to form discrete epitaxial nubs or non-discrete epitaxial structures. In either embodiment, the source or drain regions may extend below the height of dielectric layer of trench isolation region506, i.e., into the sub-fin region505. In accordance with an embodiment of the present disclosure, the more heavily doped sub-fin regions, i.e., the doped portions of the fins below interface580, inhibits source to drain leakage through this portion of the bulk semiconductor fins. In an embodiment, the source and drain structures are N-type epitaxial source and drain structures, both including phosphorous dopant impurity atoms. In accordance with one or more embodiments of the present disclosure, the source and drain regions have associated asymmetric source and drain contact structures, as described above in association withFIG.4J. With reference again toFIG.5, in an embodiment, fins504/505(and, possibly nanowires504A and504B) are composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof. In one embodiment, the concentration of silicon atoms is greater than 97%. In another embodiment, fins504/505are composed of a group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. Trench isolation region506may be composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Gate line508may be composed of a gate electrode stack which includes a gate dielectric layer552and a gate electrode layer550. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the protruding fin portions504. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Gate contact514and overlying gate contact via516may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). In an embodiment (although not shown), a contact pattern which is essentially perfectly aligned to an existing gate pattern508is formed while eliminating the use of a lithographic step with exceedingly tight registration budget. In an embodiment, the contact pattern is a vertically asymmetric contact pattern, such as described in association withFIG.4J. In other embodiments, all contacts are front side connected and are not asymmetric. In one such embodiment, the self-aligned approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts. In an embodiment, providing structure500involves fabrication of the gate stack structure508by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid. Referring again toFIG.5, the arrangement of semiconductor structure or device500places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region, e.g., over a sub-fin505, and in a same layer as a trench contact via. It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a gate-all-around (GAA) device, a tri-gate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a sub-10 nanometer (10 nm) technology node. In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods. In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect. In an embodiment, as is also used throughout the present description, hardmask materials, capping layers, or plugs are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer, capping or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hardmask, capping or plug layers known in the arts may be used depending upon the particular implementation. The hardmask, capping or plug layers maybe formed by CVD, PVD, or by other deposition methods. In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion lithography (i193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer. In another aspect, one or more embodiments are directed to neighboring semiconductor structures or devices separated by self-aligned gate endcap (SAGE) structures. Particular embodiments may be directed to integration of multiple width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by a SAGE wall. In an embodiment, nanowires/nanoribbons are integrated with multiple Wsi in a SAGE architecture portion of a front end process flow. Such a process flow may involve integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., portions of nanowires removed and then source or drain (S/D) growth is performed) or formed by vertical merging (e.g., epitaxial regions are formed around existing wires), as described in greater detail below in association withFIGS.9A-9E. To provide further context, advantages of a self-aligned gate endcap (SAGE) architecture may include the enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing. To provide illustrative comparison,FIG.6illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. Referring to the left-hand side (a) ofFIG.6, an integrated circuit structure600includes a substrate602having sub-fins604protruding therefrom within an isolation structure608laterally surrounding the sub-fins604. Corresponding nanowires649and605are over the sub-fins604. In one embodiment, lower nanowires649are oxide nanowires, and upper nanowires605are active nanowires. In one embodiment, lower oxide nanowires649include an oxidation catalyst layer thereon. A gate structure may be formed over the integrated circuit structure600to fabricate a device. However, breaks in such a gate structure may be accommodated for by increasing the spacing between sub-fin604/nanowire649/605pairings. By contrast, referring to the right-hand side (b) ofFIG.6, an integrated circuit structure650includes a substrate652having sub-fins654protruding therefrom within an isolation structure658laterally surrounding the sub-fins654. Corresponding nanowires699and655are over the sub-fins654. In one embodiment, lower nanowires699are oxide nanowires, and upper nanowires655are active nanowires. In one embodiment, lower oxide nanowires699include an oxidation catalyst layer thereon. Isolating SAGE walls660are included within the isolation structure658and between adjacent sub-fin654/nanowire699/655pairings. The distance between an isolating SAGE wall660and a nearest sub-fin654/nanowire699/655pairings defines the gate endcap spacing662. A gate structure may be formed over the integrated circuit structure650, between insolating SAGE walls to fabricate a device. Breaks in such a gate structure are imposed by the isolating SAGE walls. Since the isolating SAGE walls660are self-aligned, restrictions from conventional approaches can be minimized to enable more aggressive diffusion to diffusion spacing. Furthermore, since gate structures include breaks at all locations, individual gate structure portions may be layer connected by local interconnects formed over the isolating SAGE walls660. In an embodiment, as depicted, the SAGE walls660each include a lower dielectric portion and a dielectric cap on the lower dielectric portion, as is depicted. In accordance with an embodiment of the present disclosure, a fabrication process for structures associated withFIG.6involves use of a process scheme that provides a gate-all-around integrated circuit structure having a depopulated channel structure, an example of which is described above in association withFIGS.3A-3H. A self-aligned gate endcap (SAGE) processing scheme involves the formation of gate/trench contact endcaps self-aligned to fins without requiring an extra length to account for mask mis-registration. Thus, embodiments may be implemented to enable shrinking of transistor layout area. Embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls or self-aligned gate endcap (SAGE) walls. In an exemplary processing scheme for structures having SAGE walls separating neighboring devices,FIG.7illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure. Referring to part (a) ofFIG.7, a starting structure includes a nanowire patterning stack704above a substrate702. A lithographic patterning stack706is formed above the nanowire patterning stack704. The nanowire patterning stack704includes alternating silicon germanium layers710and silicon layers712. A protective mask714is between the nanowire patterning stack704and the lithographic patterning stack706. In one embodiment, the lithographic patterning stack706is trilayer mask composed of a topographic masking portion720, an anti-reflective coating (ARC) layer722, and a photoresist layer724. In a particular such embodiment, the topographic masking portion720is a carbon hardmask (CHM) layer and the anti-reflective coating layer722is a silicon ARC layer. Referring to part (b) ofFIG.7, the stack of part (a) is lithographically patterned and then etched to provide an etched structure including a patterned substrate702and trenches730. Referring to part (c) ofFIG.7, the structure of part (b) has an isolation layer740and a SAGE material742formed in trenches730. The structure is then planarized to leave patterned topographic masking layer720′ as an exposed upper layer. Referring to part (d) ofFIG.7, the isolation layer740is recessed below an upper surface of the patterned substrate702, e.g., to define a protruding fin portion and to provide a trench isolation structure741beneath SAGE walls742. Referring to part (e) ofFIG.7, the silicon germanium layers710are removed at least in the channel region to release silicon nanowires712A and712B. In accordance with an embodiment of the present disclosure, a fabrication process for structures associated withFIG.7involves use of a process scheme that provides a gate-all-around integrated circuit structure having a depopulated channel structure, an example of which is described above in association withFIGS.3A-3H. For example, referring to part (e) ofFIG.7, in an embodiment, nanowire712B and nanoribbon712A are an active nanowire and nanoribbon, respectively. In one such embodiment, nanowire799B is an oxide nanowire, and nanoribbon799A is an oxide nanoribbon, as is depicted. In another such embodiment, nanowire799B is an oxide nanowire, and nanoribbon799A is an active nanoribbon. In another such embodiment, nanowire799B is an active nanowire, and nanoribbon799A is an oxide nanoribbon. In any case, in an embodiment, an oxide nanowire or an oxide nanoribbon includes an oxidation catalyst layer thereon. Subsequent to the formation of the structure of part (e) ofFIG.7, one or more gate stacks may be formed around the active and oxide nanowires and/or nanoribbons, over protruding fins of substrate702, and between SAGE walls742. In one embodiment, prior to formation of the gate stacks, the remaining portion of protective mask714is removed. In another embodiment, the remaining portion of protective mask714is retained as an insulating fin hat as an artifact of the processing scheme. Referring again to part (e) ofFIG.7, it is to be appreciated that a channel view is depicted, with source or drain regions being locating into and out of the page. In an embodiment, the channel region including nanowires712B has a width less than the channel region including nanowires712A. Thus, in an embodiment, an integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although structures of712B and712A may be differentiated as nanowires and nanoribbons, respectively, both such structures are typically referred to herein as nanowires. It is also to be appreciated that reference to or depiction of a fin/nanowire pair throughout may refer to a structure including a fin and one or more overlying nanowires (e.g., two overlying nanowires are shown inFIG.7), where one or more bottom wires are oxidized for depopulation. With reference again to part (e) ofFIG.7and the subsequent description, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of active nanowires than the second vertical arrangement of nanowires. The first and second vertical arrangements of nanowires have co-planar uppermost nanowires and co-planar bottommost nanowires. The second vertical arrangement of nanowires has an oxide bottommost nanowire. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires and around the oxide bottommost nanowire. In an embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width the same as a horizontal width of the nanowires of the second vertical arrangement of nanowires. In another embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires. In another embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width less than a horizontal width of the nanowires of the second vertical arrangement of nanowires. To highlight an exemplary integrated circuit structure having three vertically arranged nanowires,FIG.8Aillustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.FIG.8Billustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure ofFIG.8A, as taken along the a-a′ axis.FIG.8Cillustrates a cross-sectional channel view of the nanowire-based integrated circuit structure ofFIG.8A, as taken along the b-b′ axis. Referring toFIG.8A, an integrated circuit structure800includes one or more vertically stacked nanowires (804set) above a substrate802. An optional fin between the bottommost nanowire and the substrate802is not depicted for the sake of emphasizing the nanowire portion for illustrative purposes. Embodiments herein are targeted at both single wire devices and multiple wire devices. As an example, a three nanowire-based devices having nanowires804A,804B and804C is shown for illustrative purposes. For convenience of description, nanowire804A is used as an example where description is focused on one of the nanowires. It is to be appreciated that where attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or essentially the same attributes for each of the nanowires. Each of the nanowires804includes a channel region806in the nanowire. The channel region806has a length (L). Referring toFIG.8C, the channel region also has a perimeter (Pc) orthogonal to the length (L). Referring to bothFIGS.8A and8C, a gate electrode stack808surrounds the entire perimeter (Pc) of each of the channel regions806. The gate electrode stack808includes a gate electrode along with a gate dielectric layer between the channel region806and the gate electrode (not shown). In an embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack808without any intervening material such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments having a plurality of nanowires804, the channel regions806of the nanowires are also discrete relative to one another. In accordance with an embodiment of the present disclosure, a fabrication process for structures associated withFIGS.8A-8Cinvolves use of a process scheme that provides a gate-all-around integrated circuit structure having a depopulated channel structure806, an example of which is described above in association withFIGS.3A-3H. For example, in one embodiment, nanowire804A is an oxide nanowire. In another embodiment, both nanowire804A and nanowire804B are oxide nanowires. In one embodiment, an oxide nanowire includes an oxidation catalyst layer thereon. Referring to bothFIGS.8A and8B, integrated circuit structure800includes a pair of non-discrete source or drain regions810/812. The pair of non-discrete source or drain regions810/812is on either side of the channel regions806of the plurality of vertically stacked nanowires804. Furthermore, the pair of non-discrete source or drain regions810/812is adjoining for the channel regions806of the plurality of vertically stacked nanowires804. In one such embodiment, not depicted, the pair of non-discrete source or drain regions810/812is directly vertically adjoining for the channel regions806in that epitaxial growth is on and between nanowire portions extending beyond the channel regions806, where nanowire ends are shown within the source or drain structures. In another embodiment, as depicted inFIG.8A, the pair of non-discrete source or drain regions810/812is indirectly vertically adjoining for the channel regions806in that they are formed at the ends of the nanowires and not between the nanowires. In an embodiment, as depicted, the source or drain regions810/812are non-discrete in that there are not individual and discrete source or drain regions for each channel region806of a nanowire804. Accordingly, in embodiments having a plurality of nanowires804, the source or drain regions810/812of the nanowires are global or unified source or drain regions as opposed to discrete for each nanowire. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions806, each of the pair of non-discrete source or drain regions810/812is approximately rectangular in shape with a bottom tapered portion and a top vertex portion, as depicted inFIG.8B. In other embodiments, however, the source or drain regions810/812of the nanowires are relatively larger yet discrete non-vertically merged epitaxial structures such as nubs described in association withFIGS.4F-4J. In accordance with an embodiment of the present disclosure, and as depicted inFIGS.8A and8B, integrated circuit structure800further includes a pair of contacts814, each contact814on one of the pair of non-discrete source or drain regions810/812. In one such embodiment, in a vertical sense, each contact814completely surrounds the respective non-discrete source or drain region810/812. In another aspect, the entire perimeter of the non-discrete source or drain regions810/812may not be accessible for contact with contacts814, and the contact814thus only partially surrounds the non-discrete source or drain regions810/812, as depicted inFIG.8B. In a contrasting embodiment, not depicted, the entire perimeter of the non-discrete source or drain regions810/812, as taken along the a-a′ axis, is surrounded by the contacts814. In accordance with an embodiment of the present disclosure, although not depicted, the pair of contacts814is an asymmetric pair of contacts, as described in association withFIG.4J. Referring toFIGS.8B and8C, the non-discrete source or drain regions810/812are global in the sense that a single unified feature is used as a source or drain region for a plurality (in this case, 3) of nanowires804and, more particularly, for more than one discrete channel region806. In an embodiment, the pair of non-discrete source or drain regions810/812is composed of a semiconductor material different than the semiconductor material of the discrete channel regions806, e.g., the pair of non-discrete source or drain regions810/812is composed of a silicon germanium while the discrete channel regions806are composed of silicon. In another embodiment, the pair of non-discrete source or drain regions810/812is composed of a semiconductor material the same or essentially the same as the semiconductor material of the discrete channel regions806, e.g., both the pair of non-discrete source or drain regions810/812and the discrete channel regions806are composed of silicon. Referring again toFIG.8A, in an embodiment, integrated circuit structure800further includes a pair of spacers816. As is depicted, outer portions of the pair of spacers816may overlap portions of the non-discrete source or drain regions810/812, providing for “embedded” portions of the non-discrete source or drain regions810/812beneath the pair of spacers816. As is also depicted, the embedded portions of the non-discrete source or drain regions810/812may not extend beneath the entirety of the pair of spacers816. Substrate802may be composed of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate802includes a lower bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a group III-V compound semiconductor material. An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride is on the lower bulk substrate. Thus, the structure800may be fabricated from a starting semiconductor-on-insulator substrate. Alternatively, the structure800is formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer. In another alternative embodiment, the structure800is formed directly from a bulk substrate and doping is used to form electrically isolated active regions, such as nanowires, thereon. In one such embodiment, the first nanowire (i.e., proximate the substrate) is in the form of an omega-FET type structure. In an embodiment, the nanowires804may be sized as wires or ribbons, as described below, and may have squared-off or rounder corners. In an embodiment, the nanowires804are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single-crystalline. For example, for a silicon nanowire804, a single-crystalline nanowire may be based from a (100) global orientation, e.g., with a <100> plane in the z-direction. As described below, other orientations may also be considered. In an embodiment, the dimensions of the nanowires804, from a cross-sectional perspective, are on the nano-scale. For example, in a specific embodiment, the smallest dimension of the nanowires804is less than approximately 20 nanometers. In an embodiment, the nanowires804are composed of a strained material, particularly in the channel regions806. Referring toFIG.8C, in an embodiment, each of the channel regions806has a width (Wc) and a height (Hc), the width (Wc) approximately the same as the height (Hc). That is, in both cases, the channel regions806are square-like or, if corner-rounded, circle-like in cross-section profile. In another aspect, the width and height of the channel region need not be the same, such as the case for nanoribbons as described throughout. In another aspect, methods of fabricating a nanowire portion of a fin/nanowire integrated circuit structure are provided. For example,FIGS.9A-9Eillustrate three-dimensional cross-sectional views representing various operations in a method of fabricating a nanowire portion of a fin/nanowire structure, in accordance with an embodiment of the present disclosure. A method of fabricating a nanowire integrated circuit structure may include forming a nanowire above a substrate. In a specific example showing the formation of two silicon nanowires,FIG.9Aillustrates a substrate902(e.g., composed of a bulk substrate silicon substrate902A with an insulating silicon dioxide layer902B there on) having a silicon layer904/silicon germanium layer906/silicon layer908stack thereon. It is to be understood that, in another embodiment, a silicon germanium layer/silicon layer/silicon germanium layer stack may be used to ultimately form two silicon germanium nanowires. Referring toFIG.9B, a portion of the silicon layer904/silicon germanium layer906/silicon layer908stack as well as a top portion of the silicon dioxide layer902B is patterned into a fin-type structure910, e.g., with a mask and plasma etch process. It is to be appreciated that, for illustrative purposes, the etch forFIG.9Bis shown as forming two silicon nanowire precursor portions. Although the etch is shown for ease of illustration as ending within a bottom isolation layer, more complex stacks are contemplated within the context of embodiments of the present disclosure. For example, the process may be applied to a nanowire/fin stack as described in association withFIG.7. The method may also include forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length. In a specific example showing the formation of three gate structures over the two silicon nanowires,FIG.9Cillustrates the fin-type structure910with three sacrificial gates912A,912B, and912C thereon. In one such embodiment, the three sacrificial gates912A,912B, and912C are composed of a sacrificial gate oxide layer914and a sacrificial polysilicon gate layer916which are blanket deposited and patterned with a plasma etch process. Following patterning to form the three sacrificial gates912A,912B, and912C, spacers may be formed on the sidewalls of the three sacrificial gates912A,912B, and912C, doping may be performed (e.g., tip and/or source and drain type doping), and an interlayer dielectric layer may be formed to cover the three sacrificial gates912A,912B, and912C. The interlayer dielectric layer may be polished to expose the three sacrificial gates912A,912B, and912C for a replacement gate, or gate-last, process. Referring toFIG.9D, the three sacrificial gates912A,912B, and912C are removed, leaving spacers918and a portion of the interlayer dielectric layer920remaining. Additionally, the portions of the silicon germanium layer906and the portion of the insulating silicon dioxide layer902B of the fin structure910are removed in the regions originally covered by the three sacrificial gates912A,912B, and912C. Discrete portions of the silicon layers904and908thus remain, as depicted inFIG.9D. The discrete portions of the silicon layers904and908shown inFIG.9Dwill, in one embodiment, ultimately become channel regions in a nanowire-based device. Thus, at the process stage depicted inFIG.9D, channel engineering or tuning may be performed. For example, in one embodiment, the discrete portions of the silicon layers904and908shown inFIG.9Dare thinned using oxidation and etch processes. Such an etch process may be performed at the same time the wires are separated by etching the silicon germanium layer906. Accordingly, the initial wires formed from silicon layers904and908begin thicker and are thinned to a size suitable for a channel region in a nanowire device, independent from the sizing of the source and drain regions of the device. Thus, in an embodiment, forming the channel region includes removing a portion of the nanowire, and the resulting perimeters of the source and drain regions (described below) are greater than the perimeter of the resulting channel region. In accordance with an embodiment of the present disclosure, following removal of the three sacrificial gates912A,912B, and912C and removal of the portions of the silicon germanium layer906and the portion of the insulating silicon dioxide layer902B of the fin structure910from the regions originally covered by the three sacrificial gates912A,912B, and912C, a fabrication process is performed that provides a gate-all-around integrated circuit structure having a depopulated channel structure, an example of which is described above in association withFIGS.3A-3H. For example, in one embodiment, nanowire904is an oxide nanowire in the channel region. In one embodiment, an oxide nanowire includes an oxidation catalyst layer thereon. The method may also include forming a gate electrode stack surrounding the entire perimeter of the channel region. In the specific example showing the formation of three gate structures over the two silicon nanowires,FIG.9Eillustrates the structure following deposition of a gate dielectric layer922(such as a high-k gate dielectric layer) and a gate electrode layer924(such as a metal gate electrode layer), and subsequent polishing, in between the spacers918. That is, gate structures are formed in the trenches921ofFIG.9D. Additionally,FIG.9Edepicts the result of the subsequent removal of the interlayer dielectric layer920after formation of the permanent gate stack. The portions of the silicon germanium layer906and the portion of the insulating silicon dioxide layer902B of the fin structure910are also removed in the regions originally covered by the portion of the interlayer dielectric layer920depicted inFIG.9D. Discrete portions of the silicon layers904and908thus remain, as depicted inFIG.9E. The method may also include forming a pair of source and drain regions in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region. Specifically, the discrete portions of the silicon layers904and908shown inFIG.9Ewill, in one embodiment, ultimately become at least a portion of the source and drain regions in a nanowire-based device. In one such embodiment, epitaxial source or drain structures are formed by merging epitaxial material around existing nanowires904and908. In another embodiment, epitaxial source or drain structures are embedded, e.g., portions of nanowires904and908are removed and then source or drain (S/D) growth is performed. In the latter case, in accordance with an embodiment of the present disclosure, such epitaxial source or drain structures may be non-discrete, as exemplified in association withFIGS.8A and8B, or may be discrete, as exemplified in association withFIG.4J. In either case, in one embodiment, source or drain structures are N-type epitaxial source or drain structures, both including phosphorous dopant impurity atoms. The method may subsequently include forming a pair of contacts, a first of the pair of contacts completely or nearly completely surrounding the perimeter of the source region, and a second of the pair of contacts completely or nearly completely surrounding the perimeter of the drain region. In an embodiment, the pair of contacts is an asymmetric pair of source and drain contact structures, such as described in association withFIG.4J. In other embodiments, the pair of contacts is a symmetric pair of source and drain contact structures. Specifically, contacts are formed in the trenches925ofFIG.9Efollowing epitaxial growth. One of the trenches may first be recessed further than the other of the trenches. In an embodiment, the contacts are formed from a metallic species. In one such embodiment, the metallic species is formed by conformally depositing a contact metal and then filling any remaining trench volume. The conformal aspect of the deposition may be performed by using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow. In an embodiment, as described throughout, an integrated circuit structure includes non-planar devices such as, but not limited to, a finFET or a tri-gate device with corresponding one or more overlying nanowire structures. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, the gate structures surround at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions. In an embodiment, as described throughout, a substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. A bulk substrate may alternatively be composed of a group III-V material. In an embodiment, a bulk substrate is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is composed of a group III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. In an embodiment, as described throughout, a trench isolation layer may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, a trench isolation layer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In an embodiment, as described throughout, self-aligned gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another. Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide. Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein. FIG.10illustrates a computing device1000in accordance with one implementation of an embodiment of the present disclosure. The computing device1000houses a board1002. The board1002may include a number of components, including but not limited to a processor1004and at least one communication chip1006. The processor1004is physically and electrically coupled to the board1002. In some implementations the at least one communication chip1006is also physically and electrically coupled to the board1002. In further implementations, the communication chip1006is part of the processor1004. Depending on its applications, computing device1000may include other components that may or may not be physically and electrically coupled to the board1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The communication chip1006enables wireless communications for the transfer of data to and from the computing device1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip1006may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device1000may include a plurality of communication chips1006. For instance, a first communication chip1006may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip1006may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor1004of the computing device1000includes an integrated circuit die packaged within the processor1004. The integrated circuit die of the processor1004may include one or more structures, such as gate-all-around integrated circuit structures having depopulated channel structures built in accordance with implementations of embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip1006also includes an integrated circuit die packaged within the communication chip1006. The integrated circuit die of the communication chip1006may include one or more structures, such as gate-all-around integrated circuit structures having depopulated channel structures built in accordance with implementations of embodiments of the present disclosure. In further implementations, another component housed within the computing device1000may contain an integrated circuit die that includes one or structures, such as gate-all-around integrated circuit structures having depopulated channel structures built in accordance with implementations of embodiments of the present disclosure. In various implementations, the computing device1000may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device1000may be any other electronic device that processes data. FIG.11illustrates an interposer1100that includes one or more embodiments of the present disclosure. The interposer1100is an intervening substrate used to bridge a first substrate1102to a second substrate1104. The first substrate1102may be, for instance, an integrated circuit die. The second substrate1104may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1100is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1100may couple an integrated circuit die to a ball grid array (BGA)1106that can subsequently be coupled to the second substrate1104. In some embodiments, the first and second substrates1102/1104are attached to opposing sides of the interposer1100. In other embodiments, the first and second substrates1102/1104are attached to the same side of the interposer1100. And, in further embodiments, three or more substrates are interconnected by way of the interposer1100. The interposer1100may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer1100may include metal interconnects1108and vias1110, including but not limited to through-silicon vias (TSVs)1112. The interposer1100may further include embedded devices1114, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1100. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer1100or in the fabrication of components included in the interposer1100. Thus, embodiments of the present disclosure include gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures. The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. Example embodiment 1: An integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires. Example embodiment 2: The integrated circuit of example embodiment 1, wherein the one or more oxide nanowires have an oxidation catalyst layer thereon. Example embodiment 3: The integrated circuit of example embodiment 2, wherein the oxidation catalyst layer includes aluminum oxide. Example embodiment 4: The integrated circuit of example embodiment 1, 2 or 3, further including epitaxial source or drain structures at ends of the vertical arrangement of nanowires. Example embodiment 5: The integrated circuit of example embodiment 4, wherein the epitaxial source or drain structures are discrete epitaxial source or drain structures. Example embodiment 6: The integrated circuit of example embodiment 4, wherein the epitaxial source or drain structures are non-discrete epitaxial source or drain structures. Example embodiment 7: The integrated circuit of example embodiment 4, 5 or 6, wherein the gate stack has dielectric sidewall spacers, and the epitaxial source or drain structures are embedded epitaxial source or drain structures extending beneath the dielectric sidewall spacers of the gate stack. Example embodiment 8: The integrated circuit of example embodiment 4, 5, 6 or 7, further including a pair of conductive contact structures coupled to the epitaxial source or drain structures. Example embodiment 9: The integrated circuit of example embodiment 8, wherein the pair of conductive contact structures is an asymmetric pair of conductive contact structures. Example embodiment 10: The integrated circuit of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the vertical arrangement of nanowires is over a fin. Example embodiment 11: The integrated circuit of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein the gate stack includes a high-k gate dielectric layer and a metal gate electrode. Example embodiment 12: The integrated circuit of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the first gate stack includes an N-type gate electrode, and the second gate stack includes a P-type gate electrode. Example embodiment 13: The integrated circuit of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the first gate stack includes a P-type gate electrode, and the second gate stack includes an N-type gate electrode. Example embodiment 14: A method of fabricating an integrated circuit structure includes forming a vertical arrangement of active nanowires above a substrate, oxidizing one or more bottommost nanowires of the vertical arrangement of active nanowires but not one or more uppermost nanowires of the vertical arrangement of active nanowires, forming a lower gate stack over and around the oxidized one or more bottommost nanowires, and forming an upper gate stack over and around the one or more uppermost nanowires of the vertical arrangement of active nanowires. Example embodiment 15: The method of embodiment 14, wherein oxidizing the one or more bottommost nanowires of the vertical arrangement of active nanowires includes first forming an oxidation catalyst layer on the one or more bottommost nanowires. Example embodiment 16: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure. The integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires. Example embodiment 17: The computing device of example embodiment 16, further including a memory coupled to the board. Example embodiment 18: The computing device of example embodiment 16 or 17, further including a communication chip coupled to the board. Example embodiment 19: The computing device of example embodiment 16, 17 or 18, further including a camera coupled to the board. Example embodiment 20: The computing device of example embodiment 16, 17, 18 or 19, further including a battery coupled to the board. Example embodiment 21: The computing device of example embodiment 16, 17, 18, 19 or 20, further including an antenna coupled to the board. Example embodiment 22: The computing device of example embodiment 16, 17, 18, 19, 20 or 21, wherein the component is a packaged integrated circuit die. | 101,622 |
11862637 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Multi-threshold voltage IC devices are sometimes used to optimize delay or power in various circuits and devices. A multi-threshold voltage IC device may include several different devices, each having a different threshold voltage (i.e., operating voltage). For example, the multi-threshold voltage IC device may include two or more of a low threshold voltage (LVT) device, a standard threshold voltage (SVT) device and a high threshold voltage (HVT) device. Adjacent devices, including adjacent multi-threshold IC devices such as multi-threshold FinFETs, may be electrically isolated using one or more isolation devices. Such an isolation device may be referred to as a “tie-off” device. In some examples, a transistor is configured as an isolation device, where the active area of the tie-off device is set to an off state. A gate of an isolation device (a “tie-off gate”) may be biased to place the isolation device in an off state and provide isolation for an adjacent active device. For instance, a tie-off device may be situated at a threshold voltage (VT) boundary between devices. In accordance with some disclosed embodiments, a poly gate for a tie-off transistor is positioned at VT boundary of mixed VT structure. The transistor may be tied off by a conductive via connecting the poly gate to a power rail maintain the device in an off state. Positioning the poly gate at the VT boundary and directly connecting the poly gate to the power rail by the via may save device area. FIG.1is a block diagram illustrating a cross-section of an example semiconductor structure10in accordance with some embodiments. The structure10is shown in the X-axis and Z-axis directions inFIG.1, while the Y-axis direction is orthogonal to the plane of the cross-section illustrated inFIG.1. The structure10includes a base layer12and an interconnect layer14. Generally, the base layer12includes a semiconductor substrate that, in turn, includes polysilicon regions (also termed “poly” throughout this disclosure), diffusion regions, semiconductor wells (e.g., N-wells, P-wells, deep N-wells, deep P-wells), etc., wherein semiconductor devices (e.g., transistors, diodes, etc.) are formed. The interconnect layer14includes N (e.g., an integer number of) conductive layers (e.g., metal layers M1to MN) used for interconnecting devices within layers in interconnect layer120and for forming electrical connections to external devices, etc. The interconnect layer14generally includes vias, inter-level dielectric materials, passivation layers, bonding pads, packaging resources, etc. Each metal (e.g., conductive) layer M in the interconnect layer14is commonly called metal one, metal two, metal three (M1, M2, M3, etc) layers, etc. Between the various metal layers M are dielectric materials (e.g., high-K, low-K material, etc.)16used to insulate the metal layers M. The base layer12and interconnect layer14are often called a front-end structure and a backend structure, respectively, because they are the respective “front end of line” (FEOL) and “back end of line” (BEOL) in the semiconductor fabrication process. FIG.2is a block diagram illustrating an example interconnect metal layer structure20in accordance with some embodiments. The metal layer structure20includes a plurality of conductive layers M (e.g., M1, M2, M3, etc.). In the embodiment shown, the metal layer structure20illustrates only two layers (e.g., M2and M3). Metal layer structures having different numbers of layers, e.g., from 1 to N layers, are within the scope of the disclosed embodiments. In the embodiment shown inFIG.2, each metal layer M includes a plurality of metal bars MB, for example, metal bars MB21, MB22, and MB23in layer M2and metal bars MB31, MB32, MB33in layer M3. In some embodiments, the shape of the metal bars is cylindrical or some other shape, and can be any cross-sectional shape. In the embodiment shown, each of the metal bars MB in a layer M are substantially parallel to one another. In the embodiment shown, each metal layer M2and M3includes three metal bars MB, however, configurations having different numbers of metal bars MB per metal layer M are within the scope of the disclosed embodiments. In some embodiments, a first set of metal bars MB (e.g., metal bars MB in metal layers M1, M3, M5, etc.) run in a first direction (e.g., X-axis direction) while a second set of metal bars MB (e.g., in metal layers M2, M4, M6, etc.) run in a second direction (e.g., Y-axis direction) wherein the X-axis direction is perpendicular to the Y-axis direction. Different configurations wherein all bars MB run in one direction, e.g., X-axis direction, Y-axis direction, or any other convenient direction, or a combination of directions, including non-perpendicular directions, are within the scope of the disclosed embodiments. In the embodiment shown inFIG.2, each metal bar MB has a width Wbar. In some embodiments, all widths Wbar are of the same dimension, but the disclosed embodiments are not limited to such a configuration. Depending on design choices, the widths Wbar may be of different dimensions (e.g., one width Wbar may be shorter/larger than another one). Two adjacent metal bars MB are spaced or separated by a distance, e.g., distance D. In some embodiments, distances D are selected to meet the minimum requirements of spacing between two metal bars MB to form capacitance between those two bars. In some embodiments, all distances D in the metal layer structure20are of the same dimension, but the disclosed embodiments are not limited to such a configuration. That is, distances D may be of different dimensions (e.g., one distance D may be shorter/longer than another one). The thickness of a metal bar MB in a layer M is proportional to the layer M thickness, which can be process technology dependent, and different groups of layers M can have different thicknesses. For example, a first group of metal layers M (e.g., Mx) can have a first thickness, a second group of metal layer M (e.g., My) can have a second thickness, and a third group of metal layers (e.g., Mz) can have a third thickness, etc, wherein the first, the second, and the third thickness are different. In the embodiment shown, the metal layer structure20has a width W and a length L. FIG.3is a block diagram illustrating a cross-section of an example semiconductor structure30in accordance with some embodiments. The embodiment shown includes a FEOL layer including semiconductor structures and a BEOL layer including interconnect metal layer structures. In the embodiment shown, the FEOL layer includes a FinFET transistor32. The FinFET transistor32includes a semiconductor substrate34, a fin36, an isolation region38, a polysilicon structure, e.g. poly40, the conductive contacts S and D connected to the fin, and the conductive contact G connected to the poly40. In the embodiment shown, the conduction path for current is the fin36(the fin can also be referred to as an active area or region). The poly40functions as a gate allowing current flow in the fin from the S (e.g. source) contact to the D (e.g. drain) contact. In general, such a gate structure includes one or more conductive segments including one or more conductive materials such as the poly noted above. Other gate materials could include one or more metals, doped polysilicon, and/or other conductive materials. The conductive segments are thus configured to control a voltage provided to an underlying dielectric layer. In various embodiments, the gate dielectric layer includes, for example, one or more of silicon dioxide and/or a high-k dielectric material, e.g., a dielectric material having a k value higher than 3.8 or 7.0. In some embodiments, a high-k dielectric material includes aluminum oxide, hafnium oxide, lanthanum oxide, or another suitable material. For example, for a voltage potential between the S and D contacts, current can flow in the fin from S to D depending on a voltage applied to the poly40. If a voltage less than a threshold voltage (VT) is applied to the poly40, then appreciable current cannot flow in the fin from the S to the D contacts, and the transistor32is “off” If a voltage greater than or equal to the VT is applied to the poly40, appreciable current flows from S to D via the fin and the transistor32is “on.” In some embodiments, the S, D, and G contacts form connections between multiple fins and polys in the FEOL layer, thereby connecting the sources, drains, and gates of one or more transistors. In some embodiments, the sources, drains, and gates of the transistor32are connected to an interconnect metal layer structure in the BEOL layer. For example, the gate of the transistor32may be connected to other structures by one or more of the metal bars in one of the layers of the interconnect metal structure in the BEOL layer, and the S/D contacts of the transistor32may be similarly be connected to other structures using other ones of the metal bars in one or more of the metal layers in the BEOL layer. In some embodiments, the BEOL layer serves to connect the transistor32to peripheral circuits. In the embodiment shown, the D, and G contacts connect to the metal bars in the BEOL layer using vias. For example, Via1forms a connection between the D contact to a metal bar in the first metal layer M1above the FEOL layer. In the embodiment shown, a separate Via1connects the G contact to a conductive landing pad in the M1layer, and Via2connects the conductive landing pad to a metal bar in the M2layer. FIG.4illustrates an example of an integrated circuit device100in accordance with disclosed aspects. In general, the device100may include FinFET structures such as those shown inFIGS.1-3. The device100shown inFIG.4includes a first power rail112, such as a VDD or VSS power rail. In the example ofFIG.4, the power rail112is the VDD rail. A first active area110extends in the X-axis direction. In some examples, the active area110include a fin such as the fin36shown inFIG.3. A plurality of poly gates120contact the active area110and extend in the Y-axis direction. In other words, the poly gates120extend generally perpendicular to the active area110. In the example illustrated inFIG.4, the plurality of poly gates120includes five poly gates labeled120a-120e. A first transistor130is formed by the first active area110and a first one of the poly gates120a, and a second transistor132is formed by the first active area110and a second one of the poly gates120b. In the illustrated example, the first transistor130has a first VT, and the second transistor132has a second VT different than the first VT. The device100thus includes a continuous active area110that defines two different VT levels. In the illustrated embodiment, the active area110includes a first VT region140and a second VT region142. For example, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. Thus, for example, the first transistor130may have a standard VT (SVT) and the second transistor132may have a low VT (LVT). Multiple VT devices may achieve a better power efficiency in some IC devices. In some examples, the active area110is fabricated to have different VT characteristics by using channel and/or halo implantation optimization. For example, a HVT device may be achieved by heavily implanting the device channel/halo pockets including ion implantation and a thermal anneal. A tie-off transistor134is positioned between the first transistor130and the second transistor134. The tie-off transistor134is formed by the first active area110and a third one of the poly gates120c. The third poly gate120cof the tie-off transistor134is connected to the power rail112maintain the tie-off transistor in an off state. The tie-off transistor134is configured to electrically isolate the first transistor130having the first VT from the second transistor132having the second TV. In the example illustrated inFIG.1, the first and second transistors130,132and the tie-off transistor134are PMOS transistors. The PMOS tie-off transistor134has its poly gate120cconnected to the VDD power rail112by a conductive via122to keep the tie-off transistor134off to electrically isolate the first transistor130from the second transistor132. In some examples, the tie-off transistor134may be situated at the boundary of the first and second VT regions140,142. As such, the poly gate120cthat connects the tie-off transistor134to the VDD rail112extends along the Y-axis direction directly over the VT boundary. Connecting the tie-off transistor to the power rail112using the poly gate120csaves area as compared to using a metal line for the tie-off device. In the example ofFIG.4, the poly gates120dand120emay be continuous poly on oxide definition edge (CPODE) patterns. In some implementations, an IC device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, device packing density and device performance are challenged by device layout and isolation. In order to avoid leakage between neighboring devices, poly segments may be formed on edges of an active region such as the fin110in a FinFET. Such poly segments are sometimes also referred to as a poly-on-OD-edge (PODE). The PODE helps to achieve better device performance and better poly profile control. In some embodiments, the PODE structures are formed on the edge of the device100, and are used to protect the ends of the fin110during processing. That is, the PODE polysilicon structures are not electrically connected as gates for the transistors but are instead “dummy” structures, having no function in the circuit. The PODE structures cover and protect the ends of the fin110, providing additional reliability during processing. In general, the number of poly gates120in contact with the fin110can be considered to be the “pitch,” often termed the “contacted poly pitch” or CPP, of the IC device along one dimension. The CPP may be at least partially determinative of the density of the IC device. By positioning the poly gate120cof the tie-off transistor134directly over the VT region boundary, the poly gate120cis “shared” by both the first and second VT regions140,142rather than requiring a separate poly lines for separate tie off devices in each of the first and second VT regions140,142. As such, one poly pitch may be eliminated in the disclosed examples, resulting in a 5 CPP device. FIG.5illustrates another example integrated circuit device101in accordance with disclosed aspects. The device101shown inFIG.5is similar to the device100ofFIG.4, though the device101includes a second power rail114, which is the VSS power rail in the illustrated example, and rather than including PMOS transistors as in the device100ofFIG.4,FIG.5discloses NMOS transistors. As with the device100disclosed above, the device101includes an active area or fin111that extends in the X-axis direction. The plurality of poly gates120contact the active area111and extend in the Y-axis direction such that the poly gates120extend generally perpendicular to the active area111. The plurality of poly gates120illustrated inFIG.5are again labeled120a-120e. In other words, the device101is also a five CPP structure. A first NMOS transistor131having the first VT is formed by the active area111and the first poly gate120a, and a second NMOS transistor133having the second VT is formed by the active area111and the second poly gate120b. The device101thus includes the continuous active area111with the first VT region140and the second VT region142. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. A tie-off transistor135is positioned between the first NMOS transistor131and the second NMOS transistor133. The tie-off transistor135is formed by the active area111and the third poly gate120c. In the example illustrated inFIG.5, the tie-off transistor135is an NMOS transistor with the poly gate120cconnected to the VSS power rail114by a conductive via123to keep the tie-off transistor135off to electrically isolate the first NMOS transistor131from the second NMOS transistor133. The tie-off transistor135is situated at the boundary of the first and second VT regions140,142. FIG.6illustrates an embodiment of an integrated circuit device102that includes both PMOS and NMOS transistors with tie-off transistors having poly gates coupled to the VDD and VSS power rails. As such, the device102includes the first and second fins110,111that define a PMOS region150and NMOS region152. The device102includes the first and second power rails112,114, which are the VDD and VSS power rails, respectively, in the illustrated example. The active areas or fins110and111extend in the X-axis direction. The plurality of poly gates120contact the active area111and extend in the Y-axis direction such that the poly gates120extend generally perpendicular to the active areas110,111. The device102has five poly gates120a-120eand is thus also a five CPP structure. The PMOS region150includes the first PMOS transistor130formed by the first active area110and the first poly gate120a, and the second PMOS transistor132formed by the first active area110and the poly gate120b. The first NMOS transistor131is formed by the active area111and the first poly gate120a, and the second NMOS transistor133is formed by the active area111and the second poly gate120b. The device102includes the continuous active areas110,111with the first VT region140and the second VT region142. Accordingly, the first PMOS transistor130and the first NMOS transistor131have the first VT, while the second PMOS transistor134and the second NMOS transistor135have the second VT. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. The tie-off transistors134and135are formed by the active areas110,111and the third poly gate120c, and are positioned at the border of the first and second VT regions140,142. As such, the PMOS tie-off transistor134is positioned between the first and second PMOS transistors130,132, and the NMOS tie-off transistor135is positioned between the first and second NMOS transistors131,133. In the example illustrated inFIG.6, the tie-off transistor134is a PMOS transistor and the tie-off transistor135is an NMOS transistor. The poly gate120cconnected to the VDD power rail by the conductive via122and to the VSS power rail114by the conductive via123. The poly gate120is patterned or cut at a separation154such that the upper portion of the poly gate120cconnects the PMOS tie-off transistor134to the VDD rail112, but does not connect the gate of the PMOS tie-off transistor134to the VSS terminal. The lower portion of the poly gate120cconnects the NMOS tie-off transistor135to the VSS rail114, but does not connect the gate of the NMOS tie-off transistor135to the VDD terminal. In other words, the poly gate120cdoes not directly connect or short the VDD rail to the VSS rail. In this manner, both tie-off transistors134and135are kept in an off state to electrically isolate the first and second PMOS transistors130,132from each other, and the first and second NMOS transistors131,133from each other. In the devices100-102shown inFIGS.4-6, the poly gates120cfor each of the tie-off transistors134,135connect to the power rails112or114by the conductive vias122or123. More particularly, the conductive vias122and123extend directly from the poly gate120cto the respective power rails.FIG.7illustrates an example integrated circuit device103in accordance with further embodiments, where the poly gate of the tie-off transistor connects to the power rail through one or more metal connectors. The device103shown inFIG.7includes the first (VDD) power rail112and has PMOS transistors. The first active area or fin110extends in the X-axis direction, and the poly gates120contact the active area110and extend in the Y-axis direction. In the example illustrated inFIG.7, the plurality of poly gates120again includes five poly gates labeled120a-120e. The first PMOS transistor130in the first VT region140is formed by the first active area110and the first poly gate120a, and the second PMOS transistor132in the second VT region142is formed by the first active area110and the second poly gate120b. Thus, the first transistor130has the first VT, and the second transistor132has the second VT different than the first VT as described above. The PMOS tie-off transistor134is positioned between the first PMOS transistor130and the second PMOS transistor132. The tie-off transistor134is formed by the first active area110and the poly gate120c. The poly gate120cof the tie-off transistor134is connected to the power rail112to maintain the tie-off transistor in an off state. More specifically, in the example shown inFIG.7a conductive via124connects the poly gate120cto a metal conductor or metal bar in one of the metal layers160such as the M0metal layer. In the illustrated example, the M0metal layer160extends in the X-axis direction. The metal layer160is connected to a metal strip162(such as a metal deposit over the active area110) by a conductive via125, and the metal strip162connects to the VDD rail112by another conductive via126. In the illustrated example, the metal strip162extends in the Y-axis direction. Thus, the poly gate120cis connected to the VDD rail112by the M0metal layer160and the metal strip162to maintain the tie-off transistor134in an off state for isolating the PMOS transistors130,132from one another. FIG.8illustrates another example where the poly gate of the tie-off transistor connects to the power rail through one or more metal connectors. The device104shown inFIG.8includes the second (VSS) power rail114and has NMOS transistors. The active area or fin111extends in the X-axis direction, and the poly gates120contact the active area111and extend in the Y-axis direction. In the example illustrated inFIG.8, the plurality of poly gates120again includes five poly gates labeled120a-120e. The first NMOS transistor131in the first VT region140is formed by the first active area111and the first poly gate120a, and the second NMOS transistor133in the second VT region142is formed by the active area111and the second poly gate120b. Thus, the first NMOS transistor131has the first VT, and the second NMOS transistor133has the second VT different than the first VT as described above. The NMOS tie-off transistor135is positioned between the first NMOS transistor131and the second NMOS transistor133. The tie-off transistor135is formed by the active area111and the poly gate120c, which is connected to the VSS power rail114to maintain the NMOS tie-off transistor135in an off state. More specifically, in the example shown inFIG.8a conductive via124connects the poly gate120cto the M0metal layer160. The metal layer160is connected to a metal strip162(such as a metal deposit over the active area110) by a conductive via125, and the metal strip162connects to the VSS rail114by a conductive via127. Thus, the poly gate120cis connected to the VSS rail114by the M0metal layer160and the metal strip162to maintain the NMOS tie-off transistor135in an off state for isolating the NMOS transistors131,133from one another. FIGS.9and10illustrate example devices that use a “soft” connection of tie-off transistors to the appropriate power rails. For instance,FIG.9illustrates a device105that includes the first and second fins110,111that define the PMOS region150and the NMOS region152. The device105includes the first and second power rails112,114, which are the VDD and VSS power rails, respectively, in the illustrated example. The active areas or fins110and111extend in the X-axis direction. The plurality of poly gates120contact the active area111and extend in the Y-axis direction such that the poly gates120extend generally perpendicular to the active areas110,111. The device105has five poly gates120a-120eand is thus also a five CPP structure. The PMOS region150includes the first PMOS transistor130formed by the first active area110and the first poly gate120a, and the second PMOS transistor132formed by the first active area110and the poly gate120b. The first NMOS transistor131is formed by the active area111and the first poly gate120a, and the second NMOS transistor133is formed by the active area111and the second poly gate120b. The device105includes the continuous active areas110,111with the first VT region140and the second VT region142. Accordingly, the first PMOS transistor130and the first NMOS transistor131have the first VT, while the second PMOS transistor134and the second NMOS transistor135have the second VT. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. In the embodiment ofFIG.9, the conductive via127connects the VSS rail114to the poly gate120aof the first PMOS transistor130. Therefore, the first PMOS transistor130is always on. However metal line162MD is connected to VDD by a conductive via128, and the poly gate120bof the second PMOS transistor132is connected to the metal line164through the M0metal layer160. The second poly gate132includes the cut poly154. As such, the VDD voltage leaks to the drain side of the PMOS transistor130from its source. The “leaked” VDD voltage is so referred to as a “soft” VDD connection, which ties off the PMOS transistor132. Similarly,FIG.10illustrates a device106that includes the first and second fins110,111that define the PMOS region150and the NMOS region152. The device106includes the first and second power rails112,114, which are the VDD and VSS power rails, respectively, in the illustrated example. The active areas or fins110and111extend in the X-axis direction. The plurality of poly gates120contact the active area111and extend in the Y-axis direction such that the poly gates120extend generally perpendicular to the active areas110,111. The device106has five poly gates120a-120eand is thus also a five CPP structure. The PMOS region150includes the first PMOS transistor130formed by the first active area110and the first poly gate120a, and the second PMOS transistor132formed by the first active area110and the poly gate120b. The first NMOS transistor131is formed by the active area111and the first poly gate120a, and the second NMOS transistor133is formed by the active area111and the second poly gate120b. The device106includes the continuous active areas110,111with the first VT region140and the second VT region142. Accordingly, the first PMOS transistor130and the first NMOS transistor131have the first VT, while the second PMOS transistor134and the second NMOS transistor135have the second VT. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. In the embodiment ofFIG.10, the conductive via126connects the VDD rail112to the poly gate120aof the first NMOS transistor131. Therefore, the first NMOS transistor131is always on. The metal line162is connected to the VSS rail114by a conductive via129, and the poly gate120bof the second NMOS transistor133is connected to the metal line164through the M0metal layer160. The second poly gate120bincludes the cut poly154. As such, the VSS voltage leaks to the drain side of the NMOS transistor131from its source. The “leaked” VSS voltage is so referred to as a “soft VSS” connection, which ties off the NMOS transistor133. FIG.11illustrates a method in accordance with disclosed embodiments. The illustrated method200provides a tie-off device. More particularly, the method includes forming a first active area on a substrate at step210. The first active area, such as the fin110, has a first VT region140and a second VT region142. At step212, a first gate120ais formed that contacts the first VT region140of the first active area to form a first transistor having a first VT. In some examples, the first transistor may be a PMOS transistor such as the PMOS transistor130, or an NMOS transistor such as the NMOS transistor131shown inFIGS.4-10. A second gate120bis formed at step214that contacts the second VT region142of the first active area110to form a second transistor having a second VT that is different than the first VT. In some examples, the second transistor may be a PMOS transistor such as the PMOS transistor132, or an NMOS transistor such as the NMOS transistor133shown inFIGS.4-10. A third gate120cis formed at step216to contact the first active area110between the first gate120aand the second gate120bto form a tie-off transistor positioned between the first transistor and the second transistor. In some examples, the tie-off transistor may be a PMOS transistor such as the PMOS tie-off transistor134, or an NMOS tie-off transistor such as the NMOS tie-off transistor135shown inFIGS.4-10. At step218, the third gate120cis connected to a power rail, such as the VDD or VSS power rails, to maintain the tie-off transistor134in an off state and thus electrically isolating the first transistor from the second transistor. In some embodiments, some or all of the method200is executed by a processor of a computer. In some embodiments, some or all of the method200is executed by a processor302of an EDA system300, discussed below with respect toFIG.12. Some or all of the operations of the method200are capable of being performed as part of a design procedure performed in a design house, such as the design house320discussed below with respect toFIG.13. FIG.12is a block diagram of an electronic design automation (EDA) system700, in accordance with some embodiments. In some embodiments, the EDA system300includes an automated place and route (APR) system. In some embodiments, the EDA system300is a general purpose computing device including a processor302and a non-transitory, computer-readable storage medium304. The computer-readable storage medium304, may be encoded with, for example, stores, computer program code306, i.e., a set of executable instructions. Execution of instructions306by the processor302represents (at least in part) an EDA tool which implements a portion or all of, e.g., the method200described above with respect toFIG.11(hereinafter, the noted processes and/or methods). Further, fabrication tools303may be included for layout and physical implementation of IC devices in accordance with methods disclosed herein such as the method200ofFIG.11. The processor302is electrically coupled to the computer-readable storage medium304via a bus308. The processor302is also electrically coupled to an I/O interface310by the bus308. A network interface312is also electrically connected to the processor302via the bus308. The network interface312is connected to a network314, so that the processor302and the computer-readable storage medium304are capable of connecting to external elements via the network314. The processor302is configured to execute the computer program code306encoded in the computer-readable storage medium304in order to cause the system300to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, the processor302is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, the computer-readable storage medium304is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer-readable storage medium304includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium304includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, the computer-readable storage medium304stores computer program code306configured to cause the system300to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, the computer-readable storage medium304also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, the computer-readable storage medium304stores a library307of standard cells including the various IC devices disclosed herein. The EDA system300includes an I/O interface310. The I/O interface310is coupled to external circuitry. In one or more embodiments, the I/O interface310includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to the processor302. The EDA system300also includes a network interface312coupled to the processor302. The network interface312allows the system300to communicate with the network314, to which one or more other computer systems are connected. The network interface312includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems300. The system300is configured to receive information through an I/O interface310. The information received through the I/O interface310includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor302. The information is transferred to the processor302via the bus308. The EDA system300is configured to receive information related to a UI through the I/O interface310. The information is stored in the computer-readable medium304as a user interface (UI)342. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by the EDA system300. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. As noted above, embodiments of the EDA system300may include fabrication tools303for implementing the processes and/or methods stored in the storage medium304. For instance, a synthesis may be performed on a design in which the behavior and/or functions desired from the design are transformed to a functionally equivalent logic gate-level circuit description by matching the design to standard cells selected from the standard cell library307. The synthesis results in a functionally equivalent logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, a photolithographic mask may be generated that is used to fabricate the integrated circuit by the fabrication tools303. Further aspects of device fabrication are disclosed in conjunction withFIG.13, which is a block diagram of IC manufacturing system301, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the manufacturing system301. InFIG.13, the IC manufacturing system301includes entities, such as a design house320, a mask house330, and an IC manufacturer/fabricator (“fab”)350, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device360, such as the devices100-106disclosed herein. The entities in the system301are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of the design house320, mask house330, and IC fab350is owned by a single larger company. In some embodiments, two or more of design house320, mask house330, and IC fab350coexist in a common facility and use common resources. The design house (or design team)320generates an IC design layout diagram322. The IC design layout diagram322includes various geometrical patterns, or IC layout diagrams designed for an IC device360, e.g., an IC device including one or more of the disclosed IC structures100-106, discussed above. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device360to be fabricated. The various layers combine to form various IC features. For example, a portion of the IC design layout diagram322includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house320implements a design procedure to form a IC design layout diagram322. The design procedure includes one or more of logic design, physical design or place and route. The IC design layout diagram322is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram322can be expressed in a GDSII file format or DFII file format. The mask house330includes a data preparation332and a mask fabrication344. The mask house330uses the IC design layout diagram322to manufacture one or more masks345to be used for fabricating the various layers of the IC device360according to the IC design layout diagram322. The mask house330performs mask data preparation332, where the IC design layout diagram322is translated into a representative data file (“RDF”). The mask data preparation332provides the RDF to the mask fabrication344. The mask fabrication344includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)345or a semiconductor wafer353. The design layout diagram322is manipulated by the mask data preparation332to comply with particular characteristics of the mask writer and/or requirements of the IC fab350. InFIG.13, the mask data preparation332and the mask fabrication344are illustrated as separate elements. In some embodiments, the mask data preparation332and the mask fabrication344can be collectively referred to as a mask data preparation. In some embodiments, the mask data preparation332includes an optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. The OPC adjusts the IC design layout diagram322. In some embodiments, the mask data preparation332includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, the mask data preparation332includes a mask rule checker (MRC) that checks the IC design layout diagram322that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram322to compensate for limitations during the mask fabrication344, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, the mask data preparation332includes lithography process checking (LPC) that simulates processing that will be implemented by the IC fab350to fabricate the IC device360. LPC simulates this processing based on the IC design layout diagram322to create a simulated manufactured device, such as the IC device360. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine the IC design layout diagram322. It should be understood that the above description of mask data preparation332has been simplified for the purposes of clarity. In some embodiments, data preparation332includes additional features such as a logic operation (LOP) to modify the IC design layout diagram322according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram322during data preparation332may be executed in a variety of different orders. After the mask data preparation332and during the mask fabrication344, a mask345or a group of masks345are fabricated based on the modified IC design layout diagram322. In some embodiments, the mask fabrication344includes performing one or more lithographic exposures based on the IC design layout diagram322. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)345based on the modified IC design layout diagram322. The mask345can be formed in various technologies. In some embodiments, the mask345is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of the mask345includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask345is formed using a phase shift technology. In a phase shift mask (PSM) version of the mask345, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by the mask fabrication344is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer353, in an etching process to form various etching regions in the semiconductor wafer353, and/or in other suitable processes. The IC fab350includes wafer fabrication352. The IC fab350is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, the IC Fab350is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (FEOL fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (BEOL fabrication), and a third manufacturing facility may provide other services for the foundry business. The IC fab350uses mask(s)345fabricated by the mask house330to fabricate the IC device360. Thus, the IC fab350at least indirectly uses the IC design layout diagram322to fabricate the IC device360. In some embodiments, the semiconductor wafer353is fabricated by the IC fab350using mask(s)345to form the IC device360. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout diagram322. The Semiconductor wafer353includes a silicon substrate or other proper substrate having material layers formed thereon. The semiconductor wafer353further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). Thus, disclosed embodiments include an integrated circuit device that includes a first power rail and a first active area extending in a first direction. A plurality of gates contact the first active area and extend in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first VT. A second transistor includes the first active area and a second one of the gates, and the second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor. The tie-off transistor includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail. In accordance with other disclosed embodiments, a semiconductor device includes a first power rail and a second power rail. A first PMOS transistor includes a first fin extending in a first direction and a first gate. The first PMOS transistor has a first VT, and the first gate extends in a second direction perpendicular to the first direction. A second PMOS transistor includes the first fin and a second gate that extends in the second direction. The second PMOS transistor has a second VT different than the first VT. The second gate is connected to the first power rail. A second fin extends in the first direction. A first NMOS transistor includes the second fin and the first gate. The first NMOS transistor has the first VT. A second NMOS transistor includes the second fin and the second gate. The second NMOS transistor has the second VT. The second gate is connected to the second power rail. In accordance with still further embodiments, a method includes forming a first active area on a substrate, where the first active area has a first VT region and a second VT region. A first gate is formed that contacts the first VT region of the first active area to form a first transistor having a first VT. A second gate is formed to contact the second VT region of the first active area to form a second transistor having a second VT that is different than the first VT. A third gate is formed to contact the first active area between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor. The third gate is connected to a power rail to maintain the tie-off transistor in an off state. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 50,768 |
11862638 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. According to various embodiments, dummy gates are recessed and a spacer treatment process is performed on gate spacers that extend along sidewalls of the dummy gates. The spacer treatment process causes the gate spacers to bow in a top-down view. The dummy gates are then removed and replaced with metal gates. Increasing the bowing of the gate spacers may allow the materials of the metal gates to be more fully deposited. The formations of gaps or voids around the metal gates may be avoided, decreasing the gate resistance (Rg) of the FinFETs. FIG.1illustrates an example of simplified Fin Field-Effect Transistors (FinFETs) in a three-dimensional view, in accordance with some embodiments. Some other features of the FinFETs (discussed below) are omitted for illustration clarity. The illustrated FinFETs may be electrically connected or coupled in a manner to operate as, for example, one transistor or multiple transistors, such as two transistors. The FinFETs include fins52extending from a substrate50. Shallow trench isolation (STI) regions56are disposed over the substrate50, and the fins52protrude above and from between neighboring STI regions56. Although the STI regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fins52are illustrated as being a single, continuous material of the substrate50, the fins52and/or the substrate50may include a single material or a plurality of materials. In this context, the fins52refer to the portions extending between the neighboring STI regions56. Gate dielectrics112are along sidewalls and over top surfaces of the fins52, and gate electrodes114are over the gate dielectrics112. Source/drain regions88are disposed in opposite sides of the fin52with respect to the gate dielectrics112and gate electrodes114. Gate spacers82separate the source/drain regions88from the gate dielectrics112and gate electrodes114. An inter-layer dielectric (ILD)92is disposed over the source/drain regions88and STI regions56. In embodiments where multiple transistors are formed, the source/drain regions88may be shared between various transistors. In embodiments where one transistor is formed from multiple fins52, neighboring source/drain regions88may be electrically connected, such as through merging the source/drain regions88by epitaxial growth, or through coupling the source/drain regions88with a same source/drain contact. FIG.1further illustrates several reference cross-sections. Cross-section A-A and is along a longitudinal axis of a fin52and in a direction of, for example, a current flow between the source/drain regions88of the FinFETs. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of a gate electrode114and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions88of the FinFETs. Cross-section D-D is parallel to cross-section B-B and extends through the source/drain regions88of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity. FIGS.2through19Bare various views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2and3are three-dimensional views.FIGS.6A,7A,8A,9A,10A,11A,12A,13A,14A,15A,16A,16D,17A,18A, and19Aare cross-sectional views illustrated along reference cross-section A-A inFIG.1, except three gate structures are shown.FIGS.6B,7B,8B,9B,10B,11B,12B,13B,14B,15B,16B,17B,18B, and19Bare cross-sectional views illustrated along reference cross-section B-B inFIG.1, except only two fins52are shown.FIGS.7C and7Dare cross-sectional views illustrated along reference cross-section D-D inFIG.1, except only two fins52are shown InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or a n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. The substrate50has a n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region50N may be physically separated from the p-type region50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. Fins52are formed in the substrate50. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. The fins may be patterned by any suitable method. For example, the fins52may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins52. STI regions56are formed over the substrate50and between neighboring fins52. As an example to form the STI regions56, an insulation material can be formed over the substrate50and between neighboring fins52. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, the insulation material is silicon oxide formed by FCVD. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the fins52. Although the STI regions56are illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not shown) may first be formed along a surface of the substrate50and the fins52. Thereafter, a fill material, such as those discussed above, may be formed over the liner. A removal process is then applied to the insulation material to remove excess insulation material over the fins52. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins52such that top surfaces of the fins52and the insulation material are coplanar (within process variations) after the planarization process is complete. In embodiments in which a mask remains on the fins52, the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the fins52, respectively, and the insulation material are coplanar (within process variations) after the planarization process is complete. The insulation material is recessed to form the STI regions56. The insulation material is then recessed such that upper portions of the fins52in the n-type region50N and in the p-type region50P protrude from between neighboring STI regions56. Further, the top surfaces of the STI regions56may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions56may be formed flat, convex, and/or concave by an appropriate etch. The STI regions56may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins52). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used The process described with respect toFIG.2is just one example of how the fins52may be formed. In some embodiments, the fins52may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins52. For example, the fins52can be recessed, and a material different from the fins52may be epitaxially grown over the recessed material. In such embodiments, the fins52comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in n-type region50N (e.g., a NMOS region) different from the material in p-type region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins52may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like. Further, appropriate wells (not shown) may be formed in the fins52and/or the substrate50. In some embodiments, a p-type well may be formed in the n-type region50N, and a n-type well may be formed in the p-type region50P. In some embodiments, p-type well or a n-type well are formed in both the n-type region50N and the p-type region50P. In the embodiments with different well types, the different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins52and the STI regions56in the n-type region50N. The photoresist is patterned to expose the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than about 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process. Following the implanting of the p-type region50P, a photoresist is formed over the fins52and the STI regions56in the p-type region50P. The photoresist is patterned to expose the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. InFIG.3, a dummy dielectric layer62is formed on the fins52. The dummy dielectric layer62may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer64is formed over the dummy dielectric layer62, and a mask layer66is formed over the dummy gate layer64. The dummy gate layer64may be deposited over the dummy dielectric layer62and then planarized, such as by a CMP. The mask layer66may be deposited over the dummy gate layer64. The dummy gate layer64may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer64may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer64may be made of other materials that have a high etching selectivity from the etching of isolation regions, e.g., the STI regions56and/or the dummy dielectric layer62. The mask layer66may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer64and a single mask layer66are formed across the n-type region50N and the p-type region50P. In the illustrated embodiment, the dummy dielectric layer62covers the STI regions56, extending over the STI regions56and between the dummy gate layer64and the STI regions56. In another embodiment, the dummy dielectric layer62covers only the fins52. InFIG.4, the mask layer66may be patterned using acceptable photolithography and etching techniques to form masks76. The pattern of the masks76then may be transferred to the dummy gate layer64to form dummy gates74. In some embodiments, the pattern of the masks76is also transferred to the dummy dielectric layer62by an acceptable etching technique to form dummy dielectrics72. The dummy gates74cover respective channel regions58of the fins52. The pattern of the masks76may be used to physically separate each of the dummy gates74from adjacent dummy gates74. The dummy gates74may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the fins52. FIG.5is a top-down view of FinFETs, in accordance with some embodiments. Some features are omitted for clarity of illustration. According to various embodiments, the fins52are formed in fin groups52G. Each fin group52G includes fins52spaced apart by a first distance S1, and the fin groups52G are spaced apart by a second distance S2, with the second distance S2being greater than the first distance S1. The fins groups52G may contain any desired quantity of fins52, such as two fins52, three fins52, or the like. A device, such as a transistor, can be formed from multiple fins52, such as from some or all of the fins52of a fin group52G. The regions in which the fin groups52G are formed (e.g., the regions that contain the fins52) may be referred to as dense regions50D, and the regions between the fin groups52G (e.g., the regions that are free of fins) may be referred to as sparse regions50S. Each of the sparse regions50S is disposed between two of the dense regions50D (e.g., two of the fin groups52G). The dummy gates74will be subsequently replaced with replacement gates, such as metal gates, for the FinFETs. The replacement gate process includes etching to remove the materials of the dummy gates74, and deposition to form the materials of the replacement gates. Performing etching and deposition in the dense regions50D (e.g., those regions with small fin-to-fin spacing) is increasingly challenging as technologies scale down. As a result, the portions of the dummy gates74between the fins52of adjacent fin groups52G are easier to replace than the portions of the dummy gates74between the fins52of a fin group52G. Put another way, the dummy gate portions74S in the sparse regions50S are easier to replace than the dummy gate portions74D in the dense regions50D. As will be discussed in greater detail below, the process for replacing the dummy gates74includes a spacer treatment process that aids in replacement of the dummy gate portions74D in the dense regions50D. FIGS.6A through19Billustrate various additional steps in the manufacturing of embodiment devices.FIGS.6A,6B,7A,7B,7C,7D,8A,8B,9A,9B,10A,10B,11A,11B,12A,12B,13A,13B,14A,14B,15A,15B,16A,16B,16D,17A,17B,18A,18B,19A, and19B are cross-sectional views that illustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated may be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure.FIGS.6C,11C,15C, and16Care top-down views that illustrate a detailed view of a region10ofFIG.5, including features in both a sparse regions50S and an adjacent dense regions50D. InFIGS.6A and6B, gate spacers82are formed on sidewalls of the dummy gates74and the masks76. The gate spacers82may be formed by conformally depositing one or more insulating material(s) and subsequently etching the insulating material(s). The insulating material(s) may be formed of low-k dielectric materials such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, a combination thereof, or the like, which may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. The insulating material(s), when etched, have portions left on the sidewalls of the dummy gates74and the masks76(hence forming the gate spacers82). After the etching, the gate spacers82can have straight sidewalls (as illustrated) or can have curved sidewalls (not illustrated). According to various embodiments, the gate spacers82each include multiple layer(s), e.g., a first spacer layer80A and a second spacer layer80B. In some embodiments, the first spacer layers80A and the second spacer layers80B are each formed of silicon oxycarbonitride (e.g., SiOxNyC1-x-y, where x and y are in the range of 0 to 1). In some embodiments, the silicon oxycarbonitride of the first spacer layers80A has a different composition than the silicon oxycarbonitride of the second spacer layers80B. During or after the formation of the gate spacers82, implants for lightly doped source/drain (LDD) regions86may be performed. In the embodiments with different device types, similar to the implants for the wells previously discussed, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins52in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins52in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The LDD regions86may have a concentration of impurities in the range of about 1015cm−3to about 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities. Referring toFIG.6C, the profile shape of the dummy gates74in a top-down view is shown.FIG.6Cis illustrated along reference cross-section C-C inFIG.4, so as to more specifically illustrate features of the dummy gates74between the fins52. During the patterning of the dummy gates74, pattern loading effects can cause sidewalls of the portions of the dummy gates74proximate the fins52to be etched less than sidewalls of the portions of the dummy gates74distal the fins52. The dummy gates74thus have a bowed profile shape in a top-down view, such that the portions of the dummy gates74proximate the fins52have a greater width W1than the portions of the dummy gates74distal the fins52. The width W1can be in the range of about 5 nm to about 20 nm when devices with small channel lengths are desired, and the width W1can be in the range of about 20 nm to about 150 nm when devices with large channel lengths are desired. Each portion of the dummy gates74between a pair of the fins52has a minimum width W1at a point that is equidistant from the fins52. The profile shape of the gate spacers82in the top-down view is also shown. The gate spacers82are formed in pairs along sidewalls of the dummy gates74. The gate spacers82thus also have a bowed profile shape in a top-down view, such that the portions of the gate spacers82distal the fins52bow inwards towards one another by a distance D1, which is measured from the portions of the gate spacers82proximate the fins52. The distance D1can be in the range of about 0.5 nm to about 5 nm. As a result of the inward bowing, the sidewalls of the gate spacers82each form an acute angle θ1with a plane parallel to the sidewalls of the fins52. The angle θ1can be in the range of about 45 degrees to about 85 degrees. In the illustrated embodiment, the dummy gate portions74S in the sparse regions50S have the same width W1as the dummy gate portions74D in the dense regions50D, and the gate spacer portions82S in the sparse regions50S bow inward by the same distance D1as the gate spacer portions82D in the dense regions50D. In another embodiment, the dummy gate portions74S in the sparse regions50S have a different width than the dummy gate portions74D in the dense regions50D, and the gate spacer portions82S in the sparse regions50S bow inward by a different distance than the gate spacer portions82D in the dense regions50D. For example, pattern loading effects, such as those discussed above, can cause the dummy gate portions74S in the sparse regions50S to be etched more and thus have a lesser width than the dummy gate portions74D in the dense regions50D. As a result, the gate spacer portions82S in the sparse regions50S can bow inward by a greater distance than the gate spacer portions82D in the dense regions50D. As will be discussed in greater detail below, a spacer treatment process will be subsequently performed to increase the distance D1by which the portions of the gate spacers82bow inward. Notably, the spacer treatment process will increase the bowing of the gate spacer portions82D in the dense regions50D by more than it increases the bowing of the gate spacer portions82S in the sparse regions50S. Thus, the replacement gates formed in the dense regions50D will have a lesser width than the replacement gates formed in the sparse regions50S. InFIGS.7A and7B, epitaxial source/drain regions88are formed in the fins52. The epitaxial source/drain regions88are formed in the fins52such that each dummy gate74(and corresponding channel region58) is disposed between respective neighboring pairs of the epitaxial source/drain regions88. In some embodiments the epitaxial source/drain regions88may extend into, and may also penetrate through, the fins52. In some embodiments, the gate spacers82are used to separate the epitaxial source/drain regions88from the dummy gates74by an appropriate lateral distance so that the epitaxial source/drain regions88do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions88may be selected to exert stress in the respective channel regions58, thereby improving performance. The epitaxial source/drain regions88in the n-type region50N may be formed by masking the p-type region50P and etching source/drain regions of the fins52in the n-type region50N to form recesses in the fins52. Then, the epitaxial source/drain regions88in the n-type region50N are epitaxially grown in the recesses. The epitaxial source/drain regions88may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fins52are silicon, the epitaxial source/drain regions88in the n-type region50N may include materials exerting a tensile strain in the channel regions58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions88in the n-type region50N may have surfaces raised from respective surfaces of the fins52and may have facets. The epitaxial source/drain regions88in the p-type region50P may be formed by masking the n-type region50N and etching source/drain regions of the fins52in the p-type region50P to form recesses in the fins52. Then, the epitaxial source/drain regions88in the p-type region50P are epitaxially grown in the recesses. The epitaxial source/drain regions88may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fins52are silicon, the epitaxial source/drain regions88in the p-type region50P may comprise materials exerting a compressive strain in the channel regions58, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions88in the p-type region50P may have surfaces raised from respective surfaces of the fins52and may have facets. The epitaxial source/drain regions88and/or the fins52may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming the LDD regions86, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019cm−3and about 1021cm−3. The n-type and/or p-type impurities for the source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions88may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions88in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins52. In some embodiments, these facets cause adjacent epitaxial source/drain regions88to merge as illustrated byFIG.7C. In some embodiments, adjacent epitaxial source/drain regions88remain separated after the epitaxy process is completed as illustrated byFIG.7D. For example, adjacent epitaxial source/drain regions88of the fins52in a same fin group52G (seeFIG.5) may (or may not) merge. The spacer etch used to form the gate spacers82may be adjusted to also form fin spacers84on sidewalls of the fins52. In the illustrated embodiment, the fin spacers84cover a portion of the sidewalls of the fins52that extend above the STI regions56, thereby blocking the epitaxial growth. The fin spacers84between adjacent fins52may be merged (as shown), or may be etched so that they are separated. In another embodiment, the spacer etch used to form the gate spacers82is adjusted to not form the gate spacers82on the STI regions56, so as to allow the epitaxially grown regions to extend to the surface of the STI regions56. InFIGS.8A and8B, a first ILD92is deposited over the epitaxial source/drain regions88, the gate spacers82, the STI regions56, and the masks76(if present) or the dummy gates74. The first ILD92may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) is formed between the first ILD92and the epitaxial source/drain regions88, the gate spacers82, the STI regions56, and the masks76(if present) or the dummy gates74. The CESL may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the first ILD92. InFIGS.9A and9B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD92with the top surfaces of the masks76(if present) or the dummy gates74. The planarization process may also remove the masks76on the dummy gates74, and portions of the gate spacers82along sidewalls of the masks76. After the planarization process, the top surfaces of the dummy gates74, the gate spacers82, and the first ILD92are coplanar (within process variations). Accordingly, the top surfaces of the dummy gates74are exposed through the first ILD92. In some embodiments, the masks76may remain, in which case the planarization process levels the top surface of the first ILD92with the top surfaces of the masks76. InFIGS.10A and10B, the masks76(if present) are removed and the dummy gates74are recessed in one or more etching step(s), so that recesses94are formed between opposing portions of the gate spacers82. The recesses94expose the sidewalls of the gate spacers82. In some embodiments, the dummy gates74are recessed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates74with little or no etching of the first ILD92or the gate spacers82. Each recess94overlies a channel region58of a respective fin52. Timed etch processes may be used to stop the etching of the dummy gates74after the recesses94reach a desired depth. Specifically, the depth of the recesses94is controlled so that a majority of the dummy gates74is removed, but the fins52and the dummy dielectrics72remain covered after the recesses94are formed. In some embodiment, forming the recesses94reduces the height of the dummy gates74by about 80% to about 90%. InFIGS.11A and11B, a spacer treatment process96is performed to increase the bowing of the gate spacers82. Specifically, the spacer treatment process96bows the sidewalls of the gate spacers82towards one another. The spacer treatment process96induces stress in the material of the gate spacers82, thereby causing them to bow in the top-down view (discussed in greater detail below). In some embodiments, the spacer treatment process96expands (e.g., increases the volume of) the gate spacers82, causing them to bow as they expand in the recesses94. In various embodiments, the spacer treatment process96includes a nitridation process, an oxidation process, combinations thereof, or the like. In some embodiments, the spacer treatment process96includes a nitridation treatment process such as an ammonia soak process, in which the gate spacers82are exposed to ammonia (NH3). The ammonia soak process may be performed in a chamber such as an etch chamber. A gas source is dispensed in the chamber. The gas source includes ammonia gas and an carrier gas. The carrier gas may be an inert gas such as argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), Radon (Rn), the like, or combinations thereof. In some embodiments, the ammonia gas is from about 5% to about 20% of the gas source, and the carrier gas is from about 80% to about 95% of the gas source. The gas source may be dispensed at a flow rate of from about 50 sccm to about 500 sccm. The nitrogen in the ammonia readily bonds with any open bonds of silicon atoms of the gate spacers82, thereby nitrating the gate spacers82and producing hydrogen byproducts, which can be evacuated from the chamber. The ammonia is kept in the chamber until the gate spacers82have been nitrated by a desired amount. In some embodiments, the ammonia soak process is performed at a temperature of from about 300° C. to about 600° C., and for a duration of from about 5 seconds to about 300 seconds. In some embodiments, the spacer treatment process96includes a nitridation treatment process such as a nitrogen radical treatment process, in which the gate spacers82are exposed to nitrogen free radicals. The nitrogen radical treatment process may be performed in a chamber such as an etch chamber. A gas source is dispensed in the chamber. The gas source includes a plurality of radical precursor gases and an carrier gas. The radical precursor gases include H2and N2. The carrier gas may be an inert gas such as argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), Radon (Rn), the like, or combinations thereof. In some embodiments, the H2is from about 5% to about 20% of the gas source, the N2is from about 5% to about 20% of the gas source, and the carrier gas is from about 60% to about 90% of the gas source. The gas source may be dispensed at a flow rate of from about 50 sccm to about 500 sccm. A plasma is generated from the gas source. The plasma may be generated by a plasma generator such as a transformer-coupled plasma generator, inductively coupled plasma system, magnetically enhanced reactive ion etching system, electron cyclotron resonance system, remote plasma generator, or the like. The plasma generator generates radio frequency power that produces a plasma from the gas source by applying a voltage above the striking voltage to electrodes in the chamber containing the gas source. When the plasma is generated, nitrogen free radicals and corresponding ions are generated. The nitrogen free radicals readily bond with any open bonds of silicon atoms of the gate spacers82, thereby nitrating the gate spacers82. The nitrogen free radicals are kept in the chamber until the gate spacers82have been nitrated by a desired amount. In some embodiments, the nitrogen radical treatment process is performed at a temperature of from about 300° C. to about 600° C., for a duration of from about 5 seconds to about 300 seconds, and at a pressure of from about 1 Torr to about 50 Torr. In some embodiments, the spacer treatment process96includes an oxidation treatment process such as a low-temperature anneal process, in which the gate spacers82are annealed in oxygen at a low temperature. For example, a rapid thermal anneal (RTA) may be performed in an ambient containing oxygen and an inert gas. The inert gas may be argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), Radon (Rn), the like, or combinations thereof. In some embodiments, the oxygen is from about 5% to about 20% of the ambient, and the inert gas is from about 80% to about 95% of the ambient. The thermal oxidation may be performed at a temperature of from about 150° C. to about 500° C., and for a duration of from about 5 seconds to about 200 seconds. Referring toFIG.11C, the profile shape of the gate spacers82in a top-down view after the spacer treatment process96is shown. The distance by which the gate spacer portions82S in the sparse regions50S bow inward is increased to a distance D2, which is greater than the distance D1(seeFIG.6C). Similarly, the distance by which the gate spacer portions82D in the dense regions50D bow inward is increased to a distance D3, which is greater than the distance D1(seeFIG.6C). The distance D2can be in the range of about 1 nm to about 10 nm, and the distance D3can be in the range of about 1.5 nm to about 15 nm. The spacer treatment process96causes the gate spacer portions82D in the dense regions50D to bow inward by more than the gate spacer portions82S in the sparse regions50S. For example, because of the high density of the fins52in the dense regions50D, the gate spacers82have little room to expand in the dense regions50D, and so they bow outward instead of expanding in-place. As such, the distance D3is greater than the distance D2. The distance D3can be from about 5% to about 50% greater than the distance D2. The recess portions94S in the sparse regions50S have corners94SCthat are defined by the sidewalls of the gate spacer portions82S in the sparse regions50S and the sidewalls of the fins52. The corners94SCform an acute angle θ2, with the angle θ2being less than the angle θ1(seeFIG.6C). Similarly, the recess portions94D in the dense regions50D have corners94DCthat are defined by the sidewalls of the gate spacer portions82D in the dense regions50D and the sidewalls of the fins52. The corners94DCform an acute angle θ3, with the angle θ3being less than the angle θ1(seeFIG.6C). The angle θ2can be in the range of about 65 degrees to about 85 degrees, and the angle θ3can be in the range of about 45 degrees to about 70 degrees. For similar reasons as those discussed with respect to the distances D2, D3, the angle θ2is greater than the angle θ3. The angle θ2can be from about 10% to about 40% greater than the angle θ3. As will be discussed in greater detail below, decreasing the sizes of the angles θ2, θ3aids in replacement of the dummy gate portions74D in the dense regions50D in a subsequent gate replacement process. InFIGS.12A and12B, the remaining portions of the dummy gates74are removed in one or more etching step(s), so that the recesses94are expanded. Portions of the dummy dielectrics72in the recesses94may also be removed. In some embodiments, only the dummy gates74are removed and the dummy dielectrics72remain and are exposed by the recesses94. In some embodiments, the dummy dielectrics72are removed from recesses94in a first region of the die (e.g., a core logic region) and remain in recesses94in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates74are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates74with little or no etching of the first ILD92or the gate spacers82. In some embodiments, the etching process for removing the remaining portions of the dummy gates74uses the same reaction gas(es) as the etching process for recessing the dummy gates74(discussed above forFIGS.10A and10B). During the removal, the dummy dielectrics72may be used as etch stop layers when the dummy gates74are etched. The dummy dielectrics72may then be optionally removed after the removal of the dummy gates74. InFIGS.13A and13B, a first gate dielectric layer102A is deposited in the recesses94, such as on the top surfaces and the sidewalls of the fins52and on the sidewalls of the gate spacers82. The first gate dielectric layer102A may also be formed on the top surfaces of the first ILD92. In some embodiments, the first gate dielectric layer102A includes one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the first gate dielectric layer102A includes an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The first gate dielectric layer102A may include a dielectric layer having a k-value greater than about 7.0. The formation methods of the first gate dielectric layer102A may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy dielectrics72remain in the recesses94, the first gate dielectric layer102A includes a material of the dummy dielectrics72(e.g., silicon oxide). InFIGS.14A and14B, a dipole doping layer104is formed over the first gate dielectric layer102A. The dipole doping layer104may be formed of an oxide, nitride, or carbide of a dipole-inducing element such as lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, or the like. The dipole doping layer104may be formed by PVD, CVD, ALD, or other suitable deposition methods. In some embodiments, the dipole doping layer104is formed of an oxide of lanthanum, e.g., LaOx. After the dipole doping layer104is formed, an annealing process is performed to drive the dipole-inducing element of the dipole doping layer104into the first gate dielectric layer102A. Once the anneal is complete, the first gate dielectric layer102A is doped with the dipole-inducing element (e.g., lanthanum) of the dipole doping layer104. Although the dipole doping layer104is illustrated as a single layer, some embodiments may utilize multiple layers. In some embodiments, a first dipole doping layer104is formed in a first region (e.g., the n-type region50N) and a second dipole doping layer104is formed in a second region (e.g., the p-type region50P). The dipole doping layers104in the n-type region50N and the p-type region50P may have different thicknesses and/or be formed of different dipole-inducing elements. The thicknesses and materials of the dipole doping layers can be varied based on the desired threshold voltages of the FinFETs. In the embodiments with different dipole doping layers, the different layers may be formed using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the first gate dielectric layer102A in the n-type region50N. The photoresist is patterned to expose the first gate dielectric layer102A in the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a first dipole doping layer is deposited on the p-type region50P, and the photoresist may act as a mask to substantially prevent the first dipole doping layer from being deposited on the n-type region50N. After the deposition, the photoresist is removed, such as by an acceptable ashing process. Following the deposition of the first dipole doping layer in the p-type region50P, a photoresist is formed over the first gate dielectric layer102A in the p-type region50P. The photoresist is patterned to expose the first gate dielectric layer102A in the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a second dipole doping layer is deposited on the n-type region50N, and the photoresist may act as a mask to substantially prevent the second dipole doping layer from being deposited on the p-type region50P. After the deposition, the photoresist may be removed, such as by an acceptable ashing process. InFIGS.15A and15B, the excess portions of the dipole doping layer104are removed. The removal may be by an acceptable etching process, such as a wet etch that is selective to the material of the dipole doping layer104. In some embodiment, the etching process is a wet etch using dilute hydrochloric acid, hydrochloric acid and hydrogen peroxide in deionized water, or dilute hydrochloric acid and ammonium hydroxide. The etching process may be performed at a temperature in the range of about 25° C. to about 180° C., and for a duration in the range of about 1 minutes to about 10 minutes. After removal of the dipole doping layer104, a second gate dielectric layer102B is deposited on the first gate dielectric layer102A. The second gate dielectric layer102B may be formed of materials that are selected from the same group of candidate materials of the first gate dielectric layer102A, which may be formed using methods that are selected from the same group of candidate methods for forming the materials of the first gate dielectric layer102A. In some embodiments, the first gate dielectric layer102A includes an interfacial layer of silicon oxide and a first layer of high-k dielectric material (e.g., hafnium oxide), while the second gate dielectric layer102B includes a second layer of the high-k dielectric material (e.g., hafnium oxide). The first gate dielectric layer102A and the second gate dielectric layer102B collectively define a gate dielectric layer102. The process described with respect toFIGS.12A through15Bis just one example of how the gate dielectric layer102may be formed and doped with a dipole-inducing element. Other techniques may be used to form doped gate dielectric layers. For example, a dipole-inducing element may first be formed in the recesses94by other means, the gate dielectric layer may then be deposited over the dipole-inducing element, and an anneal may be performed. Likewise, both the first gate dielectric layer102A and the second gate dielectric layer102B may be deposited before they are doped with the dipole-inducing element. Referring toFIG.15C, the profile shape of the gate dielectric layer102in a top-down view is shown.FIG.15Cis illustrated along reference cross-section C-C inFIG.4, so as to more specifically illustrate features of the gate dielectric layer102between the fins52. As discussed above, the spacer treatment process96helps decrease the angles θ2, ∝3of the corners94SC,94DC. Decreasing the angles θ2, θ3advantageously allows the gate dielectric layer102(e.g., the first gate dielectric layer102A and the second gate dielectric layer102B) to be more fully deposited in the corners94SC,94DC. The formations of gaps or voids around the replacement gates (e.g., voids in the corners94SC,94DC) may be avoided. The gate resistance (Rg) of the replacement gates may thus be decreased, improving performance of the FinFETs. As a result of the process for doping the gate dielectric layer102, impurities106(e.g., the dipole-inducing element) remain in the gate dielectric layer102. However, the second gate dielectric layer102B may not be doped in the same manner as the first gate dielectric layer102A. In such embodiments, the first gate dielectric layer102A includes the impurities106, while the second gate dielectric layer102B is substantially free from the impurities106. Because the gate dielectric layer102is conformally deposited, it inherits the underlying shape of the recesses94. Thus, the gate dielectric layer102has corner portions102C in the corners94SC,94DC(seeFIG.11C) of the recesses94, and has middle portions102M extending along the sidewalls of the recesses94(e.g., the sidewalls of the gate spacers82and the sidewalls of the fins52). The sidewalls of the middle portions102M form acute angles, e.g., the angles θ2, θ3. The middle portions102M of the gate dielectric layer102that extend along the gate spacers82(or more generally, a first direction) have the same bowed profile shape as the gate spacers82. The middle portions102M of the gate dielectric layer102that extend along the fins52(or more generally, a second direction that is perpendicular to the first direction) are straight and do not have a bowed profile shape. As discussed above, the spacer treatment process96helps decrease the angles θ2, θ3. Decreasing the angles θ2, θ3advantageously allows more impurities106to be formed in the corner portions102C than the middle portions102M of the gate dielectric layer102. For example, because of crowding, the process for removing the dipole doping layer104may leave more residual dipole-inducing element in the corners94SC,94DCthan in other regions of the recesses94. Thus, the corner portions102C of the gate dielectric layer102have a greater concentration of the impurities than the middle portions102M of the gate dielectric layer102. The work function of the replacement gates may thus be different at the centers and the edges of the channel regions58, allowing for more uniform turning on of the channel regions58. The amount of impurities106in the corner portions102C of the gate dielectric layer102may be controlled by controlling the parameters (e.g., duration) of the etching process used to remove the dipole doping layer104based on the desired threshold voltages of the FinFETs. In some embodiments, the concentration of the impurities106in the corner portions102C of the gate dielectric layer102is from about 1 to about 2.5 times the concentration of the impurities106in the middle portions102M of the gate dielectric layer102. For example, the impurities106in the corner portions102C of the gate dielectric layer102can have a concentration in the range of about 0.06×1015to about 800×1018atoms/cm2, and the impurities106in the middle portions102M of the gate dielectric layer102can have a concentration in the range of about 0 to about 60×1016atoms/cm2. InFIGS.16A and16B, a gate electrode layer108is deposited over the gate dielectric layer102, and fill the remaining portions of the recesses94.FIG.16Dillustrates a detailed view of region12ofFIG.16A. The gate electrode layer108may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode108is illustrated inFIGS.16A and16B, the gate electrode layer108may comprise any number of liner layers108A, any number of work function tuning layers108B, and a fill material108C as illustrated byFIGS.16C and16D. The liner layers108A (sometimes referred to as capping layers) include any acceptable material to promote adhesion and prevent diffusion. For example, the liner layers108A may be formed of a metal or metal nitride such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride (TiSiN), tantalum nitride, or the like, which may be deposited by ALD, CVD, PVD, or the like. In some embodiments, one or more of the liner layers108A may be deposited, removed (e.g., by etching), and redeposited, which helps remove residual dipole-inducing elements (e.g., lanthanum) that may remain on the top surface of the gate dielectric layer102. The work function tuning layers108B include any acceptable material to tune a work function of a device to a desired amount given the application of the device to be formed, and may be deposited using any acceptable deposition process. For example, the work function tuning layers108B may be formed of aluminum, aluminum nitride, titanium aluminide, tantalum aluminum, titanium carbon nitride, or the like, which may be deposited by ALD, CVD, PVD, or the like. In some embodiments, a first work function tuning layer is formed in a first region (e.g., the p-type region50P) and a second work function tuning layer is formed in a second region (e.g., the n-type region50N). As an example to form the work function tuning layers108B, a first work function tuning layer may be deposited in both the p-type region50P and the n-type region50N. The first work function tuning layer may be removed (e.g., by etching) from the n-type region50N, and a second work function tuning layer may then be deposited in both the p-type region50P and the n-type region50N. Thus, the p-type region50P may contain both a first work function tuning layer and a second work function tuning layer, while the n-type region50N contains the second work function tuning layer but not the first work function tuning layer. Various work function tuning layers may be formed based on the desired threshold voltages of the FinFETs. The fill material108C includes any acceptable material of a low resistance. For example, the fill material108C may be formed of a metal such as tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), combinations thereof or the like, which may be deposited by ALD, CVD, PVD, or the like. In some embodiments, an adhesion or glue layer is formed between the fill material108C and the work function tuning layers108B. The fill material108C fills the remaining portions of the recesses94. Referring toFIG.16C, the profile shape of the gate electrode layer108in a top-down view is shown.FIG.16Cis illustrated along reference cross-section C-C inFIG.4, so as to more specifically illustrate features of the gate electrode layer108between the fins52. Because the liner layers108A and the work function tuning layers108B are conformally deposited, they inherit the underlying shape of the recesses94. Thus, similar to the gate dielectric layer102, the liner layers108A and the work function tuning layers108B also have corner portions in the corners94SC,94DC(seeFIG.11C) of the recesses94, and have middle portions extending along the sidewalls of the recesses94. The corner portions and the middle portions of the liner layers108A and the work function tuning layers108B laterally surround the fill material108C. The middle portions of the liner layers108A and the work function tuning layers108B also have the same bowed profile shape as the gate spacers82. As discussed above, the spacer treatment process96helps decrease the angles θ2, θ3of the corners94SC,94DC(seeFIG.11C). Decreasing the angles θ2, θ3advantageously allows the corner portions of the gate dielectric layer102, the liner layers108A, and the work function tuning layers108B to be formed to larger thicknesses. Specifically, the thickness T1of the corner portions of the gate dielectric layer102, the liner layers108A, and the work function tuning layers108B is greater than the thickness T2of the middle portions of the gate dielectric layer102, the liner layers108A, and the work function tuning layers108B. In some embodiments, the thickness T1is from about 1.2 to about 1.6 times the thickness T2. The work function of the replacement gates may thus be different at the centers and the edges of the channel regions58, allowing for more uniform turning on of the channel regions58. In the illustrated embodiment, the corner portions in the sparse regions50S have the same thickness T1as the corner portions in the dense regions50D, and the middle portions in the sparse regions50S have the same thickness T2as the middle portions in the dense regions50D. In another embodiment, the corner portions in the sparse regions50S have a different thickness than the corner portions in the dense regions50D, and the middle portions in the sparse regions50S have a different thickness than the middle portions in the dense regions50D. InFIGS.17A and17B, a planarization process, such as a CMP, is performed to remove the excess portions of the gate dielectric layer102and the gate electrode layer108, which excess portions are over the top surfaces of the first ILD92. The remaining portions of the gate dielectric layer102in the recesses94form gate dielectrics112. The remaining portions of the gate electrode layer108in the recesses94form gate electrodes114. The gate dielectrics112and the gate electrodes114form replacement gates of the FinFETs. The gate dielectrics112and the gate electrodes114may each be collectively referred to as a “gate structure.” The gate structures extend along sidewalls of a channel region58of the fins52. InFIGS.18A and18B, a second ILD122is deposited over the gate spacers82, the first ILD92, and the gate dielectrics112, and the gate electrodes114. In some embodiments, the second ILD122is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD122is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. Optionally, gate masks120are formed over the gate structures (including the gate dielectrics112and the corresponding gate electrodes114) before formation of the second ILD122. The gate masks120are disposed between opposing portions of the gate spacers82. In some embodiments, forming the gate masks120includes recessing the gate structures so that recesses are formed directly over the gate structures and between opposing portions of gate spacers82. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled in the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD92. The gate masks120include the portions of the dielectric material remaining in the recesses. Subsequently formed gate contacts will penetrate through the gate masks120and the second ILD122to contact the top surfaces of the recessed gate electrodes114. InFIGS.19A and19B, source/drain contacts124and gate contacts126are formed to contact, respectively, the epitaxial source/drain regions88and the gate electrodes114. Openings for the source/drain contacts124are formed through the first ILD92and the second ILD122, and openings for the gate contacts126are formed through the gate masks120and the second ILD122. The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD122. The remaining liner and conductive material form the source/drain contacts124and the gate contacts126in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions88and the source/drain contacts124. The source/drain contacts124are physically and electrically coupled to the epitaxial source/drain regions88, and the gate contacts126are physically and electrically coupled to the gate electrodes114. The source/drain contacts124and the gate contacts126may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts124and the gate contacts126may be formed in different cross-sections, which may avoid shorting of the contacts. Embodiments may achieve advantages. Recessing the dummy gates74(as discussed above forFIGS.10A and10B) and then performing the spacer treatment process96(as discussed above forFIGS.11A and11B) helps increase the bowing of the gate spacers82. The angles θ2, θ3of the corners94SC,94DCof the recesses94(seeFIG.11C) may thus be decreased, which may allow the gate dielectric layer102to be more fully deposited in the corners94SC,94DC. The formations of gaps or voids around the replacement gates (e.g., voids in the corners94SC,94DC) may be avoided. The gate resistance (Rg) of the replacement gates may thus be decreased, improving performance of the FinFETs. The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate structures and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate structures are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. A nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016/0365414, which is incorporated herein by reference in its entirety. In an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric. In some embodiments of the device, the first fin and the second fin extend along a first direction, and the gate spacer extends along a second direction, the first portion and the second portion of the gate dielectric being straight along the first direction, the third portion of the gate dielectric being bowed along the second direction. In some embodiments of the device, the gate dielectric has a fourth portion and a fifth portion, the fourth portion extending along the third sidewall of the gate spacer, the fifth portion extending along a fifth sidewall of the first fin, the fifth sidewall opposite the first sidewall, the fourth portion and the fifth portion forming a third acute angle, the third acute angle being greater than the first acute angle and the second acute angle. In some embodiments of the device, the first acute angle and the second acute angle are in a range of 45 degrees to 85 degrees, and the third acute angle is in a range of 65 degrees to 85 degrees. In some embodiments, the device further includes: a third fin extending from the substrate, where a first portion of the gate spacer is disposed between the first fin and the second fin, and a second portion of the gate spacer is disposed between the first fin and the third fin, the first portion of the gate spacer bowing inward a first distance, the second portion of the gate spacer bowing inward a second distance, the second distance less than the first distance. In some embodiments of the device, the first fin and the second fin are separated by a third distance, and the first fin and the third fin are separated by a fourth distance, the fourth distance greater than the third distance. In an embodiment, a device includes: a first fin extending from a substrate; a first gate spacer over the first fin; a second gate spacer over the first fin; a gate dielectric between the first gate spacer and the second gate spacer, the gate dielectric including a dielectric material doped with a dipole-inducing element, the gate dielectric having a first corner portion, a second corner portion, and a middle portion, the first corner portion adjacent the first gate spacer, the second corner portion adjacent the second gate spacer, the middle portion extending along the first fin between the first corner portion and the second corner portion, the first corner portion and the second corner portion having a first concentration of the dipole-inducing element, the middle portion having a second concentration of the dipole-inducing element, the second concentration being less than the first concentration; and a gate electrode on the gate dielectric. In some embodiments of the device, the first corner portion and the second corner portion have a first thickness, and the middle portion has a second thickness, the second thickness being less than the first thickness. In some embodiments of the device, a ratio of the first thickness to the second thickness is in a range of 1.2 to 1.6. In some embodiments of the device, the gate electrode includes a work function tuning layer on the gate dielectric, the work function tuning layer having a first thickness adjacent the first corner portion and the second corner portion, the work function tuning layer having a second thickness adjacent the middle portion, the second thickness being less than the first thickness. In some embodiments of the device, a ratio of the first concentration to the second concentration is in a range of 1 to 2.5. In some embodiments of the device, the dielectric material is hafnium oxide and the dipole-inducing element is lanthanum. In some embodiments of the device, the first corner portion and the second corner portion are each disposed in a respective corner having an acute angle. In some embodiments of the device, the acute angle is in a range of 45 degrees to 85 degrees. In an embodiment, a method includes: forming a dummy gate over a channel region of a fin; forming gate spacers adjacent the dummy gate; recessing the dummy gate to expose sidewalls of the gate spacers; performing a spacer treatment process, the spacer treatment process bowing the sidewalls of the gate spacers towards one another; removing remaining portions of the dummy gate to expose the channel region; and forming a gate dielectric on the channel region and the sidewalls of the gate spacers. In some embodiments of the method, the spacer treatment process includes an ammonia soak process. In some embodiments of the method, the spacer treatment process includes a nitrogen radical treatment process. In some embodiments of the method, the spacer treatment process includes a low-temperature anneal process. In some embodiments of the method, the sidewalls of the gate spacers form corners with sidewalls of the fin, the corners having angles, the spacer treatment process decreasing the angles of the corners. In some embodiments of the method, forming the gate dielectric includes: depositing first gate dielectric layer on the channel region and the sidewalls of the gate spacers; depositing a doping layer on the first gate dielectric layer; annealing the doping layer to drive a dopant from the doping layer into the first gate dielectric layer; removing the doping layer, where residue of the dopant remains in the corners; and depositing a second gate dielectric layer on the first gate dielectric layer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 70,642 |
11862639 | DETAILED DESCRIPTION FIG.1shows perspective views illustrating semiconductor devices according to an example embodiment.FIG.2shows vertical cross-sectional views taken along lines A-A′ and B-B′ of a first transistor and a second transistor, respectively, shown inFIG.1.FIG.3shows vertical cross-sectional views taken along lines C-C′ and D-D′ of the first transistor and the second transistor, respectively, shown inFIG.1. The semiconductor device according to the example embodiment may include a first transistor100disposed in a first region I and a second transistor200disposed in a second region II. The semiconductor device may be a complementary metal-oxide semiconductor (CMOS) device. The first region I may be an n-type metal oxide semiconductor (NMOS) region and the second region II may be a p-type metal oxide semiconductor (PMOS) region. The first transistor100and the second transistor200may be gate-all-around field effect transistors (GAAFETs). Referring toFIGS.1to3, the first transistor100may include a first semiconductor layer102, a buried insulating layer103, a second semiconductor layer104, first channel layers112,114, and116, a gate spacer135, a source/drain region150, an interlayer insulating layer160, and a gate electrode170. The first transistor100may further include an inner spacer140and a gate dielectric layer172. The first semiconductor layer102may include, e.g., silicon. The buried insulating layer103and the second semiconductor layer104may be sequentially disposed on the first semiconductor layer102. The first semiconductor layer102and the buried insulating layer103may be disposed on an entire surface of a lower portion of the first region I, and the second semiconductor layer104may be disposed to have a predetermined width in a second direction D2and extend in a first direction D1. The buried insulating layer103may include, e.g., silicon oxide. The buried insulating layer103may electrically insulate the first semiconductor layer102from the second semiconductor layer104. In an example embodiment, the second semiconductor layer104may include, e.g., silicon. The first semiconductor layer102and the second semiconductor layer104may have different crystallographic orientations. For example, an upper surface of the first semiconductor layer102, i.e., a surface of the first semiconductor layer102facing the buried insulating layer103, may have a (110) orientation, and upper and lower surfaces of the second semiconductor layer104may each have a (100) orientation. In an example embodiment, the second semiconductor layer104may include a Group IV semiconductor, e.g., Ge, SiGe, or the like, or a Group III-V compound, e.g., InGaAs, InAs, GaSb, InSb, or the like. The plurality of first channel layers112,114, and116may be disposed to be spaced apart from one other, e.g., along a third direction D3, on the second semiconductor layer104. Each of the plurality of first channel layers112,114, and116may have a predetermined length in the first direction D1and a predetermined width in the second direction D2. When viewed in a cross-sectional view, each of the plurality of first channel layers112,114, and116may be in a rectangular shape, and upper and lower surfaces of each thereof may be greater than a side surface of each thereof. In an example embodiment, each of the plurality of first channel layers112,114, and116may include, e.g., silicon. The plurality of first channel layers112,114, and116may each have a crystallographic orientation identical to that of the second semiconductor layer104. For example, the upper and lower surfaces of each of the plurality of first channel layers112,114, and116may each have a (100) orientation. In an example embodiment, each of the plurality of first channel layers112,114, and116may include a Group IV semiconductor, e.g., Ge, SiGe, or the like, or a Group III-V compound, e.g., InGaAs, InAs, GaSb, InSb, or the like. For example, each of the plurality of first channel layers112,114, and116may be composed of a multiple layer of a Group III-V compound, e.g., InP/InGaAs/InAs, GaAs/InP/InAs, GaAs/InGaAs/InAs, GaAs/InAlAs/InAs, InP/InGaAs/InP, GaAs/InAs, GaAs/InGaAs, or InP/InGaAs. The source/drain region150may be disposed on both, e.g., opposite, sides of each of the plurality of first channel layers112,114, and116in the first direction D1. A width of the source/drain region150in the second direction D2may be formed to be greater than a width of the second semiconductor layer104in the second direction D2, and the source/drain region150may have a pentagonal cross section. The source/drain region150may be electrically connected to the plurality of first channel layers112,114, and116. The source/drain region150may be formed by selective epitaxial growth (SEG) and may be doped with an impurity. For example, when the first transistor100is an NMOS transistor, the source/drain region150may include silicon doped with an n-type impurity and may have a lattice constant that is less than that of silicon. The source/drain region150may improve mobility of carriers by applying tensile stress to the first channel layers112,114, and116, which are channel regions. The interlayer insulating layer160may be disposed on the source/drain region150and on an outer side of the gate electrode170. The interlayer insulating layer160may entirely cover an upper surface of the buried insulating layer103, a side surface of the second semiconductor layer104, and the source/drain region150. The interlayer insulating layer160may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, and may be composed of one or more layers. For example, the low-k dielectric material may include undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), a high-density plasma (HDP) oxide, or a combination thereof. A gate structure may be disposed to extend in the second direction D2and surround the plurality of first channel layers112,114, and116. The gate dielectric layer172may be conformally disposed along surfaces of the buried insulating layer103, the second semiconductor layer104, the plurality of first channel layers112,114, and116, the gate spacer135, and the inner spacer140. The gate dielectric layer172may include, e.g., a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate (BST), barium titanate, strontium titanate, yttrium oxide, aluminum oxide, or a combination thereof. In an example embodiment, the gate dielectric layer172may include hafnium oxide (HfO2). The gate electrode170may be disposed on the gate dielectric layer172. As shown inFIG.3, in a cross-sectional view in the second direction D2, the gate electrode170may entirely cover the plurality of first channel layers112,114, and116. The gate electrode170may include, e.g., aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, or a combination thereof. In an example embodiment, the gate electrode170may include tungsten. An oxide layer may be disposed on the surfaces of the plurality of first channel layers112,114, and116. Further, a work function adjustment layer may be included on the gate dielectric layer172. The gate spacers135may be disposed on both, e.g., opposite, sides of the gate electrode170in the second direction D2. The gate spacers135may be disposed to face each other on both sides of the gate electrode170. The gate spacer135may protect the gate electrode170. The gate spacer135may be composed of one or more layers. The first transistor100may further include a capping layer. The capping layer may be disposed on the gate spacer135, the interlayer insulating layer160, and the gate electrode170. The inner spacer140may be disposed on both, e.g., opposite, sides of the gate electrode170in the second direction D2. The inner spacer140may be disposed between the first channel layers112,114, and116and between the first channel layer112and the second semiconductor layer104. An outer surface of the inner spacer140in contact with the source/drain region150may be coplanar with outer surfaces of the first channel layers112,114, and116. A width of the inner spacer140in the first direction D1may be substantially equal to a width of the gate spacer135in the first direction D1. The inner spacer140may include, e.g., silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. The second transistor200in the second region II may include a configuration similar to that of the first transistor100. In detail, the second transistor200may include the first semiconductor layer102, a device isolation layer203, a base layer204, a second channel layer212,214, and216, a gate spacer235, a source/drain region250, an interlayer insulating layer260, and a gate electrode270. The second transistor200may further include an inner spacer240and a gate dielectric layer272. The device isolation layer203may cover a portion of the first semiconductor layer102, and the base layer204may be disposed on a portion of the first semiconductor layer102which is not covered with the device isolation layer203. The base layer204may protrude from the first semiconductor layer102in the third direction D3, e.g., through the device isolation layer203. The base layer204may be disposed to extend in the second direction D2. A lower surface of the device isolation layer203may be coplanar with a lower surface of the base layer204. An upper surface of the device isolation layer203may be located at a level that is lower than that of an upper surface of the base layer204. The device isolation layer203may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. The device isolation layer203may be formed by, e.g., an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or the like. In an example embodiment, the device isolation layer203may be formed by oxidizing silicon of the first semiconductor layer102. The base layer204may include, e.g., silicon, and may have a crystallographic orientation identical to that of the first semiconductor layer102. For example, upper and lower surfaces of the base layer204may each have a (110) orientation. The plurality of second channel layers212,214, and216may be disposed to be spaced apart from each other, e.g., along the third direction D3, on the base layer204. When viewed in a cross-sectional view, each of the plurality of second channel layers212,214, and216may be in a rectangular shape, and upper and lower surfaces of each thereof may be greater than a side surface of each thereof. The plurality of second channel layers212,214, and216may include, e.g., silicon, and may each have a crystallographic orientation identical to that of the first semiconductor layer102. For example, upper and lower surfaces of the plurality of second channel layers212,214, and216may each have a (110) orientation. The first channel layers112,114, and116may each have a thickness T in the third direction D3. The second channel layer212,214, and216may each have a thickness T′ in the third direction D3. The thickness T may be formed to be substantially equal to the thickness T′. As shown inFIGS.2and3, the first channel layers112,114, and116and the second channel layers212,214, and216may each have a cross section in the form of a rectangular sheet, but embodiments are not limited thereto, e.g., these layers may each have a cross section in the form of a wire. For example, in the vertical cross section taken along line C-C′ or D-D′, the first channel layers112,114, and116and/or the second channel layers212,214, and216may each have a cross section in the form of a circle or an ellipse. In an example embodiment, the plurality of first channel layers112,114, and116and the plurality of second channel layers212,214, and216may each have a cross section in the form of, e.g., a trapezoid, a triangle, or a diamond of which a lower surface is greater than an upper surface. Electrons may be used as carriers in an NMOS transistor, and holes may be used as carriers in a PMOS transistor. Electron mobility is high in silicon having a (100) orientation, whereas hole mobility is high in silicon having a (110) orientation. In the semiconductor device according to the example embodiment, the first channel layers112,114, and116and the second channel layers212,214, and216may each include silicon, the upper surfaces of the first channel layers112,114, and116may each have a (100) orientation, and the upper surfaces of the second channel layers212,214, and216may each have a (110) orientation. As described above, the crystallographic orientations of the first channel layers112,114, and116are made to be different from those of the second channel layers212,214, and216, such that mobility in an NMOS transistor and a PMOS transistor may be optimized. Therefore, the semiconductor device having a high operating speed can be realized. In an example embodiment, the first region I may correspond to a PMOS region, the second region II may correspond to an NMOS region, the upper surfaces of the plurality of first channel layers112,114, and116may each have a (110) orientation, and the upper surfaces of the plurality of second channel layers212,214, and216may each have a (100) orientation. In this case, an upper surface of the second semiconductor layer104has a (110) orientation, and the base layer204has a (100) orientation. The source/drain region250may be disposed on both sides of each of the plurality of second channel layers212,214, and216. When the second transistor200is a PMOS transistor, the source/drain regions250may include SiGe doped with a p-type impurity and may have a lattice constant that is greater than that of silicon. The source/drain region250may improve mobility of carriers by applying compressive stress to the second channel layers212,214, and216. A gate structure may include the gate electrode270and the gate dielectric layer272. The gate dielectric layer272may be conformally disposed along surfaces of the device isolation layer203, the base layer204, the plurality of second channel layers212,214, and216, the gate spacer235, and the inner spacer240. The gate electrode270may be disposed on the gate dielectric layer272. FIGS.4and5show cross-sectional views of a semiconductor device according to an example embodiment.FIG.4shows vertical cross-sectional views taken along the lines A-A′ and B-B′ of a first transistor and a second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.2.FIG.5shows vertical cross-sectionals views taken along the lines C-C′ and D-D′ of the first transistor and the second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.3. Referring toFIGS.4and5, a second transistor200amay include a plurality of second channel layers212a,214a, and216a. The second channel layers212a,214a, and216amay each have a thickness T′a in the third direction D3. As described below, the first channel layers112,114, and116and the second channel layers212a,214a, and216aare formed by different processes and thus may be formed to have different thicknesses. For example, the thickness T′a of each of the second channel layers212a,214a, and216amay be formed to be smaller than a thickness T of each of the first channel layers112,114, and116. A gap between the second channel layers212a,214a, and216amay be formed to be greater than a gap between the first channel layers112,114, and116. Generally, when a channel layer is short, a current leakage between source/drain regions may occur even when a voltage is not applied to a metal gate. As shown inFIGS.4and5, the second transistor200aincludes the second channel layers212a,214a, and216a, each having a relatively small thickness T′a such that a problem of a leakage current occurring between the source/drain regions250may be prevented. FIGS.6and7show cross-sectional views of a semiconductor device according to an example embodiment.FIG.6shows vertical cross-sectional views taken along the lines A-A′ and B-B′ of a first transistor and a second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.2.FIG.7shows vertical cross-sectional views taken along the lines C-C′ and D-D′ of the first transistor and the second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.3. Referring toFIGS.6and7, a second transistor200bmay include a plurality of second channel layers212b,214b, and216b. The second channel layer212bmay have a thickness T′b3, the second channel layer214bmay have a thickness T′b2, and the second channel layer216bmay have a thickness T′b1. The thicknesses T′b3, T′b2, and T′b1of the second channel layers212b,214b, and216bmay be formed to be different from one another. For example, the second channel layer214bmay be formed to be thinner than the second channel layer216band formed to be thicker than the second channel layer212b. FIGS.8and9show cross-sectional views of a semiconductor device according to an example embodiment.FIG.8shows vertical cross-sectional views taken along the lines A-A′ and B-B′ of a first transistor and a second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.2.FIG.9shows vertical cross-sectional views taken along the lines C-C′ and D-D′ of the first transistor and the second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.3. Referring toFIGS.8and9, the first transistor100and a second transistor200cmay have different numbers of channels. In an example embodiment, the first transistor100may include three first channel layers112,114, and116, and the second transistor200cmay include four second channel layers212c,214c,216c, and218c. A thickness T′c of each of the second channel layers212c,214c,216c, and218cmay be formed to be smaller than the thickness T of each of the first channel layers112,114, and116. The second channel layers212c,214c,216c, and218cmay have the same thickness T′c, but embodiments are not limited thereto. Referring toFIGS.8and9, the second transistor200cincludes the second channel layers212c,214c,216c, and216a, each having a relatively small thickness T′c such that a short channel effect and channel resistance may be complemented. FIGS.10and11show cross-sectional views of a semiconductor device according to an example embodiment.FIG.10shows vertical cross-sectional views taken along the lines A-A′ and B-B′ of a first transistor and a second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.2.FIG.11shows vertical cross-sectional views taken along the lines C-C′ and D-D′ of the first transistor and the second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.3. Referring toFIGS.10and11, an upper surface of the first semiconductor layer102at a lower portion of the first transistor100may be located at a level different from that of an upper surface of a first semiconductor layer102dat a lower portion of a second transistor200d. For example, the upper surface of the first semiconductor layer102dmay be located at a level that is lower than that of the upper surface of the first semiconductor layer102. In a process which will be described below, a second region II of the first semiconductor layer102may be partially etched to form the first semiconductor layer102d. The thickness T may be formed to be substantially identical to the thickness T′, but embodiments are not limited thereto. FIGS.12and13show cross-sectional views of a semiconductor device according to an example embodiment.FIG.12shows vertical cross-sectional views taken along the lines A-A′ and B-B′ of a first transistor and a second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.2.FIG.13shows vertical cross-sectional views taken along the lines C-C′ and D-D′ of the first transistor and the second transistor, respectively, according to an example embodiment, which correspond to the vertical cross-sectional views ofFIG.3. Referring toFIGS.12and13, the upper surface of the second semiconductor layer104may be located at a level different from that of an upper surface of a base layer204e. For example, the upper surface of the base layer204emay be located at a level that is lower than that of the upper surface of the second semiconductor layer104. In an example embodiment, the upper surface of the base layer204emay be located at a level that is higher than that of the upper surface of the second semiconductor layer104. The thickness T may be formed to be substantially identical to the thickness T′, but embodiments are not limited thereto. FIGS.14to20are cross-sectional views, which are illustrated according to the order of processes, for describing a method of manufacturing a first stack110and a second stack210according to an example embodiment. Referring toFIG.14, the first semiconductor layer102, the buried insulating layer103, and the second semiconductor layer104may be provided. For example, the first semiconductor layer102, the buried insulating layer103, and the second semiconductor layer104may be a silicon on insulator (SOI) substrate. For example, the SOI substrate may be formed by bonding a substrate, e.g., the first semiconductor layer102, on another substrate having an oxide film thereon, e.g., the second semiconductor layer104with the buried insulating layer103thereon, so a structure of the buried insulating layer103sandwiched between the first and second semiconductor layers102and104may be formed. In an example embodiment, the first semiconductor layer102and the second semiconductor layer104may include silicon, while the silicon in the first semiconductor layer102and the second semiconductor layer104may have different crystallographic orientations. For example, an upper surface of the first semiconductor layer102may have a (110) orientation and an upper surface of the second semiconductor layer104may have a (100) orientation. In an example embodiment, the first semiconductor layer102and/or the second semiconductor layer104may include a Group IV semiconductor, e.g., Ge, SiGe, or the like, or a Group compound, e.g., InGaAs, InAs, GaSb, InSb, or the like. Referring toFIG.15, the first stack110may be formed on the second semiconductor layer104. The first stack110may have a structure in which a plurality of sacrificial layers111,113, and115and the plurality of first channel layers112,114, and116are alternately stacked. The plurality of sacrificial layers111,113, and115and the plurality of first channel layers112,114, and116may be formed by epitaxial growth with the second semiconductor layer104as a seed layer. The plurality of sacrificial layers111,113, and115may include materials having an etch selectivity with respect to the plurality of first channel layers112,114, and116. In an example embodiment, the plurality of sacrificial layers111,113, and115may include, e.g., SiGe, and the plurality of first channel layers112,114, and116may include Si. The plurality of first channel layers112,114, and116may each have a crystallographic orientation identical to that of the second semiconductor layer104, e.g., since grown from the second semiconductor layer104. For example, the upper and lower surfaces of each of the plurality of first channel layers112,114, and116may each have a (100) orientation. In an example embodiment, the plurality of sacrificial layers111,113, and115and/or the plurality of first channel layers112,114, and116may include a Group IV semiconductor, e.g., Si, Ge, SiGe, or the like, or a Group III-V compound. Referring toFIG.16, a mask pattern M1may be disposed on the first stack110. For example, the mask pattern M1may be disposed in the first region I and may not be disposed in the second region II. Referring toFIG.17, a portion of the first stack110in the second region II, which is exposed by the mask pattern M1, may be removed. The buried insulating layer103and the second semiconductor layer104in the second region II may be etched to expose the first semiconductor layer102. InFIG.18, the upper surface of the first semiconductor layer102in the first region I and the upper surface of the first semiconductor layer102in the second region II have been shown as being located at the same level, but embodiments are not limited thereto. In an example embodiment, the first semiconductor layer102in the second region II may be over-etched, and thus the upper surface of the first semiconductor layer102in the second region II may be located at a level that is lower than that of the upper surface of the first semiconductor layer102in the first region I. Referring toFIG.18, a liner120may be formed on a side surface of the first stack110in the first direction D1. The liner120may be disposed at a boundary between the first region I and the second region II. The liner120may be formed such that the insulating layer is formed on the resultant structure ofFIG.15by CVD or ALD, and then, when anisotropic etching is performed, the insulating layer remains on only the side surface of the first stack110. Referring toFIG.19, the base layer204and the second stack210disposed on the base layer204may be formed on a portion of the exposed first semiconductor layer102. The base layer204and the second stack210may be disposed in the second region II. The second stack210may have a structure in which a plurality of sacrificial layers211,213, and215and the plurality of second channel layers212,214, and216are alternately stacked. The base layer204, the plurality of sacrificial layers211,213, and215, and the plurality of second channel layers212,214, and216may be formed by epitaxial growth with the first semiconductor layer102as a seed layer. The plurality of sacrificial layers211,213, and215may include materials having an etch selectivity with respect to the plurality of second channel layer212,214, and216. In an example embodiment, the plurality of sacrificial layers211,213, and215may include SiGe, and the base layer204and the plurality of second channel layers212,214, and216may include Si. The base layer204and the plurality of second channel layers212,214, and216may have crystallographic orientations identical to the crystallographic orientation of the first semiconductor layer102, e.g., since grown from the first semiconductor layer102. For example, the upper and lower surfaces of each of the plurality of second channel layers212,214, and216may each have a (110) orientation. In an example embodiment, the base layer204and/or the plurality of second channel layers212,214, and216may include a Group IV semiconductor, e.g., Si, Ge, SiGe, and the like, or a Group compound. Each of the plurality of second channel layers212,214, and216may be composed of a multiple layer. Referring toFIG.20, the mask pattern M1may be removed, and the liner120may be partially etched. The first channel layers112,114, and116and the second channel layers212,214, and216may also be partially etched. As shown inFIGS.14to20, the first stack110and the second stack210may be formed by separate processes. In an example embodiment, the first stack110may be formed first and, subsequently, the second stack210may be formed on the first semiconductor layer102exposed by removing a portion of the first stack110. The upper surfaces of the first channel layers112,114, and116and the upper surfaces of the second channel layers212,214, and216may be located at the same level. InFIG.20, the plurality of sacrificial layers111,113,115,211,213, and215, the first channel layers112,114, and116, and the second channel layers212,214, and216have been shown as having the same thickness, but embodiments are not limited thereto. In an example embodiment, the plurality of sacrificial layers111,113, and115may be formed to be thicker than the plurality of first channel layers112,114, and116. The plurality of sacrificial layers211,213, and215may be formed to be thicker than the plurality of second channel layers212,214, and216. FIGS.14to20show that the first semiconductor layer102including silicon has a (110) orientation and the second semiconductor layer104has a (100) orientation. However, embodiments are not limited thereto. In an example embodiment, the first semiconductor layer102including silicon may have a (100) orientation and the second semiconductor layer104may have a (110) orientation. In this case, each of the first channel layers112,114, and116may have a (110) orientation identical to the (110) orientation of the second semiconductor layer104, and the second channel layers212,214, and216may each have a (100) orientation identical to the (100) orientation of the first semiconductor layer102. Since the first stack110and the second stack210are formed by separate processes, the first stack110and the second stack210may have different structures. In an example embodiment, the plurality of second channel layers212,214, and216may be formed to be thinner than the plurality of first channel layers112,114, and116. A thickness of each of the plurality of sacrificial layers211,213, and215may be formed to be greater than the thickness of each of the plurality of sacrificial layers111,113, and115. In an example embodiment, the plurality of second channel layers212,214, and216may have different thicknesses. Alternatively, the plurality of first channel layers112,114, and116may have different thicknesses. The thicknesses of the plurality of first channel layers112,114, and116, the second channel layers212,214, and216, and the sacrificial layers111,113,115,211,213, and215may be adjusted in the third direction D3, which is a vertical direction, such that it is possible to form a transistor having various characteristics without changing the existing design rule. FIGS.21to23,24A,25A,26A,27A,28A,29A,30A, and31show perspective views and a cross-sectional view, which are illustrated according to the order of processes, for describing a method of manufacturing a semiconductor device according to an example embodiment.FIGS.24B,25B,26B,27B,28B,29B, and30Bare vertical cross-sectional views taken along lines A-A′ and B-B′ inFIGS.24A,25A,26A,27A,28A,29A, and30A. Referring toFIG.21, the first stack110and the second stack210may be patterned in fin shapes. The buried insulating layer103of the first region I and the first semiconductor layer102of the second region II may be exposed. The first semiconductor layer102and the buried insulating layer103may not be etched. The base layer204may have a pattern identical to that of the second stack210. The first stack110, the base layer204, and the second stack210, which are patterned, may have shapes protruding from the first semiconductor layer102in the third direction D3. The first stack110, the base layer204, and the second stack210, which are patterned, may extend in the first direction D. InFIG.21, widths of the first stack110, the base layer204, and the second stack210, which are patterned, have been shown as being constant in the second direction D2, but embodiments are not limited thereto. In an example embodiment, the patterned first stack110and the patterned base layer204may have shapes increasing in width downward in the second direction D2. The patterned second stack210may also have a shape increasing in width downward in the second direction D2. Referring toFIG.22, the device isolation layer203may be formed on the first semiconductor layer102in the second region II. The device isolation layer203may partially cover the upper surface of the first semiconductor layer102and the side surface of the base layer204in the second region II. The device isolation layer203may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. Referring toFIG.23, a dummy gate structure may be formed on each of the first stack110and the second stack210. The dummy gate structure may include dummy gate insulating layers130and230, dummy gate electrodes132and232, and dummy capping layers134and234. The dummy gate structure may be disposed to straddle each of the first stack110and the second stack210and may further extend in the second direction D2. The dummy gate structures may cover a side surface and an upper surface of each of the first stack110and the second stack210. The dummy gate insulating layers130and230, the dummy gate electrodes132and232, and the dummy capping layers134and234may be stacked sequentially. The dummy gate insulating layers130and230may include silicon oxide and may be formed by, e.g., a CVD method, an ALD method, or the like. The dummy gate electrodes132and232may include, e.g., polysilicon. The dummy capping layers134and234may be formed of, e.g., silicon nitride, silicon oxynitride, or a combination thereof. Referring toFIGS.24A and24B, the gate spacers135or235may be formed on the side surfaces of the dummy gate structure. The gate spacers135or235may be disposed to face each other on both sides of the dummy gate electrode132or232in the first direction D1. The gate spacers135and235may not be removed during a subsequent etching process to protect the gate electrodes170and270. Each of the gate spacers135and235may be constituted of one or more layers and may include, e.g., silicon nitride, silicon oxynitride, or a combination thereof. The gate spacers135and235may not cover upper surfaces of the dummy capping layers134and234. Referring toFIGS.25A and25B, a portion of the first stack110not covered with the dummy gate electrode132and a portion of the second stack210not covered with the dummy gate electrode232may be etched. For example, exposed upper portions of the first stack110and the second stack210may be partially removed to form recesses110R and210R. The side surfaces of the sacrificial layers111,113,115,211,213, and215, the first channel layers112,114, and116, and the second channel layers212,214, and216may be exposed by the recesses110R and210R. In an example embodiment, portions of the second semiconductor layer104and the base layer204may not be etched. In an example embodiment, a portion of the second semiconductor layer104located outside the gate spacer135and a portion of the base layer204located outside the gate spacer135may be partially or entirely removed. Referring toFIGS.26A and26B, outer sides of the sacrificial layers111,113,115,211,213, and215exposed by the recesses110R and210R may be partially etched to form a plurality of recesses140R and240R. The plurality of recesses140R and240R may have trench or dimple shapes, and the sacrificial layers111,113,115,211,213, and215may not be entirely removed. A width of the recess140R or240R may be substantially equal to a width of the gate spacer135or235. The first channel layers112,114, and116and the second channel layers212,214, and216, which have an etch selectivity with respect to the plurality of sacrificial layers111,113,115,211,213, and215, may not be etched. Referring toFIGS.27A and27B, a plurality of inner spacers140and240may be formed such that the plurality of recesses140R and240R may be filled with the plurality of inner spacers140and240. The inner spacers140and240may be formed of materials with excellent gap-filling capability. The inner spacers140may also be formed on the second semiconductor layer104and the gate spacer135. The inner spacers240may also be formed on the base layer204and the gate spacer235. The plurality of inner spacers140and240may be disposed between the first channel layers112,114, and116and between the second channel layers212,214, and216. The inner spacer140may be disposed between the second semiconductor layer104and the first channel layer112, and the inner spacer240may also be disposed between the base layer204and the second channel layer212. Outer surfaces of the inner spacers140and240may be located coplanar with the outer surfaces of the first channel layers112,114, and116and the outer surfaces of the second channel layers212,214, and216. Referring toFIGS.28A and28B, the source/drain regions150and250may be formed on upper portions of the second semiconductor layer104and the base layer204. The source/drain region150or250may be formed on both of the sides of the dummy gate structure. For example, the source/drain region150or250may be located on an outer surface of the gate spacer135or235. The source/drain regions150and250may be formed by SEG. The source/drain regions150and250may be doped with suitable ions according to types of transistors. For example, a fin used as the source/drain region250of a PMOS transistor may be doped with a p-type impurity. Boron (B), gallium (Ga), or the like may be used as the p-type impurity. A fin used as the source/drain region150of an NMOS transistor may be doped with an n-type impurity. Phosphorus (P), arsenic (As), or the like may be used as the n-type impurity. The source/drain regions150and250may have different growth according to a crystallographic orientation and may have pentagonal cross sections. However, embodiments are not limited thereto, and the source/drain regions150and250may have, e.g., a diamond shape, a circular shape, a rectangular shape, a hexagonal shape, or the like. Referring toFIGS.29A and29B, the interlayer insulating layers160and260may be formed on the source/drain regions150and250. The interlayer insulating layers160and260may entirely cover the side surfaces of the gate spacers135and235, and the source/drain regions150and250. The interlayer insulating layers160and260may each include, e.g., silicon oxide, silicon nitride, silicon oxynitride, PSG, BPSG, a low-k dielectric material, and/or one among differently applicable dielectric materials, or a multiple layer made of a plurality of layers. In an example embodiment, the interlayer insulating layers160and260may include silicon oxide. The interlayer insulating layers160and260may be formed by CVD, physical vapor deposition (PVD), ALD, spin-on coating, or the like. After the interlayer insulating layers160and260are formed, upper portions of the interlayer insulating layers160and260may be partially removed together with the dummy capping layers134and234, and the dummy gate electrodes132and232may be exposed. Referring toFIGS.30A and30B, the dummy gate electrodes132and232may be removed to form recesses132R and232R. For example, the dummy gate electrodes132and232may be removed by dry etching. A gas, e.g., Cl2, HBr, SF6, or CF4, may be used for etching. Referring toFIG.31, the dummy gate insulating layers130and230, the sacrificial layers111,113, and115of the first stack110, and the sacrificial layers211,213, and215of the second stack210may be removed to form openings OP1and OP2. The sacrificial layers111,113,115,211,213, and215having an etch selectivity with respect to the first channel layers112,114, and116and the second channel layers212,214, and216may be removed by selective etching. The inner spacers140and240may prevent the source/drain regions150and250from being etched. Referring toFIGS.1to3, the gate electrode170and the gate dielectric layer172may be formed in the recess132R and the opening OP1of the first region I. The gate dielectric layer172may be conformally formed along the surfaces of the buried insulating layer103, the second semiconductor layer104, the first channel layers112,114, and116, the gate spacer135, and the inner spacer140. The gate electrode170may be formed on the gate dielectric layer172. The gate electrode270and the gate dielectric layer272may be formed in the recess232R and the opening OP2of the second region II. The gate dielectric layer272may be conformally formed along the surfaces of the device isolation layer203, the base layer204, the second channel layer212,214, and216, the gate spacer235, and the inner spacer240. The gate electrode270may be formed on the gate dielectric layer272. By way of summation and review, example embodiments are directed to providing a semiconductor device including a first channel layer and a second channel layer which have different crystallographic orientations. In addition, example embodiments are also directed to providing a method of manufacturing a semiconductor device including a first channel layer and a second channel layer which have different crystallographic orientations. That is, according to the example embodiments, since a first channel layer and a second channel layer have different crystallographic orientations, e.g., silicon having a (100) orientation and silicon having a (110) orientation, a semiconductor device having a fast operating speed can be realized by optimizing carrier mobility, e.g., electrons and holes, in respective NMOS and PMOS transistors in accordance with the crystallographic orientations. In order to form a semiconductor device having a hybrid crystal orientation, a silicon on insulator (SOI) substrate having the hybrid crystal orientation may be used. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 42,503 |
11862640 | While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the appended claims. DETAILED DESCRIPTION In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention might be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. Further, it will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements. Systems and methods for efficiently creating layout for memory bit cells are contemplated. In various implementations, one or more standard cells include cross field effect transistors (FETs). As used herein, “Cross FETs” are also referred to as a “XFETs.” Additionally, as used herein, a “transistor” is also referred to as a “semiconductor device” or a “device.” In some implementations, the Cross FETs are vertically stacked gate all around (GAA) transistors such as a top vertical GAA transistor (or GAA transistor) is formed vertically on top of a bottom GAA transistor with at least an isolating oxide layer in between the two GAA transistors. In addition, the top GAA transistor has one or more conducting channels positioned orthogonal to the one or more conducting channels of the bottom GAA transistor. Therefore, the direction of current flow of the top GAA transistor through one or more top channels is orthogonal to the direction of current flow of the one or more bottom channels of the bottom GAA transistor. The top GAA transistor has a doping polarity of one or more top channels that is an opposite polarity of the doping polarity of one or more bottom channels of the bottom GAA transistor. For example, in an implementation, the top GAA transistor includes one or more p-type channels, whereas, the bottom GAA transistor includes one or more n-type channels. In another implementation, the p-type and n-type polarities are reversed between the one or more channels of the top GAA transistor and the bottom GAA transistor. With the orthogonal orientation between the top GAA transistor and the bottom GAA transistor, both the top and bottom GAA transistors have the maximum mobility for their respective carriers based on their orientation. An integrated circuit includes at least one integrated circuit that utilizes Cross FETs for implementing standard cells. One or more of these cells use a dual polarity local interconnect power connection to receive a voltage reference level from a backside bus. For example, a power supply reference voltage level is received by a p-type device from a backside bus where the connection traverses both a p-type local interconnect layer and an n-type local interconnect layer. Turning now toFIG.1, a generalized block diagram of a top view of a standard cell layout100is shown that uses Cross FETs. The standard cell layout100is for an inverter using Cross FETs. However, in other implementations, the characteristics and techniques used for standard cell layout100is used for a variety of other types of Boolean gates and complex gates. A three-dimensional (3-D) illustration of the p-type and n-type Cross FETs accompanies the layout100. As shown, a p-type device is vertically stacked on an n-type device. The n-type device includes at least an n-type gate102formed all around an n-type channel104. Similarly, a p-type gate106is formed all around a p-type channel108. Therefore, the p-type channel108has a doping polarity that is an opposite polarity of the n-type channel104of the bottom n-type device. Although a single n-type channel104and a single p-type channel108is shown, in other implementations, the semiconductor devices include another number of channels. In some implementations, the channel is a lateral nanowire. In other implementations, the channel is a nanosheet. The n-type channel104and the n-type gate102are oriented in an orthogonal direction to the p-type channel108and the p-type gate106. In other words, the n-type channel104and the n-type gate102are oriented in a direction that is 90 degrees from a direction of the p-type channel108and the p-type gate106. Therefore, the direction of current flow of the bottom n-type device through the n-type channel104is orthogonal to the direction of current flow of the p-type channel108of the top p-type device. With the orthogonal orientation between the top p-type device and the bottom n-type device, both devices have the maximum mobility for their respective carriers based on their orientation. In addition, the orthogonal orientation of the top p-type device and the bottom n-type device allow connections between the vertically stacked devices to use a single via layer. In the standard cell layout100, the metal zero layer (M0 or Metal0)130is the top-most layer. A gate contact would be a next vertically highest layer, but the gate contacts are not shown for ease of illustration. The p-type gate106is the next vertically highest layer followed by the p-type nanosheet108, which creates the p-type channel. Insulating layers are between the top p-type device and the bottom n-type device with a gate contact formed between the devices in the insulating layers. This gate contact is not shown with the aerial top view provided by the standard cell layout100(or layout100). Cross-section views of standard cell layout are provided later. The gate contact between the vertically stacked devices is directly connected to the p-type metal gate106and the n-type metal gate102without traversing any metal layers. The via (or contact)122of the p-type device connects the drain region of the p-type device to local interconnect112of the p-type device. The via (or contact)120of the n-type device connects the drain region of the n-type device to local interconnect110of the n-type device. The vertically stacked devices of the layout100consumes less on-die area. The use of a single via layer reduces resistance and capacitance of the circuit. Compared to Fin FETs, the use of gate all around (GAA) nanowires or nanosheets provides lower threshold voltages, faster switching times, less leakage currents, and further reduction of short channel effects. Examples of short channel effects other than leakage current are latchup effects, drain-induced barrier lowering (DIBL), punchthrough, performance dependency on temperature, impact ionization, and parasitic capacitance to the silicon substrate and to the wells used for the source and drain regions. One advantage of the orthogonal orientation of the Cross FETs in the layout100includes a single via layer. In contrast, Complementary FETs (CFETs) use multiple metal layers and multiple via layers to make connections between vertically stacked devices. Gaining access to the source and drain regions of the bottom device of Cross FETs is easier than compared with CFETs. Another advantage of the orthogonal orientation of the Cross FETs in the layout100is use of the maximum mobility of each of the carriers in each device of the vertically stacked devices. Turning now toFIG.2, a generalized block diagram of a top view of a standard cell layout200is shown. The standard cell layout200is for a 2-input Boolean NAND gate using Cross FETs. A three-dimensional (3-D) illustration of the p-type and n-type Cross FETs accompanies the layout200. Contacts (or vias), materials and structures described earlier are numbered identically. As shown, an n-type device is vertically stacked on a p-type device. Similar to the layout100, in other implementations, the Cross FETs of the layout200use multiple n-type channels104and multiple p-type channels108. Similar to the layout100, the layout200uses an orthogonal orientation between the n-type channel104and the p-type channel108, and uses a single via layer to create connections between the vertically stacked devices. In contrast to Fin field effect transistors (Fin FETs), where a Fin of doped silicon has physical contact with the silicon substrate, the channels of vertical GAA devices do not have physical contact with the silicon substrate. Generally, when compared to Fin FETs, GAA transistors provide lower threshold voltages, faster switching times, less leakage currents, and further reduction of short channel effects. In some implementations, a channel of doped silicon of the GAA transistor is a nanowire. In other implementations, a channel of doped silicon of the GAA transistor is a nanosheet. A nanosheet is a sheet of doped silicon, rather than a wire of doped silicon. In other words, the nanosheet is a wider and thicker conductive wire than a lateral nanowire. The nanosheet can also be considered as a Fin that is rotated and placed on its side vertically above the silicon substrate such that the nanosheet does not have physical contact with the silicon substrate. Rather, metal gate is formed between the nanosheet and the silicon substrate. This visualization, though, does not describe the actual fabrication steps for forming the nanosheet. Vertically stacking a top GAA transistor on top of a bottom GAA transistor further increases performance, reduces power consumption, reduces on-die area consumed by the GAA transistors, and further reduces short channel effects. Complementary FETs (CFETs) include a top GAA transistor vertically stacked on top of a bottom GAA transistor with at least an oxide layer in between for isolation. However, CFETs uses a top GAA transistor with one or more channels aligned in a same direction as the one or more channels of the bottom GAA transistor. As shown earlier, Cross FETs, though, have an orthogonal orientation between the one or more channels of the top GAA transistor and the one or more channels of the bottom GAA transistor. Compared to Complementary FETs, Cross FETs have better mobility for each of the top GAA transistor and the bottom GAA transistor, which leads to higher performance. Complementary FETs use two metal layers and three via layers to create connections between the top GAA transistor and the bottom GAA transistor. In contrast, Cross FETs utilize a single metal layer and a single via layer for connections between the top and bottom GAA transistors. Cross FETs have the bottom GAA transistor formed in a first wafer while the top GAA transistor is formed in a second wafer using conventional semiconductor fabrication steps. The first wafer and the second wafer are connected to one another through a hybrid bond process, which increases yield. In the following description, layout techniques for forming an inverter are shown inFIGS.3-5. These techniques are also used for forming a six transistor (6T) random access data storage of a memory bit cell that consumes a planar area above a silicon substrate of four transistors. This memory bit cell that uses Cross FETs is used in a memory bank as shown inFIG.6. The layout techniques for forming the 6T random access data storage of the memory bit cell are shown inFIGS.7-15. Turning now toFIG.3, a generalized block diagram of a top view of a standard cell layout300is shown. The top view of the layout300is shown on the right, and the cross-sectional view is shown on the left. For this inverter, a p-type device is being vertically stacked on an n-type device. However, in other implementations, it is possible and contemplated to have an n-type device vertically stacked on a p-type device. Each of the devices of the inverter uses gate all around (GAA) metal that wraps around one or more nanosheets in the gate region in a 360-degree manner. The bottom n-type device is fabricated on a first wafer. The top p-type device is fabricated on a separate second wafer, which is then bonded to the first wafer as described later. Here, in layout300, a silicon on insulator (SOI) oxide layer304is deposited on the silicon substrate302. In various implementations, the SOI oxide layer304is a silicon dioxide (SiO2) layer. The semiconductor device fabrication process is building a local silicon on insulator (SOI) which insulates the body of the device from the silicon substrate302. In an implementation, the formed SOI oxide layer304is relatively thick. A stack of channels is formed over the SOI oxide layer304. In an implementation, the stack of channels are n-type nanosheets306. Gate metal material308is deposited followed by CMP steps to polish the gate metal308. In various implementations, titanium nitride (TiN) is used for the gate metal308. The gate metal308is provided all around the n-type nanosheets306in a 360-degree manner. An interlayer dielectric (ILD) oxide layer310is deposited around the gate region. The n-type source and drain regions314are formed. In an implementation, the n-type source and drain regions314are epitaxially grown silicon doped with Phosphorous. Afterward, the n-type local interconnect312is formed. In some implementations, n-type local interconnect312includes the tungsten, cobalt, ruthenium, or molybdenum. A silicon nitride layer316and additional ILD oxide310are formed on the initial ILD oxide310layer. For example, a silicon nitride (SiNx) layer316is deposited on the ILD oxide310layer. The chemical and electrical properties of amorphous hydrogenated silicon nitride (SiNx) make this material a good candidate for an insulating layer in integrated circuits. Each of the nitride layer316and the ILD oxide310layer are etched to create space for the gate contact318. Similarly, the nitride layer316and the ILD oxide310layer are etched to create space for the drain contact320. The gate contact318and the drain contract320are deposited in the created spaces. Referring toFIG.4, a generalized block diagram of a top view of a standard cell layout400is shown. Contacts (or vias), materials and other layout elements described earlier are numbered identically. The standard cell layout400(or layout400) on the right is a continuation of the semiconductor processing steps being performed on the layout300for an inverter using Cross FETs. A cross-sectional view of the semiconductor layers used in the layout400also accompanies the layout400and it is shown on the left. A stack of channels is formed over the n-type gate contact318in the ILD oxide layer310. In an implementation, the stack of channels are p-type nanosheets402. In some implementations, a separate wafer has alternating layers grown such as a silicon germanium semiconducting epitaxial growth layer alternating with a silicon semiconducting epitaxial growth layer. The separate wafer with the alternating layers is bonded to the top of ILD oxide layer310of the layout300(ofFIG.3). In other implementations, the alternating layers are grown on top of ILD oxide layer310of the layout300followed by one of the earlier named processes for etching the layers to the size of the p-type nanosheets402. The earlier named processes were described in relation to forming the n-type nanosheets306. Turning now toFIG.5, a generalized block diagram of a top view of a standard cell layout500is shown. Contacts (or vias), materials and other layout elements described earlier are numbered identically. The standard cell layout500(or layout500) on the right is a continuation of the semiconductor processing steps being performed on the layout400for creating an inverter using Cross FETs. A cross-sectional view of the semiconductor layers used in the layout500also accompanies the layout500and it is shown on the left. The ILD oxide310layer is etched to create space for the p-type gate502, which is placed all around the p-type nanosheets402. Similarly, the ILD oxide310layer is etched to create space for the drain contact504. The gate contact318and the drain contract504are deposited in the created spaces. Here, a metal zero layer (or metal0 or Metal 0 or M0)506is deposited for creating further connections for the inverter. It is noted that the metal zero layer506is also referred to by different names in order to maintain a convention of using the metal zero layer as a horizontal layer such as in the next layer up. Referring toFIG.6, a generalized block diagram of one implementation of a multiplexer gate600is shown. In the implementation shown, the multiplexer gate600(or mux gate600) receives three input signals indicated as A650, B652and S654, and generates an output signal indicated as Z660. The mux gate600uses P5630and N5632as an inverter that generates the signal SB656from the received signal S654. The mux gate600uses the devices P5630and N5632as an inverter that generates the signal SB656from the received signal S654. The mux gate600uses the devices P6640and N6642as an inverter that generates the signal Z660from the received signal ZB602. The devices P3614and N1620receive the input signal A650, the devices P4616and N2622receive the input signal B652, and the devices P1610and N4626receive the input signal S654. Additionally, the devices P2612and N3624receive the internally generated signal SB656. The devices610-626are connected in a configuration that provides the functionality of a multiplexer. For example, when the select input signal S654is asserted, the mux gate600generates a logic level on the output signal Z660equivalent to the current logic level of the input signal A650. When the select input signal S654is negated, the mux gate600generates a logic level on the output signal Z660equivalent to the current logic level of the input signal B652. The mux gate600is an example of a transistor schematic of a type of cell that uses Cross FETs where devices of a vertical stack receive different input signals. For example, a semiconductor fabricated circuit of the mux gate600includes the p-type device P1610and the n-type device N1620in a same vertical stack. As shown, the p-type device P1610receives the signal S654, whereas, the n-type device N1620receives a different signal such as the signal A650. Similarly, a vertical stack that includes the pair of devices P2612and N2622receives different input signals. Likewise, each of a vertical stack that includes the pair of devices P3614and N3624receive different signals, and a vertical stack that includes P4616and N4626receive different signals. Such a cell with at least one vertical stack with devices that receive different input signals has at least one extended gate region to complete the internal connections of the fabricated circuit. Therefore, the height dimension of the cell increases to being greater than a height of cells that includes vertical stacks where the corresponding devices receive a same input signal. As an example, the fabricated cell of the mux gate600has a height greater than a height of a fabricate cell of the logic gate600. In the following description, the layout700(ofFIG.7) provides techniques for forming layout of the n-type devices of the mux gate600(ofFIG.6), whereas, the layout800(ofFIG.8) provides techniques for forming layout of the p-type devices of the mux gate600. Contacts (or vias), materials and other layout elements described earlier are numbered identically inFIGS.7-8. Turning now toFIG.7, a generalized block diagram of a top view of layout700of the mux gate600is shown. For this layout, a p-type device is being vertically stacked on an n-type device. However, in other implementations, it is possible and contemplated to have an n-type device vertically stacked on a p-type device. Here, in layout700ofFIG.7, a stack of n-type nanosheets, the metal gate, the n-type local interconnect312, and the drain contact320are formed for the layout of the mux gate600(ofFIG.6) in a similar manner as described earlier for an inverter. The signal names and the device names used in the mux gate600are shown here to aid the description of the forming of the layout. The n-type local interconnect312is used to provide the node X1670between the n-type transistors N3624and N1620, and to provide the node X2672between the n-type transistors N4626and N2622. The p-type nanosheets402are formed, the p-type gate metal material702is deposited, and the p-type local interconnect508is formed as described earlier. The p-type local interconnect508is used to provide the node X3674between the p-type transistors P4616and P1610, and to provide the node X4676between the p-type transistors P3614and P2612. In the layout800ofFIG.8, a metal zero layer (M0)506and a metal layer802between the p-type local interconnect508and the M0506is deposited for creating further connections for the layout of the mux gate600. The layout is later fabricated, and the mux gate600is a portion of an entire integrated circuit. Referring now toFIG.9, one embodiment of power connections900is shown. Contacts (or vias), materials, structures and other layout elements described earlier are numbered identically. A power bus902below the silicon substrate904routes one or more power signals such as at least a power supply reference voltage level (VDD) and a ground reference voltage level (VSS). These signals of the power bus902are routed through the silicon substrate904with the use of through silicon vias (TSVs)906. A contact (or via)908routes the power signal to a local interconnect layer. In one implementation, a p-type device is being vertically stacked on an n-type device. However, in other implementations, it is possible and contemplated to have an n-type device vertically stacked on a p-type device. The contact908physically connects to the n-type local interconnect312. Therefore, the ground reference voltage level (VSS) is routed to a source region of an n-type device. In some cases, the n-type local interconnect312is not used by an n-type device such as the n-type local interconnect312located on the left side of the diagram. This particular n-type local interconnect312is used to provide rigidity and strength to a power signal route between a power supply reference voltage level (VDD) originating from a TSV906and a p-type device located above n-type devices. The contact910physically connects to each of the n-type local interconnect312and a p-type local interconnect508. The source region of a p-type device is able to receive the power supply reference voltage level (VDD). Turning toFIG.10, one embodiment of power connections1000for standard cells utilizing Cross FETs is shown. Here, the layout of a mux gate, such as the layout700-800, replicated as the mux gate is repeatedly instantiated. For example, the layout of the mux gate is mirrored and flipped repeatedly. Although a mux gate is shown as a cell being repeatedly instantiated, it is contemplated that a variety of cells providing different functionalities can be instantiated in an integrated circuit and use the power connection techniques shown in the upcoming figures. The n-type local interconnect layer1002is used to route a ground reference voltage level to the source regions of n-type devices of the cells. The p-type local interconnect layer1004is used to route a power supply reference voltage level to the source regions of p-type devices of the cells. As shown, additional n-type local interconnect is added, which is not used by an n-type device. These repeated additional instantiations of the n-type local interconnect1002are used to route the power supply reference voltage level to the source regions of p-type devices of the cells. The vias1006provide a connection from the p-type local interconnect layer1004to the n-type local interconnect layer1002and to a through silicon via in the silicon substrate. For example, the additional n-type local interconnect1002is used to create a dual polarity local interconnect power connection such as the connection920shown earlier inFIG.9. Power rails routed in both the n-type local interconnect layer1002and the p-type local interconnect layer1004provide redundancy for the power connections and improve wafer yield. In the power connections1100(ofFIG.11), the backside rails and vias of the ground reference voltage level (VSS)1102are shown being routed horizontally below the power rails routed in the p-type local interconnect layer1004. Similarly, the backside rails and vias of the power supply voltage level (VDD)1104are shown being routed horizontally below the power rails routed in the n-type local interconnect layer1004. In various implementations, the backside rails and vias1102of VSS are rails similar to the power bus902labeled VSS inFIG.9. Similarly, the backside rails and vias1104of VDD are rails similar to the power bus902labeled VDD inFIG.9. It is noted that power connections, such as connections920(ofFIG.9) are also directly above the backside rail1104. In the power connections1200(ofFIG.12), the backside rails and vias1102and1104are shown being routed vertically below the power rails routed in the p-type and n-type local interconnect layers1002and1004. In the power connections1300(ofFIG.13), the power rails using the p-type local interconnect layer1004are removed, or otherwise, not used. Therefore, the added power connections using the n-type local interconnect layer1002, such as power connection920, no longer have redundancy. Similarly, the p-type devices no longer have redundancy with power connections. Such a design choice is used when wafer yield is expected to be high. One of the horizontal and vertical routing of the backside power buses can be used with this configuration. For example, the backside routing shown inFIGS.11-12can be used. In the power connections1400(ofFIG.14), the power rails using the n-type local interconnect layer1004are removed, or otherwise, not used. Therefore, the n-type devices no longer have redundancy with power connections. Such a design choice is used when wafer yield is expected to be high. One of the horizontal and vertical routing of the backside power buses as shown inFIGS.11-12can be used with this configuration. In the power connections1500(ofFIG.15), the power rails using the n-type local interconnect layer1024are removed, or otherwise, not used. Additionally, the backside rails and vias of the ground reference voltage level (VSS)1102are shown being routed horizontally below the power rails routed in the p-type local interconnect layer1004. Similarly, the backside rails and vias of the power supply voltage level (VDD)1104are shown being routed horizontally below the power rails routed in the n-type local interconnect layer1004. In the power connections1600(ofFIG.16), the power rails using the n-type local interconnect layer1002are removed, or otherwise, not used. Therefore, the n-type devices no longer have redundancy with power connections. Additionally, the power rails using the p-type local interconnect layer1004are removed, or otherwise, not used. Therefore, the added power connections using the n-type local interconnect layer1002, such as power connection920, no longer have redundancy. Similarly, the p-type devices no longer have redundancy with power connections. Such a design choice is used when wafer yield is expected to be high. In the power connections1700(ofFIG.17), both the power rails using the n-type local interconnect layer1002and the power rails using the p-type local interconnect layer1004are removed, or otherwise, not used. The backside rails and vias1102and1104are shown being routed vertically. Referring now toFIG.18, one embodiment of a method1800for efficiently creating layout for standard cells that utilize Cross FETs is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. However, in other embodiments some steps occur in a different order than shown, some steps are performed concurrently, some steps are combined with other steps, and some steps are absent. A semiconductor fabrication process forms cells using Cross FETs (block1802). The semiconductor fabrication process (or process) forms a given cell with a transistor receiving a power connection directly through local interconnect layers of both p-type and n-type polarities (block1804). The process places cells including the given cell in an integrated circuit (block1806). If a potential is not applied to an input node of the integrated circuit (“no” branch of the conditional block1808), then the integrated circuit waits for power up (block1810). However, if a potential is applied to the input node of the integrated circuit (“yes” branch of the conditional block1810), then the integrated circuit conveys a current from the input node to an output node through the given cell (block1812). Referring toFIG.19, one embodiment of a computing system1900is shown. The computing system1900includes the processor1910and the memory1930. Interfaces, such as a memory controller, a bus or a communication fabric, one or more phased locked loops (PLLs) and other clock generation circuitry, a power management unit, and so forth, are not shown for ease of illustration. It is understood that in other implementations, the computing system1900includes one or more of other processors of a same type or a different type than processor1910, one or more peripheral devices, a network interface, one or more other memory devices, and so forth. In some implementations, the functionality of the computing system1900is incorporated on a system on chip (SoC). In other implementations, the functionality of the computing system1900is incorporated on a peripheral card inserted in a motherboard. The computing system1900is used in any of a variety of computing devices such as a desktop computer, a tablet computer, a laptop, a smartphone, a smartwatch, a gaming console, a personal assistant device, and so forth. The processor1910includes hardware such as circuitry. For example, the processor1910includes at least one integrated circuit1920, which utilizes Cross FETs for implementing standard cells. For example, the integrated circuit includes cells1922where one or more of these cells1922uses dual polarity local interconnect power connection as shown earlier with connection920(ofFIG.9). In various implementations, the processor1910includes one or more processing units. In some implementations, each of the processing units includes one or more processor cores capable of general-purpose data processing, and an associated cache memory subsystem. In such an implementation, the processor1910is a central processing unit (CPU). In another implementation, the processing cores are compute units, each with a highly parallel data microarchitecture with multiple parallel execution lanes and an associated data storage buffer. In such an implementation, the processor1910is a graphics processing unit (GPU), a digital signal processor (DSP), or other. In some implementations, the memory1930includes one or more of a hard disk drive, a solid-state disk, other types of flash memory, a portable solid-state drive, a tape drive and so on. The memory1930stores an operating system (OS)1932, one or more applications represented by code1934, and at least source data1936. Memory1930is also capable of storing intermediate result data and final result data generated by the processor1910when executing a particular application of code1934. Although a single operating system1932and a single instance of code1934and source data1936are shown, in other implementations, another number of these software components are stored in memory1930. The operating system1932includes instructions for initiating the boot up of the processor1910, assigning tasks to hardware circuitry, managing resources of the computing system1900and hosting one or more virtual environments. Each of the processor1910and the memory1930includes an interface unit for communicating with one another as well as any other hardware components included in the computing system1900. The interface units include queues for servicing memory requests and memory responses, and control circuitry for communicating with one another based on particular communication protocols. The communication protocols determine a variety of parameters such as supply voltage levels, power-performance states that determine an operating supply voltage and an operating clock frequency, a data rate, one or more burst modes, and so on. It is noted that one or more of the above-described embodiments include software. In such embodiments, the program instructions that implement the methods and/or mechanisms are conveyed or stored on a computer readable medium. Numerous types of media which are configured to store program instructions are available and include hard disks, floppy disks, CD-ROM, DVD, flash memory, Programmable ROMs (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Generally speaking, a computer accessible storage medium includes any storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium includes storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media further includes volatile or non-volatile memory media such as RAM (e.g. synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, Flash memory, non-volatile memory (e.g. Flash memory) accessible via a peripheral interface such as the Universal Serial Bus (USB) interface, etc. Storage media includes microelectromechanical systems (MEMS), as well as storage media accessible via a communication medium such as a network and/or a wireless link. Additionally, in various embodiments, program instructions include behavioral-level descriptions or register-transfer level (RTL) descriptions of the hardware functionality in a high level programming language such as C, or a design language (HDL) such as Verilog, VHDL, or database format such as GDS II stream format (GDSII). In some cases the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represent the functionality of the hardware including the system. The netlist is then placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks are then used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer accessible storage medium are the netlist (with or without the synthesis library) or the data set, as desired. Additionally, the instructions are utilized for purposes of emulation by a hardware based type emulator from such vendors as Cadence®, EVE®, and Mentor Graphics®. Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. | 35,719 |
11862641 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS An array substrate and a manufacturing method thereof are provided by the present disclosure. In order to make the objects, technical solutions, and effects of the present disclosure clearer and more specific, the present disclosure is described in further detail below with reference to the embodiments accompanying the drawings. It should be understood that the specific embodiments described here are only used to explain the present disclosure, and not used to limit the present disclosure. Embodiment 1 Please refer toFIG.1, which is a structural schematic diagram of an array substrate provided by an embodiment of the present disclosure. In the present embodiment, the array substrate includes a substrate10, a photosensitive unit disposed on the substrate10, and the photosensitive unit includes a storage capacitor1100, a switch thin film transistor1300, and a photosensor1200located between storage capacitor1100and the switch thin film transistor1300, wherein the photosensor1200is a photodiode structure. The array substrate further includes a first electrode layer, a gate insulating layer30, a semiconductor layer, a second electrode layer, an insulating layer60, and a transparent electrode layer70which are sequentially stacked on the substrate10. In the present embodiment, the substrate10is a PI substrate, which is mainly made of polyimide, and polyimide can effectively improve the light transmittance. In the present embodiment, the first electrode layer includes a first electrode21, a second electrode22, and a third electrode23arranged in spaces. The material of the first electrode layer includes, but is not limited to, metals such as copper, aluminum, and silver. The thickness of the first electrode layer ranges from 500 to 10000 Å, which is not limited in the present embodiment. In the present embodiment, the array substrate further includes a first barrier layer disposed on the first electrode layer, wherein the first barrier layer includes a first sub-barrier layer disposed on the first electrode21, a second sub-barrier layer disposed on the second electrode22, and a third sub-barrier layer disposed on the third electrode23. The materials of the first sub-barrier layer, the second sub-barrier layer, and the third sub-barrier layer include, but are not limited to, metals such as molybdenum, titanium, and molybdenum-titanium alloy. The thickness of the first sub-barrier layer, the thickness of the second sub-barrier layer, and the thickness of the third sub-barrier layer all ranges from 50 to 1000 Å, which are not limited in the present embodiment. In the present embodiment, the semiconductor layer includes a first semiconductor layer41and a second semiconductor layer42, the first semiconductor layer41is disposed on the first electrode21and the third electrode23, and the second semiconductor layer42is disposed on the second electrode22. In the present embodiment, the first semiconductor layer41is a multiple-layered structure including a first amorphous silicon layer411and a first N-type heavily doped amorphous silicon layer412. The second semiconductor layer42is a multiple-layered structure including a second N-type heavily doped amorphous silicon layer421, a second amorphous silicon layer422, and a P-type heavily doped amorphous silicon layer423arranged in layers. In the present embodiment, the second electrode layer includes a fourth electrode51, a drain52, and a source53, the fourth electrode51is disposed on the first electrode21, and the drain52and the source53are disposed on two opposite edge regions of the third electrode23. The material of the second electrode layer20includes, but is not limited to, metals such as copper, aluminum, and silver. The thickness of the second electrode layer20ranges from 500 to 10000 Å, which is not limited in the present embodiment. In the present embodiment, the array substrate further includes a second barrier layer disposed on the second electrode layer, wherein the second barrier layer includes a fourth sub-barrier layer disposed on the fourth electrode51, a fifth sub-barrier layer disposed on the drain52, and a sixth sub-barrier layer disposed on the source53. The materials of the fourth sub-barrier layer, the fifth sub-barrier layer, and the sixth sub-barrier layer include, but are not limited to, metals such as molybdenum, titanium, and molybdenum-titanium alloy. The thickness of the fourth sub-barrier layer, the thickness of the fifth sub-barrier layer, and the thickness of the sixth sub-barrier layer all ranges from 50 to 1000 Å, which are not limited in the present embodiment. In the present embodiment, the insulating layer60includes a first insulating layer61and a second insulating layer62arranged in layers, which are disposed on the first semiconductor layer41, the second semiconductor layer42, and the gate insulating layer30. In the present embodiment, an opening hole partially exposing the second electrode22is defined by the gate insulating layer30, the first insulating layer61and the second insulating layer62, and the second semiconductor layer42contacts the second electrode22through the opening hole. In the present embodiment, the transparent electrode layer70includes a first transparent electrode71and a second transparent electrode72. An opening hole partially exposing the second semiconductor layer42is defined by the first insulating layer61and the second insulating layer62, and the first transparent electrode71contacts the second semiconductor layer42through the opening hole. In the present embodiment, the material of the transparent electrode layer70includes, but is not limited to, indium tin oxide and indium zinc oxide, which is not limited in the present embodiment. In the present embodiment, via holes are defined by the first electrode21, the second electrode22, and the drain52. The first transparent electrode71is connected to the first electrode21by the via hole on the first electrode21, the second transparent electrode72is connected to the second electrode22by the via hole on the second electrode22and is connected to the drain52by the via hole on the drain52. In the present embodiment, the storage capacitor1100includes the first electrode21, the first semiconductor layer41, and the fourth electrode51arranged in layers. The two electrode plates of the storage capacitor1100are the first electrode21and the fourth electrode52. The insulating dielectric layer between the two electrode plates of the storage capacitor1100includes, but is not limited to, the first insulating layer61, the first amorphous silicon layer411, and the first N-type heavily doped amorphous silicon layer41, which is not limited in the present embodiment. In the present embodiment, the photosensor1200includes the second electrode22, the second semiconductor layer42, and the first transparent electrode71arranged in layers. In the present embodiment, the switch thin film transistor1300includes the third electrode23, the first semiconductor layer41, the drain52, and the source53. Please refer toFIG.2, which is a circuit diagram of an array substrate provided by an embodiment of the present disclosure. In the present embodiment, the third electrode23of the switch thin film transistor1300is connected to a scan signal (Vg), the source53is connected to a readout signal (Read out), the drain52is connected to the second electrode22of the photosensor1200and the fourth electrode51of the storage capacitor1100. The first electrode21of the storage capacitor1100is connected to a low-potential power source (VSS) and the first transparent electrode71of the photosensor1200, the fourth electrode51of the storage capacitor1100is connected to the drain52of the switch thin film transistor1300and the second electrode22of the photosensor1200. In the present embodiment, the first transparent electrode71is the positive electrode of the photosensor1200, and the second electrode22is the negative electrode of the photosensor1200. In the present embodiment, the storage capacitor1100, the switch thin film transistor1300, and the photosensor120are connected through the transparent electrode layer70. In the present embodiment, the array substrate further includes a protective cover plate100disposed opposite the substrate10, wherein a light-shielding layer80is disposed on a surface of the protective cover plate100facing the substrate10, and a spacer90is disposed on a surface of the substrate10facing the protective cover plate100. The light-shielding layer80corresponds to the switch thin film transistor1300, and a projection of the third electrode23projected on the substrate10is located within the light-shielding layer80. A projection of the light-shielding layer80projected on the substrate10does not overlap with the second electrode22. The spacer90supports the substrate10and the protective cover plate100, and a projection of the spacer90projected on the substrate10does not overlap with each film layer. In the present disclosure, a photodiode structure is used as the photosensor1200in the array substrate. The semiconductor structure in the photosensor includes the second N-type heavily doped amorphous silicon layer421, the second amorphous silicon layer422, and the P-type heavily doped amorphous silicon layer423, thereby realizing the integration of photosensors into large-sized devices, the enhancement of device sensitivity, and the reduction of costs. Embodiment 2 Please refer toFIG.3, which is a flow chart of a manufacturing method of an array substrate provided by the present disclosure. In the present embodiment, the manufacturing method of an array substrate includes: Block S10: forming a first metal layer on a substrate10, and patterning the first metal layer to form a first electrode layer, wherein the first electrode layer includes a first electrode21, a second electrode22, and a third electrode23arranged in spaces, as shown inFIG.4A. In the present embodiment, the thickness of the first electrode layer ranges from 500 to 10000 Å, which is not limited in the present embodiment. In the present embodiment, the block S10includes following blocks: Block S11: providing the substrate10. The substrate10includes, but is not limited to, a glass substrate and a flexible substrate. Further, in the present embodiment, the substrate10is a flexible and transparent PI substrate, which is mainly made of polyimide, and polyimide can effectively improve the light transmittance. Block S12: depositing the first metal layer on the substrate10. The material of the first metal layer includes, but is not limited to, metals such as aluminum, molybdenum, titanium, copper, and alloys thereof. The method of depositing the first metal layer includes, but is not limited to, physical vapor deposition. Block S13: depositing a first metal barrier layer. The material of the first metal barrier layer includes, but is not limited to, metals such as molybdenum, titanium, and molybdenum-titanium alloy. The thickness of the first metal barrier layer ranges from 50 to 1000 Å, which is not limited in the present embodiment. Block S14: patterning the first metal layer and the first metal barrier layer by a mask, wherein the first metal layer is formed into a first electrode21, a second electrode22, and a third electrode23arranged in spaces, the first metal barrier layer is formed into a first sub-barrier layer disposed on the first electrode21, a second sub-barrier layer disposed on the second electrode22, and a third sub-barrier layer disposed on the third electrode23. It should be noted that, in the present embodiment, the first metal layer and the first metal barrier layer may also be deposited on the substrate10at the same time. In the present embodiment, the first metal layer and the first metal barrier layer are separately deposited for illustration only, which is not limited in the present embodiment. Block S20: forming a gate insulating layer30, a first semiconductor layer41, and a second metal layer on the first electrode layer, and patterning the second metal layer and the first semiconductor layer41to form a second electrode layer, wherein the second electrode layer includes a fourth electrode51, a drain51, and a source53, the fourth electrode51is disposed on the first electrode21, and the drain51and the source53are disposed on two opposite edge regions of the third electrode23, as shown inFIG.4B. In the present embodiment, the block S20includes: Block S21: forming the gate insulating layer30on the first electrode layer. The gate insulating layer30completely covers the first electrode21, the second electrode22, and the third electrode23. The method of forming the gate insulating layer30includes, but not limited to, chemical vapor deposition. Block S22: forming the first semiconductor layer41on the gate insulating layer30, wherein the first semiconductor layer41includes a first amorphous silicon layer411and a first N-type heavily doped amorphous silicon layer412formed on the gate insulating layer30in sequence. Block S23: depositing the second metal layer on the gate insulating layer30and the first semiconductor layer41. The material of the second metal layer includes, but is not limited to, metals such as aluminum, molybdenum, titanium, copper, and alloys thereof. The method of depositing the second metal layer includes, but is not limited to, physical vapor deposition. In the present embodiment, the block S23includes depositing a second metal barrier layer. The material of the second metal barrier layer includes, but is not limited to, metals such as molybdenum, titanium, and molybdenum-titanium alloy. The thickness of the second metal barrier layer ranges from 50 to 1000 Å, which is not limited in the present embodiment. Block S24: patterning the second metal layer and the first semiconductor layer41by a mask to form the second electrode layer, wherein the second electrode layer includes the fourth electrode51, the drain52, and the source53. In the present embodiment, the thickness of the first electrode layer ranges from 500 to 10000 Å, and the patterned first semiconductor layer41is located on the first electrode21and the third electrode23. In the present embodiment, the block S24includes: patterning the second metal layer, the second metal barrier layer, and the first semiconductor layer41by a mask, wherein the second metal layer is formed into the fourth electrode51, the drain52, and the source53arranged in spaces, and the second metal barrier layer is formed into a fourth sub-barrier layer located on the fourth electrode51, a fifth sub-barrier layer located on the drain52, and a sixth sub-barrier layer located on the source53. It should be noted that, in the present embodiment, the second metal layer and the second metal barrier layer may also be deposited on the substrate at the same time. In the present embodiment, the second metal layer and the second metal barrier layer are separately deposited for illustration only, which are not limited in the present embodiment. In the present embodiment, the patterned first semiconductor layer41is located on the first electrode21and the third electrode23. Block S30: forming a first insulating layer61on the gate insulating layer30, the fourth electrode51, the drain52, and the source53, and patterning the first insulating layer61and the gate insulating layer30to form an opening hole partially exposing the second electrode22, as shown inFIG.4C. In the present embodiment, the method of forming first insulating layer61includes, but not limited to, chemical vapor deposition. Block S40: forming a second semiconductor layer42on an exposed portion of the second electrode22, as shown inFIG.4D. In the present embodiment, the method of forming the second semiconductor layer42includes, but is not limited to, chemical vapor deposition, and the process gases used include, but are not limited to, phosphine, silane, hydrogen, nitrogen, argon, and helium. In the present embodiment, the block S40includes: forming a second N-type heavily doped amorphous silicon layer421, a second amorphous silicon layer422, and a P-type heavily doped amorphous silicon layer423on the exposed portion of the second electrode22in sequence. The second semiconductor layer42includes the second N-type heavily doped amorphous silicon layer421, the second amorphous silicon layer422, and the P-type heavily doped amorphous silicon layer423arranged in layers. Block S50: forming a second insulating layer62on the first insulating layer61and the second semiconductor layer42, and patterning the second insulating layer62, the first insulating layer61, and the gate insulating layer30to form a via hole on the first electrode22, a via hole on the second electrode23, a via hole on the drain52, and an opening hole partially exposing the second semiconductor layer42, as shown inFIG.4E. In the present embodiment, the Block S50includes following steps: Block S51: forming the second insulating layer62on the first insulating layer61and the second semiconductor layer42. The method of forming the second insulating layer62includes, but is not limited to, chemical vapor deposition. Block S52: patterning the second insulating layer62, the first insulating layer61, and the gate insulating layer30by a mask to form the via hole on the first electrode22, the via hole on the second electrode23, the via hole on the drain52, and the opening hole partially exposing the second semiconductor layer42. Block S60: forming a transparent electrode layer70on the second insulating layer62and the second semiconductor layer42, and patterning the transparent electrode layer70to form a first transparent electrode71and a second transparent electrode72, wherein the first transparent electrode71is connected to the first electrode21by the via hole on the first electrode21, the second transparent electrode72is connected to the second electrode22by the via hole on the second electrode22and is connected to the drain52by the via hole on the drain52, as shown inFIG.4F. In the present embodiment, the method of forming the transparent electrode layer70include, but is not limited to, physical vapor deposition, and the material of the transparent electrode layer70includes, but is not limited to, indium tin oxide and indium zinc oxide. In the present embodiment, the manufacturing method of the array substrate further includes: Block S70: forming a spacer90on the substrate10, and a projection of the spacer90projected on the substrate10does not overlap with each film layer. Block S80: forming a protective cover plate100on a surface of the spacer90away from the substrate10, and the spacer90supports the substrate10and the protective cover plate100. In the present embodiment, the manufacturing method further includes: forming a light-shielding layer80on a surface of the protective cover plate100facing the substrate10, wherein a projection of the third electrode23projected on the substrate10is located within the light-shielding layer80. The light-shielding layer80is located between the protective cover plate100and the substrate10, and the light-shielding layer80is located on the third electrode23, wherein a projection of the light-shielding layer80projected on the substrate10does not overlap with the second electrode22. In combination withFIG.1, in the present embodiment, the array substrate includes a photosensitive unit disposed on the substrate10, and the photosensitive unit includes a storage capacitor1100, a switch thin film transistor1300, and a photosensor1200located between storage capacitor1100and the switch thin film transistor1300. The storage capacitor1100includes the first electrode21, the first semiconductor layer41, and the fourth electrode51arranged in layers. The switch thin film transistor1300includes the third electrode23, the first semiconductor layer41, the drain52, and the source53. The light-shielding layer80corresponds to the switch thin film transistor1300. The photosensor1200includes the second electrode22, the second semiconductor layer42, and the first transparent electrode71arranged in layers. In summary, an array substrate and a manufacturing method thereof are provided by the present disclosure. The array substrate includes a substrate, a photosensitive unit disposed on the substrate, the photosensitive unit includes a storage capacitor, a switch thin film transistor, and a photosensor located between storage capacitor and the switch thin film transistor, wherein the photosensor is a photodiode structure, and a semiconductor structure in the photosensor includes a N-type heavily doped amorphous silicon layer, an amorphous silicon layer, and a P-type heavily doped amorphous silicon layer arranged in layers. In the present disclosure, a photodiode structure is used as a photosensor in an array substrate. The semiconductor structure in the photosensor includes a N-type heavily doped amorphous silicon layer, an amorphous silicon layer, and a P-type heavily doped amorphous silicon layer, thereby realizing the integration of photosensors in large-sized devices, the enhancement of device sensitivity, and the reduction of costs. In view of the above, although the present invention has been disclosed by way of preferred embodiments, the above preferred embodiments are not intended to limit the present invention, and one of ordinary skill in the art, without departing from the spirit and scope of the invention, the scope of protection of the present invention is defined by the scope of the claims. | 21,669 |
11862642 | DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION To make objectives, technical schemes, and effects of the present invention clearer and more specific, the present invention is described in further detail below with reference to the drawings. It should be understood that the specific embodiments described herein are merely for explaining the present invention, a term “embodiment” used in the specification of the present invention means an example, instance, or illustration, and are not intended to limit the present invention. The present invention provides a display panel, an array substrate, and a manufacturing method thereof, which have effects of reducing a number of photomasks required for preparing the array substrate and reducing production costs. To facilitate understanding of the present invention, the array substrate of the present invention may be a low temperature poly-silicon (LTPS) thin film transistor array (TFT array) substrate. Refer toFIG.2, which is a schematic diagram showing the array substrate according to an embodiment of the present invention. The array substrate20in the present invention includes a base substrate201, and a light shielding layer202, a buffer layer203, an active layer204, a gate insulation layer205, a gate electrode206, an inter insulation layer207, a source electrode209aand drain electrode209b, an interface layer (or interfacial layer, IL)2010, a first transparent conductive layer2011, a passivation layer2012, and a second transparent conductive layer2014which are formed on the base substrate201in sequence, wherein the gate insulation layer205and the inter insulation layer207are provided with source and drain vias208at positions corresponding to a source and drain, respectively, and the source electrode209aand the drain electrode209bare electrically connected to the source and drain located at the active layer204by the source and drain vias208, respectively. The interface layer2010and the passivation layer2012are provided with a first via2013aat a position corresponding to the drain electrode209b, the passivation layer2012is provided with a second via2013bat a position corresponding to a portion of the first transparent conductive layer2011, and the first transparent conductive layer2011is electrically connected to the drain electrode209bby the first via2013aand the second via2013b. In the present embodiment, the first transparent conductive layer2011serves as a pixel electrode in the present invention, and the second transparent conductive layer2014serves as a common electrode in the present invention. For the sake of convenience, the “pixel electrode” and “common electrode” are referred and are used for description below. In the present embodiment, the base substrate201may be a glass substrate or a resin substrate, and a material of the light shielding layer202may be made of a metal material in black color, they are not specifically limited by the present invention. In the present embodiment, the buffer layer203is formed of two insulation materials. Specifically, a silicon-nitride (SiNx) thin film203ais deposited on the base substrate201to isolate metal atoms in the base substrate201from diffusing to the active layer204formed on the buffer layer203for preventing an electrical impact on the active layer204. However, lattice constants of the SiNx thin film203aand the active layer204are mismatched. Therefore, in order to prevent unnecessary lattice defects caused by the mismatched lattice constants on the active layer204, a silicon-oxide (SiOx) thin film203bis deposited on the SiNx thin film203afor preventing the problem of the lattice defects. Further, after the buffer layer203is prepared, an annealing treatment may be performed to optimize quality of the buffer layer203. In another embodiment, the buffer layer203may be formed of single insulation material (such as SiOx thin film). It can be understood that the material and a structure of the buffer layer203should not be used to limit the present invention. In the present embodiment, in order to improve carrier mobility, excimer-laser annealing (ELA) is preferably used to transform the active layer204from amorphous silicon (a-Si) to polycrystalline silicon in the present invention. Specifically, the active layer204with amorphous silicon may be deposited on the buffer layer203by means of plasma-enhanced chemical vapor deposition (PECVD), then high-energy laser pulses generated by an excimer laser device are incident on a surface of the amorphous silicon thin film, so that the amorphous silicon thin film melts in an instant when it receives energy having an extremely high-temperature, and a conversion of amorphous silicon to polycrystalline silicon is realized. In another embodiment, the polycrystalline silicon can also be prepared by means of solid phase crystallization (SPC) or metal induced crystallization (MIC), and the like. It can be understood that the excimer laser annealing is used as a preferred embodiment to illustrate the present invention in the present invention, and it should not be used to limit the present invention. In the present embodiment, as a size of a metal-oxide-semiconductor field effect transistor (MOSFET) device is shrinking, a hot carrier effect in the device is becoming more and more serious. Therefore, in order to improve operation stability of the device and leakage currents of the device under a negative bias, lightly doped drain (LDD) areas204bare formed in a channel of the active layer204adjacent to heavily-doped areas204aof a source and drain in the low temperature poly-silicon thin film transistor array substrate20. By means of gate re-etching technology, the heavily-doped areas204aand lightly doped drain areas204bof the source and drain are realized in the present invention. Specifically, when a blanket gate electrode layer (unmarked) is formed on the gate insulation layer205, photolithography and etching processes are performed on the blanket gate electrode layer through one photomask, and a gate pattern (unmarked) treated with the photolithography and etching processes is taken as a hard mask, then n-type ions (such as phosphorus ions P+) is heavily doped to both ends of the active layer204to form the heavily-doped areas204aof the source and drain. After then, the gate pattern is re-etched to obtain the gate electrode206, and un-doped areas adjacent to the heavily-doped areas204aof the source and drain in the channel of the active layer204are exposed. More, the gate electrode206is taken as a hard mask, and n-type ions (such as phosphorus ions P−) are lightly doped to the active layer204to form the LDD areas204b, thereby the heavily-doped areas204aand lightly doped drain areas204bof the source and drain are realized. In another embodiment, a photoresist pattern with a pattern of the heavily-doped areas204aof the source and drain is formed on the active layer204through one photomask, then n-type ions are heavily doped. After the photoresist pattern is removed, the gate insulation layer205and the blanket gate electrode layer (unmarked) are deposited on the buffer layer203in sequence, and the blanket gate electrode layer is performed with photolithography and etching processes by using another photomask to obtain the gate electrode206. At this time, un-doped areas adjacent to the heavily-doped areas204aof the source and drain in the channel of the active layer204are exposed. Furthermore, the gate electrode206is taken as a hard mask, and n-type ions is lightly doped to the active layer204to form the LDD areas204b, thereby the heavily-doped areas204aand lightly doped drain areas204bof the source and drain are realized. The gate re-etching technology is preferably used to reduce the number of photomasks used to prepare the heavily-doped areas204aand lightly doped drain areas204bof the source and drain and to reduce the production costs in the present invention. In the present embodiment, the low temperature poly-silicon thin film transistor array20is an n-type metal-oxide-semiconductor (NMOS) transistor. In another embodiment, the low temperature poly-silicon thin film transistor array20may also be a p-type metal-oxide-semiconductor (PMOS) transistor or a complementary metal-oxide-semiconductor (CMOS) transistor. Further, a difference between the NMOS transistor and the PMOS transistor is species of ions doped into the areas of the source and drain. If the ion species doped into the areas of the source and drain is an n-type semiconductor, it is the NMOS transistor. If the ion species is a p-type semiconductor (such as boron ion), it is the PMOS transistor, and the CMOS transistor can be jointly formed by the NMOS transistor and the PMOS transistor. The NMOS transistor array substrate is used as a preferred embodiment in the present invention, and the present invention should not be limited thereby. In the present embodiment, a planarization layer in the prior art is replaced by the interface layer2010formed on the inter insulation layer207and covering the source electrode209aand the drain electrode209bin the present invention. Because the interface layer2010is composed of an inorganic material and has a thinner film thickness than the planarization layer, there is no need to use two or more photomasks (or etching processes) when perforating the interface layer to form vias, and the number of photomasks is reduced, thus reducing the production costs. Specifically, the interface layer2010may be composed of a nitride-oxide material, and a thickness of the interface layer2010preferably ranges from 0.1 micrometers to 0.5 micrometers (a thickness of the planarization layer ranges around from 2 micrometers to 3 micrometers). However, although the planarization layer has a greater thickness, it has an effect of reducing a parasitic capacitance between the source electrode209aand the drain electrode209band a common electrode2014. It can be understood that when the planarization layer is replaced by the interface layer2010, the parasitic capacitance will inevitably increase. In order to solve this issue, by forming a slit2015on the common electrode2014, the parasitic capacitance generated in the thin film transistor is disconnected, and the parasitic capacitance is maximally confined in an area of the thin film transistor. The slit2015is defined at a periphery of an area where a projection of the source electrode209aand the drain electrode209bin a vertical direction overlaps with the common electrode2014. Further, since the planarization layer with the greater thickness is replaced by the interface layer2010with the lesser thickness, the first via2013aand the second via2013bcan be formed by using only one photomask. Specifically, a photoresist pattern with a pattern of the first via2013aand a pattern of the second via2013bis formed on the passivation layer2012through one photomask, then a first etching process is performed in an etching stage until the first via2013ais etched to an upper surface of the interface layer2010and the second via2013bis etched to the pixel electrode2011. Accordingly, when performing the first etching process, etching gas with a high selectivity that easily etches a material of the passivation layer2012while does not easily etch materials of the interface layer2010and the pixel electrode2011must be selected. Next, a second etching process is performed in the etching stage. Since the second via2013bhas been formed, no further etching processes are required. But, the first via2013aneeds to be etched again to the drain electrode209b. When performing the second etching process, etching gas with a high selectivity that easily etches the material of the interface layer2012while does not easily etch the material of the pixel electrode2011and a material of the drain electrode209bmust to be selected, so that the second via2013bis not affected when the first via2013acontinues to be formed. It can be understood that regardless of the selectivity of the etching gas, the thin films will be etched, and it is just a difference in an etching rate. Therefore, in a case of adopting the interface layer2010with the lesser thickness, there is a little difference in depths of the first via2013aand the second via2013b. Compared with etching the planarization layer, etching the interface layer2010has more etching buffer, which allows more choices in choosing the etching gas. That is, the etching gas with high selectivity or even medium to high selectivity can be selected to achieve a technical effect of forming a deep via and a shallow via under the permission of the etching buffer in the present invention. Based on the above description, the drain electrode may be electrically connected to the pixel electrode2011through the first via2013aand the second via2013b. Compared with the prior art that two photomasks are required to perforate to make the drain electrode connect to the pixel electrode (such as the seventh photomask and the ninth photomask in the background), photomasks required for manufacturing the low temperature poly-silicon thin film transistor array substrate is maximally reduced in the present invention. In the present embodiment, the common electrode2014includes a drain electrode connection area2016(as a dotted box shown inFIG.2, the dotted box is merely for illustration, it does not represent a structure in the present invention) and a conductive area2017. The drain electrode connection area2016is an area where the pixel electrode2011is electrically connected to the drain electrode209bthrough the first via2013aand the second via2013b, and the conductive area2017can be used as an electrode cooperating with the pixel electrode2011to make liquid crystals twist, or an electrode cooperating with the pixel electrode2011to forms a storage capacitor in a liquid crystal display panel. It can be understood that uses of the conductive area2017are not limited in the present invention. Further, a slit2015is formed between the drain electrode connection area2016and the conductive area2017, and the slit2015is used to electrically disconnect the drain electrode connection area2016and the conductive area2017. Furthermore, the parasitic capacitance generated in the thin film transistor is disconnected, and the parasitic capacitance is maximally confined in the area of the thin film transistor (i.e. drain electrode connection area2016) without affecting the conductive area2017. In the present embodiment, the first via2013aand the second via2013bare filled with a material of the second transparent conductive layer2014in the drain electrode connection area2016. In another embodiment, the first via2013aand the second via2013bmay also be filled with a material different from the material of the second transparent conductive layer2014in the drain electrode connection area2016. In the present embodiment, the low temperature poly-silicon thin film transistor array substrate20further includes a touch electrode209c, which is formed simultaneously with the source electrode209aand the drain electrode209b, and is covered by the interface layer2010. The interface layer2010and the passivation layer2012are provided with a third via (unmarked) at a position corresponding to the touch electrode209c, and the touch electrode209cis electrically connected to the common electrode2014through the third via. Compared with the prior art, the touch electrode209ccan be integrated into the display panel during a process of preparing the thin film transistor array substrate without an additional photomask to form an in-cell touch display panel. Referring toFIG.3andFIGS.4A-4F,FIG.3is a flowchart of a method for manufacturing the array substrate according to an embodiment of the present invention, andFIGS.4A-4Fare schematic diagrams showing each step of the method for manufacturing the array substrate according to an embodiment of the present invention. The manufacturing method includes steps of: Step S10: providing a base substrate401, and forming a light shielding layer402, a buffer layer403, an active layer404, and a gate insulation layer405on the base substrate401in sequence, as shown inFIG.4A. In this step, when a blanket light shielding layer (unmarked) is formed on the base substrate401, photolithography and etching processes are performed through one photomask to form the light shielding layer402. In this step, when a blanket active layer (unmarked) is formed on the buffer layer403, photolithography and etching processes are performed through one photomask to form the active layer404. In addition, in order to improve carrier mobility, excimer-laser annealing is preferably used to transform the active layer404from amorphous silicon to polycrystalline silicon in the present invention. In another embodiment, the polycrystalline silicon can also be prepared by means of solid phase crystallization (SPC) or metal induced crystallization (MIC), and the like. It can be understood that the excimer laser annealing is used as a preferred embodiment to illustrate the present invention in the present invention, and it should not be used to limit the present invention. Step S20: forming a gate electrode406, and using the gate electrode406as a hard mask to form doped areas of a source and drain on the active layer404, as shown inFIG.4B. In this step, by means of gate re-etching technology, heavily-doped areas404aand lightly doped drain areas404bof the source and drain are realized in the present invention. Specifically, when a blanket gate electrode layer (unmarked) is formed on the gate insulation layer405, photolithography and etching processes are performed on the blanket gate electrode layer through a first photomask, and a gate pattern (unmarked) treated with the photolithography and etching processes is taken as a hard mask, then ions are heavily doped to both ends of the active layer404to form the heavily-doped areas404aof the source and drain. Afterwards, the gate pattern is re-etched to obtain the gate electrode406, and un-doped areas adjacent to the heavily-doped areas404aof the source and drain in a channel of the active layer404are exposed. Moreover, the gate electrode406is taken as a hard mask, and ions are lightly doped to the active layer404to form lightly doped drain areas404b, thereby the heavily-doped areas404aand lightly doped drain areas404bof the source and drain are realized. The gate re-etching technology is preferably used to reduce the number of photomasks used to prepare the heavily-doped areas404aand lightly doped drain areas404bof the source and drain and to reduce production costs in the present invention. Step S30: forming an inter insulation layer407on the gate insulation layer405, and perforating the gate insulation layer405and the inter insulation layer407to form source and drain vias408at positions corresponding to the source and drain, respectively, as shown inFIG.4C. In this step, a photoresist pattern with a pattern of the source and drain vias408is formed on the inter insulation layer407through one photomask, and the source and drain vias408are formed through photolithography and etching processes. Step S40: forming the source electrode409aand the drain electrode409bon the inter insulation layer407, and electrically connecting to the source and the drain through the source and drain vias408, respectively, as shown inFIG.4D. In this step, when a blanket source/drain metal layer (unmarked) is formed on the inter insulation layer407, the blanket source/drain metal layer is filled in the source and drain vias408, and the blanket source/drain metal layer is etched through one photomask to form the source electrode409aand the drain electrode409b. In this step, during etching processes performed on the blanket source/drain metal layer, the touch electrode409cmay be formed simultaneously with the source electrode409aand the drain electrode409band be disposed on the inter insulation layer407, and the touch electrodes are integrated in a display panel. Step S50: forming an interface layer (or interfacial layer, IL)4010, a first transparent conductive layer4011, and a passivation layer4012on the inter insulation layer407in sequence, perforating the interface layer4010and the passivation layer4012to form a first via4013a, and perforating the passivation layer4012to form a second via4013b, as shown inFIG.4E. In this step, when a blanket first transparent conductive layer (unmarked) is formed on the interface layer4010, photolithography and etching processes are performed on the blanket first transparent conductive layer through one photomask to form the first transparent conductive layer4011. In this step, a photoresist pattern of the first via4013aand a photoresist pattern of the second via4013bare formed on the passivation layer4012through a second photomask, and are treated with photolithography and etching processes to form the first via4013aand the second via4013b. Etching gas with high selectivity or even medium to high selectivity can be selected to achieve a technical effect of forming a deep via and a shallow via through one photomask under the permission of etching buffer in the present invention. It has been described in detail above and will not be repeated here. In this step, since the touch electrode409cis covered by the interface layer4010, when the first via4013aand the second via4013bare formed, a third via is formed in the interface layer4010at a position corresponding to the touch electrode409cthrough the second photomask at the same time. Step S60: forming a second transparent conductive layer4014on the passivation layer4012. In this step, when a blanket second transparent conductive layer (unmarked) is formed on the passivation layer4012, photolithography and etching processes are performed on the blanket second transparent conductive layer through a third photomask to form the first transparent conductive layer4014. Further, the second transparent conductive layer4014includes a drain electrode connection area4016(as a dotted box shown inFIG.4F, the dotted box is merely for illustration, it does not represent a structure of the present invention) and a conductive area4017, and a slit4015is formed between the drain electrode connection area4016and the conductive area4017to electrically disconnect the drain electrode connection area4016and the conductive area4017. Moreover, in order to solve a problem of an increased parasitic capacitance caused by replacing the planarization layer with the interface layer4010, the slit4015can be used to disconnect the parasitic capacitance generated in the thin film transistor, and the parasitic capacitance is maximally confined in an area of the thin film transistor (i.e. drain electrode connection area4016) without affecting the conductive area4017. In this step, the first via4013aand the second via4013bare filled with a material of the second transparent conductive layer4014in the drain electrode connection area4016. In another embodiment, the first via4013aand the second via4013bmay also be filled with a material different from the material of the second transparent conductive layer4014in the drain electrode connection area4016. In this step, the drain electrode connection area4016, the conductive area4017, and the slit4015are simultaneously formed through the third photomask. Other technical details of the method for manufacturing the low temperature poly-silicon thin film transistor array substrate provided by the present invention may refer to the above description about the low temperature poly-silicon thin film transistor array substrate, and will not be repeated here. In summary, the low temperature poly-silicon thin film transistor array substrate40provided by the present invention can be prepared by using only eight photomasks which are used in the formation of the light shielding layer402, the active layer404, the gate electrode406, the source and drain vias408, the source electrode409aand the drain electrode409b, the first transparent conductive layer4011, the first via4013aand the second via4013b, and the second transparent conductive layer4014, specifically. According to the present invention, by replacing the planarization layer in the prior art with the interface layer, performing one photomask-process to form the heavily-doped areas and the lightly doped drain areas of the source and drain with the gate re-etching process, as well as pairing with the structure of the array substrate described in the present invention and perforating the interface layer and the passivation layer to simultaneously form the deep via and the shallow via by using one photomask, the number of photomasks required to form the low temperature poly-silicon thin film transistor array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks. Further, the present invention further provides a technical solution for solving the parasitic capacitance caused by the replacement of the interface layer. It can be seen that the present invention has high practicability and utilization, and its advantages are very obvious compared with the prior art. Above all, although the present invention has been disclosed above in the preferred embodiments, the above preferred embodiments are not intended to limit the present invention. For persons skilled in this art, various modifications and alterations can be made without departing from the spirit and scope of the present invention. The protective scope of the present invention is subject to the scope as defined in the claims. | 25,688 |
11862643 | BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention is not construed as being limited to description of the embodiments below. Note that in the drawings of this specification, the identical portions or portions having a similar function are denoted by the identical reference numerals, and description thereon may be omitted. Embodiment 1 In this embodiment, an embodiment of a thin film transistor and a manufacturing method thereof will be described. FIG.1Eillustrates a cross-sectional view of a thin film transistor440having a bottom gate structure which is referred to as a channel-etched type. The thin film transistor440includes, over a substrate400having an insulating surface, a gate electrode layer421a, a gate insulating layer402, an oxide semiconductor layer including a channel formation region443, a source electrode layer445a, and a drain electrode layer445b. In addition, an insulating layer427and a protective insulating layer428are provided over the channel formation region443, an oxide conductive layer446a, an oxide conductive layer446b, the source electrode layer445a, and the drain electrode layer445b. A first region444cand a second region444dof the oxide semiconductor layer, which each overlap with an oxide insulating layer426, may be provided in an oxygen-excess state like the channel formation region443so as to have a function of reducing leak current and parasitic capacitance. Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps or the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the present invention. Here, the oxide conductive layers446aand446bare formed using a material with high conductivity, which includes a crystal region, and can reduce contact resistance between the oxide semiconductor layer and each of the source electrode layer445aand the drain electrode layer445b, so that a thin film transistor capable of high-speed operation can be realized. A process of manufacturing the thin film transistor440is described below with reference toFIGS.1A to1E. First, after a conductive film is formed over the substrate400having an insulating surface, the gate electrode layer421ais formed in a first photolithography step. Note that a resist mask used for the photolithography step may be formed with an ink-jet method. When the resist mask is formed with an ink-jet method, manufacturing costs can be reduced because a photomask is not used. As a material of the conductive film of the gate electrode layer421a, an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy including the above element, a stacked film in which any of the above-described elements are combined, and the like can be given. Alternatively, metal oxide or the like may be used. As the substrate400, a glass substrate of aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass can be used, for example. In the case where the temperature at which heat treatment is performed later is high, it is preferable to use a glass substrate whose strain point is greater than or equal to 730° C. Note that, instead of the glass substrate described above, a substrate formed using an insulator, such as a ceramic substrate, a quartz substrate, or a sapphire substrate, may be used as the substrate400. Although not illustrated, an insulating layer serving as a base film may be provided between the substrate400and the gate electrode layer421a. The base film has a function of preventing diffusion of an impurity element from the substrate400, and can be formed using a single-layer structure or a stacked structure of one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. Next, the gate insulating layer402is formed over the gate electrode layer421a. The gate insulating layer402can be formed using a light-transmitting insulating film such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer with a plasma CVD method, a sputtering method, or the like. The gate insulating layer402is not limited to the single layer of the insulating film described above, and a stacked layer of different films may also be used. For example, a silicon oxynitride film can be formed with a plasma CVD method using silane (SiH4), oxygen, and nitrogen as a film formation gas. The thickness of the gate insulating layer402is 100 nm to 500 nm inclusive. In the case of a stacked structure, for example, a first gate insulating layer having a thickness of 50 nm to 200 nm inclusive and a second gate insulating layer having a thickness of 5 nm to 300 nm are stacked in this order. In this embodiment, the gate insulating layer402is formed using a silicon oxynitride (SiON (composition ratio: N<O)) layer having a thickness of 100 nm formed with a plasma CVD method. Next, over the gate insulating layer402, an oxide semiconductor film is formed to a thickness of 5 nm to 200 nm inclusive, preferably, 10 nm to 20 nm inclusive (seeFIG.1A). The thickness is preferably as thin as 50 nm or less in order that the oxide semiconductor film keeps the amorphous state even when heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film. Reduction in thickness can prevent the oxide semiconductor film from being crystallized when heat treatment is performed after the formation of the oxide semiconductor layer. As the material of the oxide semiconductor film, a four-component metal oxide such as an In—Sn—Ga—Zn—O-based metal oxide, a three-component metal oxide such as an In—Ga—Zn—O-based metal oxide, an In—Sn—Zn—O-based metal oxide, an In—Al—Zn—O-based metal oxide, a Sn—Ga—Zn—O-based metal oxide, an Al—Ga—Zn—O-based metal oxide, and a Sn—Al—Zn—O-based metal oxide, or a two-component metal oxide such as an In—Zn—O-based metal oxide, a Sn—Zn—O-based metal oxide, an Al—Zn—O-based metal oxide, a Zn—Mg—O-based metal oxide, a Sn—Mg—O-based metal oxide, an In—Mg—O-based metal oxide, an In—O-based metal oxide, a Sn—O-based metal oxide, and a Zn—O-based metal oxide can be used. The above oxide semiconductor film may include SiO2. As the oxide semiconductor film, a thin film expressed by InMO3(ZnO)m(m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, Ga, Ga and Al, Ga and Mn, or Ga and Co can be given as M. An oxide semiconductor film whose composition formula is represented as InMO3(ZnO)m(m>0) where at least Ga is included as M is referred to as the In—Ga—Zn—O-based oxide semiconductor described above, and a thin film thereof is also referred to as an In—Ga—Zn—O-based film. In this embodiment, as the oxide semiconductor film, an In—Ga—Zn—O-based film having a thickness of 15 nm is formed with a sputtering method using a target for forming an In—Ga—Zn—O-based oxide semiconductor. Formation of the In—Ga—Zn—O-based film can be performed using an In—Ga—Zn—O-based oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1:1 [in a molar ratio] (that is, In:Ga:Zn=1:1:0.5 [in an atomic ratio])) under the following conditions: the distance between a substrate and a target is 100 mm; the pressure is 0.6 Pa; the direct-current (DC) power supply is 0.5 kW; and the atmosphere is oxygen (the flow rate of oxygen is 100%). Alternatively, a target having a composition ratio of In:Ga:Zn=1:1:1 [in an atomic ratio] or In:Ga:Zn=1:1:2 [in an atomic ratio] may be used. In addition, the filling factors of these targets are 90% to 100% inclusive, preferably, 95% to 99.9% inclusive. An oxide semiconductor film which is formed becomes dense with the use of a metal oxide target having a high filling factor. Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used for a sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating layer is formed, and a DC sputtering method is mainly used in the case where a metal film is formed. In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber. Furthermore, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during film formation to form a thin compound film thereof, a bias sputtering method in which voltage is also applied to a substrate during film formation, and the like. Note that before the oxide semiconductor film is formed with a sputtering method, dust on a surface of the gate insulating layer402is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which, without application of voltage to a target side, a surface of a substrate is modified in such a manner that an RF power source for voltage application is used to a substrate side under an argon atmosphere and ionized argon is collided with the substrate. Note that nitrogen, helium, oxygen, or the like may be used instead of argon. Before the oxide semiconductor film is formed, heat treatment (at higher than or equal to 400° C. and lower than the strain point of the substrate) may be performed under an atmosphere of an inert gas (e.g., nitrogen, helium, neon, or argon) so that impurities such as hydrogen and water, which are included in the gate insulating layer402, are removed. Then, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer in a second photolithography step (seeFIG.1B). Further, a resist mask for forming the island-shaped oxide semiconductor layer404may be formed with an ink-jet method. When the resist mask is formed with an ink-jet method, manufacturing costs can be reduced. Next, the oxide semiconductor layer404is dehydrated or dehydrogenated. First heat treatment for dehydration or dehydrogenation is performed at a temperature which is higher than or equal to 400° C., preferably, higher than 425° C., and lower than the strain point of a substrate under an atmosphere of an inert gas such as nitrogen or a rare gas (e.g., helium, neon, or argon), using an electric furnace or the like. Note that in the case of the temperature which is higher than 425° C., the heat treatment time may be 1 hour or shorter, whereas in the case of the temperature which is lower than 425° C., the heat treatment time is longer than 1 hour. As another heating method, rapid thermal anneal (RTA) treatment which is performed at 650° C. for approximately 3 minutes using a high-temperature inert gas or light may be performed. Since dehydration or dehydrogenation can be performed in a short time with the RTA method, the first heat treatment can be performed even at a temperature over the strain point of a glass substrate. Note that in this specification, heat treatment under an atmosphere of an inert gas such as nitrogen, a rare gas, or the like is referred to as heat treatment for dehydration or dehydrogenation. In this specification, “dehydrogenation” does not indicate only elimination of H2. For convenience, elimination of H, OH, and the like is referred to as “dehydration or dehydrogenation”. In addition, it is important not to remix water or hydrogen into the oxide semiconductor layer which is dehydrated or dehydrogenated without exposure to the air. In a transistor using an oxide semiconductor layer which is obtained in such a manner that an i-type oxide semiconductor layer is changed into an n-type (e.g., if-type or n+-type) oxide semiconductor layer, i.e. a low-resistant oxide semiconductor layer, by dehydration or dehydrogenation and then the n-type oxide semiconductor layer is changed into an i-type oxide semiconductor layer again so as to have high resistance, the threshold voltage of the transistor can be positive voltage, so that the transistor shows so-called normally-off characteristics. It is preferable that a transistor used for a display device be formed with a positive threshold voltage which is as close to 0 V as possible. In an active matrix display device, the electric characteristics of a transistor included in a circuit are important and influence the performance of the display device. The threshold voltage of the transistor is particularly important. Note that if the threshold voltage of the transistor is negative, the transistor shows so-called normally-on characteristics; in other words, current flows between a source electrode and a drain electrode even when the gate voltage is 0 V. Accordingly, it is difficult to control the circuit including the transistor. Even when the transistor has positive threshold voltage, the transistor cannot perform a switching operation itself because the driving voltage is insufficient in the case where the absolute value of the threshold voltage is large. In the case of an n-channel transistor, it is preferable that a channel be formed and drain current begins to flow after the positive voltage is applied as a gate voltage. A transistor in which a channel is not formed unless the driving voltage is high and a transistor in which a channel is formed and then a drain current flows even when a negative voltage is applied are not suitable as the transistor used for a circuit. An atmosphere under which the temperature at which dehydration or dehydrogenation is performed is decreased may be switched to an atmosphere different from that under which the temperature is increased or heat treatment is performed. For example, cooling is performed by using the same furnace in which dehydration or dehydrogenation is performed and by filling the furnace with a high-purity oxygen gas, a high-purity N2O gas, or ultra-dry air (having a dew point of lower than −40° C., preferably, lower than −60° C.) without exposure to the air. Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus have purity of 6N (99.9999%) or more, preferably, 7N (99.99999%) or more. In the case where heat treatment is performed under an atmosphere of an inert gas, an initially i-type oxide semiconductor layer is changed into an oxygen-deficient oxide semiconductor layer by the heat treatment to be an n-type (e.g., n−-type) oxide semiconductor layer, i.e. a low-resistant oxide semiconductor layer. Then, the oxide semiconductor layer is placed in an oxygen-excess state by formation of an oxide insulating layer which is in contact with the oxide semiconductor layer so as to be a high-resistance oxide semiconductor layer, i.e. an i-type oxide semiconductor layer. Accordingly, it is possible to manufacture a thin film transistor having favorable electric characteristics and high reliability. In the oxide semiconductor layer which is sufficiently dehydrated or dehydrogenated under the above conditions, at least a peak at around 250° C. to 300° C. of two peaks in spectra which show discharge of moisture is not detected with thermal desorption spectroscopy (TDS) even when the temperature of the dehydrated or dehydrogenated oxide semiconductor layer is increased to 450° C. FIG.11shows results of analyzing discharge of moisture with thermal desorption spectroscopy (TDS) in a plurality of samples each of which is subjected to heat treatment under a nitrogen atmosphere at a certain temperature. The thermal desorption spectroscopy is a method for detecting and identifying, using a quadrupole mass spectrometer, a gas component which is discharged or generated from a sample when the sample is heated and the temperature thereof is increased in high vacuum; thus, a gas and a molecule discharged from surfaces and insides of the samples can be observed. With the use of a thermal desorption spectroscopy apparatus manufactured by ESCO Ltd. (product name: 1024 amu QMS), measurement was performed under the following conditions: the rising temperature was at approximately 10° C./min; the pressure was 1×10−8(Pa) at the beginning of the measurement; and the pressure was at a degree of vacuum of approximately 1×10−7(Pa) during the measurement. FIG.11shows a graph that compares TDS measurement results in terms of moisture by manufacturing the following samples in each of which an In—Ga—Zn—O-based film having a film thickness of 50 nm is formed over the glass substrate: a sample which is not heated (as-deposited) and a sample processed at 250° C. for 1 hour, a sample processed at 350° C. for 1 hour, a sample processed at 350° C. for 10 hours, and a sample processed at 450° C. for 1 hour; and a sample of the glass substrate alone (not heated). The results inFIG.11indicate that the higher the heating temperature under a nitrogen atmosphere is, the more moisture which is discharged from the In—Ga—Zn—O-based film is reduced, and that, in the sample heated at 450° C., no peak at 200° C. to 350° C. is observed in a spectrum which shows discharge of moisture. Observed are two peaks of spectra which show discharge of moisture at a high temperature of 200° C. or more from the In—Ga—Zn—O-based film: a first peak which appears at a temperature between 200° C. and 250° C.; and a second peak which appears at a temperature between 250° C. and 350° C. The first peak which appears at a temperature between 200° C. and 250° C. is not clear in the samples other than the sample heated at 250° C. In the as-deposited sample, this is because two peaks overlap with each other and thus there is apparently a spectrum having one peak. Further, in the samples which are subjected to heat treatment at 350° C., this is because moisture is somewhat discharged and thus the first peak is substantially disappeared. These can also be confirmed from a symmetric property of a peak position of each spectrum and the fact that the peak position of each spectrum is shifted to a higher temperature side. In addition, the vertical axis of the graph ofFIG.11represents an arbitrary unit, where existence of discharged gas is relatively seen. These shapes of the spectra each show similar change with respect to heat treatment regardless of the area or volume of an object to be measured. Accordingly, the spectra can be effectively used as observation of a process monitor or a means for failure analysis. In other words, existence of a peak in a temperature range of 200° C. to 350° C. is examined, whereby it is possible to confirm a record that indicates whether an appropriate process has been conducted or not. Note that even in the case where the sample which is subjected to heat treatment at 450° C. under a nitrogen atmosphere is left at room temperature under an air atmosphere approximately for one week, discharge of moisture at 200° C. or more was not observed. Thus, it is found that by performing the heat treatment, the In—Ga—Zn—O-based film becomes stable. Further, TDS measurement was performed using samples which have been subjected to a heating step under the same conditions as those of the samples in each of which discharge of moisture has been measured in order to measure H, O, OH, H2, O2, N, N2, and Ar in addition to H2O. It was possible that spectra which show discharge of H, O, and OH from some of the samples be clearly observed.FIG.12shows TDS spectra of H.FIG.13shows TDS spectra of O.FIG.14shows TDS spectra of OH. The measurement result of a glass substrate alone (not heated) is added to TDS spectra of moisture, H, O, and OH for comparison. Note that the oxygen concentration under a nitrogen atmosphere in the above heat conditions is 20 ppm or less. The spectra which show discharge of H, O, and OH tend to be similar to the spectra which show discharge of moisture and indicate that, in the sample heated at 450° C., no peak is observed which shows each discharge component that appears around 250° C. to 300° C. The above results indicate that, by performance of the heat treatment of the In—Ga—Zn—O-based film, moisture, H, O, and OH are discharged. Since discharge of H, O, and OH tends to be performed in a state similar to that of moisture, it can be said that most of the discharge of H, O, and OH is derived from a water molecule. Here, in this embodiment, the substrate is introduced into an electric furnace, which is one of heat treatment apparatuses, and the heat treatment of the oxide semiconductor layer is performed under a nitrogen atmosphere. Then, the oxide semiconductor layer is not exposed to air, which prevents the oxide semiconductor layer from remixing water or hydrogen, so that an oxide semiconductor layer is obtained. In addition, slow cooling is performed in a nitrogen atmosphere in one furnace from the heating temperature T at which the oxide semiconductor layers are dehydrated or dehydrogenated to a temperature low enough to prevent water from coming in, specifically to a temperature more than 100° C. lower than the heating temperature T. Without limitation to a nitrogen atmosphere, dehydration or dehydrogenation is performed in a rare gas atmosphere such as helium, neon, or argon. The oxide semiconductor layer is partly crystallized in some cases, depending on a condition of the first heat treatment or a material of the oxide semiconductor layer. After the first heat treatment, the oxide semiconductor layer404which is changed into an oxygen-deficient oxide semiconductor layer to be a low-resistant oxide semiconductor layer is obtained (seeFIG.1B). The carrier concentration of the oxide semiconductor layer is higher after the first heat treatment than that of the oxide semiconductor film just after the film formation, accordingly; it is preferable that the oxide semiconductor layer404have a carrier concentration of 1×1018/cm3or more. Note that the oxide semiconductor layer is preferably amorphous but may be partly crystallized. Note that in this specification, even in the state where the oxide semiconductor layer is partly crystallized, it is referred to as an “amorphous” state. Further, the gate electrode layer421ais crystallized to be a microcrystalline film or a polycrystalline film in some cases, depending on a condition of the first heat treatment or a material of the gate electrode layer421a. For example, in the case where a film of an indium oxide-tin oxide alloy is used as the gate electrode layer421a, the film is crystallized by the first heat treatment at 450° C. for 1 hour. Alternatively, the first heat treatment may be performed on the oxide semiconductor film before it is processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heat treatment apparatus, and then the second photolithography step is performed. Next, an oxide insulating film is formed over the gate insulating layer402and the oxide semiconductor layer404with a sputtering method. Then, a resist mask is formed in a third photolithography step, and the oxide insulating layers426are formed by selective etching. After that, a step of removing the resist mask may be performed. At this phase, the regions are formed that overlap with the oxide insulating layers426which cover the peripheral portion and side surface of the oxide semiconductor layer (the first region444cand the second region444dof the oxide semiconductor layer), whereby leakage current and parasitic capacitance can be reduced (seeFIG.1E). The oxide insulating layer426can be formed with a thickness of at least 1 nm with a method with which impurities such as water or hydrogen are not mixed into the above oxide insulating layer, as appropriate. In this embodiment, the oxide insulating layer426is formed using a silicon oxide film which is formed with a sputtering method. The substrate temperature at the time of film formation may be from room temperature to 300° C. inclusive and, in this embodiment, is 100° C. The silicon oxide film can be formed with a sputtering method under an atmosphere of a rare gas (typically, argon), an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically, argon) and oxygen. Moreover, a silicon oxide target or a silicon target can be used as a target. For example, with the use of a silicon target, a silicon oxide film can be formed with a sputtering method under an atmosphere of oxygen and a rare gas. The oxide insulating layer which is formed in contact with the oxide semiconductor layer whose resistance is reduced is formed using an inorganic insulating film that does not contain impurities such as moisture, a hydrogen ion, OH— and blocks entry of such impurities from the outside. Typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used. In this embodiment, the film formation is performed with a pulsed DC sputtering method using a columnar polycrystalline silicon target to which boron is added (the resistivity is 0.01 Ωcm and the purity is 6N), in which the distance between substrate and target (T-S distance) is 89 mm, the pressure is 0.4 Pa, the direct-current (DC) power is 6 kW, and the atmosphere is oxygen (the oxygen flow rate is 100%). The film thickness thereof is 300 nm. Next, an oxide conductive film and a metal film are stacked over the gate insulating layer402, the oxide insulating layers426, and the oxide semiconductor layer404. With a sputtering method, film formation of the stacked layer of the oxide conductive film and the metal film can be performed continuously without exposure to air. As the material of the oxide conductive film, for example, any of the following conductive metal oxide materials can be employed: an In—Sn—O-based metal oxide; an In—Sn—Zn—O-based metal oxide; an In—Al—Zn—O-based metal oxide; a Sn—Ga—Zn—O-based metal oxide; an Al—Ga—Zn—O-based metal oxide; a Sn—Al—Zn—O-based metal oxide; an In—Zn—O-based metal oxide; a Sn—Zn—O-based metal oxide; an Al—Zn—O-based metal oxide; an In—O-based metal oxide; a Sn—O-based metal oxide; or a Zn—O-based metal oxide. The thickness of the oxide conductive film is selected as appropriate in the range of 50 nm to 300 nm inclusive. In this embodiment, a zinc oxide film is used. As a material of the metal film, an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta, an alloy containing any of these elements as a component, or the like is used. The above metal film is not limited to a single layer and a stacked layer of different films can be used. In this embodiment, a three-layer-stacked film in which a molybdenum film, an aluminum film, and a molybdenum film are stacked is used. Next, a resist mask is formed in a fourth photolithography step, and the metal film is selectively etched to form the source electrode layer445aand the drain electrode layer445b. After that, the resist mask is removed. Note that an alkaline solution is used as a resist stripper to remove the resist mask. In the case where the resist stripper is used, the zinc oxide film is also selectively etched using the source electrode layer445aand the drain electrode layer445bas masks. In this manner, the oxide conductive layer446ais formed under and in contact with the source electrode layer445a, and the oxide conductive layer446bis formed under and in contact with the drain electrode layer445b(seeFIG.1D). By providing the oxide conductive layer446abetween the source electrode layer445aand the oxide semiconductor layer, contact resistance can be reduced, which leads to resistance reduction, so that a thin film transistor capable of high-speed operation can be realized. The oxide conductive layer446aprovided between the source electrode layer445aand the oxide semiconductor layer functions as a source region, and the oxide conductive layer446bprovided between the drain electrode layer445band the oxide semiconductor layer functions as a drain region, which are effective in improvement the frequency characteristics in the case where, for example, a peripheral circuit (driver circuit) is formed over one substrate. In the case where a molybdenum film and the oxide semiconductor layer are directly in contact with each other, the contact resistance is increased. This is because molybdenum is less likely to be oxidized as compared to titanium and thus extracts a small amount of oxygen from the oxide semiconductor layer, which does not allow the interface between the molybdenum and the oxide semiconductor layer to be n-type oxide semiconductor. However, even in that case, by providing the oxide conductive layer between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer, the contact resistance can be reduced. The etching rate is different between the oxide semiconductor layer and the oxide conductive layer, and therefore, the oxide conductive layer which is on and in contact with the oxide semiconductor layer can be removed by controlling the time of period. After the metal film is selectively etched, the resist masks may be removed by an oxygen ashing treatment to leave the zinc oxide film, and then, the zinc oxide film may be selectively etched with the source electrode layer445aand the drain electrode layer445bas masks. The resist mask for forming the source electrode layer425aand the drain electrode layer425bmay be formed with an ink-jet method. Next, the insulating layer427is formed over the oxide insulating layers426, the source electrode layer445a, the drain electrode layer445band oxide semiconductor layer404. As the insulating layer427, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, a silicon oxide film is formed as the insulating layer427with an RF sputtering method. At this phase, second heat treatment is performed under an atmosphere of an inert gas such as nitrogen at a temperature of greater than or equal to 200° C. and less than or equal to 400° C., preferably, greater than or equal to 250° C. and less than or equal to 350° C. For example, heat treatment is performed under a nitrogen atmosphere at 250° C. for 1 hour. In the second heat treatment, part of the insulating layer427which is an oxide and the oxide semiconductor layer404are heated while being in contact with each other. Therefore, in the oxide semiconductor layer404the resistance of which has been reduced through the first heat treatment, oxygen is supplied from the insulating layer427to make the oxide semiconductor layer404into an oxygen-excess state, whereby the oxide semiconductor layer404has high resistance (i-type conductivity). Although the second heat treatment is performed after the formation of the silicon oxide film in this embodiment, the second heat treatment can be performed anytime after the formation of the silicon oxide film and the timing of the second heat treatment is not limited to just after the formation of the silicon oxide film. In addition, in the case where the source electrode layer445aand the drain electrode layer445bare formed using a heat-resistant material, a step in which the conditions of the first heat treatment are used can be performed at the timing of the second heat treatment. In this case, the heat treatment can be performed only once after the formation of the silicon oxide film. In the second heat treatment, the oxide conductive layers446aand446bare crystallized to each have a crystal region as long as a crystallization inhibitor such as silicon oxide is not contained in the oxide conductive layers446aand446b. For example, the oxide conductive layers tend to be crystallized into columnar-like crystals when zinc oxide or the like is used, and tend to be crystallized in a microcrystalline state when an indium oxide-tin oxide alloy is used. Consequently, realized is reduction of contact resistance between the oxide semiconductor layer and each of the source electrode layer445aand the drain electrode layer445bas well as improvement in conductivity. On the other hand, the In—Ga—Zn—O-based oxide semiconductor layer which is used in this embodiment is not crystallized even through the second heat treatment and thus an amorphous state thereof is maintained. Next, the protective insulating layer428is formed over the insulating layer427(seeFIG.1E). As the protective insulating layer428, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or the like can be used. In this embodiment, a silicon nitride film is formed as the protective insulating layer428with an RF sputtering method. Through the steps described above, the thin film transistor440can be manufactured in which the oxide conductive layer having a crystal region is formed between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer. Note that this embodiment can be freely combined with any of the other embodiments. Embodiment 2 In this embodiment will be described an example of a bottom contact thin film transistor and a manufacturing process thereof, which is different from that of Embodiment 1, with reference toFIGS.2A to2E.FIGS.2A to2Eare the same asFIGS.1A to1Eexcept that there is a difference in part of the process. Therefore, the same portions are denoted by the same reference numerals, and detailed description of the same portions is omitted. A thin film transistor470illustrated inFIG.2Eis a bottom gate structure which is referred to as a bottom contact type. The thin film transistor470includes, over the substrate400having an insulating surface, the gate electrode layer421a, the gate insulating layer402, the source electrode layer445a, the drain electrode layer445b, the oxide conductive layer446a, the oxide conductive layer446b, and the oxide semiconductor layer including the channel formation region443. In addition, the insulating layer427and the protective insulating layer428are provided over the channel formation region443, the source electrode layer445a, and the drain electrode layer445b. Here, the oxide conductive layers446aand446bare formed using a material with high conductivity, which includes a crystal region, and can reduce contact resistance between the oxide semiconductor layer and each of the source electrode layer445aand the drain electrode layer445b, so that a thin film transistor capable of high-speed operation can be realized. A process of manufacturing the thin film transistor470is described below with reference toFIGS.2A to2E. The gate electrode layer421aand the gate insulating layer402are formed in accordance with Embodiment 1. Next, a metal film and an oxide conductive film are stacked over the gate insulating layer402(seeFIG.2A). At this time, with a sputtering method, film formation of the stacked layer of the metal film and the oxide conductive film can be performed continuously without exposure to air. In this embodiment, a three-layer-stacked film in which a molybdenum film, an aluminum film, and a molybdenum film are stacked is used for the metal film, and a zinc oxide film is used for the oxide conductive film. Next, a resist mask is formed in a photolithography step, and the metal film and the zinc oxide film are selectively etched to form the source electrode layer445a, the drain electrode layer445b, the oxide conductive layer446a, and the oxide conductive layer446b(seeFIG.2B). Here, an alkaline solution is used as a resist stripper to remove the resist mask. Since the zinc oxide film is also etched in some cases, it is preferable to remove the resist mask by oxygen ashing in order to prevent the zinc oxide film from being reduced in thickness. Next, an oxide semiconductor film is formed in a manner similar to that of Embodiment 1, and the oxide semiconductor layer404is formed through a photolithography step and an etching step (seeFIG.2C). Here, the oxide semiconductor layer is dehydrated or dehydrogenated in accordance with the method of the first heat treatment described in Embodiment 1. Note that before the oxide semiconductor film is formed, heat treatment (at higher than or equal to 400° C. and lower than the strain point of the substrate) may be performed under an atmosphere of an inert gas (e.g., nitrogen, helium, neon, or argon) so that impurities such as hydrogen and water, which are included in the gate insulating layer402, are removed. Next, the insulating layer427is formed over the source electrode layer445a, the drain electrode layer445b, and the oxide semiconductor layer404. As the insulating layer427, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, a silicon oxide film is formed as the insulating layer427with an RF sputtering method. Here, heat treatment is performed in accordance with the method of the second heat treatment described in Embodiment 1. Although the second heat treatment is performed after the formation of the silicon oxide film in this embodiment, the second heat treatment can be performed anytime after the formation of the silicon oxide film and the timing of the second heat treatment is not limited to just after the formation of the silicon oxide film. In addition, in the case where the source electrode layer445aand the drain electrode layer445bare formed using a heat-resistant material, a step in which the conditions of the first heat treatment are used can be performed at the timing of the second heat treatment. Through any one of the heat treatment processes up to here, the oxide conductive layers446aand446bare crystallized to each have a crystal region as long as a crystallization inhibitor such as silicon oxide is not contained in the oxide conductive layers446aand446b. Needless to say, the heat treatment process may be performed plural times. On the other hand, the oxide semiconductor layer is not crystallized even through the heat treatment which is performed plural times and thus an amorphous state thereof is maintained. Next, the protective insulating layer428is formed over the insulating layer427(seeFIG.2E). Through the steps described above, the thin film transistor470can be manufactured in which the oxide conductive layer having a crystal region is formed between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer. Note that this embodiment can be freely combined with any of the other embodiments. Embodiment 3 In this embodiment will be described an example of a bottom contact thin film transistor and a manufacturing process thereof, which is different from those of Embodiments 1 and 2, with reference toFIGS.3A to3E.FIGS.3A to3Eare the same asFIGS.1A to1Eexcept that there is a difference in part of the process. Therefore, the same portions are denoted by the same reference numerals, and detailed description of the same portions is omitted. FIG.3Eillustrates a cross-sectional view of a thin film transistor480having a bottom gate structure which is referred to as a channel-protected type. The thin film transistor480includes, over the substrate400having an insulating surface, the gate electrode layer421a, the gate insulating layer402, an oxide semiconductor layer, the oxide conductive layer446a, the source electrode layer445a, and the drain electrode layer445b. Here, the oxide semiconductor layer includes the channel formation region443, a high-resistance source region424a, and a high-resistance drain region424b. In addition, an oxide insulating layer426awhich functions as a channel protective layer is provided in contact with channel formation region443. Further, the protective insulating layer428is provided over the source electrode layer445a, the drain electrode layer445b, the channel protective layer426a, and the oxide semiconductor layer404. A first region424cand a second region424dof the oxide semiconductor layer, which each overlap with an oxide insulating layer426b, are provided in an oxygen-excess state like the channel formation region443, and may have a function of reducing leak current and parasitic capacitance. A third region424eof the oxide semiconductor layer, which is in contact with the protective insulating layer428, is provided between the channel formation region443and the high-resistance source region424a. A fourth region424fof the oxide semiconductor layer, which is in contact with the protective insulating layer428, is provided between the channel formation region443and the high-resistance drain region424b. The oxide conductive layers446aand446bare formed using a material with high conductivity, which includes a crystal region, and can reduce contact resistance between the oxide semiconductor layer and each of the source electrode layer445aand the drain electrode layer445b, so that a thin film transistor capable of high-speed operation can be realized. The third region424eand the fourth region424fof the oxide semiconductor layer are a high-resistance source region (also referred to as an HRS region) which is an oxygen-deficient region and a high-resistance drain region (also referred to as an HRD region) which is an oxygen-deficient region, respectively. Specifically, the carrier concentration of the high-resistance drain region is greater than or equal to 1×1018/cm3and is at least higher than the carrier concentration of the channel formation region (less than 1×1018/cm3). Note that the carrier concentration in this embodiment is obtained by Hall effect measurement at room temperature. When the widths of the third region and fourth region in the channel length direction are large, an off-current of the thin film transistor can be reduced. In contrast, when the widths of the third region and fourth region in the channel length direction are small, the operation speed of the thin film transistor can be increased. In a channel-protected thin film transistor, although the width of an oxide insulating layer which functions as a channel protective layer is reduced so that a substantial channel length L is easily shortened, a short circuit might be caused when a source electrode layer and a drain electrode layer are provided over the oxide insulating layer. Therefore, the source electrode layer445aand the drain electrode layer445bare provided so that end portions thereof are apart from the oxide insulating layer. InFIG.3E, a region of the oxide semiconductor layer under the oxide insulating layer426awhich functions as a channel protective layer is referred to as a channel formation region. Therefore, the channel length L of the thin film transistor480is equal to the width of the oxide insulating layer426ain the channel length direction, and, in the cross-sectional view ofFIG.3E, corresponds to a length of the base of the trapezoidal oxide insulating layer426a. A process of manufacturing the thin film transistor480is described below with reference toFIGS.3A to3E. The gate electrode layer421aand the gate insulating layer402are formed in accordance with Embodiment 1 (seeFIG.3A). Next, an oxide semiconductor film is formed in a manner similar to that of Embodiment 1, and the island-shaped oxide semiconductor layer404is formed through a photolithography step and an etching step (seeFIG.3B). Note that before the oxide semiconductor film is formed, heat treatment (at higher than or equal to 400° C. and lower than the strain point of the substrate) may be performed under an atmosphere of an inert gas (e.g., nitrogen, helium, neon, or argon) so that impurities such as hydrogen and water, which are included in the gate insulating layer402, are removed. Here, the oxide semiconductor layer is dehydrated or dehydrogenated in accordance with the method of the first heat treatment described in Embodiment 1. Alternatively, the first heat treatment may be performed on the oxide semiconductor film before it is processed into the island-shaped oxide semiconductor layer. Next, an oxide insulating film is formed over the gate insulating layer402and the oxide semiconductor layer404with a sputtering method in a manner similar to that of Embodiment 1. Then, resist mask is formed in a photolithography step, and the oxide insulating layers426aand426bare formed by selective etching. After that, the resist mask may be removed. Here, a region of the oxide semiconductor layer under the oxide insulating layer426aserves as a channel formation region (seeFIG.3C). Next, an oxide conductive film and a metal film are stacked over the oxide insulating layer426a, the oxide insulating layers426b, and the oxide semiconductor layer and are partly etched to form the source electrode layer445a, the drain electrode layer445b, the oxide conductive layer446a, and the oxide conductive layer446b. With a sputtering method, film formation of the stacked layer of the oxide conductive film and the metal film can be performed continuously without exposure to air. In this embodiment, a three-layer-stacked film in which a molybdenum film, an aluminum film, and a molybdenum film are stacked is used for the metal film, and a zinc oxide film is used for the oxide conductive film (seeFIG.3D). Next, second heat treatment is performed under an atmosphere of an inert gas such as nitrogen at a temperature of greater than or equal to 200° C. and less than or equal to 400° C., preferably, greater than or equal to 250° C. and less than or equal to 350° C. For example, heat treatment is performed under a nitrogen atmosphere at 250° C. for 1 hour. In the second heat treatment, part of the oxide semiconductor layer404is heated while being in contact with the oxide insulating layers426aand426b. Therefore, in the oxide semiconductor layer404the resistance of which has been reduced through the first heat treatment, oxygen is supplied from the oxide insulating layers426aand426bto make the oxide semiconductor layer404into an oxygen-excess state, whereby the oxide semiconductor layer404has high resistance (i-type conductivity). On the other hand, since part of the oxide semiconductor layer404, which does not overlap with the oxide insulating layers426aand426b, is heated while being exposed, the third region424eand fourth region424fthe resistance of which is maintained or further reduced can be formed. Note that although the second heat treatment is performed after the formation of the oxide insulating layers426aand426bin this embodiment, the second heat treatment can be performed anytime after the formation of the oxide insulating layers426aand426band the timing of the second heat treatment is not limited to just after the formation of the oxide insulating layers426aand426b. Through the second heat treatment, the oxide conductive layers446aand446bare crystallized to each have a crystal region as long as a crystallization inhibitor such as silicon oxide is not contained in the oxide conductive layers446aand446b. On the other hand, the oxide semiconductor layer is not crystallized even through the second heat treatment and thus an amorphous state thereof is maintained. Next, the protective insulating layer428is formed over the oxide semiconductor layer404, the oxide insulating layer426a, the oxide insulating layers426b, the source electrode layer445a, and the drain electrode layer445b(seeFIG.3E). As the insulating layer428, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or the like is used. In this embodiment, a silicon nitride film is formed as the protective insulating layer428with an RF sputtering method. Through the steps described above, the thin film transistor480can be manufactured in which the oxide conductive layer having a crystal region is formed between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer. Note that this embodiment can be freely combined with any of the other embodiments. Embodiment 4 In this embodiment will be described an example in which an active matrix liquid crystal display device or light-emitting device is manufactured over one substrate using the thin film transistor described in any of Embodiments 1, 2, and 3. FIG.4illustrates an example of a cross-sectional structure of a liquid crystal display device using an active matrix substrate. While in Embodiments 1, 2, and 3, modes of a thin film transistor are illustrated in the cross-sectional views, in this embodiment, a structure in which a driver circuit portion and a pixel portion are included over one substrate is described with a view illustrating the following: a thin film transistor450for the driver circuit portion; a thin film transistor460for the pixel portion; a gate wiring contact portion; a storage capacitor; a gate wiring, a source wiring, and an intersection thereof; a pixel electrode; and the like. The storage capacitor, the gate wiring, and the source wiring can be formed in the same manufacturing steps as the thin film transistors shown in Embodiments 1 and 2 and can be manufactured without an increase in the number of photomasks and an increase in the number of steps. InFIG.4, the thin film transistor450is a thin film transistor provided in the driver circuit portion and the thin film transistor460electrically connected to a pixel electrode layer457ais a thin film transistor provided in the pixel portion. In this embodiment, the thin film transistor460formed over the substrate400has the same structure as the thin film transistors in Embodiments 1, 2, and 3. Here, a channel-etched thin film transistor is shown as an example. A capacitor wiring layer430which is formed using the same material in the same step as a gate electrode layer of the thin film transistor460overlaps with a capacitor electrode layer431, with a gate insulating layer402serving as a dielectric interposed therebetween; thus, a storage capacitor is formed. Note that the capacitor electrode layer431is formed using the same material in the same step as an electrode layer and an oxide conductive layer which are provided in a source region or a drain region of the thin film transistor460. Note that the storage capacitor is provided below the pixel electrode layer457a. Although not illustrated, the capacitor electrode layer431is electrically connected to the pixel electrode layer457a. This embodiment shows the example in which the storage capacitor is formed using the capacitor electrode layer431and the capacitor wiring layer430; however, there is no particular limitation on the structure of the storage capacitor. For example, the storage capacitor may be formed in such a manner that, without provision of a capacitor wiring layer, a pixel electrode layer overlaps with a gate wiring in an adjacent pixel with a planarization insulating layer, a protective insulating layer, and a gate insulating layer interposed therebetween. A plurality of gate wirings, source wirings, and capacitor wiring layers are provided in accordance with the pixel density. In a terminal portion, a plurality of first terminal electrodes at the same potential as the gate wiring, a plurality of second terminal electrodes at the same potential as the source wiring, a plurality of third terminal electrodes at the same potential as the capacitor wiring layer, and the like are arranged. The number of each of the terminals to be provided may be any number, and the number of each terminal may be determined as appropriate. In the gate wiring contact portion, a gate electrode layer421bcan be formed using a low resistance metal material. The gate electrode layer421bis electrically connected to the gate wiring through a contact hole that reaches the gate wiring. The heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer may be performed: after the oxide semiconductor layer is formed; after an oxide conductive layer is stacked over the oxide semiconductor layer; or after a passivation film is formed over a source electrode and a drain electrode. A gate electrode layer of the thin film transistor450in the driver circuit portion may be electrically connected to a conductive layer417provided above the oxide semiconductor layer. Further, in the wiring intersection, in order to reduce the parasitic capacitance as illustrated inFIG.4, the gate insulating layer402and the oxide insulating layer426are sacked between a gate wiring layer421cand a source wiring layer422. When an active matrix liquid crystal display device is manufactured, an active matrix substrate and a counter substrate provided with a counter electrode are fixed with a liquid crystal layer interposed therebetween. Similarly, with a plurality of microcapsules each including first particles having a positive charge and second particles having a negative charge disposed between two electrodes, an active matrix electrophoretic display device can be manufactured. A common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrode electrically connected to the common electrode is provided in the terminal portion. The fourth terminal electrode is used for setting the common electrode to a fixed potential such as GND or 0 V. The fourth terminal electrode can be formed using the same material as the pixel electrode layer457a. When the same material is used for the gate electrode, the source electrode, the drain electrode, the pixel electrode, another electrode layer, and another wiring layer, a common sputtering target and a common manufacturing apparatus can be used, and thus the material costs and costs of an etchant (or an etching gas) used for etching can be reduced. As a result, manufacturing costs can be reduced. When a photosensitive resin material is used for a planarization insulating layer456in the structure ofFIG.4, the step for forming a resist mask can be omitted. In addition,FIG.5illustrates a cross-sectional view in a state of a substrate of an active matrix light-emitting device before an EL layer is formed over a first electrode (a pixel electrode). InFIG.5, a channel-etched thin film transistor is illustrated; however, the thin film transistor having a structure similar to those described in Embodiments 2 and 3 can also be used. Moreover, the active matrix light-emitting device illustrated inFIG.5can have a structure similar to that of the above liquid crystal display device except for the structure of a pixel portion which will be shown below. After an insulating layer427is formed, a color filter layer453is formed. The colors of the color filter layer are red, green, and blue. The color filter layers are sequentially formed in the specific positions with a printing method, an ink-jet method, a photolithography technique, an etching method, or the like. By providing the color filter layer453on the substrate400side, alignment of the color filter layer453and a light-emitting region of a light-emitting element can be performed without depending on the alignment accuracy of the sealing substrate. Next, an overcoat layer458which covers the color filter layer453is formed. The overcoat layer458is formed using a light-transmitting resin. Here, an example in which full-color display is performed using color filter layers of three colors of red, green, and blue; however, the color display is not particularly limited thereto. A color of cyan, magenta, yellow, or white may be used. Next, a protective insulating layer428which covers the overcoat layer458and the insulating layer427is formed. For the protective insulating layer428, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum oxynitride film is used. Next, in a photolithography step and an etching step, a contact hole that reaches the connection electrode layer452is formed in the protective insulating layer428and the insulating layer427. In addition, in this photolithography step and etching step, the protective insulating layer428and the insulating layer427in a terminal portion are selectively etched to expose part of a terminal electrode. Further, in order to connect a second electrode of a light-emitting element formed later to a common potential line, a contact hole that reaches the common potential line is also formed. Next, a transparent conductive film is formed, and a photolithography step and an etching step are performed thereon, so that a first electrode457bwhich is electrically connected to the connection electrode layer452is formed. Next, a partition wall459is formed to cover the periphery of the first electrode457b. The partition wall459is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. The partition wall459can be formed using an organic insulating material or an inorganic insulating material. It is preferable that the partition wall459be formed to have an opening over the first electrode457bso that a sidewall is formed as an inclined surface with curvature. Such an opening can be easily formed using a photosensitive resin material. Through the steps described above, the state of the substrate illustrated in FIG.5can be obtained. Further, an EL layer is formed over the first electrode457band the second electrode is formed over the EL layer, whereby a light-emitting element is formed. The second electrode is electrically connected to the common potential line. The conductive layer417may be provided over the oxide semiconductor layer of the thin film transistor450of the driver circuit portion in each ofFIG.4andFIG.5. The conductive layer417can be formed using the same material in the same step as the pixel electrode layer457aor the first electrode457b. The conductive layer417is provided so as to overlap with the channel formation region443of the oxide semiconductor layer, whereby the amount of change over time in threshold voltage of the thin film transistor450can be reduced. The conductive layer417has a potential which is the same as that of the gate electrode layer421a, and can function as a second gate electrode layer. In addition, the conductive layer417may have a potential which is different from that of the gate electrode layer421a. Alternatively, the potential of the conductive layer417may be GND or 0 V, or the conductive layer417may be in a floating state. Since the thin film transistor is easily broken due to static electricity or the like, a protective circuit is preferably provided over the same substrate as the pixel portion or the driver circuit portion. The protective circuit is preferably formed with a non-linear element including an oxide semiconductor layer. For example, protective circuits are provided between the pixel portion and each of a scan-line input terminal and a signal-line input terminal. In this embodiment, a plurality of protective circuits are provided so as to prevent breakage of a pixel transistor and the like which can be caused when a surge voltage due to static electricity or the like is applied to a scan line, a signal line, and a capacitor bus line. Therefore, the protective circuit is formed so as to release charge to a common wiring when a surge voltage is applied to the protective circuit. Further, the protective circuit includes non-linear elements arranged in parallel to each other with the scan line therebetween. The non-linear element includes a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, the non-linear element can be formed through the same step as the thin film transistor460in the pixel portion, and can be made to have the same characteristics as a diode by connecting a gate terminal to a drain terminal of the non-linear element, for example. Note that this embodiment can be freely combined with any of the other embodiments. Embodiment 5 A semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor described in any of Embodiments 1, 2, and 3. Moreover, a driver circuit portion and a pixel portion, which each include the thin film transistor, can be formed over one substrate, whereby a system-on-panel can be obtained. A display device includes a display element. Further, a display medium whose contrast is changed by an electric effect, such as a liquid crystal element (also referred to as a liquid crystal display element) or an electronic ink, can be used. Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, the “display device” includes the following modules in its category: a module including a flexible printed circuit (FPC) or a tape automated bonding (TAB) tape; a module having a TAB tape which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element with a chip on glass (COG) method. The appearance and a cross section of a liquid crystal display panel, which is an embodiment of a display device, will be described with reference to FIGS.6A1,6A2, and6B. FIGS.6A1and6A2are each a plan view of a panel in which thin film transistors4010and4011and a liquid crystal element4013are sealed between a first substrate4001and a second substrate4006with a sealant4005interposed therebetween.FIG.6Bis a cross-sectional view taken along line M-N in FIGS.6A1and6A2. The sealant4005is provided so as to surround a pixel portion4002and a scan-line driver circuit4004which are provided over the first substrate4001. The second substrate4006is provided over the pixel portion4002and the scan-line driver circuit4004. Therefore, the pixel portion4002and the scan-line driver circuit4004are sealed together with a liquid crystal layer4008, by the first substrate4001, the sealant4005, and the second substrate4006. Further, a signal-line driver circuit4003which is formed using a single crystal semiconductor or a polycrystalline semiconductor is mounted in a region different from the region surrounded by the sealant4005over the first substrate4001. Note that there is no particular limitation on the connection method of the signal-line driver circuit4003, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG.6A1illustrates an example in which the signal-line driver circuit4003is mounted with a COG method, and FIG.6A2illustrates an example in which the signal-line driver circuit4003is mounted with a TAB method. Each of the pixel portion4002and the scan-line driver circuit4004which are provided over the first substrate4001includes a plurality of thin film transistors. InFIG.6B, the thin film transistor4010included in the pixel portion4002and the thin film transistor4011included in the scan-line driver circuit4004are illustrated as an example. Insulating layers4041,4020, and4021are provided over the thin film transistors4010and4011. Any of the highly reliable thin film transistors each including an oxide semiconductor layer, which are described in any of Embodiments 1, 2, and 3, can be used as the thin film transistors4010and4011. In this embodiment, the thin film transistors4010and4011are n-channel thin film transistors. A conductive layer4040is provided over the insulating layer4021so as to overlap with a channel formation region of an oxide semiconductor layer in the thin film transistor4011for the driver circuit. The conductive layer4040is provided so as to overlap with the channel formation region of the oxide semiconductor layer, whereby the amount of change over time in threshold voltage of the thin film transistor4011can be reduced. The conductive layer4040has a potential which is the same as that of the gate electrode of the thin film transistor4011, and can function as a second gate electrode layer. In addition, the conductive layer4040may have a potential which is different from that of the gate electrode of the thin film transistor4011. Alternatively, the potential of the conductive layer4040may be GND or 0 V, or the conductive layer4040may be in a floating state. A pixel electrode4030included in the liquid crystal element4013is electrically connected to the thin film transistor4010. A counter electrode4031of the liquid crystal element4013is formed over the second substrate4006. The liquid crystal element4013corresponds to a region where the pixel electrode4030, the counter electrode4031, and the liquid crystal layer4008overlap with each other. Note that the pixel electrode4030and the counter electrode4031are provided with an insulating layer4032and an insulating layer4033which each function as an alignment film, respectively. Note that a light-transmitting substrate such as glass, ceramics, or plastics can be used as the first substrate4001and the second substrate4006. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. A columnar spacer denoted by reference numeral4035is obtained by selective etching of an insulating layer and is provided in order to control the distance (a cell gap) between the pixel electrode4030and the counter electrode4031. Note that a spherical spacer may be used. The counter electrode4031is electrically connected to a common potential line formed over the same substrate as the thin film transistor4010. The counter electrode4031and the common potential line can be electrically connected to each other through conductive particles arranged between the pair of substrates, using a common connection portion. Note that the conductive particles are included in the sealant4005. Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is generated within an only narrow range of temperature, liquid crystal composition containing a chiral agent at 5 wt % or more so as to improve the temperature range is used for the liquid crystal layer4008. The liquid crystal composition which includes liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, has optical isotropy, which makes the alignment process unneeded, and has a small viewing angle dependence. An example of the liquid crystal display device is described in which a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are provided on the inner surface of the substrate in this order; however, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing process. In the thin film transistor4011, the insulating layer4041is formed in contact with the semiconductor layer including the channel formation region. The insulating layer4041can be formed using a material and a method which are similar to those of the insulating layer427described in Embodiment 1. In order to reduce the surface roughness of the thin film transistor, the thin film transistors are covered with the insulating layer4021which functions as a planarizing insulating layer. Here, a silicon oxide film is formed as the insulating layer4041with a sputtering method in a manner similar to that of Embodiment 1. A protective insulating layer4020is formed over the insulating layer4041. The protective insulating layer4020can be formed using a material and a method which are similar to those of the protective insulating layer428described in Embodiment 1. Here, a silicon nitride film is formed as the protective insulating layer4020with a PCVD method. The insulating layer4021is formed as the planarizing insulating layer. The insulating layer4021can be formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. Note that the insulating layer4021may be formed by stacking a plurality of insulating layers formed using these materials. Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. In addition, the organic group may include a fluoro group. The insulating layer4021can be formed, depending on the material, with a method such as a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (e.g., an ink-jet method, screen printing, or offset printing), or a tool such as a doctor knife, a roll coater, a curtain coater, or a knife coater. The step of baking the insulating layer4021serves also as the annealing step of the semiconductor layer, whereby the display device can be efficiently manufactured. The pixel electrode4030and the counter electrode4031can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added. Alternatively, the pixel electrode4030and the counter electrode4031can be formed using a conductive composition containing a conductive macromolecule (also referred to as a conductive polymer). It is preferable that the pixel electrode formed using the conductive composition have a sheet resistance of 10,000 Ω/square or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive macromolecule included in the conductive composition is preferably less than or equal to 0.1 Ω·cm. As the conductive macromolecule, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given. Further, a variety of signals and a potential are supplied to the signal-line driver circuit4003which is formed separately, the scan-line driver circuit4004, and the pixel portion4002through an FPC4018. In addition, a connection terminal electrode4015is formed from the same conductive film as the pixel electrode4030included in the liquid crystal element4013, and a terminal electrode4016is formed from the same conductive film as the source electrode layers and the drain electrode layers of the thin film transistors4010and4011. The connection terminal electrode4015is electrically connected to a terminal included in the FPC4018through an anisotropic conductive film4019. Note that FIGS.6A1,6A2, and6B illustrate an example in which the signal-line driver circuit4003is formed separately and mounted on the first substrate4001; however, this embodiment is not limited to this structure. The scan-line driver circuit may be separately formed and then mounted, or only part of the signal-line driver circuit or part of the scan-line driver circuit may be separately formed and then mounted. Note that this embodiment can be freely combined with any of the other embodiments. Embodiment 6 In this embodiment are described the appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel), with reference toFIGS.7A and7B.FIG.7Ais a plan view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed between the first substrate and a second substrate with a sealant.FIG.7Bis a cross-sectional view taken along line H-I inFIG.7A. A sealant4505is provided so as to surround a pixel portion4502, signal-line driver circuits4503aand4503b, and scan-line driver circuits4504aand4504bwhich are provided over a first substrate4501. In addition, a second substrate4506is provided over the pixel portion4502, the signal line-driver circuits4503aand4503b, and the scan-line driver circuits4504aand4504b. Accordingly, the pixel portion4502, the signal-line driver circuits4503aand4503b, and the scan-line driver circuits4504aand4504bare sealed together with a filler4507, by the first substrate4501, the sealant4505, and the second substrate4506. It is preferable that a panel be packaged (sealed) with a protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air, in this manner. Further, each of the pixel portion4502, the signal-line driver circuits4503aand4503b, and the scan-line driver circuits4504aand4504bwhich are provided over the first substrate4501includes a plurality of thin film transistors. InFIG.7B, a thin film transistor4510included in the pixel portion4502and a thin film transistor4509included in the signal-line driver circuit4503aare illustrated as an example. Any of the highly reliable thin film transistors each including an oxide semiconductor layer, which are described in any of Embodiments 1, 2, and 3, can be used as the thin film transistors4509and4510. In this embodiment, the thin film transistors4509and4510are n-channel thin film transistors. A conductive layer4540is provided over an insulating layer4544so as to overlap with a channel formation region of an oxide semiconductor layer in the thin film transistor4509for the driver circuit. The conductive layer4540is provided so as to overlap with the channel formation region of the oxide semiconductor layer, whereby the amount of change over time in threshold voltage of the thin film transistor4011before and after the BT test can be reduced. The conductive layer4540has a potential which is the same as that of the gate electrode of the thin film transistor4509, and can function as a second gate electrode layer. In addition, the conductive layer4540may have a potential which is different from that of the gate electrode of the thin film transistor4509. Alternatively, the potential of the conductive layer4540may be GND or 0 V, or the conductive layer4540may be in a floating state. In a periphery of the oxide semiconductor layer of the thin film transistor4509, an oxide insulating layer4542which covers a peripheral portion (including a side surface) of the oxide semiconductor layer is formed. Further, the thin film transistor4510is electrically connected to a first electrode4517through a connection electrode layer4548. Further, the oxide insulating layer4542which covers a peripheral portion (including a side surface) of the oxide semiconductor layer of the thin film transistor4510is formed. The oxide insulating layer4542can be formed using a material and a method which is similar to that of the oxide insulating layer426described in Embodiment 1. In addition, the insulating layer4544which covers the oxide insulating layer4542is formed. The insulating layer4544can be formed using a material and a method which are similar to those of the protective insulating layer428described in Embodiment 1. A color filter layer4545is formed over the thin film transistor4510so as to overlap with a light-emitting region of a light-emitting element4511. Further, in order to reduce the surface roughness of the color filter layer4545, the color filter layer4545is covered with an overcoat layer4543which functions as a planarizing insulating film. Further, an insulating layer4546is formed over the overcoat layer4543. The insulating layer4546can be formed using a material and a method which are similar to those of the protective insulating layer428described in Embodiment 1. The first electrode4517which is a pixel electrode included in the light-emitting element4511is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor4510. Note that the structure of the light-emitting element4511is not limited to a stacked structure of the first electrode4517, an electroluminescent layer4512, and a second electrode4513. The structure of the light-emitting element4511can be changed as appropriate depending on, for example, the direction in which light is extracted from the light-emitting element4511. A partition wall4520can be formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is preferable that the partition wall4520be formed to have an opening over the first electrode4517so that a sidewall is formed as an inclined surface with curvature. Such an opening can be easily formed using a photosensitive resin material. The electroluminescent layer4512is not limited to a single layer and may be formed using a plurality of layers stacked. A protective film may be formed over a second electrode4513and the partition wall4520in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed. Further, a variety of signals and a potential are supplied to the signal-line driver circuits4503aand4503b, the scan-line driver circuits4504aand4504b, and the pixel portion4502through FPCs4518aand4518b. In addition, a connection terminal electrode4515is formed from the same conductive film as the first electrode4517included in the light-emitting element4511, and a terminal electrode4516is formed from the same conductive film as a source electrode layer and a drain electrode layer of the thin film transistor4509. The connection terminal electrode4515is electrically connected to a terminal included in the FPC4518athrough an anisotropic conductive film4519. As the second substrate located in the direction in which light is extracted from the light-emitting element4511needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used for the second substrate. As the filler4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, polyvinyl chloride (PVC), acrylic, polyimide, an epoxy resin, a silicone resin, polyvinyl butyral (PVB), or ethylene vinyl acetate (EVA) can be used. If necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate for a light-emitting surface of the light-emitting element. Further, a polarizing plate or a circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed. As the signal-line driver circuits4503aand4503band the scan-line driver circuits4504aand4504b, a driver circuit formed using a single crystal semiconductor or a polycrystalline semiconductor may be mounted. Alternatively, only the signal line-driver circuits or part thereof, or only the scan-line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated inFIGS.7A and7B. Through the steps described above, a highly reliable light-emitting display device (display panel) can be manufactured. Note that this embodiment can be freely combined with any of the other embodiments. Embodiment 7 A display device disclosed in this specification can be applied to a variety of electronic devices (including an amusement machine). Examples of electronic devices are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a cellular phone (also referred to as a mobile phone or a cellular phone set), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like. FIG.8Aillustrates an example of a cellular phone. The cellular phone1100is provided with a display portion1102incorporated in a housing1101, an operation button1103, an external connection port1104, a speaker1105, a microphone1106, and the like. When the display portion1102of the cellular phone1100is touched with a finger or the like, data can be inputted into the cellular phone1100. Further, operations such as making calls, composing mails, or the like can be performed by touching the display portion1102with a finger or the like. There are mainly three screen modes of the display portion1102. The first mode is a display mode mainly for displaying images. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-and-input mode, which is a combination of the two modes, i.e. a combination of the display mode and the input mode. For example, in the case where a call is made or a mail is composed, a text input mode mainly for inputting text is selected for the display portion1102so that text displayed on a screen can be inputted. In that case, it is preferable to display a keyboard or number buttons on almost all area of the screen of the display portion1102. When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the cellular phone1100, display on the screen of the display portion1102can be automatically switched by determining the direction of the cellular phone1100(whether the cellular phone1100is placed horizontally or vertically for a landscape mode or a portrait mode). The screen modes are switched by touching the display portion1102or operating the operation button1103of the housing1101. Alternatively, the screen modes may be switched depending on the kind of the image displayed on the display portion1102. For example, when a signal of an image displayed on the display portion is a signal of moving image data, the screen mode is switched to the display mode. When the signal is a signal of text data, the screen mode is switched to the input mode. Further, in the input mode, when input by touching the display portion1102is not performed for a certain period while a signal detected by the optical sensor in the display portion1102is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode. The display portion1102can also function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken when the display portion1102is touched with a palm or a finger, whereby personal identification can be performed. Further, by providing a backlight or a sensing light source which emits a near-infrared light in the display portion, an image of a finger vein, a palm vein, or the like can be taken. FIG.8Balso illustrates an example of a cellular phone. A portable information terminal whose example is illustrated inFIG.8Bcan have a plurality of functions. For example, in addition to a telephone function, such a portable information terminal can have a function of processing a variety of data by incorporating a computer. The portable information terminal illustrated inFIG.8Bincludes two housings, a housing1800and a housing1801. The housing1800includes a display panel1802, a speaker1803, a microphone1804, a pointing device1806, a camera1807, an external connection terminal1808, and the like. The housing1801includes a keyboard1810, an external memory slot1811, and the like. In addition, an antenna is incorporated in the housing1801. The display panel1802is provided with a touch panel. A plurality of operation keys1805which is displayed as images is illustrated by dashed lines inFIG.8B. Further, in addition to the above structure, a contactless IC chip, a small memory device, or the like may be incorporated. The display device can be used for the display panel1802and the direction of display is changed appropriately depending on an application mode. Further, the display device is provided with the camera1807on the same surface as the display panel1802, and thus it can be used as a videophone. The speaker1803and the microphone1804can be used for videophone calls, recording, and playing sound, and the like as well as voice calls. Moreover, the housings1800and1801in a state where they are developed as illustrated inFIG.8Bcan shift so that one is lapped over the other by sliding; therefore, the size of the portable information terminal can be reduced, which makes the portable information terminal suitable for being carried. The external connection terminal1808can be connected to various types of cables such as a charging cable and a USB cable, and charging and data communication with a personal computer are possible. Moreover, a storage medium can be inserted into the external memory slot1811so that a larger amount of data can be stored and can be moved. Further, in addition to the above functions, an infrared communication function, a television reception function, or the like may be provided. FIG.9Aillustrates an example of a television set9600. In the television set9600, a display portion9603is incorporated in a housing9601. The display portion9603can display images. Here, the housing9601is supported by a stand9605. The television set9600can be operated with an operation switch of the housing9601or a separate remote controller9610. Channels and volume can be controlled with operation keys9609of the remote controller9610so that an image displayed on the display portion9603can be controlled. Furthermore, the remote controller9610may be provided with a display portion9607for displaying data outputted from the remote controller9610. Note that the television set9600is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the television set9600is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed. FIG.9Billustrates an example of a digital photo frame9700. For example, in the digital photo frame9700, a display portion9703is incorporated in a housing9701. The display portion9703can display a variety of images. For example, the display portion9703can display data of an image taken with a digital camera or the like and function as a normal photo frame. Note that the digital photo frame9700is provided with an operation portion, an external connection terminal (e.g., a USB terminal), an external memory slot, and the like. Although these components may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame9700. For example, a memory storing data of an image taken by a digital camera is inserted in the external memory slot of the digital photo frame, and the image data can be transferred and displayed on the display portion9703. The digital photo frame9700may be configured to transmit and receive data wirelessly. The structure may be employed in which desired image data is transferred wirelessly and displayed. FIG.10is a portable game machine and includes two housings, a housing9881and a housing9891, which are connected with a joint portion9893so that the portable game machine can be opened or folded. A display portion9882and a display portion9883are incorporated in the housing9881and the housing9891, respectively. Moreover, the portable game machine illustrated inFIG.10is provided with a speaker portion9884, a recording medium insertion portion9886, an LED lamp9890, input means (operation keys9885, a connection terminal9887, a sensor9888(having a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radial ray, flow rate, humidity, gradient, vibration, odor, or infrared ray), and a microphone9889, and the like. It is needless to say that the structure of the portable amusement machine is not limited to the above and other structures provided with at least a thin film transistor disclosed in this specification can be employed. The portable amusement machine may include other accessory equipment as appropriate. The portable game machine illustrated inFIG.10has a function of reading a program or data stored in a recording medium to display it on the display portion, and a function of sharing information with another portable game machine by wireless communication. Note that functions of the portable game machine illustrated inFIG.10are not limited to those described above and the portable game machine can have a variety of functions. As described above, the display device described in other embodiments can be arranged in display panels of a variety of electronic appliances such as the above ones. Note that this embodiment can be freely combined with any of the other embodiments. The present application is based on Japanese Patent Application serial No. 2009-204801 filed with the Japan Patent Office on Sep. 4, 2009, the entire contents of which are hereby incorporated by reference. EXPLANATION OF REFERENCE 400: substrate,402: gate insulating layer,404: oxide semiconductor layer,417: conductive layer,422: source wiring layer,426: oxide insulating layer,427: insulating layer,428: protective insulating layer,430: capacitor wiring layer,431: capacitor electrode layer,440: thin film transistor,442: connection electrode layer,443: channel formation region,449: connection electrode layer,450: thin film transistor,452: connection electrode layer,453: color filter layer,456: planarization insulating layer,458: overcoat layer,459: partition wall,460: thin film transistor,470: thin film transistor,480: thin film transistor,421a: gate electrode layer,421b: gate electrode layer,421c: gate wiring layer,424a: high-resistance source region,424b: high-resistance drain region,424c: region,424d: region,424e: region,424f: region,425a: source electrode layer,425b: drain electrode layer,426a: oxide insulating layer,426b: oxide insulating layer,444c: region,444d: region,445a: source electrode layer,445b: drain electrode layer,446a: oxide conductive layer,446b: oxide conductive layer,451a: gate electrode layer,451b: gate electrode layer,455a: source electrode layer,455b: drain electrode layer,457a: pixel electrode layer,457b: electrode,1100: cellular phone,1101: housing,1102: display portion,1103: operation button,1104: external connection port,1105: speaker,1106: microphone,1800: housing,1801: housing,1802: display panel,1803: speaker,1804: microphone,1805: operation keys,1806: pointing device,1807: camera,1808: external connection terminal,1810: keyboard,1811: external memory slot,4001: substrate,4002: pixel portion,4003: signal-line driver circuit,4004: scan-line driver circuit,4005: sealant,4006: substrate,4008: liquid crystal layer,4010: thin film transistor,4011: thin film transistor,4013: liquid crystal element,4015: connection terminal electrode,4016: terminal electrode,4018: FPC,4019: anisotropic conductive film,4020: protective insulating layer,4021: insulating layer,4030: pixel electrode,4031: counter electrode,4032: insulating layer,4040: conductive layer,4041: insulating layer,4501: substrate,4502: pixel portion,4505: sealant,4506: substrate,4507: filler,4509: thin film transistor,4510: thin film transistor,4511: light-emitting element,4512: electroluminescent layer,4513: electrode,4515: connection terminal electrode,4516: terminal electrode,4517: electrode,4519: anisotropic conductive film,4520: partition wall,4540: conductive layer,4542: oxide insulating layer,4543: overcoat layer,4544: insulating layer,4545: color filter layer,4546: insulating layer,4548: connection electrode layer,4503a: signal-line driver circuit,4503b: signal-line driver circuit,4504a: scan-line driver circuit,4504b: scan-line driver circuit,4518a: FPC,9600: television set,9601: housing,9603: display portion,9605: stand,9607: display portion,9609: operation keys,9610: remote controller,9700: digital photo frame,9701: housing,9703: display portion,9881: housing,9882: display portion,9883: display portion,9884: speaker portion,9885: operation keys,9886: recording medium insertion portion,9887: connection terminal,9888: sensor,9889: microphone,9890: LED lamp,9891: housing,9893: joint portion. | 94,699 |
11862644 | DETAILED DESCRIPTION Hereinafter a preferred embodiment of the present disclosure will be described with reference to the accompanying drawings to exemplify the embodiments of the present disclosure can be implemented, which can fully describe the technical contents of the present disclosure to make the technical content of the present disclosure clearer and easy to understand. However, the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts are within the scope of the present disclosure. In the description of the present disclosure, it should be understood that terms such as “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counter-clockwise”, as well as derivative thereof should be construed to refer to the orientation as then described or as shown in the drawings under discussion. These relative terms are for convenience of description, do not require that the present disclosure be constructed or operated in a particular orientation, and shall not be construed as causing limitations to the present disclosure. In addition, terms such as “first” and “second” are used herein for purposes of description and are not intended to indicate or imply relative importance or significance. Thus, features limited by “first” and “second” are intended to indicate or imply including one or more than one these features. In the description of the present disclosure, “a plurality of” relates to two or more than two, unless otherwise specified. In the description of the present disclosure, it should be noted that unless there are express rules and limitations, the terms such as “mount,” “connect,” and “bond” should be comprehended in broad sense. For example, it can mean a permanent connection, a detachable connection, or an integrate connection; it can mean a mechanical connection, an electrical connection, or can communicate with each other; it can mean a direct connection, an indirect connection by an intermediate, or an inner communication or an interreaction between two elements. A person skilled in the art should understand the specific meanings in the present disclosure according to specific situations. In the description of the present disclosure, unless specified or limited otherwise, it should be noted that, a structure in which a first feature is “on” or “beneath” a second feature may include an embodiment in which the first feature directly contacts the second feature and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature does not directly contact the second feature. Furthermore, a first feature “on,” “above,” or “on top of” a second feature may include an embodiment in which the first feature is right “on,” “above,” or “on top of” the second feature and may also include an embodiment in which the first feature is not right “on,” “above,” or “on top of” the second feature, or just means that the first feature has a sea level elevation greater than the sea level elevation of the second feature. While first feature “beneath,” “below,” or “on bottom of” a second feature may include an embodiment in which the first feature is right “beneath,” “below,” or “on bottom of” the second feature and may also include an embodiment in which the first feature is not right “beneath,” “below,” or “on bottom of” the second feature, or just means that the first feature has a sea level elevation less than the sea level elevation of the second feature. The disclosure below provides many different embodiments or examples for realizing different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present disclosure. Furthermore, reference numbers and/or letters may be repeated in different examples of the present disclosure. Such repetitions are for simplification and clearness, which per se do not indicate the relations of the discussed embodiments and/or settings. Moreover, the present disclosure provides examples of various specific processes and materials, but the applicability of other processes and/or application of other materials may be appreciated by a person skilled in the art. Specifically, please refer toFIG.1toFIG.6, an embodiment of the present disclosure provides an array substrate and a display panel. In conventional GOA substrates, in order to narrow frames at a right side and a left side of display panels, the clock signals lines are disposed between pixel units, just like data lines. Thus, distances between the clock signal lines are short, easily leading to interference and coupling between the clock signal lines and the data lines, thereby causing data signals to be unstable. A solution is to evenly space the clock signal lines and the data lines; however, it not only consumes more space, but also compresses an effective area of an opening area of the pixel units. Therefore, the present disclosure provides an array substrate and a display panel to solve the above problem. Please refer toFIG.1, a first schematic structural view showing a display panel according to an embodiment of the present disclosure is provided. A display panel1includes a display area11and a non-display area12. The display area11include a plurality of data lines111, which are parallel to each other and are sequentially vertically disposed; a plurality of scan lines112, which are parallel to each other and are sequentially horizontally disposed; a plurality of pixel units113including the data lines111and the scan lines112; and a plurality of clock signal lines114disposed below a plurality of projections of a vertical centerline of the pixel units. The non-display area12of the display panel1includes a driver chip121, a first clock signal source122, a second clock signal source123, a third clock signal source124, and a fourth clock signal source125. The data lines111in the display area11and the driver chip121in the non-display area12are electrically connected. The clock signal lines114in the display area11and the clock signal source in the non-display area12are electrically connected. Furthermore, please refer toFIG.2, a first schematic structural view of the array substrate according to an embodiment of the present disclosure is provided. A plurality of pixel areas arranged in an array manner are defined on the array substrate. A data line211is disposed between two adjacent columns of the pixel areas. Each of the pixel areas includes a scan line212that divides each of the pixel units into a main pixel area and a sub-pixel area. The main pixel and the sub-pixel area in each of the pixel units are electrically connected to the data lines211disposed between two adjacent pixel areas. Each of the pixel units further includes an opening area21and a non-opening area22. A first thin film transistor (TFT) section T1is disposed in the non-opening area22in the main pixel area. A second TFT section T2is disposed in the non-opening area22in the sub-pixel area. The clock signal lines213in the non-opening area22of the pixel units are a plurality of second clock signal lines2132. The second clock signal lines2132bypass the first TFT section T1and the second TFT section T2and are parallel to the data lines211. Distances between the second clock signal lines2132and the data lines211are second distances L2. Specifically, the first TFT section T1and the second TFT section T2may be a TFT, a field-effect transistor, or other devices with same property. Because a source and a drain of the transistor used in the present disclosure are symmetrical to each other, the source and the drain are interchangeable. A gate of the first TFT section T1is electrically connected to the scan line212corresponding to the pixel unit where the gate is disposed, a source of the first TFT section T1is electrically connected to the data line211corresponding to the pixel unit where the source is disposed, and a drain of the first TFT section T1is electrically connected to an electrode of the main pixel area. A gate of the second TFT section T2is electrically connected to the scan line112corresponding to the pixel unit where the gate is disposed, a source of the second TFT section T2is electrically connected to the data line212corresponding to the pixel unit where the source is disposed, and a source of the second TFT section T2is electrically connected to an electrode of the sub-pixel area. Furthermore, an opening area21of the pixel units is divided into an opening area21aof the pixel area and an opening area21bof the sub-pixel area. A pixel electrode with a pozidriv shape (please refer toFIG.2) is disposed in both the opening area21aof the pixel area and the opening area21bof the sub-pixel area. That is, every main pixel area and every sub-pixel area are divided into four pixel regions with equal size by a plurality of first trunk electrodes disposed at a vertical centerline and a plurality of second trunk electrodes disposed at a horizontal centerline, thereby allowing corresponding liquid crystals to orient in different directions, and solving a problem of color shifting. Furthermore, a first clock signal line2131of the first trunk electrodes213, which is parallel to the data lines211, is further disposed below the first trunk electrodes in the opening area21of the pixel units. Distances between the first clock signal lines2131and the data lines211are first distances L1, and the first distances L1are greater than the second distances L2. Furthermore, a width of the first clock signal lines2131is less than or equal to a width of the first trunk electrodes. Preferably, the first clock signal line2131is fully blocked by the first trunk electrodes. Furthermore, the pixel units include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, the pixel units may further include a white sub-pixel, a yellow sub-pixel, and other sub-pixels of different colors, which will not affect the present disclosure. Please refer toFIG.3, a second schematic structural view showing the array substrate according to an embodiment of the present disclosure is provided. An array substrate3specifically includes: a first substrate31disposed on a bottom side of the array substrate3, wherein the first substrate31is typically a transparent glass substrate. A first insulating layer32is disposed on a side of the first substrate31, wherein a material of the first insulating layer32may be silicon oxide, silicon nitride, or a composite film consisting of thereof. A first metal layer33is disposed in the first insulating layer32, wherein the first metal layer33includes a plurality of scan lines and a plurality of gate lines331disposed on a side of the first insulating layer near the first substrate. The scan lines output a current and a voltage to the gate lines331, and the first metal layer33is usually made of molybdenum, aluminum, an aluminum nickel alloy, gold, chromium, copper, a titanium aluminum alloy, or combinations thereof. A second insulating layer35is disposed on a side of the first insulating layer32away from the first substrate31, wherein a material of the second insulating layer35may be same as that of the first insulating layer. A second metal layer34is disposed in the second insulating layer35, wherein the second metal layer34includes a plurality of data lines341, a source342, a drain343, an active layer344, and a plurality of clock signal lines345, which are disposed on a side of the second insulating layer near the first insulating layer. The data lines341provide a current for the source342and the drain343, which are electrically connected to a doped area of the active layer344, and a material of the second metal layer34may be same as that of the first metal layer, and preferably, is a titanium aluminum alloy; A planarization layer36is disposed on a side of the second insulating layer35away from the first insulating layer, wherein the planarization layer36is configured to flatten a surface of the array substrate. A pixel through hole371and a pixel electrode37are further defined on a side of the planarization layer36away from the second insulating layer, wherein the pixel through hole371passes through the planarization layer36and the second insulating layer35, and is electrically connected to the drain343. In one embodiment of the present disclosure, the clock signal lines are disposed below the first trunk electrodes of the pixel units. The clock signal lines and the data lines341are disposed in the second metal layer34, as shown inFIG.3. As shown inFIG.4, a third schematic structural view showing the array substrate according to an embodiment of the present disclosure is provided. In another embodiment of the present disclosure, the array substrate3also includes: a first substrate disposed on a bottom side of the array substrate3, wherein the first substrate31is typically a transparent glass substrate. A first insulating layer32is disposed on a side of the first substrate31, wherein a material of the first insulating layer32may be silicon oxide, silicon nitride, or a composite film consisting of thereof. In addition, a first through hole321and a second through hole322are further defined on a side of the first insulating layer32away from the first substrate31. A first metal layer33is disposed in the first insulating layer32, wherein the first metal layer33includes a plurality of scan lines and a plurality of gate lines331disposed on a side of the first insulating layer near the first substrate. The scan lines output a current and a voltage to the gate lines331, and the first metal layer33is usually made of molybdenum, aluminum, an aluminum nickel alloy, gold, chromium, copper, a titanium aluminum alloy, or combinations thereof. In addition, the clock signals lines322are also disposed in the first metal layer33and pass through the first metal layer33. The first metal layer33is disconnected, so that the clock signals lines322may pass through it. The first through hole321and the second through hole322are respectively disposed at two sides of the clock signal lines332away from the first substrate31. An end of the first through hole321and an end of the second through hole322are electrically connected to the first metal layer33. A second insulating layer35is disposed on a side of the first insulating layer32away from the first substrate31, wherein a material of the second insulating layer35may be same as that of the first insulating layer. A second metal layer34is disposed in the second insulating layer35, wherein the second metal layer34include a plurality of data lines341, a source342, a drain343, an active layer344, and a plurality of clock signal lines345, which are disposed on a side of the second insulating layer near the first insulating layer. The data lines341provide a current for the source342and the drain343, which are electrically connected to a doped area of the active layer344. A material of the second metal layer34may be same as that of the first metal layer, and preferably, it is a titanium aluminum alloy. A planarization layer36is disposed on a side of the second insulating layer35away from the first insulating layer, wherein the planarization layer36is configured to flatten a surface of the array substrate. A pixel through hole371and a pixel electrode37are further defined on a side of the planarization layer36away from the second insulating layer, wherein the pixel through hole371passes through the planarization layer36and the second insulating layer35, and is electrically connected to the drain343. In addition, a third insulating layer38is further disposed in the array substrate3and is disposed between the first insulating layer32and the second insulating layer35. A layer of a metal oxide381is disposed in the third insulating layer38, an end of the metal oxide381is connected to the first through hole321, and another end of the metal oxide381is connected to the second through hole322. Therefore, the first metal layer381can be connected to the metal oxide381by the first through hole322at where the clock signal lines322pass through the first metal layer381, thereby preventing short circuiting from happening between the first metal layer381and the clock signal lines322. Furthermore, a thickness of the third insulating layer is relatively small, and the thickness of the third insulating layer38is less than a thickness of the first insulating layer32or a thickness of the second insulating layer35. Furthermore, the array substrate is a GOA array substrate, and a backlight module of the array substrate is a direct-type backlight module or an edge-type backlight module. Please refer toFIG.5, a second schematic structural view showing a display panel according to an embodiment of the present disclosure is provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer4disposed between the first substrate and the second substrate. The first substrate is the array substrate3, which adopts the clock signal lines345and is disposed in the second metal layer34. The second substrate is a color filter substrate5. The array substrate3is disposed opposite to the color filter substrate5. Furthermore, the second substrate includes a second substrate51, a black matrix52, and a common electrode layer53. The common electrode layer53is disposed on a side near the liquid crystal layer4, the black matrix52is disposed on a side of the common electrode layer53away from the liquid crystal layer4, and the second substrate is disposed on a side of the black matrix52away from the common electrode layer53. Furthermore, the liquid crystal layer4further includes a plurality of liquid crystals41, and a frame sealant42disposed around the liquid crystals41and configured to attach the array substrate3to the color filter substrate5. Please refer toFIG.6, a third schematic structural view showing the display panel according to an embodiment of the present disclosure is provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer4disposed between the first substrate and the second substrate. The first substrate is the array substrate3, which adopts the clock signal lines345and is disposed in the first metal layer33. The second substrate is the color filter substrate. The array substrate3is disposed opposite to the color filter substrate5. Furthermore, the second substrate includes a second substrate51, a black matrix52, and a common electrode layer53. The common electrode layer53is disposed on a side near the liquid crystal layer4, the black matrix52is disposed on a side of the common electrode layer53away from the liquid crystal layer4, and the second substrate is disposed on a side of the black matrix52away from the common electrode layer53. Furthermore, the liquid crystal layer4further includes a plurality of liquid crystals41, and a frame sealant42disposed around the liquid crystals41and configured to attach the array substrate3to the second substrate5. The present disclosure provides an array substrate, including a plurality of data lines, a plurality of scan lines, a plurality of clock signal lines, and a plurality of pixel units formed by the data lines and the scan lines horizontally and vertically crossing each other. The data lines are disposed between two adjacent columns of the pixel units. The scan lines are disposed between two adjacent rows of the pixel units. The clock signal lines in an opening area of the pixel units are disposed in a plurality of orthographic projection areas of a plurality of trunk electrodes, are parallel to the data lines, and are disposed on a different layer from the pixel electrodes. The signal lines do not occupy too much space in the display panel, and an effective area of an opening area of pixel units does not be compressed. Furthermore, distances between the clock signal lines and the data lines are increased, thereby preventing stability of the data lines from being affected due to interference and coupling between the clock signal lines and the data lines. Moreover, the clock signal lines can be made of a metal material or a metal oxide material. When the clock signal lines are made of the metal materials, widths of the clock signal lines can be minimized, and space in the display panel occupied by the clock signal lines can be reduced. In the above embodiments, the focus of each embodiment is different, and for a part that is not detailed in an embodiment, reference may be made to related descriptions of other embodiments. An array substrate and a display device have been described in detail with embodiments provided by the present disclosure which illustrates principles and implementations thereof. However, the description of the above embodiments is only for helping to understand the technical solution of the present disclosure and core ideas thereof, and it is understood by those skilled in the art that many changes and modifications to the described embodiment can be carried out without departing from the scope and the spirit of the disclosure that is intended to be limited only by the appended claims. | 21,691 |
11862645 | DETAILED DESCRIPTION Hereinafter, the invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention. The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In addition, the size and thickness of each configuration shown in the drawings are arbitrarily shown for better understanding and ease of description, but the invention is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. In this specification, the phrase “in a plan view” means viewing a target portion from the top, and the phrase “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side. It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below. “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. In an exemplary embodiment, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims. Referring toFIG.1, a display device according to an exemplary embodiment will be described hereinafter. FIG.1is a top plan view of a display device according to an exemplary embodiment. As shown inFIG.1, a display device100according to an exemplary embodiment includes a display area DA and a peripheral area PA. In an exemplary embodiment, the display device100may be provided as an organic light emitting diode (“OLED”) display, for example. However, the invention is not limited thereto, and it may be provided as a liquid crystal display (“LCD”) and the like. The display area DA may be disposed at a center of the display device100, and the peripheral area PA may surround the display area DA. However, the layout of the display area DA and the peripheral area PA is not limited thereto, and the peripheral area PA may be disposed at lateral edges of the display area DA. In an alternative exemplary embodiment, the peripheral area PA may be disposed in an upper edge or a lower edge of the display area DA. A plurality of gate lines GL1to GLn (where n is a natural number) are disposed in parallel with each other in the display area DA of the display device100, and a plurality of data lines DL1and DLm (where m is a natural number) are disposed in parallel with each other in the display area DA. The plurality of gate lines GL1to GLn and the plurality of data lines DL1to DLm are insulated from each other, and define the plurality of pixels PX by crossing each other. Each pixel PX is a minimum unit for displaying an image, and the plurality of pixels PX may be disposed in a matrix format. The plurality of pixel PX are connected with the gate lines GL1to GLn and the data lines DL1to DLm and receive predetermined signals therefrom. The peripheral area PA of the display device100may include a pad area AA. The pad area AA is disposed in a lower edge of the display device100, but the invention is not limited thereto. In an alternative exemplary embodiment, the pad area AA may be disposed at another edge of the display device100or may be disposed at lateral edges of the display device100. The pad area AA implies an area where a plurality of gate pads500that are respectively connected with the plurality of gate lines GL1to GLn and a plurality of data pads600that are respectively connected with the plurality of data lines DL1to DLm are provided. The plurality of data lines DL1to DLm may extend to the peripheral area PA, and the data lines DL1to DLm and the data pads600may be connected with each other through connection wires700. The connection wires700may be provided on different layers from the data lines DL1to DLm. Insulation layers may be provided between the connection wires700and the data lines DL1to DLm, a contact hole is provided in each insulation layer, and the connection wire700and the corresponding data lines DL1to DLm may be connected with each other through the contact hole. A test circuit portion800may be further provided in the pad area AA, and the test circuit portion800is connected with the plurality of data pads600. The test circuit portion800and the data pads600may be connected through test wires900. In an exemplary embodiment, an integrated circuit (“IC”) chip where the gate driver and the data driver are installed may be attached to the pad area AA, and the IC chip may be electrically connected with the plurality of gate pads500and the plurality of data pads600by an anisotropic conductive film (“ACF”), for example. The pad area of the display device according to the illustrated exemplary embodiment will now be described in detail with reference toFIG.2. FIG.2is a top plan view that illustrates a part of the pad area of the display device according to the exemplary embodiment. As shown inFIG.2, the plurality of data pads600are disposed in the pad area AA (refer toFIG.1) of the display device100. The plurality of data pads600may be aligned along a first direction W1and a second direction W2. The second direction W2may be a horizontal direction, and the first direction W1may be a direction that is inclined at a predetermined angle with respect to the second direction W2. However, the invention is not limited thereto, and the first direction W1may be a vertical direction. That is, the first direction W1and the second direction W2may be perpendicular to each other. The connection wire700or the test wire900is disposed between data pads600that are adjacent to each other in the second direction W2. One end of the connection wire700is connected with the data pad600, and the other end of the connection wire700is connected with the data lines DL1to DLm (refer toFIG.1) that are disposed in the display area DA (refer toFIG.1). That is, the connection wires700may connect the data pads600and the data lines DL1to DLm to each other. The test wires900are connected with the data pads600and the test circuit portion800. The test circuit portion800is a circuit device that determines whether the display device100normally operates by applying a predetermined signal to the display device100. That is, the test circuit portion800generates a predetermined signal and applies the signal to the test wires900, and the test wires900may supply the signal to the data lines DL1to DLm through the data pads600. One data pad600is connected with one connection wire700and one test wire900. In the illustrated exemplary embodiment, the data pads600are aligned in four rows. Three wires700and900may be disposed between data pads600that are adjacent to each other in the second direction W2. Three connection wires700may be disposed between adjacent data pads600that are disposed in the first row. Two connection wires700and one test wire900may be disposed between adjacent data pads600that are disposed in the second row. One connection wire700and two test wires900may be disposed between adjacent data pads600that are disposed in the third row. Three test wires900may be disposed between adjacent data pads600that are disposed in the fourth row. Dummy data pads650may be further provided in the pad area AA of the display device100. The dummy data pad650may have substantially the same shape as that of the data pad600. The dummy data pads650are floated rather than being connected with wires. Thus, no signal is applied to the dummy data pads650. The dummy data pads650may be disposed in the same layer as the data pads600. The dummy data pad650may be used as an alignment key when the IC chip is attached to the pad area AA. Referring toFIGS.3to9, the data pads of the display device and wires that are connected to the data pads according to the exemplary embodiment will be described in detail with reference toFIGS.3to9. FIG.3is an enlarged top plan view that illustrates a part of the pad area of the display device according to the exemplary embodiment,FIG.4is a top plan view of partial layers ofFIG.3,FIG.5is a top plan view of other layers ofFIG.3, andFIG.6is a top plan view of still other layers ofFIG.3.FIG.7is a cross-sectional view ofFIG.3, taken along line VII-VII,FIG.8is a cross-sectional view ofFIG.3, taken along line VIII-VIII, andFIG.9is a cross-sectional view ofFIG.3, taken along line IX-IX. As shown inFIG.3, the plurality of data pads600are aligned in the first direction W1and the second direction W2in a pad area. The plurality of data pads600may be aligned in four rows, and four data pads600are aligned in each row inFIG.3.FIG.3illustrates a part of the pad area, and four or more data pads600may be aligned in each row. The plurality of data pads600includes a leftmost first data pad601in the first row and a leftmost second data pad602in the second row. The first data pad601and the second data pad602are disposed adjacent to each other along the first direction W1. The first data pad601and the second data pad602may be respectively disposed in different layers. The first data pad601may have a quadrangular shape in a plan view, and may be substantially disposed in the shape of a parallelogram. Two sides of the parallelogram may be parallel with the first direction W1, and the other two sides thereof may be parallel with the second direction W2. The first data pad601is connected with a first connection wire701and a first test wire901. The first connection wire701is directly connected with the first data pad601, and particularly, may be connected with an upper edge of the first data pad601. The first connection wire701may substantially extend in a vertical direction. The first test wire901is directly connected with the first data pad601, and particularly, may be connected with a lower edge of the first data pad601. The first test wire901may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W1. The first data pad601, the first connection wire701, and the first test wire901are disposed in the same layers. As shown inFIG.7, a buffer layer120is provided on a substrate110, and a gate insulation layer140is provided on the buffer layer120. In an exemplary embodiment, the buffer layer120may be provided as a single layer of a silicon nitride (SiNx) or a multilayer where a silicon nitride (SiNx) and a silicon oxide (SiOx) are stacked, for example. The buffer layer120serves to planarize a surface of the substrate110while preventing an unnecessary component such as an impurity or moisture from permeating. The buffer layer120may be disposed not only in a peripheral area PA (refer toFIG.1) of the substrate110but also in a display area DA (refer toFIG.1). That is, the buffer layer120may be disposed on the entire surface of substrate110. However, the invention is not limited thereto, and in another exemplary embodiment, the buffer layer120may be omitted as necessary. In an exemplary embodiment, the gate insulation layer140may include an inorganic insulation material such as a silicon oxide (SiOx), a silicon nitride (SiNx), a silicon oxynitride (SiON), a silicon oxyfluoride (SiOF), an aluminum oxide (AlOx), and the like, or an organic insulating material, for example, and may be provided as a single layer or a multilayer that includes at least one of these materials. In an exemplary embodiment, the gate insulation layer140may include a first gate insulation layer141and a second gate insulation layer142that is provided on the first gate insulation layer141, for example. The gate insulation layer140may be disposed not only in a peripheral area PA (refer toFIG.1) of the substrate110but also in a display area DA (refer toFIG.1). That is, the gate insulation layer140may be disposed on the entire surface of the substrate110. The first data pad601is disposed on the first gate insulation layer141and the second gate insulation layer142is disposed on the first data pad601. The second gate insulation layer142covers a part of the first data pad601, and specifically, the second gate insulation layer142covers an edge of the first data pad601. That is, the edge of the first data pad601may be disposed between the first gate insulation layer141and the second gate insulation layer142. An interlayer insulation layer160may be provided on the second gate insulation layer142. In an exemplary embodiment, the interlayer insulation layer160may include an inorganic insulation material such as a silicon oxide (SiOx), a silicon nitride (SiNx), a silicon oxynitride (SiON), a silicon oxyfluoride (SiOF), an aluminum oxide (AlOx), and the like, or an organic insulating material, for example, and may be provided as a single layer or a multilayer that includes at least one of these materials. A contact hole1161that overlaps at least a part of the first data pad601is provided in the second gate insulation layer142and the interlayer insulation layer160. The contact hole1161may overlap a center portion of the first data pad601. The first auxiliary data pad671is provided on the interlayer insulation layer160. The first auxiliary data pad671is connected with the first data pad601through the contact hole1161. The first auxiliary data pad671covers the portion of the first data pad601, overlapping the contact hole1161. A circuit board410faces the substrate110, and a pad portion420is disposed under the circuit board410. A data driver is installed in the circuit board410, and the pad portion420is connected with the data driver. The circuit board410and the pad portion420provide an IC chip (refer toFIG.2). An anisotropic conductive film440is provided between the substrate110and the circuit board410. The anisotropic conductive film440is an adhesive film used for circuit connection, and has anisotropicity such that the anisotropic conductive film440is electrically conductive in one direction but is electrically insulated in the other direction. The anisotropic conductive film440includes an adhesive that is cured by heat and a micro-conductive particle450that is provided in the adhesive. When a pressure is applied to the anisotropic conductive film440at a high temperature, the conductivity particle450contacts the first auxiliary data pad671and the pad portion420of the IC chip (i.e., IC ofFIG.2), and accordingly, the first auxiliary data pad671and the pad portion420are electrically connected with each other. In addition, when the adhesive is cured, the substrate110and the circuit board410are physically connected with each other. Referring toFIGS.3and5, the second data pad602has a quadrangular shape in a plan view, and may substantially have a parallelogram shape, for example. Two sides of the parallelogram may be parallel with the first direction W1and the other two sides thereof may be parallel with the second direction W2. The shape of the second data pad602may be similar to that of the first data pad601. The second data pad602is disposed in a lower side of the first data pad601and may be adjacent to the first data pad601in the first direction W1. The second data pad602is connected with a second connection wire702and a second test wire902. The second connection wire702is directly connected with the second data pad602, and particularly, may be connected with an upper edge of the second data pad602. The second connection wire702may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W1. The second test wire902is directly connected with the second data pad602, and particularly, may be connected with a lower edge of the second data pad602. The second test wire902may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W1. The second data pad602, the second connection wire702, and the second test wire902are disposed in the same layer. The second data pad602is disposed in a different layer from that of the first data pad601, the first connection wire701, and the first test wire901. As shown inFIG.8, the buffer layer120is disposed on the substrate110, the gate insulation layer140is disposed on the buffer layer120, and the second data pad602is disposed on the gate insulation layer140. The second data pad602is disposed on the second gate insulation layer142. The interlayer insulation layer160is disposed on the second data pad602. The interlayer insulation layer160covers a part of the second data pad602, and particularly, covers an edge of the second data pad602. That is, the edge of the second data pad602may be disposed between the second gate insulation layer142and the interlayer insulation layer160. A contact hole1162that overlaps at least a part of the second data pad602is provided in the interlayer insulation layer160. The contact hole1162may contact a center portion of the second data pad602. A second auxiliary data pad672is disposed on the interlayer insulation layer160. The second auxiliary data pad672is connected with the second data pad602through the contact hole1162. The second auxiliary data pad672covers the portion of the second data pad602that is overlapped with the contact hole1162. Referring toFIGS.3and4, the plurality of data pads600may include a third data pad603that is disposed in the leftmost side in the third row. The third data pad603is disposed adjacent to the second data pad602along the first direction W1. The third data pad603may be disposed in a different layer from that of the second data pad602. The third data pad603is disposed in the shape of a quadrangle in a plan view, and may be substantially provided in the shape of a parallelogram, for example. Two sides of the parallelogram may be parallel with the first direction W1and the other two sides thereof may be parallel with the second direction W2. The shape of the third data pad603may be similar to that of the second data pad602. The third data pad603is disposed below the second data pad602, and may be adjacent to the second data pad602along the first direction W1. The third data pad603is connected with a third connection wire703and a third test wire903. The third connection wire703is directly connected with the third data pad603, and particularly may be connected with an upper edge of the third data pad603. The third connection wire703may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W1. The third test wire903is directly connected with the third data pad603, and particularly, may be connected with a lower edge of the third data pad603. The third test wire903may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W. The third data pad603, the third connection wire703, and the third test wire903are disposed in the same layer. The third data pad603may be disposed in the same layer as the first data pad601, the first connection wire701, and the first test wire901. The third data pad603is disposed in a different layer from that of the second data pad602, the second connection wire702, and the second test wire902. Referring toFIGS.3and5, the plurality of data pads600may further include a fourth data pad604that is disposed in the leftmost side of the fourth row. The fourth data pad604is disposed adjacent to the third data pad603along the first direction W1. The fourth data pad604may be disposed in a different layer from that of the third data pad603. The fourth data pad604has a quadrangular shape in a plan view, and may substantially provided in the shape of a parallelogram, for example. Two sides of the parallelogram may be parallel with the first direction W1and the other two sides thereof may be parallel with the second direction W2. The shape of the fourth data pad604may be similar to that of the third data pad603. The fourth data pad604is disposed below the third data pad603, and may be adjacent to the third data pad603along the first direction W1. The fourth data pad604is connected with a fourth connection wire704and a fourth test wire904. The fourth connection wire704is directly connected with the fourth data pad604, and particularly, may be connected with an upper edge of the fourth data pad604. The fourth connection wire704may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W1. The fourth test wire904is directly connected with the fourth data pad604, and particularly, may be connected with a lower edge of the fourth data pad604. The fourth test wire904may substantially extend in a vertical direction. The fourth data pad604, the fourth connection wire704, and the fourth test wire904are disposed in the same layer. The fourth data pad604may be disposed in the same layer as that of the second data pad602, the second connection wire702, and the second test wire902. The fourth data pad604is disposed in a different layer from that of the first data pad601, the first connection wire701, the first test wire901, the third data pad603, the third connection wire703, and the third test wire903. Referring toFIGS.3and4, the plurality of data pad600may further include a fifth data pad605that is disposed in the first row. The fifth data pad605is disposed adjacent to the first data pad601along the second direction W2. The fifth data pad605may be disposed in the same layer as that of the first data pad601. The fifth data pad605is provided in the shape of a quadrangle in a plan view, and may be substantially provided in the shape of a parallelogram, for example. Two sides of the parallelogram may be parallel with the first direction W1and the other two sides thereof may be parallel with the second direction W2. The shape of the fifth data pad605may be similar to that of the first data pad601. The fifth data pad605is disposed in the right side of the first data pad601, and may be adjacent to the first data pad601along the second direction W2. The fifth data pad605is connected with a fifth connection wire705and a fifth test wire905. The fifth connection wire705is directly connected with the fifth data pad605, and particularly may be connected with an upper edge of the fifth data pad605. The fifth connection wire705may substantially extend in the vertical direction. The fifth test wire905is directly connected with the fifth data pad605, and particularly, may be connected with a lower edge of the fifth data pad605. The fifth test wire905may have a plurality of bent portions, and may alternately extend in the vertical direction and the first direction W1. The fifth data pad605, the fifth connection wire705, and the fifth test wire905may be disposed in the same layer. The fifth data pad605may be disposed in the same layer as that of the first data pad601, the first connection wire701, and the first test wire901. Referring toFIGS.3to5, the plurality of data pads600may further include a sixth data pad606that is disposed in the second row, a seventh data pad607that is disposed in the third row, and an eighth data pad608that is disposed in the fourth row. The sixth data pad606is disposed adjacent to the fifth data pad605along the first direction W1. The seventh data pad607is disposed adjacent to the sixth data pad606along the first direction W1. The eighth data pad608is disposed adjacent to the seventh data pad607along the first direction W1. The sixth data pad606, the seventh data pad607, and the eighth data pad608are provided in the shape of a quadrangle in a plan view, respectively, and may be similar to the fifth data pad605in shape, for example. The sixth data pad606is directly connected with a sixth connection wire706and a sixth test wire906, and is disposed in the same layer as that of the sixth connection wire706and the sixth test wire906. The sixth data pad606is disposed in a different layer from that of the fifth data pad605, the fifth connection wire705, and the fifth test wire905. The seventh data pad607is directly connected with a seventh connection wire707and a seventh test wire907, and is disposed in the same layer as that of the seventh connection wire707and the seventh test wire907. The seventh data pad607may be disposed in the same layer as that of the fifth data pad605, the fifth connection wire705, and the fifth test wire905. The seventh data pad607is disposed in a different layer from that of the sixth data pad606, the sixth connection wire706, and the sixth test wire906. The eighth data pad608is directly connected with an eighth connection wire708and an eighth test wire908, and is disposed in the same layer as that of the eighth connection wire708and the eighth test wire908. The eighth data pad608may be disposed in the same layer as that of the sixth data pad606, the sixth connection wire706, and the sixth test wire906. The eighth data pad608is disposed in a different layer from that of the fifth data pad605, the fifth connection wire705, the fifth test wire905, the seventh data pad607, the seventh connection wire707, and the seventh test wire907. The data pads600that are disposed in the same rows are disposed in the same layers, respectively. In an exemplary embodiment, the plurality of data pads600that are disposed in the first row are disposed in the same layer, for example. The plurality of data pads600that are disposed in the second row are disposed in the same layer. The plurality of data pads600that are disposed in the third row are disposed in the same layer. The plurality of data pads600that are disposed in the fourth row are disposed in the same layer. The connection wires700and the test wires900that are connected with the respective data pads600are disposed in the same layer as that of the respective data pads600, and are directly connected therewith. Data pads600that are disposed in different rows that are adjacent to each other in the first direction W1are respectively disposed in different layers. In an exemplary embodiment, the data pad600disposed in the second row is disposed in a different layer from that of the data pad600that is disposed in the first row, for example. The data pad600disposed in the third row is disposed in a different layer from that of the data pad600that is disposed in the second row. The data pad600disposed in the fourth row is disposed in a different layer from that of the data pad600that is disposed in the third row. In this case, the data pad600disposed in the third row may be disposed in the same layer as that of the data pad600that is disposed in the first row. The data pad600disposed in the fourth row may be disposed in the same layer as that of the data pad600that is disposed in the second row. However, the invention is not limited thereto, and data pads600disposed in the first, second, third, and fourth rows may be respectively disposed in different layers. Three wires700and900are disposed between data pads600that are disposed in the same row and adjacent to each other in the second direction W2. In an exemplary embodiment, the second connection wire702, the third connection wire703, and the fourth connection wire704are disposed between the first data pad601and the fifth data pad605, for example. The third connection wire703, the fourth connection wire704, and the fifth test wire905are disposed between the second data pad602and the sixth data pad606. The fourth connection wire704, the fifth test wire905, and the sixth test wire906are disposed between the third data pad603and the seventh data pad607. The fifth test wire905, the sixth test wire906, and the seventh test wire907are disposed between the fourth data pad604and the eighth data pad608. The first data pad601and the second connection wire702are adjacent to each other, and the first data pad601and the second connection wire702may be applied with different voltages. Thus, a design that can prevent the first data pad601and the second connection wire702from being short-circuited is needed. When the first data pad601and the second connection wire702are disposed in the same layer, the first data pad601and the second connection wire702may be short-circuited. In order to prevent the short-circuit between the first data pad601and the second connection wire702, the first data pad601and the second connection wire702need to be disposed apart from each other with a wide gap. In the illustrated exemplary embodiment, the first data pad601and the second connection wire702are respectively disposed in different layers, and therefore the first data pad601and the second connection wire702are not short-circuited even though the gap between the first data pad601and the second connection wire702is reduced. The second connection wire702and the third connection wire703are adjacent to each other, and may be respectively applied with different voltages. Thus, a design that can prevent the second connection wire702and the third connection wire703from being short-circuited is needed. When the second connection wire702and the third connection wire703are disposed in the same layer, the second connection wire702and the third connection wire703may be short-circuited. In order to prevent the short-circuit, the second connection wire702and the third connection wire703are disposed apart from each other with a wide gap. In the illustrated exemplary embodiment, the second connection wire702and the third connection wire703are respectively disposed in different layers, and accordingly the second connection wire702and the third connection wire703are not short-circuited even though the gap between the second connection wire702and the third connection wire703is reduced. The third connection wire703and the fourth connection wire704are disposed adjacent to each other, and may be respectively applied with different voltages. Thus, a design that can prevent the third connection wire703and the fourth connection wire704from be short-circuited is needed. When the third connection wire703and the fourth connection wire704are disposed in the same layer, the third connection wire703and the fourth connection wire704may be short-circuited. In order to prevent the short-circuit, the third connection wire703and the fourth connection wire704are disposed apart from each other with a wide gap. In the illustrated exemplary embodiment, the third connection wire703and the fourth connection wire704are respectively disposed in different layers, and the third connection wire703and the fourth connection wire704are not short-circuited even though the gap therebetween is reduced. The fourth connection wire704and the fifth data pad605are adjacent to each other, and the fourth connection wire704and the fifth data pad605may be applied with different voltages. Accordingly, a design that can prevent the fourth connection wire704and the fifth data pad605from be short-circuited is needed. When the fourth connection wire704and the fifth data pad605are disposed in the same layer, the fourth connection wire704and the fifth data pad605may be short-circuited. In order to prevent the short-circuit, the fourth connection wire704and the fifth data pad605are disposed apart from each other with a wide gap. In the illustrated exemplary embodiment, the fourth connection wire704and the fifth data pad605are respectively disposed in different layers, and therefore the fourth connection wire704and the fifth data pad605are not short-circuited even though a distance therebetween is reduced. As described, in the illustrated exemplary embodiment, the data pads600and the wires700and900that are adjacent to each other are respectively disposed in different layers, and accordingly, distances between adjacent data pads600and the wires700and900can be reduced. A distance between the wires700and900may be reduced, and a distance between data pads600that are adjacent to each other in the second direction W2may be reduced. Accordingly, the area of the pad area AA can be reduced. Hereinabove, the data pad has been described, but the invention is not limited thereto. A similar structure may be applied to a gate pad as well. Next, a display area of a display device according to an exemplary embodiment will be described in detail with reference toFIGS.10to14. FIG.10is an equivalent circuit view of one pixel of a display device according to an exemplary embodiment. As shown inFIG.10, a display device according to the illustrated exemplary embodiment includes a plurality of signal lines151,152,153,171,172, and192and a plurality of pixels PX that are connected with the plurality of signal lines and substantially arranged in a matrix format. The respective pixels PX include a plurality of transistors T1, T2, T3, T4, T5, and T6that are connected with the plurality of signal lines151,152,153,171,172, and192, a storage capacitor Cst, and an OLED OLD. The transistors T1, T2, T3, T4, T5, and T6include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, and a light emission control transistor T6. The signal lines151,152,153,171,172, and192include a scan line151that transmits a scan signal Sn, a previous scan line152that transmits a previous scan signal Sn-1to the initialization transistor T4, a light emission control line153that transmits a light emission control signal EM to the operation control transistor T5and the light emission control transistor T6, a data line171that transmits a data signal Dm while crossing the scan line151, a driving voltage line172that transmits a driving voltage ELVDD and is provided substantially parallel with the data line171, and an initialization voltage line192that transmits an initialization voltage Vint for initialization of the driving transistor T1. A gate electrode G1of the driving transistor T1is connected with a first end Cst1of the storage capacitor Cst, a source electrode S1of the driving transistor T1is connected with the driving voltage line172via the operation control transistor T5, and a drain electrode D1of the driving transistor T1is electrically connected with an anode of the OLED OLD via the light emission control transistor T6. The driving transistor T1receives the data signal Dm according to a switching operation of the switching transistor T2, and supplies a driving current Id to the OLED OLD. A gate electrode G2of the switching transistor T2is connected with the scan line151, a source electrode S2of the switching transistor T2is connected with the data line171, and a drain electrode D2of the switching transistor T2is connected with the driving voltage line172via the operation control transistor T5while being connected with the source electrode S1of the driving transistor T1. The switching transistor T2is turned on according to the scan signal Sn received through the scan line151, and performs a switching operation to transmit the data signal Dm transmitted to the data line171to the source electrode S1of the driving transistor T1. A gate electrode G3of the compensation transistor T3is connected with the scan line151, a source electrode S3of the compensation transistor T3is connected with the anode of the OLED OLD via the light emission control transistor T6while being connected with the drain electrode D1of the driving transistor T1, and a drain electrode D3of the compensation transistor T3is connected with a drain electrode D4of the initialization transistor T4, the first end Cst1of the capacitor Cst, and the gate electrode G1of the driving transistor T1. The compensation transistor T3is turned on according to the scan signal Sn received through the scan line151, and diode-connects the driving transistor T1by connecting the gate electrode G1and the drain electrode D1of the driving transistor T1to each other. A gate electrode G4of the initialization transistor T4is connected with the previous scan line152, a source electrode S4of the initialization transistor T4is connected with the initialization voltage line192, and a drain electrode D4of the initialization transistor T4is connected with the first end Cst1of the capacitor Cst and the gate electrode G1of the driving transistor T1through the drain electrode D3of the compensation transistor T3. The initialization transistor T4is turned on according to the previous scan signal Sn-1received through the previous scan line152, and performs an initialization operation to initialize a gate voltage of the gate electrode G1of the driving transistor T1by transmitting the initialization voltage Vint to the gate electrode G1of the driving transistor T1. A gate electrode G5of the operation control transistor T5is connected with the light emission control line153, a source electrode S5of the operation control transistor T5is connected with the driving voltage line172, and a drain electrode D5of the operation control transistor T5is connected with the source electrode S1of the driving transistor T1and the drain electrode D2of the switching transistor T2. A gate electrode G6of the light emission control transistor T6is connected with the light emission control line153, a source electrode S6of the light emission control transistor T6is connected with the drain electrode D1of the driving transistor T1and the source electrode S3of the compensation transistor T3, and a drain electrode D6of the light emission control transistor T6is electrically connected with the anode of the OLED OLD. The operation control transistor T5and the light emission control transistor T6are simultaneously turned on according to the light emission control signal EM received through the light emission control line153such that the driving voltage ELVDD is compensated by the diode-connected driving transistor T1and then connected to the OLED OLD. A second end Cst2of the storage capacitor Cst is connected with the driving voltage line172, and a cathode of the OLED OLD is connected with a common voltage line741that transmits a common voltage ELVSS. A detailed structure of the display device according to the exemplary embodiment ofFIG.10will now be described with reference toFIGS.11,12,13, and14, together withFIG.10. FIG.11is a schematic plan view of the plurality of transistors and the capacitor of the display device according to the exemplary embodiment,FIG.12is a detailed plan view ofFIG.11,FIG.13is a cross-sectional view ofFIG.12, taken along line XIII-XIII, andFIG.14is a cross-sectional view ofFIG.12, taken along line XIV-XIV. Hereinafter, a detailed planar structure of the display device according to the exemplary embodiment will be described with reference toFIG.11, and then the detailed planar structure will be further described with reference toFIGS.13and14. The display device according to the exemplary embodiment includes the scan line151, the previous scan line152, and the light emission control line153that respectively apply the scan signal Sn, the previous scan signal Sn-1, and the light emission control signal EM and are disposed along a row direction. In addition, the display device includes the data line171and the driving voltage line172that cross the scan line151, the previous scan line152, and the light emission control line153and apply the data signal Dm and the driving voltage ELVDD, respectively. The initialization voltage Vint is transmitted to the compensation transistor T3from the initialization voltage line192via the initialization transistor T4. The initialization voltage line192includes straight lines and oblique lines that are alternately provided. In addition, each pixel PX includes the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistors T4, the operation control transistor T5, the light emission control transistor T6, the storage capacitor Cst, and the OLED OLD. The OLED OLD includes a pixel electrode191, an organic emission layer370, and a common electrode270. Channels of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, the operation control transistor T5, and the light emission control transistor T6are respectively provided in one connected semiconductor layer130, and the semiconductor layer130may be bent in various shapes. In an exemplary embodiment, the semiconductor layer130may include a polysilicon or an oxide semiconductor, for example. A channel131includes a driving channel131aprovided in the driving transistor T1, a switching channel131bprovided in the switching transistor T2, a compensation channel131cprovided in the compensation transistor T3, an initialization channel131dprovided in the initialization transistor T4, an operation control channel131eprovided in the operation control transistor T5, and a light emission control channel131fprovided in the light emission control channel131f. The driving transistor T1includes the driving channel131a, a driving gate electrode155a, a driving source electrode136a, and a driving drain electrode137a. The driving gate electrode155aoverlaps the driving channel131a, and the driving source electrode136aand the driving drain electrode137aare adjacent to opposite sides of the driving channel131a. The driving gate electrode155ais connected with a first data connection member174through a contact hole61. The switching transistor T2includes the switching channel131b, a switching gate electrode155b, a switching source electrode136b, and a switching drain electrode137b. The switching gate electrode155bthat is a part of the scan line151, expanding downward, overlaps the switching channel131b, and the switching source electrode136band the switching drain electrode137bare adjacent to opposite sides of the switching channel131b. The switching source electrode136bis connected with the data line171through a contact hole62. The compensation transistor T3includes the compensation channel131c, a compensation gate electrode155c, a compensation source electrode136c, and a compensation drain electrode137c. The compensation gate electrode155cthat is a part of the scan line151overlaps the compensation channel131c. The compensation source electrode136cand the compensation drain electrode137care adjacent to opposite sides of the compensation channel131c. The compensation drain electrode137cis connected with the first data connection member174through a contact hole63. The initialization transistor T4includes the initialization channel131d, an initialization gate electrode155d, an initialization source electrode136d, and an initialization drain electrode137d. In order to prevent a leakage current, two initialization gate electrodes155d, each a part of the previous scan line152, are provided, and the two initialization gate electrodes155doverlap the initialization channel131d. The initialization source electrode136dand the initialization drain electrode137dare adjacent to opposite sides of the initialization channel131d. The initialization source electrode136dis connected with a second data connection member175through a contact hole64. The operation control transistor T5includes the operation control channel131e, an operation control gate electrode155e, an operation control source electrode136e, and an operation control drain electrode137e. The operation control gate electrode155ethat is a part of the light emission control line153overlaps the operation control channel131e, and the operation control source electrode136eand the operation control drain electrode137eare adjacent to opposite sides of the operation control channel131e. The operation control source electrode136eis connected with a part expanded from the driving voltage line172through a contact hole65. The light emission control transistor T6includes the light emission control channel131f, a light emission control gate electrode155f, a light emission control source electrode136f, and a light emission control drain electrode137f. The light emission control gate electrode155fthat is a part of the light emission control line153overlaps the light emission control channel131f, and the light emission control source electrode136fand the light emission control drain electrode137fare adjacent to opposite sides of the light emission control channel131f. The light emission control drain electrode137fis connected with a third data connection member179through a contact hole66. A first end of the driving channel131aof the driving transistor T1is connected with the switching drain electrode137band the operation control drain electrode137e, and a second end of the driving channel131ais connected with the compensation source electrode136cand the light emission control source electrode136f. The storage capacitor Cst includes a first storage electrode155aand a second storage electrode156that are disposed interposing the second gate insulation layer142therebetween. The first storage electrode155acorresponds to the driving gate electrode155a, and the second storage electrode156is a portion expanded from a storage line157and fully covers the driving gate electrode155awhile occupying a wider area than the driving gate electrode155a. The second gate insulation layer142may be a dielectric material, and storage capacitance is determined by charges charged in the storage capacitor Cst and a voltage between the two storage electrodes155aand156. As described, since the driving gate electrode155ais used as the first storage electrode155a, a space for providing the storage capacity in a space that is narrowed due to the driving channel131athat occupies a wide area in the pixel can be assured. The first storage electrode155a, which is the driving gate electrode155a, is connected with a first end of the first data connection member174through the contact hole61and a storage opening51. The storage opening51is an opening defined in the second storage electrode156. Thus, the contact hole61through which the first end of the first data connection member174and the driving gate electrode155aconnect with each other is defined in the storage opening51. The first data connection member174is provided in the same layer as that of the data line171so as to be substantially parallel with the data line171, and a second end of the first data connection member174is connected with the compensation drain electrode137cof the compensation transistor T3and the initialization drain electrode137dof the initialization transistor T4through the contact hole63. Thus, the first data connection member174connects the driving gate electrode155awith the compensation drain electrode137cof the compensation transistor T3and the initialization drain electrode137dof the initialization transistor T4. Therefore, the storage capacitor Cst stores storage capacitance that corresponds to a difference between the driving voltage ELVDD transmitted to the second storage electrode156through the driving voltage line172and a driving gate voltage of the driving gate electrode155a. The third data connection member179is connected with the pixel electrode191through a contact hole81, and the second data connection member175is connected with the initialization voltage line192through a contact hole82. Hereinafter, a cross-sectional structure of the display device according to the illustrated exemplary embodiment will be described in detail according to the stacking order. A buffer layer120is provided on a substrate110. The semiconductor layer130that includes the channel131including the driving source electrode136a, the switching channel131b, the compensation channel131c, the initialization channel131d, the operation control channel131e, and the light emission control channel131fis provided on the buffer layer120. In the semiconductor layer130, the driving source electrode136aand the driving drain electrode137aare disposed at opposite sides of the driving channel131a, and the switching source electrode136band the switching drain electrode137bare disposed at opposite sides of the switching channel131b. In addition, the compensation source electrode136cand the compensation drain electrode137care disposed at opposite sides of the compensation channel131c, and the initialization source electrode136dand the initialization drain electrode137dare disposed at opposite sides of the initialization channel131d. Further, the operation control source electrode136eand the operation control drain electrode137eare disposed at opposite sides of the operation control channel131e, and the light emission control source electrode136fand the light emission control drain electrode137fare disposed at opposite sides of the light emission control channel131f. The first gate insulation layer141that covers the semiconductor layer130is provided on the semiconductor layer130. First gate wires151,152,153,155a,155b,155c,155d,155e, and155fthat include the scan line151including the switching gate electrode155band the compensation gate electrode155c, the previous scan line152including the initialization gate electrode155d, the light emission control line153including the operation control gate electrode155eand the light emission control gate electrode155f, and the driving gate electrode (i.e., the first storage electrode)155aare disposed on the first gate insulation layer141. The first data pad601(refer toFIG.3), the third data pad603, the fifth data pad605, and the seventh data pad607that are disposed in the above-described pad area IC ofFIG.1may be disposed in the same layer as that of the first gate wires151,152,153,155a,155b,155c,155d,155e, and155f. In addition, the first data pad601, the third data pad603, the fifth data pad605, and the seventh data pad607may include the same material as that of the first gate wires151,152,153,155a,155b,155c,155d,155e, and155f. A metallic material is deposited on the first gate insulation layer141and then patterned such that the first gate wires151,152,153,155a,155b,155c,155d,155e, and155f, the first data pad601ofFIG.3, the third data pad603ofFIG.3, the fifth data pad605ofFIG.3, and the seventh data pad607ofFIG.3can be simultaneously provided. The second gate insulation layer142is disposed on the first gate wires151,152,153,155a,155b,155c,155d,155e, and155fand the first gate insulation layer141to cover the same. The first gate wires151,152,153,155a,155b,155c,155d,155e, and155fare disposed between the first gate insulation layer141and the second gate insulation layer142. Second gate wires157and156that include the storage line157that is disposed in parallel with the scan line151and the second storage electrode156that is a portion expanded from the storage line156are disposed on the second gate insulation layer142. The second data pad602ofFIG.3, the fourth data pad604ofFIG.3, the sixth data pad606ofFIG.3, and the eighth data pad608ofFIG.3that are disposed in the above-described pad area IC ofFIG.1may be disposed in the same layer as that of the second gate wires157and156. In addition, the second data pad602, the fourth data pad604, the sixth data pad606, and the eighth data pad608may include the same material as that of the second gate wires157and156. A metallic material is deposited on the second gate insulation layer142and then patterned such that the second gate wires157and156, the second data pad602, the fourth data pad604, the sixth data pad606, and the eighth data pad608can be simultaneously provided. An interlayer insulation layer160is provided on the second gate insulation layer142and the second gate wires157and156. The contact holes61,62,63,64,65, and66that expose at least a part of an upper surface of the semiconductor layer130are defined in the interlayer insulation layer160. Data wires171,172,174,175, and179that include the data line171, the driving voltage line172, the first data connection member174, the second data connection member175, and the third data connection member179are disposed on the interlayer insulation layer160. The first auxiliary data pad671and the second auxiliary data pad672(refer toFIG.3) that are disposed in the above-described pad area IC ofFIG.1may be disposed in the same layer as that of the data wires171,172,174,175, and179. In addition, the first auxiliary data pad671and the second auxiliary data pad672may include the same material as that of the data wires171,172,174,175, and179. A metallic material is deposited on the interlayer insulation layer160and then patterned such that the data wires171,172,174,175, and179, the first auxiliary data pad671, and the second auxiliary data pad672can be simultaneously provided. The data line171is connected with the switching source electrode136bthrough the contact hole62. A first end of the first data connection member174is connected with the first storage electrode155athrough the contact hole61, and a second end of the first data connection member174is connected with the compensation drain electrode137cand the initialization drain electrode137dthrough the contact hole63. The second data connection member175that extends in parallel with the data line171is connected with the initialization source electrode136dthrough the contact hole64. The third data connection member179is connected with the light emission control drain electrode137fthrough the contact hole66. A passivation layer180is disposed on the data wires171,172,174,175, and179and the interlayer insulation layer160to cover the same. The pixel electrode191and the initialization voltage line192are disposed on the passivation layer180. The third data connection member179is connected with the pixel electrode191through a contact hole81defined in the passivation layer180, and the second data connection member175is connected with the initialization voltage line192through a contact hole82defined in the passivation layer180. A pixel defining layer350that covers the passivation layer180, the initialization voltage line192, and an edge of the pixel electrode191is provided on the passivation layer180, the initialization voltage line192, and the edge of the pixel electrode191, and a pixel opening351that exposes the pixel electrode191is defined in the pixel defining layer350. An organic emission layer370is disposed on the pixel electrode191that is exposed by the pixel opening351, and a common electrode270is provided on the organic emission layer370. The common electrode270is disposed on the pixel defining layer350and thus disposed over the plurality of pixels PX (refer toFIGS.1and10). As described, the OLED OLD that includes the pixel electrode191, the organic emission layer370, and the common electrode270is provided. Next, a display device according to another exemplary embodiment will be described with reference toFIG.15. A display device according to an exemplary embodiment ofFIG.15is substantially the same as the display device according to the exemplary embodiment ofFIGS.1to14, and therefore no duplicated description will be provided. The exemplary embodiment ofFIG.15is different from the above-exemplary embodiment ofFIGS.1to14in that a data pad and a connection wire overlap each other or adjacent connection wires overlap each other, and this will be described in further detail. FIG.15is a cross-sectional view of a display device according to an exemplary embodiment. As shown inFIG.15, a second connection wire702, a third connection wire703, and a fourth connection wire704are provided between a first data pad601and a fifth data pad605. In the above described exemplary embodiment ofFIG.9, the first data pad601and the second connection wire702that are adjacent each other do not overlap each other, and the second connection wire702and the third connection wire703that are adjacent to each other do not overlap each other. Further, the adjacent third and fourth connection wires703and704do not overlap each other, and the fourth connection wire704and the fifth data pad605that are adjacent to each other do not overlap each other. However, in the illustrated exemplary embodiment ofFIG.15, the first data pad601and the second connection wire702that are adjacent to each other may overlap each other. The second connection wire702and the third connection wire703that are adjacent to each other may overlap each other. The third connection wire703and the fourth connection wire704that are adjacent to each other may overlap each other. The fourth connection wire704and the fifth data pad605that are adjacent each other may overlap each other. In the illustrated exemplary embodiment, a data pad and a connection wire700that are adjacent to each other may be overlapped with each other because they have no possibility of being short-circuited. Further, adjacent connection wires700have no possibility of being short-circuited because adjacent connection wires700are respectively disposed in different layers, and accordingly, may be overlapped with each other. Next, a display device according to an exemplary embodiment will be described with reference toFIGS.16and17. A display device according to an exemplary embodiment ofFIGS.16and17is substantially the same as the display device according to the exemplary embodiment ofFIGS.1to14, and therefore no duplicated description will be provided. The illustrated exemplary embodiment ofFIGS.16and17is different from the exemplary embodiment ofFIGS.1to14in that a plurality data pads are arranged in three rows, and this will be described in detail. FIG.16is a top plan view that partially illustrates a pad area of a display device according to an exemplary embodiment, andFIG.17is a cross-sectional view ofFIG.16, taken along line XVII-XVII. As shown inFIGS.16and17, a plurality of data pads1600may be aligned along a first direction W1and a second direction W2in the pad area of the display device. In this case, the plurality of data pads1600may be aligned in three rows. The plurality of data pads1600include a first data pad1601and a fourth data pad1604that are disposed in the first row, a second data pad1602and a fifth data pad1605that are disposed in the second row, and a third data pad1603and a sixth data pad1606that are disposed in the third row. The first data pad1601and the second data pad1602are disposed adjacent to each other along the first direction W1, and they are respectively disposed in different layers. The second data pad1602and the third data pad1603are disposed adjacent to each other along the first direction W1, and they are respectively disposed in different layers. The third data pad1603may be disposed in the same layer as that of first data pad1601. The first data pad1601is connected with a first connection wire1701and a first test wire1901, and they are disposed in the same layer. The second data pad1602is connected with a second connection wire1702and a second test wire1902, and they are disposed in the same layer. The third data pad1603is connected with a third connection wire1703and a third test wire1903, and they are disposed in the same layer. The first data pad1601and the fourth data pad1604are disposed adjacent to each other along the second direction W2, and they are disposed in the same layer. The fourth data pad1604and the fifth data pad1605are disposed adjacent to each other, and they are respectively disposed in different layers. The fifth data pad1605and the sixth data pad1606are disposed adjacent to each other along the first direction W1, and they are respectively disposed in different layers. The sixth data pad1606and the fourth data pad1604may be disposed in the same layer. The fourth data pad1604is connected with a fourth connection wire1704and a fourth test wire1904, and they are disposed in the same layer. The fifth data pad1605is connected with a fifth connection wire1705and a fifth test wire1905, and they are disposed in the same layer. The sixth data pad1606is connected with a sixth connection wire1706and a sixth test wire1906, and they are disposed in the same layer. Two wires1700and1900are disposed between the pads1600that are disposed adjacent to each other in the second direction W2in the same row. In an exemplary embodiment, the second connection wire1702and the third connection wire1703are disposed between the first data pad1601and the fourth data pad1604, for example. The third connection wire1703and the fourth test wire1904are disposed between the second data pad1602and the fifth data pad1605. The fourth test wire1904and the fifth test wire1905are disposed between the third data pad1603and the sixth data pad1606. Since the first data pad1601and the second connection wire1702are respectively disposed in different layers, the first data pad1601and the second connection wire1702are not short-circuited even though a distance therebetween is reduced. Since the second connection wire1702and the third connection wire1703are respectively disposed in different layers, the second connection wire1702and the third connection wire1703are not short-circuited even though a distance therebetween is reduced. Since the third connection wire1703and the fourth data pad1604are respectively disposed in different layers, the third connection wire1703and the fourth data pad1604are not short-circuited even though a distance therebetween is reduced. A second gate insulation layer142and an interlayer insulation layer160are provided on the first data pad1601. A contact hole11161that overlaps at least a part of the first data pad1601is provided in the second gate insulation layer142and the interlayer insulation layer160. The contact hole11161may overlap a center portion of the first data pad1601. A first auxiliary data pad1671is provided on the interlayer insulation layer160. The first auxiliary data pad1671is connected with the first data pad1601through the contact hole11161. The first auxiliary data pad1671covers a portion of the first data pad1601through the contact hole11161. It is illustrated that the first auxiliary data pad1671overlaps the second connection wire1702. However, the invention is not limited thereto, and the first auxiliary data pad1671may not overlap the second connection wire1702. Next, a display device according to an exemplary embodiment ofFIGS.18and19will be described. A display device according to an exemplary embodiment ofFIGS.18and19is substantially the same as the display device according to the exemplary embodiment ofFIGS.1to14, and therefore no duplicated description will be provided. The illustrated exemplary embodiment ofFIGS.18and19is different from the exemplary embodiment ofFIGS.1to14in that a plurality data pads are arranged in two rows, and this will be described in detail. FIG.18is a top plan view that partially illustrates a pad area of a display device according to an exemplary embodiment, andFIG.19is a cross-sectional view ofFIG.18, taken along line XIX-XIX. As shown inFIGS.18and19, a plurality of data pads2600are arranged in a first direction W1and a second direction W2in the pad area of the display device. In this case, the plurality of data pads2600may be arranged in two rows. The plurality of data pads2600include a first data pad2601and a third data pad2603that are disposed in the first row, and a second data pad2062and a fourth data pad2604that are disposed in the second row. The first data pad2601and the second data pad2602are disposed adjacent to each other along the first direction W1, and they are respectively disposed in different layers. The first data pad2601is connected with a first connection wire2701and a first test wire2901, and they are disposed in the same layer. The second data pad2602is connected with a second connection wire2702and a second test wire2902, and they are disposed in the same layer. The first data pad2601and the third data pad2603are disposed adjacent to each other along the second direction W2, and they are disposed in the same layer. The third data pad2603and the fourth data pad2604are disposed adjacent to each other along the first direction W1, and they are respectively disposed in different layers. The third data pad2603is connected with a third connection wire2703and a third test wire2903, and they are disposed in the same layer. The fourth data pad2604is connected with a fourth connection wire2704and a fourth test wire2904, and they are disposed in the same layer. One wire2700or2900is disposed between data pads2600that are disposed adjacent to each other along the second direction W2in the same row. In an exemplary embodiment, the second connection wire2702is disposed between the first data pad2601and the third data pad2603, for example. The third test wire2903is disposed between the second data pad2602and the fourth data pad2604. Since the first data pad2601and the second connection wire2702are respectively disposed in different layers, the first data pad2601and the second connection wire2702are not short-circuited even though a distance therebetween is reduced. Since the second connection wire2702and the third data pad2603are respectively disposed in different layers, the second connection wire2702and the third data pad2603are not short-circuited even though a distance therebetween is reduced. A second gate insulation layer142and an interlayer insulation layer160are provided on the first data pad2601. A contact hole21161that overlaps at least a part of the first data pad2601is provided in the second gate insulation layer142and the interlayer insulation layer160. The contact hole21161may overlap a center portion of the first data pad2601. A first auxiliary data pad2671is disposed on the interlayer insulation layer160. The first auxiliary data pad2671is connected with the first data pad2601through the contact hole21161. The first auxiliary data pad2671covers a portion of the first data pad2601, overlapping the contact hole21161. It is illustrated that the first auxiliary data pad2671overlaps the second connection wire2702. However, the invention is not limited thereto, and the first auxiliary data pad2671may not overlap the second connection wire2702. While this invention has been described in connection with what is presently considered to be practical example embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. | 71,365 |
11862646 | DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS In order to make those skilled in the art better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments. The inventors of the present disclosure have found that, generally, the pin region of the display panel is smaller than the display region of the display panel. The wiring in the pin region is relatively limited, and the phenomena, such as too small distance between signal lines, or cross wiring of the signal lines, etc. exist. In this case, parasitic capacitance is generated, and the accuracy of the control signals in the signal lines is affected due to noise, and thus the performance of the display panel is affected too. The present disclosure provides a base substrate, a touch display panel and a display panel, which are intended to solve at least a part of the above technical problems of the related art. The technical solution of the present disclosure will be illustrated in combination with embodiments in detail below. FIG.1is a schematic diagram showing a structure of a display substrate according to an embodiment of the present disclosure. As shown inFIG.1, the display substrate100has a display region100aand a pin region100b. As shown inFIG.2, the display substrate100includes a base substrate10, at least two types of signal lines130, and a DC conductive structure120. The at least two types of signal lines130extend from the pin region100bto the display region100a. In an embodiment, in the pin region100b, the DC conductive structure120is disposed between any two types of signal lines130, and each of the any two types of signal lines130is spaced apart from the DC conductive structure120. In the embodiment, in the pin region100bof the display substrate100, the DC conductive structure120is disposed between the first signal lines131and the second signal lines132. After a constant DC voltage (e.g., VDD DC voltage), which is equivalent to a reference potential, is supplied to the DC conductive structure120, a stable electric field can be formed, and the DC potential is too strong to be easily disturbed. Therefore, the pulse signals in the first signal lines131and the second signal lines132separated by the DC conductive structure120have a stable reference potential of the DC potential, so as to effectively reduce the parasitic influence between the first signal lines131and the second signal lines132, that is, to prevent the possible mutual interference between the first signal lines131and the second signal lines132. Therefore, the precision of signal transmitted in the pin region100bwith a limited space can be optimized, and the performance of the device can be improved. In an embodiment, the at least two types of signal lines130may include at least one first signal line131, at least one second signal line132. . . , and at least one Nth signal line, i.e., the signal lines130for transmitting different pulse signals. The pulse signals may include a display data signal and a touch data signal. It is understood that the signal line130for transmitting the display data signal is the display data signal line130, and the signal line130for transmitting the touch data signal is the touch data signal line130. The inventors of the present disclosure have found that non-negligible signal interference exists in the display region100aof the display substrate100. To this end, the present disclosure provides an implementation for the display substrate100as follows. As shown inFIGS.2to4, in the display region100a, the DC conductive structure120is disposed between two types (i.e., any two types) of signal lines130of the at least two types of signal lines130, and any one of the two types (i.e., any two types) of signal lines130is spaced apart from the DC conductive structure120. In the present embodiment, in the display region100aof the display substrate100, the DC conductive structure120is disposed between the first signal lines131and the second signal lines132. After a DC voltage (e.g., VDD DC voltage), which is equivalent to a reference potential, is supplied into the DC conductive structure120, a stable electric field can be formed, and the DC potential is too strong to be easily disturbed. Therefore, the pulse signals in the first signal lines131and the second signal lines132separated by the DC conductive structure120have a stable reference potential of the DC potential, so as to effectively reduce the parasitic influence between the first signal lines131and the second signal lines132, that is, to prevent the possible mutual interference between the first signal lines131and the second signal lines132. Therefore, the precision of signal transmitted in the display region100aof the display substrate100, and the performance of the device can be improved. The present disclosure is particularly suitable for devices having a high wiring density in the display region100a, such as a small display panel and an ultra-clear display panel. In an embodiment, the display region100aof the display substrate100corresponds to a display region of a display panel. Alternatively, the display region100aof the display substrate100corresponds to a touch display region of a touch display panel. The inventors of the present disclosure consider that when the signal lines130are wired arbitrarily, phenomena such as cross wiring occur and the probability of mutual interference increases. As such, in an embodiment, as shown inFIGS.2to4, according to the display substrate100in the embodiment of the present disclosure, the at least two types of signal lines130are disposed in parallel. The first signal lines131and the second signal lines132may be of the same type, such as data lines. That is, the DC conductive structure is disposed between two data lines. In an embodiment, the first signal lines131and the second signal lines132may be of two different types, such as data lines and gate lines. That is, the DC conductive structure is disposed between one data line and one gate line. In the embodiment, in the pin region100band/or the display region100aof the display substrate100, the signal lines130are disposed in parallel, so that the phenomenon such as crossing wiring can be reduced, the possible mutual interference between the two types of signal lines130can be reduced, and the utilization rate of the wiring space can be improved too. In an embodiment, as shown inFIG.2, the first signal lines131of the at least two types of signal lines130are located in a first layer111of the display substrate100, the second signal lines132of the at least two types of signal lines130are located in a third layer113of the display substrate100, and the DC conductive structure120is located in a second layer112of the display substrate100. The first layer111, the second layer112, and the third layer113are three different layers. The second layer112is located between the first layer111and the third layer113. In the embodiment, the first signal lines131, the second signal lines132and the DC conductive structure120are respectively located in three different layers stacked along a direction perpendicular to the base substrate10, and the DC conductive structure120spaces the first signal lines131apart from the second signal lines132along a thickness direction of the display substrate100to shield the first signal lines131and the second signal lines132. This arrangement is suitable for a device with many layers. In an embodiment, the at least one first signal line131may include at least one signal line of the same type, and the at least one second signal line132may include at least one signal line of the same type. As shown inFIGS.2,3, and4,FIG.2shows that the first signal lines131and the second signal lines132each include six signal lines of the same type,FIG.3shows that the first signal lines131include three signal lines of the same type, and the second signal lines132include four signal lines of the same type. In the embodiment, as shown inFIG.2, the at least one first signal line includes a plurality of first signal lines, the at least one second signal line includes a plurality of second signal lines, and the DC conductive structure120may be a planar conductive structure, so that an orthogonal projection of the DC conductive structure120on the base substrate10, an orthogonal projection of the at least one first signal line131on the base substrate10, and an orthogonal projection of the at least one second signal line line132on the base substrate10may overlap each other. A width of the DC conductive structure120may be substantially equal to a distance from a first one to a last one of the plurality of first signal lines sequentially arranged. The width of the DC conductive structure120may be substantially equal to a distance from a first one to a last one of the plurality of second signal lines sequentially arranged. However, the number of signal lines is not limited thereto, and the at least one first signal line131or the at least one second signal line132may include only one signal line. As shown inFIG.2, in the display region100aand/or the pin region100b, an extension direction of the first signal lines131, an extension direction of the second signal lines132, and an extension direction of the DC conductive structure120are parallel to each other. The DC conductive structure120is disposed between the first signal lines131and second signal lines132. The orthographic projections of the first signal lines131on the base substrate10, the orthographic projection of the DC conductive structure120on the base substrate10, and the orthographic projections of the second signal lines132on the base substrate10overlap each other. In an embodiment, in the display region100aand/or the pin region100b, the DC conductive structure120is disposed between the first signal lines131and second signal lines132in an intersection region where the first signal lines131and second signal lines132cross over each other. In the intersection region, the orthogonal projections of the first signal lines131on the base substrate10, the orthogonal projection of the DC conductive structure120on the base substrate10, and the orthogonal projections of the second signal lines132on the base substrate10overlap each other. In an embodiment, as shown inFIG.3, all of the first signal lines131and second signal lines132and the DC conductive structure120are located in the same layer, i.e., are covered by the same insulation layer. In the embodiment, the first signal lines131, the second signal lines132and the DC conductive structure120are located in the same layer. The DC conductive structure120spaces the first signal lines131apart from the second signal lines132along a direction parallel of the display substrate100so as to shield the first signal lines131from the second signal lines132. This arrangement is beneficial to thinning of the device. As shown inFIG.3, in the display region100aand/or the pin region100b, the extension direction of the first signal lines131, the extension direction of the second signal lines132, and the extension direction of the DC conductive structure120are parallel to each other. It is understood that an insulation process is performed on the first signal lines131, the second signal lines132and the DC conductive structure120. For example, an insulation structure (i.e., an insulation layer) for insulating the signal lines130from the DC conductive structure120is formed. In an embodiment, as shown inFIG.4, the DC conductive structure120includes a first DC conductive structure121and a second DC conductive structure122. The first DC conductive structure is disposed between any two types of signal lines. The first signal lines131, second signal lines132, and the first DC conductive structure121are all located in a fourth layer114of the display substrate100, and the second DC conductive structure122is located in a fifth layer115of the display substrate100. The second DC conductive structure122is located on a side of the first DC conductive structure121, the first signal lines131, and the second signal lines131and132away from the base substrate10. The first DC conductive structure121and the second DC conductive structure122are electrically connected to each other through a via hole160. An orthogonal projection of the second DC conductive structure122on the fourth layer114or the base substrate10at least covers an orthogonal projection of the first DC conductive structure121on the base substrate10and covers the orthogonal projections, on the base substrate10, of the first signal lines131and second signal lines132adjacent to the first DC conductive structure121. In the embodiment, the first DC conductive structure121, the first signal lines131, and the second signal lines132are located in the fourth layer114of the display substrate100. The first DC conductive structure121separates the first signal lines131from the second signal lines132to shield the first signal lines131and the second signal lines132. The second DC conductive structure122is located in the fifth layer115of the display substrate100, and the first DC conductive structure121and the second DC conductive structure122are electrically connected to each other through the via hole160, that is, the first DC conductive structure121has the same potential as the second DC conductive structure122. The second DC conductive structure122extends along a direction parallel to the display substrate100, so as to wrap, together with the first DC conductive structure121, the first signal lines131and the second signal lines132, thereby enhancing the shielding effect for the first signal lines131and the second signal lines132. In an embodiment, an orthogonal projection of the second DC conductive structure122on the base substrate10covers an orthogonal projection of the first DC conductive structure121on the base substrate10and covers the orthogonal projections of the first signal lines13and second signal lines132on the base substrate10. The extension direction of the first signal lines131, the extension direction of the second signal lines132, and the extension direction of the first DC conductive structure121are parallel to each other. In an embodiment, one terminal of the DC conductive structure120is grounded. In the embodiment, the DC conductive structure120is grounded, so as to guide an external interference signal to the ground, thereby preventing the interference signal from entering the signal lines130, preventing the interference signal from interfering the control signals in the signal lines130, and thus avoiding the loss of the control signals. In an embodiment, the DC conductive structure120has a metal structure made of Ti/Al/Ti. That is, the DC conductive structure120has a metal structure in which Ti (titanium)/Al (aluminum)/Ti are stacked. Based on the same inventive concept, an embodiment of the present disclosure provides a touch display panel, including: any one of the display substrates100in the above embodiments. The display substrate100includes a gate layer, a source-drain electrode layer, and a touch sense layer stacked on the base substrate10. The first signal lines131of the at least two types of signal lines130of the display substrate100are located in the gate layer111. The second signal lines132of the at least two types of signal lines130of the display substrate100are located in the touch sense layer113. The DC conductive structure120of the display substrate100is located in the source-drain electrode layer112. In the embodiment, the display device includes the display panel provided in the foregoing embodiments, and reference may be made to the foregoing embodiments for the principle and technical effect, which will not described herein again. In an embodiment, the first signal lines131of the at least two types of signal lines130of the display substrate100are display data signal lines, and the second signal lines132of the at least two types of signal lines130of the display substrate100are touch data signal lines. The DC conductive structure120of the display substrate100is a power supply structure for supplying power to the touch display panel, and the DC conductive structure120is connected to a constant DC voltage VDD of the touch display panel. Specifically, the display data signal lines131may be made of molybdenum, and the touch data signal lines132may be made of Ti/Al/Ti. Based on the same inventive concept, an embodiment of the present disclosure provides a display panel including: the display substrate100provided in any one of the above embodiments. The display substrate100includes a buffer layer, an interlayer insulation layer, a source-drain electrode layer, and a planarization layer stacked on the base substrate10. The at least two types of signal lines131and132and the DC conductive structure120of the display substrate100are located in the source-drain electrode layer111. In the embodiment, the display device includes the display panel provided in the foregoing embodiments, and reference can be made to the foregoing embodiments for the principle and technical effect, which will not be described herein again. In an embodiment, the at least two types of signal lines130of the display substrate100include at least two of the gate lines130, the initialization signal lines130(which are input signal lines (sty) of the GOA driving circuit), the data signal lines130, and reset signal lines130. The DC conductive structure120is a power supply structure of the display panel, and the DC conductive structure120is connected to a constant DC voltage VDD of the display panel. According to an embodiment of the present invention, a method for manufacturing a display substrate is provided. The display substrate has a display region100aand a pin region100bon a side of the display region. The method includes: forming a first signal line131and a second signal line132extending from the pin region100bto the display region100aon a side of the base substrate10; forming a DC conductive structure120between the first signal line131and second signal line132, such that each of the first and second signal lines131and132is spaced apart from the DC conductive structure120, the DC conductive structure120being connected to a constant DC voltage. The first signal line131, the second signal line132, and the DC conductive structure120are respectively formed in three different layers stacked along a direction perpendicular to the base substrate10, such that an orthogonal projection of the first signal line131on the base substrate10, an orthogonal projection of the second signal line132on the base substrate10, and an orthogonal projection of the DC conductive structure120on the base substrate10overlap each other. Alternatively, the first signal line131, the second signal line132, and the DC conductive structure120are formed in the same layer. The DC conductive structure120includes a first DC conductive structure121and a second DC conductive structure122electrically connected by a via hole160. The first DC conductive structure121, the first signal line131, and the second signal line132are formed in the same layer114, such that the first DC conductive structure120is located between the first signal line131and the second signal line132. The second DC conductive structure122is formed on a side of the first DC conductive structure121away from the base substrate10, such that an orthographic projection of the second DC conductive structure122on the base substrate10covers an orthographic projection of the first DC conductive structure121on the base substrate10, and covers orthographic projections of the first and second signal lines131and132on the base substrate10. The first signal line and the second signal line are two different types of signal lines. The first signal line includes at least one signal line of the same type parallel to each other. The second signal line includes at least one signal line of the same type parallel to each other. According to the embodiments of the present disclosure, the following beneficial effects can be at least realized. 1. The DC conductive structure120is disposed between any two types of signal lines130. After a DC voltage is supplied into the DC conductive structure120, the parasitic influence between the two types of signal lines130can be effectively reduced, and possible mutual interference between the two types of signal lines130can be prevented. 2. The signal lines130are arranged in parallel, thereby not only reducing the phenomenon such as crossed wiring, but also the mutual interference between the two types of signal lines130, and improving the utilization rate of wiring space. 3. The at least two signal lines130and the DC conductive structure120are respectively located in different layers, and the DC conductive structure120spaces the two signal lines130apart from each other along a thickness direction of the display substrate100to shield the two signal lines130. This arrangement is suitable for devices with a plurality of layers. 4. The at least two signal lines130and the DC conductive structure120are located on the same layer, and the DC conductive structure120spaces the two signal lines130apart from each other along a plane direction of the display substrate100to shield the two signal lines130. This arrangement is beneficial to thinning of the device. 5. The DC conductive structure120is grounded to guide an external interference signal to the ground, thereby preventing the interference signal from entering the signal lines130and from interfering the control signal in the signal line130, and thus avoiding the loss of the control signals. It will be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure, and these changes and modifications are to be considered within the scope of the present disclosure. | 22,341 |
11862647 | DETAILED DESCRIPTION Hereinafter, some embodiments will be described in detail with reference to the accompanying drawings. FIG.1is a drawing illustrating a device100according to a first embodiment. Referring toFIG.1, the device100according to the first embodiment relates to an ANN (Artificial Neural Network), and may have a stackable 3D structure. Such device100may be used for machine learning. According to the first embodiment, the device100may include a substrate110, and a neuron block121and a synapse block123connected with at least one coupling element (not shown). The substrate110may support the neuron block121and the synapse block123. The neuron block121and the synapse block123may be stacked on the substrate110. Here, one axis X may be defined in a direction perpendicular to one surface of the substrate110. In other words, the neuron block121and the synapse block123may be stacked on one surface of the substrate110along the one axis X. The neuron block121and the synapse block123may be functionally and structurally divided from each other on one surface of the substrate110. At this time, the neuron block121and the synapse block123may be placed adjacent to each other on one surface of the substrate110. Also, the neuron block121and the synapse block123may be electrically connected through at least one coupling element (not shown). The neuron block121may have a computing function. Such neuron block121may be composed of a plurality of neurons, and each neuron may be configured with basic computing unit. The synapse block123is provided for signal transmission for the neuron block121, and for this, the synapse block123may have a memory function. Such synapse block123may be composed of a plurality of synapses, and the synapses may connect the neurons in a network form through weighted links. Substantially, the coupling element may electrically connect the neurons and the synapses. The neuron block121and the synapse block123may be simultaneously manufactured on one surface of the substrate110. The neuron block121and the synapse block123respectively may include at least one first channel element130, an insulating element140, at least one second channel element150, and at least one connecting element160. At this time, in the neuron block121and the synapse block123, at least one of the number or the arrangement of the first channel element130, the second channel element150, and the connecting element160may be different, and the number and the arrangement of the first channel element130, the second channel element150, and the connecting element160may all be the same. The first channel element130may be arranged on one surface of the substrate110. Here, the first channel element130may be placed on one surface of the substrate110along the one axis X. The insulating element140may be placed on the substrate110and the first channel element130. Here, the insulating element130may cover the first channel element130on one surface of the substrate110along the one axis X. The second channel element150may be arranged on the insulating element140. Here, the second channel element150may be placed on the first channel element130along the one axis X. Here, the second channel element150may be placed to be stacked on the first channel element130with the insulating element140interposed therebetween. The connecting element160may electrically connect the first channel element130and the second channel element150. For this, the connecting element160may penetrate the insulating element140. In other words, the first channel element130and the second channel element150may be stacked on the substrate110in order. Through this, the first channel element130and the second channel element150may be placed up and down along the one axis X with the insulating element140interposed therebetween. In addition, the first channel element130and the second channel element150may be connected to each other through the connecting element160. For example, one of the first channel element130or the second channel element150may be a transistor of channel N, and another of the first channel element130or the second channel element150may be a transistor of channel P. As one example, one of the first channel element130or the second channel element150may be N type FET (Field Effect Transistor), and another of the first channel element130or the second channel element150may be P type FET. FIGS.2,3,4,5,6,7,8,9,10,11, and12are drawings illustrating a manufacturing method of the device100according to the first embodiment. Referring toFIGS.2,3,4,5,6,7,8,9,10,11, and12, the device100according to the first embodiment may be manufactured. In other words, the device100may be manufactured in a stackable 3D structure. At this time, on the single substrate110, the neuron block121and the synapse block123may be simultaneously manufactured. However, the neuron block121and the synapse block123may be manufactured to be functionally and structurally divided from each other on one surface of the substrate110. First, as shown inFIGS.2,3,4, and5, the first channel elements130for the neuron block121and the synapse block123may be formed on the substrate110. Each first channel element130may include a first active unit132, a first insulating layer133, and first electrodes135,136,137. At this time, the first electrodes135,136,137may include a first G (Gate) electrode135, a first S (Source) electrode136, and a first D (Drain) electrode137. As shown inFIG.2, the first active layer131may be formed on one surface of the substrate110. After the substrate110is prepared, the first active layer131may be formed on one surface of the substrate110. For example, the substrate110may include a base substrate111and a first oxide film113formed on the base substrate111. In other words, as the first oxide film113is formed on the base substrate111in a deposition method, the substrate110may be prepared. After this, the first active layer131may be formed on the first oxide film113. For example, the first active layer131may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium). Next, as shown inFIG.3, the first active layer131may be divided into a plurality of first active units132. At this time, the first active units132may be separated from each other on one surface of the substrate110. Here, in the first oxide film113, surrounding areas of each of the first active units132may be exposed. Then, as shown inFIG.4, the first insulating layer133may be formed on the first active units132. In other words, the first insulating layer133may be placed on one surface of the first active units132. At this time, the first insulating layer133may be further formed on the surrounding areas of each of the first active units132in the first oxide film113. Here, the first insulating layer133may be formed of the same material for all of the first active units132. For example, the first insulating layer133may be formed of one material or a combination of at least two materials. Next, as shown inFIG.5, the first electrodes135,136,137may be formed for the first active units132. For this, part of the first insulating layer133may be removed on one surface of the first active units132. After this, for each of the first active units132, the first G electrode135, the first S electrode136, and the first D electrode may be processed. The first G electrode135may be placed on the opposite side of the first active unit132with the first insulating layer133interposed therebetween. In other words, the first G electrode135may not contact the first active unit132. The first S electrode136may be placed on one side of the first active unit132. In other words, the first S electrode136may contact one side of the first active unit132, and may not contact the first G electrode135by being separated from the first G electrode135. The first D electrode137may placed on the other side of the first active unit132. In other words, the first D electrode137may contact the other side of the first active unit132, and may not contact the first G electrode135by being separated from the G electrode135. Also, the first active unit132may connect the first S electrode136and the first D electrode137between the first S electrode136and the D electrode137. Then, as shown inFIGS.6,7, and8, throughout the neuron block121and the synapse block123, the insulating element140may be formed on the first channel elements130. The insulating element140may include an insulating member141and a second oxide film143. As shown inFIGS.6and7, the insulating member141may be formed to cover the first elements130on the substrate110. For example, the insulating member141may be formed of the same material with the base substrate111. At this time, as shown inFIG.6, the insulating member141may be formed in a deposition method. After this, as shown inFIG.7, the insulating member141may be flattened through CMP (Chemical Mechanical Polishing). Through this, on the first channel elements130, one surface of the insulating member141may be provided. Next, as shown inFIG.8, the second oxide film143may be formed on one surface of the insulating member141in the deposition method. For example, the second oxide film143may be formed of the same material with the first oxide film113. Subsequently, as shown inFIGS.8,9,10, and11, the second channel elements150for the neuron block121and the synapse block123may be formed on the insulating element140. At this time, the second channel elements150may be formed to be respectively stacked on the first channel elements130with the insulating element140interposed therebetween. Each second channel element150may include a second active unit152, a second insulating layer153, and second electrodes155,156,157. At this time, the second electrodes155,156,157may include a second G electrode155, a second S electrode156, and a second D electrode157. As shown inFIG.8, the second active layer151may be formed on one surface of the insulating element140. At this time, the second active layer151may be formed on the second oxide film143. For example, the second active layer151may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium). Next, as shown inFIG.9, the second active layer151may be divided into a plurality of second active units152. At this time, the second active units152may be separated from each other on the one surface of the insulating element140. Here, in the second oxide film143, surrounding areas of each of the second active units152may be exposed. Then, as shown inFIG.10, the second insulating layer153may be formed on the second active units152. In other words, the second insulating layer153may be formed on one surface of the second active units153in the deposition method. At this time, the second insulating layer153may be further formed on the surrounding areas of each of the second active units152in the second oxide film143. Here, the second insulating layer153may be formed of the same material with all of the second active units152. For example, the second insulating layer153may be formed of one material or a combination of at least two materials. Next, as shown inFIG.11, the second electrodes155,156,157may be formed for the second active units152. For this, part of the second insulating layer153may be removed on one surface of the second active units152. After this, for each of the second active units152, the second G electrode155, the second S electrode156, and the second D electrode157may be processed. The second G electrode155may be placed on the opposite side of the second active unit152with the second insulating layer153interposed therebetween. In other words, the second G electrode155may not contact the second active unit152. The second S electrode156may be placed on one side of the second active unit152. In other words, the second S electrode156may contact one side of the second active unit152, and may not contact the second G electrode155by being separated from the second G electrode155. The second D electrode157may be placed on the other side of the second active unit152. In other words, the second D electrode157may contact the other side of the second active unit152, and may not contact the second G electrode155by being separated from the second G electrode155. In addition, the second active unit152may connect the second S electrode156and the second D electrode157between the second S electrode156and the second D electrode157. Lastly, as shown inFIG.12, the connecting elements160may be formed to connect the first channel elements130and the second channel elements150. For this, the connecting elements160may penetrate the insulating element140. At this time, the connecting elements160may connect the first S electrode136and the second S electrode156, and connect the first D electrode137and the second D electrode157. Through this, the neuron block121and the synapse block123may be stacked on the substrate110. After this, although it is not shown, at least one coupling element (not shown) may be formed to connect the neuron block121and the synapse block123. Accordingly, the device100according to the first embodiment is manufactured. FIG.13is a drawing illustrating a device200according to a second embodiment. Referring toFIG.13, the device200according to the second embodiment relates to an ANN device, and may have a stackable 3D structure. Such device200may be used for machine learning. According to the second embodiment, the device200may include a substrate210, a neuron block221, and a synapse block223. At this time, since components of the device200according to the second embodiment are similar to each of corresponding components of the device100according to the first embodiment, the detailed description will be omitted. However, according to the second embodiment, during the neuron block121and the synapse block123are simultaneously manufactured on one surface of the substrate110, some components may be differently manufactured for the neuron block221and the synapse block223. The neuron block221and the synapse block223may respectively include at least one first channel element230, an insulating element240, at least one second channel element250, and at least one connecting element260. At this time, at least one of the first channel element230or the second channel element250may be differently formed for the neuron block221and the synapse block223. FIGS.14,15,16,17,18,19,20,21,22,23,24,25, and26are drawings illustrating a manufacturing method of the device200according to the second embodiment. Referring toFIGS.14,15,16,17,18,19,20,21,22,23,24,25, and26, the device200according to the second embodiment may be manufactured. In other words, the device200may be manufactured in a stackable 3D structure. At this time, on the single substrate210, the neuron block221and the synapse block223may be simultaneously manufactured. However, the neuron block221and the synapse block223may be manufactured to be functionally and structurally divided from each other on one surface of the substrate210. As shown inFIGS.14,15,16,17, and18, the first channel elements230for the neuron block221and the synapse block223may be formed on the substrate210. Each of the first channel elements230may include a first active unit232, a first insulating layer233, and first electrodes235,236,237. At this time, the first electrodes235,236,237may include a first G (Gate) electrode235, a first S (Source) electrode236, and a first D (Drain) electrode237. As shown inFIG.14, a first active layer231may be formed on one side of the substrate210. After the substrate210is prepared, the first active layer231may be formed on one surface of the substrate210. For example, the substrate210may include a base substrate211and a first oxide film213formed on the base substrate211. In other words, as the first oxide film213is formed on the base substrate211in a deposition method, the substrate210may be prepared. After this, the first active layer231may be formed on the first oxide film213. For example, the first active layer231may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium). Next, as shown inFIG.15, the first active layer231may be divided into a plurality of the first active units232. At this time, the first active units232may be separated from each other on one surface of the substrate210. Here, in the first oxide film213, surrounding areas of each of the first active units232may be exposed. Next, as shown inFIGS.16and17, the first insulating layer233,234may be formed on the first active units232. In other words, the first insulating layer233,234may be placed on one surface of the first active units232. At this time, the first insulating layer233,234may be further formed on the surrounding areas of each of the first active units232, in the first oxide film213. Here, the first insulating layer234for the neuron block221and the first insulating layer233for the synapse block223may be individually formed, and may be formed of different materials. For example, the first insulating layer233,234may be formed of one material or a combination of at least two materials. As an example, at least one of the first insulating layer234for the neuron block221or the first insulating layer233for the synapse block223may be formed of a combination of at least two materials. For example, after the first insulating layer233for the synapse block223is formed, the first insulating layer234for the neuron block221may be formed. For this, the first active units232may be divided into at least one active unit232for the neuron block221and the rest of the active unit232for the synapse block223. As shown inFIG.16, a first mask member232amay be formed in the first oxide film213to cover the at least one active unit232and its surrounding area in the first oxide film213. Also, the first insulating layer233for the synapse block223may be formed on the rest of the active unit232and its surrounding area in the first oxide film213, and then, the first mask member232amay be removed. After this, as shown inFIG.17, a second mask member232bmay be formed to cover the rest of the first active units232and the first insulating layer233on the first oxide layer213. In addition, the first insulating layer234for the neuron block221may be formed on at least one first active unit232and its surrounding area in the first oxide film213, and then, the second mask member232bmay be removed. For example, the first mask member232aand the second mask member232bmay include at least one of Si3N4, SiNX, SiO2, Y2O3, La2O3, or TiO2. As another example, after the first insulating layer234for the neuron block221is formed, the first insulating layer233for the synapse block223may be formed. This is similar to the above described example, so detailed description will be omitted. Next, as shown inFIG.18, the first electrodes235,236,237may be formed for the first active units232. For this, part of the first insulating layer233,234may be removed on one surface of the first active units232. After this, for each of the first active units232, the first G electrode235, the first S electrode236, and the first D electrode237may be processed. The first G electrode235may be placed on the opposite side of the first active unit232with the first insulating layer233,234interposed therebetween. In other words, the first G electrode235may not contact the first active unit232. The first S electrode236may be placed on one side of the first active unit232. In other words, the first S electrode236may contact one side of the first active unit232, and may not contact the first G electrode235by being separated from the first G electrode235. The first D electrode237may be placed on the other side of the first active unit232. In other words, the first D electrode237may contact the other side of the first active unit232, and may not contact the first G electrode235by being separated from the first G electrode235. Also, the first active unit232may connect the first S electrode236and the first D electrode237between the first S electrode236and the first D electrode237. Then, as shown inFIGS.19,20, and21, throughout the neuron block221and the synapse block223, the insulating element240may be formed on the substrate210and the first channel elements230. The insulating element240may include an insulating member241and a second oxide film243. As shown inFIGS.19and20, the insulating member241may be formed to cover the first channel elements230on the substrate210. For example, the insulating member241may be formed of the same material with the base substrate211. At this time, as shown inFIG.19, the insulating member241may be formed in a deposition method. After this, as shown inFIG.20, the insulating member241may be flattened through CMP (Chemical Mechanical Polishing). Through this, on the first channel elements230, one surface of the insulating member241may be provided. Next, as shown inFIG.21, the second oxide film243may be formed on one surface of the insulating member241in the deposition method. For example, the second oxide film243may be formed of the same material with the first oxide film213. Then, as shown inFIGS.21,22,23,24, and25, the second channel elements250for the neuron block221and synapse block223may be formed on the insulating element240. At this time, the second channel elements250may be formed to be respectively stacked on the first channel elements230with the insulating element240interposed therebetween. Each second channel element250may include a second active unit252, second insulating layer253,254, and second electrodes255,256,257. At this time, the second electrodes255,256,257may include a second G electrode255, a second S electrode256, and a second D electrode257. As shown inFIG.21, the second active layer251may be formed on one surface of the insulating element240. At this time, the second active layer251may be formed on the second oxide film243. For example, the second active layer251may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium). Next, as shown inFIG.22, the second active layer251may be divided into a plurality of second active units252. At this time, the second active units252may be separated from each other on one surface of the insulating element240. Here, on the second oxide film243, surrounding areas of each of the second active units252may be exposed. Next, as shown inFIGS.23and24, the second insulating layer253,254may be formed on the second active units252. In other words, the second insulating layer253,254may be formed on one surface of the second active units252in a deposition method. At this time, the second insulating layer253,254may be further formed on the surrounding areas of each of the second active units252. Here, the second insulating layer254for the neuron block221and the second insulating layer253for the synapse block223may be individually formed, and may be formed of different materials. For example, the second insulating layer253,254may be formed of one material or a combination of at least two materials. As an example, at least one of the second insulating layer254for the neuron block221and the second insulating layer253for the synapse block223may be formed of a combination of at least two materials. For example, after the second insulating layer253for the synapse block223is formed, the second insulating layer254for the neuron block221may be formed. For this, the second active units252may be divided into at least one second active unit252for the neuron block221and the rest of the second active unit252for the synapse block223. As shown inFIG.23, a third mask member252amay be formed in the second oxide film243to cover at least one second active unit252and its surrounding area in the second oxide film243. Also, the second insulating layer253for the synapse block223may be formed on the rest of the second active unit252and its surrounding area in the second oxide film243, and then, the third mask member252amay be removed. After this, as shown inFIG.24, a fourth mask member252bmay be formed to cover the rest of the second active units252and the second insulating layer253in the second oxide film243. Also, the second insulating layer254for the neuron block221may be formed on the at least one second active unit252and its surrounding area on the second oxide film243, and then, the fourth mask member252bmay be removed. For example, the third mask member252aand the fourth mask member252bmay include at least one of Si3N4, SiNX, SiO2, Y2O3, La2O3, or TiO2. As another example, after the second insulating layer254for the neuron block221is formed, the second insulating layer253for the synapse block223may be formed. This is similar to the above described example, so the detailed description will be omitted. Next, as shown inFIG.25, the second electrodes255,256,257may be formed for the second active units252. For this, part of the second insulating layer253,254may be removed on the one surface of the second active units252. After this, for each second active unit252, the second G electrode255, the second S electrode256, and the second D electrode257may be processed. The second G electrode255may be placed on the opposite side of the second active unit252with the second insulating layer253,254interposed therebetween. In other words, the second G electrode255may not contact the second active unit252. The second S electrode256may be placed on one side of the second active unit252. In other words, the second S electrode256may contact one side of the second active unit252, and may not contact the second G electrode255by being separated from the second G electrode255. The second D electrode257may be placed the other side of the second active unit252. In other words, the second D electrode257may contact the other side of the second active unit252, and may not contact the second G electrode255by being separated from the G electrode255. Also, the second active unit252may connect the second S electrode256and the second D electrode257between the second S electrode256and the second D electrode257. Last, as shown inFIG.26, the connecting elements260may be formed to connect the first channel elements230and the second channel elements250. For this, the connecting elements260may penetrate the insulating element240. At this time, the connecting elements260may connect the first S electrode236and the second S electrode256, and connect the first D electrode237and the second D electrode257. Through this, the neuron block221and the synapse block223may be stacked on the substrate210. After this, it is not shown, but at least one coupling element (not shown) may be formed to connect the neuron block221and the synapse block223. Accordingly, the device200according to the second embodiment is manufactured. FIGS.27A and27Bare drawings for explaining exemplary embodiments of the devices100,200according to various embodiments. For examples, at least one of the first active layer131,231or the second active layer151,251may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium), and may be successfully manufactured. At this time, at least one of the first active layer131,231or the second active layer151,251may be respectively stacked on at least one of the substrate110,120or the insulating element140,240based on low-temperature stack process or low-temperature element manufacture process. In one example, on the base substrate111,211made of Si, when the first oxide film113,213made of AL203is stacked, the first active layer131,231including InGaAs may be successfully stacked on the first oxide film113,213. Similarly, on the insulating member141,241made of Si, when the second oxide film143,243made of AL2O3 is stacked, the second active layer151,251including InGaAs may be successfully stacked on the second oxide film143,243. In another example, on the base substrate111,211made of Si, when the first oxide film113,213made of SiO2 is stacked, the first active layer131,231including Ge may be successfully stacked on the first oxide film113,213. Similarly, on the insulating member141,241made of Si, when the second oxide film143,243made of SiO2 is stacked, the second active layer151,251including Ge may be successfully stacked on the second oxide film143,243. As including at least one of the first active layer131,231or the second active layer151,251as described above, the neuron block121,221may implement performance capable of computing function according to a plurality of neurons as shown inFIG.27A. Furthermore, as including at least one of the first active layer131,231or the second active layer151,251as described above, the synapse block123,223may implement performance capable of signal transmitting and memory function according to a plurality of synapses as shown inFIG.27B. According to various embodiments, it may minimize signal transmission pathway in the device100,200implementing artificial neural network. In other words, as the neuron block121,221functioning as neurons and the synapse block123,223functioning as synapses are stacked together on the single substrate110,210and the neuron block121,221and the synapse block123,223are implemented in a form that the first channel element130,230and the second channel element150,250are stacked, the signal transmission pathway may be minimized between the neuron block121,221and the synapse block123,223and between the first channel element130,230and the second channel element150,250. Accordingly, since signal loss on the signal transmission pathway may be minimized, the device100,200may not only operate with reduced power consumption but also be implemented in small size. In addition, since the neuron block121,221and the synapse block123,223may be simultaneously manufactured on one surface of the substrate110,210, the resources required to manufacture the device100,200may be reduced. The device100,200according to various embodiments, which relates to an artificial neural network device, may include the substrate110,210, neuron block121,221placed on a partial area on one surface of the substrate110,210, the synapse block121,221placed on the remaining area on the surface of the substrate110,210, and at least one coupling element electrically connecting the neuron block and the synapse block. According to various embodiments, the neuron block121,221and the synapse block123,223may include at least one first channel element130,230respectively arranged on the surface of the substrate110,210, and at least one second channel element150,250respectively stacked on the first channel element130,230. According to various embodiments, the neuron block121,221and the synapse block123,223may respectively further include the connecting elements160,260electrically connecting the first channel element130,230and the second channel element150,250. According to various embodiments, the neuron block121,221and the synapse block123,223respectively further include the insulating element140,240interposed between the first channel element130,230and the second channel element150,250and separating the first channel130,230and the second channel150,250from each other. According to various embodiments, the connecting elements160,260may penetrate the insulating element140.240. According to various embodiments, the first channel element130,230may include the first active layer131,231, the first insulating layer133,233,234placed on one surface of the first active layer131,231, the first G electrode135,235placed on the opposite side of the first active layer131,231with the first insulating layer interposed therebetween, the first S electrode136,236contacting one side of the first active layer131,231and separated from the first G electrode135,235, and the first D electrode137,237contacting the other side of the first active layer131,231, and separated from the first G electrode135,235. According to various embodiments, the first insulating layer122,233,234may be formed of a combination of at least two materials. According to one embodiment, the first insulating layer133of the neuron block121and the first insulating layer133of the synapse block123may be formed of the same material. According to another embodiment, the first insulating layer234of the neuron block221and the first insulating layer233of the synapse block223may be formed of different materials. According to various embodiments, the second channel element150,250may include the second active layer151,251, the second insulating layer153,253,254placed on one surface of the second active layer151,251, the second G electrode155,255placed on the opposite side of the second active layer151,251with the second insulating layer153,253,254interposed therebetween, the second S electrode156,256contacting one side of the second active layer151,251, and separated from the second G electrode155,255, and the second D electrode157,257contacting the other side of the second active layer151,251, and separated from the second G electrode155,255. According to various embodiments, the second insulating layer153,253,254may be formed of a combination of at least two different materials. According to one embodiment, the second insulating layer153of the neuron block121and the second insulating layer153of the synapse block123may be formed of the same material. According to another embodiment, the second insulating layer254of the neuron block221and the second insulating layer253of the synapse block223may be formed of different materials. According to various embodiments, the connecting elements160,260may electrically connect the first S electrode136,236and the second S electrode156,256, and may electrically connect the first D electrode137,237and the second D electrode157,257. According to various embodiments, at least one of the first active layer131,231or the second active layer151,251may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium). The manufacturing method of the device100,200according to various embodiments, which relates to a manufacturing method of an artificial neural network device, may include preparing the substrate110,210, forming the neuron block121,221and the synapse block123,223together on one surface of the substrate110,210, and electrically connecting the neuron block and the synapse block through at least one coupling element. According to various embodiments, the forming the neuron block121,221and the synapse block123,223together may include forming at least one first channel element130,230on the surface of the substrate110,210, and forming at least one second channel element150,250to be respectively stacked on the first channel element130,230. According to various embodiments, the forming the neuron block121,221and the synapse block123,223may further include forming the connecting elements160,260to electrically connect the first channel element130,230and the second channel element150,250. According to various embodiments, the forming the second channel element150,250may include forming the insulating element140,240covering the first channel element130,230on the surface of the substrate110,210, and forming the second channel element150,250on the first channel element130,230with the insulating element140,240interposed therebetween. According to various embodiments, the connecting elements160,260may be formed to penetrate the insulating element140,240. According to various embodiments, the first channel element130230may include the first active layer131,231, the first insulating layer133,233,234placed on one surface of the first active layer131,231, the first G electrode135,235placed on the opposite side of the first active layer131,231with the first insulating layer interposed therebetween, the first S electrode136,236contacting one side of the first active layer131,231and separated from the first G electrode135,235, and the first D electrode137,237contacting the other side of the first active layer131,231and separated from the first G electrode135,235. According to various embodiments, the first insulating layer122,233,234may be formed of a combination of at least two materials. According to one embodiment, the first insulating layer133of the neuron block121and the first insulating layer133of the synapse block123may be formed of the same material. According to another embodiment, the first insulating layer234of the neuron block221and the first insulating layer233of the synapse block223may be formed of different materials. According to various embodiments, the second channel element150,250may include the second active layer151,251, the second insulating layer153,253,254placed on one surface of the second active layer151,251, the second G electrode155,255placed on the opposite side of the second active layer151,251with the second insulating layer interposed therebetween, the second S electrode156,256contacting one side of the second active layer151,251and separated from the second G electrode155,255, and the second D electrode157,257contacting the other side of the second active layer151,251and separated from the second G electrode155,255. According to various embodiments, the second insulating layer153,253,254may be formed of a combination of at least two materials. According to one embodiment, the second insulating layer153of the neuron block121and the second insulating layer153of the synapse block123may be formed of the same material. According to another embodiment, the second insulating layer254of the neuron block221and the second insulating layer253of the synapse block223may be formed of different materials. According to various embodiments, the connecting elements160,260may electrically connect the first S electrode136,236and the second S electrode156,256, and may electrically connect the first D electrode137,237and the second D electrode157,257. According to various embodiments, at least one of the first active layer131,231or the second active layer151,251may include at least one of Si (Silicon), TMD (Transition Metal Dichalcogenide), InGaAs (Indium Gallium Arsenide), or Ge (Germanium). It should be understood that various embodiments of the disclosure and terms used in the embodiments do not intend to limit technical features disclosed in the disclosure to the particular embodiment disclosed herein; rather, the disclosure should be construed to cover various modifications, equivalents, or alternatives of embodiments of the disclosure. With regard to description of drawings, similar or related components may be assigned with similar reference numerals. As used herein, singular forms of noun corresponding to an item may include one or more items unless the context clearly indicates otherwise. In the disclosure disclosed herein, each of the expressions “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B, or C”, “one or more of A, B, and C”, or “one or more of A, B, or C”, and the like used herein may include any and all combinations of one or more of the associated listed items. The expressions, such as “a first”, “a second”, “the first”, or “the second”, may be used merely for the purpose of distinguishing a component from the other components, but do not limit the corresponding components in the importance or the order. It is to be understood that if an element (e.g., a first element) is referred to as “coupled to (functionally or communicatively)” or “connected to” another element (e.g., a second element), it means that the element may be coupled with the other element directly, or via the other element (e.g., a third element). The term “module” used in the disclosure may include a unit implemented in hardware, software, or firmware and may be interchangeably used with the terms logic, logical block, part, or circuit. The module may be a minimum unit of an integrated part or may be a part thereof. The module may be a minimum unit for performing one or more functions or a part thereof. For example, the module may include an application-specific integrated circuit (ASIC). According to various embodiments, each component (e.g., the module or the program) of the above-described components may include one or plural entities. According to various embodiments, at least one or more components of the above components or operations may be omitted, or one or more components or operations may be added. Alternatively or additionally, some components (e.g., the module or the program) may be integrated in one component. In this case, the integrated component may perform the same or similar functions performed by each corresponding components prior to the integration. According to various embodiments, operations performed by a module, a programming, or other components may be executed sequentially, in parallel, repeatedly, or in a heuristic method, or at least some operations may be executed in different sequences, omitted, or other operations may be added. | 41,326 |
11862648 | DETAILED DESCRIPTION According to aspects of the disclosure, a detector array is provided for measuring characteristics of light. The detector array may include a photodiode array and a filter array disposed over the photodiode array. The photodiode array may include a plurality of photodiodes. The filter array may include a plurality of bandpass filters. Each bandpass filter may be positioned over a different photodiode. Furthermore, each bandpass filter may have a different transmission band than the rest, thereby enabling its underlying photodiode to measure the energy of the light in the filter's transmission band. When the signals produced by the photodiodes in the detector array are combined, an energy measurement can be obtained for an entire spectrum of interest. The spectrum of interest may encompass one or more of the visible light band, the IR band, and/or the UV band. According to aspects of the disclosure, the optoelectronic device is provided that includes the detector array and a signal processor that is configured to process the signals generated by the photodiodes in the detector array. In some implementations, the signal processor may include an input/output interface that is configured to serially output the signals by the photodiodes in the photodiode array. Additionally or alternatively, in some implementations, the signal processor may include a processor that is configured to perform one or more arithmetic and logic operations based on the signals generated by the photodiodes in the photodiode array, and output the result of the operations via the I/O interface. For example, the processor may be configured to calculate the color of light that is incident upon the optoelectronic device, and output an indication of the color via the I/O interface. According to aspects of the disclosure, the detector array may include various adaptations for reducing cross-talk between photodiodes in the photodiode array. In some implementations, the detector array may include a guide array that is disposed between the photodiode array and the filter array. The guide array may include a plurality of guide members. Each guide member may be formed of a light-transmissive material. Each guide member may be disposed between a different photodiode/filter pair, such that light that is filtered through the filter in the pair is guided by the guide member to the photodiode in the same pair. According to aspects of the disclosure, the guide members in the guide array may be separated from one another by a layer of light-blocking material. The layer of light-blocking material may be formed in the spaces between the guide members in the guide array, thereby reducing the amount of light that can travel between neighboring guide members. The layer of light-blocking material may be formed of at least one of a light reflecting material and a light absorbing material. In some implementations, the layer of light-blocking material may include three metal layers that are stacked over each other. According to aspects of the disclosure, the photodiode array may be configured to reduce cross-talk between the photodiodes in the photodiode array. For example, in some instances, the photodiodes may be CMOS photodiodes including respective n+/p-epi regions and one or more n-well region(s). The n-well region(s) may be diffused/implanted to a depth that is greater than the depth at which photons having a predetermined wavelength can penetrate the photodiode array. The predetermined wavelength may include any suitable wavelength, such as a wavelength that is in the ultraviolet (UV) band, a wavelength that is in the IR band, and a wavelength that is in the visible light band. Because the n-well is biased to a bandgap generated DC voltage, the n-well regions may reduce the amount of light from traveling between neighboring p+/n+ regions, thereby reducing the amount of cross-talk between the photodiodes in the photodiode array. According to aspects of the disclosure, the light-blocking layer of the guide array may be at least partially aligned with the n-well region(s) of the photodiodes in the photodiode array. For example, the light-blocking layer of the guide array may be disposed directly over the n-well regions to create a continuous structure which prevents light from traveling sideways. This structure may reduce the amount of cross-talk that occurs between the photodiodes in the photodiode array by ensuring that all (or a significant portion of) light that enters the optoelectronic device through a given filter reaches only (or primarily) a given photodiode that is situated under the given filter, without affecting photodiodes that are situated adjacently to the given photodiode. In some aspects, aligning the light-blocking layer of the guide array with the n-well region(s) of the photodiode array can significantly improve the accuracy of the resultant detector array. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. It will be understood that these terms are intended to encompass different orientations of the element in addition to any orientation depicted in the figures. Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. FIG.1Ais a diagram of an example of a detector array100, according to aspects of the disclosure. The detector array100may include a section110athat is configured to detect the spectral characteristics of UV light, a section110bthat is configured to detect the spectral characteristics of visible light, and a section110cthat is configured to detect the spectral characteristics of IR light. More particularly, the detector array100may include a photodiode array110, a guide array120disposed over the photodiode array, and a filter array130disposed over the guide array120. Furthermore, the detector array100may include and an IR cutoff filter140and IR pass filter150disposed over the filter array130, as shown. The photodiode array110may include a plurality of photodiodes112a-ithat are formed over a p-substrate140. The photodiodes112a-cmay be P+/n-well photodiodes and they may be used to detect the power of light emissions in the UV band. Each of the photodiodes112a-cmay include a respective p+ region114that is surrounded on the sides and bottom by an n-well region117a, and a p-region118that is disposed under the n-well region117a. The photodiodes112d-imay include n+/P− photodiodes and they may be used to detect the power of light emissions in the IR and visible light bands. Each of the photodiodes112d-imay include a respective n+ region115that is surrounded on the sides, but not necessarily the bottom, by an n-well region117b, and a p-region119disposed under the n-well region117band the n+ regions115. In the present example, the n-well regions117aand117bhave the same composition, but alternative implementations are possible in which the n-well regions117a-bhave different compositions. For ease of description, throughout this disclosure, the n-well regions117aand117bmay be referred to collectively, as n-well region117, when appropriate. Similarly, the respective n-well regions117bof the photodiodes112d-imay be referred to collectively as “a n-well region” and they might be part of a continuous n-well layer, as shown further below inFIGS.9A-B. In some implementations, the n-well regions117bmay have a secondary function of providing optical insulation between neighboring n+ regions115to prevent cross-talk between the photodiodes112d-i. More particularly, in some implementations, the n+ regions115may have a thickness t1and the n-well a regions117bmay have a thickness t2that is greater than the thickness t2. The thickness t2may be greater than the depth at which one or more photons having a predetermined frequency can penetrate the photodiode array110. By way of example, the predetermined frequency may be a frequency in the UV band, a frequency in the IR band, or a frequency in the visible light band. The guide array120may include a plurality of guide members124a-iseparated by a light-blocking layer122. Each of the guide members124a-imay be aligned with a different one of the photodiodes112a-i, as shown. Furthermore, each of the guide members124a-imay be formed of a dielectric light-transmissive material. The light-transmissive material may include a SiN or SiO2 material and/or any other suitable type of light-transmissive material. The light-blocking layer122may be formed of at least one of a light reflecting material and/or a light absorbing material. In some implementations, the light-blocking layer122may be arranged to prevent (or reduce) cross-talk between the guide members124a-iby preventing light from travelling from one of the guide members124a-ito another. In some implementations, the light-blocking layer122may be formed of three metal layers122a-cthat are stacked over one another, as shown, and separated by layers122d-e. In some implementations, any of the metal layers122a-cmay be formed of the same material as the rest. Additionally or alternatively, in some implementations, any of the metal layers122a-cmay be formed of a different material than the rest. In some implementations, the metal layer122amay be formed of aluminum or aluminum-silicon alloy such as Al—Si—Cu, the metal layer122bmay be formed of Al—Cu alloy sandwiched between titanium nitride barrier layer, and the metal layer122cmay be formed of copper. The layers122d-emay be formed of the same material or different materials. In some implementations, the layer122dmay be formed of tungsten plugs with TiN adhesion layer and the layer122emay be formed of copper. In some implementations, the light-blocking layer122may be formed concurrently (and/or simultaneously) with the metallization of CMOS logic that is situated on the same die as the detector array100(e.g., see the signal processor405inFIG.4). In such instances, the structural composition of the light-blocking layer stack (e.g., the light blocking layer122) may be mainly determined by the implementation of the CMOS or BiCMOS back end of line (BEOL) technologies used. By way of example, the technologies used may include a 3 metal layer or 4 metal layer BEOL technologies. Although in the present example, the light-blocking layer122has a multi-layer structure, alternative implementations are possible in which the light-blocking layer122includes only one layer. In some implementations, each of the guide members124a-imay have a thickness in the range of 4.5 um to 5.5 um. Additionally or alternatively, in some implementations, the light-blocking layer122may have a thickness in the range of 6.5 um to 7.7 um. Additionally or alternatively, in some implementations, the light-blocking layer122may have a greater thickness than any of the guide members124a-i. For example, in such instances, the guide members124a-imay have a thickness in the range of 4.5 um to 5.5 um and the light-blocking layer122may have a thickness in the range of 6.5 um to 7.7 um. Additionally or alternatively, in some implementations, the guide array120may have a thickness in the range of 7.5 um to 8.5 um. The filter array130may include a plurality of bandpass filters132a-i. Each of the filters132a-imay be aligned with a different one of the guide members124a-i. Furthermore, each bandpass filter may have a different transmission band. As illustrated inFIG.2, the filter132amay have a transmission band210a(e.g., 300-330 nm); the filter132bmay have a transmission band210b(e.g., 340-370 nm); the filter132cmay have a transmission band210c(e.g., 370-400 nm); the filter132dmay have a transmission band210d(e.g., 400-500 nm); the filter132emay have a transmission band210e(e.g., 500-600 nm); the filter132fmay have a transmission band210f(e.g., 600-700 nm); the filter132gmay have a transmission band210g(e.g., 700-800 nm); the filter132hmay have a transmission band210h(e.g., 800-900 nm); and the filter132imay have a transmission band210i(e.g., 900-1000 nm). The filter array130may include a plurality of metal layers134and a plurality of metal layers136. Each of the metal layers134may be aligned with a different one of the metal layers136. Additionally or alternatively, each of the metal layers134may be spaced apart by a different distance from the metal layer136with which the metal layer134is aligned. In some implementations, a metal layer136may be considered to be aligned with a given metal layer134if at least some of light passing through the metal layer136reaches the given metal layer134. Additionally or alternatively, in some implementations, a metal layer136may be considered to be aligned with a given metal layer134, if at least a portion of the metal layer136is situated directly above the given metal layer134. In some implementations, the metal layers134and136may be suspended in a layer of light-transmissive material138, as shown. The metal layers134and136may be formed of any suitable type of material. In some implementations, any of the metal layers134and136may be formed of an alloy including aluminum and silver. The layer of light-transmissive material may include a SiN material and/or any other suitable type of light-transmissive material like silicon dioxide SiO2. In some implementations, each of the metal layers134may have a thickness in the range of 400 A to 600 A. Additionally or alternatively, in some implementations, each of the metal layers136may have a thickness in the range of 400 A to 600 A. Additionally or alternatively, in some implementations, the entire filter array130may have a thickness in the range of 0.125 um to 0.4 um. Each of the filters132a-iin the filter array130may include a respective one of the respective metal layer136and a different one of the metal layers134that is situated underneath the metal layer136. In some implementations, as noted above, the distance between the metal layers134and136in any of the filters132a-imay be different from the distance between the metal layers134and136in the remaining ones of the filters132a-i. More precisely, each of the filters132a-imay include a different Fabry-Perot cavity that is formed by the filter's respective metal layer136and the metal layer134. Although in the present example the filters132a-iare implemented using Fabry-Perot cavities, alternative implementations are possible in which another type of filter is used such as double stack of Fabry-Perot cavity having three metal layers and two layer of light-transmissive materials forming a stack including Ag/SIN/Ag/SIN/Ag layers. FIG.1Bshows the configuration of the filter132ain further detail, in accordance with one particular implementations. In some implementations, apart from the distance between the metal layers134and136, the structure of the filters132b-imay be the same or similar to that of the filter132a. As is further discussed below,FIG.1Bis provided to clearly show the spatial relationship between each (or at least one) of the metal layers134and the light-blocking layer122. Shown inFIG.1Bis a portion of the guide member124aand a portion of the light-blocking layer122. As illustrated inFIG.1B, the light-blocking layer122may have a thickness that is greater than the thickness of the guide member124a, such that a top surface123of the light-blocking layer122is situated above the top surface125of the guide member124a. As illustrated, the metal layer136may include a central portion136aand end portions136bthat are inclined relative to the central portion136a. Similarly, the metal layer134may include a central portion134aand end portions134bthat are inclined relative to the central portion134a. In some implementations, the entire central portion134aof the metal layer134may be situated below the level of the top surface123of the light-blocking layer122. Additionally or alternatively, in some implementations, only some of the central portion134aof the metal layer134may be situated below the level of the top surface123of the light-blocking layer. Situating at least some of the central portion134aof the metal layer134below the level of the top surface123of the light-blocking layer132may reduce the amount of cross-talk between the filter132aand neighboring filters to greatly improve the resolution of the filter array130. In the example ofFIG.1B, the level of the top surface123is denoted by a dashed line. Although in the present example, the metal layer134includes a horizontal central portion134aand inclined end-portions134b, alternative implementations are possible in which the inclined end-portions134bare omitted. Although in the present example, the metal layer136includes a horizontal central portion136aand inclined end-portions136b, alternative implementations are possible in which the inclined end-portions136bare omitted. In the present example, the metal layer134can be regarded as different segments (or portions) of the same discontinuous metal layer. In this regard, it will be understood that alternative implementations are possible in which the metal layers134are replaced by a single continuous metal layer (e.g., see the metal layer1510which is shown inFIGS.15A-B). Moreover, in the present example, the metal layers136can be regarded as different segments (or portions) of the same discontinuous metal layer. In this regard, it will be understood that alternative implementations are possible in which the metal layers136are replaced by a single continuous metal layer (e.g., see the metal layer1810which are shown inFIGS.15A-B). Returning toFIG.1A, the IR-cutoff filter140may be disposed over the filters132d-f. In some implementations, the IR-cutoff filter140may be arranged to block light having a wavelength that is greater than 700 nm and transmit light having a wavelength that is less than 700 nm. Additionally or alternatively, in some implementations, the IR-cutoff filter140may have a thickness in the range of 4 um to 5 um. The IR-pass filter150may be disposed over the filters132g-i. In some implementations, the IR-pass filter may be arranged to block light having a wavelength that is less than 700 nm and transmit light having a wavelength that is greater than 700 nm. Additionally or alternatively, in some implementations, the IR-pass filter150may have a thickness in the range of 2 um to 2.5 um. Any of the IR-cutoff filter140and the IR-pass filter150may be an absorption filter based on organic dye or pigment. Any of the IR-cutoff filter140and the IR-pass filter150may be may be formed on top of the filter array130by using spin coating and/or any other suitable process. Additionally or alternatively, in some implementations, the IR-cutoff filter150can be a metallic interference IR-cutoff filter including silver and a dielectric material, such as Nb2O5(niobium pentoxide), with a total thickness of 1 um. In some implementations, the Ag thickness may be about 100 A and the Nb2O5thickness may be in the range of 500 A to 600 A. In some implementation, the IR-cutoff filter140and the IR-pass filter150may be replaced with a full dielectric IR-cutoff filter that is configured to block wavelengths lower than 400 nm and wavelengths larger than 700 nm. The total thickness of such full dielectric IR-cutoff filter may be in the range of 4.5 um to 5.5 um. FIG.1Cis a top-down view of the detector array100with the IR-cutoff filter140and the IR-pass filter150removed.FIG.1Cillustrates that the photodiodes112a-i, the guide members124a-i, and the filters132a-imay be aligned to form a plurality of detector cells160a-i. For example, the filter132amay be aligned with the guide member124a, and the guide member124amay be aligned with the photodiode112a. As a result, the filter132a, the guide member124a, and the photodiode112amay together form the detector cell160a. As another example, the filter132bmay be aligned with the guide member124b, and the guide member124bmay be aligned with the photodiode112b. As a result, the filter132b, the guide member124b, and the photodiode112bmay together form the detector cell160b. As yet another example, the filter132imay be aligned with the guide member124i, and the guide member124imay be aligned with the photodiode112i. As a result, the filter132i, the guide member124i, and the photodiode112imay together form the detector cell160i. In some implementations, a guide member may be considered to be aligned with an underlying photodiode if at least some of light passing through the guide member can reach the photodiode. Additionally or alternatively, in some implementations, a guide member may be considered to be aligned with an underlying photodiode if the guide member is disposed directly above the photodiode. Additionally or alternatively, in some implementations, a guide member may be considered to be aligned with an underlying photodiode if the guide member is disposed partially above the photodiode, such that a portion of the guide member is situated directly above the photodiode and another portion is overhanging the photodiode. In some implementations, a filter may be considered to be aligned with an underlying guide member if at least some of light passing through the filter can reach the guide member. Additionally or alternatively, in some implementations, a filter may be considered to be aligned with an underlying guide member if the filter is disposed directly above the guide member. Additionally or alternatively, in some implementations, a filter may be considered to be aligned with an underlying guide member if the filter is disposed partially above the guide member, such that a portion of the filter is situated directly above the guide member and another portion is overhanging the guide member. According to aspects of the disclosure, the detector cells160a-imay be optically insulated from one another to eliminate (or reduce) the amount of crosstalk between the cells160a-i, or the photodiodes112a-i, in particular. In some implementations, the optical insulation may be provided by the light-blocking layer122which, as noted above, may prevent (or reduce the amount of) light travelling from one of the guide member124a-ito another one of the guide member124a-i. Additionally or alternatively, in some implementations, the optical insulation may be provided by the n-well region(s)117which, as noted above, may be arranged to prevent light that has reached one photodiode from travelling across that photodiode to reach neighboring photodiodes. In some implementations, the light-blocking layer122may be aligned with the guide layer(s)124a-ito form a continuous structure that prevents (or reduces the amount of) light that can travel from one of the detector cells160a-ito another one of the detector cells160a-i. For example, at least a portion of the light-blocking layer122may be situated directly above the n-well region(s)117aand/or the n-well region(s)117b. In some implementations, aligning the light-blocking layer of the guide array with the n-well region(s) of the photodiode array may improve the accuracy of the detector array100. FIGS.3A-Billustrate the operation of the detector array100, according to aspects of the disclosure. Shown inFIG.3Ais a plot310, which illustrates the spectral content of a test light. Shown inFIG.3Bis a plot320, which illustrates the response of the detector array100to the test light.FIGS.3A-Billustrate that when the detector array100is exposed to the test light, the signals generated by the photodiodes112a-iin the detector array100may be used to reconstitute the spectral content of the test light over a given range of interest. In the plot320, the magnitude of each signal that is generated by the photodiodes112a-imay be represented by a different one of the bars322a-i. More particularly, the bar322amay represent the magnitude of a signal (e.g., a voltage signal) generated by the photodiode112a; the bar322bmay represent the magnitude of a signal generated by the photodiode112b; and the bar322cmay represent the magnitude of a signal that is generated by the photodiode112c. Similarly, the bar322dmay represent the magnitude of a signal generated by the photodiode112d; the bar322emay represent the magnitude of the signal generated by the photodiode112e; the bar322fmay represent the magnitude of the signal generated by the photodiode112f; the bar322gmay represent the magnitude of the signal generated by the photodiode112g; the bar322hmay represent the magnitude of the signal generated by the photodiode112h; and the bar322imay represent the magnitude of the signal generated by the photodiode112i. FIG.4is a diagram of an example of an optoelectronic device400, according to aspects of the disclosure. As illustrated, the optoelectronic device400includes the detector array100and a signal processor405. The detector array100and the signal processor405may be integrated on the same die or they may be formed on separate dies. The signal processor may include any suitable type of processing circuitry. In some implementations, the signal processor405may include one or more of a switch410, an amplifier420, an analog-to-digital converter (ADC)430, a processor440, and an input/output (I/O) interface450. The switch410may include any suitable type of electronic device that is configured to receive a plurality of signals from the photodiodes112a-iand feed the signals, one at a time, to the amplifier420. The amplifier420may include any suitable type of device that is configured to increase the power of the signals generated by the photodiodes112a-i. The ADC430may include any suitable type of device that is configured to generate a digital representation of an analog signal that is input into the ADC430. The ADC430may include a 16-bit ADC, a 32-bit ADC, a 64-bit ADC, etc. The processor440may include any suitable type of electronic circuitry that is capable of performing one or more arithmetic or logic operations based on values generated by the ADC430. The I/O interface450may include any suitable type of parallel or serial interface, such as a Universal Serial Bus (USB) interface or an I2C interface, etc. In operation, the photodiodes112a-bmay generate a plurality of signals representing the power of different portions of the spectrum of light that is incident on the detector array100. The switch410may switch the signals, such that each of the signals generated by the photodiodes112a-iis supplied to the amplifier420. The amplifier420may amplify each of the signals and feed it to the ADC430. The ADC430may produce a digital representation of each of the signals and supply the digital representation to the processor440. Based on the respective digital representations of the signals generated by the photodiodes112a-i, the processor440may detect a characteristic of light, such as correlated color temperature (CCT) or color. Although in the present example the optoelectronic device includes the processor440, alternative implementations are possible in which the processor440is omitted. In such instances, the digital representations of the signals generated by the photodiodes112a-imay be output from the I/O interface for use by external processing circuitry. Although in the example ofFIG.4, the amplifier420is a 1-channel amplifier, alternative implementations are possible in which the amplifier includes multiple channels. Moreover, in instances in which the amplifier420includes multiple channels, the switch410may be configured to provide multiple signals to the amplifier420in parallel. For example, in instances in which the sensor array100includes 32 detector cells, the amplifier420may be an 8-channel amplifier and the switch410may be configured to feed in parallel signals from8different detector cells to the amplifier. As a result, the processor440(and/or I/O interface450) may receive all signals that are generated by the sensor array100in as little as 4 clock cycles. FIG.5depicts an example of a mathematical operation, which the processor440may be configured to perform, according to aspects of the disclosure. In this example, the processor440may be configured to generate a vector510which identifies the color of light applied to the detector array100in the CIE 1931 color space. As such, the vector510may include tristimulus values X, Y, Z which provide an objective description of color sensation registered in the human eye. Although in the present example the processor440generates a representation of light in the CIE 1394 color space, alternative implementations are possible in which another type of representation is created, such as a representation in the RGB color space or a representation in the YCrCb color space. As illustrated, the vector510may be calculated by multiplying a vector530by a coefficient matrix520. The vector530may include the values Va-Vi which represent the values of the signals generated by different photodiodes in the detector array100. For example, value Va may represent the magnitude of the signal generated by the photodiode112a; value Vb may represent the magnitude of the signal generated by the photodiode112b; value Vc may represent the magnitude of the signal generated by the photodiode112c; value Vd may represent the magnitude of the signal generated by the photodiode112d; value Ve may represent the magnitude of the signal generated by the photodiode112e; value Vf may represent the magnitude of the signal generated by the photodiode112f; value Vg may represent the magnitude of the signal generated by the photodiode112g; value Vh may represent the magnitude of the signal generated by the photodiode112h; and value Vi may represent the magnitude of the signal generated by the photodiode112i. In some implementations, the coefficient matrix520may be a matrix that is pre-stored in a memory (not shown) of the processor440. The coefficient matrix may be calculated by calibrating the optoelectronic device400with a known or standard reference light source. The calibration may be performed by exposing the optoelectronic device400to a calibration light whose color is known, and solving the equation shown inFIG.5for the coefficient matrix520. FIG.6is a schematic diagram of an example of optoelectronic device600, according to aspects of the disclosure. The optoelectronic device includes a detector array610and a signal processor620. The detector array610may include detector cells160a-i, as shown. The detector array610may be the same or similar to the detector array100, except for the sensors cells160a-ibeing arranged in a grid. The signal processor620may be the same or similar to the signal processor405, which is discussed above with respect toFIG.4.FIG.7is a schematic diagram of an example of an optoelectronic device700, according to aspects for the disclosure. The optoelectronic device700may be the same or similar to the optoelectronic device600, but for including an IR-cutoff filter740and an IR-pass filter750, as shown. The IR-cutoff filter740may be disposed over cells160d,160e, and160fof the detector array610and it may be the same or similar to the IR-cutoff filter140. The IR-pass filter750may be disposed over cells160g,160h, and160iof the detector array610and it may be the same or similar to the IR-pass filter150. FIG.8is a flowchart of an example of a process800for manufacturing a detector array, according to aspects of the disclosure. At step805, a photodiode array910is formed. An example of the photodiode array910is shown inFIGS.9A-C. As illustrated, the photodiode array may include photodiodes912a-iformed on a p-substrate940. In some implementations, the photodiodes912a-cmay be the same or similar to the photodiodes112a-c, which are discussed above with respect toFIGS.1A-B. Additionally or alternatively, the photodiodes912d-imay be the same or similar to the photodiodes112d-i, which are discussed above with respect toFIG.1. The photodiodes912a-cmay be p+/n-well diodes and they may be used to detect the power of light emissions in the UV band. Each of the photodiodes912a-cmay include a respective p+ region914that is surrounded on sides and bottom by an n-well region917a, and a p-region918that is disposed under the n-well region917a. The p+ regions914may be the same or similar to the p+ regions114, the n-well region917amay be the same or similar to the n-well region117a, and the p-region918may be the same or similar to the p-region118. The photodiodes912d-imay include n+/P-epi photodiodes and they may be used to detect light in the IR and visible light bands. Each of the photodiodes912d-imay include a respective n+ region915that is surrounded on the sides by the n-well region917b, and a p-region919disposed under the n-well region917band the n+ regions915. The n+ regions915may be the same or similar the n+ regions115, the n-well region(s)917bmay be the same or similar as the n-well region117b, and the p-region919may be the same or similar to the p-region119. At step810, a layer of dielectric light-transmissive material1010is formed over the photodiode array910. An example of the light-transmissive layer1010is shown inFIGS.10A-B. As illustrated, the layer of light-transmissive material may be formed of any suitable type of material, such as silicon dioxide including Borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silica glass (USG) and fluorosilicate glass (FSG) glass materials, etc. In some implementations, the layer of light-transmissive material1010may be formed using plasma-enhanced chemical vapor deposition (PECVD) and/or any other suitable type of process. In some implementations, the layer of light-transmissive material1010may be separated from the photodiode array910by a passivation layer (not shown). The passivation layer may be formed of silicon dioxide SiO2and Silicon Nitride Si3N4. In some implementations, the layer of light-transmissive1010material may have a thickness in the range of 5 um-7.5 um. At step815, a plurality of trenches1110are formed into the layer of light-transmissive material1010to define a plurality of guide members1012. The guide members1012may be the same or similar to the guide members124a-i. An example of the trenches1110is shown inFIGS.11A-C. As illustrated, in some implementations, the trenches1110may be formed above at least a portion of the n-well regions917b. Additionally or alternatively, in some implementations, the trenches1110may be formed above portions of the n-well region917athat are situated between adjacent p+ regions914. Additionally or alternatively, in some implementations, the trenches1110may be formed above portions of the n-well region917bthat are situated between adjacent n+ regions915. The trenches1110may be formed using CMOS or BICMOS back end of line process and/or any other suitable type of process. The trenches1110may have a depth that is less than, greater than, or equal to the thickness of the light-transmissive layer1010. At step820, a light-blocking layer1210is formed in the trenches1110to complete a guide array1120. An example of the light-blocking layer1210and the guide array1220is shown inFIGS.12A-B. The guide array1220may include the guide members1012and the light-blocking layer1210, as shown. The guide array1220may be the same or similar to the guide array120, which is discussed above with respect toFIGS.1A-B. The light-blocking layer1210may be the same or similar to the light-blocking layer122, which is discussed above with respect toFIGS.1A-C. In some implementations, the light-blocking layer1210may have thickness in the range of 4.5 um to 5.5 um for a 3 metal layer process. In some implementations, the light-blocking layer1210may have a greater thickness than the layer of light-transmissive material1010, such that the top surface of the light-blocking layer1210is situated above the top surface of the layer of light-transmissive material1310. At step825, a layer of dielectric light-transmissive material1310is formed over the photodiode array. An example of the layer of light-transmissive material1310is shown inFIGS.13A-B. The layer of light-transmissive material1310may be formed using any suitable type of material, such as a Si3N4material, Al2O3, HfO2, SiO2, TiO2, Nb2O5. In some implementations, low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) may be used to form the layer1310. At step830, a plurality of trenches1410is formed into the layer of light-transmissive material1310. An example of the trenches1410is shown inFIGS.14A-B. As illustrated, in some implementations, the trenches1410may have substantially the same depth and each of the trenches1410may be formed above a different one of the photodiodes912a-i. In some implementations, each of the trenches1410may extend below the level of the top surface of the light-blocking layer1210, as shown. The level of the top surface of the light-blocking layer1210is denoted by a dashed line inFIGS.14A-B. In some implementations, the trenches1410may be formed using low temperature plasma etching or atomic layer precision etching (ALE) systems and/or any other suitable type of process. At step835, a metal layer1510is formed over the layer of light-transmissive material1310. An example of the metal layer1510is shown inFIGS.15A-B. The metal layer1510may be formed of any suitable material, such as silver, aluminum, gold or copper etc. In some implementations, the metal layer may be formed using an alloy including aluminum (Al) and silver (Ag). The metal layer1510may be formed using any suitable type of process, such as thermal evaporation, electron gun deposition with ion assist deposition, and sputter deposition for example. In some implementations, portions of the metal layer1510that are formed on the bottom of the trenches1410may be at least partially situated below the level of the top surface of the light-blocking layer1210. The level of the top surface of the light-blocking layer1210is denoted by a dashed line inFIGS.15A-B. At step840, a layer of dielectric light-transmissive material1610is formed over the metal layer1510. An example, of the layer of light-transmissive material1610is shown inFIGS.16A-B. The layer of light-transmissive material1610may be formed using any suitable type of material, such as a Si3N4material, Al2O3, HfO2, SiO2, TiO2, Nb2O5. In some implementations, low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) may be used to form the layer1610. In some implementations, the layer of light-transmissive material1610may have a thickness in the range of 1200 A to 2500 A. At step845, a plurality of trenches1710is formed into the layer of light-transmissive material1610. An example of the trenches1710is shown inFIGS.17A-B. In some implementations, at least one of the trenches1710may have a different depth than at least one other trench1710. Additionally or alternatively, in some implementations, each of the trenches1710may have a different depth than the rest. Additionally or alternatively, in some implementations, each of the trenches1710may be formed over a different one of the photodiodes912a-iin the photodiode array910, as shown. In some implementations, the trenches1710may be formed using low temperature plasma etching or atomic layer precision etching (ALE) systems and/or any other suitable type of process. At step850, a metal layer1810is formed over the light-transmissive layer1610and the trenches1710, as shown. An example of the metal layer1810is shown inFIGS.18A-B. In some implementations, the metal layer1810may be formed of an alloy including aluminum (Al) and silver (Ag). In some implementations, the metal layer1810may be formed using silver, aluminum, gold, copper and/or any other suitable type of material. The metal layer1510may be formed using any suitable type of process, such as thermal evaporation, electron gun deposition with ion assist deposition, and sputter deposition for example. In some implementations, the layer1810may have a thickness in the range of 400 A to 600 A depending on the bandwidth requirement of the band pass filter design. At step855, a layer of light-transmissive material1905is formed over the metal layer1810to complete a filter array1910. An example of the filter array1910is shown inFIGS.19A-B. In some implementations, the layer of light-transmissive material1905may be formed using any suitable type of material, such as a Si3N4material, Al2O3, HfO2, SiO2, TiO2, Nb2O5. In some implementations, low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) may be used to form the layer1905. Apart for using continuous metal layers to form different Fabry-Perot cavities, the filter array1910may be the same or similar to the filter array130, which is discussed above with respect toFIGS.1A-B. FIGS.19A-Bshow an example of a resultant detector array1920that is produced as a result of performing steps805-855of the process800. As illustrated, the detector array1920may include plurality of detector cells160a-i. As the numbering suggests, the detector cells in the detector array1920may be similar to the detector cells in the detector array100and the detector cells in the detector array610, which are discussed above with respect toFIGS.1A-Band6. As noted above, in some implementations, the detector cells160a-cmay be arranged to measure the energy of light emissions in the UV band, the cells160d-fmay be arranged to measure the energy of light emissions in the visible light band, and the cells160g-imay be arranged to measure the energy of light in the IR band. At step860, an IR-cutoff filter2010is formed over the detector cells160d-fof the detector array1720and an IR-pass filter2020is formed over the detector cells160g-iof the detector array1920to complete an optoelectronic device2030. In some implementations, the IR-cutoff filter2010may be the same or similar to the IR-cutoff filter140. Additionally or alternatively, in some implementations, the IR-cutoff filter2010may be the same or similar to the IR-pass filter150. An example of the filters2010and2020is shown inFIGS.20A-B. FIGS.1-20Bare provided as an example only. At least some of the elements discussed with respect to these figures can be arranged in different order, combined, and/or altogether omitted. It will be understood that the provision of the examples described herein, as well as clauses phrased as “such as,” “e.g.”, “including”, “in some aspects,” “in some implementations,” and the like should not be interpreted as limiting the disclosed subject matter to the specific examples. By way of example, in some implementations, the term “light-transmissive material” may refer to any material having a light transmissivity greater than 80% to 95%. By way of example, in some implementations, that the term “light-blocking material” may refer to any material having a light transmissivity less than 2% to 0.1%. It will be further understood that the values for the thicknesses of various elements of the disclosed device(s) are provided as an example only, and the disclosure is not limited in any way to those values. It will be further understood that the materials and processes used to form various components of the disclosed device(s) are provided as an example only, and the disclosure is not limited in any way to those materials and/or processes. Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concepts described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described. | 45,226 |
11862649 | MODE FOR CARRYING OUT THE INVENTION Embodiments will be described below with reference to the drawings. However, the embodiments can be implemented with many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Therefore, the present invention should not be construed as being limited to the description of embodiments below. A plurality of embodiments described below can be combined as appropriate. In addition, in the case where a plurality of structure examples are described in one embodiment, the structure examples can be combined as appropriate. Note that in the drawings attached to this specification, the block diagram in which components are classified according to their functions and shown as independent blocks is illustrated; however, it is difficult to separate actual components completely according to their functions, and it is possible for one component to relate to a plurality of functions. In the drawings and the like, the size, the layer thickness, the region, or the like is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. Note that the drawings are schematic views illustrating ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. Moreover, the same components or components having similar functions, components formed using the same material, components formed at the same time, or the like in the drawings are denoted by the same reference numerals in some cases, and the repeated description thereof is omitted in some cases. Moreover, in this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Alternatively, for example, the term “insulating film” can be changed into the term “insulating layer” in some cases. In this specification and the like, the terms for describing arrangement such as “over” and “below” do not necessarily mean “directly over” and “directly below”, respectively, in the positional relationship between components. For example, the expression “a gate electrode over a gate insulating layer (gate terminal, gate region or gate electrode)” does not exclude the case where there is an additional component between the gate insulating layer and the gate electrode. In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically. In this specification and the like, “electrically connected” includes the case where connection is made through an “object having any electric function”. Here, there is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between the connected components. Examples of the “object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements with a variety of functions as well as an electrode and a wiring. In this specification and the like, “voltage” often refers to a potential difference between a given potential and a reference potential (e.g., a ground potential). Thus, a voltage and a potential difference can be interchanged with each other. In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. The transistor includes a channel formation region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel region refers to a region through which current mainly flows. Functions of a source and a drain might be interchanged with each other when a transistor of opposite polarity is employed or when the direction of current is changed in circuit operation, for example. Thus, the terms of a source and a drain are interchangeable for use in this specification and the like. Furthermore, unless otherwise specified, off-state current in this specification and the like refers to drain current of a transistor in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, the off state of an n-channel transistor refers to a state where voltage Vgs of a gate with respect to a source is lower than a threshold voltage Vth, and the off state of a p-channel transistor refers to a state where the voltage Vgs of a gate with respect to a source is higher than the threshold voltage Vth. That is, the off-state current of an n-channel transistor sometimes refers to a drain current at the time when the voltage Vgs of a gate with respect to a source is lower than the threshold voltage Vth. In the above description of off-state current, the drain may be replaced with the source. That is, the off-state current sometimes refers to a source current when the transistor is in an off state. In addition, leakage current sometimes expresses the same meaning as off-state current. In this specification and the like, the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is in the off state. In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor, and the like. For example, in the case where a metal oxide is used in a channel formation region of a transistor, the metal oxide is called an oxide semiconductor in some cases. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be called a metal oxide semiconductor In other words, a transistor containing a metal oxide in a channel formation region can be referred to as an “oxide semiconductor transistor” or an “OS transistor”. Similarly, the “transistor using an oxide semiconductor” described above is also a transistor containing a metal oxide in a channel formation region. Furthermore, in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride. The details of a metal oxide will be described later. Embodiment 1 In this embodiment, an imaging device of one embodiment of the present invention is described with reference to drawings. One embodiment of the present invention is an imaging device including a pixel where a photoelectric conversion element and n (n is an integer more than or equal to 2) retention circuits are provided. The photoelectric conversion element and the n retention circuits are stacked with each other. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits have a function of retaining imaging data. The retention circuits includes an OS transistor having a characteristic of extremely low off-state current, and can retain imaging data for a long time. In this specification and the like, imaging data is data corresponding to the illuminance of light emitted to the photoelectric conversion element. The imaging device of one embodiment of the present invention has a function of obtaining imaging data to write it to the retention circuits. The imaging device of one embodiment of the present invention also has a function of reading the imaging data out retained in the retention circuits, performing analog-to-digital conversion (hereinafter AD conversion), and outputting the imaging data outside the imaging device. An operation method of the imaging device of one embodiment of the present invention is described below. First, in the first period, the imaging device obtains the first imaging data and writes it to the first retention circuit. Similarly, in the second to n-th periods, the imaging device obtains the second to n-th imaging data and writes them to the second to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. AD conversion is performed on the read imaging data and the imaging data is output outside the imaging device as described above. The above is an operation method of the imaging device of one embodiment of the present invention. As described above, the retention circuit included in the imaging device of one embodiment of the present invention can retain the imaging data for a long time. The imaging device obtains one imaging data and writes it to the retention circuit; the imaging data is not needed to be read out immediately after writing. Rather, n imaging data (the first to n-th imaging data) are obtained, and then the imaging data can be read out. That is, n imaging data can be read out collectively. A plurality of imaging data can be obtained in a short period compared to the case where one imaging data is obtained and read out alternately. The imaging device of one embodiment of the present invention can be used for a high-speed camera, for example. In addition, when imaging data are collectively read out, n imaging data can be obtained in a short period even though the imaging data are not rapidly read out. Accordingly, a plurality of imaging data can be obtained in a short period, and the power consumption of the imaging device of one embodiment of the present invention can be reduced. As described above, the first to n-th retention circuits of the imaging device of one embodiment of the present invention are stacked. Thus, even when n imaging data are collectively read out, imaging data corresponding to an image with the same level of resolution when imaging data is read out one by one can be obtained. Therefore, the imaging device of one embodiment of the present invention can achieve both obtaining a plurality of imaging data in a short period and obtaining imaging data corresponding to a high-resolution image. Structure Example 1 of Imaging Device FIG.1is a block diagram showing a structure example of an imaging device10that is the imaging device of one embodiment of the present invention. The imaging device10includes a layer20and n layers30(n is an integer more than or equal to 2) provided over the layer20. That is, the layer20and the n layers30are stacked. In this specification and the like, each of the n layers30is distinguished by describing each as a layer30_1to a layer30_n. For example, in the n layers30, the bottom layer30is described as the layer30_1, and the layer30_2to the layer30_nare provided upwards in this order. Note that in the n layers30, the uppermost layer30may be described as the layer30_1, and the layer30_2to the layer30_nmay be provided downwards in this order. In addition, when “_i” is added to reference numerals of components such as a circuit provided to the layer30_i(i is an integer within the range of 1 to n), the layer30to which the components are provided is denoted. Photoelectric conversion elements21are arranged in a matrix in the layer20. For the photoelectric conversion elements21, a photodiode can be used. When light is emitted to the photoelectric conversion elements21, electric charge corresponding to the illuminance of the light is accumulated. The layer30includes an imaging portion31, a gate driver circuit33, a source driver circuit34, and an AD conversion circuit35. The imaging portion31includes retention circuits32arranged in a matrix. The gate driver circuit33and the source driver circuit34can have a structure in which a shift register circuit is included, for example. The retention circuits32in as many columns and rows as the photoelectric conversion elements21are provided to the layer30, for example. The imaging device10includes n layers30, and the retention circuits32_ntimes as many as the photoelectric conversion elements21can be provided to the imaging device10. The retention circuit32can be provided to include a region overlapping with the photoelectric conversion element21. In one layer30, one gate driver circuit33, one source driver circuit34, and one AD conversion circuit35can be provided, for example. In that case, in the imaging device10, n gate driver circuits33, n source driver circuits34, and n AD conversion circuits35are provided. Note that at least two gate driver circuits33, at least two source driver circuits34, and/or at least two AD conversion circuits35may be provided in one layer30. One electrode of the photoelectric conversion element21is electrically connected to the retention circuit32_1to the retention circuit32_n. For example, the one electrode of the photoelectric conversion element21is electrically connected to the retention circuit32_1to the retention circuit32_nwhich have a region overlapping with the photoelectric conversion element21. The gate driver circuit33is electrically connected to the retention circuit32. The AD conversion circuit35is electrically connected to the retention circuit32through a wiring40. The source driver circuit34is electrically connected to the AD conversion circuit35. The retention circuit32_1to the retention circuit32_ncan be provided to have a region overlapping with each other. One photoelectric conversion element21and the retention circuit32_1to the retention circuit32_nwhich have a region overlapping with each other constitute one pixel. A gate driver circuit33_1to a gate driver circuit33_ncan be provided to have a region overlapping with each other. A source driver circuit34_1to a source driver circuit34_ncan be provided to have a region overlapping with each other. An AD conversion circuit35_1to an AD conversion circuit35_ncan be provided to have a region overlapping with each other. The retention circuit32has a function of retaining imaging data. The gate driver circuit33has a function of generating a selection signal for controlling the operation of the retention circuits32. The selection signal is supplied to the retention circuits32, so that the retention circuits32to which imaging data is written and the retention circuits32from which imaging data is read out can be selected. The gate driver circuit33can select the retention circuits32row by row. The source driver circuit34has a function of selecting the retention circuits32from which retained imaging data is read out, for example. The source driver circuit34can select the retention circuits32column by column. Thus, the imaging data retained in the retention circuit32in the row selected by the gate driver circuit33and the column selected by the source driver circuit34can be read out. The AD conversion circuit35has a function of converting imaging data that is analog data read out from the retention circuit32into digital data and outputting the digital data outside the imaging device10as a signal OUT. The signal OUT can be output to a display device, for example. Alternatively, the signal OUT can be output to a memory device, a communication device, or the like. Note that the imaging data read out from the retention circuit32are supplied to the AD conversion circuit35through the wiring40. It can be said that the wiring40has a function of a data line. Structure Example of Retention Circuit FIG.2is a circuit diagram showing a structure example of the retention circuit32and the connection relation between the photoelectric conversion element21and the retention circuit32. The retention circuit32includes a transistor12, a transistor13, a transistor14, a transistor15, and a capacitor16. Note that the capacitor16is not necessarily provided. One electrode of the photoelectric conversion element21is electrically connected to one of a source and a drain of the transistor12. The other of the source and the drain of the transistor12is electrically connected to one of a source and a drain of the transistor13. The one of the source and the drain of the transistor13is electrically connected to a gate of the transistor14. The gate of the transistor14is electrically connected to one electrode of the capacitor16. One of a source and a drain of the transistor14is electrically connected to one of a source and a drain of the transistor15. Note that althoughFIG.2shows a structure in which a cathode of the photoelectric conversion element21is electrically connected to the one of the source and the drain of the transistor12and an anode of the photoelectric conversion element21is electrically connected to a wiring47, the anode of the photoelectric conversion element21may be electrically connected to the one of the source and the drain of the transistor12and the cathode of the photoelectric conversion element21may be electrically connected to the wiring47. The point where the other of the source and the drain of the transistor12, one of a source and a drain of the transistor13, a gate of the transistor14, and one electrode of the capacitor16are connected is a node FD. A gate of the transistor12is electrically connected to a wiring41. A gate of the transistor13is electrically connected to the wiring42. A gate of the transistor15is electrically connected to the wiring43. The other of the source and the drain of the transistor13is electrically connected to a wiring44. The other of the source and the drain of the transistor14is electrically connected to the wiring40. The other of the source and the drain of the transistor15is electrically connected to a wiring45. The other electrode of the capacitor16is electrically connected to a wiring46. The other electrode of the photoelectric conversion element21is electrically connected to the wiring47. A wiring41, a wiring42, and a wiring43have a function of a scan line for controlling on/off of the transistor12, the transistor13, and the transistor15respectively, and are electrically connected to the gate driver circuit33which is not shown inFIG.2. A constant potential can be supplied to the wiring44to the wiring47. For instance, a power supply potential can be supplied. In this case, the wiring44to the wiring47have a function of power supply lines. For example, a high potential can be supplied to the wiring44and the wiring45and a low potential can be supplied to the wiring46and the wiring47. The potential supplied to the wiring44is a potential VR. In the case where the anode of the photoelectric conversion element21is electrically connected to the one of the source and the drain of the transistor12and the cathode of the photoelectric conversion element21is electrically connected to the wiring47, a high potential can be supplied to the wiring45and the wiring47, and a low potential can be supplied to the wiring44and the wiring46. In this specification and the like, a low potential can be a ground potential or a negative potential, for example. A high potential can be a potential higher than a low potential. The transistor12functions as a transfer transistor which controls transfer to the node FD of the electric charge accumulated in the photoelectric conversion element21by exposing the photoelectric conversion element21to light. By turning the transistor12on, the electric charge accumulated in the photoelectric conversion element21is transferred to the node FD. Thus, the potential of the node FD is set to a potential depending on the illuminance of light emitted to the photoelectric conversion element21, and imaging data is written to the retention circuit32. Then, the transistor12is turned off, whereby imaging data written to the retention circuit32is retained. The transistor13has a function as a reset transistor which controls resetting the potential of the node FD. When the transistor12and the transistor13are turned on before exposure of the photoelectric conversion element21to light is started, the electric charge accumulated in the photoelectric conversion element21and the node FD can be reset. Accordingly, the potential of the node FD can be reset to the potential VR, for example. The transistor14has a function of an amplifier transistor that amplifies the imaging data retained in the retention circuit32. The transistor15has a function of controlling reading of imaging data retained in the retention circuit32. When the transistor15is turned on, the potential of the wiring45is supplied to the one of the source and drain of the transistor14, and a current depending on the potential of the node FD flows into the transistor14. Thus, the imaging data retained in the retention circuit32is read out. As described above, the transistor15can be said to have a function of a selection transistor that selects the retention circuit32where imaging data is read out. The transistor12and the transistor13are preferably transistors having an extremely low off-state current. Accordingly, the leakage of the electric charge accumulated in the node FD can be suppressed; the potential of the node FD can be held for a long time. Imaging data can be retained in the retention circuit32for a long time. Thus, when imaging data is written to the retention circuit32, the imaging data need not to be read out immediately after writing. An OS transistor can be given as an example of a transistor having an extremely low off-state current. An OS transistor is characterized by a high withstand voltage. Thus, the use of an OS transistor as the transistor12in particular allows a high voltage to be supplied to the photoelectric conversion element21. The transistor12to the transistor15are provided in the layer30. That is, the transistor12to the transistor15can be provided in the same layer. The transistor12to the transistor15can have the same structure. For example, all the transistor12to the transistor15can be OS transistors. FIG.3is a diagram showing a stacked structure example of the photoelectric conversion element21and the retention circuits32, and is a diagram of the structure example of the pixel included in the imaging device10. InFIG.3, n is 2 for clarification of the drawing and ease of the explanation thereof. That is,FIG.3shows the photoelectric conversion element21, the retention circuit32_1, and the retention circuit32_2. Note that n may be 2 in the following drawings and the like. As shown inFIG.3, the retention circuit32_1and the retention circuit32_2can have a similar structure. Since the retention circuit32_1to the retention circuit32_ncan have a similar structure, the retention circuit32_1and the retention circuit32_2can be manufactured with the same masks. Thus, even when n is increased, an increase in the number of masks used for manufacturing the imaging device10can be suppressed. That is, even when the number of layers30is increased, an increase in the number of masks used for manufacturing the imaging device10can be suppressed. Thus, even when the number of layers30is increased, a drastic increase of manufacturing cost for the imaging device10can be suppressed and the imaging device10can be inexpensive. Operation Method Example 1 of Imaging Device FIG.4is a timing chart showing an operation method example of the imaging device10when a pixel has the structure shown inFIG.3. InFIG.4, “H” shows a high potential and “L” shows a low potential. This may apply to the other drawings. In the operation method shown inFIG.4, all the transistor12to the transistor15are n-channel transistors, but any or all of the transistor12to the transistor15can be p-channel transistors. Even in this case, the operation method shown inFIG.4can be referred to when high potentials and low potentials are interchanged appropriately. In the period T01, the potential of a wiring41_1and the potential of a wiring42_1are set to a high potential. The potential of a wiring41_2, the potential of a wiring42_2, the potential of a wiring43_1, and the potential of a wiring43_2are set to a low potential. This turns a transistor12_1and a transistor13_1on, and resets the electric charge accumulated in the photoelectric conversion element21and a node FD_1. This reset the potential of a node FD_2to the potential VR (reset operation). In the period T02, the potential of the wiring42_1is set to a low potential. This turns the transistor13_1off and transfers the electric charge accumulated in the photoelectric conversion element21depending on the illuminance of light emitted to the photoelectric conversion element21to the node FD_1. Thus, the potential of the node FD_1is changed depending on the illuminance of light emitted to the photoelectric conversion element21(exposure operation). Accordingly, imaging data is obtained by the imaging device10, and the imaging data is written to the retention circuit32_1. Specifically, one imaging data is written to the retention circuit32_1. In this specification and the like, the imaging data written to the retention circuit32_1may be referred to as the first imaging data, for example. In the period T03, the potential of the wiring41_1is set to a low potential. This turns the transistor12_1off and finishes the exposure operation, so that the potential of the node FD_1is retained. In other words, the imaging data is retained in the retention circuit32_1(retention operation). In the period T04, the potential of the wiring41_2and the potential of the wiring42_2are set to a high potential. This turns a transistor12_2and a transistor13_2on, and resets the electric charge accumulated in the photoelectric conversion element21and the node FD_2. This resets the potential of the node FD_2to the potential VR (reset operation). In the period T05, the potential of the wiring42_2is set to a low potential. This turns the transistor13_2off and transfers the electric charge accumulated in the photoelectric conversion element21depending on the illuminance of light emitted to the photoelectric conversion element21to the node FD_2. This changes the potential of the node FD_2depending on the illuminance of light emitted to the photoelectric conversion element21(exposure operation). Accordingly, imaging data is obtained by the imaging device10, and the imaging data is written to the retention circuit32_2. In the period T06, the potential of the wiring41_2is set to a low potential. This turns the transistor12_2off and finishes the exposure operation, so that the potential of the node FD_2is retained. In other words, the imaging data is retained in the retention circuit32_2(retention operation). In the period T07, the potential of the wiring43_1and the potential of the wiring43_2are set to a high potential. This turns a transistor15_1and a transistor15_2on, sets the potential of the wiring40_1to a potential corresponding to the potential of the node FD_1, and sets the potential of the wiring40_2to a potential corresponding to the potential of the node FD_2. In other words, the imaging data retained in the retention circuit32_1and the imaging data retained in the retention circuit32_2are read out (read operation). The imaging data read out from the retention circuit32_1is converted into digital data by the AD conversion circuit35_1and output to the outside of the imaging device10as a signal OUT_1. The imaging data read out from the retention circuit32_2is converted into digital data by the AD conversion circuit35_2and output outside the imaging device10as a signal OUT2. Note that inFIG.4, the digital signal corresponding to the imaging data read out from the retention circuit32_1is shown as IS_1, and the digital signal corresponding to the imaging data read out from the retention circuit32_2is shown as IS_2. This may apply to the other drawings. In the period T08, the potential of the wiring43_1and the potential of the wiring43_2are set to a low potential. This turns the transistor15_1and the transistor15_2off and finishes the read operation. The above is an example of the operation method of the imaging device10. As described above, in the period T07, the imaging data retained in the retention circuit32_1and the imaging data retained in the retention circuit32_2are read out. Accordingly, in the operation method inFIG.4, the imaging data held in the retention circuit32_1and imaging data held in the retention circuit32_2are said to be read out at the same time. As described above, the retention circuit32can retain the imaging data for a long time. Accordingly, it is unnecessary to read out the imaging data from the retention circuit32_1immediately after the imaging device10obtains one imaging data and write it to the retention circuit32_1. Rather, the imaging data can be read out after n imaging data (n=2 inFIG.4) are obtained. That is, the n imaging data can be read out collectively. Thus, the imaging device10can obtain a plurality of imaging data in a short period compared to the case where one imaging data is obtained and read out alternately. Thus, the imaging device of one embodiment of the present invention can be used for a high-speed camera, for example. In addition, when imaging data are collectively read out, n imaging data can be obtained in a short period even though the imaging data are not rapidly read out. Accordingly, a plurality of imaging data can be obtained in a short period, and the power consumption of the imaging device10can be reduced. As described above, the retention circuit32_1to the retention circuit32_nare stacked. Thus, even when n imaging data are collectively read out, imaging data corresponding to a similar resolution image obtained when imaging data is read out one by one can be obtained. Therefore, the imaging device10can achieve both obtaining a plurality of imaging data in a short period and obtaining imaging data corresponding to a high-resolution image. Structure Example 2 of Imaging Device FIG.5is a block diagram showing a structure example of the imaging device10and a variation example ofFIG.1. In the imaging device10inFIG.1, the gate driver circuit33, the source driver circuit34, and the AD conversion circuit35are provided in the layer30. On the other hand, in the imaging device10inFIG.5, the gate driver circuit33, the source driver circuit34, and the AD conversion circuit35are provided in the layer20. In the layer20of the imaging device10having the structure inFIG.5, a demultiplexer circuit36and a multiplexer circuit37are provided. An input terminal of the demultiplexer circuit36is electrically connected to the gate driver circuit33. Output terminals of the demultiplexer circuit36are electrically connected to the retention circuits32. Specifically, the output terminals of the demultiplexer circuit36are electrically connected to the wiring41to the wiring43shown inFIG.3and other drawings. Thus, the demultiplexer circuit36can be said to be provided between the gate driver circuit33and the retention circuits32. Input terminals of the multiplexer circuit37are electrically connected to the retention circuits32through the wirings40. An output terminal of the multiplexer circuit37is electrically connected to the AD conversion circuit35. The multiplexer circuit37can be said to be provided between the retention circuit32and the AD conversion circuit35. The demultiplexer circuit36has a function of allocating a selection signal generated by the gate driver circuit33to any one of the retention circuit32_1to the retention circuit32_n. The multiplexer circuit37has a function of selecting imaging data read out from the retention circuit32_1to the retention circuit32_nto provide to the AD conversion circuit35. Note that inFIG.5, n is 2. When the imaging device10has a structure including the demultiplexer circuit36and the multiplexer circuit37, the number of gate driver circuits33, the number of source driver circuits34, and the number of AD conversion circuits35can be smaller than n. For example, as shown inFIG.5, one gate driver circuit33, one source driver circuit34, and one AD conversion circuit35can be provided in the layer20. Note that at least two gate driver circuits33, at least two source driver circuits34, and/or at least two AD conversion circuits35may be provided in the layer20. The number of gate driver circuits33, the number of source driver circuits34, and the number of AD conversion circuits35included in the imaging device10are reduced, whereby the imaging device10can have low power consumption. Note that any of the gate driver circuit33, the source driver circuit34, and the AD conversion circuit35may be provided in the layer30. For example, the gate driver circuit33may be provided in the layer30, and the source driver circuit34and the AD conversion circuit35may be provided in the layer20. In that case, the demultiplexer circuit36is not needed to be provided in the imaging device10. Operation Method Example 2 of Imaging Device FIG.6is a timing chart showing an operation method example of the imaging device10in the case where the pixel has the structure shown inFIG.3and the imaging device10has the structure shown inFIG.5. Here, the operations within the period T11to the period T16inFIG.6are the same as the operations within the period T01to the period T06inFIG.4. In the period T17, the potential of the wiring43_1is set to a high potential. This turns the transistor15_1on and sets the potential of the wiring40_1to the potential corresponding to the potential of the node FD_1. In other words, the imaging data retained in the retention circuit32_1is read out (read operation). The imaging data read out from the retention circuit32_1is supplied to the AD conversion circuit35through the multiplexer circuit37and converted into digital data by the AD conversion circuit35. The digital data is output as the signal OUT outside the imaging device10. That is, the signal IS_1is output outside the imaging device10from the AD conversion circuit35. In the period T18, the potential of the wiring43_1is set to a low potential. This turns the transistor15_1off and finishes the read operation of the imaging data retained in the retention circuit32_1. In the period T19, the potential of the wiring43_2is set to a high potential. This turns the transistor15_2on and sets the potential of the wiring40_2to the potential corresponding to the potential of the node FD_2. In other words, the imaging data retained in the retention circuit32_2is read out (read operation). The imaging data read out from the retention circuit32_2is supplied to the AD conversion circuit35through the multiplexer circuit37and converted into digital data by the AD conversion circuit35. The digital data is output as the signal OUT outside the imaging device10. That is, the signal IS_2is output outside the imaging device10from the AD conversion circuit35. In the period T20, the potential of the wiring43_2is set to a low potential. This turns the transistor152off and finishes the read operation of the imaging data retained in the retention circuit32_2. The above is an example of the operation method of the imaging device10. As described above, in the period T17, the imaging data retained in the retention circuit32_1is read out and in the period T18, the imaging data retained in the retention circuit32_2is read out. Accordingly, in the operation method inFIG.6, the imaging data held in the retention circuit32_1and the imaging data held in the retention circuit32_2are said to be sequentially read out. The operation method shown inFIG.6takes more time to read out imaging data than the case of reading out imaging data at the same time as shown inFIG.4because imaging data are sequentially read out. However, in the operation method inFIG.6, imaging data can be read out after n imaging data are obtained as in the operation method shown inFIG.4. Thus, even when the imaging device10is operated with the operation method shown inFIG.6, the imaging device10can obtain a plurality of imaging data in a short period as in the case where the imaging device10is operated with the operation method shown inFIG.4. As described above, the retention circuit32can retain imaging data for a long time. Therefore, even when imaging data are sequentially read out, image quality corresponding to the imaging data which are read out is inhibited from decreasing than that when imaging data are collectively read out. Structure Example 3 of Imaging Device FIG.7is a block diagram showing a structure example of an imaging device10and a variation example ofFIG.1. The imaging device10inFIG.1includes the layers30including the retention circuits32over the layer20including the photoelectric conversion element21. On the other hand, the imaging device10inFIG.7includes the layers30including the retention circuits32under the layer20, which is different from the structure inFIG.1. Operation Mode of Imaging Device FIGS.8(A) and8(B)are diagrams showing operation methods of the retention circuits32_i(i is an integer within the range of 1 to n) arranged in a matrix in the imaging device10. In other words,FIGS.8(A) and3(B)are diagrams showing operation methods of the retention circuits32when the retention circuit32arranged in a matrix in one layer30are focused. FIG.8(A)is a diagram showing a rolling shutter mode and an exposure operation51, a retention operation52, and a read operation53are performed on the retention circuits32_irow by row.FIG.8(B)is a diagram showing a global shutter mode; the exposure operation51is concurrently performed on all the retention circuits32_iin all rows and the read operation53is sequentially performed row by row. When a rolling shutter mode is employed, an image is distorted when an object moves since simultaneousness of imaging is lost. On the other hand, when a global shutter mode is employed, an image with few distortions can be easily obtained even though an object moves since simultaneousness of imaging is secured. Thus, the imaging device10can obtain imaging data corresponding to a high-quality image through the use of the global shutter mode. In contrast, the larger the row number of the retention circuits32_ibecomes, the longer the period of the retention operation52becomes when a global shutter mode is employed, as shown inFIG.8(B). However, as described above, when the retention circuits32have a structure including a transistor with extremely low off-state current such as an OS transistor, the retention circuits32can retain imaging data for a long time. Therefore, a global shutter mode can be employed. In the above manner, imaging data corresponding to a high-quality image can be obtained by the imaging device10. Structure Example 1 of Pixel FIG.9is a diagram showing a specific structure example of a pixel included in the imaging device10and shows a cross-sectional structure example of the photoelectric conversion element21and cross-sectional structure examples of the transistor12_1, the transistor13_1, the transistor12_2, and the transistor13_2in the channel length direction. Here, inFIG.9, the transistor12and the transistor13are OS transistors. In some cases, some of the conductive layers, insulating layers, and the like shown in the drawing is not provided, or conductive layers, insulating layers, and the like that are not shown in the drawing are included in each layer. InFIG.9, the layers30are provided over the layer20. Thus, the structure inFIG.9can be used in, for example, the imaging device10having the structure inFIG.1. In the pixel having the structure shown inFIG.9, the photoelectric conversion element21is provided over an insulating layer102. The insulating layer102can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride. Note that the same material as the insulating layer102can be used for other insulating layers inFIG.9. A two-terminal photodiode can be used for the photoelectric conversion element21, for example. As the photodiode, a pn-type photodiode using single crystal silicon, a pin-type photodiode using an amorphous silicon thin film, a microcrystalline silicon thin film, or a polycrystalline silicon thin film, a photodiode using selenium, a selenium compound, or an organic compound, or the like can be used. FIG.9shows a structure example in which the photoelectric conversion element21is a pn photodiode using a single crystal silicon substrate. The photoelectric conversion element21having a structure shown inFIG.9can include a region104, a region106, a region108, and a region110. For example, the region104can be a p+ region, the region106can be a p− region, the region108can be an n region, and the region110can be a p+ region. An insulating layer112is provided over the photoelectric conversion element21, and an insulating layer114is provided over the insulating layer112. The insulating layer112can have a function of a planarization film, for eliminating level differences caused by the photoelectric conversion element21and the like provided in the underlying surface. For example, the top surface of the insulating layer112may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity. The insulating layer114is preferably formed using a film having a barrier property that prevents diffusion of impurities such as hydrogen from the photoelectric conversion element21and the like to the transistor12_1to the transistor15_1and the like which are provided in the retention circuit32_1. Note that the transistor14_1and the transistor15_1are not shown inFIG.9. As an example of the film having a barrier property against hydrogen, silicon nitride formed by, for example, a chemical vapor deposition (CVD) method can be given. Diffusion of hydrogen into an OS transistor that can be used as the transistor12and the transistor13may degrade the performance of the OS transistor. A film that inhibits hydrogen diffusion is preferably provided between the photoelectric conversion element21and the transistors12_1and13_1. The film that inhibits hydrogen diffusion is specifically a film from which a small amount of hydrogen is released. The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulating layer114that is converted into hydrogen atoms per area of the insulator324is less than or equal to 10×1015atoms/cm2, preferably less than or equal to 5×1015atoms/cm2, in the TDS analysis in a film-surface temperature range of 50° C. to 500° C., for example. An insulating layer116_1is provided over the insulating layer114, and the transistor12_1and the transistor13_1are provided over the insulating layer116_1. FIG.10(A)is a cross-sectional view of a transistor300in the channel length direction that can be used as the transistor12and the transistor13, andFIG.10(B)is a cross-sectional view of the transistor300in the channel width direction. The transistor300includes an insulating layer118over an insulating layer116, an insulating layer120over the insulating layer118, an insulating layer122over the insulating layer120, a metal oxide330aover the insulating layer122, a metal oxide330bover the metal oxide330a, a conductive layer342aand a conductive layer342bseparately provided from each other over the metal oxide330b, an insulating layer124over the insulating layer342aand the insulating layer342bin which an opening is formed overlapping with the region between the conductive layer342aand the conductive layer342b, a conductive layer360in the opening, an insulating layer350between the conductive layer360and the metal oxide330b, the conductive layer342a, the conductive layer342b, and the insulating layer124, and a metal oxide330cbetween the conductive layer350and the metal oxide330b, the conductive layer342a, the conductive layer342b, and the insulating layer124. As shown inFIGS.10(A) and10(B), an insulating layer123is preferably positioned between the insulating layer124and the metal oxide330a, the metal oxide330b, the conductive layer342a, and the conductive layer342b. As shown inFIGS.10(A) and10(B), the conductive layer360preferably includes a conductive layer360aprovided inside the insulating layer350and a conductive layer360bembedded in the conductive layer360a. As shown inFIGS.10(A) and10(B), an insulating layer126is preferably positioned over the insulating layer124, the conductive layer360, and the insulating layer350. Hereinafter, the metal oxide330a, the metal oxide330b, and the metal oxide330cmay be collectively referred to as a metal oxide330. The conductive layer342aand the conductive layer342bmay be collectively referred to as a conductive layer342in some cases. The transistor300has a structure in which three layers of the metal oxide330a, the metal oxide330b, and the metal oxide330care stacked in the region where the channel is formed and its vicinity; however, the present invention is not limited thereto. For example, a single layer of the metal oxide330b, a two-layer structure of the metal oxide330band the metal oxide330a, a two-layer structure of the metal oxide330band the metal oxide330c, or a stacked-layer structure of four or more layers may be provided. Although the transistor300has a structure in which the conductive layer360has a stacked-layer structure of two layers, the present invention is not limited thereto. For example, the conductive layer360may have a single-layer structure or a stacked-layer structure of three or more layers. Note that the transistor300shown inFIGS.10(A) and10(B)is an example, and the structure is not limited thereto; an appropriate transistor can be used in accordance with a circuit structure or a driving method. The conductive layer360has a function of a gate of the transistor300. The conductive layer342ahas a function of one of a source and a drain of the transistor300, and the conductive layer342bhas a function of the other of the source and the drain of the transistor300. As described above, the conductive layer360is formed to fill in the opening of the insulating layer124and the region between the conductive layer342aand the conductive layer342b. The positions of the conductive layer360, the conductive layer342a, and the conductive layer342bare selected in a self-aligned manner with respect to the opening of the insulating layer124. That is, in the transistor300, the gate can be positioned between the source and the drain in a self-aligned manner Therefore, the conductive layer360can be formed without an alignment margin, resulting in a reduction in the area occupied by the transistor300. Accordingly, miniaturization and high integration of the imaging device can be achieved. In addition, since the conductive layer360is formed in the region between the conductive layer342aand the conductive layer342bin a self-aligned manner, the conductive layer360does not have a region overlapping with the conductive layer342aor the conductive layer342b. Thus, parasitic capacitance formed between the conductive layer360and each of the conductive layer342aand the conductive layer342bcan be reduced. This improves the switching speed of the transistor300, whereby the frequency characteristics of one embodiment of the present invention can be improved. The insulating layer350has a function of a gate insulating film. Here, as the insulating layer122in contact with the metal oxide330, an insulator that contains oxygen more than oxygen in the stoichiometric composition is preferably used. That is, an excess-oxygen region is preferably formed in the insulating layer122. When such an insulator containing excess oxygen is provided in contact with the metal oxide330, oxygen vacancies in the metal oxide330can be reduced and the reliability of the transistor300can be improved. As the insulator including an excess-oxygen region, specifically, an oxide material that releases part of oxygen by heating is preferably used. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 1.0×1019atoms/cm3, further preferably greater than or equal to 2.0×1019atoms/cm3or greater than or equal to 3.0×1020atoms/cm3in TDS analysis. Note that the temperature of the film surface in the TDS analysis is preferably within the range of 100° C. to 700° C., or within the range of 100° C. to 400° C. In the case where the insulating layer122includes an excess-oxygen region, the insulating layer120preferably has a function of inhibiting diffusion of oxygen (e.g., an oxygen atom or an oxygen molecule) (or the insulating layer122is less likely to transmit oxygen). When the insulating layer120has a function of inhibiting diffusion of oxygen or impurities, oxygen contained in the metal oxide330is not diffused to the insulating layer118side, which is preferable. For example, the insulating layer120is preferably formed using a single layer or stacked layers of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiOA), or (Ba,Sr)TiO3(BST). As miniaturization and high integration of transistors progress, a problem such as generation of leakage current may arise because of a thinner gate insulating film. When a high-k material is used for an insulator functioning as the gate insulating film, a gate potential during operation of the transistor can be reduced while the physical thickness is maintained. It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material having a function of inhibiting diffusion of impurities, oxygen, and the like (the oxygen is less likely to pass). Note that as the insulator containing an oxide of aluminum and/or hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulating layer120is formed using such a material, the insulating layer120functions as a layer that inhibits release of oxygen from the metal oxide330and mixing of impurities such as hydrogen from the periphery of the transistor300to the metal oxide330. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator. It is preferable that the insulating layer118be thermally stable. For example, silicon oxide and silicon oxynitride, which have thermal stability, are suitable. Furthermore, combination of an insulator which is a high-k material and silicon oxide or silicon oxynitride enables formation of the insulating layer118with a stacked-layer structure with thermal stability and a high dielectric constant. Note that the insulating layer118, the insulating layer120, and the insulating layer122may each have a stacked-layer structure of two or more layers. In that case, not limited to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. In the transistor300, a metal oxide which functioning as an oxide semiconductor is preferably used as the metal oxide330including a channel formation region. For example, as the metal oxide330, a metal oxide such as an In-M-Zn oxide (an element M is one or more kinds selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. An In—Ga oxide or an In—Zn oxide may be used for the metal oxide330. The metal oxide functioning as the channel formation region in the metal oxide330has a band gap of preferably 2 eV or higher, further preferably 2.5 eV or higher. With the use of a metal oxide having such a wide band gap, the off-state current of the transistor can be reduced. When the metal oxide330includes the metal oxide330aunder the metal oxide330b, it is possible to inhibit diffusion of impurities into the metal oxide330bfrom the components formed below the metal oxide330a. The metal oxide330cover the metal oxide330bcan inhibit diffusion of impurities into the metal oxide330bfrom the components formed above the metal oxide330c. Note that the metal oxide330preferably has a stacked-layer structure of metal oxides with different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M to the constituent elements in the metal oxide used as the metal oxide330ais preferably higher than that in the metal oxide used as the metal oxide330b. The atomic ratio of the element M to In in the metal oxide used as the metal oxide330ais preferably higher than that in the metal oxide used as the metal oxide330b. The atomic ratio of In to the element M in the metal oxide used as the metal oxide330bis preferably higher than that in the metal oxide used as the metal oxide330a. The metal oxide330ccan be formed using a metal oxide that can be used as the metal oxide330aor the metal oxide330b. The energy of the conduction band minimum of each of the metal oxide330aand the metal oxide330cis preferably higher than that of the metal oxide330b. In other words, the electron affinity of each of the metal oxide330aand the metal oxide330cis preferably smaller than that of the metal oxide330b. Here, the energy level of the conduction band minimum is gradually varied at a junction portion of each of the metal oxide330a, the metal oxide330b, and the metal oxide330c. In other words, the energy levels of the conduction band minimum at a junction portion of each of the metal oxide330a, the metal oxide330b, and the metal oxide330ccontinuously vary or are continuously connected. This can be achieved by decrease in the density of defect states in a mixed layer formed at the interface between the metal oxide330aand the metal oxide330band the interface between the metal oxide330band the metal oxide330c. Specifically, when the metal oxide330aand the metal oxide330bor the metal oxide330band the metal oxide330ccontain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the metal oxide330bis an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as each of the metal oxide330aand the metal oxide330c. At this time, the metal oxide330bserves as a main carrier path. When the metal oxide330aand the metal oxide330chave the above structure, the density of defect states at the interface between the metal oxide330aand the metal oxide330band the interface between the metal oxide330band the metal oxide330ccan be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor300can have a high on-state current. The conductive layer342ahaving a function of one of the source and the drain and the conductive layer342bhaving a function of the other of the source and the drain are provided over the metal oxide330b. For the conductive layer342, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen. As shown inFIG.10(A), a region343(a region343aand a region343b) is sometimes formed as a low-resistance region at and near the interface between the metal oxide330and the conductive layer342. In that case, the region343afunctions as one of a source region and a drain region, and the region343bfunctions as the other of the source region and the drain region. The channel formation region is formed in a region between the region343aand the region343b. When the conductive layer342is provided in contact with the metal oxide330, the oxygen concentration in the region343sometimes decreases. In addition, a metal compound layer that contains the metal contained in the conductive layer342and the component of the metal oxide330is sometimes formed in the region343. In such a case, the carrier density of the region343increases, and the region343becomes a low-resistance region. The insulating layer123is provided to cover the conductive layer342and inhibits oxidation of the conductive layer342. At this time, the insulating layer123may be provided to cover a side surface of the metal oxide330and to be in contact with the insulating layer122. A metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used as the insulating layer123. For the insulating layer123, it is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, hafnium aluminate is preferable because it is less likely to be crystallized by heat treatment in a later step. Note that the insulating layer123is not an essential component when the conductive layer342is an oxidation-resistant material or does not significantly lose its conductivity even after absorbing oxygen. Design is appropriately determined in consideration of required transistor characteristics. The insulating layer350has a function of a gate insulating film. The insulating layer350is preferably positioned in contact with the inner side (the top surface and the side surface) of the metal oxide330c. The insulating layer350is preferably formed using an insulator from which oxygen is released by heating. An oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 1.0×1019atoms/cm3, further preferably greater than or equal to 2.0×1019atoms/cm3or greater than or equal to 3.0×1020atoms/cm3in thermal desorption spectroscopy analysis (TDS analysis) is used, for example. Note that the temperature of the film surface in the TDS analysis is preferably within the range of 100° C. to 700° C. Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. When an insulator from which oxygen is released by heating is provided as the insulating layer350in contact with the top surface of the metal oxide330c, oxygen can be efficiently supplied from the insulating layer350to the channel formation region of the metal oxide330bthrough the metal oxide330c. Furthermore, as in the insulating layer122, the concentration of impurities such as water and hydrogen in the insulating layer350is preferably reduced. The thickness of the insulating layer350is preferably within the range of 1 nm to 20 nm. To efficiently supply excess oxygen in the insulating layer350to the metal oxide330, a metal oxide may be provided between the insulating layer350and the conductive layer360. The metal oxide preferably inhibits diffusion of oxygen from the insulating layer350to the conductive layer360. Providing the metal oxide that inhibits diffusion of oxygen inhibits diffusion of excess oxygen from the insulating layer350to the conductive layer360. That is, the reduction in the amount of excess oxygen supplied to the metal oxide330can be inhibited. Moreover, oxidization of the conductive layer360due to excess oxygen can be inhibited. For the metal oxide, a material that can be used for the insulating layer123is used. Although the conductive layer360functioning as a gate electrode has a two-layer structure inFIGS.10(A) and10(B), a single-layer structure or a stacked-layer structure of three or more layers may be employed. For the conductive layer360a, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), and a copper atom. Alternatively, the conductive layer360ais preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). When the conductive layer360ahas a function of inhibiting oxygen diffusion, it is possible to prevent a reduction in conductivity of the conductive layer360bdue to oxidation caused by oxygen contained in the insulating layer350. As a conductive material having a function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used, for example. The conductive layer360bis preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductive layer360bfunctions as a wiring and thus a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductive layer360bmay have a stacked-layer structure, for example, a stacked-layer structure of any of the above conductive materials and titanium or titanium nitride. The insulating layer124is provided over the conductive layer342with the insulating layer123therebetween. The insulating layer124preferably includes an excess oxygen region. For example, the insulating layer124preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Silicon oxide and silicon oxynitride are particularly preferable in terms of high thermal stability. In particular, silicon oxide and porous silicon oxide, in which an excess-oxygen region can be easily formed in a later step, are preferable. The insulating layer124preferably includes an excess oxygen region. When the insulating layer124from which oxygen is released by heating is provided in contact with the metal oxide330c, oxygen in the insulating layer124can be efficiently supplied to the metal oxide330bthrough the metal oxide330c. The concentration of impurities such as water or hydrogen in the insulating layer124is preferably lowered. The opening of the insulating layer124is formed to overlap a region between the conductive layer342aand the conductive layer342b. Accordingly, the conductive layer360is formed to fill in the opening of the insulating layer124and the region between the conductive layer342aand the conductive layer342b. The gate length needs to be short for miniaturization of the imaging device, but it is necessary to prevent a reduction in conductivity of the conductive layer360. When the conductive layer360is made thick to achieve this, the conductive layer360might have a shape with a high aspect ratio. In this embodiment, the conductive layer360is provided to fill in the opening of the insulating layer124; hence, even when the conductive layer360has a shape with a high aspect ratio, the conductive layer360can be formed without collapsing during the process. The insulating layer126is preferably provided in contact with the top surface of the insulating layer124, the top surface of the conductive layer360, and the top surface of the insulating layer350. When the insulating layer126is deposited by a sputtering method, excess-oxygen regions can be provided in the insulating layer350and the insulating layer124. Accordingly, oxygen can be supplied from the excess-oxygen regions to the metal oxide330. For example, a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used as the insulating layer126. In particular, aluminum oxide has a high barrier property, and even a thin aluminum oxide film having a thickness within the range of 0.5 nm to 3.0 nm can inhibit diffusion of hydrogen and nitrogen. Accordingly, aluminum oxide deposited by a sputtering method serves as an oxygen supply source and can also have a function of a barrier film against impurities such as hydrogen. The insulating layer128functioning as an interlayer film is preferably provided over the insulating layer126. As in the insulating layer122or the like, the concentration of impurities such as water and hydrogen in the insulating layer128is preferably reduced. As shown inFIG.9, an opening reaching a conductive layer202_1and an opening reaching a conductive layer204_1are provided in an insulating layer126_1and an insulating layer128_1, and conductive layers130_1are provided to fill the openings. An opening reaching a conductive layer206_1, an opening reaching a conductive layer208_1, and an opening reaching a conductive layer210_1are provided in an insulating layer123_1, an insulating layer124_1, the insulating layer126_1, and the insulating layer128_1, and the conductive layers130_1are provided to fill the openings. The conductive layer202_1and the conductive layer204_1correspond to the conductive layer360shown inFIGS.10(A) and10(B), and the conductive layer206_1, the conductive layer208_1, and the conductive layer210_1correspond to the conductive layer342aor the conductive layer342bshown inFIG.10(A). The conductive layer130can have a two-layer structure of a conductive layer130aand a conductive layer130bas shown inFIG.10(A). As a material of the conductive layer130aand the conductive layer130b, a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, it is preferable to be formed with a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. For example, the conductive layer130may have a single-layer structure or a stacked-layer structure of three or more layers. A conductive layer131, a conductive layer132, a conductive layer134, a conductive layer136, a conductive layer138, and a conductive layer140are provided to have regions in contact with the conductive layer130_1. The region108is electrically connected to the conductive layer206_1through the conductive layer130_1and the conductive layer131. The conductive layer132is electrically connected to the conductive layer202_1through the conductive layer130_1. The conductive layer134is electrically connected to the conductive layer210_1through the conductive layer130_1. The conductive layer136is electrically connected to the conductive layer204_1through the conductive layer130_1. The conductive layer138is electrically connected to the conductive layer208_1through the conductive layer130_1. The conductive layer140is electrically connected to the region110through the conductive layer130_1. The conductive layer132can be part of the wiring41_1shown inFIG.3. The conductive layer136can be part of the wiring42_1shown inFIG.3. The conductive layer138can be part of the wiring44_1shown inFIG.3. The conductive layer140can be part of the wiring47shown inFIG.3. As the conductive layer131, the conductive layer132, the conductive layer134, the conductive layer136, the conductive layer138, and the conductive layer140, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like can be used. Alternatively, a conductive material such as an indium tin oxide, an indium oxide containing tungsten oxide, an indium zinc oxide containing tungsten oxide, an indium oxide containing titanium oxide, an indium tin oxide containing titanium oxide, an indium zinc oxide, or an indium tin oxide to which silicon oxide is added can be used. The conductive layer131, the conductive layer132, the conductive layer134, the conductive layer136, the conductive layer138, and the conductive layer140that are shown inFIG.9each have a single-layer structure; however, the structure is not limited thereto, and a stacked-structure of two or more layers can be used. For example, a conductor having a barrier property and a conductor highly adhesive to a conductor with high conductivity can be formed between a conductor having a barrier property and a conductor having high conductivity. An insulating layer142is provided over the insulating layer128_1, the conductive layer131, the conductive layer132, the conductive layer134, the conductive layer136, the conductive layer138, and the conductive layer140. The insulating layer142can have a structure similar to that of the insulating layer112. An insulating layer144is provided over the insulating layer142. The insulating layer144can have a structure similar to that of the insulating layer114. Accordingly, the insulating layer144can have a barrier property against hydrogen and the like and can suppress performance degradation of the OS transistor provided in the layer30_2. An insulating layer116_2is provided over the insulating layer144, and the transistor12_2and the transistor132are provided over the insulating layer116_2. As described above, the transistor300shown inFIGS.10(A) and10(B)can be used as the transistor12_2and the transistor13_2. The transistor12_1, the transistor13_1, the transistor12_2, and the transistor13_2can have the same structure. InFIG.9, the conductive layer202_2and the conductive layer204_2correspond to the conductive layer360shown inFIGS.10(A) and10(B), and the conductive layer206_2, the conductive layer208_2, and the conductive layer210_2correspond to the conductive layer342aor the conductive layer342bshown inFIG.10(A). A conductive layer161, a conductive layer162, a conductive layer164, a conductive layer166, a conductive layer168, and a conductive layer170are provided so as to have regions in contact with the conductive layer130_2. The region108is electrically connected to the conductive layer206_2through the conductive layer130_1, the conductive layer131, the conductive layer130_2, and the conductive layer161. The conductive layer162is electrically connected to the conductive layer202_2through the conductive layer130_2. The conductive layer164is electrically connected to the conductive layer210_2through the conductive layer130_2. The conductive layer166is electrically connected to the conductive layer204_2through the conductive layer130_2. The conductive layer168is electrically connected to the conductive layer208_2through the conductive layer130_2. The conductive layer170is electrically connected to the region110through the conductive layer130_2, the conductive layer140, and the conductive layer130_1. The conductive layer162can be part of the wiring41_2shown inFIG.3. The conductive layer166can be part of the wiring42_2shown inFIG.3. The conductive layer168can be part of the wiring44_2shown inFIG.3. The conductive layer170can be part of the wiring47shown inFIG.3. The conductive layer161, the conductive layer162, the conductive layer164, the conductive layer166, the conductive layer168, and the conductive layer170can have a structure similar to that of the conductive layer131, the conductive layer132, the conductive layer134, the conductive layer136, the conductive layer138, and the conductive layer140. An insulating layer172is provided over the insulating layer128_2, the conductive layer161, the conductive layer162, the conductive layer164, the conductive layer166, the conductive layer168, and the conductive layer170. The insulating layer172can have a structure similar to that of the insulating layer112and the insulating layer142. The above is the description of the structure example of a pixel included in the imaging device10shown inFIG.1and the like. As described above, the retention circuit32_1provided in the layer30_1can have a similar structure to that of the retention circuit32_2provided in the layer30_2. Thus, as shown inFIG.9, for example, the conductive layer202_1can have a region overlapping with the conductive layer202_2, the conductive layer204_1can have a region overlapping with the conductive layer204_2, the conductive layer206_1can have a region overlapping with the conductive layer206_2, the conductive layer208_1can have a region overlapping with the conductive layer208_2, and the conductive layer210_1can have a region overlapping with the conductive layer210_2. The conductive layer130_1can have a region overlapping with the conductive layer130_2. The conductive layer131can have a region overlapping with the conductive layer161, the conductive layer132can have a region overlapping with the conductive layer162, the conductive layer134can have a region overlapping with the conductive layer164, the conductive layer136can have a region overlapping with the conductive layer166, the conductive layer138can have a region overlapping with the conductive layer168, and the conductive layer140can have a region overlapping with the conductive layer170. Thus, even when a material blocking visible light is used for the conductive layers, this can inhibit the decrease in the aperture ratio of the imaging device10compared to the case where only one layer30is provided. Therefore, the imaging device of one embodiment of the present invention can achieve both obtaining a plurality of imaging data in a short period and imaging data corresponding to a high-quality image. The retention circuit32_2can be manufactured using the same mask as the mask used for manufacturing the retention circuit32_1. This inhibits increase in the number of masks used for manufacturing the imaging device10compared to the case where only one layer30is provided. Thus, manufacturing cost for the imaging device10can be inhibited from being much higher than that of the case where only one layer30is provided, and the imaging device10can be inexpensive. Structure Example 2 of Pixel FIG.11(A)shows a specific structure example of a pixel included in the imaging device10, and a modification example of the structure inFIG.9. InFIG.11(A), the layers30are provided under the layer20. Thus, the structure shown inFIG.11(A)can be used for the imaging device10having the structure shown inFIG.7, for example. In a pixel in the structure ofFIG.11(A), the insulating layer112is provided over the substrate100, the insulating layer114is provided over the insulating layer112, and the layer30is provided over the insulating layer114. The substrate100can be, for example, a substrate including silicon such as a single crystal silicon substrate. An insulating layer173is provided over the insulating layer172. The insulating layer173can have a structure similar to that of the insulating layer114shown inFIG.9. The photoelectric conversion element21is provided over the insulating layer173. The photoelectric conversion element21includes a conductive layer176, a photoelectric conversion layer182, and a conductive layer184. The conductive layer176has a function of one electrode of the photoelectric conversion element21, and the conductive layer184has a function of the other electrode of the photoelectric conversion element21. An opening reaching the conductive layer161is provided in the insulating layer173and the insulating layer172, and the conductive layer176can be formed to fill the opening. The one of the source and the drain of the transistor12is electrically connected to the one electrode of the photoelectric conversion element21. A conductive layer having a structure similar to that of the conductive layer130may be provided in the opening and the conductive layer176may be provided to have a region in contact with the conductive layers. A conductive layer178is provided in the layer20to be apart from the conductive layer176. For example, the conductive layer178can be formed using the same material in the same manufacturing step as the conductive layer176. The conductive layer178can be part of the wiring47shown inFIG.3. The conductive layer184can be provided to have a region in contact with the conductive layer178. This can electrically connect the other electrode of the photoelectric conversion element21and the wiring47. Note that the conductive layer178and the conductive layer184may be electrically connected through another conductive layer without direct contact. The photoelectric conversion layer182can include a selenium-based material. The photoelectric conversion element21using a selenium-based material has a property of high external quantum efficiency with respect to visible light. Furthermore, a selenium-based material has a high light-absorption coefficient, which is advantageous because the photoelectric conversion layer182can easily be made thin. The photoelectric conversion element21using a selenium-based material can be a highly sensitive sensor in which the amount of amplification is large because of avalanche multiplication. In other words, the use of a selenium-based material for the photoelectric conversion layer182allows sufficient photoelectric current to be obtained albeit a pixel area becomes small; the imaging device10can have high sensitivity. Thus, the imaging device10including the photoelectric conversion element21using a selenium-based material is also suitable for imaging in a low-illuminance environment. As a selenium-based material, amorphous selenium or crystalline selenium can be used. Crystalline selenium can be obtained, for example, by subjecting amorphous selenium to heat treatment after deposition. When the crystal grain size of crystalline selenium is smaller than a pixel pitch, variations in characteristics between pixels can be reduced. Moreover, crystalline selenium has properties with higher spectral sensitivity and light-absorption coefficient for visible light than amorphous selenium. The photoelectric conversion layer182may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. With CIS or CIGS, a photoelectric conversion element that utilizes avalanche multiplication as in the case of using a single layer of selenium can be formed. The conductive layer184preferably has a light-transmitting property. The light-transmitting conductive layer184can have a structure including indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, graphene, or graphene oxide, for example. The conductive layer184is not limited to a single layer, and may be a stacked layer of films with different materials. Here, an organic compound may be used for the photoelectric conversion layer182.FIG.11(B)is a cross-sectional view showing a structure example of the photoelectric conversion element21when an organic compound is used for the photoelectric conversion layer182. As shown inFIG.11(B), a hole-transport layer186, an active layer180, and an electron-transport layer188are sequentially stacked in the photoelectric conversion layer182. In this case, the conductive layer178has a function of the anode of the photoelectric conversion element21, and the conductive layer184has a function of the cathode of the photoelectric conversion element21. Note that when the conductive layer178has a function of the cathode of the photoelectric conversion element21and the conductive layer184has a function of the anode of the photoelectric conversion element21, the stacking order is inverted. The active layer180has a function of absorbing light which is emitted to the photoelectric conversion element21. Owing to the photoelectric effect, a current depending on the illuminance of the light absorbed by the active layer180flows through the photoelectric conversion element21. The active layer180can be formed using a combination of a plurality of organic materials as appropriate. For example, the active layer180can have a structure including tetraphenyldibenzoperiflanthene (DBP) and fullerene. The hole-transport layer186has a function of transporting holes from the conductive layer178having a function of the anode to the active layer180. The hole-transport layer186contains a hole-transport material. For example, the hole-transport layer186can contain molybdenum oxide. Note that the hole-transport layer186can be formed using any material other than the above-described materials as long as the material has a hole-transport property higher than an electron-transport property. The electron-transport layer188has a function of transporting electrons from the conductive layer184having a function of the cathode to the active layer180. The electron-transport layer188contains an electron-transport material. The electron-transport layer188can have a one-layer structure or a stacked-layer structure of two or more layers. For example, a stacked-layer structure of fullerene and bathocuproine (BCP) can be used. Note that the electron-transport layer188can be formed using any material other than the above-described materials as long as the material has an electron-transport property higher than a hole-transport property. When an organic compound is used for the photoelectric conversion layer182in the photoelectric conversion element21, the imaging device10can be inexpensive. In addition, the imaging device10can have flexibility. Structure Example 3 of Pixel FIG.12(A)is a perspective view showing an example in which a coloring layer (color filter) and the like are added to the pixel included in the imaging device10. In the perspective view, cross sections of a plurality of pixels are also shown. An insulating layer380is formed over the layer20where the photoelectric conversion element21is formed. As the insulating layer380, a silicon oxide film with a high light-transmitting property with respect to visible light can be used. A silicon nitride film may be stacked as a passivation film. A dielectric film of hafnium oxide or the like may be stacked as an anti-reflection film. A light-blocking layer381may be formed over the insulating layer380. The light-blocking layer381has a function of preventing color mixing of light passing through the upper coloring layer. As the light-blocking layer381, a metal layer of aluminum, tungsten, or the like can be used. Alternatively, the metal layer and a dielectric film having a function of an anti-reflection film may be stacked. An organic resin layer382can be provided as a planarization film over the insulating layer380and the light-blocking layer381. A coloring layer383(a coloring layer383a, a coloring layer383b, a coloring layer383c) is formed in the pixel. When colors of R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the coloring layer383a, the coloring layer383b, and the coloring layer383c, for example, a color image can be obtained. An insulating layer386having a light-transmitting property with respect to visible light can be provided over the coloring layer383, for example. As shown inFIG.12(B), an optical conversion layer385may be used instead of the coloring layer383. Such a structure enables the imaging device capable of obtaining images in various wavelength regions. When a filter that blocks light with a wavelength shorter than or equal to that of visible light is used as the optical conversion layer385, for example, it is possible to obtain an infrared imaging device. When a filter that blocks light with a wavelength shorter than or equal to that of near infrared light is used as the photoelectric conversion layer385, it is possible to obtain a far-infrared imaging device. When a filter that blocks light with a wavelength longer than or equal to that of visible light is used as the photoelectric conversion layer385, it is possible to obtain an ultraviolet imaging device. Alternatively, a coloring layer for visible light and a filter for infrared rays or ultraviolet rays may be combined. With such a structure, a feature obtained by combining different wavelength data can be detected. Furthermore, when a scintillator is used as the optical conversion layer385, an imaging device that obtains an image visualizing the intensity of radiation, which is used for an X-ray imaging device or the like, can be obtained. Radiation such as X-rays passes through an object and enters the scintillator, and then is converted into light (fluorescence) such as visible light or ultraviolet light owing to a photoluminescence phenomenon. Then, the light is detected by the photoelectric conversion element21, whereby image data is obtained. Furthermore, the imaging device having this structure may be used in a radiation detector or the like. A scintillator contains a substance that, when irradiated with radiation such as X-rays or gamma-rays, absorbs energy of the radiation to emit visible light or ultraviolet light. For example, a resin or ceramics in which Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, or the like is dispersed can be used. In the photoelectric conversion element21using a selenium-based material, radiation such as X-rays can be directly converted into charge; thus, a structure in which the scintillator is unnecessarily can also be employed. As shown inFIG.12(C), a microlens array384may be provided over the coloring layer383. Light passing through lenses of the microlens array384goes through the coloring layer383positioned thereunder and the photoelectric conversion element21is irradiated with the light. The microlens array384may be provided over the optical conversion layer385shown inFIG.12(B). This embodiment can be combined with any of the other embodiments as appropriate. Embodiment 2 In this embodiment, a structure example of a transistor that can be used for the imaging device of one embodiment of the present invention is described with reference to drawings. Transistor Structure Example 1 A structure example of a transistor510A is described with reference toFIGS.13(A),13(B), and13(C).FIG.13(A)is a top view of the transistor510A.FIG.13(B)is a cross-sectional view of a portion indicated by a dashed-dotted line L1-L2inFIG.13(A).FIG.13(C)is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2inFIG.13(A). Note that for clarification of the drawing, some components are not shown in the top view ofFIG.13(A), FIGS.13(A),13(B), and13(C) show the transistor510A, an insulating layer511, an insulating layer512, an insulating layer514, an insulating layer516, an insulating layer521, an insulating layer522, and an insulating layer574, an insulating layer580, an insulating layer582, and an insulating layer584that has a function as interlayer films. In addition, conductive layers546(a conductive layer546aand a conductive layer546b) that are electrically connected to the transistor510A and have a function as contact plugs are shown. The transistor510A includes an insulating layer524that has a function of base insulating layer; a conductive layer560(a conductive layer560aand a conductive layer560b) functioning as a gate electrode; an insulating layer550functioning as a gate insulating film; a metal oxide530(a metal oxide530a, a metal oxide530b, and a metal oxide530c) including a region where a channel is formed; a conductive layer542afunctioning as one of a source and a drain; and a conductive layer542bfunctioning as the other of the source and the drain. In the transistor510A shown inFIG.13, the metal oxide530c, the insulating layer550, and the conductive layer560are positioned in an opening provided in the insulating layer580with the insulating layer574positioned therebetween. Moreover, the metal oxide530c, the insulating layer550, and the conductive layer560are positioned between a conductive layer542aand a conductive layer542b. The insulating layer511and the insulating layer512have a function as interlayer films. As the interlayer film, a single layer or stacked layers of an insulating layer such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST) can be used. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulating layer, for example. Alternatively, the insulating layer may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulating layer. For example, the insulating layer511preferably has a function as a barrier film that inhibits entry of impurities such as water and hydrogen into the transistor510A from the substrate side. Accordingly, for the insulating layer511, it is preferable to use an insulating material that has a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom (through which the above impurities are less likely to pass). Alternatively, the insulator511is preferably formed using an insulating material having a function of inhibiting diffusion of oxygen (e.g., oxygen atoms and oxygen molecules), that is, an insulating material through which oxygen is less likely to pass. Moreover, aluminum oxide or silicon nitride, for example, may be used for the insulating layer511. This structure can inhibit diffusion of impurities such as hydrogen and water to the transistor510A side from the substrate side of the insulating layer511. For example, the dielectric constant of the insulating layer512is preferably lower than that of the insulating layer511. When a material with a low permittivity is used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. In the transistor510A, the conductive layer560sometimes has a function as a gate. Like the insulating layer511or the insulating layer512, the insulating layer514and the insulating layer516have a function as interlayer films. For example, the insulating layer514preferably has a function as a barrier film that inhibits entry of impurities such as water and hydrogen into the transistor510A from the substrate side. This structure can inhibit diffusion of impurities such as hydrogen and water to the transistor510A side from the substrate side of the insulating layer514. Moreover, for example, the insulating layer516preferably has a lower dielectric constant than the insulating layer514. When a material with a low permittivity is used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulating layer522preferably has a barrier property. The insulating layer522having a barrier property has a function as a layer that inhibits entry of impurities such as hydrogen into the transistor510A from the surroundings of the transistor510A. For the insulating layer522, a single layer or stacked layers of an insulating layer containing what is called a high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST) are preferably used, for example. As miniaturization and high integration of transistors progress, a problem such as generation of leakage current may arise because of a thinner gate insulating film. When a high-k material is used for an insulator having a function as the gate insulating film, a gate potential during operation of the transistor can be reduced while the physical thickness is maintained. It is preferable that the insulating layer521be thermally stable, for example. For example, silicon oxide and silicon oxynitride are thermal stable; thus, the insulating layer521is formed using a high-k material and the insulating layer522is formed using a material containing silicon oxide and/or oxynitride, which can achieve a thermally stable and high dielectric constant stacking structure. The metal oxide530including a region having a function as the channel formation region includes the metal oxide530a, the metal oxide530bover the metal oxide530a, and the metal oxide530cover the metal oxide530b. Including the metal oxide530aunder the metal oxide530bmakes it possible to inhibit diffusion of impurities into the metal oxide530bfrom the components formed below the metal oxide530a. The metal oxide530cover the metal oxide530bcan inhibit diffusion of impurities into the metal oxide530bfrom the components formed above the metal oxide530c. As the metal oxide530, the above-described oxide semiconductor, which is one kind of metal oxide, can be used. Note that the metal oxide530cis preferably provided in the opening provided in the insulating layer580with the insulating layer574positioned therebetween. When the insulating layer574has a barrier property, diffusion of impurities from the insulating layer580into the metal oxide530can be inhibited. One of conductive layers542has a function as a source electrode and the other has a function as a drain electrode. For the conductive layer542aand the conductive layer542b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten or an alloy containing any of the metals as its main component can be used. In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and high oxidation resistance. Although a single-layer structure is shown inFIG.13, a stacked-layer structure of two or more layers may be employed. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Further alternatively, a two-layer structure where an aluminum film is stacked over a tungsten film, a two-layer structure where a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure where a copper film is stacked over a titanium film, or a two-layer structure where a copper film is stacked over a tungsten film may be employed. A three-layer structure consisting of a titanium film or a titanium nitride film, an aluminum film or a copper film stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film formed thereover; a three-layer structure consisting of a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film formed thereover; or the like may be employed. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. A barrier layer may be provided over the conductive layer542. The barrier layer is preferably formed using a material having a barrier property against oxygen or hydrogen. This structure can inhibit oxidation of the conductive layer542at the time of depositing the insulating layer574. A metal oxide can be used for the barrier layer, for example. In particular, an insulating film of aluminum oxide, hafnium oxide, gallium oxide, or the like, which has a barrier property against oxygen and hydrogen, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used. With the barrier layer, the range of choices for the material of the conductive layer542can be expanded. For example, a material having a low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductive layer542. Moreover, for example, a conductive layer that can be easily deposited or processed can be used. The insulating layer550has a function of a gate insulating film. The insulating layer550is preferably provided in the opening provided in the insulating layer580with the metal oxide530cand the insulating layer574positioned therebetween. As miniaturization and high integration of transistors progress, a problem such as generation of leakage current may arise because of a thinner gate insulating film. In that case, the insulating layer550may have a stacked-layer structure. When the insulator having a function as the gate insulating film has a stacked-layer structure of a high-k material and a thermally stable material, a gate potential during operation of the transistor can be reduced while the physical thickness is maintained. Furthermore, the stacked-layer structure can be thermally stable and have a high dielectric constant. The conductive layer560having a function as a gate includes the conductive layer560aand the conductive layer560bover the conductive layer560a. The conductive layer560ais preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom. Alternatively, the conductive layer560ais preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). Note that in this specification and the like, a function of inhibiting diffusion of impurities or oxygen means a function of inhibiting diffusion of any one or all of the above impurities and oxygen. When the conductive layer560ahas a function of inhibiting oxygen diffusion, the range of choices for the material of the conductive layer560bcan be expanded. That is, when the conductive layer560ais provided, a decrease in the conductivity of the conductive layer560bdue to oxidization can be suppressed even when the material which is easily oxidized is used for the conductive layer560b. As a conductive material having a function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used, for example. For the conductive layer560a, the oxide semiconductor that can be used as the metal oxide530can be used. In that case, when the conductive layer560bis deposited by a sputtering method, the electric resistance of the conductive layer560ais lowered so that the conductive layer560acan become a conductive layer. Such a conductor can be referred to as an OC (Oxide Conductor) electrode. The conductive layer560bis preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductive layer560has a function as a wiring and thus a conductive layer having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductive layer560bmay have a stacked-layer structure, for example, a stack of any of the above conductive materials and titanium or titanium nitride. The insulating layer574is positioned between the insulating layer580and the transistor510A. Note that the insulating layer574is preferably formed using an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen. For example, aluminum oxide or hafnium oxide is preferably used. Alternatively, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide; silicon nitride oxide; or silicon nitride can be used. The insulating layer574of the imaging device of one embodiment of the present invention can inhibit diffusion of impurities such as water and hydrogen contained in the insulating layer580into the metal oxide530bthrough the metal oxide530cand the insulating layer550. In addition, oxidation of the conductive layer560due to excess oxygen contained in the insulating layer580can be inhibited. The insulating layer580, the insulating layer582, and the insulating layer584have a function as interlayer films. Like the insulating layer514, the insulating layer582preferably has a function as a barrier insulating film that inhibits entry of impurities such as water and hydrogen into the transistor510A from the outside. Like the insulating layer516, the insulating layer580and the insulating layer584preferably have a lower dielectric constant than the insulating layer582. When a material with a low permittivity is used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. The transistor510A may be electrically connected to another component through a plug and a wiring such as the conductive layer546embedded in the insulating layer580, the insulating layer582, and the insulating layer584. As a material for the conductive layer546, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or stacked layers. For example, it is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum. Alternatively, it is preferable to form the plugs and wirings with a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. For example, when the conductive layer546has a stacked-layer structure of tantalum nitride or the like, which is a conductive layer having a barrier property against hydrogen and oxygen, and tungsten, which has high conductivity, diffusion of impurities from the outside can be inhibited while the conductivity of a wiring is maintained. The transistor having the above-described structure is used as the transistor included in the imaging device of one embodiment of the present invention, whereby the imaging device of one embodiment of the present invention can be an imaging device including a transistor having a metal oxide and high on-state current. Alternatively, the imaging device of one embodiment of the present invention can be an imaging device including a transistor having a metal oxide and low off-state current. Alternatively, the imaging device of one embodiment of the present invention can be an imaging device that has small variation in electrical characteristics, stable electrical characteristics, and improved reliability. Transistor Structure Example 2 A structure example of a transistor510B is described with reference toFIGS.14(A),14(B), and14(C).FIG.14(A)is a top view of the transistor510B.FIG.14(B)is a cross-sectional view of a portion, indicated by a dashed-dotted line L1-L2inFIG.14(A).FIG.14(C)is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2inFIG.14(A). Note that for clarification of the drawing, some components are not shown in the top view ofFIG.14(A). The transistor510B is a variation example of the transistor510A. Therefore, differences from the transistor510A are mainly described to avoid repeated description. The transistor510B includes a region where the conductive layer542(the conductive layer542aand the conductive layer542b), the metal oxide530c, the insulating layer550, and the conductive layer560overlap with each other. With this structure, a transistor having a high on-state current can be provided. Moreover, a transistor having high controllability can be provided. The conductive layer560having a function as a gate electrode includes the conductive layer560aand the conductive layer560bover the conductive layer560a. The conductive layer560ais preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom. Alternatively, the conductive layer560ais preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). When the conductive layer560ahas a function of inhibiting oxygen diffusion, the range of choices for the material of the conductive layer560bcan be expanded. That is, the conductive layer560ainhibits oxidation of the conductive layer560b, thereby preventing the decrease in conductivity of the conductive layer560b. The insulating layer574is preferably provided to cover the top surface and the side surface of the conductive layer560, the side surface of the insulating layer550, and the side surface of the metal oxide530c. Note that the insulating layer574is preferably formed using an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen. For example, aluminum oxide or hafnium oxide is preferably used. Alternatively, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide; silicon nitride oxide; or silicon nitride can be used. The insulating layer574can inhibit oxidation of the conductive layer560. Moreover, providing the insulating layer574can inhibit diffusion of impurities such as water and hydrogen contained in the insulating layer580into the transistor510B. An insulating layer576(an insulating layer576aand an insulating layer576b) having a barrier property may be provided between the conductive layer546and the insulating layer580. Providing the insulating layer576can prevent oxygen in the insulating layer580from reacting with the conductive layer546and oxidizing the conductive layer546. Furthermore, with the insulating layer576having a barrier property, the range of choices for the material of the conductive layer used as the plug or the wiring can be expanded. The use of a metal material having an oxygen absorbing property and high conductivity for the conductive layer546, for example, can provide an imaging device with low power consumption. Specifically, a material having a low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used. Moreover, for example, a conductive layer that can be easily deposited or processed can be used for the conductive layer546. Transistor Structure Example 3 A structure example of a transistor510C is described with reference toFIGS.15(A),15(B), and15(C).FIG.15(A)is a top view of the transistor510C.FIG.15(B)is a cross-sectional view of a portion indicated by a dashed-dotted line L1-L2inFIG.15(A).FIG.15(C)is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2inFIG.15(A). Note that for clarification of the drawing, some components are not shown in the top view of FIG.15(A). The transistor510C is a variation example of the transistor510A. Therefore, differences from the transistor510A are mainly described to avoid repeated description. The transistor510C shown inFIG.15includes a conductive layer547abetween the conductive layer542aand the metal oxide530b, and a conductive layer547bbetween the conductive layer542band the metal oxide530b. Here, the conductive layer542a(the conductive layer542b) extends beyond the top surface and the side surface on the conductive layer560side of the conductive layer547a(the conductive layer547b), and includes a region in contact with the top surface of the metal oxide530b. For the conductive layer547, a conductive layer that can be used for the conductive layer542is used. It is preferred that the thickness of the conductive layer547be at least greater than that of the conductive layer542. In the transistor510C shown inFIG.15having such a structure, the conductive layer542can be closer to the conductive layer560than that in the transistor510A is. Alternatively, the conductive layer560and an end portion of the conductive layer542aand an end portion of the conductive layer542bcan overlap with each other. Accordingly, the effective channel length of the transistor510C can be shortened, and the on-state current and the frequency characteristics can be improved. The conductive layer547a(the conductive layer547b) is preferably provided to overlap with the conductive layer542a(the conductive layer542b). With such a structure, the conductive layer547a(the conductive layer547b) functioning as a stopper can prevent over-etching of the metal oxide530bby etching for forming the opening where the conductive layer546a(the conductive layer546b) is to be embedded. In the transistor510C shown inFIG.15, an insulating layer545may be positioned on and in contact with an insulating layer544. The insulating layer544preferably has a function as a barrier insulating film that inhibits entry of impurities such as water and hydrogen and excess oxygen into the transistor510C from the insulating layer580side. As the insulating layer545, an insulating layer that can be used as the insulating layer544can be used. In addition, the insulating layer544may be formed using a nitride insulating layer such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide, for example. Transistor Structure Example 4 A structure example of a transistor510D is described with reference toFIGS.16(A),16(B), and16(C).FIG.16(A)is a top view of the transistor510D.FIG.16(B)is a cross-sectional view of a portion indicated by a dashed-dotted line L1-L2inFIG.16(A).FIG.16(C)is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2inFIG.16(A). Note that for clarification of the drawing, some components are not shown in the top view ofFIG.16(A). The transistor510D is a variation example of the above transistors. Therefore, differences from the above transistors are mainly described to avoid repeated description. The transistor510D includes the insulating layer550over the oxide530cand a metal oxide552over the insulating layer550. The conductive layer560is provided over the metal oxide552, and an insulating layer570is provided over the conductive layer560. An insulating layer571is provided over the insulating layer570. The metal oxide552preferably has a function of inhibiting diffusion of oxygen. When the metal oxide552that inhibits diffusion of oxygen is provided between the insulating layer550and the conductive layer560, diffusion of the oxygen to the conductive layer560is inhibited. That is, the reduction in the amount of oxygen supplied to the metal oxide530can be inhibited. Furthermore, oxidation of the conductive layer560can be inhibited. Note that the metal oxide552may function as part of a gate. For example, an oxide semiconductor that can be used for the metal oxide530can be used for the metal oxide552. In that case, when the conductive layer560is deposited by a sputtering method, the electric resistance of the metal oxide552is lowered so that the metal oxide552can become a conductive layer. Such a conductor can be referred to as an OC (Oxide Conductor) electrode. Note that the metal oxide552functions as part of a gate insulating film in some cases. Therefore, when silicon oxide, silicon oxynitride, or the like, which has high thermal stability, is used for the insulating layer550, a metal oxide that is a high-k material with a high dielectric constant is preferably used as the metal oxide552. This stacked-layer structure enables the transistor510D to be thermally stable and have a high dielectric constant. Accordingly, a gate potential applied during operation of the transistor can be lowered while physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of an insulating layer having a function as the gate insulator can be reduced. Although the metal oxide552in the transistor510D is shown as a single layer, the metal oxide552may have a stacked-layer structure of two or more layers. For example, a metal oxide having a function as part of a gate electrode and a metal oxide having a function as part of the gate insulating film may be stacked. When the metal oxide552included in the transistor510D has a function as a gate, the on-state current of the transistor510D can be increased without weakening the influence of electric fields from the conductive layer560. When the metal oxide552has a function as a gate insulating film, the distance between the conductive layer560and the metal oxide530can be maintained owing to the physical thickness of the insulating layer550and the metal oxide552. Thus, leakage current between the conductive layer560and the metal oxide530can be reduced. Consequently, in the transistor510D having the stacked-layer structure of the insulating layer550and the metal oxide552, it is easy to adjust the physical distance between the conductive layer560and the metal oxide530and the intensity of electric fields applied from the conductive layer560to the metal oxide530. Specifically, for the metal oxide552, a material obtained by lowering the resistance of an oxide semiconductor that can be used for the metal oxide530can be used. Alternatively, a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. It is particularly preferable to use an insulating layer containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, hafnium aluminate is preferable because it is less likely to be crystallized by heat treatment in a later step. Note that the metal oxide552is not an essential structure. Design is appropriately determined in consideration of required transistor characteristics. The insulating layer570is preferably formed using an insulating material having a function of inhibiting the passage of oxygen and impurities such as water or hydrogen. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidization of the conductive layer560due to oxygen from above the insulating layer570can be inhibited. Moreover, entry of impurities such as water or hydrogen from above the insulating layer570into the metal oxide530through the conductive layer560and the insulating layer550can be inhibited. The insulating layer571has a function as a hard mask. By providing the insulating layer571, the conductive layer560can be processed to have a side surface that is substantially vertical to the substrate surface; specifically, an angle formed by the side surface of the conductive layer560and a surface of the substrate can be within the range of 75° to 100°, preferably within the range of 80° to 95°. The insulating layer571may be formed using an insulating material having a function of inhibiting the passage of oxygen and impurities such as water or hydrogen so that the insulating layer571also functions as a barrier layer. In that case, the insulating layer570does not have to be provided. Parts of the insulating layer570, the conductive layer560, the metal oxide552, the insulating layer550, and the metal oxide530care selectively removed using the insulating layer571as a hard mask, so that the side surfaces of them are substantially aligned with each other and part of the surface of the metal oxide530bcan be exposed. In the transistor510D, part of the exposed surface of the metal oxide530bincludes a region531aand a region531b. One of the region531aand the region531bfunctions as a source region, and the other of the region531aand the region531bhas a function as a drain region. The region531aand the region531bcan be formed by, for example, introducing an impurity element such as phosphorus or boron to the exposed surface of the metal oxide530bby an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. In this embodiment and the like, an impurity element refers to an element other than main constituent elements. The region531aand the region531bcan also be formed in the following manner: a metal film is deposited after part of the surface of the metal oxide530bis exposed and then the element in the metal film is diffused into the metal oxide530bby heat treatment. The electrical resistivity of the regions of the metal oxide530bto which the impurity element is added decreases. Accordingly, the region531aand the region531bare each referred to as an “impurity region” or a “low-resistance region” in some cases. The region531aand the region531bcan be formed in a self-aligned manner by using the insulating layer571and/or the conductive layer560as a mask. Accordingly, the conductive layer560does not overlap with the region531aand/or the region531b, so that the parasitic capacitance can be reduced. Furthermore, an offset region is not formed between the channel formation region and the source or drain region (the region531aor the region531b). The formation of the region531aand the region531bin a self-aligned manner achieves an increase in the on-state current, a reduction in the threshold voltage, and an improvement in the operation frequency, for example. Note that an offset region may be provided between the channel formation region and the source/drain region in order to further reduce the off-state current. The offset region is a region where the electrical resistivity is high and the impurity element is not added. The offset region can be formed by the above-described addition of the impurity element after the formation of an insulating layer575. In this case, the insulating layer575has a function as a mask like the insulating layer571or the like. Thus, the impurity element is not added to the region of the metal oxide530boverlapped with the insulating layer575, so that the electrical resistivity of the region can be kept high. In the transistor510D, the insulating layer575is provided on the side surfaces of the insulating layer570, the conductive layer560, the metal oxide552, the insulating layer550, and the metal oxide530c. The insulating layer575is preferably an insulating layer having a low dielectric constant. The insulating layer575is preferably silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or a resin, for example. In particular, silicon oxide, silicon oxynitride, silicon nitride oxide, or porous silicon oxide is preferably used for the insulating layer575, in which case an excess-oxygen region can be easily formed in the insulating layer575in a later step. Silicon oxide and silicon oxynitride are preferable because of their thermal stability. The insulating layer575preferably has a function of diffusing oxygen. The transistor510D also includes the insulating layer574over the insulating layer575and the metal oxide530. The insulating layer574is preferably deposited by a sputtering method. The insulating layer formed by a sputtering method can be an insulating layer containing few impurities such as water or hydrogen. For example, aluminum oxide is preferably used for the insulating layer574. Note that an oxide film formed by a sputtering method may extract hydrogen from the component over which the oxide film is formed. For that reason, the insulating layer574formed by a sputtering method absorbs hydrogen and water from the metal oxide530and the insulating layer575. This reduces the hydrogen concentration in the metal oxide530and the insulating layer575. Transistor Structure Example 5 A structure example of a transistor510E is described with reference toFIGS.17(A),17(B), and17(C).FIG.17(A)is atop view of the transistor510E.FIG.17(B)is a cross-sectional view of a portion indicated by a dashed-dotted line L1-L2inFIG.17(A).FIG.17(C)is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2inFIG.17(A). Note that for clarification of the drawing, some components are not shown in the top view ofFIG.17(A). The transistor510E is a variation example of the above transistors. Therefore, differences from the above transistors are mainly described to avoid repeated description. In the transistor510E, the conductive layer542is not included and part of the exposed surface of the metal oxide530bincludes the region531aand the region531b. One of the region531aand the region531bfunctions as a source region, and the other has a function as a drain region. Moreover, an insulating layer573is included between the metal oxide530band the insulating layer574. The regions531(the region531aand the region531b) shown inFIG.17are regions where an element described below is added to the metal oxide530b. The regions531can be formed with the use of a dummy gate, for example. Specifically, a dummy gate is provided over the metal oxide530b, and the above element that reduces the resistance of the metal oxide530bis added using the dummy gate as a mask. That is, the element is added to regions of the metal oxide530that are not overlapped by the dummy gate, whereby the regions531are formed. For the addition of the element, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. Typical examples of an element that reduces the resistance of the metal oxide530include boron and phosphorus. Hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas element, or the like can also be used. Typical examples of the rare gas include helium, neon, argon, krypton, and xenon. The concentration of the element is measured by secondary ion mass spectrometry (SIMS) or the like. In particular, boron and phosphorus are preferably used because an apparatus used in a manufacturing line for amorphous silicon or low-temperature polysilicon can be used. Since the existing facility can be used, capital investment can be reduced. Next, an insulating film to be the insulating layer573and an insulating film to be the insulating layer574may be formed over the metal oxide530band the dummy gate. Stacking the insulating film to be the insulating layer573and the insulating film to be the insulating layer574can provide a region where the region531, the metal oxide530c, and the insulating layer550overlap with each other. Specifically, after an insulating film to be the insulating layer580is provided over the insulating film to be the insulating layer574, the insulating film to be the insulating layer580is subjected to CMP (Chemical Mechanical Polishing) treatment, whereby part of the insulating film to be the insulating layer580is removed and the dummy gate is exposed. Then, when the dummy gate is removed, part of the insulating layer573in contact with the dummy gate is preferably also removed. Thus, the insulating layer574and the insulating layer573are exposed at the side surface of the opening provided in the insulating layer580, and the region531provided in the metal oxide530bis partly exposed at the bottom surface of the opening. Next, an oxide film to be the metal oxide530c, an insulating film to be the insulating layer550, and a conductive film to be the conductive layer560are formed in this order in the opening, and then, the oxide film to be the metal oxide530c, the insulating film to be the insulating layer550, and the conductive film to be the conductive layer560are partly removed by CMP treatment or the like until the insulating layer580is exposed; thus, the transistor shown inFIG.17can be formed. Note that the insulating layer573and the insulating layer574are not essential components. Design is appropriately determined in consideration of required transistor characteristics. The cost of the transistor shown inFIG.17can be reduced because an existing apparatus can be used and the conductive layer542is not provided. This embodiment can be combined with any of the other embodiments as appropriate. Embodiment 3 Examples of a package and a camera module in each of which an image sensor chip is placed are described in this embodiment with reference to drawings. For the image sensor chip, the structure of the imaging device of one embodiment of the present invention can be used. FIG.18(A1) is an external perspective view of the top surface side of a package in which an image sensor chip is placed. The package includes a package substrate610to which an image sensor chip650is fixed shown inFIG.18(A3), a cover glass620, an adhesive630for bonding them, and the like. FIG.18(A2) is an external perspective view of the bottom surface side of the package. A BGA (Ball Grid Array) in which solder balls are used as bumps640on the bottom surface of the package is employed. Note that, without being limited to the BGA, an LGA (Land Grid Array), a PGA (Pin Grid Array), or the like may be employed. FIG.18(A3) is a perspective view of the package, in which part of the cover glass620and the adhesive630is not shown. Electrode pads660are formed over the package substrate610, and the electrode pads660and the bumps640shown inFIG.18(A2) are electrically connected to each other via through-holes. The electrode pads660are electrically connected to the image sensor chip650through the wires670. Furthermore,FIG.18(B1) is an external perspective view of the top surface side of a camera module in which an image sensor chip is placed in a package with a built-in lens. The camera module includes a package substrate611to which an image sensor chip651shown inFIG.18(B3) is fixed, a lens cover621, a lens635, and the like. FIG.18(B2) is an external perspective view of the bottom surface side of the camera module. A QFN (Quad Flat No-lead package) structure in which lands641for mounting are provided on the bottom surface and side surfaces of the package substrate611is employed. Note that this structure is only an example, and a QFP (Quad Flat Package) or the above-mentioned BGA may also be provided. FIG.18(B3) is a perspective view of the module, in which parts of the lens cover621and the lens635are not shown. The lands641are electrically connected to electrode pads661, and the electrode pads661are electrically connected to the image sensor chip651or the IC chip690through wires671. Furthermore, the IC chip690having a function of a driver circuit, a signal conversion circuit, or the like of an imaging device is provided between the package substrate611and the image sensor chip651; thus, the structure as an SiP (System in Package) is formed. The image sensor chip placed in a package having the above form can be easily mounted on a printed substrate or the like, and the image sensor chip can be incorporated into a variety of semiconductor devices and electronic devices. This embodiment can be combined with any of the other embodiments as appropriate. Embodiment 4 In this embodiment, electronic devices having the imaging device of one embodiment of the present invention are described. FIG.19(A)is an external view of a camera1000to which a finder1100is attached. The camera1000can be a digital camera, for example. Note that although the camera1000and the finder1100are separate and detachable electronic devices inFIG.19(A), a finder including a display device may be incorporated in a housing1001of the camera1000. The camera1000includes the housing1001, a display portion1002, operation buttons1003, a shutter button1004, and the like. A detachable lens1006is attached to the camera1000. Although the lens1006of the camera1000here is detachable from the housing1001for replacement, the lens1006may be integrated with the housing. The camera1000can take images at the press of the shutter button1004. The display portion1002functions as a touch panel and images can also be taken at the touch of the display portion1002. The housing1001of the camera1000includes a mount including an electrode, so that the finder1100, a stroboscope, or the like can be connected to the housing. The finder1100includes a housing1101, a display portion1102, and the like. The finder1100can be an electronic viewfinder. The housing1101includes a mount for engagement with the mount of the camera1000so that the finder1100can be attached to the camera1000. The mount includes an electrode, and an image or the like received from the camera1000through the electrode can be displayed on the display portion1102. The imaging device of one embodiment of the present invention can be provided in the camera1000. Accordingly, the camera1000can take imaging data corresponding to high-resolution images in a short period. Accordingly, the camera1000can be a high-speed camera. FIG.19(B)is an external view of a head-mounted display1200. The head-mounted display1200includes a mounting portion1201, a lens1202, a main body1203, a display portion1204, a cable1205, and the like. A battery1206is incorporated in the mounting portion1201. The cable1205supplies electric power from the battery1206to the main body1203. The main body1203includes a wireless receiver or the like and can display an image corresponding to the received image data on the display portion1204. The movement of the eyeball and the eyelid of the user is captured by a camera provided in the main body1203and then coordinates of the sight line of the user are calculated using the information to utilize the sight line of the user as an input means. A plurality of electrodes may be provided in the mounting portion1201at a position in contact with the user. The main body1203may have a function of sensing current flowing through the electrodes with the movement of the user's eyeball to recognize the user's sight line. The main body1203may have a function of sensing current flowing through the electrodes to monitor the user's pulse. The mounting portion1201may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor to have a function of displaying the user's biological information on the display portion1204. The main body1203may sense the movement of the user's head or the like to change an image displayed on the display portion1204in synchronization with the movement. The imaging device of one embodiment of the present invention can be provided in the camera provided in the main body1203and the sensor provided in the mounting portion1201. With this structure, the camera can take imaging data correspond to high-resolution images in a short period. Thus, the camera can be a high-speed camera. FIGS.19(C),19(D), and19(E) are external views of a head-mounted display1300. The head-mounted display1300includes a housing1301, a display portion1302, a band-shaped fixing unit1304, and a pair of lenses1305. A user can see display on the display portion1302through the lenses1305. Note that it is suitable that the display portion1302be curved and placed. When the display portion1302is curved and placed, a user can feel a high realistic sensation. Note that although the structure in which one display portion1302is provided is described in this embodiment as an example, the structure is not limited thereto, and two display portions1302may be provided. In that case, one display portion is placed for one eye of the user, so that three-dimensional display using parallax or the like is possible. The head-mounted display1300can be provided with a camera. Accordingly, an outside scene can be captured. The head-mounted display1300can synthesize a virtual image such as computer graphics (CG) and an image taken by the camera. The head-mounted display1300can be a device for augmented reality (AR). The imaging device of one embodiment of the present invention can be provided as the above camera. Accordingly, the camera can take imaging data corresponding to high-resolution images in a short period. Thus, the camera can be a high-speed camera, FIG.20(A)is an external view showing an example of a cellular phone1400. The cellular phone1400includes a housing1481, a display portion1482, an operation button1483, an external connection port1484, a speaker1485, a microphone1486, a camera1487, and the like. The cellular phone includes a touch sensor in the display portion1482. All operations including making a call and inputting text can be performed by touching the display portion1482with a finger, a stylus, or the like. The imaging device of one embodiment of the present invention can be provided as the camera1487. Accordingly, the camera1478can take imaging data corresponding to high-resolution images in a short period. Thus, the camera1478can be a high-speed camera. FIG.20(B)is an external view of a portable information terminal1500. The portable information terminal1500includes a housing1511, a display portion1512, speakers1513, a camera1519, and the like. A touch panel function of the display portion1512enables input and output of information. Furthermore, a character or the like in an image that is captured by the camera1519can be recognized and the character can be voice-output from the speakers1513. The imaging device of one embodiment of the present invention can be provided as the camera1519. Accordingly, the camera1519can take imaging data corresponding to high-resolution images in a short period. Thus, the camera1519can be a high-speed camera. FIG.20(C)is an external view of a surveillance camera1600. The surveillance camera1600includes a support unit1651, a camera unit1652, a protective cover1653, and the like. The camera unit1652is provided with a rotation mechanism and the like and can capture an image of all of the surroundings when provided on a ceiling. Note that a surveillance camera is a name in common use and does not limit the use thereof. A device that has a function of a surveillance camera can also be called a camera or a video camera, for example. The imaging device of one embodiment of the present invention can be provided as the camera unit1652. Accordingly, the camera unit1652can take imaging data corresponding to high-resolution images in a short period. Thus, the camera unit1652can be a high-speed camera. FIG.20(D)is an external perspective view showing a watch-type information terminal1700. The information terminal1700includes a display portion1732, a housing and wristband1733, a camera1739, and the like. The display portion1732is provided with a touch panel for operating the information terminal. The display portion1732and the housing and wristband1733have flexibility and fit a body well. The imaging device of one embodiment of the present invention can be provided as the camera1739. Accordingly, the camera1739can take imaging data corresponding to high-resolution images in a short period. Thus, the camera1739can be a high-speed camera. This embodiment can be combined with any of the other embodiments as appropriate. REFERENCE NUMERALS 10: imaging device,12: transistor,12_1: transistor,12_2: transistor,13: transistor,13_1: transistor,13_2: transistor,14: transistor,14_1: transistor,15: transistor,15_1: transistor,15_2: transistor,16: capacitor,20: layer,21: photoelectric conversion element,30: layer,30_i: layer,30_n: layer,30_1: layer,30_2: layer,31: imaging portion,32: retention circuit,32_i: retention circuit,32_n: retention circuit,32_1: retention circuit,32_2: retention circuit,33: gate driver circuit,33_n: gate driver circuit,33_1: gate driver circuit,34: source driver circuit,34_n: source driver circuit,34_1: source driver circuit,35: AD conversion circuit,35_n: AD conversion circuit,35_1: AD conversion circuit,35_2: AD conversion circuit,36: demultiplexer circuit,37: multiplexer circuit,40: wiring,40_1: wiring,40_2: wiring,41: wiring,41_1: wiring,412: wiring,42: wiring,42_1: wiring,42_2: wiring,43: wiring,43_1: wiring,43_2: wiring,44: wiring,44_1: wiring,44_2: wiring,45: wiring,46: wiring,47: wiring,51: exposure operation,52: retention operation,53: read operation,100: substrate,102: insulating layer,104: region,106: region,108: region,110: region,112: insulating layer,114: insulating layer,116: insulating layer,116_1: insulating layer,116_2: insulating layer,118: insulating layer,120: insulating layer,122: insulating layer,123: insulating layer,123_1: insulating layer,124: insulating layer,124_1: insulating layer,126: insulating layer,126_1: insulating layer,128: insulating layer,128_1: insulating layer,128_2: insulating layer,130: conductive layer130_1: conductive layer,130_2: conductive layer,130a: conductive layer,130b: conductive layer,131: conductive layer,132: conductive layer,134: conductive layer,136: conductive layer,138: conductive layer,140: conductive layer,142: insulating layer,144: insulating layer,161: conductive layer,162: conductive layer,164: conductive layer,166: conductive layer,168: conductive layer,170: conductive layer,172: insulating layer,173: insulating layer,176: conductive layer,178: conductive layer,180: active layer,182: photoelectric conversion layer,184: conductive layer,186: hole-transport layer,188: electron-transport layer,202_1: conductive layer,202_2: conductive layer,204_1: conductive layer,204_2: conductive layer,206_1: conductive layer,206_2: conductive layer,208_1: conductive layer,208_2: conductive layer,210_1: conductive layer,210_2: conductive layer,300: transistor,324: insulator,330: metal oxide,330a: metal oxide,330b: metal oxide,330c: metal oxide,342: conductive layer,342a: conductive layer,342b: conductive layer,343: region,343a: region,343b: region,350: insulating layer,360: conductive layer,360a: conductive layer,360b: conductive layer,380: insulating layer,381: light-blocking layer,382: organic resin layer,383: coloring layer,383a: coloring layer,383b: coloring layer,383c: coloring layer,384: microlens array,385: optical conversion layer,386: insulating layer,510A: transistor,510B: transistor,510C: transistor,510D: transistor,510E: transistor,511: insulating layer,512: insulating layer,514: insulating layer,516: insulating layer,521: insulating layer,522: insulating layer,524: insulating layer,530: metal oxide,530a: metal oxide,530b: metal oxide,530c: metal oxide,531: region,531a: region,531b: region,542: conductive layer,542a: conductive layer,542b: conductive layer,544: insulating layer,545: insulating layer,546: conductive layer,546a: conductive layer,546b: conductive layer,547: conductive layer,547a: conductive layer,547b: conductive layer,550: insulating layer,552: metal oxide,560: conductive layer,560a: conductive layer,560b: conductive layer,570: insulating layer,571: insulating layer,573: insulating layer,574: insulating layer,575: insulating layer,576: insulating layer,576a: insulating layer,576b: insulating layer,580: insulating layer,582: insulating layer,584: insulating layer,610: package substrate,611: package substrate,620: cover glass,621: lens cover,630: adhesive,635: lens,640: bump,641: land,650: image sensor chip,651: image sensor chip,660: electrode pad,661: electrode pad,670: wire,671: wire,690: IC chip,1000: camera,1001: housing,1002: display portion,1003: operation button,1004: shutter button,1006: lens,1100: finder,1101: housing,1102: display portion,1200: head-mounted display,1201: mounting portion,1202: lens,1203: main body,1204: display portion,1205: cable,1206: battery,1300: head-mounted display,1301: housing,1302: display portion,1304: fixing unit,1305: lens,1400: cellular phone,1481: housing,1482: display portion,1483: operation button,1484: external connection port,1485: speaker,1486: microphone,1487: camera,1500: portable information terminal,1511: housing,1512: display portion,1513: speaker,1519: camera,1600: surveillance camera,1651: supporting unit,1652: camera unit,1653: protection cover,1700: information terminal,1732: display portion,1733: housing and wristband,1739: camera | 142,228 |
11862650 | DETAILED DESCRIPTION The present disclosure will now be described with reference to the drawings wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. It will be appreciated that this detailed description and the corresponding figures do not limit the scope of the present disclosure in any way, and that the detailed description and figures merely provide a few examples to illustrate some ways in which the inventive concepts can manifest themselves. The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some complementary metal-oxide semiconductor image sensors (CISs) include a plurality of photodetectors disposed in a semiconductor substrate. A light filter array (e.g., a color filter array) having a plurality of light filters (e.g., color filters) disposed in a light filter grid structure is disposed over the photodetectors. A plurality of microlenses are typically disposed over the light filter array, such that the light filter array separates the microlenses from the photodetectors. Typically, the microlenses have a rounded upper surface, such that the microlenses focus incident radiation (e.g., photons) onto the photodetectors. A challenge with the above CISs is an amount of incident radiation that the microlenses focus onto the photodetectors. To improve the performance of CISs (e.g., increase pixel resolution, decrease form factor, etc.), feature sizes of the CISs are typically scaled down. However, as microlenses are scaled down (e.g., as radii of the microlenses are scaled down near/below the wavelength of incident radiation), diffraction may negatively affect an amount of radiation that the microlenses focus onto the photodetectors. Accordingly, as feature sizes of CISs continue to scale down, microlenses may negatively affect the quantum efficiency (QE) of CISs. In various embodiments, the present application is directed toward a wave guide filter having a substantially planar upper surface. The wave guide filter is disposed over a photodetector and comprises a light filter disposed in a light filter grid structure, the light filter grid structure and the light filter being at least partially translucent to light (e.g., photons having a wavelength between about 10 nanometers (nm) and about 1 millimeter (mm)). The light filter comprises a first material having a first refractive index, and the light filter grid structure comprises a second material having a second refractive index that is less than the first refractive index. The wave guide filter is configured to guide incident light toward the photodetector. Because both the light filter and the light filter grid structure are at least partially translucent, both the light filter and the light filter grid may guide light toward the photodetector. Further, because the first refractive index is greater than the second refractive index, light incident to the light filter is confined to the light filter (e.g., due total internal reflection) and guided onto the photodetector. In addition, because the second refractive index is less than the first refractive index, most of the light incident to the light filter grid structure is guided to the light filter and refracted toward the photodetector, thereby guiding the light incident to the light filter grid structure onto the photodetector. Thus, the wave guide filter may have a substantially planar upper surface and focus incident radiation onto the photodetectors, thereby decreasing the negative diffraction effects caused by the scaled down microlenses. Accordingly, the wave guide filter may improve the QE of CISs having scaled down feature sizes (e.g., less than about 1 micrometer (um)). FIGS.1A-1Billustrate various views of some embodiments of an image sensor100comprising a wave guide filter having a substantially planar upper surface.FIG.1Aillustrates a cross-sectional view taken along line A-A ofFIG.1B.FIG.1Billustrates a view of the image sensor100facing a back-side of the semiconductor substrate. As shown inFIGS.1A-1B, the image sensor100comprises a plurality of photodetectors102disposed in a semiconductor substrate104. The plurality of photodetectors102are configured to absorb incident radiation (e.g., photons) and generate respective electrical signals corresponding to the incident radiation. In further embodiments, the semiconductor substrate104comprises any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, an isolation structure110is disposed over/in the semiconductor substrate104. In further embodiments, the isolation structure110is disposed on a back-side104bof the semiconductor substrate104. In yet further embodiments, the isolation structure110extends into the semiconductor substrate104between the plurality of photodetectors102from the back-side104bof the semiconductor substrate104. A wave guide filter112having a substantially planar upper surface is disposed over the semiconductor substrate104. In some embodiments, the wave guide filter112is disposed over the back-side104bof the semiconductor substrate104. In further embodiments, the wave guide filter112comprises a dielectric layer114disposed on the isolation structure110. In some embodiments, a metal grid116is disposed in the dielectric layer114. In further embodiments, a first portion of the metal grid116is disposed on a first side of one of the photodetectors102, and a second portion of the metal grid116is disposed on a second side of the one of the photodetectors102opposite the first side. In such embodiments, a portion of the dielectric layer114that is disposed directly over the one of the photodetectors102may separate the first portion of the metal grid116from the second portion of the metal grid116. In yet further embodiments, the metal grid116may comprise, for example, tungsten, copper, aluminum, or the like. A first plurality of light filters118are disposed in a first light filter grid structure120and are disposed over the photodetectors102. In some embodiments, the first plurality of light filters118are disposed in a first light filter array comprising a plurality of rows and columns. For example, the first plurality of light filters118may comprise a first light filter118aconfigured to transmit light (e.g., photons having a wavelength between about 10 nm and about 1 mm) having wavelengths in a first range, a second light filter118bconfigured to transmit light having wavelengths in a second range different than the first range, and a third light filter118cconfigured to transmit light having wavelengths in a third range different than the first and second range. In further embodiments, the first light filter118a, the second light filter118b, and the third light filter118cmay be disposed in a same row. In further embodiments, each light filter of the first plurality of light filters118corresponds to a photodetector of the plurality of photodetectors102. In some embodiments, the first plurality of light filters118may be color filters. For example, the first light filter118amay be a red color filter, the second light filter118bmay be a green color filter, and the third light filter118cmay be a blue color filter. In further embodiments, the first plurality of light filters118may be infrared (IR) filters configured to filter incident radiation having an IR wavelength. In yet further embodiments, the first plurality of light filters118may comprise a combination of color filters and IR filters. In some embodiments, the first light filter grid structure120defines a layout of the first plurality of light filters118. In further embodiments, the first light filter grid structure120may be vertically aligned with the metal grid116. In further embodiments, each of the first plurality of light filters118may have a substantially similar footprint (e.g., an area one of the first plurality of light filters118projects onto the dielectric layer114). In further embodiments, a width W of the first light filter grid structure120may be substantially the same between each column of the light filter array. In further embodiments, a length L of the first light filter grid structure120may be substantially the same between each row of the light filter array. In yet further embodiments, the width W of the first light filter grid structure120may be different than the length L of the first light filter grid structure120. In other embodiments, the width W and the length L may be about the same. A first interface layer124is disposed over both the first plurality of light filters118and the first light filter grid structure120. In some embodiments, the first interface layer124has a substantially planar upper surface. An anti-reflective coating (ARC)126is disposed over the first interface layer124. In some embodiments, the ARC126has a substantially planar upper surface. In further embodiments, the substantially planar upper surface of the ARC126may define an uppermost surface of the wave guide filter112. In some embodiments, the first plurality of light filters118comprise a first light filtering material having a first refractive index. In further embodiments, the first refractive index may be between about 1.4 and about 4. In further embodiments, the first light filtering material may comprise, for example, a photoresist (e.g., a positive/negative photoresist) comprising a dye/pigment, a dispersant polymer, a polymerization monomer, and/or other chemicals (e.g., chemicals for the polymerization reaction). In yet further embodiments, the first plurality of light filters118are at least partially translucent to light. In some embodiments, the first light filter grid structure120comprises a first dielectric material having a second refractive index that is less than the first refractive index. In further embodiments, the first refractive index squared minus the second refractive index squared is less than about 0.25. In further embodiments, the first light filter grid structure120may comprise, for example, an oxide (e.g., silicon dioxide (SiO2)), a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxynitride (SiOXNY)), or the like. In further embodiments, the first refractive index squared minus the second refractive index squared is less than about 0.25. In yet further embodiments, the first light filter grid structure120is at least partially translucent to light. Because both the first plurality of light filters118and the first light filter grid structure120are at least partially translucent, both the first plurality of light filters118and the first light filter grid structure120may guide light toward the plurality of photodetectors102. Further, because the first refractive index is greater than the second refractive index, light incident to the first plurality of light filters128is confined to the first plurality of light filters118(e.g., due total internal reflection), respectively, and is guided onto the plurality of photodetectors102. In addition, because the second refractive index is less than the first refractive index, most light incident to the first light filter grid structure130is guided to the first plurality of light filters118and refracted toward the plurality of photodetectors102, thereby guiding most of the light incident to the first light filter grid structure130onto the plurality of photodetectors102. Thus, the wave guide filter112may have a substantially planar upper surface and focus incident radiation onto the plurality of photodetectors102, thereby decreasing the negative effects caused by diffraction in scaled down microlenses. Accordingly, the wave guide filter112may improve the quantum efficiency (QE) of complementary metal-oxide semiconductor image sensors (CISs) having scaled down feature sizes (e.g., less than about 1 micrometer (um)). In some embodiments, a height H of the first light filter grid structure120is greater than about 0.8 um. More specifically, in some embodiments, the height H of the first light filter grid structure120is between about 0.8 urn and about 2.0 urn. In further embodiments, if the height H of the first light filter grid structure120is greater than about 0.8 urn, the height H of the first light filter grid structure120is large enough that the light incident to the first light filter grid structure130may be guided to the first plurality of light filters118, thereby improving an amount of incident radiation that the wave guide filter112guides onto the photodetectors102. In yet further embodiments, if the height H of the first light filter grid structure120is less than about 2.0 urn, the height H of the first light filter grid structure120is small enough that the light incident to the first light filter grid structure130may be guided to the first plurality of light filters118with enough energy that the first plurality of light filters118may refract the incident light130onto the plurality of photodetectors102, thereby improving an amount of incident radiation that the wave guide filter112guides onto the photodetectors102. Thus, if the height H of the first light filter grid structure120is less than about 0.8 urn and/or greater than about 2.0 urn, it will be appreciated that an amount of incident light (e.g.,128/130) that the wave guide filter112guides onto the photodetectors102may be negatively affected. In some embodiments, the width W of the first light filter grid structure120is between about ⅙ of a width (e.g., a distance between opposite sides of one of the plurality of photodetectors102) of one of the plurality of photodetectors102and about ⅓ of the width of the one of the plurality of photodetectors102. For example, if the widths of the plurality of photodetectors102are about 0.9 urn, respectively, the width W of the first light filter grid structure120may be between about 0.15 urn and about 0.3 urn. In further embodiments, if the width W of the first light filter grid structure120is greater than about ⅙ of the width of the one of the plurality of photodetectors102, the width W of the first light filter grid structure120is large enough that the light incident to the first light filter grid structure130may be guided to the first plurality of light filters118, thereby improving an amount of incident radiation that the wave guide filter112guides onto the photodetectors102. In yet further embodiments, if the width W of the first light filter grid structure120is less than about ⅓ of the width of the one of the plurality of photodetectors102, the width W of the first light filter grid structure120is small enough that the light incident to the first light filter grid structure130may be guided to the first plurality of light filters118with enough energy that the first plurality of light filters118may refract the incident light130onto the plurality of photodetectors102, thereby improving an amount of incident radiation that the wave guide filter112guides onto the photodetectors102. Thus, if the width W of the first light filter grid structure120is less than about ⅙ of the width of the one of the plurality of photodetectors102and/or greater than about ⅓ of the width of the one of the plurality of photodetectors102, it will be appreciated that an amount of incident light (e.g.,128/130) that the wave guide filter112guides onto the photodetectors102may be negatively affected. FIGS.2A-2Billustrate various views of some embodiments of the image sensor ofFIGS.1A-1B.FIG.2Aillustrates a cross-sectional view taken along line A-A ofFIG.2B.FIG.2Billustrates a view of the image sensor facing a back-side of the semiconductor substrate. As shown inFIGS.2A-2B, the first plurality of light filters118may have different footprints. For example, the first light filter118amay have a smaller footprint than the second light filter118b. In such embodiments, the first light filter118amay have a substantially similar footprint as the third light filter118c. In further embodiments, the some of the light filters of the first plurality of light filters118that have a larger footprint may each guide light in a same wavelength range. For example, the some of the light filters of the first plurality of light filters118that have a larger footprint may be green color filters, while the some other light filters of the first plurality of light filters118that have a smaller footprint may be red color filters and/or blue color filters. Because the first plurality of light filters118may have different footprints, an overall spectrum of light that the wave guide filter112guides may be selectively tuned. For example, the wave guide filter may be selectively tuned, such that the quantum efficiency (QE) of green light is greater than the QE of red and/or blue light. In some embodiments, the first light filter grid structure120may not be vertically aligned with the metal grid116. For example, in some embodiments, portions of the first light filter grid structure120may be shifted laterally (e.g., along an x-axis and/or a y-axis) in relation to portions of the metal grid116, respectively. For example, a first portion of the first light filter grid structure120is disposed between the second light filter118band the third light filter118c. In some embodiments, the first portion of the first light filter grid structure120may be shifted in a first lateral direction (e.g., along the x-axis in a first direction) in relation to a portion of the metal grid116disposed directly beneath the first portion of the first light filter grid structure120. In further embodiments, a second portion of the first light filter grid structure120is disposed on a side of the third light filter118copposite the first portion of the first light filter grid structure120. In yet further embodiments, the second portion of the first light filter grid structure120may be shifted in a second lateral direction opposite the first lateral direction (e.g., along the x-axis in a second direction opposite the first direction) in relation to a portion of the metal grid116disposed directly beneath the second portion of the first light filter grid structure120. In some embodiments, a metallization structure202is disposed on a front-side104fof the semiconductor substrate104. The metallization structure202comprises an interconnect structure204(e.g., a copper interconnect) disposed in an interlayer dielectric (ILD) layer206. The interconnect structure204comprises a plurality of conductive features (e.g., metal lines, metal vias, metal contacts, etc.) that electrically couple a plurality of semiconductor devices208(e.g., a transfer transistor(s), reset transistor(s), etc.) together. FIG.3illustrates a cross-sectional view of some more detailed embodiments of the image sensor ofFIGS.1A-1B. As shown inFIG.3, the image sensor100comprise a central region302and a peripheral region304. The peripheral region304is disposed between an edge of the semiconductor substrate104and the central region302. It will be appreciated that a plurality of peripheral regions may be disposed on opposite sides of the central region302, such that the peripheral regions are disposed between opposite edges of the semiconductor substrate104and the central region302. In some embodiments, the isolation structure110comprises an upper isolation structure region110athat is disposed over the semiconductor substrate104and extends along the back-side104bof the semiconductor substrate104. In further embodiments, the isolation structure110comprises a plurality of deep trench isolation (DTI) structures110bthat extend from the upper isolation structure region110ainto the semiconductor substrate104. In further embodiments, the DTI structures110bextend vertically into the semiconductor substrate104between the plurality of photodetectors102. In further embodiments, the isolation structure110may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiments, the DTI structures110bmay be back-side DTI structures. In some embodiments, the dielectric layer114may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., (SiN), an oxy-nitride (e.g., SiOXNY), or the like. In further embodiments, the dielectric layer114and the isolation structure110may be a same material. In other embodiments, the dielectric layer114may comprise a different material than the isolation structure110. In the central region302, in some embodiments, a layout of the metal grid116may be about vertically aligned with a layout of the DTI structures110b. For example, in the central region302, the layout of the metal grid116may directly overlie the layout of the DTI structures110b. In the peripheral region304, in some embodiments, the layout of the metal grid116may be shifted toward the central region302in relation to the layout of the DTI structures110b. For example, in the peripheral region304, the layout of the metal grid116may be shifted (e.g., along the x-axis and/or y-axis) in relation to the layout of the DTI structures110b. In further embodiments, the layout of the metal grid116in the peripheral region304is shifted toward the central region302by a first distance D1. In further embodiments, the first distance D1is less than or equal to about half of the width of the one of the plurality of photodetectors102. In yet further embodiments, the width of the one of the plurality of photodetectors102may be less than or equal to about 1 um. In some embodiments, a patterned etch stop layer306is disposed between the first light filter grid structure120and the dielectric layer114. In further embodiments, the patterned etch stop layer306may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiments, the patterned etch stop layer306comprises a different material than the first light filter grid structure120. In the central region302, in some embodiments, the layout of the first light filter grid structure120may be about vertically aligned with the layout of the metal grid116. For example, in the central region302, the layout of the first light filter grid structure120may directly overlie the layout of the metal grid116. In the peripheral region304, in some embodiments, the layout of the first light filter grid structure120may be shifted (e.g., along the x-axis and/or y-axis) toward the central region302in relation to the layout of the metal grid116. In further embodiments, the layout of the first light filter grid structure120in the peripheral region304may be shifted toward the central region302by a second distance D2. In further embodiments, the second distance D2is less than or equal to about half of the width of the one of the plurality of photodetectors102. In yet further embodiments, the second distance D2is greater than the first distance D1. In some embodiments, heights of the first light filter grid structure120and heights of the first plurality of light filters118may differ, such that upper surfaces of the first light filter grid structure120and upper surfaces of the first plurality of light filters118are not co-planar. In further embodiments, the upper surfaces of the first plurality of light filters118may be non-planar. For example, an upper surface of one of the first plurality of light filters118may be concave. In some embodiments, the first interface layer124is configured to provide a substantially planar surface in which a layer(s) may be subsequently formed on, such that the subsequent layer(s) may be formed with a substantially planar upper surface. For example, the first interface layer124may have a substantially planar upper surface while being disposed on a non-planar surface comprising the upper surfaces of the first light filter grid structure120and the upper surfaces of the first plurality of light filters118, thereby providing a substantially planar surface on which the ARC126may be formed. In further embodiments, the first interface layer124may have self-leveling properties, such that the first interface layer124fills in differences in heights between the first plurality of light filters118and the first light filter grid structure120. In yet further embodiments, the first interface layer124may comprise, for example, a spin-on dielectric (e.g., SiO2), a photoresist (e.g., a positive/negative photoresist), a resin (e.g., a phenol formaldehyde resin, epoxy-resin, etc.), a polymer, or the like. In some embodiments, the ARC126is disposed on the substantially planar upper surface of the first interface layer124. In further embodiments, the upper surface of the ARC126is substantially planar due to, at least in part, the substantially planar upper surface of the first interface layer124. In further embodiments, the ARC126comprises, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), or the like. FIG.4illustrates a cross-sectional view of some other embodiments of the image sensor ofFIG.3. As shown inFIG.4, the metal grid116is disposed within the isolation structure110. In some embodiments, the metal grid116is disposed within the DTI structures110b. In further embodiments, upper surfaces of the metal grid116are disposed beneath the back-side104bof the semiconductor substrate104. In the central region302, in some embodiments, the metal grid116may be disposed in the DTI structures110b, such that a portion of the metal grid116disposed in a corresponding DTI structure is spaced about evenly from opposite sides of the corresponding DTI structure. In the peripheral region304, in some embodiments, the metal grid116may be disposed in the DTI structures110band shifted toward the central region302, such that a portion of the metal grid116disposed in a corresponding DTI structure is disposed closer to one side of the corresponding DTI structure than an opposite side of the corresponding DTI structure. In yet further embodiments, the first plurality of light filters118and the patterned etch stop layer306may be disposed on the upper isolation structure region110a. FIG.5illustrates a cross-sectional view of some other embodiments of the image sensor ofFIG.3. As shown inFIG.5, a plurality of noise reducing structures502are disposed in the dielectric layer114. The plurality of noise reducing structures502are configured to reduce noise (e.g. crosstalk) that may negatively affect performance of the image sensor100. In some embodiments, each of the plurality of noise reducing structures502is disposed between neighboring portions of the metal grid116. In further embodiments, the noise reducing structures502have a higher refractive index than the dielectric layer114. In yet further embodiments, the noise reducing structures502may comprise, for example, a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In some embodiments, each of the plurality of noise reducing structures502may be about evenly spaced from the neighboring portions of the metal grid116in which they are disposed between. In further embodiments, upper surfaces of the plurality of noise reducing structures502are co-planar with an upper surface of the dielectric layer114. In yet further embodiments, the first plurality of light filters118, the patterned etch stop layer306, and/or the first light filter grid structure120may be disposed on the noise reducing structures502. FIG.6illustrates a cross-sectional view of some other embodiments of the image sensor ofFIG.3. As shown inFIG.6, a second plurality of light filters602are disposed in a second light filter grid structure604. In some embodiments, the second plurality of light filters602comprise a second light filtering material having a third refractive index. The second light filtering material may comprise, for example, a photoresist (e.g., a positive/negative photoresist) comprising a dye/pigment, a dispersant polymer, a polymerization monomer, and/or other chemicals (e.g., chemicals for the polymerization reaction). In further embodiments, the second light filtering material and the first light filtering material may be a same material. In other embodiments, the second light filtering material and the first light filtering material may be different materials. In yet further embodiments, a combined height of the second light filter gird structure604and the first light filter grid structure120is greater than about 0.8 um. More specifically, in some embodiments, the combined height of the second light filter grid structure604and the first light filter grid structure120is between about 0.8 um and about 2.0 um. In some embodiments, the third refractive index may be between about 1.4 and about 4. In further embodiments, the third refractive index may be about the same as the first refractive index. In other embodiments, the third refractive index may be different than the first refractive index. In yet further embodiments, the second plurality of light filters602are at least partially translucent to light. In some embodiments, the second light filter grid structure604comprises a second dielectric material having a fourth refractive index that is less than the third refractive index. In further embodiments, the second light filter grid structure604may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiment, the second dielectric material and the first dielectric material may be a same material. In other embodiments, the second dielectric material and the first dielectric material may be different materials. In some embodiments, the third refractive index squared minus the fourth refractive index squared is less than about 0.25. In further embodiments, the fourth refractive index may be about the same as the second refractive index. In other embodiments, the fourth refractive index may be different than the second refractive index. In further embodiments, the second light filter grid structure604is at least partially translucent to light. In some embodiments, the first, second, third, and/or fourth refractive indexes may be selectively tuned. In further embodiments, the first refractive index may be selectively tuned by, for example, selectively choosing a specific material for the first light filtering material (e.g., choosing an oxide or a nitride), selectively choosing a specific composition of the first light filtering material (e.g., choosing a specific amount of dye/pigment in the first light filtering material), or the like. In further embodiments, the third refractive index may be selectively tuned in a substantially similar way as the first refractive index. In further embodiments, the second refractive index may be selectively tuned by, for example, selectively choosing a specific material for the second light filtering material (e.g., choosing an oxide or a nitride); selectively choosing a specific composition of the second light filtering material (e.g., choosing a specific porosity of the second light filtering material); forming the first light filter grid structure120with a plurality of layers having different refractive indexes (e.g., having a first layer covered by a second layer), such that the refractive index of the plurality of layers is a specific second refractive index; or the like. In yet further embodiments, the fourth refractive index may be selectively tuned in a substantially similar way as the second refractive index. In some embodiments, the first interface layer124is disposed over both the second plurality of light filters602and the second light filter grid structure604. In such embodiments, the first interface layer124may fill in differences in heights between the second plurality of light filters602and the second light filter grid structure604. In some embodiments, a second interface layer606separates the first plurality of light filters118and the first light filter grid structure120from the second plurality of light filters602and the second light filter grid structure604. In further embodiments, the second interface layer606has a substantially planar upper surface. In further embodiments, the second interface layer606is configured to provide a substantially planar upper surface in which a layer(s) may be subsequently formed on, such that the subsequent layer(s) may be formed with a substantially planar upper surface. For example, the second interface layer606may have a substantially planar upper surface while being disposed on a non-planar surface comprising the upper surfaces of the first light filter grid structure120and the upper surfaces of the first plurality of light filters118. In yet further embodiments, the second interface layer606may have self-leveling properties, such that the second interface layer606fills in differences in heights between the first plurality of light filters118and the first light filter grid structure120. In some embodiments, the second interface layer606may comprise, for example, a spin-on dielectric (e.g., SiO2), a photoresist (e.g., a positive/negative photoresist), a resin (e.g., a phenol formaldehyde resin, epoxy-resin, etc.), a polymer, or the like. In further embodiments, the second interface layer606and the first interface layer124may be a same material. In other embodiments, the second interface layer606and the first interface layer124may be different materials. In some embodiments, the second plurality of light filters602and the second light filter grid structure604may be disposed on the second interface layer606. In further embodiments, the second plurality of light filters602may be color filters. In further embodiments, the second plurality of light filters602may be IR filters configured to filter incident radiation having an IR wavelength. In further embodiments, the second plurality of light filters602may comprise a combination of color filters and IR filters. In the central region302, in some embodiments, a layout of the second light filter grid structure604may be about vertically aligned with the layout of the first light filter grid structure120. In the peripheral region304, in some embodiments, a layout of the second light filter grid structure604may be shifted toward the central region302by a third distance D3. In further embodiments, the third distance D3is less than or equal to about half of the width of the one of the plurality of photodetectors102. In yet further embodiments, the third distance D3and the second distance D2may be about the same. In other embodiments, the third distance D3and the second distance D2may be different. In some embodiments, when the wave guide filter112comprises the second light filter grid structure604and the first light filter grid structure120, the wave guide filter112may further improve edge performance of the image sensor by, for example, having the layout of the second light filter grid structure604in the peripheral region304shifted in relation to the layout of the first light filter grid structure120in the peripheral region304(e.g., shifted toward the central region302or away from the central region302). In addition, when the wave guide filter112comprises both the second plurality of light filters602and the first plurality of light filters118, the wave guide filter112may be utilized in additional image sensor applications due to the wave guide filter112filtering a range of wavelengths of incident radiation that a wave guide filter112comprising only one of the second plurality of light filters602or the first plurality of light filters118may filter. FIGS.7A-7Billustrate various views of some other embodiments of the image sensor ofFIGS.1A-1B.FIG.7Aillustrates a cross-sectional view taken along line A-A ofFIG.7B.FIG.7Billustrates a view of the image sensor facing a back-side of the semiconductor substrate. As shown inFIGS.7A-7B, a group of photodetectors702is disposed in the semiconductor substrate104. In some embodiments, the plurality of photodetectors102of the group of photodetectors702are arranged in a photodetector array comprising one or more rows and one or more columns. For example, the photodetector array may comprise two columns and two rows (e.g., a 2×2 structure). It will be appreciated that the photodetector array may comprise other combinations of rows and columns, for example, one row and two columns (e.g., a 2×1 structure). In some embodiments, a common light filter704is disposed over the group of photodetectors702. In further embodiments, the common light filter704at least partially covers the group of photodetectors702. Because the common light filter704at least partially covers the group of photodetectors702, the image sensor100may be able to detect differences in where incident radiation focuses onto the plurality of photodetectors102of the group of photodetectors702. Accordingly, the image sensor100may have autofocus capabilities (e.g., phase detection auto focus). In some embodiments, the common light filter704may cover a portion of each of the plurality of photodetectors102of the group of photodetectors702. In further embodiments, the common light filter704may be centrally disposed over the group of the photodetectors702, such that the common light filter704covers a substantially similar sized portion of each of the plurality of photodetectors102of the group of photodetectors702. In further embodiments, the first plurality of light filters118may be disposed around sides of the common light filter704. In such embodiments, light filters of the first plurality of light filters118disposed on opposite sides of the common light filter704may be spaced about a same distance from the common light filter704. FIGS.8A-8Billustrate various views of some embodiments of the image sensor ofFIGS.7A-7B.FIG.8Aillustrates a cross-sectional view taken along line A-A ofFIG.8B.FIG.8Billustrates a view of the image sensor facing a back-side of the semiconductor substrate. As shown inFIGS.8A-8B, the common light filter704is shifted in a lateral direction (e.g., along the x-axis). In some embodiments, the first plurality of light filters118disposed around the sides of the common light filter704may be shifted in the lateral direction. In further embodiments, the common light filter704may be shifted a greater distance in the lateral direction than the first plurality of light filters118. In yet further embodiments, the common light filter704may cover portions of some of the plurality of photodetectors102of the group of photodetectors702, and not cover portions of some other of the plurality of photodetectors102of the group of photodetectors702. In some embodiments, portions of the first light filter grid structure120may have different widths. For example, in some embodiments, a first portion of the first light filter grid structure120is disposed on a first side of the common light filter704, and second portion of the first light filter grid structure120is disposed on a second side of the common light filter704opposite the first side. In such embodiments, the first portion of the first light filter grid structure120may have a greater width than the second portion of the first light filter grid structure120. In further embodiments, portions of the metal grid116may have different widths. For example, in some embodiments, a first portion of the metal grid116is disposed on the first side of the common light filter704, and a second portion of the metal grid116is disposed on the second side of the common light filter704. In such embodiments, the first portion of metal grid116may have a greater width than the second portion of the metal grid116. FIGS.9-19illustrate a series of cross-sectional views of some embodiments of a method for forming the image sensor ofFIG.6. As shown inFIG.9, an isolation structure110is formed over/in the semiconductor substrate104. In some embodiments, the isolation structure110is formed on a back-side104bof the semiconductor substrate104. In further embodiments, a process for forming the isolation structure110comprises selectively etching the semiconductor substrate104to form trenches in the semiconductor substrate104that extend into the semiconductor substrate104from a back-side104bof the semiconductor substrate104. In some embodiments, the semiconductor substrate104is selectively etched by forming a masking layer (not shown) on the back-side104bof the semiconductor substrate104, and subsequently exposing the semiconductor substrate104to an etchant configured to remove unmasked portions of the semiconductor substrate104. Thereafter, in some embodiments, the masking layer is stripped away. Subsequently, a dielectric layer is deposited or grown on the back-side104bof the semiconductor substrate104and in the trenches, thereby forming the isolation structure110. In some embodiments, the dielectric layer may be deposited or grown by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing. In further embodiments, the dielectric material may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiments, a planarization process (e.g., chemical-mechanical planarization (CMP)) may be performed on the isolation structure110to form a substantially planar upper surface. As shown inFIG.10, a metal grid116is formed over the isolation structure110. In some embodiments, a process for forming the metal grid116comprises depositing a conductive layer (not shown) on the isolation structure110. In further embodiments, the conductive layer may be deposited on the isolation structure110by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In further embodiments, the conductive layer may comprise, for example, tungsten, copper, aluminum, or the like. Thereafter, the conductive layer is selectively etched by forming a masking layer (not shown) on the conductive layer, and subsequently exposing the conductive layer to an etchant configured to remove unmasked portions of the conductive layer, thereby forming the metal grid116. In some embodiments, the masking layer is subsequently stripped away. As shown inFIG.11, a dielectric layer114is formed over the metal grid116and the isolation structure110. In some embodiments, a process for forming the dielectric layer114comprises depositing the dielectric layer114on the metal grid116and the isolation structure110. In further embodiments, the dielectric layer114may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In yet further embodiments, a planarization process (e.g., CMP) may be performed on the dielectric layer114to form a substantially planar upper surface. As shown inFIG.12, an etch stop layer1202is formed over the dielectric layer114. In some embodiments, a process for forming the etch stop layer1202comprises depositing the etch stop layer1202on the dielectric layer114. In further embodiments, the etch stop layer1202may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In yet further embodiments, the etch stop layer1202may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. Also shown inFIG.12, a first light filter grid layer1204is formed over the etch stop layer1202. In some embodiments, a process for forming the first light filter grid layer1204comprises depositing the first light filter grid layer1204onto the etch stop layer1202. In some embodiments, the first light filter grid layer1204may be deposited on the etch stop layer1202by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In some embodiments, the first light filter grid layer1204may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiments, the first light filter grid layer1204is at least partially translucent to light. As shown inFIG.13, a first light filter grid structure120and a patterned etch stop layer306are formed over the dielectric layer114. Further, in forming the first light filter grid structure120and the patterned etch stop layer306, a plurality of first light filter trenches1302are formed over the dielectric layer114. In some embodiments, each of the plurality of first light filter trenches1302are defined by an upper surface of the dielectric layer114, sidewalls of the first light filter grid structure120, and sidewalls of the patterned etch stop layer306. In some embodiments, a process for forming the first light filter grid structure120and the patterned etch stop layer306comprises selectively etching the first light filter grid layer1204(see, e.g.,FIG.12) and the etch stop layer1202(see, e.g.,FIG.12). In further embodiments, the first light filter grid layer1204and the etch stop layer1202may be selectively etched by forming a masking layer (not shown) on the first light filter grid layer1204, and subsequently exposing the first light filter grid layer1204to an etchant configured to remove unmasked portions of the first light filter grid layer1204and unmasked portions of the etch stop layer1202, thereby forming the first light filter grid structure120and the patterned etch stop layer306. In some embodiments, the masking layer is subsequently stripped away. It will be appreciated that, in some embodiments, multiple etching processes may be performed to form the first light filter grid structure120and the patterned etch stop layer306. As shown inFIG.14, a first plurality of light filters118are formed over the dielectric layer114and in the first light filter grid structure120. In some embodiments, a process for forming the first plurality of light filters118comprises depositing a first light filtering material in the plurality of first light filter trenches1302(see, e.g.,FIG.13) and on the dielectric layer114. In some embodiments, the first light filtering material may be deposited by, for example, a spin-on process, CVD, some other deposition process, or a combination of the foregoing. In further embodiments, depositing the first light filtering material in the plurality of first light filter trenches1302may cause upper surfaces of the first plurality of light filters118to be non-planar with upper surfaces of the first light filter grid structure120(e.g., due to the first light filtering material being deposited by a spin-on process). In some embodiments, the first plurality of light filters118(and thus the first light filtering material) may be formed with a first refractive index. In further embodiments, the first refractive index may be between about 1.4 and about 4. In further embodiments, the first light filter grid structure120(and thus the first light filter grid layer1204) may be formed with a second refractive index that is less than the first refractive index. In further embodiments, the first refractive index squared minus the second refractive index squared is less than about 0.25. As shown inFIG.15, a second interface layer606is formed over the first plurality of light filters118and the first light filter grid structure120. In some embodiments, a process for forming the second interface layer606comprises depositing the second interface layer606on the first plurality of light filters118and the first light filter grid structure120. In further embodiments, the second interface layer606may be deposited by, for example, a spin-on process, CVD, or some other deposition process. In further embodiments, the second interface layer606may be formed with a substantially planar upper surface. In further embodiments, the second interface layer606may be formed on a non-planar surface comprising upper surfaces of the first plurality of light filters118and upper surfaces of the first light filter grid structure120. Also shown inFIG.15, a second light filter grid layer1502is formed over the second interface layer606. In some embodiments, a process for forming the second light filter grid layer1502comprises depositing the second light filter grid layer1502on the second interface layer606. In some embodiments, the second light filter grid layer1502may be deposited on the second interface layer606by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In some embodiments, the second light filter grid layer1502may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiments, the second light filter grid layer1502is at least partially translucent to light. As shown inFIG.16, a second light filter grid structure604is formed over the second interface layer606. Further, in forming the second light filter grid structure604, a plurality of second light filter trenches1602are formed over the second interface layer606. In some embodiments, each of the plurality of second light filter trenches1602are defined by an upper surface of the second interface layer606and sidewalls of the second light filter grid structure604. In some embodiments, a process for forming the second light filter grid structure604comprises selectively etching the second light filter grid layer1502(see, e.g.,FIG.15). In further embodiments, the second light filter grid layer1502may be selectively etched by forming a masking layer (not shown) on the second light filter grid layer1502, and subsequently exposing the second light filter grid layer1502to an etchant configured to remove unmasked portions of the second light filter grid layer1502, thereby forming the second light filter grid structure604. In some embodiments, the masking layer is subsequently stripped away. As shown inFIG.17, a second plurality of light filters602are formed over the second interface layer606and in the second light filter grid structure604. In some embodiments, a process for forming the second plurality of light filters602comprises depositing a second light filtering material in the plurality of second light filter trenches1602(see, e.g.,FIG.15) and on the second interface layer606. In some embodiments, the second light filtering material may be deposited by, for example, a spin-on process, CVD, some other deposition process, or a combination of the foregoing. In further embodiments, depositing the second light filtering material in the second light filter trenches1602may cause upper surfaces of the second plurality of light filters602to be non-planar with upper surfaces of the second light filter grid structure604(e.g., due to the second light filtering material being deposited by a spin-on process). In some embodiments, the second plurality of light filters602(and thus the second light filtering material) may be formed with a third refractive index. In further embodiments, the third refractive index may be between about 1.4 and about 4. In further embodiments, the second light filter grid structure604(and thus the second light filter grid layer1502) may be formed with a fourth refractive index that is less than the third refractive index. In yet further embodiments, the third refractive index squared minus the fourth refractive index squared is less than about 0.25. As shown inFIG.18, a first interface layer124is formed over the second plurality of light filters602and the second light filter grid structure604. In some embodiments, a process for forming the first interface layer124comprises depositing the first interface layer124on the second plurality of light filters602and the second light filter grid structure604. In further embodiments, the first interface layer124may be deposited by, for example, a spin-on process, CVD, or some other deposition process. In further embodiments, the first interface layer124may be formed with a substantially planar upper surface. In further embodiments, the first interface layer124may be formed on a non-planar surface comprising upper surfaces of the second plurality of light filters602and upper surfaces of the second light filter grid structure604. As shown inFIG.19, an anti-reflective coating (ARC)126is formed on the first interface layer124. In some embodiments, a process for forming the ARC126comprises depositing the ARC126on the first interface layer124. In further embodiments, the ARC126may be deposited on the first interface layer124by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In further embodiments, the ARC126is formed with a substantially planar upper surface. In further embodiments, the ARC126may be formed with a substantially planar upper surface due to, at least in part, the substantially planar upper surface of the first interface layer124. In yet further embodiments, after the ARC126is formed, formation of the wave guide filter112is complete. As illustrated inFIG.20, a flowchart2000of some embodiments of a method for forming an image sensor comprising a wave guide filter having a substantially planar upper surface is provided. While the flowchart2000ofFIG.20is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At2002, an isolation structure is formed over/in a semiconductor substrate, wherein the isolation structure extends into the semiconductor substrate between a plurality of photodetectors.FIG.9illustrates a cross-sectional view of some embodiments corresponding to act2002. At2004, a metal grid is formed over the isolation structure.FIG.10illustrates a cross-sectional view of some embodiments corresponding to act2004. At2006, a dielectric layer is formed over the metal grid and the isolation structure.FIG.11illustrates a cross-sectional view of some embodiments corresponding to act2006. At2008, a wave guide filter having a substantially planar upper surface is formed over the dielectric layer. The wave guide filter comprises a light filter grid structure having a first refractive index and a plurality of light filters having a second refractive index that is less than the first refractive index.FIGS.12-19illustrate a series of cross-sectional views of some embodiments corresponding to act2008. Because the first refractive index is greater than the second refractive index, light incident to the plurality of light filters is confined to the plurality of light filters (e.g., due total internal reflection), respectively, and is guided onto the plurality of photodetectors. In addition, because the second refractive index is less than the first refractive index, light incident to the light filter grid structure is guided to the plurality of light filters and refracted toward the plurality of photodetectors, thereby guiding the light incident to the first light filter grid structure onto the plurality of photodetectors. Thus, the wave guide filter may have a substantially planar upper surface and focus incident radiation onto the plurality of photodetectors, thereby decreasing the negative diffraction effects caused by scaled down microlenses. Accordingly, the wave guide filter may improve the quantum efficiency (QE) of complementary metal-oxide semiconductor image sensors (CISs) having scaled down feature sizes (e.g., less than about 1 micrometer (um)). In some embodiments, the present application provides an image sensor. The image sensor comprises a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter comprises a light filter disposed in a light filter grid structure. The light filter comprises a first material that is translucent and has a first refractive index. The light filter grid structure comprises a second material that is translucent and has a second refractive index less than the first refractive index. In other embodiments, the present application provides an image sensor. The image sensor comprises a photodetector disposed in a semiconductor substrate. A first light filter grid structure is disposed over a back-side of the semiconductor substrate. The back-side of the semiconductor substrate is opposite a front-side of the semiconductor substrate. A metallization structure is disposed on the front-side of the semiconductor substrate. A first light filter is disposed in the first light filter grid structure. A dielectric layer is disposed over the back-side of the semiconductor substrate and disposed between the photodetector and the first light filter. A metal grid is disposed in the dielectric layer, wherein the metal grid comprises a first portion disposed on a first side of the photodetector and a second portion disposed on a second side of the photodetector opposite the first side of the photodetector. In yet other embodiments, the present application provides a method for forming an image sensor. The method comprises forming an isolation structure on a semiconductor substrate. A metal grid is formed on the isolation structure. A dielectric layer is formed on the isolation structure and covering the metal grid. A first light filter grid structure is formed over the dielectric layer. A first light filter is formed in the first light filter grid structure. A first interface layer is formed over both the first light filter grid structure and the first light filter. A second light filter grid structure is formed over the first interface layer. A second light filter is formed in the second light filter grid structure. A second interface layer is formed over both the second light filter grid structure and the second light filter. An anti-reflective coating (ARC) is formed over the second interface layer, wherein the ARC is formed with a substantially planar upper surface. An anti-reflective coating (ARC) is formed on the substantially planar upper surface of the interface layer, wherein the ARC is formed with a substantially planar upper surface. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 61,123 |
11862651 | DESCRIPTION OF EXAMPLE EMBODIMENTS FIGS.1,2, and3illustrate one light trapping image sensor100.FIG.1is a cross-sectional view of image sensor100in an example use scenario.FIG.2shows image sensor100in further detail.FIG.3is a top view of a pixel array of image sensor100. The cross sections of image sensor100depicted inFIGS.1and2are taken along line2-2′ inFIG.3.FIGS.1,2, and3are best viewed together in the following description. Image sensor100includes a semiconductor substrate110and a lens array130disposed over a light-receiving top surface114of semiconductor substrate110. Image sensor100is a backside-illuminated complementary metal oxide semiconductor (CMOS) image sensor that includes an array of photosensitive pixels112formed in and on semiconductor substrate110. Without departing from the scope hereof, image sensor100may include fewer or more pixels112than shown inFIGS.1,2, and3. Each pixel112converts light182incident on pixel112to an electrical output signal188. Each pixel112includes a reflective material that forms a cavity120around a portion of the semiconductor material of semiconductor110to at least partly trap light182that has entered cavity120. Light enters cavity120through an aperture122in a ceiling224formed by the reflective material at top surface114. Although depicted inFIG.3as having circular cross section, apertures122may have a different shape, for example square, without departing from the scope hereof. When light182is of a wavelength where the internal quantum efficiency of semiconductor substrate110is low, the average path length that a photon of light182must travel in order to be converted to an electrical charge may greatly exceed to the thickness of semiconductor substrate110. For example, the absorption coefficient of silicon is α1060=10 cm−1at 1060 nanometers (near-infrared) and α535=10,000 cm−1at 535 nanometers (green). As a result, while 535-nanometer light travels only one micron to lose 64% of its intensity to photon-to-charge conversion, 1060-nanometer light must travel one millimeter to lose 64% of its intensity to photon-to-charge conversion. Typically, the thickness of a semiconductor substrate of an image sensor is a few microns, e.g., between 2 and 20 microns, such that only a very small fraction of incident 1060-nanometer light will undergo photon-to-charge conversion while traveling through the thickness of the semiconductor substrate. By virtue of trapping light182, cavities120effectively multiply the semiconductor-substrate-thickness experienced by light182that has entered cavities120.FIG.2shows one example ray284entering a cavity120and being reflected by walls of cavity120to make multiple passes through the semiconductor material of semiconductor substrate110inside cavity120. (It is understood that this ray tracing description may not be accurate, and that wave optics may be required to properly describe the light propagation into and inside cavity120.) The thickness162of semiconductor substrate110may be in the range between 2 and 20 microns. Yet, cavities120may allow path lengths, of light182within cavities120, that is many times greater than thickness162. Cavities120thereby compensate for the low absorption coefficient pertaining to certain wavelength ranges and enhance the quantum efficiency of image sensor100in such wavelength ranges, as compared to a conventional image sensor without cavities120. In order to enjoy the light-trapping benefit of cavities120, light182must be coupled relatively effectively into cavities120through aperture122, and each aperture122must be made as small as possible. For this purpose, lens array130is disposed over top surface114and includes lenses132aligned to apertures122. Lenses132are configured to focus light182at least approximately on apertures122, such that at least a significant portion of light incident on each lens132is coupled into a respective cavity120even when aperture122is small. Each lens132may have a high numerical aperture to produce tight focus on aperture122to improve light coupling into cavity120through aperture122. In one embodiment, each lens132is a plano-convex microlens and may have a numerical aperture of approximately 0.5 or greater (such as between 0.4 and 0.7). In this embodiment, an optical axis238of the microlens may be centered on aperture122. In another embodiment, each lens132is a microsphere and may have a numerical aperture of approximately 1.0 (such as between 0.9 and 1.4). Each pixel112may have a square cross section with side length264, such that the pixel pitch along rows and columns of the array of pixels112is the same as side length264. Each aperture122may have a circular cross section with diameter266, or a square cross section with side length266. Side length264may be in the range between 0.8 microns (approximately the lower limit for satisfactory focusing and light collection performance achievable with presently available microlens manufacturing technology) and 10 microns (corresponding to an upper limit on acceptable resolution of the array of pixels112in some scenarios), and diameter/side-length266may be in the range between 0.25 microns and half of side length264. With such dimensions, an accurate description of the light coupling into cavities120and light propagation inside cavities120must take into account the wave nature of the light. However, for illustrative purposes and without being bound by theory, a simplified description of image sensor100may be useful for evaluating the effect of certain parameters of image sensor100. For illustrative purposes and without being bound by theory, consider a simplified model of a single pixel112and its associated lens132, and assume that the focal point of lens132coincides with aperture122. In this model, light182is refracted by lens132to form an Airy pattern on ceiling224. Ideally, to optimize light coupling into cavity120, the Airy disk (the central disk of the Airy pattern) is fully within aperture122, such that diameter/side-length266is no less than Dmin=2(λ/n)πNA,(Eq.1) wherein λ is the free-space wavelength of light182, n is the index of refraction of lens132, and NA is the numerical aperture of lens132. For a lens132with a numerical aperture of 0.5, Dmin=1.27λ/n which, for λ=1060 nanometers and n=1.5 (typical for a polymer), corresponds to Dmin≈900 nanometers. For a lens with a numerical aperture of 1.0, Dmin=0.64λ/n which, for λ=1060 nanometers and n=1.5, corresponds to Dmin≈450 nanometers. In some scenarios, it may be beneficial to operate with a larger diameter/side-length266than Dminto improve light coupling into cavity120. In one embodiment, diameter/side-length266is no less than Dminand no more than a third or half of side length264. In other scenarios, it may be beneficial to operate with a smaller diameter/side-length266than Dminto reduce light leakage out of cavity120via aperture122. In one embodiment, semiconductor substrate110is a silicon-based substrate, and image sensor100provides quantum efficiency improvement especially in the near-infrared spectrum, where the absorption coefficient of silicon is low. Herein, “near-infrared” refers to light having a wavelength in the range between 700 and 1400 nanometers. In another embodiment, semiconductor substrate110is a silicon-germanium-based substrate, and image sensor100provides quantum efficiency improvement especially in the near-infrared spectrum, where the absorption coefficient of silicon-germanium is low, although not as low as the absorption coefficient of silicon. In yet another embodiment, semiconductor substrate110is an indium-gallium-arsenide-based substrate or a germanium substrate, and image sensor100provides quantum efficiency improvement especially in the visible spectrum, where the absorption coefficient of indium-gallium-arsenide and germanium is low. Regardless of the material choice, semiconductor substrate110includes doped regions to form a photodiode in each pixel112. Each pixel112may further include one or more transistors or gates for conducting photo-generated electric charge out of pixel112to produce signal188. Lens array130is implemented in a light transport layer136disposed over top surface114on ceilings224and spanning over apertures122. Light transport layer136may include one or more wavelength filters. In one embodiment, image sensor100is a monochrome image sensor. In this embodiment, light transport layer136may be substantially optically clear in a desired operating wavelength range, optionally while blocking light outside the desired operating wavelength range. In one example, light transport layer136is configured to transmit near-infrared light and block visible light. In another example, light transport layer136is configured to transmit both visible and near-infrared light. In another embodiment, image sensor100is a color image sensor, wherein pixels112include a plurality of groups of pixels112dedicated to detecting light of a respective plurality of colors, such as red, green, blue, and near-infrared. In this embodiment, light transport layer136may include a color filter array between lens array130and top surface114, or incorporated in lenses132. FIG.1depicts image sensor100in an example use scenario, wherein image sensor100is deployed in a camera102set up to image a scene180at night, and semiconductor substrate110is a silicon-based substrate. Camera102is configured to capture images of a scene180, through detection of near-infrared light from scene180. Thus, in the depicted example use scenario, light182is in the near-infrared spectrum. Camera102includes image sensor100and an imaging objective170. Imaging objective170may be a single lens or a composite lens system that includes a plurality of optical elements. Night imaging based on near-infrared light is typically a low-light scenario, and silicon has a low absorption coefficient in the near-infrared spectrum. It may therefore be challenging to achieve sufficient image brightness with a reasonably short exposure time. Camera102benefits from the enhanced quantum efficiency of image sensor100to be capable of at least partly compensating for the low absorption coefficient of silicon and a low level of near-infrared light available for imaging. In one implementation, camera102is a monochrome night-vision camera configured to image near-infrared light. In another implementation, camera102is a color camera configured to capture both color images and near-infrared images, using respective subsets of pixels112. For each pixel112, the reflective material, forming cavity120, forms ceiling224, a floor226, and sidewalls228. Floor226may be at a bottom surface216of semiconductor substrate110facing in the direction opposite of top surface114. Each of ceiling224, floor226, and sidewalls228may include metal, such as aluminum, and/or a low-index-of-refraction (low-n) dielectric, such as an oxide (e.g., silicon dioxide) or a polymer. Herein, a “low-n dielectric” refers to a dielectric material having an index of refraction that is less than 1.6. Ceiling224, floor226, and sidewalls228may be separate from each other and/or two or more of ceiling224, floor226, and sidewalls228, may have different respective material compositions. In one implementation, sidewalls228are or include deep-trench isolation that electrically isolates adjacent pixels112from each other. In this implementation, one set of sidewalls228of image sensor100may form a plurality of continuous walls, each running between adjacent rows of the array of pixels112inFIG.3, and another set of sidewalls228may form a plurality of continuous walls, each running between adjacent columns of the array of pixels112inFIG.3. In one embodiment, the surface of floor226facing cavity120, and optionally also the surface of ceiling224facing cavity120, has a jagged profile to at least partly randomize the propagation of light182inside cavity120so as to improve light trapping by cavity120. In one example of this embodiment, floor226and, optionally also ceiling224, includes pyramid-like features protruding into cavity120. In another example of this embodiment, floor226, and optionally also ceiling224, includes surfaces that are at an oblique angle to thickness162. Image sensor100may include a connection layer240disposed below bottom surface216on floors226. Connection layer240includes electrical connections to pixels112that are used to conduct electrical signals188to external connections (not shown inFIGS.1,2, and3). In one embodiment, each floor226is at least in part a metal electrode that serves both to (a) reflect light propagating inside cavity120and (b) participate in readout of electrical signals188from pixels112. FIGS.4A and4Billustrate one light-trapping image sensor400equipped with a 100% fill-factor microlens array.FIG.4Ais a cross-sectional view of image sensor400, andFIG.4Bis a top view of an array of pixels of image sensor400. The cross section inFIG.4Ais taken along line4A-4A′ inFIG.4B.FIGS.4A and4Bare best viewed together in the following description. Without departing from the scope hereof, image sensor400may include more or fewer pixels than depicted inFIGS.4A and4B. Herein, a fill factor of 100% refers to a lens array that does not have a gap between adjacent lenses. It is understood, however, that deviations from the desired lens surface profiles may exist at the boundary between adjacent lenses, such that only, e.g., 95-99% of the lens array area is fully functional. Image sensor400is an embodiment of image sensor100that includes semiconductor substrate110, an array of pixels412formed in and on semiconductor substrate110, and a light transport layer436. Each pixel412is an embodiment of pixel112having a cavity420. Each pixel412has a side length264that may be in the range between 0.8 microns and 10 microns. The pixel pitch of pixels412is identical to side length264. Cavity420is an embodiment of cavity120that implements ceiling124and a ceiling424which forms an aperture422to allow light182to enter cavity420. Light transport layer436is an embodiment of light transport layer136that includes a microlens array430(an embodiment of lens array130) of plano-convex microlenses432disposed on an intermediate layer437that, in turn, is disposed on top surface114over ceilings424of pixels412. Intermediate layer437and microlenses432are configured such that each microlens432focuses light182approximately at aperture422. However, microlenses do not have a high numerical aperture and therefore do not focus light182very tightly, as indicated by Eq. 1 where Dminis inversely proportional to the numerical aperture. Thus, to allow entry into cavity420of a substantial portion of light focused by microlenses432, the transverse extent466(e.g., diameter or side length) of aperture422must be relatively large. In one example, the numerical aperture of each microlens432is 0.25, such that Dmin=2.55λ/n which, for λ=1060 nanometers and n=1.5, corresponds to Dmin≈1800 nanometers. FIGS.5A and5Billustrate one light-trapping image sensor500equipped with a sub-100% fill-factor microlens array.FIG.5Ais a cross-sectional view of image sensor500, andFIG.5Bis a top view of an array of pixels of image sensor500. The cross section inFIG.5Ais taken along line5A-5A′ inFIG.5B.FIGS.5A and5Bare best viewed together in the following description. Image sensor500is an embodiment of image sensor100. Without departing from the scope hereof, image sensor500may include more or fewer pixels than depicted inFIGS.5A and5B. Image sensor500is similar to image sensor400except that (a) microlens array430is replaced by a microlens array530of plano-convex microlenses532, and (b) pixels412are replaced by pixels512. Each pixel512is similar to pixel412except for having a different cavity-ceiling configuration. Each pixel512forms a cavity520with a ceiling524that forms an aperture522with transverse extent566(e.g., diameter or side length). Microlenses532have been shrunk, relative to microlenses432, to achieve a higher numerical aperture. The thickness563of intermediate layer437is such that the focal point of each microlens532is at the corresponding aperture522. By virtue of the higher numerical aperture of microlenses532, transverse extent566may be made smaller than transverse extent466while ensuring satisfactory light coupling into cavities520. Each microlens532has a diameter568and a height565. In one example, each microlens532is a spherical lens (that is, the surface profile of the convex lens surface of microlens532is spherical), height565is approximately half of diameter568, and the refractive index of microlens532is approximately 1.5. In this example, per the equations NA=D/(2f) and f=R/(n−1) (wherein D and f are the diameter and focal length, respectively, of microlens532, and R is the radius of curvature of the convex surface of microlens532), the numerical aperture of each microlens532is 0.5. According to Eq. 1, in this example, Dmin=1.27λ/n which, for λ=1060 nanometers, corresponds to Dmin≈900 nanometers. This is a substantial improvement over image sensor400. As compared to image sensor400, image sensor500facilitates an improved trade-off between (i) efficiency of light coupling into cavities520and (ii) the light-trapping performance of cavities520. In one embodiment, transverse extent564is in the range between 500 nanometers and one half of the pixel pitch (side length264) of pixels512. As a result of the shrinking of microlenses532, the fill factor of microlens array530is less than 100%. Microlenses532are spaced apart from each other, such that each adjacent pair of microlenses532have a planar surface portion534of intermediate layer437therebetween. Nearest-neighbor microlenses532has a minimum separation569therebetween. Separation569is a non-zero distance, and diameter568is less than side length264(pixel pitch) of pixels512. Even though the light collection efficiency of microlens array530suffers from the fill factor being less than 100%, the improved performance of cavities520outweighs this loss to provide an enhancement in quantum efficiency over image sensor400. FIGS.6A and6Billustrate one light-trapping image sensor600with a microsphere array630.FIG.6Ais a cross-sectional view of image sensor600, andFIG.6Bis a top view of microsphere array630. The cross section inFIG.6Ais taken along line6A-6A′ inFIG.6B.FIGS.6A and6Bare best viewed together in the following description. Image sensor600is an embodiment of image sensor100. Without departing from the scope hereof, image sensor600may include more or fewer pixels than depicted inFIGS.6A and6B. Image sensor600is similar to image sensor500except that (a) light transport layer536is replaced by microsphere array630, and (b) pixels512are replaced by pixels612. Each pixel612is similar to pixel512except for forming a cavity620with a ceiling624that forms an aperture622with transverse extent666(e.g., diameter or side length). Microsphere array630is an embodiment of lens array130and includes an array of microspheres632. The back focal length of each microsphere632is short and may, to a first approximation, be assumed to be near-zero. Therefore, each microsphere632is disposed directly on a respective pixel612, centered on aperture622. Per the equations NA=D/(2f) and f=R/[2(n−1)] (wherein D, f, and R are the diameter, focal length, and radius, respectively, of microsphere632), the numerical aperture of each microsphere632is NA=2(n−1). In one example, the refractive index of microsphere632is n=1.5 and the numerical aperture of microsphere632is therefore 1.0. In this example, Dmin≈450 nanometers at λ=1060 nanometers. As compared to image sensor500, microsphere array630of image sensor600thus facilitates further improvement in the trade-off between (i) efficiency of light coupling into cavities620and (ii) the light-trapping performance of cavities620. In an embodiment, transverse extent666is greater than 250 nanometers and less than one third of the pixel pitch. In one embodiment, the diameter663of each microsphere632approximately matches side length264(pixel pitch) of pixels612. In this embodiment, diameter663may be in the range between 90% and 100% of side length264, and microsphere array630may be formed by depositing a colloidal suspension of microspheres onto semiconductor substrate110. In another embodiment, diameter663is between 50% and 90% of side length264. In this embodiment, microsphere array630may be molded before placing the fully formed microsphere array630on the array of pixels612. Even though the fill factor of microsphere array630is less than 100% and microsphere array630therefore does not collect all light incident on image sensor600, the improved performance of cavities620outweighs the loss in light collection efficiency to provide an enhancement in quantum efficiency over both image sensor400and image sensor500. Each aperture622may be empty between semiconductor substrate110and the corresponding microsphere632. In an alternative embodiment, each aperture622may be filled with a clear material, such as a low-n dielectric that allows light182to enter cavity620while back-reflecting light propagating in cavity620when such light is incident on the low-n dielectric at an angle that is shallower than the critical angle for total internal reflection. FIGS.7A and7Billustrate one light-trapping color image sensor700with a color-filtering microsphere array730.FIG.7Ais a cross-sectional view of image sensor700, andFIG.7Bis a top view of microsphere array730. The cross section inFIG.7Ais taken along line7A-7A′ inFIG.7B.FIGS.7A and7Bare best viewed together in the following description. Without departing from the scope hereof, image sensor700may include more or fewer pixels than depicted inFIGS.7A and7B. Image sensor700is an embodiment of image sensor600that implements microsphere array630as color-filtering microsphere array730. Color-filtering microsphere array730includes a plurality of microspheres732R,732G,732B, and73218, selectively transmissive to red, green, blue, and near-infrared light, respectively. Each of microspheres732R,732G,732B, and7321R is an embodiment of microsphere632that includes or is composed of a color filtering material. Color-filtering microsphere array730arranges microspheres732R,732G,732B, and7321R in an array of identical microsphere groups710, each including one microsphere732R, one microsphere732G, one microsphere732B, and one microsphere7321R. Without departing from the scope hereof, color-filtering microsphere array730may be configured to selective transmit a different set of wavelength ranges than red, green, blue, and near-infrared. More generally, color-filtering microsphere array730includes an array of identical microsphere groups, each including a plurality of microspheres selectively transmissive to light in a respective plurality of different wavelength ranges. FIGS.8A and8Billustrate one light-trapping color image sensor800with separate microsphere and color filter arrays.FIG.8Ais a cross-sectional view of image sensor800, andFIG.8Bis a top view of a color filter array840of image sensor800. The cross section inFIG.8Ais taken along line8A-8A′ inFIG.8B.FIGS.8A and8Bare best viewed together in the following description. Without departing from the scope hereof, image sensor800may include more or fewer pixels than depicted inFIGS.8A and8B. Image sensor800is an embodiment of image sensor600that further includes a color filter array840, and wherein all microsphere632are identical and substantially transmissive to light throughout the operating wavelength range of image sensor800. Due to the short (near-zero) back focal length of microspheres632, color filter array840does not fit between microsphere array630and the array of pixels612. Instead, color filter array840is disposed on top of microsphere array630, such that microsphere array630is sandwiched between color filter array840and the array of pixels612. Color-filter array840includes a plurality of color filters842R,842G,842B, and84218, selectively transmissive to red, green, blue, and near-infrared light, respectively. Each color filter of color filter840is registered to a respective microsphere632of microsphere array630. Color-filter array840arranges color filters842R,842G,842B, and8421R in an array of identical color filter groups810, each including one color filter842R, one color filter842G, one color filter842B, and one color filter8421R. Without departing from the scope hereof, color filter array840may be configured to selective transmit a different set of wavelength ranges than red, green, blue, and near-infrared. More generally, color filter array840includes an array of identical color filter groups, each including a plurality of color filters selectively transmissive to light in a respective plurality of different wavelength ranges. FIGS.9A and9Billustrate one light-trapping color image sensor900with separate microlens and color filter arrays.FIG.9Ais a cross-sectional view of image sensor900, andFIG.9Bis a top view of a color-filtering light transport layer936of image sensor900. The cross section inFIG.9Ais taken along line9A-9A′ inFIG.9B.FIGS.9A and9Bare best viewed together in the following description. Without departing from the scope hereof, image sensor900may include more or fewer pixels than depicted inFIGS.9A and9B. Image sensor900is an embodiment of image sensor500wherein light transport layer536is implemented as color-filtering light transport layer936. Color-filtering light transport layer936implements intermediate layer437as a color filter array940. Color filter array940includes a plurality of color filters942R,942G,942B, and9421R, selectively transmissive to red, green, blue, and near-infrared light, respectively. Each color filter of color filter940is registered to a respective pixel512. Color-filter array940arranges color filters942R,942G,942B, and9421R in an array of identical color filter groups910, each including one color filter942R, one color filter942G, one color filter942B, and one color filter94218. Without departing from the scope hereof, color filter array940may be configured to selective transmit a different set of wavelength ranges than red, green, blue, and near-infrared. More generally, color filter array940includes an array of identical color filter groups, each including a plurality of color filters selectively transmissive to light in a respective plurality of different wavelength ranges. FIG.10illustrates, in cross-sectional view, one light-trapping image sensor1000with cavity ceilings and floors having a jagged surface profile to introduce randomization of light propagation inside the cavities. Such randomization may improve light trapping in the cavities. Image sensor1000is an embodiment of image sensor600that implements each pixel612as a pixel1012. Each pixel1012has a cavity1020with a ceiling1024, a floor1026, and sidewalls228. Cavity1020, ceiling1024, and floor1026are embodiments of cavity620, ceiling624, and floor226, respectively. Ceiling1024forms aperture622. In each pixel1012, at least a portion1027of the surface of each of ceiling1024and floor1026is jagged to randomize the reflection of light off ceiling1024. In one example, the jagged surface profile is achieved by a plurality of pyramids extending into cavity1020. More generally, the jagged surface profile includes a plurality of surfaces that are at different oblique angles to thickness162. In one embodiment, sidewalls228are smooth, at least because it is challenging to form a jagged surface profile on sidewalls228. AlthoughFIG.10shows both ceiling1024and floor1026being jagged in places, image sensor1000may instead implement only one of ceiling1024and floor1026with jagged surface profile, without departing from the scope hereof. AlthoughFIG.10shows only a portion of floor1026being jagged, all of floor1026may have a jagged surface profile facing cavity1020, without departing from the scope hereof. Also without departing from the scope hereof, jagged features may be formed at least in part by a clear material (such as a low-n dielectric), in which case, the jagged features may span across aperture622. FIG.11illustrates, in top plan view, a cavity wall1100having a plurality of pyramids1127protruding into the cavity. Cavity wall1100is an embodiment of either one of ceiling1024and floor1026. Pyramids1127may span all of cavity wall1100or only a portion of cavity wall1100. In one example, cavity wall1100is a cavity floor, and a central portion1129of cavity wall1100is free of pyramids1127to instead accommodate one or more gates for transferring photo-generated charge out of cavity1020. FIG.12illustrates one light-trapping image sensor1200with low-n dielectric pyramids extending into the cavities. Image sensor1200is an embodiment of image sensor1000implementing and embodiment of cavity wall1100as both the cavity floor and the cavity ceiling. Image sensor1200includes a plurality of pixels1212(embodiments of pixels1012). Each pixel1212forms a cavity1220with a ceiling1224and a floor1226. Ceiling1224includes a metal layer1225and low-n dielectric pyramids1227(examples of pyramids1127) protruding into cavity1220. Pyramids1227span across aperture622and serve to reduce back-reflection of light incident on aperture622from microsphere632. Metal layer1225is interrupted by aperture622which is filled by low-n dielectric. The bases of pyramids1227of ceiling1224may be at the surface of metal layer1225facing cavity1220, or the bases of pyramids1227may be distanced from metal layer1225by a continuous layer of low-n dielectric. Floor1226includes a metal layer1228and low-n dielectric pyramids1227protruding into cavity1220. Optionally, as indicated inFIG.12, a central portion of each floor1226is free of pyramids1227to instead accommodate one or more gates1252for transferring photo-generated charge from a photodiode1250out of cavity1220. For clarity of illustration, gate(s)1252and photodiode1250are depicted only in one pixel1212inFIG.12. Metal layer1228may participate in the readout of photo-generated charge. In one implementation, metal layer1228may be interrupted below gate1252to allow a contact from gate(s)1252to another metal layer of connection layer240. In each of ceiling1224and floor1226, the low-n dielectric material back reflects light incident at an angle that is shallower than the critical angle for total internal reflection. When semiconductor substrate110is a silicon-based substrate and the index of refraction of the low-n dielectric material is 1.45, the critical angle for total internal reflection is approximately 25 degrees (with respect to the surface normal). Thus, for a majority of incidence angles, the low-n dielectric material will back-reflect light by means of total internal reflection. Light that is incident at steeper angles than the critical angle is instead back-reflected by the metal layers. FIG.13illustrates one light-trapping pixel1300that utilizes a combination of low-n dielectric and metal to form a cavity1320. Each wall of cavity1320includes metal lined with low-n dielectric. Pixel1300is an embodiment of pixel1212combined with respective portion of connection layer240(shown inFIG.13as connection layer portion1340). Cavity1320encloses photodiode1250. The ceiling of cavity1320includes a metal layer1325forming aperture622, and low-n-dielectric that (a) lines the side of metal layer1325facing cavity1320and (b) forms pyramids1227. The floor of cavity1320includes a metal layer1328, and low-n-dielectric that (a) lines the side of metal layer1328facing cavity1320and (b) forms pyramids1227. The floor of cavity1320has no pyramids at a central location where gate(s)1252conduct photo-generated charge out of cavity1320through an opening in metal layer1328to a metal connection1342. Metal layer1328may be connected to a part of gate(s)1252to participate in the readout of this photo-generated charge. Each sidewall of cavity1320include a metal wall1339with a low-n dielectric lining1338. In an alternative embodiment, pyramids1227are replaced by a flat low-n dielectric lining. Each pyramid1227may have a depth1360in the range between 0.2 and 1.0 microns. In pixel1300, the low-n dielectric may be an oxide, e.g., silicon dioxide. Each of pixels1012,1212, and1300, and related embodiments discussed above in reference toFIGS.10-13, may be implemented in any one of image sensors400,500,600,700,800, and900, without departing from the scope hereof. FIG.14illustrates one method1400for manufacturing light-trapping image sensor100. Method1400includes steps1420,1430, and1450. Method1400takes semiconductor substrate110as input. Step1420forms sidewalls228between pixels. Step1420may implement a step1422of forming the deep-trench isolation between pixels of semiconductor substrate110, such that this deep-trench isolation forms at least part of sidewalls228. Step1430deposits metallic or low-n dielectric material on the backside and frontside of semiconductor substrate110to form at least part of ceiling224and floor226, respectively. Step1450deposits lens array130on the backside of semiconductor substrate110on top of ceilings224or on top of a color filter array (if present) disposed on top of ceilings224. In one embodiment, step1450includes a step1452of depositing microspheres632over the pixels to form microsphere array630. Step1452may include either one of steps1454and1456. Step1454deposits microspheres632on a patterned surface, for example as discussed by Mitsui et al. in “Micro demultiplexer fabricated by self-assembly of microspheres on a patterned substrate”, 2009, 11th International Conference on Transparent Optical Networks, which is incorporated herein by reference in its entirety. Step1456forms the microsphere array using diffuser lithography and plastic replication, for example as discussed by Chang et al. in “Shape-controlled, high fill-factor microlens arrays fabricated by a 3D diffuser lithography and plastic replication method”, Optics Express, 2004, Vol. 12, No. 25, pp. 6366-6371, which is incorporated herein by reference in its entirety, whereafter the microsphere array is deposited on semiconductor substrate110. In another embodiment, step1450includes a step1458of forming microlens array430or530. In certain embodiments, step1430is preceded by a step1410of forming a jagged surface profile on the backside and/or the frontside of semiconductor substrate110. Step1410may include a step1412of lithographically forming inverted-pyramid recesses in semiconductor substrate110, for example by laser interference lithography and a subsequent pattern transfer process using reactive ion etching followed by KOH etching, as outlined in Amalraj Peter Amalathas and Maan M. Alkaisi (May 2nd 2018), “Fabrication and Replication of Periodic Nanopyramid Structures by Laser Interference Lithography and UV Nanoimprint Lithography for Solar Cells Applications, Micro/Nanolithography—A Heuristic Aspect on the Enduring Technology”, Jagannathan Thirumalai, IntechOpen, DOI: 10.5772/intechopen.72534, available from https://www.intechopen.com/books/micro-nanolithography-a-heuristic-aspect-on-the-enduring-technology/fabrication-and-replication-of-periodic-nanopyramid-structures-by-laser-interference-lithography-and, which is incorporated herein by reference in its entirety. Embodiments of method1400implementing step1458, may further include a step1440, before step1450, of depositing color filter array940on semiconductor substrate110. Embodiments of method1400implementing step1452, may further include a step1460, after step1450, of depositing color filter array840on microsphere array630. FIG.15plots, as a curve1510, finite-difference time-domain (FDTD) simulated quantum efficiency at a wavelength of 1060 nanometers as function of diameter663of microspheres632in one example of image sensor600that (a) is characterized by side length264(pixel pitch) being 1.1 microns, thickness162being 6 microns, the refractive index of microspheres632being 1.5, transverse extent666being 0.6 microns, and semiconductor substrate110being a silicon substrate, and (b) implements each pixel612as pixel1300, wherein metal layers1325,1328, and1338are aluminum, the low-n dielectric is silicon-dioxide, the ceiling has a 3×3 array of pyramids1227, and the floor has a 3×3 array of pyramids1227with the central pyramid1227omitted. Curve1510peaks at a quantum efficiency of 30%, achieved at a microsphere diameter of 1.8 microns (see point1512). For comparison,FIG.15also plots, as a line1530, the corresponding quantum efficiency achieved for an image sensor that does not have light-trapping cavities but is enhanced by a single inverted pyramid per pixel in the light-receiving surface of the silicon substrate to reduce back-reflection.FIG.15shows that this example of light-trapping image sensor600represents a three-fold improvement over the non-light-trapping image sensor. FIG.16plots FDTD-simulated quantum efficiencies at a wavelength of 1060 nanometers for examples of image sensors400and500, as a function of a correction to thickness461of intermediate layer437. Curve1610is the FDTD-simulated quantum efficiency for one example of image sensor500that (a) is characterized by side length264(pixel pitch) being 1.1 microns, thickness162being 6 microns, the refractive index of microlenses532being 1.5, transverse extent566being 0.6 microns, and semiconductor substrate110being a silicon substrate, and (b) implements each pixel512as pixel1300, wherein metal layers1325,1328, and1338are aluminum, the low-n dielectric is silicon-dioxide, the ceiling has a 3×3 array of pyramids1227, and the floor has a 3×3 array of pyramids1227with the central pyramid1227omitted. Curve1620is the FDTD-simulated quantum efficiency for a corresponding example of image sensor500. For curve1610, the fill factor is 78%. For curve1620, the fill factor is 99%. For comparison,FIG.16also plots line1530ofFIG.15.FIG.16shows that image sensor500with a microlens fill factor of 78% outperforms image sensor400with a microlens fill factor of 99%, while both image sensor400and500outperform the non-light-trapping image sensor associated with line1530. In theFIG.16example, the quantum efficiency of image sensor500peaks at 13% (see point1622), and the quantum efficiency of image sensor400peaks at 23% (see point1612). ComparingFIGS.15and16, it is evident that image sensor600represents an improvement over both image sensor400and image sensor500, at least in these examples. Combinations of Features Features described above as well as those claimed below may be combined in various ways without departing from the scope hereof. For example, it will be appreciated that aspects of one light-trapping image sensor or associated method, described herein, may incorporate features or swap features of another light-trapping image sensor or associated method described herein. The following examples illustrate some possible, non-limiting combinations of embodiments described above. It should be clear that many other changes and modifications may be made to the methods, products, and systems herein without departing from the spirit and scope of this invention:(A1) One light-trapping image sensor includes a pixel array and a lens array. The pixel array is formed in and on a semiconductor substrate and including photosensitive pixels each including a reflective material forming a cavity around a portion of semiconductor material to at least partly trap light that has entered the cavity. The cavity has a ceiling at a light-receiving surface of the semiconductor substrate, and the ceiling forms an aperture for receiving the light into the cavity. The lens array is disposed on the pixel array. Each lens of the lens array is aligned to the aperture of a respective cavity to focus the light into the cavity through the aperture.(A2) The image sensor denoted as (A1) may be a backside-illuminated complementary metal oxide semiconductor image sensor, and the semiconductor material may be silicon.(A3) In either one of the image sensors denoted as (A1) and (A2), each lens may be a microsphere.(A4) In the image sensor denoted as (A3), each microsphere may be disposed directly on a respective one of the photosensitive pixels.(A5) In either one of the image sensors denoted as (A3) and (A4), the pixel array may be a rectangular array, wherein the photosensitive pixels have a pixel pitch along rows and columns of the pixel array, and the diameter of each microsphere may be equal to the pixel pitch.(A6) Any of the image sensors denoted as (A3) through (A5) may be a color image sensor further including a color filter array disposed above the lens array to spectrally filter the light before being focused by the microspheres, wherein the color filter array is an array of identical color filter groups each including a plurality of color filters configured to transmit light in a respective plurality of spectral ranges.(A7) Any of the image sensors denoted as (A3) through (A5) may be a color image sensor, wherein each microsphere is formed from a color-filtering material to spectrally filter the light while focusing the light, and wherein the lens array is an array of identical microsphere groups each including a plurality of microspheres configured to selectively transmit light in a respective plurality of spectral ranges.(A8) In either of the image sensors denoted as (A6) and (A7), the semiconductor material may be silicon, and one of the spectral ranges may include near-infrared wavelengths.(A9) In either of the image sensors denoted as (A1) and (A2), each lens may be a plano-convex microlens with a convex surface for receiving the light into the plano-convex microlens.(A10) In the image sensor denoted as (A9), the lens array may have less than 100% fill factor such that each plano-convex microlens is separated from each of its adjacent plano-convex microlenses by a non-zero distance.(A11) In either of the image sensors denoted as (A9) and (A10), focal point of each plano-convex microlens may be at the aperture of the corresponding cavity.(A12) Any of the image sensors denoted as (A9) through (A11) may be a color image sensor further including a color filter array disposed between the pixel array and the lens array, wherein the color filter array is an array of identical color filter groups each including a plurality of color filters configured to transmit light in a respective plurality of spectral ranges.(A13) In the image sensor denoted as (A12), the semiconductor material may be silicon, and one of the spectral ranges may include near-infrared wavelengths.(A14) In any of the image sensors denoted as (A1) through (A13), the ceiling may include metal.(A15) In any of the image sensors denoted as (A1) through (A14), each cavity may further have a floor, and sidewalls spanning between the floor and the ceiling, wherein, for each cavity, the floor includes a respective metal contact for conducting a photo-generated charge out of the cavity.(A16) In any of the image sensors denoted as (A1) through (A14), each cavity may further have a floor, and sidewalls spanning between the floor and the ceiling, wherein, for each cavity, the sidewalls include deep trench isolation.(A17) In the image sensor denoted as (A16), the deep trench isolation may include metal and an oxide layer lining the metal.(A18) In either of the image sensors denoted as (A16) and (A17), the sidewalls may be shared between adjacent photosensitive pixels such that, where the deep trench isolation is between adjacent first and second photosensitive pixels, the metal or low-index-of-refraction dielectric of the deep trench isolation is lined by a first oxide layer facing the first photosensitive pixel and a second oxide layer facing the second photosensitive pixel.(A19) In any of the image sensors denoted as (A1) through (A14), each cavity may further have a floor, and sidewalls spanning between the floor and the ceiling, wherein, for each cavity, one or both of the floor and the ceiling are at least partly jagged.(A20) In the image sensor denoted as (A19), jagged portions of the one or both of the floor and ceiling may have pyramids extending into the semiconductor material enclosed by the cavity. Changes may be made in the above systems and methods without departing from the scope hereof. It should thus be noted that the matter contained in the above description and shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover generic and specific features described herein, as well as all statements of the scope of the present systems and methods, which, as a matter of language, might be said to fall therebetween. | 44,807 |
11862652 | DETAILED DESCRIPTION An embodiment of the present disclosure will be described below in detail with reference to the drawings. It is to be noted that the description will be provided in the following order.1. Embodiment (an example in which a fixed charge film has a multilayer structure, and layers are formed using different manufacturing methods)2. Modification (an example in which a light-shielding film is provided also in a pixel separation groove)3. Application examples (application examples to a solid-state image pickup device and an electronic apparatus) 1. Embodiment FIG.1illustrates a cross-sectional configuration of an image pickup element (an image pickup element10) according to an embodiment of the present technology. The image pickup element10may configure, for example, one pixel (for example, a pixel P), in an image pickup device (an image pickup device1) such as a CCD image sensor and a CMOS image sensor (seeFIG.5). The image pickup element10may be of a backside illumination type, and includes a light receiving section20, a wiring layer30, and a condensing section40. The light receiving section20includes a photoelectric conversion section22. The condensing section40is provided on a light incident surface (a light-receiving surface S1) side of the light receiving section20. The wiring layer30is provided on a surface on a side opposite to the light incident surface side. The light receiving section20includes a semiconductor substrate21, a fixed charge film23, and a protective film24. The semiconductor substrate21has a groove (a pixel separation groove21A), which is provided on the light incident surface side and between the pixels P. The fixed charge film23and the protective film24are provided on an entire surface, which is on the light incident surface side, of the semiconductor substrate21. The image pickup element10of the present embodiment partially has a laminated structure in which the fixed charge film23is formed of two kinds of insulating films (a first insulating film23A and a second insulating film23B) that are formed in different regions. A configuration of the image pickup element10will be described below, in order of the light receiving section20, the wiring layer30, and the condensing section40. (Light Receiving Section) The light receiving section20includes the semiconductor substrate21and the fixed charge film23. In the semiconductor substrate21, for example, a photodiode may be embedded as the photoelectric conversion section22. The fixed charge film23is provided on a back surface (the light incident surface, or the light-receiving surface S1) of the semiconductor substrate21. The semiconductor substrate21may be configured of, for example, p-type silicon (Si), and has the pixel separation groove21A as described above. The pixel separation groove21A is provided between the pixels P on the light-receiving surface S1side, to extend in a thickness direction (a Z direction) of the semiconductor substrate21. A depth (a height (h)) of the pixel separation groove21A may only be a depth allowing suppression of crosstalk, and may be, for example, 0.25 μm or more and 5 μm or less. A width (W) of the pixel separation groove21A may only be a width allowing suppression of crosstalk, and may be, for example, 100 nm or more and 1,000 nm or less. In proximity to the surface (a surface S2) of the semiconductor substrate21, a transfer transistor is disposed. The transfer transistor may transfer, for example, signal charge generated in the photoelectric conversion section22, to a vertical signal line Lsig (seeFIG.5). A gate electrode of the transfer transistor may be, for example, provided in the wiring layer30. The signal charge may be either an electron or a positive hole generated by photoelectric conversion. Here, a case in which an electron is read out as the signal charge will be described as an example. In proximity to the surface S2of the semiconductor substrate21, for example, components such as a reset transistor, an amplifying transistor, and a select transistor may be provided together with the above-described transfer transistor. Such transistors may each be, for example, a metal oxide semiconductor field effect transistor (MOSEFT), and included in a circuit for each of the pixels P. Each of the circuits may have, for example, a three-transistor configuration including a transfer transistor, a reset transistor, and an amplifying transistor, or may have a four-transistor configuration including a select transistor in addition to these three transistors. The transistors except the transfer transistor may also be shared by the pixels. The photoelectric conversion section22(the photodiode) may be, for example, an n-type semiconductor region, which is formed in the thickness direction (the Z direction) of the semiconductor substrate21(here, a Si substrate), for each of the pixels P. The photoelectric conversion section22may be a pn-junction-type photodiode, with a p-type semiconductor region provided in proximity to a front surface and a back surface of the semiconductor substrate21. It is to be noted that, in the semiconductor substrate21, a p-type semiconductor region is also formed between the pixels P, and the above-described pixel separation groove21A is formed in this p-type semiconductor region. The fixed charge film23has negative charge, and has a configuration in which the first insulating film23A and the second insulating film23B are partially laminated (for example, seeFIG.2C). Specifically, the first insulating film23A is provided on the entire back surface of the semiconductor substrate21, namely, provided on the light-receiving surface S1of the semiconductor substrate21as well as contiguously from a wall surface to a bottom surface of the pixel separation groove21A. It is to be noted that the first insulating film23A includes multiple layers (here, two layers (23A1and23A2)). The second insulating film23B is provided on a region (the light-receiving surface S1), which excludes an inner wall (the wall surface and the bottom surface) of the pixel separation groove21A, of the semiconductor substrate21. It is to be noted that the second insulating film23B is formed contiguously from the light-receiving surface S1to a part of the wall surface of the pixel separation groove21A. The first insulating film23A may be formed by, for example, atomic layer deposition (ALD) or metal organic chemical vapor deposition (MOCVD). The second insulating film23B may be formed, for example, by physical vapor deposition (PVD). The first insulating film23A and the second insulating film23B may be formed in any lamination order, if the first insulating film23A is at least directly formed on the semiconductor substrate21. In the present embodiment, as illustrated inFIG.2C, the fixed charge film23may have, for example, a configuration in which the first insulating film23A1, the second insulating film23B, and the first insulating film23A2are laminated in this order from the semiconductor substrate21side. Alternatively, as illustrated inFIG.3C, the first insulating film23A1, the first insulating film23A2, and the second insulating film23B may be laminated in this order from the semiconductor substrate21side. The first insulating films23A1and23A2may each preferably have, for example, a thickness of 1 nm or more 25 nm or less. The first insulating film23A (23A1and23A2) may be preferably formed to have an overall thickness of 2 nm or more and 100 nm or less. This makes it possible to improve pinning performance of the semiconductor substrate21on the wall surface and the bottom surface of the pixel separation groove21A. The second insulating film23B may preferably have, for example, a film thickness of 10 nm or more and 80 nm or less. As a material of the fixed charge film23(23A and23B), a high dielectric material having fixed charge may be preferably used. Specific examples of the material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and tantalum oxide (Ta2O5). These oxides have been used for films such as a gate insulating film of an insulated-gate field-effect-transistor and therefore, a film formation method has been established. Hence, films of these oxides may be easily formed. In particular, using materials such as HfO2(a refractive index of 2.05), Ta2O5(a refractive index of 2.16), and TiO2(a refractive index of 2.20) whose refractive index is relatively low, adds an antireflection effect to the fixed charge film23. Other examples of the material may include rare earth element oxide. Specific examples of the rare earth element oxide may include lantern (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). It is to be noted that silicon (Si) may be added to the above-described oxide to the extent of not impairing an insulation property. Alternatively, other than the oxide, nitride and oxynitride such as hafnium nitride, aluminum nitride, hafnium oxynitride, and aluminum oxynitride may be used. Adding Si or Ni to the fixed charge film23improves heat resistance and capability of blocking ion implantation to a Si interface and the Si substrate during the process. The first insulating film23A (23A1and23A2) and the second insulating film23B may be configured of the same material, but the materials of the first insulating film23A and the second insulating film23B may be different. A manufacturing process may be simplified using the same material for the first insulating films23A1and23A2that use a common manufacturing method. Alternatively, the first insulating films23A1and23A2as well as the second insulating film23B may be formed using different materials. Preferable materials of each of the insulating films23A1,23A2, and23B may be as follows. First, examples of the preferable material of the first insulating film23A1may include HfO2, ZrO2, and Al2O3. Examples of the preferable material of the first insulating film23A2may include HfO2, ZrO2, Al2O3, TiO2, and Ta2O5. Examples of the preferable material of the second insulating film23B may include HfO2, ZrO2, Al2O3, TiO2, and Ta2O5. In particular, use of a material having a high refractive index for the second insulating film23B, which is formed to be thicker than the first insulating film23A, makes it possible to efficiently obtain an antireflection effect, and to improve sensitivity of the image pickup element10, by increasing light entering the photoelectric conversion section22. The protective film24is provided on the fixed charge film23, and a back surface of the light receiving section20is flattened by filling the pixel separation groove21A with the protective film24. The protective film24may be configured of, for example, a single layer film of silicon nitride (Si2N3), silicon oxide (SiO2), silicon oxynitride (SiON), and the like, or a laminated film of these materials. (Wiring Layer) The wiring layer30is provided in contact with the surface (the surface S2) of the semiconductor substrate21. The wiring layer30includes a plurality of wirings32(for example,32A,32B, and32C) in an interlayer insulating film31. The wiring layer30may be, for example, adhered to a supporting substrate11made of Si. The wiring layer30is disposed between the supporting substrate11and the semiconductor substrate21. (Condensing Section) The condensing section40is provided on the light-receiving surface S1side of the light receiving section20, and has an on-chip lens41on a light incident side. The on-chip lens41is disposed, as an optical functional layer, to face the photoelectric conversion section22of each of the pixels P. Between the light receiving section20(specifically, the protective film24) and the on-chip lens41, a flattening film43and a color filter44are laminated in this order from the light receiving section20side. Further, a light-shielding film42is provided on the protective film24between the pixels P. The on-chip lens41has a function of condensing light towards the light receiving section20(specifically, the photoelectric conversion section22of the light receiving section20). A lens diameter of the on-chip lens41is set at a value corresponding to the size of the pixel P and may be, for example, 0.9 μm or more and 8 μm or less. Further, a refractive index of the on-chip lens41may be, for example, 1.5 or more and 1.9 or less. Examples of a lens material may include an organic material and a silicon oxide film (SiO2). The light-shielding film42may be provided between the pixels P, namely, for example, at a position, which corresponds to the pixel separation groove21A, of the protective film24. The light-shielding film42suppresses color mixture due to crosstalk of obliquely entering light between the adjacent pixels. Examples of a material of the light-shielding film42may include tungsten (W), aluminum (Al), and an alloy of Al and copper (Cu). The light-shielding film42may have, for example, a film thickness of 20 nm or more and 5,000 nm or less. The flattening film43may be configured of, for example, a single layer film of any of silicon nitride (Si2N3), silicon oxide (SiO2), silicon oxynitride (SiON), and the like, or a laminated film of any of these materials. The color filter44may be, for example, any of a red (R) filter, a green (G) filter, a blue (B) filter, and a white filter (W), and may be, for example, provided for each of the pixels P. These color filters44are provided in a regular color array (for example, a Bayer array). In the image pickup element10, light receiving data of colors corresponding to the color array is obtained by providing these color filters44. The image pickup element10as described above may be manufactured as follows, for example. (Manufacturing Method) First, the semiconductor substrate21including various transistors and peripheral circuits are formed. For the semiconductor substrate21, for example, a Si substrate may be used. In proximity to the surface (the surface S2) of the Si substrate, the transistors such as the transfer transistor and the peripheral circuits such as a logic circuit are formed. Next, an impurity semiconductor region is formed by ion implantation to the semiconductor substrate21. Specifically, an n-type semiconductor region (the photoelectric conversion section22) is formed at a position corresponding to each of the pixels P, and a p-type semiconductor region is formed between the pixels P. Subsequently, the pixel separation groove21A may be formed at a predetermined position of the light-receiving surface S1of the semiconductor substrate21, specifically, in the p-type semiconductor region provided between the pixels P. The pixel separation groove21A may be formed by, for example, dry etching, to have a depth (h) of 1 nm, for example. Next, the fixed charge film23is formed on the light-receiving surface S1side of the semiconductor substrate21. Specifically, at first, as illustrated inFIG.2A, the first insulating film23A1may be formed by, for example, ALD or MOCVD. The first insulating film23A1is contiguously provided on the light-receiving surface S1of the semiconductor substrate21as well as from a wall surface to a bottom surface of the pixel separation groove21A. When ALD is used, the first insulating film23A1may be formed based on, for example, such conditions that a substrate temperature is 200° C. to 500° C., a flow quantity of a precursor is 10 sccm to 500 sccm, an irradiation time of the precursor is 1 second to 15 seconds, and a flow quantity of ozone (O3) is 5 sccm to 50 sccm. When MOCVD is used, the first insulating film23A1may be formed, for example, using a substrate temperature of 100° C. to 600° C. It is to be noted that, when the Si substrate is used as the semiconductor substrate21and the first insulating film23A1is formed on the Si substrate by using ALD, a silicon oxide film reducing an interface state and having a thickness of about 1 nm is allowed to be concurrently formed on the surface of the Si substrate. Next, as illustrated inFIG.2B, the second insulating film23B may be formed on the first insulating film23A1, by using, for example, PVD. Conditions for this formation may be, for example, a pressure of 0.01 Pa to 50 Pa, power of 500 W to 2,000 W, an Ar flow quantity of 5 sccm to 50 sccm, and an oxygen (O2) flow quantity of 5 sccm to 50 sccm. It is to be noted that, by a shadowing effect, the second insulating film23B formed by PVD is formed only on the light-receiving surface S1of the semiconductor substrate21and on a part of the wall surface, which is contiguous to the light-receiving surface S1, of the pixel separation groove21A. The second insulating film23B is not formed in inside (most part of the wall surface and the bottom surface) of the pixel separation groove21A. Next, as illustrated inFIG.2C, the first insulating film23A2may be formed on the second insulating film23B and the first insulating film23A1by using, for example, ALD or MOCVD. The first insulating film23A1covers the wall surface and the bottom surface of the pixel separation groove21A. Conditions in ALD and MOCVD are similar to those described above. The fixed charge film23is thus formed. As described above, after the first insulating film23A1is formed on the entire back surface of the semiconductor substrate21by ALD or MOCVD, the second insulating film23B is formed on the light-receiving surface S1side of the first insulating film23A1by PVD. The fixed charge film (23A1,23B, and23A2) having an antireflection function is allowed to be formed on the surface part of the semiconductor substrate21without degrading interfacial quality, and at the same time, the fixed charge film (23A1and23A2) improving the interface state is allowed to be formed in the groove. It is to be noted that, as described above, the fixed charge film23may be formed in film formation order other than the lamination order illustrated inFIGS.2A to2C. Specifically, for example, the fixed charge film23may be formed as illustrated inFIGS.3A to3C. First, the first insulating film23A1is formed in a region from the light-receiving surface S1of the semiconductor substrate21to the wall surface and the bottom surface of the pixel separation groove21A by using ALD or MOCVD in a manner similar to that in the above-described manufacturing process. Subsequently, the first insulating film23A2is formed using ALD or MOCVD again. The second insulating film23B is then formed by PVD. In this way, if at least the insulating film is directly formed on the back surface of the semiconductor substrate21by ALD or MOCVD that is less likely to damage a film-formed surface, any manufacturing method may be adopted for an insulating film to be subsequently laminated. Next, as the protective film24, for example, a SiO2film may be formed on the fixed charge film23on the light-receiving surface S1by using, for example, ALD or chemical vapor deposition (CVD). The pixel separation groove21A is filled with the SiO2film. Subsequently, for example, a W film may be formed on the protective film24by using, for example, sputtering or CVD, and then patterned by photolithography so that the light-shielding film42is formed. Next, the flattening film43is formed on the protective film24and the light-shielding film42. Subsequently, for example, the color filter44in the Bayer array and the on-chip lens41may be formed in this order on the flattening film43. The image pickup element10may be thus obtained. (Operation of Image Pickup Element) In the image pickup element10as described above, signal charge (here, an electron) may be obtained in the pixel P of the image pickup device as follows, for example. Upon entering the image pickup element10through the on-chip lens41, light L passes through the color filter44and the like and then is detected (absorbed) by the photoelectric conversion section22in each of the pixels P, so that red, green, or blue color light is photoelectrically converted. Of an electron-hole pair generated in the photoelectric conversion section22, the electron moves to the semiconductor substrate21(for example, the n-type semiconductor region in the Si substrate) to be stored, while the positive hole moves to the p-type region to be discharged. (Functions and Effects) As described earlier, in an image pickup element having a photoelectric conversion section configured of, for example, a semiconductor material such as Si, a dark current may be easily generated due to crystal defects and dangling bonds present on a surface of the photoelectric conversion section. The dark current may be suppressed by forming an insulating film (a fixed charge film) having fixed charge, on a surface of a semiconductor substrate. Further, in an image pickup element, optical color mixture may be suppressed by providing a groove between pixels of a semiconductor substrate and filling this groove with an insulating film. However, in general, this groove is formed by dry etching and therefore, crystal defects as well as an interface state are easily formed on a surface of the semiconductor substrate due to damage caused by the dry etching. Therefore, although the optical color mixture may be suppressed, the dark current may be easily generated. The dark current generated in the groove may be suppressed by forming the above-described fixed charge film on a wall surface and a bottom surface of the groove. Further, an insulating film producing both a dark-current suppression effect and an antireflection effect may be achieved using, for example, an insulating material having a refractive index of 2 or more as a material of the fixed charge film, and forming a film of this material over the entire back surface including the groove. However, there has been the following issue for the fixed charge film. In general, PVD whose deposition rate is high is selected in view of producibility. However, PVD damages a film formation region, namely, here, the entire back surface of the semiconductor substrate including the groove, thereby degrading interfacial quality. In particular, a dark current is more easily generated at the surface (the wall surface and the bottom surface) of the groove, the surface being damaged by the dry etching used in forming the groove. In contrast, in the image pickup element10and the method of manufacturing the same according to the present embodiment, the fixed charge film23is a laminated film (including the first insulating film23A and the second insulating film23B), and the layers thereof are formed using different methods. Specifically, at first, the first insulating film23A1is formed using ALD or MOCVD on the semiconductor substrate21and then, the second insulating film23B is formed using PVD. Subsequently, the first insulating film23A2is formed using ALD or MOCVD. When the formation of the film (the first insulating film23A1) by ALD or MOCVD is performed before the film formation by PVD as described above, it is possible to prevent damage to the film formation surface by PVD. This is due to properties of the first insulating film23A1formed by ALD or MOCVD. When film formation is performed using ALD or MOCVD, a more minute film with a high degree of crystallization is formed. For this reason, the first insulating film23A1acts as a protective film of the semiconductor substrate21, which reduces damage to the surface of the semiconductor substrate21in forming the second insulating film23B by PVD. Therefore, it is possible to improve the interfacial quality of the light-receiving surface S1. In addition, it is possible to suppress deterioration in unpinning that occurs due to physical damage to the wall surface and the bottom surface of the pixel separation groove21A in forming the pixel separation groove21A or impurity inactivation by ion irradiation. It is to be noted that a lower limit, which is necessary for reduction of damage to the surface of the semiconductor substrate21by PVD, of the film thickness of the first insulating film23A1may be preferably 1 nm or more, and a upper limit may be preferably 25 nm or less in view of a film formation time. In addition, the first insulating films23A1and23A2are formed, using ALD or MOCVD, on the entire surface (the light-receiving surface S1as well as the wall surface and the bottom surface of the pixel separation groove21A) on the light incident surface side of the semiconductor substrate21. Moreover, the second insulating film23B is formed, using PVD, on the light-receiving surface S1and the part of the wall surface, which is contiguous to the light-receiving surface S1, of the pixel separation groove21A by the shadowing effect to be described below. The shadowing effect in the second insulating film23B depends on the depth (h) of the pixel separation groove21A. The deeper the depth (h) is, the greater the shadowing effect is, so that film formation on the wall surface of the pixel separation groove21A is suppressed. The depth (h) allowing suppression of the film formation on the wall surface may be preferably 1 μm or more. When the depth (h) is less than 1 μm, a groove shape may be desirably an overhang type. As described above, in the present embodiment, the fixed charge film23, which is formed on the light-receiving surface side of the semiconductor substrate21including the photoelectric conversion section22, is formed as a laminated film including two kinds of different insulating films (the first insulating film23A and the second insulating film23B) formed in different regions. Specifically, the first insulating film23A is formed on the entire surface (the light-receiving surface S1as well as the wall surface and the bottom surface of the pixel separation groove21A) on the light incident surface side of the semiconductor substrate21by using ALD or MOCVD. Further, the second insulating film23B is formed on the light-receiving surface S1by using PVD. In particular, the second insulating film23B is formed after the first insulating film23A is formed and therefore, it is possible to form a fixed charge film without damaging the surface of the semiconductor substrate21. In other words, it is possible to provide an image pickup device in which the interface state of the surface (the light-receiving surface S1as well as the wall surface and the bottom surface of the pixel separation groove21A) of the semiconductor substrate21is improved and generation of a dark current is suppressed. Further, the lamination order of the first insulating film23A2and the second insulating film23B after the first insulating film23A1is formed on the semiconductor substrate21is not limited in particular. However, it is possible to prevent entrance of impurities such as oxygen and hydrogen into the semiconductor substrate21, by forming the first insulating film23A2after the second insulating film23B is formed as illustrated inFIGS.2A to2C. This makes it possible to further improve the interface state and pinning performance on the light-receiving surface S1. Furthermore, as compared with ALD and MOCVD, PVD provides a high deposition rate and therefore, it is possible to form a film that is thick to some extent in a relatively short time by PVD. Therefore, by forming the second insulating film23B using a material having a relatively high refractive index, antireflection performance of the fixed charge film23for obliquely entering light is improved, which allows suppression of color mixture in the photoelectric conversion section22. It is to be noted that, in the present embodiment, the fixed charge film23is configured such that the first insulating film23A includes two layers and the second insulating film23B includes one layer, but these films may each include two layers, or three more layers. 2. Modification FIG.4illustrates a cross-sectional configuration of an image pickup element (an image pickup element10A) according to a modification of the above-described embodiment. The image pickup element10A is of the backside illumination type and has a structure having the plurality of pixels P two-dimensionally arranged, in a manner similar to that of the above-described embodiment. In the light receiving section20of the image pickup element10A, the pixel separation groove21A is provided between the pixels P of the semiconductor substrate21in a manner similar to that of the above-described embodiment. The fixed charge film23is formed on the light-receiving surface S1of the semiconductor substrate21as well as the wall surface and the bottom surface of the pixel separation groove21A, and the protective film24is formed on the fixed charge film23. In a condensing section50, in a manner similar to that in the above-described embodiment, a flattening film53, a light-shielding film52, and a color filter54are laminated between the light receiving section20and an on-chip lens51. In the image pickup element10A of the present modification, the light-shielding film52is extended inside the pixel separation groove21A, which is different from the above-described embodiment. Except this point, the image pickup element10A has a configuration similar to that of the image pickup element10, and has similar functions and effects as well. In this way, in the present modification, the light-shielding film52is embedded in the pixel separation groove21A of the light receiving section20. Therefore, it is possible to further suppress color mixture due to obliquely entering light in the photoelectric conversion section22. 3. Application Examples FIG.5illustrates an overall configuration of a solid-state image pickup device (the image pickup device1) in which any of the image pickup elements (the image pickup elements10and10A) of the above-described embodiment and modification is used for each pixel. The image pickup device1may be a CMOS image sensor, and includes a pixel section1aserving as an image pickup area, in a central part on the semiconductor substrate21. In a peripheral region of the pixel section1a, for example, a peripheral circuit section130including a row scanning section131, a system control section132, a horizontal selection section133, and a column scanning section134may be provided. The pixel section1amay include, for example, a plurality of unit pixels P (each equivalent to the image pickup element10or10A) two-dimensionally arranged in rows and columns. To the unit pixel P, for example, a pixel driving line Lread (specifically, a row selecting line and a reset control line) may be wired for each pixel row, and the vertical signal line Lsig may be wired for each pixel column. The pixel driving line Lread transmits a drive signal for signal reading from a pixel, and has one end connected to an output terminal of the row scanning section131, the output terminal corresponding to each row. The row scanning section131includes components such as a shift register and an address decoder. The row scanning section131may be, for example, a pixel driving section that drives the pixels P of the pixel section1arow by row. A signal outputted from each of the pixels P in the pixel row selected by the row scanning section131is supplied to the horizontal selection section133through each of the vertical signal lines Lsig. The horizontal selection section133may be configured of, for example, components such as an amplifier and a horizontal selection switch provided for each of the vertical signal lines Lsig. The column scanning section134includes components such as a shift register and an address decoder, and drives the horizontal selection switches of the respective horizontal selection sections133while sequentially scanning these horizontal selection switches. By this selective scanning of the column scanning section134, a signal of each of the pixels P transmitted through each of the vertical signal lines Lsig is sequentially outputted to a horizontal signal line135, and then transmitted to the outside of the semiconductor substrate21through the horizontal signal line135. A circuit portion including the row scanning section131, the horizontal selection section133, the column scanning section134, and the horizontal signal line135may be directly formed on the semiconductor substrate21, or may be disposed in an external control IC. It is possible to provide this circuit portion in other substrate connected by a cable or the like. The system control section132receives a clock provided from outside the semiconductor substrate21as well as data commanding an operation mode, and outputs inside information of the image pickup device1. In addition, the system control section132may include, for example, a timing generator that generates various timing signals. The system control section132may control driving of the peripheral circuits such as the row scanning section131, the horizontal selection section133, and the column scanning section134, based on the various timing signals generated by the timing generator. The image pickup device1as described above is applicable to all types of electronic apparatuses having an image pickup function. Examples of the electronic apparatuses may include camera systems such as digital still cameras and video cameras, as well as mobile phones. As an example,FIG.6illustrates a schematic configuration of a camera (an electronic apparatus2). The electronic apparatus2may be, for example, a video camera capable of shooting a still image or a moving image. The electronic apparatus2may include an image pickup device (the image pickup device1), an optical system (an optical lens)310, a shutter unit311, a signal processing section312, and a drive section313. The optical system310guides image light (incident light) from a subject to the pixel section1aof the image pickup device1. The optical system310may include a plurality of optical lenses. The shutter unit311controls an optical irradiation period and a shielding period for the image pickup device1. The drive section313controls shutter operation of the shutter unit311and transfer operation of the image pickup device1. The signal processing section312performs various kinds of signal processing on a signal outputted from the image pickup device1. For example, an image signal Dout after the signal processing may be stored in a storage medium such as a memory, or outputted to a unit such as a monitor. Further, in the above-described embodiment and the like, the configurations of the image pickup element10and10A of the backside illumination type have been each taken as an example. However, the present technology is applicable to a front illumination type. Furthermore, an inner lens (not illustrated) may be disposed between the light receiving section20and the color filter44(or54) of the condensing section40(or50). Still furthermore, it is not necessary to provide all the components of the above-described embodiment and the like, and other component may be provided. It is possible to achieve at least the following configurations from the above-described example embodiments of the disclosure.(1) An image pickup element including:a semiconductor substrate including a photoelectric conversion section for each pixel;a pixel separation groove provided in the semiconductor substrate; anda fixed charge film provided on a light-receiving surface side of the semiconductor substrate,wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least a portion of the light-receiving surface.(2) The image pickup element according to (1), wherein the first insulating film and the second insulating film are different in number of layers.(3) The image pickup element according to (1), wherein, in the fixed charge film, the first insulating film, the second insulating film, and the first insulating film are formed in order from the semiconductor substrate side.(4) The image pickup element according to (1), wherein, in the fixed charge film, the first insulating film, the first insulating film, and the second insulating film are formed in order from the semiconductor substrate side.(5) The image pickup element according to (1), wherein the second insulating film is contiguous from the light-receiving surface to a part of the wall surface of the pixel separation groove.(6) The image pickup element according to (1), wherein the first insulating film and the second insulating film are each formed of any one of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and tantalum oxide (Ta2O5).(7) The image pickup element according to (1), wherein the first insulating and the second insulating film are made of a same material.(8) The image pickup element according to (7), wherein the material is any one of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and tantalum oxide (Ta2O5).(9) The image pickup element according to (8), wherein the material includes silicon.(10) The image pickup element according to (1), further comprising a protective film in the pixel separation groove.(11) The image pickup element according to (10), wherein the protective film is any one of silicon nitride (Si2N3), silicon oxide (SiO2) and silicon oxynitride (SiON).(12) A method of manufacturing an image pickup element, the method includingforming a fixed charge film on a light-receiving surface of a semiconductor substrate that includes a photoelectric conversion section for each pixel and has a pixel separation groove,wherein the forming of the fixed charge film includesforming a first insulating film to be provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, andforming a second insulating film to be provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.(13) The method according to (12), wherein the first insulating film is formed by atomic layer deposition or metal organic chemical vapor deposition.(14) The method according to (12), wherein the second insulating film is formed by physical vapor deposition.(15) An electronic apparatus provided with an image pickup element, the image pickup element including:a semiconductor substrate including a photoelectric conversion section for each pixel;a pixel separation groove provided in the semiconductor substrate; anda fixed charge film provided on a light-receiving surface side of the semiconductor substrate,wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof | 39,606 |
11862653 | DETAILED DESCRIPTION The detailed description set forth below, in connection with the appended drawings, is intended as a description of example embodiments of the present disclosure and is not intended to represent the only forms in which the present disclosure may be embodied. The description sets forth aspects and features of the present disclosure in connection with the illustrated example embodiments. It is to be understood, however, that the same or equivalent aspects and features may be accomplished by different embodiments, and such other embodiments are encompassed within the spirit and scope of the present disclosure. As noted elsewhere herein, like reference numerals in the description and the drawings are intended to indicate like elements. Further, descriptions of features, configurations, and/or other aspects within each embodiment should typically be considered as available for other similar features, configurations, and/or aspects in other embodiments. FIG.1shows a cross-sectional view of an imaging sensor package100according to an embodiment of the present disclosure. InFIG.1, the imaging sensor package100is shown in a flat state for convenience of description. It is to be understood that the imaging sensor package100may be curved in one or more directions (e.g., along one or more axes). Depending on the needs and design of a particular imaging system, the imaging sensor package100may be curved to have a spherical, aspherical, cylindrical, parabolic, or any suitable non-planar surface or shape. In one embodiment, the imaging sensor package100may be curved to have a spherical curvature (e.g., may be curved along two in-plane axes) (see, e.g.,FIGS.5A and5B). Referring toFIG.1, the imaging sensor package100includes an imaging sensor10coupled to an architected substrate (e.g., a patterned substrate)20. Together, the imaging sensor10and architected substrate20may be referred to as the sensor-substrate laminate or simply as the imaging sensor package100. The imaging sensor10may include a readout integrated circuit11, a detector12on the readout integrated circuit11, and an antireflective coating13on the detector12. The architected substrate20is arranged below (e.g., is coupled to a bottom surface of) the readout integrated circuit11. In some embodiments, the imaging sensor10may be formed (e.g., separately formed) and then coupled to the architected substrate20. But in other embodiments, a complete (e.g., unpatterned) substrate may be coupled to the imaging sensor10and then patterned to form the architected substrate20. The detector12may include a plurality of light sensing elements, and the readout integrated circuit11may act as a substrate for the light sensing elements. The imaging sensor10may be sensitive to (e.g., may receive and interpret) different wavelength ranges of light based on the composition of the detector12. For example, the detector12may be sensitive to visible or infrared (IR) light, and the infrared light may be near infrared radiation (NIR), short-wave infrared radiation (SWIR), medium-wave infrared radiation (MWIR), and/or long-wave infrared radiation (LWIR). Infrared sensing detectors (e.g., infrared sensing elements) may include a Type II strained layer superlattice (SLS) (e.g., InSb, InAs/InAsSb), a III-V bulk alloy, a photovoltaic material (e.g., mercury cadmium telluride, InSb, PbSnTe, PtSi), a photoconductive material (e.g., mercury cadmium telluride, InSb, InGaAs/InP, Ge, doped silicon), and/or a microbolometer (e.g., vanadium oxide or amorphous silicon). Visible light detectors (e.g., visible light sensing elements) may include a charge-coupled device (CCD) and/or a complementary-metal-oxide semiconductor (CMOS). The light sensing elements of the detector12may be spaced from each other by a distance (e.g., may have a pitch) in a range from about 1 μm to about 40 μm and may be coupled to (e.g., may be formed on) the readout integrated circuit11. The readout integrated circuit11may include a substrate formed or (or including) silicon, germanium, and/or other suitable semiconductor materials and may further include oxide layers and metal lines to act as the readout integrated circuit11. FIGS.4A and4Bshow finite element analyses of an imaging sensor10without the architected substrate20curved in two directions (e.g., spherically curved).FIG.4Ashows physical deformation of the imaging sensor10, andFIG.4Bshows stress distribution in the imaging sensor10. As can be seen inFIG.4A, when the imaging sensor10without the architected substrate20is curved, it undergoes uncontrolled wrinkling primarily concentrated at edge centers, and as can be seen inFIG.4B, the imaging sensor10without the architected substrate20experiences relatively high local compressive and tensile stresses. FIGS.5A and5Bshow finite element analyses of different embodiments of the imaging sensor package, which includes the imaging sensor10and different embodiments of the architected substrate20, that is curved in two directions (e.g., that is spherically curved).FIGS.5A and5Bcorrespond toFIG.4B(e.g., show stress distributions) but include the architected substrates. FIG.5Ashows the stress distributions in the image sensor package200that includes an island-type (e.g., square pattern) architected substrate20, which is described below in more detail.FIG.5Bshows the stress distributions in the image sensor package300that includes a radially-patterned architected substrate20, which is also described below in more detail. As can be seen inFIGS.5A and5B, by coupling the architected substrate20to the bottom surface of the imaging sensor10, the stress is less concentrated in the imaging sensor10(e.g., the stress is more evenly distributed across the imaging sensor10), which also reduces uncontrolled wrinkling or buckling by inducing controlled, low-amplitude wrinkling in the imaging sensor10, discussed further below. The low-amplitude wrinkling may be considered as local deviations from the ideal curved surface. That is, the imaging sensors10in the imaging sensor packages200and300, shown inFIGS.5A and5B, respectively, experience low-amplitude wrinkling.FIG.2is a schematic cross-section illustration of the imaging sensor package100that shows the low-amplitude wrinkling of the imaging sensor10in an exaggerated manner for convenience of description. FIG.6is a graph showing differences in maximum in-plane stress of an imaging sensor as a function of distance from a center point thereof. The solid line refers to the imaging sensor10without an architected substrate (see, e.g.,FIGS.4A and4B), and the dotted line refers to the curved sensor package300with the radially-patterned architected substrate (see, e.g.,FIG.5B). As can be seen, the in-plane stress is much more evenly distributed throughout the imaging sensor package300that includes the architected substrate than in the imaging sensor10without the architected substrate. Hereinafter, aspects of embodiments of the architected substrate20will be described in more detail. The architected substrate20reduces the total strain energy in the imaging sensor10by alleviating compressive strain through the low-amplitude wrinkling as schematically shown inFIG.2. The architected substrate20may be designed such that the low-amplitude wrinkling of the imaging sensor10does not affect or substantially affect the imaging quality of the imaging sensor10. For example, the architected substrate20may be designed such that the wavelength of the wrinkling (e.g., the distance between wrinkling peaks) is smaller than the size of one light detecting element (e.g., one pixel); thus, many or all pixels in the imaging sensor10are subject to at least one and possibly more than one wrinkle, resulting in substantially consistent impact on light collection efficiency of the light detecting elements and little overall effect on image output. On the other hand, uncontrolled wrinkling, such as may be experience by curved imaging sensors without the architected substrate20(see, e.g.,FIGS.4A and4B) affects pixels differently (e.g., some pixels may be subjected to greater wrinkling than other pixels), causing some pixels to suffer highly degraded light collection efficiency and variant focal lengths compared to other pixels in the same imaging sensor, resulting is a distorted output image. Further, the amplitude of the low-amplitude wrinkling may also be smaller than the pixel size while the wavelength expands beyond the size of the pixel, which improves consistency and output image quality over uncontrolled wrinkling. For example, the amplitude may be less than twice the width of one pixel or may be less than one-quarter the width of one pixel. In some embodiments, the average deviation of the pixel normal from ideal is less than about 45 degrees and may be less than about 10 degrees. The architected substrate20has non-uniform patterning, such as non-uniform thickness and/or material composition, which create stiffness variations or discontinuities in the architected substrate20. These stiffness discontinuities (e.g., areas of relatively high and relatively low stiffness) impart the low-amplitude wrinkling to the imaging sensor10as it is curved (e.g., as it is curved in a mold). The architected substrate20retains (or substantially retains) its volume throughout the curving process. The architected substrate20may have a size that is longer in two directions (referred to as in-plane directions) than in a third direction (referred to as an out-of-plane direction). In some embodiments, the in-plane directions may be a length direction and a width direction of the architected substrate20, and the out-of-plane direction may be a thickness direction of the architected substrate20. The architected substrate20may be larger (e.g., may have a larger surface area or volume) or smaller than the imaging sensor10. For example, the in-plane size (e.g., the surface area) of the architected substrate20may be in a range from about 40% to about 200% of the in-plane size (e.g., the surface area) of the imaging sensor10. In one embodiment, the in-plane size of the architected substrate20and the imaging sensor10may be the same or substantially the same. The architected substrate20may have an outer profile having a square, rectangular, circular, elliptical, or arbitrary shape. In one embodiment, the outer profile (e.g., the outer peripheral shape) of the architected substrate20and the imaging sensor10may be the same or substantially the same. The architected substrate20may have a thickness (e.g., an out-of-plane substrate thickness) in a range between about 1 μm and about 400 μm. In some embodiments, the architected substrate20may have a thickness in a range from about 0.5 μm to about 5 μm or between about 15 μm and about 100 μm. When viewed from the perspective of the ratio of the length of the imaging sensor10to the greatest thickness of the imaging sensor package100, the ratio will be between about 20 and about 500. In some embodiments, the ratio will be between about 20 and about 50 to provides regions with larger wrinkling resistance. In other embodiments the ratio may be between about 200 to about 400 to lower the stored elastic energy in the imaging sensor package100. The thickness of the architected substrate depends upon effective mechanical properties of the substrate and imaging sensor10, thickness of the imaging sensor10, pixel size, and the radii of curvature to which the imaging sensor package100is curved. The thickness of the architected substrate20may vary along the length and/or width directions (e.g., may vary along the in-plane position) thereof to create the stiffness discontinuities therein. In some embodiments, the architected substrate20may be non-continuous (e.g., the thickness may be zero in some areas). In some embodiments, such discontinuities may be provided such that an island-type architected substrate20including a plurality of separate pieces is provided, and the separate pieces may be individually coupled to the imaging sensor10and not directly coupled to each other. For example, the architected substrate20shown inFIGS.1and2may be an island-type architected substrate20including a plurality of separate pieces20.1Similarly, the architected substrate shown inFIG.5Ais also an island-type architected substrate. As another embodiment, the architected substrate shown inFIG.5Bhas discontinuities (e.g., areas of zero thickness) is a single component as all of the radial fingers of the architected substrate meet at the center thereof. For ease of description, the island-type architected substrate20may be considered as a single component with 0 thickness in some areas. That is, the thickness of the architected substrate20may vary between full thickness (100%) and no material present, or discontinuous, (0%) along in-plane positions thereon. At areas other than any discontinuous area, the thickness may not be less than 5% the full thickness to reduce risk of breakage or the like. Further, the thickness of the architected substrate20may vary continuously (e.g., the thickness transitions may be smooth or relatedly smooth) or discretely (e.g., step differences may be present between different thickness portions). By varying the thickness of the architected substrate20along the in-plane position, the imaging sensor10is allowed to deviate from an ideal surface when it is curved (e.g., the imaging sensor10may wrinkle or buckle) in a controlled manner to mitigate any stress concentrations in the imaging sensor10during curving (or bending), thereby allowing tighter radii of curvature with lower risk of breakage and little, if any, degradation of the imaging performance. As can be seen inFIG.2, for example, the imaging sensor10wrinkles at the lower stiffness portions (e.g., the discontinuous portions) of the architected substrate20. In this manner, the wrinkling of the imaging sensor10may be controlled by designing the thickness variations in the architected substrate20. In some embodiments, the architected substrate20may have local variations in density in the out-of-plane direction (e.g., in the thickness direction). For example, in some embodiments, the architected substrate may include (or may be formed of) sandwich panels with a core (e.g., a prismatic, lattice, or stochastic core) between the sandwich panels. Referring toFIG.3A, the architected substrate21includes sandwich panels21.1,21.3with core members21.2extending between the sandwich panels21.1,21.3with an opening21.4in the architected substrate21to form a prismatic architected substrate21. While only one opening21.4in the architected substrate21is shown, the present disclosure is not limited thereto, and the architected substrate21may include additional openings therein. The architected substrate21has a discontinuous area (e.g., the opening21.4), which provides a local reduction in stiffness of the architected substrate21, but in other embodiments, the core members21.2may be various arranged to vary the stiffness of the architected substrate21along the in-plane position. For example, the core members21.2may be spaced farther apart from each other in some areas of the architected substrate21than in other areas thereof to create the stiffness discontinuities. In other embodiments, the outermost sandwich panel21.1and the core members21.2may be removed in one area, leaving only the innermost sandwich panel21.3, thereby also creating a local area of reduced stiffness. Referring toFIG.3B, the architected substrate22includes a stochastic core22.2between sandwich panels22.1,22.3, with an opening22.4therein. Referring toFIG.3C, the architected substrate23has core members23.2with openings23.4in only the outermost sandwich panel23.1, forming a T-shaped architected substrate23. For example, the innermost sandwich panel23.3may extend along the entire imaging sensor10and openings23.4may only be in the outermost sandwich panel23.1, but this is merely an example. In some embodiments, the core (or core member) of the architected substrate20may be a microtruss, as provided, for example, in U.S. Pat. Nos. 7,653,279, and 7,382,959, the entire content of each of which is incorporated herein by reference. The architected substrate20may include (or may be formed of) a stiff, ductile material having a modulus that is greater than about 2 GPa and, in some embodiments, is greater than about 70 GPa. The architected substrate20may have a strain to failure of about 0.5% or greater and, in some embodiments, may have a strain to failure of greater than about 5%. The coefficient of thermal expansion (CTE) of the architected substrate20may be between about 0 and about 15 ppm/K and, in some embodiments, may be between about 1 ppm/K and about 8 ppm/K. The architected substrate20may include (or may be formed of) metals and metal alloys, including but not limited to, aluminum, copper, nickel, iron, invar, titanium, molybdenum, steel, tungsten, and/or bismuth. In some embodiments, the architected substrate20may include (or may be formed of) a polymer. In some embodiments, and as another way of forming local stiffness variations, the architected substrate20may include a plurality of different materials, and the material composition may vary throughout the architected substrate20. For example, the material composition of the architected substrate20may be a function of in-plane position, out-of-plane position, or both, and the change in material or composition may be discrete or continuous (e.g., the materials may be mixed together and/or partially mixed together at areas of the architected substrate20). The thickness, material, and compositional changes described above may or may not follow a pattern. In some embodiments, the imaging sensor10and the architected substrate20may be separately formed and then coupled to each other prior to being curved. When the architected substrate20has discontinuous portions (e.g., is an island-type architected substrate), it may be considered that a plurality of architected substrates are coupled to the imaging sensor. Similarly, when the architected substrate20has material variations in the out-of-plane direction (e.g., the thickness direction), it may be considered that a plurality of architected substrates are coupled to the imaging sensor10in the form of layers. For convenience of description, even embodiments including a plurality of architected substrates20, the overall architected substrate20will be referred to in the singular form. The architected substrate20may be coupled to the imaging sensor10(e.g., to a bottom surface of the readout integrated circuit11) by bonding (e.g., a fuse or welding operation), adhering (e.g., using a thermosetting polymer, such as an epoxy or pressure sensitive adhesive), depositing (e.g., electroplating, electroless plating, plasma spray, chemical vapor deposition (CVD), electron-beam CVD, sputter coating, etc.), or attaching (e.g., spin-coating of a polymer followed by UV or thermal cure). The architected substrate20and the imaging sensor10may be coupled to each other either when the imaging sensor10is at the wafer level (e.g., when a plurality of imaging sensors10are joined together on a single wafer) or after singulation of the individual imaging sensors10. An interfacial layer may be coupled to the architected substrate20before coupling it to the imaging sensor10to promote coupling therebetween. In some embodiments, a primer layer and/or a seed layer may also be formed on the architected substrate20. Further, in some embodiments, an interfacial layer may be coupled to the imaging sensor10before coupling it with the architected substrate20to promote coupling therebetween. In some embodiments, a primer layer and/or a seed layer may also be formed on the imaging sensor10(e.g., on the bottom surface of the readout integrated circuit11). In some embodiments, an upper substrate may be coupled to the upper (imaging) surface of the imaging sensor10over the antireflective coating13. The upper substrate may be transparent to the light spectrum of interest to the imaging sensor10and may be epitaxially matched to the detector12and/or to the substrate of the readout integrated circuit11. For example, the upper substrate may be formed of (or may include) GaAs and/or GaSb. In some embodiments, the upper substrate may correct for a CTE mismatch between the layers of the imaging sensor10and, in such embodiments, may include (or may be formed of) Si. The device(s) of the imaging sensor and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of the device may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of the device may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of the device may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the exemplary embodiments of the present disclosure. It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers, levels, and/or sections, these elements, components, regions, layers, levels, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, level, or section from another element, component, region, layer, level, or section. Thus, a first element, component, region, layer, level, or section discussed below could be termed a second element, component, region, layer, level, or section, without departing from the spirit and scope of the inventive concept. Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, the term “major component” means a component constituting at least half, by weight, of a composition, and the term “major portion”, when applied to a plurality of items, means at least half of the items. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the present disclosure”. Also, the terms “exemplary” and “example” are intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present. Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Although example embodiments of a curved imaging sensor package with an architected substrate have been described and illustrated herein, many modifications and variations within those embodiments will be apparent to those skilled in the art. Accordingly, it is to be understood that a curved imaging sensor package with an architected substrate according to the present disclosure may be embodied in forms other than as described herein without departing from the spirit and scope of the present disclosure. The present disclosure is defined by the following claims and equivalents thereof. | 27,717 |
11862654 | DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some image sensors comprise an array of pixels and an inter-pixel trench isolation structure. The array is on a substrate, and the pixels comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure extends into the substrate and individually surrounds the photodetectors along boundaries of the pixels to separate the photodetectors from each other. Often, the inter-pixel trench isolation structure is a dielectric material with a refractive index less than that of the substrate to promote total internal reflection (TIR) at sidewall interfaces at which the inter-pixel trench isolation structure and the substrate directly contact. For example, the inter-pixel trench isolation structure may be silicon dioxide, whereas the substrate may be silicon. Other suitable materials are, however, amenable. TIR at the sidewall interfaces reflects incident radiation that would otherwise pass between the photodetectors. Hence, the inter-pixel trench isolation structure may reduce crosstalk and may improve performance of the photodetectors by TIR. Further, TIR at the sidewall interfaces may reflect incident radiation back towards photodetectors at which the radiation was received. Hence, the inter-pixel trench isolation structure may provide the photodetectors additional opportunities for absorption of the radiation and may further improve performance of the photodetectors. However, TIR depends upon radiation impinging on the sidewall interfaces at angles greater than the so-called critical angle. For example, the critical angle may be about 20 degrees when the inter-pixel trench isolation structure and the substrate are respectively silicon dioxide and silicon. Hence, radiation imping on the sidewall interfaces at angles less than the critical angle may pass between the photodetectors and increase crosstalk. Some photodetectors operate in a reverse biased state with a high bias voltage and hence have a strong electric field across corresponding depletion regions. Such photodetectors may, for example, include avalanche photodiodes (APDs), single-photon avalanche diodes (SPADs), and other suitable types of photodetectors. Because of the strong electric field, hot-carrier luminescence may occur. Hot-carrier luminescence is non-directional and emits radiation in any direction. As a result, radiation from hot-carrier luminescence may impinge on the sidewall interfaces at angles less than the critical angle and may hence pass between photodetectors. This may increase crosstalk and may hence degrade performance of the photodetectors. Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined wholly or partially by a low-transmission layer. In some embodiments, an image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate and, as noted above, is defined wholly or partially by the low-transmission layer. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The low-transmission layer has low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation. Further, the low-transmission layer has low transmission due to intrinsic properties of material making up the low-transmission layer and does not depend upon TR for low transmission. Hence, the low-transmission layer blocks radiation regardless of the angle of incidence. The low-transmission layer may, for example, be or comprise metal, a conductive ceramic, some other suitable material(s), or any combination of the foregoing. Because the inter-pixel trench isolation structure individually surrounds the photodetectors to separate the photodetectors from each other, the inter-pixel trench isolation structure receives radiation traveling between photodetectors. Because the inter-pixel trench isolation structure has low transmission, the inter-pixel trench isolation structure blocks the radiation from traveling between the photodetectors and hence reduces crosstalk. The reduced crosstalk, in turn, increases signal-to-noise ratios (SNRs) of the photodetectors and other suitable performance metrics of the photodetectors. Because the low-transmission layer has low transmission due to intrinsic properties of the material making up the low-transmission layer and does not depend upon TIR, the low-transmission layer is able to efficiency block radiation from hot carrier luminescence regardless of angle of incidence. With reference toFIG.1, a cross-sectional view100of some embodiments of an image sensor is provided in which an inter-pixel trench isolation structure102is defined in part by a low-transmission layer104and separates a pixel106from neighboring pixels (not shown) in a substrate108. The substrate108accommodates a photodetector110individual to the pixel106and is a semiconductor. The substrate108may, for example, be or comprise monocrystalline silicon and/or some other suitable semiconductor material(s). The inter-pixel trench isolation structure102extends into a back side108bof the substrate108at a boundary of the pixel106. Further, the inter-pixel trench isolation structure102comprises a pair of inter-pixel isolation segments respectively on opposite sides of the pixel106. In some embodiments, the inter-pixel trench isolation structure102extends in a closed path along the boundary of the pixel106when viewed top down. In some embodiments, the inter-pixel trench isolation structure102is also known as an outer trench isolation structure. The low-transmission layer104is separated from the substrate108by a dielectric liner layer112and, in some embodiments, defines a bulk of the inter-pixel trench isolation structure102. The dielectric liner layer112further defines the inter-pixel trench isolation structure102and electrically isolates the low-transmission layer104from the substrate108. The dielectric liner layer112may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). The low-transmission layer104has a low transmission for radiation114, such that the inter-pixel trench isolation structure102also has a low transmission for radiation114. Because of the low transmission, the inter-pixel trench isolation structure102blocks radiation114passing from the pixel106to the neighboring pixels, or vice versa, and hence reduces crosstalk between the pixel106and the neighboring pixels. By reducing crosstalk, SNR and other suitable performance metrics of the photodetector110may be enhanced. Because the low transmission layer104blocks radiation114from passing between pixels, the low-transmission layer104may also be known as an optical barrier layer. In some embodiments, the low transmission is transmission less than about 1%, 5%, 10%, or some other suitable percentage of radiation114. In some embodiments, the low-transmission layer104is opaque to radiation114. In some embodiments, the low transmission is low compared to that of the dielectric liner layer112and/or that of silicon oxide. If transmission is too high (e.g., greater than about 10% or some other suitable percentage), crosstalk may be high and performance of the photodetector110may be low. The low-transmission layer104further has a high reflectance for radiation114, such that the inter-pixel trench isolation structure102has a high reflectance for radiation114. Because of the high reflectance, the inter-pixel trench isolation structure102may reflect radiation114back towards the photodetector110. This provides the photodetector110with another opportunity to absorb the radiation114, which improves quantum efficiency (QE), SNR, and other suitable performance metrics of the photodetector110. The high reflectance may, for example, be reflectance greater than about 80%, 90%, 95%, or some other suitable percentage of radiation114. If reflectance is too low (e.g., less than about 80% or some other suitable percentage), QE, SNR, and other suitable performance metrics of the photodetector110may be low. The low transmission of the low-transmission layer104and the high reflectance of the low-transmission layer104are due to intrinsic properties of material making up the low-transmission layer104and do not depend upon TIR. In some embodiments, the low-transmission layer104is metal and/or some other suitable conductive material(s). The metal may, for example, be or include copper, aluminum, silver, some other suitable metal(s), or any combination of the foregoing. In alternative embodiments, the low-transmission layer104is a dielectric and/or some other suitable material(s). In at least some embodiments in which the low-transmission layer104is dielectric, the dielectric liner layer112may be omitted. In some embodiments, the photodetector110operates in a reverse biased state at a high voltage. For example, the photodetector110may be an APD, a SPAD, or some other suitable type of photodetector. The high voltage may, for example, be a voltage greater than about 100 volts, 200 volts, 1000 volts, 1500 volts, or some other suitable value. Further, the high voltage may, for example, be a voltage of about 100-200 volts, about 200-1000 volts, about 1000-1500 volts, about 1500-2000 volts, or some other suitable value. Because the photodetector110may operate at the high voltage, the photodetector110may be prone to hot carrier luminescence116(schematically illustrated by a star). Hot carrier luminescence116may emit hot carrier radiation114hcin any direction, which makes it difficult to efficiently block the hot carrier radiation114hcby TIR. As noted above, TIR depends upon the angle of incidence exceeding a so-called critical angle. In some embodiments, the hot carrier radiation114hchas a wavelength of about 900-1000 nanometers, about 900-950 nanometers, about 950-1000 nanometers, or some other suitable wavelength. Because the inter-pixel trench isolation structure102has the low transmission and does not depend upon TIR for the low transmission, the inter-pixel trench isolation structure102may block the hot carrier radiation114hcregardless of the angle of incidence. As a result, the inter-pixel trench isolation structure102may efficiently reduce crosstalk from hot carrier luminescence116. Further, because the inter-pixel trench isolation structure102has the high reflectance and does not depend upon TIR for the high reflectance, the inter-pixel trench isolation structure102may reflect the hot carrier radiation114hcregardless of angle of incidence. In some embodiments, the dielectric liner layer112has a high transmission. The high transmission may, for example, be transmission greater than 90%, 95%, 99%, or some other suitable percentage of incident radiation. In some embodiments, the dielectric liner layer112is transparent to radiation114. If transmission is too low (e.g., less than about 90% or some other suitable percentage), the dielectric liner layer112may prevent too much radiation114from impinging on the low-transmission layer104and being reflected. As a result, QE and other suitable performance metrics of the photodetector110may be low. In some embodiments, a thickness Tdllof the dielectric liner layer112is small so the dielectric liner layer112has the high transmission. The thickness Tdllmay, for example, be small when less than about 100 nanometers, about 50 nanometers, about 10 nanometers, or some other suitable value. Further, the thickness Tdllmay, for example, be small when about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, about 20 nanometers, or some other suitable value. If the thickness Tdllis too large (e.g., greater than about 100 nanometers or some other suitable value), the dielectric liner layer112may prevent too much radiation114from impinging on the low-transmission layer104. If the thickness Tdllis too small (e.g., less than about 10 nanometers or some other suitable value), the dielectric liner layer112may fail to provide electrical isolation between the low-transmission layer104and the substrate108. In some embodiments, the dielectric liner layer112has a higher refractive index than the substrate108. This may promote TIR at sidewall interfaces at which the dielectric liner layer112and the substrate108directly contact. However, TIR may be redundant because the low-transmission layer108has the high reflectance. In some embodiments, the dielectric liner layer112further serves as a diffusion barrier for material of the low-transmission layer104to prevent diffusion into the substrate108. For example, the low-transmission layer104may be or comprise copper and the dielectric liner layer112may be or comprise aluminum oxide (e.g., Al2O3) or some other suitable material. Depending upon the material of the low-transmission layer104, the material may shift operating parameters of the photodetector110out of specification if allowed to diffuse to the substrate108. With continued reference toFIG.1, a front side dielectric structure118underlies the substrate108and covers a front side108fof the substrate108. The front side dielectric layer118has a higher refractive index than the substrate108at the front side108fof the substrate108to promote TIR at the front side108f. As a result, radiation114that passes through the photodetector110may be reflected back to the photodetector110, thereby giving the photodetector110another opportunity to absorb the radiation114. This may, in turn, improve QE and other suitable performance metrics of the photodetector110. The front side dielectric structure118may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). As seen hereafter, the front side dielectric structure118may wholly or partially accommodate an interconnect structure (not shown) in some embodiments. The interconnect structure comprises a plurality of wires, a plurality of vias, and a plurality of contacts that are alternatingly stacked and define conductive paths leading from the photodetector110. The conductive paths may, for example, electrically coupling the photodetector110to readout circuitry and/or other suitable imaging circuitry. A back side dielectric structure120covers the back side108bof the substrate108and defines a diffuser122with the substrate108. The diffuser122overlies the photodetector110and has a periodic pattern at the back side108bof the substrate108. The periodic pattern of the diffuser122serves to scatter external radiation114exreceived at the back side108bof the substrate108. For example, the diffuser122may scatter external radiation114exto increase an angle of incidence of the external radiation114exat the front side108fof the substrate108to increase TIR at the front side108f. This may, in turn, further improve QE and other suitable performance metrics of the photodetector110. The back side dielectric structure120may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). In some embodiments, the back side dielectric structure120is the same material as the dielectric liner layer112and/or is integrated with the dielectric liner layer112. Further, in some embodiments, the back side dielectric layer120has a higher refractive index than the substrate108at the back side108bof the substrate108to promote TIR at the back side108b. As a result, radiation114may be reflected back to the photodetector110by TIR, thereby giving the photodetector110another opportunity to absorb the radiation114. This may, in turn, improve QE and other suitable performance metrics of the photodetector110. A spacer layer124overlies the back side dielectric structure120, and a micro lens126overlies the spacer layer124. In alternative embodiments, the spacer layer124is replaced with a color filter. The spacer layer124spaces the micro lens126from the photodetector110and may, for example, be or comprise silicon oxide and/or some other suitable dielectrics. The micro lens126focuses external radiation114exon the photodetector110. With reference toFIG.2, a top layout view200of some embodiments of the image sensor ofFIG.1is provided.FIG.2may, for example, be taken along line A-A′ inFIG.1and/orFIG.1may, for example, be taken along line A-A′ inFIG.2. The dielectric liner layer112and the low-transmission layer104each extend along the boundary of the pixel in closed paths to surround the photodetector110. The low-transmission layer104has low transmission so as to reduce crosstalk. Further, the low-transmission layer104has high reflectance so as to reflect radiation114back to the photodetector110. The reduced crosstalk increases SNR and other suitable performance metrics of the photodetector110, whereas the high reflectance increases QE and other suitable performance metrics of the photodetector110. With reference toFIG.3A, a cross-sectional view300A of some alternative embodiments of the image sensor ofFIG.1is provided in which the inter-pixel trench isolation structure102is further defined by a barrier layer302. The barrier layer302is a different material than the dielectric liner layer112and is a diffusion barrier for material of the low-transmission layer104to prevent the material from diffusing into the substrate108. For example, the low-transmission layer104may be or comprise copper, the barrier layer302may be or comprise aluminum oxide (e.g., Al2O3), and the dielectric liner layer112may be or comprise silicon oxide. Other suitable materials are, however, amenable. Depending upon the material of the low-transmission layer104, the material may shift operating parameters of the photodetector110out of specification and/or degrade performance of the photodetector110if allowed to diffuse. In some embodiments, the barrier layer302is dielectric and hence provides additional electrical isolation between the low-transmission layer104and the substrate108. In alternative embodiments, the barrier layer302is conductive. In some embodiments, the barrier layer302has a high transmission. The high transmission may, for example, be transmission greater than 90%, 95%, 99%, or some other suitable percentage of radiation114. In some embodiments, the barrier layer302is transparent to radiation114. If transmission is too low (e.g., less than about 90% or some other suitable percentage), the barrier layer302may prevent too much radiation114from impinging on the low-transmission layer104and being reflected. As a result, QE and other suitable performance metrics of the photodetector110may be low. In some embodiments, a thickness Tblof the barrier layer302is small so the barrier layer302has the high transmission. The thickness Tblmay, for example, be small when less than about 100 nanometers, about 50 nanometers, about 10 nanometers, or some other suitable value. Further, the thickness Tblmay, for example, be small when about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, about 20 nanometers, or some other suitable value. If the thickness Tblis too large (e.g., greater than about 100 nanometers or some other suitable value), the thickness Tblmay prevent too much radiation114from impinging on the low-transmission layer104and being reflected by the low-transmission layer104. If the thickness Tblis too small (e.g., less than about 10 nanometers or some other suitable value), the barrier layer302may fail to serve as a diffusion barrier for material of the low-transmission layer104. With reference toFIG.3B, a cross-sectional view300B of some alternative embodiments of the image sensor ofFIG.1is provided in which an additional inter-pixel trench isolation structure304separates the pixel106from neighboring pixels (not shown). The additional inter-pixel trench isolation structure304extends into the front side108fof the substrate108at the boundary of the pixel106and directly contacts the inter-pixel trench isolation structure102within the substrate108. Further, the additional inter-pixel trench isolation structure304comprises a pair of additional inter-pixel isolation segments respectively on opposite sides of the pixel106. In some embodiments, the additional inter-pixel trench isolation structure304extends in a closed path along the boundary of the pixel106when viewed top down. The additional inter-pixel trench isolation structure304comprises a dielectric material having a higher refractive index than the substrate108so as to promote TIR at sidewall interfaces at which the additional inter-pixel trench isolation structure304and the substrate108directly contact. By promoting TIR at the sidewall interfaces, radiation114may be reflected back towards the photodetector110to reduce crosstalk and improve QE, SNR, and other suitable performance metrics. The additional inter-pixel trench isolation structure304may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). Because the additional inter-pixel trench isolation structure304and the inter-pixel trench isolation structure102extend into opposite sides of the substrate108and directly contact within the substrate108, the additional inter-pixel trench isolation structure304define a composite structure extending through the substrate108. The composite structure may provide enhanced inter-pixel isolation and crosstalk reduction when a thickness Tsof the substrate108is too great for the additional inter-pixel trench isolation structure304and the inter-pixel trench isolation structure102to individually extend through the substrate108. With reference toFIGS.4A and4B, cross-sectional views400A,400B of some alternative embodiments of the image sensor ofFIG.1are provided in which constituents of the image sensor are varied. InFIG.4A, the inter-pixel trench isolation structure102extends partially through the substrate108from the front side108fof the substrate108. In alternative embodiments, the inter-pixel trench isolation structure102extends fully through the substrate108. InFIG.4B, a top surface of the low-transmission layer104is about even with that of the substrate108. With reference toFIGS.5A and5B, cross-sectional views500A and500B of some alternative embodiments of the image sensor ofFIG.1are provided in which constituents of the image sensor are omitted. InFIG.5A, the diffuser122is omitted. As such, an interface between the substrate108and the back side dielectric structure120is flat from a first side of the pixel106to a second side of the pixel106opposite the first side. InFIG.5B, the dielectric liner layer112is omitted. The dielectric liner layer112may, for example, be omitted at least when the low-transmission layer104is a dielectric having low transmission. WhileFIG.2is described with regard toFIG.1, it is to be appreciated thatFIG.2is applicable to any ofFIGS.3A,3B,4A,4B, and5in alternative embodiments. Hence, any ofFIGS.3A,3B,4A,4B, and5may be taken along line A-A′ inFIG.2. Further,FIG.2may be taken along line A-A′ in any ofFIGS.3A,3B,4A,4B, and5. In alternative embodiments in whichFIG.2is applied toFIG.3A,FIG.2further comprises the barrier layer302extending in a closed path around the photodetector110along a boundary of the pixel106. With reference toFIG.6, a cross-sectional view600of some embodiments of the image sensor ofFIG.1is provided in which the image sensor comprises multiple pixels106. The pixels106are each as their counterpart is illustrated and described atFIG.1. Further, the pixels106share the inter-pixel trench isolation structure102. For clarity, boundaries602between the pixels106are demarcated by dashed lines. In some embodiments, a width Wltlof the low-transmission layer104is greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Further, in some embodiments, the width Wltlis about 100-200 nanometers, about 200-500 nanometers, or some other suitable value. If the width Wltlis too small (e.g., less than about 100 nanometers or some other suitable value), the low-transmission layer104and the inter-pixel trench isolation structure102may have high transmission and hence crosstalk may be high. If the width Wltlis too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetectors110may be small and/or the pixels106may be large. The former leads to low QE of the photodetectors110, whereas the latter leads to low pixel density. In some embodiments, a ratio between the width Wltland the thickness Tdllis about 5:1 to 20:1, about 5:1 to 10:1, about 10:1 to 15:1, about 15:1 to 20:1, or some other suitable values. If the ratio is too high (e.g., greater than about 20:1 or some other suitable value), the thickness Tdllmay be too small and/or the width Wltlmay be too large. If the thickness Tdllis too small, the dielectric liner layer112may provide poor electrical isolation between the low-transmission layer104and the substrate108. If the ratio is too low (e.g., less than about 5:1 or some other suitable value), the thickness Tdllmay be too large and/or the width Wits may be too small. If the thickness Tdllis too small, the dielectric liner layer112may prevent too much radiation114from impinging on the low-transmission layer104. WhileFIG.6illustrates an image sensor comprising multiple pixels106each configured as the pixel106inFIG.1, the pixels106ofFIG.6may each be configured as the pixel106in any ofFIGS.3A,3B,4A,4B, and5in alternative embodiments. With reference toFIG.7, a top layout view700of some embodiments of the image sensor ofFIG.6is provided.FIG.7may, for example, be taken along line B-B′ inFIG.6and/orFIG.6may, for example, be taken along line B-B′ inFIG.7. The low-transmission layer104is continuous and individually surrounds the pixels106along boundaries602of the pixels106to separate the pixels106from each other and to reduce crosstalk. The dielectric liner layer112comprise a plurality of ring-shaped segments. The ring-shaped segments are individual to the pixels106and each extends in a closed path along the boundary of the individual pixel. While not visible within the top layout view700, the ring-shaped segments may be interconnected through portions of the dielectric liner layer112underlying the low-transmission layer104. With reference toFIG.8, a cross-sectional view800of some alternative embodiments of the image sensor ofFIG.1is provided in which the low-transmission layer104has high absorption instead of high reflection. As a result, radiation114is mostly absorbed, instead of reflected, by the low-transmission layer104when it impinges on the low-transmission layer104. The high absorption may, for example, be absorption greater than about 80%, 90%, or 95%. Other suitable percentages are, however, amenable. Because the low-transmission layer104has high absorption and low transmission, the low-transmission layer104and hence the inter-pixel trench isolation structure102prevent crosstalk. However, if the low-transmission layer104absorbed most radiation incident on the inter-pixel trench isolation structure102, QE losses would be high and hence QE would be poor. Therefore, the dielectric liner layer112is configured to promote TIR at sidewall interfaces at which the dielectric liner layer112and the substrate108directly contact. TIR reflects most radiation, and the low-transmission layer104absorbs radiation that isn't reflected, so QE losses and crosstalk are both low. Note that in the preceding embodiments, TIR at the sidewall interfaces was redundant because the low-transmission layer104had high reflectance. To promote TIR at the sidewall interfaces, the dielectric liner layer112has a higher refractive index than the substrate108. For example, the dielectric liner layer112may be or comprise silicon oxide, whereas the substrate108may be or comprise silicon. Other suitable materials are, however, amenable. Additionally, the dielectric liner layer112has a thickness Tdllto increase TIR and minimize QE losses. Generally, the larger the thickness Tdll, the greater the TIR at the sidewall interfaces and hence the less the QE losses. The thickness Tdllmay, for example, be greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Further, the thickness Tdllmay, for example, be about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value. If the thickness Tdllis too small (e.g., less than about 100 nanometers or some other suitable value), TIR at the sidewall interfaces may be low and QE losses may be high. Hence, QE and other suitable performance metrics of the photodetector110may be low. If the thickness Tdllis too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector110may be small and/or the pixel106may be large. The former leads to low QE of the photodetectors110, whereas the latter leads to low pixel density. The low transmission of the low-transmission layer104and the high absorption of the low-transmission layer104are due to intrinsic properties of material making up the low-transmission layer104and do not depend upon TIR. In some embodiments, the low-transmission layer104is metal, a conductive ceramic, some other suitable conductive material(s), or any combination of the foregoing. The metal may, for example, be or comprise tungsten and/or some other suitable metal(s). The conductive ceramic may, for example, be or comprise titanium nitride, tantalum nitride, some other suitable conductive ceramic(s), or any combination of the foregoing. In alternative embodiments, the low-transmission layer104is a dielectric and/or some other suitable material(s). In at least some embodiments in which the low-transmission layer104is dielectric, the dielectric liner layer112may be omitted. With reference toFIG.9, a top layout view900of some embodiments of the image sensor ofFIG.8is provided.FIG.9may, for example, be taken along line C-C′ inFIG.8and/orFIG.8may, for example, be taken along line C-C′ inFIG.9. Radiation114that impinges on sidewall interfaces of the dielectric liner layer112at an angle (e.g., α1) less than a critical angle for TIR passes through the dielectric liner layer112and is absorbed by the low-transmission layer104. On the other hand, radiation114that impinges on the sidewall interfaces of the dielectric liner layer112at an angle (e.g., α1) greater than the critical angle for TIR is reflected by TIR. In at least some embodiments in which the substrate108is or comprise silicon and the dielectric liner layer112is or comprises silicon oxide, the critical angle is about 20 degrees. Other suitable materials and/or critical angles are, however, amenable. With reference toFIG.10, a cross-sectional view1000of some embodiments of the image sensor ofFIG.8is provided in which the image sensor comprises multiple pixels106. The pixels106are each as their counterpart is illustrated and described atFIG.8Further, the pixels106share the inter-pixel trench isolation structure102. For clarity, boundaries602between the pixels106are demarcated by dashed lines. In some embodiments, a ratio between the width Wltlof the low-transmission layer104and the thickness Tdllof the dielectric liner layer112is about 1:1 to 5:1, about 1:1 to 2.5:1, about 2.5:1 to 5:1, or some other suitable values. If the ratio is too high (e.g., greater than about 5:1 or some other suitable value), the thickness Tdllmay be too small and/or the width Wltlmay be too large. If the thickness Tdllis too small, TIR at the sidewall interfaces may be low and QE losses may be high. If the width Wltlis too large, the photodetectors110may be too small and/or the pixels106may be too large. The former leads to low QE and the latter leads to low pixel density. If the ratio is too low (e.g., less than about 1:1 or some other suitable value), the thickness Tdllmay be too large and/or the width Wltlmay be too small. If the thickness Tdllis too large, the photodetectors110may be too small and/or the pixels106may be too large as above. If the width Wltlis too small, the low-transmission layer104may be too thin to absorb radiation114. With reference toFIG.11, a top layout view1100of some embodiments of the image sensor ofFIG.10is provided.FIG.11may, for example, be taken along line D-D′ inFIG.10and/orFIG.10may, for example, be taken along line D-D′ inFIG.11. With reference toFIG.12, a cross-sectional view1200of some alternative embodiments of the image sensor ofFIG.1is provided in which the low-transmission layer104has high absorption, instead of high reflection, as described atFIG.8. Because the low-transmission layer104has high absorption and low transmission, the low-transmission layer104prevents crosstalk. However, if the low-transmission layer104absorbed most radiation directed across pixel boundaries, QE losses would be high and hence QE would be poor. Therefore, the image sensor further comprises an intra-pixel trench isolation structure1202. The intra-pixel trench isolation structure1202is surrounded by the inter-pixel trench isolation structure102and extends into the back side108bof the substrate108. Further, the intra-pixel trench isolation structure1202comprises a pair of intra-pixel isolation segments respectively on opposite sides of the pixel106and between which the photodetector110is sandwiched. In some embodiments, the intra-pixel trench isolation structure1202extends in a closed path around the photodetector110when viewed top down. In some embodiments, the intra-pixel trench isolation structure1202is also known as an inner trench isolation structure. The intra-pixel trench isolation structure1202is configured to promote TIR at sidewall interfaces at which the intra-pixel trench isolation structure1202and the substrate108directly contact. TIR reflects most radiation in route to the inter-pixel trench isolation structure102, and the low-transmission layer104absorbs radiation that is not reflected by TIR, so QE losses and crosstalk are both low. To promote TIR, the intra-pixel trench isolation structure1202has a higher refractive index than the substrate108. For example, the intra-pixel trench isolation structure1202may be or comprise silicon oxide, whereas the substrate108may be or comprise silicon. Other suitable materials are, however, amenable. Additionally, the intra-pixel trench isolation structure1202has a width Witito increase TIR and minimize QE losses. The width Witimay, for example, be greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Further, the width Witimay, for example, be about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value. If the width Witiis too small (e.g., less than about 100 nanometers or some other suitable value), TIR at the sidewall interfaces may be low and QE losses may be high. Hence, QE and other suitable performance metrics of the photodetector110may be low. If the width Witiis too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector110may be small and/or the pixel may be large. The former leads to low QE and the latter leads to low pixel density. In some embodiments, the intra-pixel trench isolation structure1202is defined by the back side dielectric structure120. In alternative embodiments, the intra-pixel trench isolation structure1202is independent of the back side dielectric structure120. In some embodiments, the intra-pixel trench isolation structure1202is spaced from the inter-pixel trench isolation structure102by a spacing S that is about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, or some other suitable value. The intra-pixel trench isolation structure1202may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). With reference toFIGS.13A-13C, top layout views1300A-1300C of some embodiments of the image sensor ofFIG.12are provided.FIGS.13A-13Care alternative embodiments of each other and may, for example, be taken along line E-E′ inFIG.12. Further,FIG.12may, for example, be taken along line E-E′ in any ofFIGS.13A-13C. The dielectric liner layer112and the low-transmission layer104each extend along the boundary of the pixel106in closed paths to surround the photodetector110. The intra-pixel trench isolation structure1202is surrounded by the dielectric liner layer112and the low-transmission layer104. Further, the intra-pixel trench isolation structure1202extends in a closed path around the photodetector110. Radiation114that impinges on of the intra-pixel trench isolation structure1202at an angle (e.g., α1inFIGS.13A and13B) less than a critical angle for TIR passes through the intra-pixel trench isolation structure1202and is absorbed by the low-transmission layer104. Radiation114that impinges on the intra-pixel trench isolation structure1202at an angle (e.g., α2inFIGS.13A and13B) greater than the critical angle for TIR is reflected by TIR. InFIG.13A, the intra-pixel trench isolation structure1202is square ring shaped with square corners. InFIG.13B, the intra-pixel trench isolation structure1202is square ring shaped with chamfered corners. InFIG.13C, the intra-pixel trench isolation structure1202is circular ring shaped. In alternative embodiments, the intra-pixel trench isolation structure1202has other suitable layouts and/or the corners. With reference toFIG.14A, a cross-sectional view1400A of some alternative embodiments of the image sensor ofFIG.12is provided in which an additional inter-pixel trench isolation structure304separates the pixel106from neighboring pixels (not shown). The additional inter-pixel trench isolation structure304extends into the front side108fof the substrate108at the boundary of the pixel106and directly contacts both the inter-pixel trench isolation structure102and the intra-pixel trench isolation structure1202within the substrate108. The additional inter-pixel trench isolation structure304may, for example, be as described atFIG.3Band may hence provide enhanced inter-pixel isolation and crosstalk reduction when a thickness Tsof the substrate108is too great for the additional inter-pixel trench isolation structure304and the inter-pixel trench isolation structure102to individually extend through the substrate108. With reference toFIG.14B, a cross-sectional view1400B of some alternative embodiments of the image sensor ofFIG.14Ais provided in which the additional inter-pixel trench isolation structure304is spaced from the intra-pixel trench isolation structure1202. Further, an additional intra-pixel trench isolation structure1402extends into the front side108fof the substrate108to the intra-pixel trench isolation structure1202while being surrounded by and spaced from the additional inter-pixel trench isolation structure304. The additional intra-pixel trench isolation structure1402comprises a dielectric material having a higher refractive index than the substrate108so as to promote TIR at sidewall interfaces at which the additional intra-pixel trench isolation structure1402and the substrate108directly contact. By promoting TIR at the sidewall interfaces, radiation114may be reflected back towards the photodetector110to reduce crosstalk and improve QE, SNR, and other suitable performance metrics. The additional intra-pixel trench isolation structure1402may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). WhileFIGS.13A-13Care described with regard toFIG.12, it is to be appreciated thatFIGS.13A-13Care applicable to any ofFIGS.14A and14Bin alternative embodiments. Hence, any ofFIGS.14A and14Bmay be taken along line E-E′ in any ofFIGS.13A-13C. Further, any ofFIGS.13A-13Cmay be taken along line E-E′ in any ofFIGS.14A and14B. With reference toFIG.15, a cross-sectional view1500of some alternative embodiments of the image sensor ofFIG.12is provided in which the image sensor comprises multiple pixels106. The pixels106are each as their counterpart is illustrated and described atFIG.12. Further, the pixels106share the inter-pixel trench isolation structure102and have individual intra-pixel trench isolation structures1202. For clarity, boundaries602between the pixels106are demarcated by dashed lines. WhileFIG.15illustrates an image sensor comprising multiple pixels106each configured as the pixel106inFIG.12, the pixels106ofFIG.15may each be configured as the pixel106in any ofFIGS.14A and14Bin alternative embodiments. With reference toFIG.16, a top layout view1600of some embodiments of the image sensor ofFIG.15is provided.FIG.16may, for example, be taken along line F-F′ inFIG.15and/orFIG.15may, for example, be taken along line F-F′ inFIG.16. With reference toFIG.17, a cross-sectional view1700of some embodiments of the image sensor ofFIG.1is provided in which the photodetector110is shown in more detail and is electrically coupled to an interconnect structure1702on the front side108fof the substrate108. The photodetector110comprises a first contact region1704, a guard ring1706, and a pair of second contact regions1708. Further, the photodetector110may, for example, be an APD, an SPAD, or some other suitable type of photodetector. The first contact region1704is at a center of the pixel106. The guard ring1706surrounds the first contact region1704and has a pair of guard ring segments. The guard ring segments are respectively on opposite sides of the first contact region1704at a boundary of the first contact region. In some embodiments, the guard ring1706extends in a closed path along a boundary of the first contact region1704when viewed top down. The first contact region1704and the guard ring1706share a common doping type, but the first contact region1704has a higher doping concentration. Further, the common doping type is opposite to a doping type of adjoining regions of the substrate108and/or a bulk of the substrate108. The second contact regions1708are respectively on opposite sides of the guard ring1706at a periphery of the pixel106. In some embodiments, the second contact regions1708correspond to different segments of a ring-shaped contact region extending in a closed path around the guard ring1706. The second contact regions1708share a common doping type that is opposite that of the first contact region1704and the guard ring1706. The interconnect structure1702is in the front side dielectric structure118and comprises a plurality of contacts1710, a plurality of wires1712, and a plurality of vias1714. The contacts1710extend from the first and second contact regions1704,1708, and the wires1712and the vias1714are alternating stacked under the contacts1710to define conductive paths leading from the contacts1710. The contacts1710, the wires1712, and the vias1714may, for example, be or comprise metal and/or other suitable conductive materials. With reference toFIG.18, a cross-sectional view1800of some alternative embodiments of the image sensor ofFIG.1is provided in which the image sensor is front side illuminated (FSI) instead of back side illuminated (BSI). As such, the spacer layer124and the micro lens126are on the front side108fof the substrate108and the image sensor is configured to receive external radiation114exfrom the front side108fof the substrate108. Additionally, the inter-pixel trench isolation structure102extends into the front side108fof the substrate108to a depth less than a full thickness of the substrate108. In alternative embodiments, the inter-pixel trench isolation structure102extends fully through the substrate108. With reference toFIGS.19A and19B, cross-sectional views1900A,1900B of some alternative embodiments of the image sensor ofFIG.18are provided in which the inter-pixel trench isolation structure102extends into the back side108bof the substrate108instead of the front side108fof the substrate108. InFIG.19A, the low-transmission layer104and the dielectric liner layer112do not cover the back side108bof the substrate108. InFIG.19B, the low-transmission layer104and the dielectric liner layer cover the back side108bof the substrate108. Further, the back side dielectric structure120is divided into a first back side dielectric layer120aand a second back side dielectric layer120brespectively under and over the low-transmission layer104. The first back side dielectric layer120aand/or the second back side dielectric layer120bmay, for example, be as the back side dielectric structure120ofFIG.18is described. Because the low-transmission layer104covers the back side108bof the substrate108and has a high reflectance, radiation114that passes across the back side108bof the substrate108to the low-transmission layer104may be reflected back to the photodetector110. This gives the photodetector110another opportunity to absorb the radiation114. Hence, QE and other suitable performance metrics of the photodetector110are enhanced. With reference toFIG.20, a cross-sectional view2000of some embodiments of the image sensor ofFIG.18is provided in which the photodetector110is shown in more detail and is electrically coupled to an interconnect structure1702on the front side108fof the substrate108. The photodetector110and the interconnect structure1702are as described atFIG.17except conductive features (e.g., the contacts1710, the wires1712, and the vias1714) of the interconnect structure1702are cleared directly under the first contact region1704to allow radiation to pass through the interconnect structure1702to the photodetector110. WhileFIG.3Aillustrates alternative embodiments of the image sensor ofFIG.1including the barrier layer302, alternative embodiments of the image sensor in any ofFIGS.3B,4A,4B,5A,5B,6,8,10,12,14A,14B,15,17,18,19A,19B, and20may include the barrier layer302as inFIG.3A. WhileFIG.3Billustrates alternative embodiments of the image sensor ofFIG.1including the additional inter-pixel trench isolation structure304, alternative embodiments of the image sensor in any ofFIGS.3A,4B,5A,5B,6,8,10,12,15, and17may include the additional intra-pixel trench isolation structure304as inFIG.3B. WhileFIG.4Aillustrates alternative embodiments of the image sensor ofFIG.1in which the inter-pixel trench isolation structure102extends into the front side108fof the substrate108, alternative embodiments of the image sensor in any ofFIGS.3A,3B,4B,5A,5B,6,8,10,12,15, and17may also have the inter-pixel trench isolation structure102extending into the front side108fof the substrate108as inFIG.4A. WhileFIG.4Billustrates alternative embodiments of the image sensor ofFIG.1in which a top surface of the low-transmission layer104is about even with that of the substrate108, alternative embodiments of the image sensor in any ofFIGS.3A,3B,4A,5A,5B,6,8,10,12,14A,14B,15,17,18,19A,19B, and20may also have the top surface of the low-transmission layer104about even with that of the substrate108. WhileFIGS.5A and5Billustrates alternative embodiments of the image sensor ofFIG.1in which constituents of the diffuser122and/or the dielectric liner layer112is/are omitted, alternative embodiments of the image sensor in any ofFIGS.3A,3B,4A,4B,6,8,10,12,14A,14B,15,17,18,19A,19B, and20may also omit the diffuser122and/or the dielectric liner layer112. WhileFIG.8illustrates alternative embodiments of the image sensor ofFIG.1in which the low-transmission layer104is absorptive and the dielectric liner layer112is configured for TIR, the low-transmission layer104may be absorptive as inFIG.8and the dielectric liner layer112may be configured for TIR as inFIG.8in alternative embodiments of the image sensor in any ofFIGS.3A,3B,4A,4B,5A,5B,6,12,14A,14B,15,17,18,19A,19B, and20. WhileFIG.12illustrates alternative embodiments of the image sensor ofFIG.1in which the low-transmission layer104is absorptive and the image sensor further comprises the intra-pixel trench isolation structure1202, the low-transmission layer104may be absorptive as inFIG.12and the image sensor may further comprises the intra-pixel trench isolation structure1202as inFIG.12in alternative embodiments of the image sensor in any ofFIGS.3A,3B,4A,4B,5A,5B,6,8,10,17,18,19A,19B, and20. WhileFIG.17illustrates more detailed embodiments of the image sensor ofFIG.1in which the photodetector110is shown in more detail and electrically coupled to an interconnect structure1702, the photodetector110in any ofFIGS.3A,3B,4A,4B,5A,5B,6,12,14A,14B, and15may be as shown inFIG.17and electrically coupled to an interconnect structure1702as inFIG.17in alternative embodiments. WhileFIG.18illustrates alternative embodiments of the image sensor ofFIG.1in which the image sensor is FSI, the image sensor in any ofFIGS.3A,3B,4A,4B,5A,5B,6,12,14A,14B, and15may be FSI as inFIG.18in alternative embodiments. With reference toFIGS.21-26,27A,27B,28, and29, a series of cross-sectional views2100-2600,2700A,2700B,2800,2900of some embodiments of a method for forming an image sensor is provided in which an inter-pixel trench isolation structure defined in part by a low-transmission layer. The method may, for example, be employed to form the image sensor in any ofFIGS.1,2,3A,3B,4B,5A,5B, and6-11and other suitable image sensors. As illustrated by the cross-sectional view2100ofFIG.21, a photodetector110is formed in a substrate108from a front side108fof the substrate108. The photodetector110is individual to a pixel106of the image sensor being formed and comprises a first contact region1704, a guard ring1706, and a pair of second contact regions1708. The first contact region1704and the guard ring1706share a common doping type opposite to that of adjoining regions of the substrate108. Further, the guard ring1706has a lesser doping concentration than the first contact region1704. The second contact regions1708have an opposite doping type as the first contact region1704and the guard ring1706. The photodetector110may, for example, be an APD, an SPAD, or some other suitable type of photodetector. In alternative embodiments, the photodetector110has some other suitable configuration. As illustrated by the cross-sectional view2200ofFIG.22, a front side dielectric structure118is formed covering the photodetector110on the front side108fof the substrate108. In some embodiments, the front side dielectric structure118has a higher refractive index than the substrate108at an interface between the front side dielectric structure118and the substrate108to promote TIR at the interface. The first back side dielectric layer120amay, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). Also illustrated by the cross-sectional view2200ofFIG.22, an interconnect structure1702is formed electrically coupled to the photodetector110in the front side dielectric structure118. The interconnect structure1702comprises a plurality of contacts1710, a plurality of wires1712, and a plurality of vias1714. The contacts1710extend from the first and second contact regions1704,1708, and the wires1712and the vias1714are alternating stacked over the contacts1710to define conductive paths leading from the contacts1710. As illustrated by the cross-sectional view2300ofFIG.23, the substrate108is flipped so a back side108bof the substrate108overlies the front side108fof the substrate108. Further, the back side108bof the substrate108is patterned to form a periodic pattern2302directly over the photodetector110. The periodic pattern may, for example, have a saw-toothed profile or some other suitable profile. The patterning may, for example, be performed by a photolithography/etching process or some other suitable patterning process. As illustrated, by the cross-sectional view2400ofFIG.24, a first back side dielectric layer120ais deposited covering the back side108bof the substrate108and the periodic pattern2302(see, e.g.,FIG.23). The first back side dielectric layer120ahas a higher refractive index than the substrate108to promote TIR at an interface between the first back side dielectric layer120aand the substrate108. Further, a top surface of the first back side dielectric layer120ais rough at least at the periodic pattern. The first back side dielectric layer120amay, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). Collectively, the first back side dielectric layer120aand the substrate108define a diffuser122at the periodic pattern2302(see, e.g.,FIG.23). The diffuser122serves to scatter external radiation114exreceived at the back side108bof the substrate108. This may, for example, increase an angle of incidence of the external radiation114exat the front side108fof the substrate108to increase TIR at the front side108f. By increasing TIR at the front side108fof the substrate108, more of the external radiation114exmay be reflected back to the photodetector110. Hence, QE and other suitable performance metrics of the photodetector110may be enhanced. As illustrated by the cross-sectional view2500ofFIG.25, a top surface of the first back side dielectric layer120ais flattened. The flattening may, for example, be performed by a chemical mechanical polish (CMP) or some other suitable planarization process. As illustrated by the cross-sectional view2600ofFIG.26, the first back side dielectric layer120aand the substrate108are patterned to define an inter-pixel isolation trench2602. The inter-pixel isolation trench2602may, for example, also be known as an outer isolation trench. The inter-pixel isolation trench2602has a pair of segments respectively on opposite sides of the photodetector110at a boundary of the pixel106. In some embodiments, the inter-pixel isolation trench2602extends in a closed path along a boundary of the pixel106to surround the photodetector110when viewed top down. Further, in some embodiments, the inter-pixel isolation trench2602has the same top layout as the inter-pixel trench isolation structure102ofFIG.2orFIG.7. The patterning may, for example, be performed by a photolithography/etching process or some other suitable patterning process. As illustrated by the cross-sectional views2700A ofFIG.27A, a dielectric liner layer112and a low-transmission layer104are deposited filling the inter-pixel isolation trench2602(see, e.g.,FIG.26). The dielectric liner layer112is deposited before the low-transmission layer104and electrically separates the low-transmission layer104from the substrate108. The dielectric liner layer112may, for example, be or comprise silicon oxide, aluminum oxide, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the dielectric liner layer112also serves as a diffusion barrier for the low-transmission layer104. For example, the dielectric liner layer112may be or comprise aluminum oxide, whereas the low-transmission layer104may be or comprise copper. Other suitable materials are, however, amenable. In some embodiments, the dielectric liner layer112has a higher refractive index than the substrate108. For example, the dielectric liner layer112may be or comprise silicon oxide, whereas the substrate108may be or comprise silicon. The dielectric liner layer112has low absorption for radiation and, in some embodiments, has high transmission for radiation. The low absorption may, for example, be absorption less about than 10%, 5%, 1%, or some other suitable percentage of incident radiation. The high transmission may, for example, be transmission greater than 90%, 95%, 99%, or some other suitable percentage of incident radiation. The low absorption minimizes QE losses while the high transmission allows radiation to pass unimpeded to the low-transmission layer104. In some embodiments, the dielectric liner layer112is transparent to radiation. In some embodiments, to achieve low absorption and high transmission, a thickness Tdllof the dielectric liner layer112is small. The thickness Tdllmay, for example, be small when less than about 100 nanometers, about 50 nanometers, about 10 nanometers, or some other suitable value. Further, the thickness Tdllmay, for example, be small when about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, about 20 nanometers, or some other suitable value. If the thickness Tdllis too small (e.g., less than about 10 nanometers or some other suitable value), the dielectric liner layer112may be unable to electrically separate the low-transmission layer104from the substrate108. If the thickness Tdllis too large (e.g., more than about 100 nanometers or some other suitable value), the dielectric liner layer112may absorb or otherwise interfere with radiation traveling to the low-transmission layer104. The dielectric liner layer112may, for example, be deposited by thermal oxidation, such that the dielectric liner layer112grows from the substrate108but does not grow, or minimally grows, from the first back side dielectric layer120a. Alternatively, the dielectric liner layer112may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or some other suitable deposition process. The low-transmission layer104overlies the dielectric liner layer112in the inter-pixel isolation trench2602and further covers the first back side dielectric layer120a. The low-transmission layer102has low transmission for radiation and hence blocks most or all radiation incident thereon. In some embodiments, the low transmission is transmission less than about 1%, 5%, 10%, or some other suitable percentage of radiation. In some embodiments, the low-transmission layer104is opaque to radiation. The low-transmission layer104further has high reflectance for radiation. The high reflectance may, for example, be reflectance greater than about 80%, 90%, 95%, or some other suitable percentage of radiation. The low transmission of the low-transmission layer104and the high reflectance of the low-transmission layer104are due to intrinsic properties of material making up the low-transmission layer104and do not depend upon TIR. In some embodiments, the low-transmission layer104is metal and/or some other suitable conductive material(s). The metal may, for example, be or comprise copper, aluminum, silver, some other suitable metal(s), or any combination of the foregoing. In alternative embodiments, the low-transmission layer104is a dielectric and/or some other suitable material(s). In at least some embodiments in which the low-transmission layer104is dielectric, deposition of the dielectric liner layer112may be omitted and the low-transmission layer104may be deposited directly on the substrate108in the inter-pixel isolation trench2602. The low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102filling the inter-pixel isolation trench2602. A top layout of the inter-pixel trench isolation structure102may, for example, be as in any ofFIGS.2,7,9, and11. Because the low-transmission layer104has the low transmission and the high reflectance, the inter-pixel trench isolation structure102also has the low transmission and the high reflectance. Because of the low transmission, the inter-pixel trench isolation structure102may reduce radiation from passing from the pixel106to neighboring pixels (not shown), or vice versa, and may hence reduce crosstalk. By reducing crosstalk, SNR and other suitable performance metrics of the photodetector110may be enhanced. Because of the high reflectance, the inter-pixel trench isolation structure102may reflect radiation incident thereon back towards the photodetector110. This provides the photodetector110with another opportunity to absorb the radiation, which may improve QE, SNR, and other suitable performance metrics of the photodetector110. In some embodiments, the photodetector110operates in a reverse biased state at a high voltage. For example, the photodetector110may be an APD, a SPAD, or some other suitable type of photodetector. Because the photodetector110may operate at the high voltage, the photodetector110may be prone to hot carrier luminescence116(schematically illustrated by a star). Hot carrier luminescence116may emit hot carrier radiation114hcin any direction, which makes it difficult to efficiently block the hot carrier radiation114hcby TIR. TIR depends upon the angle of incidence exceeding a so-called critical angle. Because the inter-pixel trench isolation structure102has the low transmission and does not depend upon TIR for the low transmission, the inter-pixel trench isolation structure102may block the hot carrier radiation114hcregardless of the angle of incidence. As a result, the inter-pixel trench isolation structure102may efficiently reduce crosstalk from hot carrier luminescence116. Further, because the inter-pixel trench isolation structure102has the high reflectance and does not depend upon TIR for the high reflectance, the inter-pixel trench isolation structure102may reflect the hot carrier radiation114hcregardless of angle of incidence. In some embodiments, the patterning atFIG.26and the deposition of the dielectric liner layer112coordinate so a width Wltlof the low-transmission layer104in the inter-pixel isolation trench2602is greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Further, in some embodiments, the width Wltlis about 100-200 nanometers, about 200-500 nanometers, or some other suitable value. If the width Wltlis too small (e.g., less than about 100 nanometers or some other suitable value), the low-transmission layer104may have high transmission and hence crosstalk may be high. If the width Wltlis too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector110may be small and/or the size of the pixel106may be large. The former degrades performance of the photodetector110and the latter degrades pixel density. As illustrated by the cross-sectional views2700B ofFIG.27B, the dielectric liner layer112and the low-transmission layer104are deposited filling the inter-pixel isolation trench2602(see, e.g.,FIG.26) according to alternative embodiments. In other words,FIGS.27A and27Bare alternatives of each other and hence each individually illustrates the deposition proceeding fromFIG.26. In contrast withFIG.27A, the low-transmission layer104ofFIG.27Bhas high absorption instead of high reflection. As a result, radiation is mostly absorbed, instead of reflected, by the low-transmission layer104. The high absorption may, for example, be absorption greater than about 80%, 90%, or 95%. Other suitable percentages are, however, amenable. If the inter-pixel trench isolation structure102absorbed most radiation incident on the inter-pixel trench isolation structure102, QE losses would be high and hence QE would be poor. Therefore, the dielectric liner layer112is configured to promote TIR at sidewall interfaces at which the dielectric liner layer112and the substrate108directly contact. TIR at the sidewall interfaces reflects most radiation before it reaches the low-transmission layer104, and the low-transmission layer104absorbs any radiation that passes through dielectric liner layer112without be reflected by TIR, so QE losses and crosstalk are both low. To promote TIR at the sidewall interfaces, the dielectric liner layer112has a higher refractive index than the substrate108. Additionally, the dielectric liner layer112has a thickness Tdllto increase TIR and minimize QE losses. Generally, the larger the thickness Tdll, the greater the TIR at the sidewall interfaces and hence the less the QE losses. The thickness Tdllmay, for example, be greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Further, the thickness Tdllmay, for example, be about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value. If the thickness Tdllis too small (e.g., less than about 100 nanometers or some other suitable value), TIR at the sidewall interfaces may be low and QE losses may be high. Hence, QE and other suitable performance metrics of the photodetector110may be low. If the thickness Tdllis too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector110may be small and/or the size of the pixel106may be large. The former leads to poor performance and the latter leads to low pixel density. In some embodiments, the low-transmission layer104is metal, a conductive ceramic, some other suitable conductive material(s), or any combination of the foregoing. The metal may, for example, be or comprise tungsten and/or some other suitable metal(s). The conductive ceramic may, for example, be or comprise titanium nitride, tantalum nitride, some other suitable conductive ceramic(s), or any combination of the foregoing. As illustrated by the cross-sectional view2800ofFIG.28, a top surface of the low-transmission layer104is recessed to uncover the first back side dielectric layer120a. The recessing may be performed on the low-transmission layer104in any ofFIGS.27A and27Bbut is illustrated using the low-transmission layer104inFIG.27A. As noted above,FIGS.27A and27Bare alternatives of each other. In some embodiments, the recessing persists until the top surface of the low-transmission layer104is about even with that of the first back side dielectric layer120a. In other embodiments, the recessing persists until the top surface of the low-transmission layer104is about even with that of the substrate108. In some embodiments, the recessing also flattens the top surface of the low-transmission layer104. The recessing may, for example, be performed by an etch back, a CMP, some other suitable process, or any combination of the foregoing. As illustrated by the cross-sectional view2900ofFIG.29, a second back side dielectric layer120band a spacer layer124are deposited over the inter-pixel trench isolation structure102and the first back side dielectric layer120a. Further, micro lenses126are formed over the spacer layer124. The second back side dielectric layer120band the spacer layer124may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). WhileFIGS.21-26,27A,27B,28, and29are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.21-26,27A,27B,28, and29are not limited to the method but rather may stand alone separate of the method. WhileFIGS.21-26,27A,27B,28, and29are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.21-26,27A,27B,28, and29illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.30, a block diagram3000of some embodiments of the method ofFIGS.21-26,27A,27B,28, and29is provided. At3002, a photodetector is formed in a substrate from a front side of the substrate. See, for example,FIG.21. At3004, an interconnect structure is formed covering and electrically coupled to the photodetector on the front side of the substrate. See, for example,FIG.22. At3006, a back side of the substrate is patterned to form a periodic pattern overlying the photodetector. See, for example,FIG.23. At3008, a first back side dielectric layer is deposited covering the back side of the substrate and the periodic pattern. See, for example,FIG.24. At3010, a top surface of the first back side dielectric layer is flattened. See, for example,FIG.25. At3012, the first back side dielectric layer and the back side of the substrate are patterned to form an inter-pixel isolation trench surrounding the photodetector along a boundary of a pixel at which the photodetector is located. See, for example,FIG.26. At3014, a dielectric liner layer is deposited lining and partially filling the inter-pixel isolation trench. See, for example,FIGS.27A and27B. At3016, a low-transmission layer is deposited filling the inter-pixel isolation trench over the dielectric liner layer and covering the first back side dielectric layer. See, for example,FIGS.27A and27B. The low-transmission layer may, for example, be metal, a conductive ceramic, some other suitable materials, or any combination of the foregoing. Further, the low-transmission layer may, for example, have high reflectance or high absorption. At3018, a top surface of the low-transmission layer is recessed to uncover the first back side dielectric layer. See, for example,FIG.28. At3020, a second back side dielectric layer and a spacer layer are deposited covering the first back side dielectric layer and the low-transmission layer. See, for example,FIG.29. At3022, a micro lens is formed covering the photodetector over the spacer layer. See, for example,FIG.29. While the block diagram3000ofFIG.30is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. With reference toFIGS.31-33,34A,34B,35, and36, a series of cross-sectional views3100-3300,3400A,3400B,3500,3600of some alternative embodiments of the method ofFIGS.31-33,34A,34B,35, and36is provided in which the dielectric liner layer112and the first back side dielectric layer120aare integrated together. As illustrated by the cross-sectional view3100ofFIG.31, the acts atFIGS.21-23are performed. A photodetector110is formed in a substrate108from a front side108fof the substrate108as described with regard toFIG.21. A front side dielectric structure118and an interconnect structure1702are formed covering the photodetector110on the front side108fof the substrate108as described with regard toFIG.22. A back side108bof the substrate108is patterned to form a periodic pattern2302directly over the photodetector110as described with regard toFIG.23. Also illustrated by the cross-sectional view3100ofFIG.31, the substrate108is patterned to define an inter-pixel isolation trench2602. The inter-pixel isolation trench2602has a pair of segments respectively on opposite sides of the photodetector110. In some embodiments, the inter-pixel isolation trench2602extends in a closed path along a boundary of the pixel106to surround the photodetector110when viewed top down. Further, in some embodiments, the inter-pixel isolation trench2602has the same top layout as the inter-pixel trench isolation structure102ofFIG.2or7. The patterning may, for example, be performed by a photolithography/etching process or some other suitable patterning process. In some embodiments, the patterning to form the inter-pixel isolation trench2602is independent of the patterning to form the periodic pattern2302. For example, the inter-pixel isolation trench2602and the periodic pattern2302may be formed using different photolithography/etching processes with difference masks. As illustrated by the cross-sectional view3200ofFIG.32, a first back side dielectric layer120ais deposited covering the back side108bof the substrate108and lining the inter-pixel isolation trench2602. The first back side dielectric layer120ahas a higher refractive index than the substrate108to promote TR at an interface between the first back side dielectric layer120aand the substrate108. Further, a top surface of the first back side dielectric layer120ais rough at least at the periodic pattern (see, e.g.,FIG.31). The first back side dielectric layer120amay, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). The dielectric liner layer112may, for example, be deposited by CVD, PVD, or some other suitable deposition process. In some embodiments, a thickness Tfbdof the first back side dielectric layer120ais greater at a bottom surface of the first back side dielectric layer120aand a top surface of the first back side dielectric layer120athan at sidewalls of the first back side dielectric layer120adue to the deposition process. Collectively, the first back side dielectric layer120aand the substrate108define a diffuser122at the periodic pattern2302(see, e.g.,FIG.31). The diffuser122serves to scatter external radiation114exreceived at the back side108bof the substrate108. Further, a portion of the first back side dielectric layer120ain the inter-pixel isolation trench2602defines a dielectric liner layer112. Other than being formed as part of the first back side dielectric layer120a, the dielectric liner layer112may, for example, be as described with regard toFIGS.27A and27B. As illustrated by the cross-sectional view3300ofFIG.33, a top surface of the first back side dielectric layer120ais flattened. Further, the first back side dielectric layer120ais etched back to reduce the thickness Tfbdof the first back side dielectric layer120aat top and bottom surfaces of the first back side dielectric layer120a. The flattening may, for example, be performed by a CMP and/or some other suitable planarization process. As illustrated by the cross-sectional views3400A,3400B ofFIGS.34A and34B, a low-transmission layer104is deposited filling the inter-pixel isolation trench2602(see, e.g.,FIG.33) over the dielectric liner layer112.FIGS.34A and34Bare alternative of each other and hence each individually illustrates the deposition.FIG.34Aproceeds fromFIG.33, whereasFIG.34Bproceeds from alternative embodiments ofFIG.33in which the dielectric liner layer112is deposited or otherwise formed with a lesser thickness Tdll. InFIG.34A, the low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102as described with regard toFIG.27B. The low-transmission layer104has a low transmission and a high absorption, whereas the dielectric liner layer112is configured for TIR. The dielectric liner layer112reflects radiation by TIR, and the low-transmission layer104absorbs radiation not reflected by TIR, to respectively increase QE and reduce crosstalk. InFIG.34B, the low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102as described with regard toFIG.27A. The low-transmission layer104has a low transmission and a high reflection, whereas the dielectric liner layer112has low absorption. In some embodiments, the dielectric liner layer112is transparent. The low-transmission layer104reflects radiation to reduce crosstalk and increase QE. As illustrated by the cross-sectional view3500ofFIG.35, a top surface of the low-transmission layer104is recessed to uncover the first back side dielectric layer120aas described with regard toFIG.28. The recessing may be performed on the low-transmission layer104in any ofFIGS.34A and34Bbut is illustrated using the low-transmission layer104inFIG.34A. As noted above,FIGS.34A and34Bare alternatives of each other. As illustrated by the cross-sectional view3600ofFIG.36, a second back side dielectric layer120band a spacer layer124are deposited over the inter-pixel trench isolation structure102and the first back side dielectric layer120a. Further, micro lenses126are formed over the spacer layer124. The second back side dielectric layer120band the spacer layer124may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). WhileFIGS.31-33,34A,34B,35, and36are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.31-33,34A,34B,35, and36are not limited to the method but rather may stand alone separate of the method. WhileFIGS.31-33,34A,34B,35, and36are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.31-33,34A,34B,35, and36illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.3700, a block diagram3700of some embodiments of the method ofFIGS.31-33,34A,34B,35, and36is provided. At3702, a photodetector is formed in a substrate from a front side of the substrate. See, for example,FIGS.31and21. At3704, an interconnect structure is formed covering and electrically coupled to the photodetector on the front side of the substrate. See, for example,FIGS.31and22. At3706, a back side of the substrate is patterned to form a periodic pattern overlying the photodetector. See, for example,FIGS.31and23. At3708, the back side of the substrate is patterned to form an inter-pixel isolation trench surrounding the photodetector along a boundary of a pixel at which the photodetector is located. See, for example,FIG.31. At3710, a first back side dielectric layer is deposited covering the back side of the substrate and lining the inter-pixel isolation trench. See, for example,FIG.32. At3712, a top surface of the first back side dielectric layer is flattened and etched back. See, for example,FIG.33. At3714, a low-transmission layer is deposited filling the inter-pixel isolation trench and covering the first back side dielectric layer. See, for example,FIGS.34A and34B. At3716, a top surface of the low-transmission layer is recessed to uncover the first back side dielectric layer. See, for example,FIG.35. At3718, a second back side dielectric layer and a spacer layer are deposited covering the first back side dielectric layer and the low-transmission layer. See, for example,FIG.36. At3720, a micro lens is formed covering the photodetector. See, for example,FIG.36. While the block diagram3700ofFIG.37is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. With reference toFIGS.38,39,40A,40B,41, and42, a series of cross-sectional views3800,3900,4000A,4000B,4100,4200of some alternative embodiments of the method ofFIGS.21-26,27A,27B,28, and29is provided in which the dielectric liner layer112is deposited covering the first back side dielectric layer120a. As illustrated by the cross-sectional view3800ofFIG.38, the acts atFIGS.21-26are performed. A photodetector110is formed in a substrate108from a front side108fof the substrate108as described with regard toFIG.21. A front side dielectric structure118and an interconnect structure1702are formed covering the photodetector110on the front side108fof the substrate108as described with regard toFIG.22. A back side108bof the substrate108is patterned to form a periodic pattern directly over the photodetector110as described with regard toFIG.23. A first back side dielectric layer120ais deposited covering the back side108bof the substrate108and the periodic pattern as described with regard toFIG.24. Collectively, the first back side dielectric layer120aand the substrate108define a diffuser122at the periodic pattern. A top surface of the first back side dielectric layer120ais flattened as described with regard toFIG.25. The first back side dielectric layer120aand the substrate108are patterned to define an inter-pixel isolation trench2602as described with regardFIG.26. Also illustrated by the cross-sectional view3800ofFIG.38, a dielectric liner layer112is deposited covering the first back side dielectric layer120aand lining the inter-pixel isolation trench2602. The dielectric liner layer112may, for example, be deposited by CVD, PVD, or some other suitable deposition process. In some embodiments, a thickness Tdllof the dielectric liner layer112is greater at top and bottom surfaces of the dielectric liner layer112than at sidewalls of the dielectric liner layer112due to the deposition process. The dielectric liner layer112may, for example, be as described with regard toFIGS.27A and27B. As illustrated by the cross-sectional view3900ofFIG.39, the dielectric liner layer112is etched back to reduce the thickness Tdllof the dielectric liner layer112at top and bottom surfaces of the dielectric liner layer112. As illustrated by the cross-sectional views4000A,4000B ofFIGS.40A and40B, a low-transmission layer104is deposited filling the inter-pixel isolation trench2602(see, e.g.,FIG.39) over the dielectric liner layer112.FIGS.40A and40Bare alternative of each other and hence each individually illustrates the deposition.FIG.40Aproceeds fromFIG.39, whereasFIG.40Bproceeds from alternative embodiments ofFIG.39in which the dielectric liner layer112is deposited or otherwise formed with a lesser thickness Tdll. InFIG.40A, the low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102as described with regard toFIG.27B. The low-transmission layer104has a low transmission and a high absorption, whereas the dielectric liner layer112is configured for TIR. The dielectric liner layer112reflects radiation by TIR, and the low-transmission layer104absorbs radiation not reflected by TIR, to respectively increase QE and reduce crosstalk. InFIG.40B, the low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102as described with regard toFIG.27A. The low-transmission layer104has a low transmission and a high reflection, whereas the dielectric liner layer112has low absorption. In some embodiments, the dielectric liner layer112is transparent. The low-transmission layer104reflects radiation to reduce crosstalk and increase QE. As illustrated by the cross-sectional view4100ofFIG.41, a top surface of the low-transmission layer104is recessed to uncover the first back side dielectric layer120aas described with regard toFIG.28. The recessing may be performed on the low-transmission layer104in any ofFIGS.40A and40Bbut is illustrated using the low-transmission layer104inFIG.40A. As noted above,FIGS.40A and40Bare alternatives of each other. As illustrated by the cross-sectional view4200ofFIG.42, a second back side dielectric layer120band a spacer layer124are deposited over the inter-pixel trench isolation structure102and the first back side dielectric layer120a. Further, micro lenses126are formed over the spacer layer124. The second back side dielectric layer120band the spacer layer124may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). WhileFIGS.38,39,40A,40B,41, and42are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.38,39,40A,40B,41, and42are not limited to the method but rather may stand alone separate of the method. WhileFIGS.38,39,40A,40B,41, and42are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.38,39,40A,40B,41, and42illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.4300, a block diagram4300of some embodiments of the method ofFIGS.38,39,40A,40B,41, and42is provided. At4302, a photodetector is formed in a substrate from a front side of the substrate. See, for example,FIGS.38and21. At4304, an interconnect structure is formed covering and electrically coupled to the photodetector on the front side of the substrate. See, for example,FIGS.38and22. At4306, a back side of the substrate is patterned to form a periodic pattern overlying the photodetector. See, for example,FIGS.38and23. At4308, a first back side dielectric layer is deposited covering the back side of the substrate and the periodic pattern. See, for example,FIGS.38and24. At4310, a top surface of the first back side dielectric layer is flattened. See, for example,FIGS.38and25. At4312, the first back side dielectric layer and the back side of the substrate are patterned to form an inter-pixel isolation trench surrounding the photodetector along a boundary of a pixel at which the photodetector is located. See, for example,FIGS.38and36. At4314, a dielectric liner layer is deposited lining the inter-pixel isolation trench and covering the first back side dielectric layer. See, for example,FIG.38. At4316, the dielectric liner layer is etched back. See, for example,FIG.39. At4318, a low-transmission layer is deposited filling the inter-pixel isolation trench over the dielectric liner layer and covering the first back side dielectric layer. See, for example,FIGS.40A and40B. At4320, a top surface of the low-transmission layer is recessed to uncover the first back side dielectric layer. See, for example,FIG.41. At4322, a second back side dielectric layer and a spacer layer are deposited covering the first back side dielectric layer and the low-transmission layer. See, for example,FIG.42. At4324, a micro lens is formed covering the photodetector over the spacer layer. See, for example,FIG.42. While the block diagram4300ofFIG.43is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. With reference toFIGS.44-47,48A,48B,49, and50, a series of cross-sectional views4400-4700,4800A,4800B,4900, and5000of some alternative embodiments of the method ofFIGS.21-26,27A,27B,28, and29is provided in which the image sensor further comprises an intra-pixel trench isolation structure. The method may, for example, be employed to form the image sensor in any ofFIGS.12,13A-13C,14A,14B,15, and16and other suitable image sensors. As illustrated by the cross-sectional view4400ofFIG.44, the acts atFIGS.21-23are performed. A photodetector110is formed in a substrate108from a front side108fof the substrate108as described with regard toFIG.21. A front side dielectric structure118and an interconnect structure1702are formed covering the photodetector110on the front side108fof the substrate108as described with regard toFIG.22. A back side108bof the substrate108is patterned to form a periodic pattern2302directly over the photodetector110as described with regard toFIG.23. Also illustrated by the cross-sectional view4400ofFIG.44, the substrate108is patterned to define an intra-pixel isolation trench4402. The intra-pixel isolation trench4402may, for example, also be known as an inner isolation trench. The intra-pixel isolation trench4402has a pair of segments respectively on opposite sides of the photodetector110. The patterning may, for example, be performed by a photolithography/etching process or some other suitable patterning process. In some embodiments, the patterning to form the intra-pixel isolation trench4402is independent of the patterning to form the periodic pattern2302. For example, the intra-pixel isolation trench4402and the periodic pattern2302may be formed using different photolithography/etching processes with difference masks. In some embodiments, the intra-pixel isolation trench4402extends in a closed path to surround the photodetector110when viewed top down. In some embodiments, the intra-pixel isolation trench4402has the same top layout as the intra-pixel trench isolation structure1202in any ofFIGS.13A-13C and16. In some embodiments, a width Witiof the intra-pixel isolation trench4402greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Further, in some embodiments, the width Witiis about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value. As seen hereafter, an intra-pixel trench isolation structure is formed in the intra-pixel isolation trench4402and is configured to reflect incident radiation by TIR. If the width Wit, is too small (e.g., less than about 100 nanometers or some other suitable value), TIR at the sidewall interfaces may be low. If an inter-pixel trench isolation structure surrounding the intra-pixel trench isolation structure has high absorption, the low TIR may result in high QE losses. If the width Witiis too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector110may be small and/or the size of the pixel106may be large. The former leads to poor performance of the photodetector110and the latter leads to low pixel density. As illustrated by the cross-sectional view4500ofFIG.45, a first back side dielectric layer120ais deposited covering the back side108bof the substrate108and filling the intra-pixel isolation trench4402. The first back side dielectric layer120ahas a higher refractive index than the substrate108to promote TR at an interface between the first back side dielectric layer120aand the substrate108. Further, a top surface of the first back side dielectric layer120ais rough at least at the periodic pattern2302(see, e.g.,FIG.44). The first back side dielectric layer120amay, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). Collectively, the first back side dielectric layer120aand the substrate108define a diffuser122configured to scatter external radiation114exat the periodic pattern2302(see, e.g.,FIG.44). Further, a portion of the first back side dielectric layer120ain the intra-pixel isolation trench4402defines an intra-pixel trench isolation structure1202. The intra-pixel trench isolation structure1202may, for example, have a top layout as illustrated at any ofFIGS.13A-13Cor may have some other suitable top layout. As illustrated by the cross-sectional view4600ofFIG.46, a top surface of the first back side dielectric layer120ais flattened. Further, the first back side dielectric layer120ais etched back to reduce the thickness Tfbdof the first back side dielectric layer120aat top and bottom surfaces of the first back side dielectric layer120a. The flattening may, for example, be performed by a CMP and/or some other suitable planarization process. As illustrated by the cross-sectional views4700,4800A,4800B,4900,5000ofFIGS.47,48A,48B,49, and50, the acts atFIGS.26,27A,27B,28, and29are performed. AtFIG.47, the first back side dielectric layer120aand the substrate108are patterned to define an inter-pixel isolation trench2602as described with regard toFIG.26. The inter-pixel isolation trench2602may, for example, have the same top layout as the inter-pixel trench isolation structure102in any ofFIGS.13A-13Cor some other suitable top layout. AtFIGS.48A and48B, a dielectric liner layer112and a low-transmission layer104are deposited filling the inter-pixel isolation trench2602(see, e.g.,FIG.47) as described respectively with regard toFIGS.27A and27B. Collectively, the low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102. The inter-pixel trench isolation structure102may, for example, have a top layout as in any ofFIGS.13A-13Cor some other suitable top layout. AtFIG.49, a top surface of the low-transmission layer104is recessed to uncover the first back side dielectric layer120aas described with regard toFIG.28. AtFIG.50, a second back side dielectric layer120b, a spacer layer124, and micro lenses126are formed as described with regard toFIG.29. WhileFIGS.44-47,48A,48B,49, and50are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.44-47,48A,48B,49, and50are not limited to the method but rather may stand alone separate of the method. WhileFIGS.44-47,48A,48B,49, and50are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.44-47,48A,48B,49, and50illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. For example, the acts atFIGS.31-33,34A,34B,35, and36may instead be performed in place of the acts atFIGS.47,48A,48B,49and50. With reference toFIG.51, a block diagram5100of some embodiments of the method ofFIGS.44-47,48A,48B,49, and50is provided. At5102, a photodetector is formed in a substrate from a front side of the substrate. See, for example,FIGS.44and21. At5104, an interconnect structure is formed covering and electrically coupled to the photodetector on the front side of the substrate. See, for example,FIGS.44and22. At5106, a back side of the substrate is patterned to form a periodic pattern overlying the photodetector. See, for example,FIGS.44and23. At5108, the back side of the substrate is patterned to form an intra-pixel isolation trench surrounding the photodetector. See, for example,FIG.44. At5110, a first back side dielectric layer is deposited covering the back side of the substrate and filling the intra-pixel isolation trench. See, for example,FIG.45. At5112, a top surface of the first back side dielectric layer is flattened and etched back. See, for example,FIG.46. At5114, the first back side dielectric layer and the back side of the substrate are patterned to form an inter-pixel isolation trench surrounding the intra-pixel trench isolation trench along a boundary of a pixel at which the photodetector is located. See, for example,FIG.47. At5116, a dielectric liner layer is deposited lining and partially filling the inter-pixel isolation trench. See, for example,FIGS.48A and48B. At5118, a low-transmission layer is deposited filling the inter-pixel isolation trench over the dielectric liner layer and covering the first back side dielectric layer. See, for example,FIGS.48A and48B. At5120, a top surface of the low-transmission layer is recessed to uncover the first back side dielectric layer. See, for example,FIG.49. At5122, a second back side dielectric layer and a spacer layer are deposited covering the first back side dielectric layer and the low-transmission layer. See, for example,FIG.50. At5124, a micro lens is formed covering the photodetector over the spacer layer. See, for example,FIG.50. While the block diagram5100ofFIG.51is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. With reference toFIGS.52-54,55A,55B, and56-58, a series of cross-sectional views5200-5400,5500A,5500B, and5600-5800of some alternative embodiments of the method ofFIGS.21-26,27A,27B,28, and29is provided in which the image sensor is FSI. The method may, for example, be employed to form the image sensor in any ofFIGS.18and20and other suitable image sensors. As illustrated by the cross-sectional view5200ofFIG.52, the acts atFIGS.23-25are performed. A back side108bof a substrate108is patterned to form a periodic pattern at a pixel106as described with regard toFIG.23. A first back side dielectric layer120ais deposited covering the back side108bof the substrate108and the periodic pattern as described with regard toFIG.24. Collectively, the first back side dielectric layer120aand the substrate108define a diffuser122at the periodic pattern. A top surface of the first back side dielectric layer120ais flattened as described with regard toFIG.25. As illustrated by the cross-sectional view5300ofFIG.53, the substrate108is flipped so a front side108fof the substrate108overlies the back side108bof the substrate108. Further, a mask layer5302is deposited covering the front side108fof the substrate108. The mask layer5302may, for example, be or comprise silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. As illustrated by the cross-sectional views5400,5500A,5500B,5600ofFIGS.54,55A,55B, and56, the acts atFIGS.26,27A,27B, and28are performed. AtFIG.54, the mask layer5302and the substrate108are patterned to define an inter-pixel isolation trench2602as described with regard toFIG.26. AtFIGS.55A and55B, a dielectric liner layer112and a low-transmission layer104are deposited filling the inter-pixel isolation trench2602(see, e.g.,FIG.54) as respectively described with regard toFIGS.27A and27B. Collectively, the low-transmission layer104and the dielectric liner layer112define an inter-pixel trench isolation structure102. AtFIG.56, a top surface of the low-transmission layer104is recessed to uncover the mask layer5302as described with regard toFIG.28. Further, atFIG.56, the mask layer5302is removed. In alternative embodiments, the mask layer5302persists after the acts atFIG.56. As illustrated by the cross-sectional view5700ofFIG.57, a photodetector110is formed in the substrate108surrounded by the inter-pixel trench isolation structure102. The photodetector110may, for example, be formed as described with regard toFIG.21. As illustrated by the cross-sectional view5800ofFIG.58, a front side dielectric structure118is formed covering the photodetector110and the inter-pixel trench isolation structure102on the front side108fof the substrate108. Further, an interconnect structure1702is formed covering and electrically coupled to the photodetector110while forming the front side dielectric structure118. The interconnect structure1702comprises a plurality of contacts1710, a plurality of wires1712, and a plurality of vias1714stacked in the front side dielectric structure118. Also illustrated by the cross-sectional view5800ofFIG.58, a spacer layer124is deposited over the front side dielectric structure118and the interconnect structure1702. Further, micro lenses126are formed over the spacer layer124. The spacer layer124may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). WhileFIGS.52-54,55A,55B, and56-58are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.52-54,55A,55B, and56-58are not limited to the method but rather may stand alone separate of the method. WhileFIGS.52-54,55A,55B, and56-58are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.52-54,55A,55B, and56-58illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.59, a block diagram5900of some embodiments of the method ofFIGS.52-54,55A,55B, and56-58is provided. At5902, a back side of a substrate is patterned to form a periodic pattern at a pixel. See, for example,FIGS.52and23. At5904, a first back side dielectric layer is deposited covering the back side of the substrate and the periodic pattern. See, for example,FIGS.52and24. At5906, a top surface of the first back side dielectric layer is flattened and etched back. See, for example,FIGS.52and25. At5908, a mask layer is deposited covering a front side of the substrate. See, for example,FIG.53. At5910, the mask layer and the substrate are patterned to form an inter-pixel isolation trench surrounding the pixel along a boundary of the pixel. See, for example,FIG.54. At5912, a dielectric liner layer is deposited lining and partially filling the inter-pixel isolation trench. See, for example,FIGS.55A and55B. At5914, a low-transmission layer is deposited filling the inter-pixel isolation trench over the dielectric liner layer and covering the mask layer. See, for example,FIGS.55A and55B. At5916, a top surface of the low-transmission layer is recessed to uncover the mask layer. See, for example,FIG.56. At5918, the mask layer is removed. See, for example,FIG.56. At5920, a photodetector is formed in the substrate at the pixel. See, for example,FIG.57. At5922, an interconnect structure is formed covering and electrically coupled to the photodetector on the front side of the substrate. See, for example,FIG.58. At5924, a spacer layer is deposited covering the interconnect structure. See, for example,FIG.58. At5926, a micro lens is formed covering the photodetector. See, for example,FIG.58. While the block diagram5900ofFIG.59is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. In some embodiments, the present disclosure provides an image sensor including: a substrate; a pixel including a photodetector, wherein the photodetector is in the substrate; and an outer trench isolation structure extending into the substrate, wherein the outer trench isolation structure has a pair of outer isolation segments respectively on opposite sides of the photodetector at a boundary of the pixel, wherein the outer trench isolation structure includes a low-transmission layer, and wherein the low-transmission layer blocks incident radiation regardless of incident angle. In some embodiments, the low-transmission layer is metal and is reflective of the incident radiation. In some embodiments, the low-transmission layer is metal and is absorptive of the incident radiation. In some embodiments, the outer trench isolation structure includes a dielectric liner layer separating the low-transmission layer from the substrate, wherein the dielectric liner layer has a lower refractive index than the substrate. In some embodiments, a thickness of the dielectric liner layer is greater than about 100 nanometers. In some embodiments, the image sensor further includes an inner trench isolation structure including a pair of inner isolation segments respectively on the opposite sides of the photodetector, wherein the inner trench isolation structure is between the outer isolation segments and includes a dielectric having a lower refractive index than the substrate. In some embodiments, the outer trench isolations structure extends in a closed path along the boundary of the pixel to completely surround the pixel. In some embodiments, the low-transmission layer has optical transmission less than about 10%. In some embodiments, the present disclosure provides another image sensor including: a substrate; an array of pixels in a plurality of rows and a plurality of columns on the substrate, wherein the pixels include individual photodetectors in the substrate; and an inter-pixel trench isolation structure in the substrate, wherein the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the pixels, to separate the pixels from each other, and wherein the inter-pixel trench isolation structure includes a metal layer. In some embodiments, the metal layer includes copper and/or aluminum. In some embodiments, the metal layer includes tungsten, titanium nitride, tantalum nitride, or any combination of the foregoing. In some embodiments, the inter-pixel trench isolation structure is configured to reflect radiation incident on a sidewall of the inter-pixel trench isolation structure at any angle. In some embodiments, the image sensor further includes an intra-pixel trench isolation structure including a plurality of ring-shaped trench isolation segments, wherein the ring-shaped trench isolation segments are individual to the pixels and are surrounded by the inter-pixel trench isolation structure at the individual pixels. In some embodiments, the intra-pixel trench isolation structure is configured to reflect radiation incident on a sidewall of the intra-pixel trench isolation structure at an angle greater than about 20 degrees, but not less than about 20 degrees. In some embodiments, the present disclosure provides a method for forming an image sensor, the method including: forming a pixel on a substrate and including a photodetector in the substrate; patterning the substrate to form an outer trench, wherein the outer trench surrounds the photodetector along a boundary of the pixel and has a pair of outer isolation segments respectively on opposite sides of the photodetector; and depositing a low-transmission layer covering the substrate and filling the outer trench, wherein the low-transmission layer blocks incident radiation regardless of incident angle. In some embodiments, the method includes recessing a top surface of the low-transmission layer to localize the low-transmission layer to the outer trench. incident radiation regardless of incident angle. In some embodiments, the method includes depositing a dielectric liner layer lining the outer trench, wherein the low-transmission layer is deposited over the dielectric liner layer. incident radiation regardless of incident angle. In some embodiments, the method includes the dielectric liner layer is configured for TR at a sidewall of the dielectric liner layer in the outer trench. In some embodiments, the method further includes: patterning the substrate to form an inner trench, wherein the inner trench has a pair of inner isolation segments respectively on the opposite sides of the photodetector, and wherein the outer trench surrounds the inner trench; and depositing a dielectric layer filling the inner trench before the patterning to form the outer trench. In some embodiments, the method further includes: patterning the substrate to form a periodic structure overlying the photodetector; depositing a dielectric layer covering the substrate and having a bottom surface conforming to the periodic structure, wherein the dielectric layer has a higher refractive index than the substrate; and flattening a top surface of the dielectric layer before the patterning to form the outer trench. In some embodiments, the present disclosure provides another method for forming an image sensor, the method including: forming a pixel including a photodetector in a substrate; patterning the substrate to form an inner trench, wherein the inner trench has a pair of inner trench segments between which the photodetector is sandwiched; forming a dielectric layer filling the inner trench; patterning the substrate and the dielectric layer to form an outer trench, wherein the outer trench surrounds the photodetector along a boundary of the pixel and has a pair of outer trench segments respectively on opposite sides of the photodetector and between which the inner trench segments are sandwiched; depositing a low-transmission layer covering the substrate and filling the outer trench, wherein the low-transmission layer blocks incident radiation regardless of incident angle; and performing a planarization into the low-transmission layer, wherein a top surface of the low-transmission layer is level with a top surface of the dielectric layer and is elevated relative to a top surface of the substrate upon completion of the planarization. In some embodiments, the method further includes depositing a dielectric liner layer lining the outer trench, wherein the low-transmission layer is deposited over the dielectric liner layer. In some embodiments, the dielectric liner layer is configured for total internal reflection at a sidewall of the dielectric liner layer in the outer trench. In some embodiments, the low-transmission layer has a transmission that is low compared to that of the dielectric liner layer. In some embodiments, the planarization is further performed into the dielectric liner layer, wherein a top surface of the dielectric liner layer is level with the top surface of the dielectric layer and the top surface of the low-transmission layer upon completion of the planarization. In some embodiments, the method further includes: patterning the substrate to form a periodic structure overlying the photodetector, wherein the dielectric layer is further formed covering the substrate and having a bottom surface conforming to the periodic structure, and wherein the dielectric layer has a higher refractive index than the substrate; and flattening the top surface of the dielectric layer before the patterning to form the outer trench. In some embodiments, the photodetector includes a first contact region, a pair of second contact regions, and a guard ring in the substrate, wherein the first contact region has a first doping type, wherein the pair of second contact regions have a second doping type opposite the first doping type and are respectively on opposite sides of the first contact region, wherein the guard ring separates the first contact region from the second contact regions, wherein the periodic structure has a width beginning at a first location and ending at a second location, and wherein the first and second locations respectively and directly overlie the second contact regions. In some embodiments, the present disclosure provides another method for forming an image sensor, the method including: forming a pixel including a photodetector in a substrate; performing a first etch into the substrate to form a recess with a saw-toothed profile overlying the photodetector; performing a second etch into the substrate to form a first trench, wherein the first trench extends in a first closed path to surround the pixel; depositing a dielectric layer filling the recess and the first trench; performing a third etch into the substrate and the dielectric layer to form a second trench, wherein the second trench extends along a boundary of the pixel in a second closed path to surround the first trench; depositing a metal layer covering the substrate and filling the second trench, wherein the metal layer blocks incident radiation; and recessing the metal layer to remove portions of the metal layer outside the second trench, wherein the recessing includes a planarization into the metal layer, and wherein a top surface of the metal layer is level with a top surface of the dielectric layer and is elevated relative to a top surface of the substrate upon completion of the planarization; wherein a height of the first trench is substantially equal to a height of the substrate. In some embodiments, the height of the first trench is equal to the height of the substrate. In some embodiments, the substrate includes silicon, wherein the metal layer directly contacts silicon of the substrate in the second trench. In some embodiments, the method further includes forming an interconnect structure covering and electrically coupled to the pixel, wherein the interconnect structure is on a frontside of the substrate; wherein the third etch is performed into a backside of the substrate, opposite the frontside of the substrate. In some embodiments, the metal layer is absorptive of the incident radiation. In some embodiments, the first trench has a pair of first trench segments between which the photodetector is sandwiched, wherein the second trench has a pair of second trench segments respectively on opposite sides of the photodetector and between which the first trench segments are sandwiched. In some embodiments, the dielectric layer has a higher refractive index than the substrate and directly contacts the substrate in the first trench. In some embodiments, the present disclosure provides another A method for forming an image sensor, the method including: forming a pixel including a photodetector in a substrate; patterning the substrate to form a first trench surrounding the photodetector with a pair of first-trench segments between which the photodetector is sandwiched; depositing a dielectric layer filling the first trench and covering the pixel; patterning the substrate to form a second trench surrounding the photodetector with a pair of second-trench segments between which the first-trench segments are sandwiched, wherein the patterning to form the second trench is performed into both the dielectric layer and the substrate; depositing a liner layer lining the second trench; and depositing a metal layer filling the second trench over the liner layer and covering the dielectric layer; wherein the first and second trenches extend through the substrate, from top to bottom, wherein the metal layer is more absorptive of incident radiation than the dielectric layer, and wherein a top surface of the liner layer is level with a top surface of the dielectric layer, and is elevated relative to a top surface of the substrate, upon completion of the depositing of the liner layer. In some embodiments, the dielectric layer has a higher refractive index than the substrate and directly contacts the substrate in the first trench. In some embodiments, the method further includes: patterning the substrate to form a diffuser structure overlying the photodetector, wherein the dielectric layer is further deposited covering the diffuser structure; and planarizing the dielectric layer to flatten a surface of the dielectric layer facing away from the substrate. In some embodiments, the method further includes performing a planarization into the metal layer, wherein a top surface of the metal layer is level with the top surface of the dielectric layer, and is elevated relative to the top surface of the substrate, upon completion of the planarization. In some embodiments, the method further includes depositing a second dielectric layer covering and directly contacting the top surface of the dielectric layer, a top surface of the metal layer, and the top surface of the liner layer, wherein the second dielectric layer has a planar profile along an entire width of the pixel. In some embodiments, a height of the dielectric layer is equal to a combined height of the metal layer and the liner layer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 117,988 |
11862655 | MODE FOR CARRYING OUT THE INVENTION In the following, some embodiments of the disclosure are described in detail with reference to the drawings. It is to be noted that description is given in the following order.1. First Embodiment (Solid-state imaging device; an example in which a through electrode is made of a semiconductor and a separation groove on the periphery of the through electrode has a gap)2. Second Embodiment (Solid-state imaging device; an example in which the through electrode is made of a metal and the separation groove on the periphery of the through electrode has a gap)3. Modification Example 1 (An example in which a thermally-oxidized film is provided on an outer side surface of the separation groove)4. Third Embodiment (Solid-state imaging device; an example in which the through electrode is made of a semiconductor and the separation groove on the periphery of the through electrode is filled with a dielectric layer)5. Fourth Embodiment (Solid-state imaging device; an example in which the through electrode is made of a metal and the separation groove on the periphery of the through electrode is filled with the dielectric layer)6. Modification Example 2 (An example in which a thermally-oxidized film is provided on the outer side surface of the separation groove)7. Overall Configuration Example of Solid-state Imaging Unit8. Application Example (An example of an electronic apparatus) 1. First Embodiment FIG.1illustrates a sectional configuration of a solid-state imaging device10according to a first embodiment of the disclosure. The solid-state imaging device10may configure, for example, a pixel section as an imaging pixel region in a solid-state imaging unit (to be described later) such as a CMOS image sensor used in electronic apparatuses such as digital still cameras and video cameras. The solid-state imaging device10may be of, for example, a so-called longitudinal spectroscopic type in which one photoelectric conversion element20and two photodiodes PD1and PD2are stacked along a thickness direction of a semiconductor substrate30. The photoelectric conversion element20is provided on the side of a first surface (rear surface)30A of the semiconductor substrate30. The photodiodes PD1and PD2are so provided in the semiconductor substrate30as to be stacked along the thickness direction of the semiconductor substrate30. The photoelectric conversion element20and the photodiodes PD1and PD2selectively detect light in wavelength ranges different from one another to perform photoelectric conversion on the thus-detected light. More specifically, the photoelectric conversion element20obtains a color signal of green (G). The photodiodes PD1and PD2respectively obtain color signals of blue (B) and red (R) by a difference in absorption coefficient. This allows the solid-state imaging device10to obtain a plurality of kinds of color signals in one pixel without using a color filter. It is to be noted that, in the embodiment, description is given of a case where electrons of electron-hole pairs generated by photoelectric conversion are read out as signal charges (a case where an N-type semiconductor region serves as a photoelectric conversion layer). Moreover, in the drawing, “+ (plus)” attached to “P” and “N” indicates that P-type or N-type impurity concentration is high, and “++” indicates that P-type or N-type impurity concentration is higher than impurity concentration in “+”. For example, floating diffusions (floating diffusion layers) FD1, FD2, and FD3, a vertical transistor (transfer transistor) Tr1, a transfer transistor Tr2, an amplifier transistor (modulator) AMP, a reset transistor RST, and a multi-layered wiring40may be provided on a second surface (front surface)30B of the semiconductor substrate30. The multi-layered wiring40may have, for example, a configuration in which wiring layers41,42, and43are stacked in an insulating film44. It is to be noted that, in the drawings, the sides of the first surface30A and the second surface30B of the semiconductor substrate30are respectively referred to as light-entering side S1and wiring layer side S2. The photoelectric conversion element20may have, for example, a configuration in which a lower transparent electrode21, a photoelectric conversion film22, and an upper transparent electrode23are stacked in this order from the side of the first surface30A of the semiconductor substrate30. The transparent electrode21is separated for each photoelectric conversion element20. The photoelectric conversion film22and the transparent electrode23are provided as continuous layers shared by a plurality of photoelectric conversion elements20. For example, a film24having a fixed charge, a dielectric layer25having insulation properties, and an interlayer insulating film26may be provided between the first surface30A of the semiconductor substrate30and the transparent electrode21. A protective film27is provided on the transparent electrode23. An optical member such as a planarization film and an on-chip lens (none of which is illustrated) are provided above the protective film27. A through electrode50is provided between the first surface30A and the second surface30B of the semiconductor substrate30. The photoelectric conversion element20is coupled to a gate Gamp of the amplifier transistor AMP and the floating diffusion FD3via the through electrode50. This allows the solid-state imaging device10to favorably transfer, to the side of the second surface30B of the semiconductor substrate30via the through electrode50, charges generated in the photoelectric conversion element20on the side of the first surface30A of the semiconductor substrate30, thereby enhancing characteristics. The through electrode50has a function as a connector between the photoelectric conversion element20and the gate Gamp of the amplifier transistor AMP and between the photoelectric conversion element20and the floating diffusion FD3, as well as serves as a transmission path for charges (here, electrons) generated in the photoelectric conversion element20. A lower end of the through electrode50may be coupled to, for example, a connection section41A in the wiring layer41of the multi-layered wiring40via a lower first contact51. The connection section41A and the gate Gamp of the amplifier transistor AMP are coupled to each other via a lower second contact52. The connection section41A and the floating diffusion FD3are coupled to each other via a lower third contact53. An upper end of the through electrode50may be coupled to, for example, the lower transparent electrode21via an upper contact54. FIG.2illustrates a planar configuration, viewed from the side of the second surface30B of the semiconductor substrate30, of an example of the solid-state imaging device10in which a plurality of (for example, four inFIG.2) photoelectric conversion elements20are arranged in two rows by two columns. The through electrode50may be preferably provided for each of the plurality of photoelectric conversion elements20. In other words, as the lower transparent electrode21of the photoelectric conversion element20is separated for each of the plurality of photoelectric conversion elements20, the through electrode50is also provided for each of the plurality of photoelectric conversion elements20. As illustrated inFIGS.1and2, a reset gate Grst of the reset transistor RST may be preferably disposed adjacent to the floating diffusion FD3. This makes it possible to reset charges accumulated in the floating diffusion FD3by the reset transistor RST. It is to be noted thatFIG.2illustrates only the amplifier transistor AMP and the reset transistor RST that process charges from the photoelectric conversion element20. The transfer transistors Tr1and Tr2relating to the photodiodes PD1and PD2are not illustrated inFIG.2, but are appropriately disposed in an unoccupied region. The through electrode50illustrated inFIG.1penetrates the semiconductor substrate30, as well as is separated from the semiconductor substrate30by a separation groove60. The through electrode50may be made of, for example, a same semiconductor as a semiconductor of the semiconductor substrate30, for example silicon (Si), and may preferably have a resistance value reduced by doping with an N-type or P-type impurity (for example, P+ inFIG.1). Moreover, high-concentration impurity regions (for example, P++ inFIG.1) may be preferably provided in the upper end and the lower end of the through electrode50to further reduce connection resistance with the upper contact54and connection resistance with the lower first contact51. As illustrated inFIG.1, an outer side surface61, an inner side surface62, and a bottom surface63of the separation groove60may be covered with the dielectric layer25having insulation properties. The dielectric layer25may include, for example, an outer dielectric layer25A covering the outer side surface61of the separation groove60, and an inner dielectric layer25B covering the inner side surface62of the separation groove60. The outer dielectric layer25A and the inner dielectric layer25B may be preferably spaced with a gap70between. In other words, the separation groove60may have a ring shape or a circular shape, and the gap70may have a ring shape or a circular shape that is concentric with the separation groove60. This makes it possible to reduce capacitance generated between the through electrode50and the semiconductor substrate30, thereby enhancing conversion efficiency as well as suppressing lag (persistence). In the following, description is given of this. As described above, the through electrode50is made of a conductive material such as P+ silicon, and the dielectric layer25is provided between the through electrode50and the semiconductor substrate30. Since the through electrode50penetrates the semiconductor substrate30, and is coupled to the amplifier transistor AMP and the floating diffusion FD3, it may be desirable to reduce capacitance generated between the through electrode50and the semiconductor substrate30. The following three measures are considered to reduce the capacitance. A first one of the measures is to reduce area of a side wall of the through electrode50. A second one of the measures is to increase a distance d between the through electrode50and the semiconductor substrate30. A third one of the measures is to decrease a dielectric constant of an insulator between the through electrode50and the semiconductor substrate30. Reducing the area of the side wall of the through electrode50as the first measure allows for reduction in a thickness of the semiconductor substrate30or reduction in a diameter of the through electrode50. However, this may cause reduction in regions of the photodiodes PD1and PD2, or an increase in difficulty level of a forming process of the semiconductor substrate30. Increasing the distance d between the through electrode50and the semiconductor substrate30as the second measure is a relatively easy measure, but may lead to an increase in device area. In the embodiment, the gap70is provided in the separation groove60so as to take the foregoing third measure, i.e., to reduce the dielectric constant of the insulator between the through electrode50and the semiconductor substrate30. Although gas such as hydrogen and nitrogen is present in the gap70, for example, the dielectric constant of the gas may be lower than a dielectric constant of a dielectric of a solid such as a TEOS (Tetraethyl orthosilicate) film, and may be close to a dielectric constant of vacuum. This makes it possible to remarkably reduce capacitance between the through electrode50and the semiconductor substrate30. It is to be noted that variation in size of the gap70may be preferably as small as possible in the solid-state imaging device10or in a wafer, and may be preferably, for example, within plus or minus 10% or less. A reason for this is that the capacitance between the through electrode50and the semiconductor substrate30is sensitive to the size of the gap70. Moreover, in the solid-state imaging device10, as illustrated inFIG.1, an impurity region (P+ inFIG.1) of a same conductive type (N-type or P-type) as a conductive type of the through electrode50may be preferably provided on the outer side surface61of the separation groove60in the semiconductor substrate30. Further, the film24having the fixed charge may be preferably provided on the outer side surface61, the inner side surface62, and the bottom surface63of the separation groove60, and the first surface30A of the semiconductor substrate30. More specifically, for example, a P-type impurity region (P+ inFIG.1) as well as a film having a negative fixed charge as the film24having the fixed charge may be preferably provided on the outer side surface61of the separation groove60in the semiconductor substrate30. This allows for reduction in dark current. In the followings, description is given of this. In the longitudinal stereoscopic type solid-state imaging device10, the through electrode50and the separation groove60are provided for each of the photoelectric conversion elements20while being in proximity to the photodiodes PD1and PD2in the semiconductor substrate30. Surfaces of the through electrode50and the separation groove60are unlike a surface of the semiconductor substrate30, and are processed by dry etching or other processing, which generally have a large number of defect levels. This may increase dark currents and white spots of the photodiodes PD1and PD2adjacent to the through electrode50and the separation groove60. Here, to reduce the dark currents or the white spots, the P-type impurity region (P+ inFIG.1) is provided on the outer side surface61of the separation groove60in the semiconductor substrate30, and the film having the negative fixed charge is further provided as the film24having the fixed charge. An hole accumulation layer is formed on the outer side surface61of the separation groove60by an electric field induced by the film24having the negative fixed charge. The hole accumulation layer suppresses the generation of electrons from the outer side surface61of the separation groove60. Moreover, even if charges (electrons) are generated from the outer side surface61of the separation groove60, the thus-generated electrons disappear in the hole accumulation layer during diffusion of the electrons, and accordingly, the dark currents are reduced. In the following, description is given of configurations and materials of respective components. The photoelectric conversion element20may be configured to perform photoelectric conversion on green light corresponding to a part or an entirety of a wavelength range of 495 nm to 570 nm both inclusive. The transparent electrodes21and23may each include, for example, a conductive film having light transparency, and may be made of, for example, ITO (indium tin oxide). The photoelectric conversion film22is an organic film made of an organic photoelectric conversion material that photoelectrically converts light in a selective wavelength range while allowing light in other wavelength ranges to pass therethrough. The photoelectric conversion film22may be made of, for example, an organic photoelectric conversion material containing a rhodamine-based dye, a merocyanine-based dye, quinacridone, or any other dye. It is to be noted that the photoelectric conversion element20may be provided with, in addition to the transparent electrodes21and23and the photoelectric conversion film22, other unillustrated layers such as a base layer, an electron block layer, and a buffer layer. The film24having the fixed charge may be a film having a positive fixed charge or a film having a negative fixed charge. Non-limiting examples of a material of the film having the negative fixed charge may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. Moreover, non-limiting examples of the material other than the foregoing materials may include lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, an aluminum nitride film, a hafnium oxynitride film, and an aluminum oxynitride film. The film24having the fixed charge may have a configuration in which two or more kinds of films are stacked. For example, in the case of the film having the negative fixed charge, such a configuration makes it possible to further enhance a function as the hole accumulation layer. Examples of a material of the dielectric layer25may include, but not specifically limited to, a silicon oxide film, TEOS, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film26may be configured of, for example, a silicon oxide film. The protective film27may be configured of, for example, a silicon nitride film. The semiconductor substrate30may be configured of, for example, an n-type silicon (Si) substrate, and may have a p-well31in a predetermined region. The vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, the reset transistor RST, and other components that are described above are provided on the second surface30B of the p-well31. Moreover, a peripheral circuit (not illustrated) including, for example but not limited to, a logic circuit is provided on the periphery of the semiconductor substrate30. The photodiodes PD1and PD2each have PN junction in a predetermined region of the semiconductor substrate30. The photodiodes PD1and PD2allow for dispersion of light toward a longitudinal direction with use of a difference in wavelength of light absorbed according to a light-entering depth in a silicon substrate. The photodiode PD1selectively detects blue light to accumulate signal charges corresponding to blue, and is disposed at a depth that allows blue light to be photoelectrically converted effectively. The photodiode PD2selectively detects red light to accumulate signal charges corresponding to red, and is disposed at a depth that allows red light to be photoelectrically converted effectively. It is to be noted that blue (B) is a color corresponding to a wavelength range of, for example, 450 nm to 495 nm both inclusive, and red (R) is a color corresponding to a wavelength range of, for example, 620 nm to 750 nm both inclusive. It is only necessary for the respective photodiodes PD1and PD2to enable to detect light in a part or an entirety of the respective wavelength ranges. The photodiode PD1may include, for example, a P+ region serving as a hole accumulation layer and an N region serving as an electron accumulation layer. The photodiode PD2may include, for example, a P+ region serving as a hole accumulation layer and an N region serving as an electron accumulation layer (i.e., may have a P-N-P stacking configuration). The N region of the photodiode PD1is coupled to the vertical transistor Tr1. The P+ region of the photodiode PD1is bent along the vertical transistor Tr1to be continuous with the P+ region of the photodiode PD2. The vertical transistor Tr1is a transfer transistor that transfers, to the floating diffusion FD1, signal charges (electrons in the embodiment) corresponding to blue that are generated and accumulated in the photodiode PD1. Since the photodiode PD1is formed at a position deep from the second surface30B of the semiconductor substrate30, the transfer transistor of the photodiode PD1may be preferably configured of the vertical transistor Tr1. The transfer transistor Tr2transfers, to the floating diffusion FD2, signal charges (electrons in the embodiment) corresponding to red that are generated and accumulated in the photodiode PD2, and may be configured of, for example, a MOS transistor. The amplifier transistor AMP is a modulator that modulates an amount of charges generated in the photoelectric conversion element20into a voltage, and may be configured of, for example, a MOS transistor. The reset transistor RST is configured to reset charges transferred from the photoelectric conversion element20to the floating diffusion FD3, and may be configured of, for example, a MOS transistor. The lower first to third contacts51to53and the upper contact54may be made of, for example, a doped silicon material such as PDAS (Phosphorus Doped Amorphous Silicon), or a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum. The solid-state imaging device10may be manufactured, for example, as follows. FIGS.3to8illustrate a method of manufacturing the solid-state imaging device10in the order of procedure. First, as illustrated inFIG.3, for example, the p-well31may be formed as a well of a first conductive type in the semiconductor substrate30, and the photodiodes PD1and PD2of a second conductive type (for example, N-type) may be formed in the P-well31. A P+ region may be formed in proximity to the first surface30A of the semiconductor substrate30. As illustrated inFIG.3as well, an impurity region (P+ region) may be so formed in a region where the through electrode50and the separation groove60are to be formed as to penetrate from the first surface30A to the second surface30B of the semiconductor substrate30. Moreover, high-concentration impurity regions (P++ regions) may be formed in regions where the upper end and the lower end of the through electrode50are to be formed. As illustrated inFIG.3as well, N+ regions that are to serve as the floating diffusions FD1to FD3may be formed along the second surface30B of the semiconductor substrate30, and thereafter, the gate insulating film32, and a gate wiring33including gates of the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST may be formed on the second surface30B of the semiconductor substrate30. The vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST may be thus formed. Moreover, the lower first to third contacts51to53and the multi-layered wiring40including the wiring layers41to43including the connection section41A, and the insulating film44may be formed on the second surface30B of the semiconductor substrate30. An example used as a base of the semiconductor substrate30may be a SOI (Silicon on Insulator) substrate in which the semiconductor substrate30, an embedded oxide film (not illustrated) and a holding substrate (not illustrated) are stacked. The embedded oxide film and the holding substrate, which are not illustrated inFIG.3, may be bonded to the first surface30A of the semiconductor substrate30. Annealing treatment may be performed after ion implantation. Subsequently, as illustrated inFIG.4, a support substrate (not illustrated) or any other semiconductor base may be bonded to the side of the second surface30B (the multi-layered wiring40) of the semiconductor substrate30, and the semiconductor substrate30may be vertically reversed. Next, the semiconductor substrate30may be separated from the embedded oxide film and the holding substrate of the SOI substrate to expose the first surface30A of the semiconductor substrate30. The foregoing processes may be carried out by techniques used in a normal CMOS process such as ion implantation and CVD (Chemical Vapor Deposition). Thereafter, as illustrated inFIG.5, the semiconductor substrate30may be processed from the side of the first surface30A by, for example, dry etching to form the circular or ring-shaped separation groove60. As indicated by an arrow D60A inFIG.5, a depth of the separation groove60may be preferably deep enough to penetrate the semiconductor substrate30from the first surface30A to the second surface30B and reach the gate insulating film32. Moreover, in order to further enhance an insulating effect on the bottom surface63of the separation groove60, as indicated by an arrow D60B inFIG.5, the separation groove60may preferably reach the insulating film44of the multi-layered wiring40through the semiconductor substrate30and the gate insulating film32.FIG.5illustrates a case where the separation groove60penetrates the semiconductor substrate30and the gate insulating film32. After forming the separation groove60, as illustrated inFIG.6, for example, the film24having the negative fixed charge may be formed on the outer side surface61, the inner side surface62, and the bottom surface63of the separation groove60, and the first surface30A of the semiconductor substrate30. As the film24having the negative fixed charge, two or more kinds of films may be stacked. This makes it possible to further enhance the function as the hole accumulation layer. After forming the film24having the negative fixed charge, the dielectric layer25including the outer dielectric layer25A and the inner dielectric layer25B may be formed as illustrated inFIG.7. At this occasion, a film thickness and film formation conditions of the dielectric layer25may be appropriately adjusted to form the gap70in the separation groove60between the outer dielectric layer25A and the inner dielectric layer25B. After forming the dielectric layer25and the gap70, as illustrated inFIG.8, the interlayer insulating film26and the upper contact54may be formed, and the upper contact54may be coupled to the upper end of the through electrode50. Thereafter, the lower transparent electrode21, the photoelectric conversion film22, the upper transparent electrode23, and the protective film27may be formed as illustrated inFIG.1. Finally, the optical member such as a planarization film and the on-chip lens (not illustrated) may be provided. Thus, the solid-state imaging device10illustrated inFIG.10is completed. In the solid-state imaging device10, when light enters the photoelectric conversion element20via the on-chip lens (not illustrated), the light passes through the photoelectric conversion element20, and the photodiodes PD1and PD2in this order to be respectively photoelectrically converted into color light of green, blue, and red in the course of such passage. In the following, description is given of actions of obtaining signals of respective colors. Obtaining of Green Signal by Photoelectric Conversion Element20 Of light entering the photoelectric conversion element20, green light is first selectively detected (absorbed) and photoelectrically converted by the photoelectric conversion element20. The photoelectric conversion element20is coupled to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3via the through electrode50. Electrons of electron-hole pairs generated in the photoelectric conversion element20are therefore extracted from the side of the transparent electrode21to be transferred to the side of the second surface30B of the semiconductor substrate30via the through electrode50and then accumulated in the floating diffusion FD3. Concurrently with this, an amount of charges generated in the photoelectric conversion element20is modulated into a voltage by the amplifier transistor AMP. Moreover, the reset gate Grst of the reset transistor RST is disposed adjacent to the floating diffusion FD3. The charges accumulated in the floating diffusion FD3are therefore reset by the reset transistor RST. Here, the photoelectric conversion element20is coupled to not only the amplifier transistor AMP but also the floating diffusion FD3via the through electrode50, which makes it possible to easily reset the charges accumulated in the floating diffusion FD3by the reset transistor RST. In a case where the through electrode50and the floating diffusion FD3are not coupled to each other, it is difficult to reset the charges accumulated in the floating diffusion FD3, and a large voltage is therefore applied to draw the charges to the side of the transparent electrode23. This may cause damage to the photoelectric conversion film22. Moreover, since a configuration that allows for resetting in a short time may cause an increase in dark time noise, thereby leading to trade-off, this configuration is difficult. Obtaining Blue Signal and Red Signal by Photodiodes PD1and PD2 Next, of the light having passed through the photoelectric conversion element20, blue light and red light are respectively absorbed and photoelectrically converted by the photodiode PD1and the photodiode PD2in order. In the photodiode PD1, electrons corresponding to the entered blue light are accumulated in the N region of the photodiode PD1, and the thus-accumulated electrons are transferred to the floating diffusion FD1by the vertical transistor Tr1. Similarly, in the photodiode PD2, electrons corresponding to the entered red light are accumulated in the N region of the photodiode PD2, and the thus-accumulated electrons are transferred to the floating diffusion FD2by the transfer transistor Tr2. Thus, in the embodiment, since the photoelectric conversion element20is coupled to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3via the through electrode50, it is possible to favorably transfer, to the side of the second surface30B of the semiconductor substrate30via the through electrode50, charges generated in the photoelectric conversion element20on the side of the first surface30A of the semiconductor substrate30, thereby enhancing characteristics. Moreover, since the through electrode50and the semiconductor substrate30are separated from each other by the separation groove60, the outer dielectric layer25A, the inner dielectric layer25B, and the gap70, it is possible to reduce capacitance generated between the through electrode50and the semiconductor substrate30, thereby further improving characteristics such as conversion efficiency. Further, since the reset gate Grst of the reset transistor RST is disposed adjacent to the floating diffusion FD3, it is possible to easily reset the charges accumulated in the floating diffusion FD3by the reset transistor RST. This makes it possible to reduce damage to the photoelectric conversion film22, thereby improving reliability. Furthermore, this makes it possible to reset the charges in a short time without increasing dark time noise. 2. Second Embodiment FIG.9illustrates a sectional configuration of a solid-state imaging device10A according to a second embodiment of the disclosure. The solid-state imaging device10A may include the through electrode50made of a metal or a conductive material, but otherwise may have similar configurations, workings, and effects to those of the foregoing first embodiment. Accordingly, description is given with similar components denoted by similar reference numerals. As with the first embodiment, the solid-state imaging device10A may be of, for example, a so-called longitudinal spectroscopic type in which one photoelectric conversion element20and two photodiodes PD1and PD2are stacked along the thickness direction of the semiconductor substrate30. The photoelectric conversion element20is provided on the side of the first surface (rear surface)30A of the semiconductor substrate30. The photodiodes PD1and PD2are so provided in the semiconductor substrate30as to be stacked along the thickness direction of the semiconductor substrate30. The photoelectric conversion element20, the photodiodes PD1and PD2, and the semiconductor substrate30may have similar configurations to those of the first embodiment. The floating diffusions FD1to FD3, the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, the reset transistor RST, and the multi-layered wiring40may have similar configurations to those of the first embodiment. As with the first embodiment, the through electrode50is provided between the first surface30A and the second surface30B of the semiconductor substrate30. The photoelectric conversion element20is coupled to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3via the through electrode50. As with the first embodiment, this allows the solid-state imaging device10to favorably transfer, to the side of the second surface30B of the semiconductor substrate30via the through electrode50, charges generated in the photoelectric conversion element20on the side of the first surface30A of the semiconductor substrate30, thereby enhancing characteristics. As with the first embodiment, the floating diffusion FD3is disposed in proximity to the through electrode50. The reset gate Grst of the reset transistor RST may be preferably disposed adjacent to the floating diffusion FD3. This makes it possible to reset charges accumulated in the floating diffusion FD3by the reset transistor RST. In the embodiment, the through electrode50may be made of the metal or the conductive material as described above. This makes it possible to further reduce a resistance value of the through electrode50and to further reduce connection resistance between the through electrode50and the lower first to third contacts51to53and between the through electrode50and the upper contact54. This makes it possible to more favorably transfer, to the side of the second surface30B of the semiconductor substrate30via the through electrode50, charges generated in the photoelectric conversion element20on the side of the first surface30A of the semiconductor substrate30, thereby further enhancing the characteristics. Non-limiting examples of the metal or the conductive material forming the through electrode50may include aluminum, tungsten, titanium, cobalt, hafnium, and tantalum. As with the first embodiment, the separation groove60may be preferably provided between the through electrode50and the semiconductor substrate30. The outer side surface61, the inner side surface62, and the bottom surface63of the separation groove60may be preferably covered with the dielectric layer25having insulation properties. The outer dielectric layer25A covering the outer side surface61of the separation groove and the inner dielectric layer25B covering the inner side surface62of the separation groove60may be preferably spaced with the gap70between. This makes it possible to reduce capacitance generated between the through electrode50and the semiconductor substrate30, thereby enhancing conversion efficiency as well as suppressing lag (persistence). Moreover, in the solid-state imaging device10A, as with the first embodiment, an impurity region (P+ inFIG.9) may be preferably provided on the outer side surface61of the separation groove60in the semiconductor substrate30. Further, the film24having the fixed charge may be preferably provided on the outer side surface61, the inner side surface62, and the bottom surface63of the separation groove60, and the first surface30A of the semiconductor substrate30. More specifically, for example, a P-type impurity region (P+ inFIG.9) as well as a film having a negative fixed charge as the film24having the fixed charge may be preferably provided on the outer side surface61of the separation groove60in the semiconductor substrate30. This allows for reduction in dark current. As with the first embodiment, the film24having the fixed charge may be a film having a positive fixed charge or a film having a negative fixed charge. Non-limiting examples of a material of the film having the negative fixed charge may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. Moreover, non-limiting examples of the material other than the foregoing materials may include lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, an aluminum nitride film, a hafnium oxynitride film, and an aluminum oxynitride film. As with the first embodiment, the film24having the fixed charge may have a configuration in with two or more kinds of films are stacked. For example, in the case of the film having the negative fixed charge, such a configuration makes it possible to further enhance a function as the hole accumulation layer. As with the first embodiment, examples of a material of the dielectric layer25may include, but not specifically limited to, a silicon oxide film, TEOS, a silicon nitride film, and a silicon oxynitride film. As with the first embodiment, the lower first to third contacts51to53and the upper contact54may be made of, for example, a doped silicon material such as PDAS, or a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum. The solid-state imaging device10A may be manufactured, for example, as follows. FIGS.10to18illustrate a method of manufacturing the solid-state imaging device10A in the order of procedure. First, as with the first embodiment, through the process illustrated inFIG.3, for example, the p-well31may be formed as a well of the first conductive type in the semiconductor substrate30, and the photodiodes PD1and PD2of the second conductive type (for example, N-type) may be formed in the p-well31. The P+ region may be formed in proximity to the first surface30A of the semiconductor substrate30. Moreover, as with the first embodiment, through the process illustrated inFIG.3as well, an impurity region (P+ region) may be so formed in a region where the through electrode50and the separation groove60are to be formed as to penetrate from the first surface30A to the second surface30B of the semiconductor substrate30. It is to be noted that, in the embodiment, since the through electrode50is made of the metal or the conductive material, high-concentration impurity regions (P++ regions) in the upper end and the lower end of the through electrode50are unnecessary. As with the first embodiment, through the process illustrated inFIG.3as well, N+ regions that are to serve as the floating diffusions FD1to FD3may be formed on the second surface30B of the semiconductor substrate30, and thereafter, the gate insulating film32, and the gate wiring33including gates of the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST may be formed on the second surface30B of the semiconductor substrate30. The vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST may be thus formed. Moreover, the lower first to third contacts51to53and the multi-layered wiring40including the wiring layers41to43including the connection section41A, and the insulating film44may be formed on the second surface30B of the semiconductor substrate30. As with the first embodiment, an example used as the base of the semiconductor substrate30may be the SOI substrate. Annealing treatment may be performed after ion implantation. Subsequently, as illustrated inFIG.10, a support substrate (not illustrated) or any other semiconductor base may be bonded to the side of the second surface30B (the multi-layered wiring40) of the semiconductor substrate30, and the semiconductor substrate30may be vertically reversed. Next, the semiconductor substrate30may be separated from the embedded oxide film and the holding substrate of the SOI substrate to expose the first surface30A of the semiconductor substrate30. The foregoing processes may be carried out by techniques used in a normal CMOS process such as ion implantation and CVD (Chemical Vapor Deposition). Thereafter, as illustrated inFIG.11, the semiconductor substrate30may be processed from the side of the first surface30A by, for example, dry etching to form the circular or ring-shaped separation groove60that penetrates the semiconductor substrate30. After forming the separation groove60, as illustrated inFIG.12, an insulating film80may be formed on the outer side surface61and the bottom surface63of the separation groove60, and the first surface30A of the semiconductor substrate30. As a material of the insulating film80, TEOS, or a SiO film, a SiN film, or any other film formed by an ALD method may be used. Subsequently, as illustrated inFIG.13, the insulating film80may be recessed by dry etching or any other method. Thereafter, as illustrated inFIG.14, a metal material film50A may be embedded in the separation groove60. After the metal material film50A is embedded, as illustrated inFIG.15, the metal material film50A may be recessed or planarized by dry etching or CMP (Chemical Mechanical Polishing) to form the through electrode50. At this occasion, a thickness of the insulating film80may be reduced in proximity to an entrance of the separation groove60by etching back; therefore, the metal material film50A may be preferably recessed to a depth where the thickness of the insulating film80is secured. This makes it possible to prevent a short circuit between the through electrode50and the semiconductor substrate30. After forming the through electrode50, as illustrated inFIG.16, the insulating film80may be removed. After removing the insulating film80, as illustrated inFIG.17, the film24having, for example, the negative fixed charge may be formed on the outer side surface61, the inner side surface62, and the bottom surface63of the separation groove60, and the first surface30A of the semiconductor substrate30. As the film24having the negative fixed charge, two or more kinds of films may be stacked. This makes it possible to further enhance the function as the hole accumulation layer. After forming the film24having the negative fixed charge, as illustrated inFIG.17as well, the dielectric layer25may be formed. At this occasion, the film thickness and film formation conditions of the dielectric layer25may be appropriately adjusted to form the gap70in the separation groove60. It is to be noted that a surface of the dielectric layer25may be planarized by CMP or any other method. After forming the dielectric layer25and the gap70, as illustrated inFIG.18, the interlayer insulating film26and the upper contact54may be formed, and the upper contact54may be coupled to the upper end of the through electrode50. Thereafter, the lower transparent electrode21, the photoelectric conversion film22, and the upper transparent electrode23, and the protective film27may be formed as illustrated inFIG.9. Finally, the optical member such as a planarization film and the on-chip lens (not illustrated) may be provided. Thus, the solid-state imaging device10A illustrated inFIG.9is completed. In the solid-state imaging device10A, when light enters the photoelectric conversion element20via the on-chip lens (not illustrated), the light passes through the photoelectric conversion element20, and the photodiodes PD1and PD2in this order to be respectively photoelectrically converted into color light of green, blue, and red in the course of such passage, and signals of respective colors are thus obtained in a similar manner to that of the first embodiment. Since the through electrode50is made of the metal or the conductive material here, it is possible to reduce the resistance value of the through electrode50, thereby further improving characteristics. Thus, in the embodiment, the through electrode50is made of the metal or the conductive material, which makes it possible to reduce the resistance value of the through electrode50, thereby further enhancing characteristics. 3. Modification Example 1 FIG.19illustrates a sectional configuration of a solid-state imaging device10B according to Modification Example 1. The solid-state imaging device10B may include a thermal oxidized film34between the dielectric layer25and the through electrode50and between the dielectric layer25and the semiconductor substrate30. The thermally oxidized film34may be made of, for example but not limited to, a silicon oxide film in which silicon in the semiconductor substrate30is thermally oxidized, silicon oxynitride, or a high-dielectric insulating film. Otherwise, the solid-state imaging device10B may have similar configurations, workings, and effects to those of the foregoing first embodiment. Moreover, the solid-state imaging device10B may be manufactured in a similar manner to that of the first embodiment, except that the thermally oxidized film34is provided on the outer side surface61and the inner side surface62of the separation groove60. 4. Third Embodiment FIG.20illustrates a sectional configuration of a solid-state imaging device10C according to a third embodiment of the disclosure. The solid-state imaging device10C is configured to reduce capacitance generated between the through electrode50and the semiconductor substrate30by filling the separation groove60with the dielectric layer25having insulation properties, thereby further improving characteristics such as conversion efficiency. Otherwise, the solid-state imaging device10C may have similar configurations, workings, and effects to those of the foregoing first embodiment. The solid-state imaging device10C may be manufactured, for example, as follows. FIGS.21and22illustrate a method of manufacturing the solid-state imaging device10C in the order of procedure. It is to be noted that same processes as those of the first embodiment are described with reference toFIGS.3to6. First, as with the first embodiment, through the process illustrated inFIG.3, for example, the p-well31may be formed as a well of the first conductive type in the semiconductor substrate30, and the photodiodes PD1and PD2of the second conductive type (for example, N-type) may be formed in the p-well31. The P+ region may be formed in proximity to the first surface30A of the semiconductor substrate30. Moreover, as with the first embodiment, through the process illustrated inFIG.3as well, an impurity region (P+ region) may be so formed in a region where the through electrode50and the separation groove60are to be formed as to penetrate from the first surface30A to the second surface30B of the semiconductor substrate30. Moreover, high-concentration impurity regions (P++ regions) may be formed in regions where the upper end and the lower end of the through electrode50are to be formed. As with the first embodiment, through the process illustrated inFIG.3as well, the N+ regions that are to serve as the floating diffusions FD1to FD3may be formed along the second surface30B of the semiconductor substrate30, and thereafter, the gate insulating film32, and the gate wiring33including the gates of the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST may be formed on the second surface30B of the semiconductor substrate30. The vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST may be thus formed. Moreover, the lower first to third contacts51to53and the multi-layered wiring40including the wiring layers41to43including the connection section41A, and the insulating film44may be formed on the second surface30B of the semiconductor substrate30. As with the first embodiment, an example used as the base of the semiconductor substrate30may be the SOI substrate. Annealing treatment may be performed after ion implantation. Subsequently, as with the first embodiment, through the process illustrated inFIG.4, a support substrate (not illustrated) or any other semiconductor base may be bonded to the side of the second surface30B (the multi-layered wiring40) of the semiconductor substrate30, and the semiconductor substrate30may be vertically reversed. Next, the semiconductor substrate30may be separated from the embedded oxide film and the holding substrate of the SOI substrate to expose the first surface30A of the semiconductor substrate30. The foregoing processes may be carried out by techniques used in a normal CMOS process such as ion implantation and CVD. Thereafter, as with the first embodiment, through the process illustrated inFIG.5, the semiconductor substrate30may be processed from the side of the first surface30A by, for example, dry etching to form the circular or ring-shaped separation groove60. After forming the separation groove60, as with the first embodiment, through the process illustrated inFIG.6, for example, the film24having the negative fixed charge may be formed on the outer side surface61, the inner side surface62, and the bottom surface63of the separation groove60, and the first surface30A of the semiconductor substrate30. As the film24having the negative fixed charge, two or more kinds of films may be stacked. This makes it possible to further enhance the function as the hole accumulation layer. After forming the film24having the negative fixed charge, as illustrated inFIG.21, the separation groove60may be filled with the dielectric layer25. After forming the dielectric layer25, as illustrated inFIG.22, the interlayer insulating film26and the upper contact54may be formed, and the upper contact54may be coupled to the upper end of the through electrode50. Thereafter, the lower transparent electrode21, the photoelectric conversion film22, the upper transparent electrode23, and the protective film27may be formed as illustrated inFIG.20. Finally, the optical member such as a planarization film and the on-chip lens (not illustrated) may be provided. Thus, the solid-state imaging device10C illustrated inFIG.20is completed. 5. Fourth Embodiment FIG.23illustrates a sectional configuration of a solid-state imaging device10D according to a fourth embodiment of the disclosure. The solid-state imaging device10D is configured to reduce capacitance generated between the through electrode50and the semiconductor substrate30by filling the separation groove60with the dielectric layer25having insulation properties, thereby further improving characteristics such as conversion efficiency. Otherwise, the solid-state imaging device10D may have similar configurations, workings, and effects to those of the foregoing second embodiment. As illustrated inFIG.24, the solid-state imaging device10D may be manufactured in a similar manner to that of the second embodiment, except that the separation groove60is filled with the dielectric layer25. 6. Modification Example 2 FIG.25illustrates a sectional configuration of a solid-state imaging device10E according to Modification Example 2. The solid-state imaging device10E may include the thermally oxidized film34, which is similar to that of Modification Example 1, between the dielectric layer25and the through electrode50and between the dielectric layer25and the semiconductor substrate30. As with Modification Example 1, the thermally oxidized film34may be made of, for example but not limited to, a silicon oxide film in which silicon in the semiconductor substrate30is thermally oxidized, silicon oxynitride, or a high-dielectric insulating film. Otherwise, the solid-state imaging device10E may have similar configurations, workings, and effects to those of the foregoing third embodiment. Moreover, the solid-state imaging device10E may be manufactured in a similar manner to that of the third embodiment, except that the thermally oxidized film34is provided on the outer side surface61and the inner side surface62of the separation groove60. 7. Overall Configuration of Solid-state Imaging Unit FIG.26illustrates an overall configuration of a solid-state imaging unit including, as a pixel section110, one of the solid-state imaging devices10and10A to10E described in the foregoing embodiments. The solid-state imaging unit1may be, for example, a CMOS image sensor, and may include, for example, the pixel section110as an imaging pixel region, as well as a circuit section130. The circuit section130may include, for example, a row scanner131, a horizontal selector133, a column scanner134, and a system controller132. The circuit section130may be provided in a peripheral region around the pixel section110. Alternatively, the circuit section130may be stacked above or below the pixel section110(that is, in a region facing the pixel section110). The pixel section110may include, for example, a plurality of pixels PXL that are arranged in a two-dimensional array. The pixels PXL may be wired with pixel drive lines Lread (specifically, row selector lines and reset control lines) for each pixel row, and may be wired with vertical signal lines Lsig for each pixel column. The pixel drive lines Lread are adapted to transmit drive signals to read signals from the pixels. One ends of the pixel drive lines Lread may be coupled to output terminals that correspond to their respective rows of the row scanner131. The row scanner131may include, for example, a shift register and an address decoder, and may serve as a pixel drive section that drives the pixels PXL of the pixel section110, for example, in a row unit. Signals may be outputted from the pixels PXL of a pixel row selected and scanned by the row scanner131; and the signals thus outputted may be supplied to the horizontal selector133through the respective vertical signal lines Lsig. The horizontal selector133may include, for example, an amplifier and horizontal selector switches that are provided for each of the vertical signal lines Lsig. The column scanner134may include, for example, a shift register and an address decoder, and is adapted to scan and sequentially drive the horizontal selector switches of the horizontal selector133. Such selective scanning by the column scanner134allows the signals transmitted from the pixels PXL through the respective vertical signal lines Lsig to be sequentially transmitted to a horizontal signal line135and to be outputted through the horizontal signal line135. The system controller132is adapted to receive, for example, a clock supplied from the outside, data on instructions of operation modes, and to output data such as internal information of the solid-state imaging unit1. Furthermore, the system controller132may include a timing generator that generates various timing signals, and is adapted to perform drive control of the row scanner131, the horizontal selector133, the column scanner134, and other parts, based on the various timing signals generated by the timing generator. 8. Application Example The solid-state imaging unit according to the forgoing description including the above-described example embodiments may be applied to various electronic apparatuses having imaging functions. Examples may include camera systems such as digital still cameras and video cameras, and mobile phones having imaging functions.FIG.27illustrates, for purpose of an example, an overall configuration of an electronic apparatus2(e.g., a camera). The electronic apparatus2may be a video camera configured to capture still images and moving pictures, and may include the solid-state imaging unit1, an optical system (an imaging lens)310, a shutter device311, a drive section313(that includes the above-mentioned circuit section130), a signal processing section312, a user interface314, and a monitor315. The drive section313is adapted to drive the solid-state imaging unit1and the shutter device311. The optical system310is adapted to guide image light (entering light) from an object toward the pixel section110of the solid-state imaging unit1. The optical system310may include a plurality of optical lenses. The shutter device311is adapted to control a light-irradiating period and a light-shielding period of the solid-state imaging unit1. The drive section313is adapted to control transfer operation of the solid-state imaging unit1and shutter operation of the shutter device311. The signal processing section312is adapted to perform various signal processing on signals outputted from the solid-state imaging unit1. A picture signal Dout after the signal processing may be outputted to the monitor315. Alternatively, the picture signal Dout may be stored in a storage medium such as a memory. The user interface314allows for designation of scenes to be photographed (e.g., designation of dynamic ranges and designation of wavelengths (such as terahertz, visible light, infrared, ultraviolet, and X ray)). Such designation (i.e., an input signal from the user interface314) may be sent to the drive section313; based on the designation, desired imaging may be carried out in the solid-state imaging unit1. Although description has been made by giving the example embodiments as mentioned above, the contents of the disclosure are not limited to the above-mentioned example embodiments, etc. and may be modified in a variety of ways. For example, the pixel circuit of the solid-state imaging device10may have a three-transistor configuration including three transistors in total, including a transfer transistor, an amplifier transistor, and a reset transistor, or four-transistor configuration further including a selection transistor in addition to the three transistors. Moreover, for example, in the forgoing example embodiments, description has been given on a case where the solid-state imaging unit is applied to a camera as an example; however, the solid-state imaging unit may be also applied to general electronic apparatuses that image light (electromagnetic waves), such as endoscopes, vision chips (artificial retinas), and biosensors. Moreover, in the forgoing example embodiments, description has been given on the configuration of the backside illuminated type solid-state imaging device10; however, the contents of the present disclosure are applicable also to a front illuminated type solid-state imaging device. For example, in the solid-state imaging device10and the solid-state imaging unit1according to the forgoing example embodiments, it is not necessary to include all the components, and another component or other components may be further provided. It is to be noted that the contents of the technology may have the following configurations. (1) A solid-state imaging device including:one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate;a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; andan amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate,in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode. (2) The solid-state imaging device according to (1), further including a reset transistor provided on the second surface of the semiconductor substrate, the reset transistor including a reset gate,in which the reset gate is disposed adjacent to the floating diffusion. (3) The solid-state imaging device according to (1) or (2), in whichthe one or more photoelectric conversion elements include a plurality of photoelectric conversion elements, andthe through electrode is provided for each of the plurality of photoelectric conversion elements. (4) The solid-state imaging device according to any one of (1) to (3), in which the through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove. (5) The solid-state imaging device according to (4), in whichthe through electrode is made of a semiconductor doped with an N-type or P-type impurity, andan impurity region of a same conductive type as a conductive type of the through electrode is provided on an outer side surface of the separation groove in the semiconductor substrate. (6) The solid-state imaging device according to (4), in which the through electrode is made of a metal or a conductive material. (7) The solid-state imaging device according to any one of (4) to (6), in which the separation groove is filled with a dielectric layer having insulation properties. (8) The solid-state imaging device according to any one of (4) to (6), in whichan outer side surface of the separation groove is covered with an outer dielectric layer,an inner side surface of the separation groove is covered with an inner dielectric layer, andthe outer dielectric layer and the inner dielectric layer are spaced with a gap between. (9) The solid-state imaging device according to any one of (4) to (8), in which a film having a fixed charge is provided on an outer side surface, an inner side surface, and a bottom surface of the separation groove, and the first surface of the semiconductor substrate. (10) The solid-state imaging device according to any one of (1) to (9), further including one or more photodiodes provided in the semiconductor substrate. (11) A solid-state imaging device including:a photoelectric conversion element provided on side of a first surface of a semiconductor substrate;a through electrode coupled to the photoelectric conversion element, and provided between the first surface and a second surface of the semiconductor substrate;a separation groove provided between the through electrode and the semiconductor substrate; anda dielectric layer embedded in the separation groove, and having insulation properties. (12) A solid-state imaging device including:a photoelectric conversion element provided on side of a first surface of a semiconductor substrate;a through electrode coupled to the photoelectric conversion element, and provided between the first surface and a second surface of the semiconductor substrate;a separation groove provided between the through electrode and the semiconductor substrate;an outer dielectric layer covering an outer side surface of the separation groove;an inner dielectric layer covering an inner side surface of the separation groove; anda gap provided between the outer dielectric layer and the inner dielectric layer. (13) An electronic apparatus provided with a solid-state imaging device, the solid-state imaging device including:one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate;a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; andan amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate,in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode. (14) An electronic apparatus provided with a solid-state imaging device, the solid-state imaging device including:a photoelectric conversion element provided on side of a first surface of a semiconductor substrate;a through electrode coupled to the photoelectric conversion element, and provided between the first surface and a second surface of the semiconductor substrate;a separation groove provided between the through electrode and the semiconductor substrate; anda dielectric layer embedded in the separation groove, and having insulation properties. (15) An electronic apparatus provided with a solid-state imaging device, the solid-state imaging device including:a photoelectric conversion element provided on side of a first surface of a semiconductor substrate;a through electrode coupled to the photoelectric conversion element, and provided between the first surface and a second surface of the semiconductor substrate;a separation groove provided between the through electrode and the semiconductor substrate;an outer dielectric layer covering an outer side surface of the separation groove;an inner dielectric layer covering an inner side surface of the separation groove; anda gap provided between the outer dielectric layer and the inner dielectric layer. This application claims the benefit of Japanese Priority Patent Application JP 2013-169553 filed on Aug. 19, 2013, the entire contents of which are incorporated herein by reference. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof. | 64,273 |
11862656 | DESCRIPTION OF EMBODIMENTS Hereinafter, modes (hereinafter called embodiments) for carrying out the present disclosure will be described. The description is given in the following order. 1. First embodiment: CMOS image sensor (FIGS.1to13) 2. Second embodiment: CMOS image sensor (FIGS.14to18) 3. Third embodiment: Imaging device (FIG.19) 4. Usage example of CMOS image sensor (FIG.20) First Embodiment Example Configuration of First Embodiment of CMOS Image Sensor FIG.1is a block diagram illustrating an example configuration of a first embodiment of a complementary metal oxide semiconductor (CMOS) image sensor as a semiconductor device to which the present disclosure is applied. A CMOS image sensor10includes a semiconductor chip11and a semiconductor chip12connected via bumps13. The semiconductor chip11and the semiconductor chip12each include a semiconductor substrate, such as a silicon substrate, and a metal wiring layer of Cu, Al, or the like. A pixel region21, pixel driving lines22, vertical signal lines23, a vertical driving unit24, a column processing unit25-1, and a system control unit27are formed on the semiconductor chip11. A column processing unit25-2, a horizontal driving unit26, and a memory and signal processing unit28are formed on the semiconductor chip12. In the pixel region21, pixels each including a photoelectric conversion element that generates charge with a charge amount corresponding to a light amount of incident light and accumulates the charge inside are two-dimensionally arranged in a matrix to perform imaging. In addition, the pixel driving line22is formed in each row and the vertical signal line23is formed in each column for the pixels in the matrix in the pixel region21. The vertical driving unit24includes a shift register, an address decoder, or the like, and drives the pixels in the pixel region21in units of rows, for example. One terminal of the pixel driving line22is connected to an output terminal, which is not shown, corresponding to each row of the vertical driving unit24. Although a specific configuration of the vertical driving unit24is not shown, the vertical driving unit24includes two scanning systems, a read scanning system and a sweep scanning system. The read scanning system sequentially selects each row to sequentially read pixel signals from the pixels in units of rows, and outputs a selection signal or the like from the output terminal connected to the pixel driving line22of the selected row. Thus, from the pixels in the row selected by the read scanning system, electrical signals of charge accumulated in the photoelectric conversion elements are read as pixel signals and supplied to the vertical signal lines23. The sweep scanning system outputs a reset signal from the output terminal connected to the pixel driving line22of each row, earlier than the scanning by the read scanning system by a period of time corresponding to a shutter speed, in order to sweep (reset) unnecessary charge from the photoelectric conversion elements. By this scanning by the sweep scanning system, what is called electronic shutter operation is sequentially performed row by row. Here, electronic shutter operation refers to operation of discarding charge of photoelectric conversion elements and newly starting light exposure (starting accumulation of charge). The column processing unit25-1is one part of signal processing circuits provided for the respective columns of the pixel region21, and the column processing unit25-2is the other part. The column processing unit25-1and the column processing unit25-2are connected to each other via the bumps13to form the signal processing circuits provided for the respective columns of the pixel region21. Each signal processing circuit performs signal processing, such as A/D conversion processing and correlated double sampling (CDS) processing, on pixel signals output from the pixels of the selected row through the vertical signal lines23. Each signal processing circuit temporarily retains the pixel signals after the signal processing. The horizontal driving unit26includes a shift register, an address decoder, or the like, and sequentially selects the signal processing circuit of each column. By this selection scanning by the horizontal driving unit26, the pixel signals having been subjected to signal processing by each signal processing circuit are sequentially output to the memory and signal processing unit28. The system control unit27includes a timing generator, which generates various timing signals, or the like. The system control unit27generates control signals for controlling the vertical driving unit24, the column processing unit25-1, the column processing unit25-2, and the horizontal driving unit26, on the basis of the various timing signals generated by the timing generator. The system control unit27supplies the control signal for controlling the vertical driving unit24to the vertical driving unit24, and supplies the control signal for controlling the column processing unit25-1to the column processing unit25-1. In addition, the system control unit27supplies the control signal for controlling the column processing unit25-2to the column processing unit25-2via the bump13, and supplies the control signal for controlling the horizontal driving unit26to the horizontal driving unit26via the bump13. The memory and signal processing unit28performs various kinds of signal processing on the pixel signals output from the horizontal driving unit26. At this time, the memory and signal processing unit28stores an intermediate result of signal processing, for example, in an internal memory as necessary, and refers to the intermediate result at necessary timing. The memory is configured with, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like. The memory and signal processing unit28outputs the pixel signals after the signal processing. First Example Structure of CMOS Image Sensor FIG.2Ais a cross-sectional view illustrating a first example structure of the CMOS image sensor10ofFIG.1.FIG.2Bis a view of the first example structure of the CMOS image sensor10, seen from the light irradiation side. As illustrated inFIGS.2A and2B, the pixel region21and the like are formed on the semiconductor chip11. In addition, in a region of the semiconductor chip11that corresponds to the semiconductor chip12, a peripheral circuit unit51including the column processing unit25-1and the system control unit27is formed. Furthermore, electrode pads52for wire bonding are formed on the semiconductor chip11. Electrode pads53A for bump connection are formed in the peripheral circuit unit51. On the light irradiation side of the semiconductor chip11, a passivation54A of SiN or the like is formed to have openings in regions corresponding to the electrode pads53A for bump connection and the electrode pads52for wire bonding. The bumps (micro-bumps)13are connected to the electrode pads53A for bump connection via the openings of the passivation54A. Meanwhile, electrode pads53B for bump connection are formed on (the column processing unit25-2of) the semiconductor chip12. In addition, on the side opposite to the light irradiation side of the semiconductor chip12, a passivation54B of SiN or the like is formed to have openings in regions corresponding to the electrode pads53B for bump connection. The bumps13are connected to the electrode pads53B for bump connection via the openings of the passivation54B. Thus, the semiconductor chip12is bonded to the light irradiation side of the semiconductor chip11via the bumps13on the semiconductor chip12and the bumps13on the semiconductor chip11. That is, the semiconductor chip12is flip-chip bonded to the light irradiation side of the semiconductor chip11. To keep mechanical strength, a space between the semiconductor chip11and the semiconductor chip12is filled with an under-fill resin55. Around a bonding region of the semiconductor chip12on the semiconductor chip11, a dam56that prevents leakage of the under-fill resin55to a region other than the bonding region at the time of filling the space with the under-fill resin55is formed; thus, the under-fill resin55spreads only inside the dam56. In addition, on the light irradiation side of the semiconductor chip11, a lens material57of an organic substance or the like is formed in the pixel region21of a region other than the bumps13. The lens material57may include one kind of organic substance, or may include two or more kinds of organic substances stacked. A thin inorganic film of SiO2, SiN, or the like may be stacked, as an antireflection film, on the organic substance forming the lens material57. The lens material57functions as on-chip lenses in the pixel region21, and collects irradiation light on the pixel region21. The lens material57is not formed in a region58other than the pixel region21on the semiconductor chip11. That is, the lens material57has an opening in the region58other than the pixel region21. Note that, although not shown, a color filter and the like are actually formed between the lens material57and the pixel region21. (Description of Manufacturing Method of CMOS Image Sensor) FIG.3is a view for describing an overview of a manufacturing method of the CMOS image sensor10ofFIG.2. First, as illustrated inFIG.3A, the passivation54A and the lens material57are stacked on the entire surface on the light irradiation side of the semiconductor chip11, where the pixel region21, the peripheral circuit unit51, and the electrode pads52for wire bonding are formed. Next, as illustrated inFIG.3B, the region58other than the pixel region21of the lens material57is etched and an opening is made. Then, as illustrated inFIG.3C, to connect the bumps13and the electrode pads53A for bump connection, regions of the passivation54A that correspond to the electrode pads53A for bump connection are etched and opening portions71for bumps are formed. In addition, to connect wire bonding and the electrode pads52for wire bonding, regions that correspond to the electrode pads52for wire bonding are etched and opening portions72for wire bonding are formed. Then, as illustrated inFIG.3D, the bumps13are formed on the electrode pads53A for bump connection in the peripheral circuit unit51, and the dam56is formed around the bonding region of the semiconductor chip12on the peripheral circuit unit51. Then, as illustrated inFIG.3E, the semiconductor chip12where the electrode pads53B for bump connection connected to the bumps13are formed is bonded onto the peripheral circuit unit51of the semiconductor chip11so that the bumps13of the semiconductor chip11and the semiconductor chip12are connected. Then, the space between the semiconductor chip11and the semiconductor chip12is filled with the under-fill resin55. FIG.4is an enlarged view of the vicinity of the peripheral circuit unit51for describing details of a formation method of the bumps13of the semiconductor chip11. First, as illustrated inFIG.4A, a seed metal73is deposited. Then, as illustrated inFIG.4B, photolithography is performed and a resist74is formed in a region other than regions where the bumps13are formed. Next, as illustrated inFIG.4C, plating growth of solder is performed by using the resist74as a mask; thus, solders75are formed. Then, as illustrated inFIG.4D, the resist74is removed. Then, as illustrated inFIG.4E, the seed metal73in a region other than the solders75is etched. Lastly, as illustrated inFIG.4F, reflow is performed and the bumps13are formed. In contrast, in the case where the lens material57is stacked on the entire surface on the light irradiation side of the semiconductor chip11, the lens material57exists in addition to the passivation54A on the light irradiation side of the electrode pads53A for bump connection, as illustrated inFIG.5. Accordingly, it is necessary to make openings in the passivation54A and the lens material57to form opening portions81. Accordingly, the aspect ratio between the depth of the opening portion81and the open width is large. Thus, the embeddability of the solder and the seed metal73at the time of forming the bumps13is degraded, and resist residue due to underexposure and underdevelopment at the time of lithography becomes likely to occur. As a result, malformation of the bumps13and the like occur. In addition, since the lens material57includes an organic substance, gas occurs from the lens material57around the opening portions81of the passivation54A and a reaction product is produced by reaction with an etching gas at the time of etching for forming the opening portions81of the passivation54A. Furthermore, in the case where the lens material57is a material more brittle than the passivation54A, the lens material57is physically etched to be scattered at the time of etching for forming the opening portions81of the passivation54A, and the scattered lens material57inhibits the etching for forming the opening portions81of the passivation54A. Thus, an abnormality of the opening portions81of the passivation54A occurs, and malformation of the bumps13, degradation of connection resistance, and the like occur. As the bumps13are increasingly miniaturized and the pitch of the bumps13is increasingly narrowed, the aspect ratio of the opening portion81is further increased and the above-described problems at the time of forming the bumps13become significant. However, in the CMOS image sensor10, in which the column processing unit25-2is formed on the semiconductor chip12different from the semiconductor chip11and flip-chip bonding is performed, an increase in the number of the bumps13enables high-speed operation. Accordingly, it is desirable to arrange as many bumps13as possible in the limited size of the semiconductor chip12, and miniaturization of the bumps13and narrowing of the pitch of the bumps13are necessary. Also in the case where the lens material57is thick, the aspect ratio of the opening portion81is increased and the above-described problems at the time of forming the bumps13become significant. Since the electrode pads52for wire bonding are sufficiently large, in the etching for forming the opening portions72for wire bonding, which are formed on the electrode pads52for wire bonding, the influence of the lens material57around the opening portions72for wire bonding is small. In addition, a wire ball is formed not by lithography but by mechanically forming an alloy by using ultrasound and pressure and performing crimping; therefore, problems like those at the time of forming the bumps13do not occur. Meanwhile, in the CMOS image sensor10, openings are made in at least regions where the bumps13and the electrode pads52for wire bonding are formed; therefore, as illustrated inFIG.4E, the aspect ratio of the opening portion71for a bump is smaller than that of the opening portion81ofFIG.5. Accordingly, the embeddability of the solder and the seed metal73at the time of forming the bumps13can be improved. In addition, the flow of liquid is not obstructed at the time of wet processing, such as development. As a result, occurrence of residue of the resist74or the like due to underexposure and underdevelopment at the time of lithography can be prevented. Furthermore, at the time of etching for forming the opening portions71for bumps of the passivation54A, etching can be prevented from being inhibited by the lens material57around the opening portions71for bumps. Second Example Structure of Pixel Region and Peripheral Circuit FIG.6is a cross-sectional view illustrating a second example structure of the CMOS image sensor10ofFIG.1. The structure of the CMOS image sensor10ofFIG.6is the same as the structure ofFIG.2except that the lens material57is formed in a region other than a region91, which corresponds to the semiconductor chip12and is the whole region inside the dam56(including the dam56) on the semiconductor chip11, and the electrode pads52for wire bonding. That is, in the example ofFIG.6, the lens material57is formed to have openings in the region91, which corresponds to the semiconductor chip12and is larger than the semiconductor chip12, on the semiconductor chip11and regions of the electrode pads52for wire bonding. For example, when the dam56is formed at a position approximately 200 μm away from the edge of the semiconductor chip12, an opening is made in the lens material57around 200 μm from the edge of a region to which the semiconductor chip12is bonded on the semiconductor chip11. Third Example Structure of Pixel Region and Peripheral Circuit FIG.7is a cross-sectional view schematically illustrating a third example structure of the CMOS image sensor10ofFIG.1. The structure of the CMOS image sensor10ofFIG.7is the same as the structure ofFIG.2except that the lens material57is formed to have openings in only a region92, which is part of the inside of the dam56(including the dam56) on the semiconductor chip11and is larger than the size of the semiconductor chip12, and the electrode pads52for wire bonding. That is, in the example ofFIG.7, the lens material57is formed to have openings in the region, which corresponds to the semiconductor chip12and is larger than the size of the semiconductor chip12and smaller than a region inside the dam56(including the dam56), on the semiconductor chip11and the electrode pads52for wire bonding. As described above, in the examples ofFIGS.6and7, the lens material57is also formed in a region other than the pixel region21; therefore, the lens material57can protect the region other than the pixel region21as well. In addition, when the lens material57includes a color filter that prevents reflection of light, reflection of light from the region other than the pixel region21can be prevented. Although the lens material57is not formed in part of a region on the peripheral circuit unit51, the part can be protected as well because it is filled with the under-fill resin55. In addition, by selecting an appropriate resin as the under-fill resin55, reflection of light from the inside of the dam56(not including the dam56) can be prevented. Fourth Example Structure of Pixel Region and Peripheral Circuit FIG.8is a cross-sectional view schematically illustrating a fourth example structure of the CMOS image sensor10ofFIG.1. The structure of the CMOS image sensor10ofFIG.8is the same as the structure ofFIG.2except that the lens material57is formed to have openings in only a region93, which has the same size as the semiconductor chip12, inside the dam56on the semiconductor chip11and the electrode pads52for wire bonding. That is, in the example ofFIG.8, the lens material57is formed to have openings in the region93, which corresponds to the semiconductor chip12and has the same size as the semiconductor chip12, on the semiconductor chip11and the electrode pads52for wire bonding. In consideration of misalignment of the semiconductor chip12, the lens material57may have an opening in a region that is at the inner side than the region93by the amount of misalignment and is smaller than the size of the semiconductor chip12. Note that when an opening region of the lens material57is too small, problems occur at the time of forming the bumps13as in the case where the lens material57is formed on the entire surface of the semiconductor chip11. Accordingly, for example, as illustrated inFIG.9, an opening region94other than the electrode pads52for wire bonding of the lens material57is formed such that a distance101from the side of the bump13closest to the lens material57to the side of the lens material57closest to the bump13is larger than the larger one of twice the opening size at the time of lithography, that is, a diameter102of the bump13, and a minimum value103of the pitch of the bumps13. Alternatively, as illustrated inFIGS.9and10, the opening region94is formed such that the ratio (hereinafter called wire bonding ratio) of a distance124from the side of the opening portion72for wire bonding closest to the lens material57to the side of the lens material57closest to the opening portion72for wire bonding to a size123of the opening portion72for wire bonding in a direction in which the lens material57and a wire bonding120are aligned is smaller than the ratio (hereinafter called bump ratio) of a distance105from the side of the opening portion71for a bump closest to the lens material57to the side of the lens material57closest to the opening portion71for a bump to a size104of the opening portion71for a bump in a direction in which the lens material57and the bumps13are aligned. That is, the opening region94is formed such that the bump ratio is equal to or greater than the wire bonding ratio that does not cause a problem at the time of forming the wire bonding120. As described above, in the examples ofFIGS.8to10, as in the case ofFIGS.6and7, the lens material57is also formed in a region other than the pixel region21. Accordingly, the region other than the pixel region21can be protected as well and reflection of light from the region other than the pixel region21can be prevented. The size of an opening region (the region93or the opening region94) other than the electrode pads52for wire bonding of the lens material57is equal to or smaller than the size of the semiconductor chip12. Accordingly, the semiconductor chip12and the under-fill resin55can protect the opening region of the lens material57on the peripheral circuit unit51and prevent reflection of light from the opening region. Examples of Shape of Region92 FIGS.11to13are views of part of the semiconductor chip11, seen from the light irradiation side, which show examples of the shape of the region92ofFIG.7. As illustrated inFIG.11, the region92includes, for example, one region that surrounds all the bumps13formed on the semiconductor chip11. In this case, level differences formed by the lens material57on the surface on the light irradiation side of the semiconductor chip11are reduced, and the flow of liquid is less likely to be obstructed at the time of wet processing, such as development. Note that, as illustrated inFIG.12, the region92may include two or more regions that divide the bumps13into two or more groups and surround the bumps13for each group. In addition, the shape of the region92is not limited to a rectangular shape, and may be a circular shape as illustrated inFIG.13, for example. Although the region92is described usingFIGS.11to13, the same applies to the region93and the opening region94. In the first embodiment, the case where an embodiment of the present disclosure is applied to a CMOS image sensor is described; however, an embodiment of the present disclosure can also be applied to a solid-state imaging device other than a CMOS image sensor, such as a charge coupled device (CCD) image sensor. In addition, an embodiment of the present disclosure can be applied to an element in which a resin such as polyimide is used as a protective film instead of the lens material57and bumps are formed. Furthermore, the method for distributing components of the CMOS image sensor10to the semiconductor chip11and the semiconductor chip12is not limited to the above-described method. In addition, units connected by bumps are not limited to the column processing units25-1and25-2, the horizontal driving unit26, and the system control unit27. Furthermore, the semiconductor chip12may be formed by a plurality of semiconductor chips. Units formed on the plurality of semiconductor chips may be the same or different. Second Embodiment Overview of Example Configuration of Second Embodiment of CMOS Image Sensor FIG.14is a view illustrating an overview of an example configuration of a second embodiment of a CMOS image sensor to which the present disclosure is applied. In a CMOS image sensor140ofFIG.14, a lower chip141, which is a semiconductor chip on the lower side of the figure, and an upper chip142, which is a semiconductor chip on the upper side of the figure, are flip-chip bonded to each other. The lower chip141includes a semiconductor substrate and a metal wiring layer of Cu, Al, or the like, and a pixel region141A and a peripheral circuit141B are formed on the lower chip141. The configuration of the pixel region141A is similar to the configuration of the pixel region21ofFIG.1. The peripheral circuit141B, whose configuration is similar to the configuration of the vertical driving unit24, the column processing units25-1and25-2, the horizontal driving unit26, and the system control unit27, is formed on the same lower chip141where the pixel region141A is formed, and includes bumps, which are not shown, for bonding to the upper chip142. A lens material, which is not shown, formed on the lower chip141is formed to have an opening in a region corresponding to a bonding region of the upper chip142. Accordingly, as in the first embodiment, occurrence of problems at the time of forming the bumps, which are not shown, included in the peripheral circuit141B can be prevented. The upper chip142includes a semiconductor substrate and a metal wiring layer of Cu, Al, or the like, and a signal processing circuit142A is formed on the upper chip142. The configuration of the signal processing circuit142A is similar to the configuration of the memory and signal processing unit28ofFIG.1. Example Configuration of CMOS Image Sensors Before Dicing FIG.15is a perspective view illustrating an example configuration of the CMOS image sensors140ofFIG.14before dicing, andFIG.16is a cross-sectional view along A-A ofFIG.15. As illustrated inFIG.15, the CMOS image sensors140before dicing include a semiconductor wafer150where the lower chips141are arranged in an array and the upper chips142bonded across two lower chips141. Note thatFIG.15shows only a part of the semiconductor wafer150where2(lateral)×3 (longitudinal) lower chips141are formed. An external shape of each of the lower chip141(first semiconductor chip) and the upper chip142is a rectangular shape having a predetermined thickness. A scribe region151is provided between the lower chips141. A test element group (TEG) pattern161and marks162are formed in the scribe region151between two lower chips141across which the upper chip142is present. The TEG pattern161is a pattern for evaluating bumps, which are not shown, that bond the lower chips141and the upper chips142to each other. The marks162are marks used for alignment at the time of bonding the lower chips141and the upper chips142. The lower chips141and the upper chips142are bonded to each other such that the marks162coincide with marks, which are not shown, formed on the upper chip142. In addition, electrodes163for evaluating the bumps, which are not shown, that bond the lower chips141and the upper chips142are formed in the scribe region151to be connected to the TEG pattern161. Around a region to which the upper chip142is bonded on the lower chips141, a dam164that prevents leakage of an under-fill resin filling a space between the lower chips141and the upper chip at the time of bonding the lower chips141and the upper chip to each other is formed. The upper chip142is formed by a north chip171formed on the upper side (north side) of the figure and a south chip172formed on the lower side (south side) of the figure between which a scribe region173is sandwiched. An external shape of each of the north chip171(second semiconductor chip) and the south chip172(third semiconductor chip) is a rectangular shape having a predetermined thickness. Marks, which are not shown, used for alignment at the time of bonding the lower chips141and the upper chips142to each other are formed in the scribe region173. On the upper chip142, the signal processing circuit142A is divided into five circuits181to185and, among the circuits, two circuits181and182are formed on the north chip171and three circuits183to185are formed on the south chip172. The CMOS image sensors140before dicing are separated by dicing (cutting) the scribe region151around the lower chips141, as illustrated inFIG.16. Thus, in the CMOS image sensor140after the separation, the whole region of a side (first side)191in the left-right direction (horizontal direction) ofFIG.15out of scribe lines forming an outline of the lower chip141to which the scribe region151is added and the whole region of a side (second side)192in the left-right direction ofFIG.15out of scribe lines forming an outline of the north chip171to which the scribe region173is added are flush with each other. In addition, the whole region of a side (third side)193facing the side191out of the scribe lines forming the outline of the lower chip141to which the scribe region151is added and the whole region of a side (fourth side)194in the left-right direction ofFIG.15out of scribe lines forming an outline of the south chip172to which the scribe region173is added are flush with each other. Note that although the whole regions of the side191and the side192are flush with each other and the whole regions of the side193and the side194are flush with each other in the second embodiment, it is not necessary that the whole regions be flush as long as at least partial regions are flush with each other. As described above, in the CMOS image sensor140, both the north chip171and the south chip172are formed on one upper chip142. Accordingly, the north chip171and the south chip172can be bonded to the lower chip141at the same time. In addition, the lower chips141may be formed on the semiconductor wafer150in the same orientation and the lower chips141do not need an axis of symmetry. Furthermore, the north chip171and the south chip172do not need an axis of symmetry. In addition, the TEG pattern161, the marks162, and the electrodes163, which are used only at the time of manufacture, are arranged in the scribe region151and eliminated at the time of separating the CMOS image sensors140. Accordingly, an effective region of the lower chip141can be increased as compared with a case where the TEG pattern161, the marks162, and the electrodes163are arranged in the CMOS image sensor140. In contrast, in the case where a north chip203and a south chip204are individually formed on a lower chip202formed on a semiconductor wafer201as illustrated inFIG.17, the north chip203and the south chip204are bonded to the lower chip202one by one. Accordingly, it is necessary to form marks205and marks206used for alignment at the time of bonding for the north chip203and the south chip204. Thus, when the marks205and the marks206are formed on the lower chip202on the semiconductor wafer201as illustrated inFIG.17, the size of the lower chip202is increased and manufacturing cost is increased. In addition, it is necessary to form dams207and208that prevent leakage of an under-fill resin filling a space between the lower chip202and each of the north chip203and the south chip204around bonding regions on the lower chip202for the north chip203and the south chip204. (Description of Manufacturing Method of CMOS Image Sensor) FIG.18is a perspective view for describing a manufacturing method of the CMOS image sensor140. First, as illustrated inFIG.18A, the lower chip141is formed on the semiconductor wafer150. The TEG pattern161and the marks162are formed in the scribe region151between the lower chips141, and the electrodes163are formed in the scribe region151in a region other than between the lower chips141. The dam164is formed around a region to which the upper chip142is bonded on the lower chips141. In the peripheral circuit141B inside the dam164on the lower chip141, bumps221, such as balls or pillars, are formed by a method such as electrolytic plating, electroless plating, transfer, or crimping to be connected to electrodes for bumps, which are not shown, formed in the lower chip141. The bumps221are arranged with a narrow pitch of, for example, several tens of microns. To ensure electrical characteristics and reliability thereof, the bumps221include a barrier layer, a seed layer, a metal layer for bonding, and the like using metal materials such as Ni, Pd, Au, Sn, Ag, Pb, Bi, Cu, and In, typically. Next, as illustrated inFIG.18B, the north chip171where the circuits181and182are formed and the south chip172where the circuits183to185are formed are arranged with the scribe region173sandwiched therebetween; thus, the upper chip142is formed. Bumps222are formed on the north chip171and the south chip172. Marks231and a TEG pattern232are formed in the scribe region173. Then, as illustrated inFIG.18C, the upper chips142are sequentially arranged on the semiconductor wafer150to be bonded such that the marks162coincide with the marks231. Thus, the bumps222on the north chip171are bonded to the bumps221on the south side of one lower chip141, and the bumps222on the south chip172are bonded to the bumps221on the north side of another lower chip141different from the lower chip141. In this manner, the lower chips141and the upper chips142are bonded to each other on the basis of the marks162and the marks231; thus, even in the case where the bumps221and the bumps222are arranged with high density, the bumps221and the bumps222can be connected accurately. Note that on the north side of the lower chip141where the north chip171is arranged on the south side, the south chip172of the upper chip142that is different from the upper chip142having the north chip171is arranged. In addition, on the south side of the lower chip141where the south chip172is arranged on the north side, the north chip171of the upper chip142that is different from the upper chip142having the south chip172is arranged. Next, between the lower chips141and the upper chips142, an under-fill resin is injected from one direction or two directions of south and north. In the case where the under-fill resin is injected from two directions of south and north, the under-fill resin is injected by line application from opposite directions of left and right between the south direction and the north direction. Thus, the lower chips141and the upper chips142are fixed. Lastly, the scribe region151around the lower chips141is diced and the CMOS image sensors140are separated, as illustrated inFIG.18D. As described above, the north chip171and the south chip172are collectively bonded to the lower chips141; therefore, the number of times of bonding can be drastically reduced as compared with a case where the north chip203and the south chip204are individually bonded to the lower chip202as illustrated inFIG.17. That is, the north chip171and the south chip172can be bonded to the lower chips141easily. As a result, bonding turn-around time (TAT) is shortened and manufacturing cost can be reduced. In addition, time for heat treatment necessary for bump connection is shortened and thus heat load on the semiconductor wafer150is reduced and the influence of heat treatment to characteristics of the CMOS image sensor140can be minimized. In addition, since the north chip171and the south chip172are collectively bonded to the lower chips141, the marks used for alignment at the time of bonding the north chip171and the south chip172and the TEG pattern for evaluating bumps can be shared. Furthermore, the CMOS image sensor140does not have layout constraints, such as mirror inversion and an axis of symmetry; therefore, there is no need to change the physical arrangement in the CMOS image sensor140. Although the number of the lower chips141bonded to one upper chip142is two in the second embodiment, the number may be more than two. For example, the upper chip142may be bonded across 2 (lateral)×2 (longitudinal) lower chips, i.e., four lower chips, or may be bonded across 3 (lateral)×2 (longitudinal) lower chips, i.e., six lower chips. Note that the number of the lower chips141bonded to one upper chip142is in a trade-off relationship with yield. Although the number of circuits forming the signal processing circuit142A is five in the second embodiment, the number may be any number as long as it is more than one. Furthermore, although a lens material is not formed in a region on the lower chips141that corresponds to a bonding region of the upper chip142as in the first embodiment in the second embodiment, the lens material may be formed in that region. Although the pixel region141A and the peripheral circuit141B are formed on the same lower chip141in the second embodiment, they may be formed on different semiconductor chips. Also in this case, bonding between semiconductor chips is performed in a manner similar to that of the lower chips141and the upper chips142. Furthermore, the CMOS image sensor10and the CMOS image sensor140may be back-side illumination CMOS image sensors or front-side illumination CMOS image sensors. Note that in the case where the CMOS image sensor10and the CMOS image sensor140are front-side illumination CMOS image sensors, electrode pads for bump connection may be formed above a metal wiring layer. Accordingly, the electrode pads for bump connection can be formed in steps similar to those for forming normal electrode pads for wire bonding connection. In addition, there is no need to perform a back side re-wiring step of bringing wiring of a metal wiring layer on the back side to the front side, unlike in the case of back-side illumination CMOS image sensors. Therefore, manufacturing cost can be reduced. Third Embodiment Example Configuration of Embodiment of Imaging Device FIG.19is a block diagram illustrating an example configuration of an embodiment of an imaging device as an electronic appliance to which the present disclosure is applied. An imaging device1000ofFIG.19is a video camera, a digital still camera, or the like. The imaging device1000includes a lens group1001, a solid-state image sensor1002, a DSP circuit1003, a frame memory1004, a display unit1005, a recording unit1006, an operation unit1007, and a power supply unit1008. The DSP circuit1003, the frame memory1004, the display unit1005, the recording unit1006, the operation unit1007, and the power supply unit1008are mutually connected via a bus line1009. The lens group1001takes in incident light (image light) from a photographic subject, and forms an image on an imaging surface of the solid-state image sensor1002. The solid-state image sensor1002includes the CMOS image sensor10(140) described above. The solid-state image sensor1002converts the amount of incident light whose image is formed on the imaging surface by the lens group1001to electrical signals in units of pixels, and supplies the electrical signals as pixel signals to the DSP circuit1003. The DSP circuit1003performs predetermined image processing on the pixel signals supplied from the solid-state image sensor1002, and supplies the pixel signals after the image processing to the frame memory1004in units of frames so that the pixel signals are temporarily stored. The display unit1005is configured with, for example, a panel-type display device, such as a liquid crystal panel or an organic electro luminescence (EL) panel, and displays an image on the basis of the pixel signals in units of frames temporarily stored in the frame memory1004. The recording unit1006is configured with a digital versatile disk (DVD), a flash memory, or the like, and reads and records the pixel signals in units of frames temporarily stored in the frame memory1004. The operation unit1007issues, under control by a user, operation commands about various functions of the imaging device1000. The power supply unit1008supplies power to the DSP circuit1003, the frame memory1004, the display unit1005, the recording unit1006, and the operation unit1007as appropriate. An electronic appliance to which an embodiment of the present technology is applied may be any device that uses a CMOS image sensor in an image capturing unit (photoelectric conversion unit), examples of which include a portable terminal device having an imaging function and a copying machine using a CMOS image sensor in an image reading unit, in addition to the imaging device1000. Usage Examples of CMOS Image Sensor FIG.20is a view illustrating usage examples of the CMOS image sensor10(140) described above. The CMOS image sensor10(140) described above can be used in various cases of, for example, sensing light such as visible light, infrared light, ultraviolet light, and X-rays as is described below.Devices that take images used for appreciation, such as a digital camera and a portable appliance with a camera function.Devices used for traffic, such as an in-vehicle sensor that takes images of the front and the back of a car, surroundings, the inside of the car, and the like, a monitoring camera that monitors travelling vehicles and roads, and a distance sensor that measures distances between vehicles and the like, which are used for safe driving (e.g., automatic stop), recognition of the condition of a driver, and the like.Devices used for home electric appliances, such as a TV, a refrigerator, and an air conditioner, to takes images of a gesture of a user and perform appliance operation in accordance with the gesture.Devices used for medical care and health care, such as an endoscope and a device that performs angiography by reception of infrared light.Devices used for security, such as a monitoring camera for crime prevention and a camera for personal authentication.Devices used for beauty, such as skin measurement equipment that takes images of the skin and a microscope that takes images of the scalp.Devices used for sports, such as an action camera and a wearable camera for sports and the like.Devices used for agriculture, such as a camera for monitoring the condition of the field and crops. Note that the effects described in the present specification are merely examples, and not limitative; other effects may be exhibited. In addition, embodiments of the present disclosure are not limited to the above-described embodiments, and various alterations may occur insofar as they are within the scope of the present disclosure. For example, an embodiment of the present technology can also be applied to a semiconductor device in which a plurality of semiconductor chips are flip-chip bonded to each other, other than a CMOS image sensor. Additionally, the present technology may also be configured as below. (1) A semiconductor device including:a plurality of bumps on a first semiconductor substrate; anda lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps. (2) The semiconductor device according to (1),wherein the lens material is formed only in a pixel region on the first semiconductor substrate. (3) The semiconductor device according to (1),wherein the lens material is formed only in the region other than a region on the first semiconductor substrate that corresponds to a second semiconductor substrate configured to be bonded to the first semiconductor substrate via the bump. (4) The semiconductor device according to (3),wherein the lens material is formed to have an opening in a region on the first semiconductor substrate, the opening being larger than the second semiconductor substrate. (5) The semiconductor device according to (4), further including:an under-fill resin formed between the second semiconductor substrate and the first semiconductor substrate; anda dam that is formed on the first semiconductor substrate and prevents leakage of the under-fill resin to a region other than a region to which the second semiconductor substrate is bonded on the first semiconductor substrate,wherein the lens material is formed to have an opening in a whole region inside the dam on the first semiconductor substrate. (6) The semiconductor device according to (3), further including:an under-fill resin formed between the second semiconductor substrate and the first semiconductor substrate; anda dam that is formed on the first semiconductor substrate and prevents leakage of the under-fill resin to a region other than a region to which the second semiconductor substrate is bonded on the first semiconductor substrate,wherein the lens material is formed to have an opening in only a partial region inside the dam on the first semiconductor substrate. (7) The semiconductor device according to (3),wherein the lens material is formed to have an opening in a region on the first semiconductor substrate, the opening is smaller than the second semiconductor substrate. (8) The semiconductor device according to (1),wherein the side of the lens material closest to the bump is a side of an on-chip lens. (9) The semiconductor device according to (1), further including:an electrode pad for bump connection formed on the first semiconductor substrate and configured to be connected to the bump; andan electrode pad for wire bonding formed on the first semiconductor substrate and configured to be connected to a wire bonding,wherein a ratio of a distance between a side of an opening portion for wire bonding closest to the lens material and a side of the lens material closest to the opening portion for wire bonding to a size of the opening portion for wire bonding is smaller than a ratio of a distance between a side of an opening portion for a bump closest to the lens material and a side of the lens material closest to the opening portion for a bump to a size of the opening portion for a bump. (10) A method of manufacturing a semiconductor device, the method including:forming a plurality of bumps on a first semiconductor substrate, andforming a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps. (11) An electronic appliance including:a plurality of bumps on a first semiconductor substrate; anda lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps. (12) A semiconductor device including:a first semiconductor substrate having a rectangular shape;a second semiconductor substrate having a rectangular shape, wherein an area of the second semiconductor substrate is less than an area of the first semiconductor substrate and at least a region of a first edge of the second semiconductor substrate is flush with at least a region of a first edge of the first semiconductor substrate; and a third semiconductor substrate having a rectangular shape, wherein an area of the third semiconductor substrate is less than an area of the first semiconductor substrate and at least a region of a first edge of the third semiconductor substrate is flush with at least a region of a second edge of the first semiconductor substrate. (13) The semiconductor device according to (12),wherein the first semiconductor substrate includes an array of pixels,wherein the second and third semiconductor substrates each include at least one logic circuit,wherein each of the first edge of the first semiconductor substrate and the first edge of the second semiconductor substrate correspond to a scribe line forming a first edge of the stacked semiconductor device, andwherein each of the second edge of the first semiconductor substrate and the first edge of the third semiconductor substrate correspond to a scribe line forming a second edge of the stacked semiconductor device. (14) A method of manufacturing a semiconductor device, the method including:bonding a first semiconductor substrate including a plurality of logic circuits to second and third semiconductor substrates arrayed in a semiconductor wafer, where each of the second and third semiconductor substrates includes a pixel array, and wherein the first semiconductor substrate spans the second and third semiconductor substrates; andcutting a first edge of the first semiconductor substrate and a first edge of the second semiconductor substrate such that the first edge of the first semiconductor substrate and the first edge of the second semiconductor substrate are flush with one another. (15) The method of manufacturing the semiconductor device according to (14), further including:bonding a fourth semiconductor substrate including a plurality of logic circuits to the second semiconductor substrate and a fifth semiconductor substrate, wherein the fourth semiconductor substrate spans the second and fifth semiconductor substrates; andcutting a second edge of the second semiconductor substrate and a first edge of the fourth semiconductor substrate such that the second edge of the second semiconductor substrate and the first edge of the fourth semiconductor substrate are flush with one another. (16) An electronic appliance including:a first semiconductor substrate having a rectangular shape;a second semiconductor substrate having a rectangular shape, wherein an area of the second semiconductor substrate is less than an area of the first semiconductor substrate and at least a region of a first edge of the second semiconductor substrate is flush with at least a region of a first edge of the first semiconductor substrate; anda third semiconductor substrate having a rectangular shape, wherein an area of the third semiconductor substrate is less than an area of the first semiconductor substrate and at least a region of a first edge of the third semiconductor substrate is flush with at least a region of a second edge of the first semiconductor substrate. (17) A semiconductor device including:a first semiconductor substrate including a plurality of on-chip lenses corresponding to a plurality of pixels; anda second semiconductor substrate mounted to a light incident side of the first semiconductor substrate via one or more soldier bumps, wherein a size of the first semiconductor substrate is greater than a size of the second semiconductor substrate, and wherein the second semiconductor substrate is configured to receive one or more pixel signals from the first semiconductor substrate, process the one or more pixel signals, and output the processed one or more pixel signals. REFERENCE SIGNS LIST 10CMOS image sensor21pixel region11,12semiconductor chip13bump52electrode pad for wire bonding53A electrode pad for bump connection55under-fill resin56dam57lens material71opening portion for a bump72opening portion for wire bonding91to93region94opening region101distance102diameter103minimum value104size105distance120wire bonding123size124distance140CMOS image sensor141lower chip171north chip172south chip191to194side | 51,535 |
11862657 | DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description, a large number of particular specific configurations are described to provide a perfect understanding of an embodiment of the present invention. However, it is clear that the other embodiments can be implemented without being limited to such particular specific configurations. Moreover, the following embodiment does not limit the present invention according to Claims and includes all the combinations of characteristic configurations described in the embodiment. Hereinafter, one embodiment of the present invention is described with reference to the drawings. In the following description of the drawings, the same portions are designated by the same reference numerals. The drawings are schematically illustrated and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from the actual relationship, ratio, and the like. The embodiment of the present invention describes a case where a semiconductor package10according to one embodiment of the present invention is applied to a semiconductor package4acontained in a camera module2to be mounted in a mobile terminal1, such as a smartphone or a cellular phone illustrated inFIG.5. Although the case where the present invention is applied to the mobile terminal1is described herein, the present invention is applicable without being limited to the mobile terminal1and is applicable without being limited to the camera module. FIG.1is a plan view schematically illustrating an example of the semiconductor package10according to one embodiment of the present invention. The semiconductor package10according to one embodiment of the present invention is a WLCSP (Wafer Level Chip Size Package) and includes a wafer portion10aand a plurality of terminals t arranged on the side of the mounting surface of the wafer portion10aas illustrated inFIG.1. The semiconductor package10has a rectangular shape having an aspect ratio of about 2 or more and 4 or less as viewed in plan and has a short side length of 0.35 mm or more and 0.8 mm or less, for example. The “aspect ratio” indicates (Long side length/Short side length). The semiconductor package10includes the plurality of terminals t and the terminals t are arranged in zigzag and only two arrays are arranged in the width direction. The width of each terminal t is 0.15 mm or more and 0.3 mm or less. The width of the terminal t herein refers to the maximum value of the distance between the short sides facing each other when the terminal t is a rectangle as viewed in plan and refers to the diameter of a circle when the terminal t is a circle as viewed in plan.FIG.1illustrates a case where six terminals t1to t6are provided. Herein, when the terminals t having the same shape as the shape of the terminals t arranged on the semiconductor package10illustrated inFIG.1and having the same number as the number of the terminals t of the semiconductor package10are arranged in a lattice shape as illustrated inFIG.2, the terminals t need to be arranged at a certain degree of interval in relation to wiring and the like. More specifically, it is necessary to secure an interval ΔL in the width direction of the semiconductor package10between the array of the terminals t arranged on one side and the array of the terminals t arranged on the other side. On the other hand, when the terminals t are arranged in zigzag, the terminals t in the longitudinal direction of the semiconductor package10may be arranged in such a manner that the terminal t arranged on one side is present between the terminals t arranged on the other side. In this case, at least the interval ΔL may be secured between the terminal t on one side and the terminal t on the other side. Therefore, the interval ΔL may be secured not in the width direction of the semiconductor package10but in a direction crossing the width direction of the semiconductor package10between the terminal t1and the terminal t4, for example. Therefore, the distance in the width direction of the semiconductor package10between the terminal on one side and the terminal on the other side is shorter than the ΔL. Therefore, the width of the semiconductor package10is narrower in the case where the terminals t are arrange in zigzag as illustrated inFIG.1than in the case where the terminals t are arranged in the lattice shape as illustrated inFIG.2corresponding to the reduction in the interval in the width direction of the semiconductor package10between the terminals on one side and the terminals on the other side (L1<L2, in which L1indicates the width of the semiconductor package (zigzag arrangement)10illustrated inFIG.1and L2indicates the width of the semiconductor package (lattice shape arrangement) illustrated inFIG.2). More specifically, the size of the semiconductor package10can be reduced in the width direction. At this time, the terminal t of the semiconductor package illustrated inFIG.1and the terminal t of the semiconductor package10illustrated inFIG.2have the same shape and six terminals t are arranged in both the cases. Accordingly, by arranging the terminals t in zigzag as illustrated inFIG.1, the size of the semiconductor package10can be reduced in the width direction while maintaining the same terminal shape and the same number of terminals. Therefore, even when the size of the semiconductor package10is reduced in the width direction, a reduction in stability in mounting can be suppressed. When the terminals t are arranged in zigzag, the size of the semiconductor package10can be reduced in the width direction but, conversely, the length in the longitudinal direction increases as illustrated inFIG.1andFIG.2. Herein, as illustrated inFIG.3A, the constituent components contained in the camera module2, such as the semiconductor package10, are arranged around the lens3. More specifically, the constituent components are arranged around a lens position control mechanism performing position control of the lens3, such as an autofocus mechanism and a hand shake correction mechanism, as illustrated inFIG.6orFIG.7. Moreover, a unit of the camera module2comparatively has space in the longitudinal direction of the semiconductor package4aas illustrated inFIG.3A. Therefore, the size reduction in the longitudinal direction of the semiconductor package4adoes not contribute to the size reduction of the unit of the camera module2. Conversely, the width of the unit is mostly determined by the sum of the diameter of the lens3and the width of the semiconductor package4ain the unit of the camera module2as illustrated inFIG.3A. Therefore, the use of the semiconductor package10in which the size of the semiconductor package4ais reduced in the width direction as illustrated inFIG.3Bin place of the semiconductor package4acontributes to the size reduction of the camera module2. Therefore, as illustrated inFIG.1, the size reduction of the camera module2or the unit of the camera module2can be achieved by the use of the semiconductor package10in which the terminals t are arranged in zigzag. More specifically, an increase in the aperture of the lens3can be achieved without increasing the size of the camera module2and the enhancement of the performance of the camera module2and the reduction in the thickness of the mobile terminal1mounted with the camera module2can be achieved. Moreover, the width of the semiconductor package10can be reduced by arranging the terminals t in zigzag as described above. Therefore, when the size of a unit, such as the unit of the camera module2, is determined by the width of a semiconductor package, the size reduction of the unit can be achieved by the use of the semiconductor package10according to one embodiment of the present invention as the semiconductor package. Moreover, the space between the terminals t is comparatively larger in the semiconductor package10in which the terminals t are arranged in zigzag illustrated inFIG.1than in the semiconductor package10in which the terminals t are arranged in the lattice shape illustrated inFIG.2. Therefore, the routing of wiring can be further facilitated. For example, the degrees of freedom of the arrangement positions of electronic components mounted in the semiconductor package10, such as the sensor4for position detection, and the routing of wiring are higher. When a hall element is used as the sensor4for position detection and wiring for current supply is connected to any two terminals t of the terminals t1to t6in the semiconductor package10illustrated inFIG.1, there is a possibility that, when the wiring for current supply and the hall element are close to each other, for example, the hall element is affected by a leak magnetic field and the like due to the flow of a current through the wiring for current supply, which leads to a reduction in the detection accuracy of the sensor4for position detection. However, the semiconductor package10illustrated inFIG.1has higher degree of freedom of the arrangement position of the sensor4for position detection and the routing of wiring. Therefore, the reduction in the detection accuracy of the sensor4for position detection can be prevented by performing the arrangement of the sensor4for position detection and the routing of wiring in such a manner as to reduce the influence of the leak magnetic field and the like on the sensor4for position detection due to the flow of a current through the wiring for current supply. For example, by arranging the sensor4for position detection and the wiring for current supply to be apart from each other as far as possible, by setting the directions where a current flows to be opposite to each other between a pair of wiring for current supply to offset the leak magnetic field, or the like, the influence caused by the leak magnetic field given to the sensor4for position detection may be reduced. Moreover, also when the arrangement positions of the sensor4for position detection and the like need to be determined in consideration of the influence of the leak magnetic field of wiring, the degree of freedom of the arrangement position of the sensor4for position detection can be made higher because the degree of freedom of the routing of wiring is high in the semiconductor package10according to one embodiment of the present invention. Moreover, in the semiconductor package10according to one embodiment of the present invention, the terminals t are arranged in two arrays in the width direction and are arranged in zigzag as illustrated inFIG.1. More specifically, as viewed from the terminals t belonging to one array in the longitudinal direction of the semiconductor package10, the terminals belonging to the next array are present in the obliquely upward direction or in the obliquely downward direction and are not present in the horizontal direction. Therefore, the wiring can be routed in the horizontal direction of the terminal t, and thus the routing of wiring is not limited. Furthermore, the semiconductor package10can be more stably mounted in the case where the terminals t are arranged in the two arrays than in the case where the terminals t are arranged only in one array. Moreover, when the terminals t are arranged in zigzag in the two arrays, the arrangement positions of the terminals t belonging to one array and the terminals t belonging to the other array approach the positions on the same straight line with a reduction in the interval in the width direction of the semiconductor package10between the terminals t belonging to one array and the terminals t belonging to the other array, and thus the stability in mounting decreases. Conversely, the stability in mounting increases with an increase in the interval in the width direction of the semiconductor package10between the terminals t belonging to one array and the terminals t belonging to the other array but the width of the semiconductor package10increases. Therefore, when the terminals t are arranged in zigzag, the terminals t need to be arranged at positions where both the stability in mounting and the width of the semiconductor package10are satisfied. In the semiconductor package10according to one embodiment of the present invention, the terminals t1to t3belonging to one array and the terminals t4to t6belonging to the other array are arranged to be in contact with a line segment M passing through the center in the width direction of the semiconductor package10as illustrated inFIG.1. Therefore, the semiconductor package10in which the stability in mounting is not excessively poor and in which the width of the semiconductor package10can be reduced to some extent can be obtained. Although the terminals t are arranged in zigzag to be in contact with the line segment M inFIG.1, the arrangement is not limited thereto and the terminals t may be arranged at positions where the stability can be obtained in mounting and the width of the semiconductor package10is a desired value. More specifically, the terminals t may be arranged to be overlapped with the line segment M as viewed in plan to a degree such that the stability in mounting can be obtained or, conversely, the terminals t may be arranged at positions to be somewhat apart from the line segment M to a degree such that the width of the semiconductor package10can be reduced to some extent. Moreover, the electronic components mounted in the semiconductor package10, such as the sensor4for position detection, are preferably arranged at a position apart from the terminals t when the influence of a stress is taken into consideration, for example. When the sensor4for position detection is arranged in a central portion of the semiconductor package10as illustrated inFIG.1, for example, the interval between the sensor4and the terminals t is longer and the width of the semiconductor package10is smaller in the semiconductor package10in which the six terminals t are arranged in zigzag illustrated inFIG.1than in the semiconductor package10in which the six terminals are arranged in the lattice shape illustrated inFIG.2. Accordingly, the width of the semiconductor package10can be made narrower while reducing the influence of a stress. Moreover, the width of the semiconductor package10is narrower but the length in the longitudinal direction of the semiconductor package10is longer in the semiconductor package10according to one embodiment of the present invention than in the semiconductor package10in which the terminals t are arranged in the lattice shape as described above. Therefore, the present invention is suitable for a semiconductor package to be arranged in the portion where there is much space in the longitudinal direction but there is not much space in the width direction of the semiconductor package10. FIG.1describes that the terminals t are arranged in zigzag. However, when described in detail, the terminals t of the semiconductor package10are arranged in such a manner that (a) arbitrary three terminals (hereinafter also referred to as three terminals) are individually arranged in such a manner that each center of the three terminals t in the longitudinal direction of the semiconductor package10is not overlapped each other, and each center of the three terminals t in the longitudinal direction of the semiconductor package10and each center of the other terminals t arranged on the semiconductor package10in the longitudinal direction of the semiconductor package10are not overlapped with each other as viewed from the side of the long side of the semiconductor package10and one terminal t among the three terminals t (inFIG.1, terminal t, the position in the longitudinal direction of which is the center) and the other two terminals are present on mutually different sides across the line segment M passing through the center in the width direction of the semiconductor package10, (b) an angle θ formed by two line segments connecting the gravity of the terminal t positioned in a center in the longitudinal direction of the semiconductor package10among the three terminals t and the gravity of each of the other two terminals t is equal to or larger than a threshold value (for example, about 60°), and further (c) the width L1of the semiconductor package10and the distance Lt between the rightmost end position of the terminal t arranged at the rightmost end position in the width direction of the semiconductor package10among the three terminals t and the leftmost end position of the terminal t arranged at the leftmost end position in the width direction satisfy Lt/L1≥0.5. More specifically, among the arbitrary three terminals t, e.g., the terminals t1, t2, and t4, the terminal t1, for example, is arranged in such a manner that each of the center in the longitudinal direction of the semiconductor package10of the terminals t1, t2and t4is not overlapped each other and each of the center in the longitudinal direction of the semiconductor package10of the terminals (terminals t1, t2and t4in the case ofFIG.4) and each of the other terminals t (t3, t5, t6) arranged on the semiconductor package10are not overlapped with each other as viewed from the side of the long side of the semiconductor package10and the other two terminals t2and t4among the three terminals t are similarly arranged as illustrated inFIG.4. Furthermore, with respect to the three terminals t1, t2, and t4, the terminals t1and t2are arranged on the left side across the line segment M and the terminal t4is arranged on the right side across the line segment M as illustrated inFIG.4. Moreover, the angle θ formed by the line segment connecting the gravity of the terminal t4positioned in a center in the longitudinal direction of the semiconductor package10, among the three terminals and the gravity of the terminal t1and the line segment connecting the gravity of the terminal t4and the gravity of the terminal t2is equal to or larger than the threshold value and the width L1of the semiconductor package10and the distance Lt between the leftmost end position of the terminal t1or t2and the rightmost end position of the terminal t4satisfy Lt/L1≥0.5. The description “present on mutually different sides across the line segment M passing through the center in the width direction of the semiconductor package10” means that the centers of gravity of the terminals t1, t2, and t4are present on different sides across the line segment M. The description “arranged in such a manner that each of the center in the longitudinal direction of the semiconductor package10of the three terminals t is not overlapped and each of the centers in the longitudinal direction of the semiconductor package10of the three terminals t and each center in the longitudinal direction of the semiconductor package10of the other terminals t arranged on the semiconductor package10are not overlapped with each other as viewed from the side of the long side of the semiconductor package10” namely means that the three terminals t1, t2, and t4may be arranged in such a manner that the wiring is not blocked by the other terminals t even when connected by drawing out the wiring from either the right or left side with respect to the three terminals t1, t2, and t4. Due to the fact that the three terminals t1, t2, and t4are arranged as described above, the degree of freedom of the routing of wiring on the semiconductor package10can be secured. For example, the terminals t are arranged in such a manner that the interval between the centers in the longitudinal direction of the terminals t as viewed from the side of the long side of the semiconductor package10is 100 μm or more. The upper limit of the interval is not specified. However, the terminals t are arranged in such a manner that the interval between the centers in the longitudinal direction of the terminals t as viewed from the side of the long side of the package10is smaller than the long side of the semiconductor package10. Herein, when focused on the three terminals t1, t2, and t4, the terminal t4is arranged on the right side and the terminals t1and t2are arranged on the left side across the line segment M and the numbers of the terminals t on the right and left sides are different from each other as illustrated inFIG.4. More specifically, from the viewpoint of the number of the terminals t, the stability in the horizontal direction across the line segment M appears lower than in the case where the numbers of the terminals t on the right and left sides across the line segment M are the same. However, the three terminals, t1, t2, and t4are arranged so that the angle θ formed by the line segment connecting the terminals t1and t4and the line segment connecting the terminals t2and t4is equal to or larger than a threshold value and the angle θ based on the terminal t4positioned at the center in the longitudinal direction of the semiconductor package10is equal to or larger than a threshold value. Therefore, although the numbers of the terminals t on the right and left sides across the line segment M are different from each other, the stability in the horizontal direction can be secured and the stability also in the longitudinal direction can be secured. More specifically, even when the number of the terminals t is set to 3, the stability in the horizontal direction can be sufficiently secured. Therefore, even when the number of terminals is 3, the stability in mounting of the semiconductor package10can be secured. More specifically, the number of the terminals t to be provided on the semiconductor package10may be at least 3 from the viewpoint of the stability in mounting and therefore there is no necessity of providing an unnecessary terminal, and thus the size in the longitudinal direction of the semiconductor package10can also be correspondingly reduced. When the three terminals t satisfying the above-described arrangement conditions (a) to (c) or a comparatively small number of terminals t including the three terminals t are provided on the semiconductor package10, the two terminals t among the three terminals t satisfying the above-described arrangement conditions (a) to (c) are preferably individually arranged in the vicinity of both ends in the longitudinal direction of the semiconductor package10. Moreover, the terminals t1, t2, and t4are arranged in such a manner that the distance Lt between the rightmost end of the terminal t4and the leftmost end of the terminals t1and t2and the width L1of the semiconductor package10satisfy Lt/L1≥0.5 and the terminals t1, t2, and t4are arranged in such a manner that the distance Lt in the horizontal direction between the terminals t1, t2, and t4is at least ½ or more of the width L1of the semiconductor package10. Therefore, the stability in mounting in the horizontal direction can be further secured. In the three terminals t1, t2, and t4, the distance in the longitudinal direction between the terminals t1and t4may be different from the distance in the longitudinal direction between the terminals t2and t4as viewed in plan. Moreover, the terminals t1and t2do not necessarily need to be arranged on the same straight line along the longitudinal direction of the semiconductor package10and the terminal t2may be arranged at a position close to the line segment M or on the line segment M as viewed in plan. Although the terminal t4, the position in the longitudinal direction of the semiconductor package10is the center, among the terminals t1, t2, and t4is arranged on the right side across the line segment M and the remaining terminals t1and t2are arranged on the left side across the line segment M as the arrangement satisfying the above-described arrangement condition (a) inFIG.4, the arrangement is not limited thereto. For example, inFIG.4, the terminal t1, the terminal t4, and the terminal t5instead of the terminal t2may be set as one set of the three terminals t satisfying the above-described arrangement conditions (a) to (c). More specifically, the terminal t1, the position in the longitudinal direction of the semiconductor package10of which is an end portion, may be arranged on the left side across the line segment M and the remaining terminals t4and t5may be arranged on the right side across the line segment M. However, it is more preferable from the viewpoint of the stability in the width direction of the semiconductor package10that the terminal t4, the position in the longitudinal direction of the semiconductor package10is the center, is arranged on one side across the line segment M and the remaining two terminals are arranged on the other side across the line segment M as in the terminals t1, t2, and t4. When four or more terminals t are arranged, the other terminals t except the three terminal t1, t2, and t4satisfying the above-described arrangement conditions (a) to (c) may be arranged at positions where the center in the longitudinal direction of the semiconductor package10of each of the three terminals t1, t2, and t4is not overlapped each other, and the center in the longitudinal direction of the semiconductor package10of each of the three terminals t1, t2, and t4and the center in the longitudinal direction of the semiconductor package10of each of the other terminals t except the three terminals t1, t2, and t4are not overlapped with each other as viewed from the side of the long side of the semiconductor package10. For example, in the set of the three terminals t1, t4, and t5satisfying the above-described arrangement conditions (a) to (c), the terminal t may be arranged at the position of the t2inFIG.4. In this case, the center in the longitudinal direction of the semiconductor package10of each of the terminals t1, t4, and t5and the center in the longitudinal direction of the semiconductor package10of the terminal t2are not overlapped with each other as viewed from the side of the long side of the semiconductor package10. Moreover, a new terminal may be arranged between the terminal t5and a terminal t6inFIG.4. It is preferable from the viewpoint of the degree of freedom of the routing of wiring that all the terminals t arranged on the semiconductor package10containing the three terminal t1, t2, and t4, for example, satisfying the above-described arrangement conditions (a) to (c) are arranged at positions where the centers in the longitudinal direction of the semiconductor package10of the terminals t are not overlapped with each other as viewed from the side of the long side of the semiconductor package10. The terminals t may not be arranged at equal intervals in the longitudinal direction. The other terminals t except the three terminal t1, t2, and t4may also be arranged to satisfy the arrangement conditions (a) to (c) as with the three terminals t1, t2, and t4while forming one set by the three terminals t. More specifically, the terminals t may be arranged so that two or more of the sets of the terminals t satisfying the arrangement conditions (a) to (c) may be present. Moreover, the terminals t may be arranged to satisfy the arrangement conditions (a) to (c) in each of all the combinations obtained by selecting three terminals t containing two terminals t arranged on the right and left sides across the line segment M. When two or more of the sets of the three terminals t satisfying the arrangement conditions (a) to (c) are arranged, one set is preferably arranged in the vicinity of each of both ends in the longitudinal direction of the semiconductor package10. When a plurality of number of the terminals t are arranged in such a manner as to satisfy the arrangement conditions (a) to (c), it is preferable to arrange the terminals t so that the sum of the number of the terminals t arranged on each of the right and left sides across the line segment M is the same. By arranging the terminals t as described above, also due to the fact that the numbers of the terminals t on the right and left sides are equal to each other, the stability in mounting of the semiconductor package10can be improved. Although the embodiment described above describes the case where the six terminals t are provided, the number of the terminals t is not limited to six and the present invention is applicable even in the case of the semiconductor package10including an arbitrary number, 4 or more and 10 or less, of the terminals t, such as four terminals t, six terminals t, eight terminals t, and ten terminals t. The number of the terminals t is preferably an even number to stabilize the balance in the width direction of the semiconductor package10in mounting. The sensor4for position detection is not limited to the case of being mounted in the semiconductor package10and may be formed separately from the semiconductor package10. The semiconductor package10may be stored in the unit as illustrated inFIG.7and may be arranged on the outside of a member supporting the lens3as with the coil5or the magnet6as illustrated inFIG.6. The semiconductor package10is not limited to one mounted with the sensor4for position detection and may be mounted with the other electronic components. As described above, the embodiment of the present invention is described but the above-described embodiment describes devise and methods for embodying the technical idea of the present invention and the technical idea of the present invention does not specify the materials, shapes, structures, arrangement, and the like of constituent components. The technical idea of the present invention can be variously altered within the technical scope specified by Claims. Description of Reference Numerals 1mobile terminal2camera module3lens4sensor for position detection4asemiconductor package5coil6magnet10semiconductor package10awafer portiont1to t6terminal | 29,812 |
11862658 | Elements present in more than one of the figures are given the same reference in all of them. The description begins with a filter module that has a plurality of generally identical filter cells formed on a substrate SUB. With reference toFIGS.2aand2b, a filter cell comprises three interference filters of the Fabry-Pérot type FP1, FP2, FP3in successive alignment so as to form a strip. The cell is constituted by a stack on said substrate SUB of the filter module, the substrate being made of glass, or of silica, or of silicon, for example, and the stack being made up of a first mirror MIR1, of a spacer SP, and of a second mirror MIR2. The spacer SP, which defines the central wavelength of each filter, is thus constant for any given filter and varies from one filter to another. Its profile is staircase-shaped since each filter has a surface that is substantially rectangular. An advantageous method of making the filter module using thin layer technology is given by way of example. With reference toFIG.3a, the method starts by depositing the first mirror MIR1on the substrate SUB, followed by a dielectric layer or a set of dielectric layers TF for defining the spacer SP. The mirror is either metallic or dielectric. With reference toFIG.3b, the dielectric TF is etched:initially at the second and third filters FP2and FP3, in order to define the thickness of the spacer SP at the second filter FP2; andsubsequently at the third filter FP3, in order to define the thickness of said spacer at the third filter. At the first filter FP1, the spacer SP has the deposition thickness. With reference toFIG.3c, the second mirror MIR2is deposited on the spacer SP in order to finalize the three filters. The spacer SP may be obtained by depositing a dielectric TF followed by successive etching as described above, but it may also be obtained by depositing a plurality of thin layers in succession. By way of example, it is possible to scan the range of wavelengths from 900 nm to 2000 nm by modifying the optical thickness of the spacer. It should be observed at this point that the thickness of the spacer needs to be small enough to obtain only one transmission band in the range to be probed. Specifically, the greater the thickness, the greater the number of wavelengths that satisfy the condition [ne=k λ/2]. The invention thus enables a set of aligned filters to be made, which filters can thus be referenced in one-dimensional space. With reference toFIG.4, the invention also enables the filter cells to be organized in two-dimensional space. Such an organization is often referred to as a matrix organization. Each one of four identical horizontal strips comprises four cells. The first strip, i.e. the strip that is shown at the top of the figure, corresponds to the first row of a matrix and comprises cells IF11to IF14. The second, third, and fourth strips respectively comprise cells IF21to IF24, filters IF31to IF34, and cells IF41to IF44. The organization is said to be a matrix organization because cell IFjk belongs to the jthhorizontal strip and also to a kthvertical strip that comprises cells IF1k, IF2k, . . . , IF4k. With reference toFIG.5, it is desirable for the various filters of the filter module to be well separated in order to avoid partial overlap of one filter on a filter adjacent to it, and in order to minimize any problem of crosstalk. To achieve this, it is possible to add a grid over the filter module (the grid being shown in black in the figure) so as to form a crosstalk barrier for delimiting all of the filters. The grid should be absorbent. By way of example, an absorbent grid may be made by depositing and etching a black chromium (chromium+chromium oxide) while a reflective grid may be made by depositing and etching chromium. With reference toFIG.6, each filter cell now has 9 filters. Each of these cells is in the form of a square within which a corresponding filter lies that is tuned to a distinct wavelength λ1, λ2, λ3, λ4, . . . , λ9. In this figure, for reasons of clarity, the spacing between the cells has been voluntarily increased compared with the spacing between two filters. Naturally, in reality, these spacings are identical. The filter module is thus associated with a detector capable of measuring the light fluxes produced by the various filters. With reference toFIG.7, the filter module MF that is shown inFIG.6is reproduced. The detector DET is made using InGaAs technology on an InP substrate as described in the introduction of the present application. The filter module MF comes to bear against the detector DET in contact with the InP substrate so that the filters λ1, λ2, λ3are facing the pixels P1, P2, P3and are interposed between the InP substrate of the detector DET and the substrate SUB of the filter module. In this way, the distance separating the pixels from the filters is minimized, and can be reduced to the thickness of the InP substrate, and crosstalk is also minimized. Positioning this module MF is performed by means of alignment patterns, which is a technique known to the person skilled in the art of photolithography and is therefore not described in any further detail below. The filter module MF is fastened to the detector DET by means of a margin of adhesive ST. In particular, the filter module MF is made on a first type of substrate, e.g. made of glass, silica, or silicon, and the detector DET is made on a second type of substrate, which is made of InP in this example, these two elements as assembled together forming the hybrid structure of the imaging sensor. For reasons of clarification, it is specified that the pixels commonly have a size of about 15 micrometers. Furthermore, it is naturally well understood that the InP substrate100needs to be made thinner. To achieve this, two solutions are proposed. The first solution consists in polishing the substrate mechanically down to a thickness of approximately in the range 20 μm to 30 μm. In the second solution, with reference toFIG.8, a stop layer108is grown on the InP substrate, and then a thin layer109of InP is grown on the stop layer by epitaxy. The active layer103of InGaAs is then grown on said thin layer109. It is thus necessary to etch the substrate100to the stop layer108by selective etching, and then to etch said stop layer also by selective etching. This results in obtaining the required thickness for the InP backing109. The above-described embodiments of the invention have been chosen because of their concrete nature. However, it is not possible to list exhaustively all possible embodiments covered by the invention. In particular, it is naturally possible to replace any of the means described by equivalent means without going beyond the ambit of the present invention. | 6,795 |
11862659 | DESCRIPTION OF EMBODIMENTS Hereinafter, one embodiment will be described in detail with reference to the drawings. In each figure, the same or corresponding elements may be designated by the same reference symbols, and duplicate description may be omitted. FIG.1is a schematic view illustrating a backside incident-type imaging element according to the present embodiment.FIG.1(a)is a plan view, andFIG.1(b)is a schematic cross-sectional view.FIG.2is a detailed cross-sectional view of the backside incident-type imaging element illustrated inFIG.1. As illustrated inFIGS.1and2, the backside incident-type imaging element1includes a first element part3and a second element part5. The first element part3is, for example, a CCD (charge coupled device) unit responsible for light reception and charge transfer, and the second element part5is, for example, a CMOS (complementary metal oxide semiconductor) unit responsible for signal processing such as analog-digital conversion. That is, the backside incident-type imaging element1is, for example, a monolithic CCD-COMS sensor. An example of a size of the backside incident-type imaging element1is about 20 mm in a longitudinal direction and about 10 mm in a short direction in a plan view. The backside incident-type imaging element1includes a semiconductor substrate10, a semiconductor layer30, a first insulating layer40, and a second insulating layer50. The semiconductor substrate10includes a front surface10aand a back surface10bon the opposite side from the front surface10a. The semiconductor substrate10has, for example, a P-type conductive type, and is, for example, a silicon substrate. The semiconductor layer30is formed on the front surface10aof the semiconductor substrate10. The semiconductor layer30has, for example, a P-type conductive type, and is, for example, an epitaxial growth layer containing silicon. The first element part3and the second element part5are configured in the semiconductor layer30. A thickness of the semiconductor layer30is, for example, about 10 μm. The first element part3includes a light receiving portion (pixel portion)13and an amplifier15. The light receiving portion13includes, for example, a plurality of two-dimensionally arranged pixels, and generates a signal charge according to incident light hν from the back surface10bside of the semiconductor substrate10. The amplifier15changes the signal charge generated by the light receiving portion13into a signal voltage. The light receiving portion13and the amplifier15are electrically connected to each other by a wiring W1. An example of a size of the light receiving portion13is about 7 mm×7 mm in a plan view. In addition, an example of a size of the amplifier15is about 7 mm in the longitudinal direction and about 20 μm in the short direction (direction from the light receiving portion13toward a analog-digital converter17described later) in a plan view. Further, the wiring W1and a wiring W3described later are provided on both sides of the amplifier15. However, an example of a length of the wiring W1is about 50 μm, and a length of the wiring W3is about 150 μm. Note that the wiring W1may be a transfer electrode. As described above, each of the lengths of the wiring W1and the wiring W3is larger than the size of the amplifier15in the short direction. That is, each of a distance between the light receiving portion13and the amplifier15and a distance between the amplifier15and the analog-digital converter17described later is larger than the size of the amplifier15in the short direction. The second element part5includes the analog-digital converter17, a multiplexer19, a drive unit21, and an output unit23. The analog-digital converter17converts a signal voltage output from the first element part3into a digital signal. The multiplexer19bundles a plurality of digital signals from the analog-digital converter17into one digital signal. The drive unit21includes, for example, a phase-locked loop (PLL) and a timing generator, and generates a signal for driving the analog-digital converter17. The output unit23includes, for example, an LVDS (Low Voltage Differential signaling) unit, converts a digital signal from the multiplexer19into a differential voltage signal, and outputs the converted signal to the outside. The amplifier15and the analog-digital converter17are electrically connected to each other by the wiring W3, and the analog-digital converter17and the multiplexer19are electrically connected to each other by a wiring W5. Further, the analog-digital converter17and the drive unit21are electrically connected to each other by a wiring W7, and the multiplexer19and the output unit23are electrically connected to each other by a wiring W9. The first insulating layer40is formed on a front surface of the semiconductor layer30on the opposite side from the semiconductor substrate10via an insulating film45such as a silicon oxide film. The first insulating layer40is, for example, a BPSG (Boron Phospho Silicate Glass) layer. A thickness of the first insulating layer40is, for example, about 1 μm. The second insulating layer50is formed on a front surface of the first insulating layer40on the opposite side from the semiconductor layer30. The second insulating layer50contains, for example, a silicon oxide (for example, SiO2). A thickness of the second insulating layer50is, for example, about 1 μm. In the backside incident-type imaging element1described above, when the incident light hν is incident on the light receiving portion13, the incident light hν is converted into a signal charge at each pixel of the light receiving portion13. The signal charge is transferred between pixels and converted into a signal voltage by the amplifier15provided at an end of the light receiving portion. The signal voltage is converted into a digital signal in the analog-digital converter17. Digital signals are bundled by the multiplexer19to form one digital signal. This digital signal is converted into a differential voltage signal by the output unit23and output. Subsequently, a structure of each layer will be described. In the semiconductor layer30, an N-type channel region31, a P-type well region32, and a P+-type region33are formed in the first element part3. A pair of N+-type regions37is formed in each of the N-type channel region31and the P-type well region32. A part of the N-type channel region31is used for the light receiving portion13. A rest of the N-type channel region31and the P-type well region32are used for the amplifier15. Note that the P+-type means that the concentration of P-type impurities is as high as, for example, about 1×1017cm−3or more. Further, the N+-type means that the concentration of N-type impurities is as high as, for example, about 1×1020cm−3or more. Further, in the semiconductor layer30, an N-type deep well region34is formed in the second element part5. A P-type well region35and an N-type well region36are formed in the N-type deep well region34. A plurality of N+-type regions37is formed in the P-type well region35. A plurality of P+-type regions39is formed in the N-type well region36. Further, in the second element part5, a P+-type region39is formed outside the N-type deep well region34, and a ground GND is electrically connected to the P+-type region39. In this way, a ground potential is applied to the semiconductor substrate10via the P+-type region39and the P-type semiconductor layer30. The P+-type region39and the N+-type regions37are exposed on the front surface of the semiconductor layer30via the insulating film45. A plurality of wiring portions41is formed inside the first insulating layer40. The wiring portions41contain, for example, polysilicon. The wiring portions41are formed on the semiconductor layer30side, and are formed to come into contact with the semiconductor layer30via the insulating film45. A plurality of metal wiring portions51is formed inside the second insulating layer50. The metal wiring portions51contain, for example, aluminum, etc. The metal wiring portions51may provide, for example, the wirings W1to W9described above. Here, the semiconductor substrate10includes a first region10A, a second region10B, and a third region10C. The first region10A is a region corresponding to the light receiving portion13. In other words, the first region10A is a region including the light receiving portion13when viewed in a first direction intersecting with (orthogonal to) the front surface10aand the back surface10b. The second region10B is a region corresponding to the analog-digital converter17. In other words, the second region10B is a region including the analog-digital converter17when viewed in the first direction. The third region10C is located between the first region10A and the second region10B. Further, a thickness of the semiconductor substrate10in the first direction (distance between the front surface10aand the back surface10b) is relatively thicker in the second region10B than in the first region10A. This point will be described in more detail. A recess60recessed on the front surface10aside from the first region10A to the third region10C is formed on the back surface10bof the semiconductor substrate10. In this way, the thickness of the semiconductor substrate10is made relatively thinner in the first region10A than in the second region10B. On the other hand, in the second region10B, the thickness of the semiconductor substrate10is maintained. That is, the semiconductor substrate10is thinned in the region corresponding to the light receiving portion13, and an original thickness (for example, 300 μm) thereof remains in the region corresponding to the analog-digital converter17. In particular, here, the recess60penetrates the semiconductor substrate10(that is, a bottom surface61of the recess60serves as the front surface of the semiconductor layer30). In other words, the thickness of the semiconductor substrate10is set to 0 at least in the first region10A. In other words, at a bottom of the recess60, the semiconductor layer30is exposed from the semiconductor substrate10. An inner side surface of the recess60includes an inclined surface63located in the third region10C and is inclined so that the thickness of the semiconductor substrate10gradually (continuously) increases from the first region10A to the second region10B. The inclined surface63does not reach the second region10B when viewed in the first direction. The amplifier15(and the wirings W1and W3) is disposed on the third region10C including the inclined surface63. That is, the amplifier15is located in the third region10C including the inclined surface63when viewed in the first direction. The recess60can be formed, for example, by etching, etc. Note that a width of the third region10C in a direction from the first region10A to the second region10B is a total length of the amplifier15, the wiring W1, and the wiring W2described above, and is, for example, about 220 μm. By ensuring the width of the third region10C to this extent, it is possible to maintain the thickness of the semiconductor substrate10over the entire second region10B without causing the inclined surface63to reach the second region10B. Note that here, the third region10C includes a part in which a thickness changes according to inclination of the inclined surface63and a part in which the thickness is constant with the thickness of the second region10B. Further, the semiconductor substrate10includes a fourth region10D. The fourth region10D is located on the opposite side of the second region10B from the first region10A and the third region10C. The fourth region10D is a region corresponding to a part of the second element part5other than the analog-digital converter17. Here, the fourth region10D mainly includes the multiplexer19and the output unit23when viewed in the first direction. Further, the thickness of the semiconductor substrate10is constant with the thickness of the second region10B in the fourth region10D. In addition, a frame10cin which the thickness of the second region10B is maintained is formed at an outer peripheral portion of the backside incident-type imaging element1(here, an outer edge of the first region10A). Note that an antireflection film71is formed on the back surface10bof the semiconductor substrate10, including an inner surface of the recess60. The antireflection film71contains, for example, a silicon oxide (for example, SiO2). A thickness of the antireflection film71is, for example, about 0.1 μm. Further, a light-shielding film73is formed on the antireflection film71. The light-shielding film73is, for example, aluminum. A thickness of the light-shielding film73is, for example, about 1 μm. An opening is formed in the light-shielding film73on the bottom surface61of the recess60, and the light receiving portion13is exposed from the opening when viewed in the first direction. The opening of the antireflection film71provides an incident portion of the incident light hν on the light receiving portion13. Further, a P+-type region38is formed in an area corresponding to the bottom surface61of the recess60in the semiconductor layer30. As described above, in the backside incident-type imaging element1, the semiconductor layer30formed on the front surface10aof the semiconductor substrate10has the first element part3and the second element part5. The first element part3includes the light receiving portion13that generates a signal charge according to the incident light hν from the back surface10bside of the semiconductor substrate10. Further, the second element part5includes the analog-digital converter17that converts a signal voltage into a digital signal. In addition, the thickness of the semiconductor substrate10is relatively thicker in the second region10B corresponding to the analog-digital converter17than in the first region10A corresponding to the light receiving portion13. In other words, the semiconductor substrate10is thin in the region corresponding to the light receiving portion13and thickened in the region corresponding to the analog-digital converter17. As a result, the amount of light incident on the light receiving portion13from the first region10A of the semiconductor substrate10is increased, and the resistance of the second region10B corresponding to the analog-digital converter17of the semiconductor substrate10can be avoided. Therefore, according to the backside incident-type imaging element1, the processing speed can be improved by achieving both high sensitivity and stabilization of the ground. Further, in the backside incident-type imaging element1, the semiconductor substrate10includes the third region10C located between the first region10A and the second region10B when viewed in the first direction. In addition, the thickness of the semiconductor substrate10is made relatively thinner in the first region10A than in the second region10B by the recess60provided on the back surface10bfrom the first region10A to the third region10C. Further, in the backside incident-type imaging element1, the inner side surface of the recess60includes the inclined surface63located in the third region10C and inclined so that the thickness of the semiconductor substrate10gradually increases from the first region10A to the second region10B. In this way, it is possible to make the first region10A thinner and the second region10B thicker by the recess60provided on the back surface10bof the semiconductor substrate10. Further, since the inner side surface of the recess60has the inclined surface63(since the inclined surface63reaches an opening end of the recess60), the open end of the recess60is obtuse. In this way, occurrence of chips and cracks at the opening end of the recess60is suppressed, and as a result, damage to the backside incident-type imaging element1is suppressed. Further, in the backside incident-type imaging element1, the first element part3includes the amplifier15that converts the signal charge generated by the light receiving portion13into a signal voltage. Further, the amplifier15is located in the third region10C when viewed in the first direction. In this way, the amplifier15rarely affected by the thickness of the semiconductor substrate10can be disposed in the third region10C. Furthermore, in the backside incident-type imaging element1, the semiconductor layer30is exposed from the semiconductor substrate10at the bottom of the recess60. Therefore, the amount of incident light from the first region10A to the light receiving portion13can be further increased. The embodiment has described one aspect of the disclosure. Therefore, the disclosure is not limited to the backside incident-type imaging element1described above, and various modifications are possible. Hereinafter, modifications will be described. FIGS.3and4are schematic views illustrating backside incident-type imaging elements according to first and second modifications. As illustrated inFIG.3, a backside incident-type imaging element1A according to the first modification is the same as the backside incident-type imaging element1in a plan view (which is similarly applied hereinafter when viewed in the first direction), and is different from the backside incident-type imaging element1only in a cross-sectional shape of the semiconductor substrate10. That is, in the backside incident-type imaging element1A, the recess60is enlarged when compared to the backside incident-type imaging element1. More specifically, in the backside incident-type imaging element1A, the recess60is formed over the entire third region10C, and the third region10C does not include a part in which the thickness is constant with the thickness of the second region10B. In this way, the semiconductor substrate10is thinned by the recess60in the entire third region10C. That is, in this example, the semiconductor substrate10is thinned including the region corresponding to the amplifier15. In addition, as illustrated inFIG.4, a backside incident-type imaging element1B according to the second modification is the same as the backside incident-type imaging elements1and1A in a plan view, and is different from the backside incident-type imaging elements1and1A only in a cross-sectional shape of the semiconductor substrate10. That is, the backside incident-type imaging element1B is different from the backside incident-type imaging element1A in that the thickness is relatively thicker in the second region10B than in the fourth region10D. More specifically, in the backside incident-type imaging element1B, the thickness of the semiconductor substrate10is relatively thinner in the fourth region10D than in the second region10B by providing a recess80on the back surface10bof the semiconductor substrate10. That is, in this example, in the semiconductor substrate10, only the region corresponding to the analog-digital converter17is thickened, and a region corresponding to elements other than the analog-digital converter17is thinned. Here, the recess80penetrates the semiconductor substrate10(that is, the bottom surface81of the recess80becomes the front surface of the semiconductor layer30). In other words, the thickness of the semiconductor substrate10is set to 0 in the fourth region10D. Further, in other words, at the bottom of the recess80, the semiconductor layer30is exposed from the semiconductor substrate10. The inner side surface of the recess80includes an inclined surface83located in the fourth region10D and inclined so that the thickness of the semiconductor substrate10gradually (continuously) increases from the fourth region D to the second region10B. As in the backside incident-type imaging elements1A and1B, the semiconductor substrate10may be configured such that the thickness of the second region10B corresponding to (immediately below) the analog-digital converter17is relatively thick, and the thickness of any other region is relatively thin. In this way, it is possible to avoid the increase in the resistance of the semiconductor substrate10immediately below the analog-digital converter17while ensuring the amount of light incident on the light receiving portion13. That is, the processing speed can be improved by achieving both high sensitivity and stabilization of the ground. FIG.5is a schematic view illustrating a backside incident-type imaging element according to a third modification. As illustrated inFIG.5, a backside incident-type imaging element1C according to the third modification has the same structure as that of the backside incident-type imaging element1. The backside incident-type imaging element1C is different from the backside incident-type imaging element1in that the semiconductor substrate10is directly electrically connected to the ground GND. In this way, a form in which the ground potential is applied to the semiconductor substrate10is arbitrary. FIG.6is a schematic view illustrating a backside incident-type imaging element according to a fourth modification. As illustrated inFIG.6, a backside incident-type imaging element1D includes a first element part3and a pair of second element parts5disposed on both sides of the first element part3to interpose the first element part3therebetween. That is, the backside incident-type imaging element1D has a structure in which a single CCD unit and a pair of CMOS units are formed (integrated) on a single semiconductor substrate10. The structure of the first element part3and the pair of second element parts5including a cross-sectional structure of the semiconductor substrate10is the same as that of the backside incident-type imaging element1. Furthermore, in the above embodiment and modifications, structures of the respective parts can be arbitrarily adopted between each other. As an example, the structure of the fourth region10D of the backside incident-type imaging element1B according to the second modification can be adopted for the backside incident-type imaging elements1,1A,1C, and1D according to the embodiment and the other modifications. Further, as another example, the structure including the pair of second element parts5of the backside incident-type imaging element1D according to the fourth modification can be adopted for the backside incident-type imaging elements1A,1B, and1C according to the other modifications. Note that the backside incident-type imaging elements1to1D according to the embodiment and the modifications are configured in long shapes with an arrangement direction of the light receiving portion13, the amplifier15, the analog-digital converter17, the multiplexer19, and the output unit23as the longitudinal direction in a plan view. On the other hand, the backside incident-type imaging elements may be configured in long shapes with a direction (second direction) intersecting (orthogonal to) the arrangement direction of the light receiving portion13, the amplifier15, the analog-digital converter17, the multiplexer19, and the output unit23as the longitudinal direction in the plan view. In this case, the light receiving portion13, the amplifier15, the analog-digital converter17, the multiplexer19, and the output unit23may be formed in long shapes in the second direction. In this instance, the output unit23may be divided into a plurality of parts arranged in the second direction. Here, in the above-mentioned example, the CCD has been mentioned as the first element part3. However, the first element part3may be an active pixel sensor having an amplifier in each pixel. In this case, the amplifier15located in the third region10C becomes unnecessary. However, in this case, on the third region10C including the inclined surface63(that is, the thickness of the semiconductor substrate10changes), the wirings W1and W3electrically connecting the light receiving portion13and the analog-digital converter17to each other may be disposed without disposing the light receiving portion13and the analog-digital converter17affected by the change in the thickness of the semiconductor substrate10. In addition, the above-described example shows a case where the thickness of the semiconductor substrate10becomes 0 in the first region10A corresponding to the light receiving portion13of the semiconductor substrate10. However, in the first region10A, the thickness of the semiconductor substrate10does not have to be 0, and it is sufficient that the transmittance of the incident light hν of the first region10A to the semiconductor layer30(the amount of incident light to the light receiving portion13) is larger than that of the second region10B. INDUSTRIAL APPLICABILITY According to the disclosure, it is possible to provide a backside incident-type imaging element capable of improving processing speed. REFERENCE SIGNS LIST 1,1A,1B,1C,1D: backside incident-type imaging element,3: first element part,5: second element part,10: semiconductor substrate,10a: front surface,10b: back surface,10A: first region,10B: second region,10C: third region,13: light receiving portion,15: amplifier,17: analog-digital converter,30: semiconductor layer,60: recess,63: inclined surface. | 25,069 |
11862660 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS FIG.3is a perspective view of a pixel in an image sensor in accordance with an embodiment of the invention. Referring toFIG.3, a pixel101according to the embodiment by the invention comprises a photodiode115, and transfer, reset, source follower, and selection transistors operationally coupled with the photodiode115. According to this embodiment of the invention, the components of the pixel101are arranged in separate first and second semiconductor patterns111and113that are spaced apart from each other. In this exemplary embodiment of the invention, the photodiode115and the transfer transistor are disposed in the second semiconductor pattern113, while the reset, source follower, and selection transistors are placed in the first semiconductor pattern111. The gate217of the transfer transistor is disposed under the photodiode115. Thus, the fill factor of the pixel is not affected by the presence or size of the transfer, reset, source follower, and selection transistors therein. According to this embodiment, as the second semiconductor pattern113is used entirely for the photodiode115, it is possible to achieve the fill factor of substantially 100%. In this embodiment, since the first semiconductor pattern111including the transistors does not affect the fill factor, the first semiconductor pattern111may be formed in the same size as the second semiconductor pattern113. Thus, it is possible to improve the noise characteristic of 1/f and the light-gathering performance (e.g., speed) of the pixel. In addition, the charge collection regions411_1and411_2, may be enlarged to extend the dynamic range thereof. The photodiode115includes a first conductive region (e.g., an N-type region)113nformed in the second semiconductor pattern113and a second conductive region (e.g., a P-type region)113penveloping the first conductive region113n. In this embodiment, electron-hole pairs as signal charges are generated in response to photons incident upon the second semiconductor pattern113, and electrons are accumulated in the N-type region113n. Since the N-type region113nis entirely enclosed (enveloped) by the P-type region113p, the leakage of electrons out of the N-type region113nis minimized. The transfer gate217is disposed under a gate insulation layer317adjacent to the N-type region113n, interposed between the gate insulation layer317and the N-type region113n. It can be seen that the transfer transistor includes the transfer gate217, and that the second charge collection region411_2and the N-type region113nare positioned at either side of the transfer gate217. If a bias voltage is applied to turn ON the transfer gate217, the charges (e.g., electrons) accumulated in the N-type region113nare transferred to the second charge collection region411_2functioning as a floating diffusion region. The second charge collection region411_2is formed in the second semiconductor pattern113outside of the transfer gate217, being doped with N-type impurities. On the first semiconductor pattern111, a reset gate211, a source follower gate213, and a selection gate215are formed on gate insulation layers311,313, and315formed on the first semiconductor pattern111. Impurity regions in the first semiconductor pattern111, are source/drain regions. The gate and the impurity regions at either side of a gate constitute a transistor. For instance, a reset transistor includes the reset gate211and the impurity regions411_1and413at either side of the reset gate211. A source follower transistor includes the source follower gate213and the impurity regions413and415at either side of the source follower gate213. A selection transistor includes the selection gate215and the impurity regions415and417at either side of the selection gate215. A VDD voltage (from a power supply not shown) is applied to the impurity region413between the reset and source follower gates211and213. The impurity region411_1of the reset transistor is electrically connected to the second charge collection region411_2, acting as a floating diffusion region (similar to the second charge collection region411_2). In other words, the impurity region411_1of the reset transistor accumulates charges transferred from the photodiode115(which hereinafter will be referred to as the first charge collection region in recognition of the fact that signal charges are first accumulated therein). When a bias voltage is applied to the reset gate211, a conductive channel is formed under the reset gate211in the first semiconductor pattern111and signal charges remaining in the first and second charge collection regions411_1and411_2flow into a power source (not shown) connected to the impurity region413of the reset transistor. The pixel is thereby initialized. The source follower gate213(of the source follower transistor) is electrically connected to the first and second charge collection regions411_1and411_2. The first and second charge collection regions,411_1and411_2, and the source follower gate213are electrically connected with each other by way of a local conductive pattern611and contact plugs511,513, and711, forming a common node. Thus, a signal voltage, corresponding to (e.g., proportionate with) the amount of signal charges accumulated in the first and second charge collection regions411_1and411_2, appears at the impurity region415of the source follower transistor. When a bias voltage is applied to the selection gate215of the selection transistor, the signal voltage (at the impurity region415) is transferred to an output terminal of the selection transistor, i.e., to the impurity region417. The signal transferred to the output terminal417of the selection transistor is detected and processed by a peripheral circuit (not shown). The signal processing operations performed by peripheral circuits are well known to persons skilled in the art and will be described with reference toFIG.6below. The first semiconductor pattern111, including the reset, source follower, and selection transistors, may be a P-type silicon semiconductor substrate. The transistors formed in the first semiconductor pattern111may be formed by, for example, depositing and patterning each of a gate insulation layer and a conductive layer, and implanting ionic impurities to form the impurity regions. A conductive layer for the gate is not restricted to this exemplary embodiment and may be formed of other materials or in other structures, for example, polysilicon, or a multi-layer of polysilicon and silicide. When the first semiconductor pattern111is a P-type, N-type ionic impurities are injected to form source/drain regions of the transistors. An interlayer insulating layer (911, seeFIG.5, not shown inFIG.3) is interposed between the first and second semiconductor patterns111and113, as will be detailed with reference toFIG.5. The transfer gate217may be formed by depositing a conductive layer on the interlayer insulating layer (911shown inFIG.5) and patterning the conductive layer. Patterning of the conductive layer may be conducted by a photolithography process. The gate insulation layer317covering (insulating) the transfer gate217may be formed by a film deposition technique. The second semiconductor pattern113disposed on the second interlayer insulating layer (813shown inFIG.5), covering the transfer gate217and the gate insulation layer317thereon, may be formed by means of a film deposition technique such as chemical vapor deposition (CVD) or plasma-enhanced CVD, or epitaxial growth, the methods of formation not being restricted to those examples. The photodiode115may be formed by conducting ion implantation into the second semiconductor pattern113. For instance, the photodiode115may be produced (after forming the second semiconductor pattern113doped with P-type impurities), by implanting ionic impurities to form the N-type region113nand implanting ionic impurities to form the top P-type region113p. According to this embodiment, the photodiode113constitutes a vertical PNP structure, thereby avoiding the effect of image lag. The second charge collection region412_2acting as the floating diffusion region may be formed by implanting ionic impurities into the second semiconductor pattern113and using the transfer gate217as an ion injection mask. The steps of ion implantation for the photodiode115and the second charge collection region411_2may proceed in an appropriate order. The contact plugs,511,513, and517, may be formed by patterning the interlayer insulating layer(s) (811,813as shown inFIG.5) to form contact holes and then filling the contact holes with a conductive material. The local conductive pattern611is may be formed by depositing and patterning a conductive layer (upon interlayer insulating layer811). The contact plugs511and513connected each to the first charge collection region411_1and the source follower gate213may be formed at the same time through the interlayer insulating layer811. Interconnections not shown are disposed between the first and second semiconductor patterns111and113in order to apply bias voltages to the reset gate211, the selection gate215, and the transfer gate217. The interconnections not shown may be formed while forming the local conductive pattern611. While forming the contact plugs511and513connected to the first charge collection region411_1and the source follower gate213respectively, a contact plug (not shown) connected to the selection gate215may be formed at the same time. And, at the same time that the contact plug711is formed to connect the local conductive pattern611with the second charge collection region411_2, a contact plug (not shown) for connecting the transfer gate217with an interconnection that conducts a bias voltage to the transfer gate217may be also be formed. A processing sequence for forming the contact plugs, the interconnections, and the local conductive pattern may be varied in alternative modes. According to this embodiment, as the interconnections for applying bias voltage to the plural gates are formed under the photodiode115, it is possible to secure misalignment margins for the interconnections, providing flexibility in arranging the interconnections. In this exemplary embodiment, a color filter may be disposed over the photodiode, so to minimizes optical and electrical cross-talk therein. In addition, since the photodiode is very close to or contacts with the color filter and has a large fill-factor, it may not require a micro-lens for condensing light. A light shielding pattern can be formed under the photodiode without degrading the fill factor of the pixel, and it is possible to minimize electrical interference more effectively. The photodiode may be formed after completing almost all of metal interconnections. Thus, since there is no metal contact on the photodiode, a dark level thereof can be minimized. FIG.4is a plane view illustrating part of the pixel array of the image sensor ofFIG.3, andFIG.5is a cross-sectional view of a pixel in the array ofFIG.4taken along section line II-II′ inFIG.4. Referring toFIG.4, the first semiconductor pattern111, including the reset gate211, the source follower gate213, and the selection gate215, is located under the second semiconductor pattern113and is entirely covered by the second semiconductor pattern113. Therefore, the dimensions of the pixel are determined by the size of the second semiconductor pattern113including the photodiode115. The second semiconductor pattern113can be used entirely as the photodiode115. As illustrated inFIG.4, a gate width (or the width of the active region) can be enlarged in by extension of the first semiconductor pattern111along the y axis, by which enlarged width the performance of transistor becomes improved. The width of the first semiconductor pattern111may be extended so as to make the first semiconductor pattern111the same size as the second semiconductor pattern113. Further, since the first semiconductor pattern111is disposed under the second semiconductor pattern113including the photodiode115, it is permissible to variously modify the configuration of the first semiconductor pattern111without reducing the fill factor. For instance, upon altering the configuration of the first semiconductor pattern111in various ways, it is possible to design channel patterns suitable for the optimum performance of the transistors without reducing the fill factor. In addition, because the transfer gate127is disposed under the photodiode115, the gate length of the transfer gate127may be variously designed for the optimum transfer efficiency. A cross-section of the pixel ofFIG.3andFIG.4can be seen fromFIG.5. InFIG.5, the reference numerals811and813denote first and second interlayer insulating layers and are collectively referred to by the reference numeral911. The reference numeral1111indicates a color filter. The first and second interlayer insulating layers811and813may be formed of, for example, borophospho-silicate glass (BPSG) doped with boron (B) and phosphorous (P), boro-silicate glass (BSG) doped with boron, phosphor-silicate glass (PSG) doped with phosphorous, undoped silicate glass (USG), or vapor-deposited silicon oxide. The color filter may be formed by a conventional process. Referring toFIG.5, the color filter1111is arranged close or in direct contact with the top of the photodiode115. In the conventional image sensor shown inFIG.1or2, because various kinds of interconnections are arranged over the photodiode, the color filter is inevitably spaced apart from (above) the photodiode. And the conventional image sensor uses microlenses to raise the efficiency of light sensing. Further, due to the distance between the color filter and the photodiode in the conventional image sensor, the light passing through the color filter may arrive at an adjacent pixel as well as a target pixel. In exemplary embodiments of the present invention, since the color filter1111is disposed close to or in direct contact with the photodiode115, light passing through the color filter is entirely incident on the photodiode115in substance. Moreover, because, in exemplary embodiments of the invention, the photodiode is located directly under the color filter, a microlens need not be formed in the pixel. FIG.6is a block diagram of the image sensor2080including the pixel ofFIGS.3,4and5. Referring toFIG.6, the pixel array2000includes a plurality of pixels arranged in a matrix. The matrix of the pixel array2000includes rows and columns of pixels. A row driver2100selects a specific row of pixels in the pixel array2000in response to an output of a row decoder2200, and a column driver2600selects a specific column of pixels in the pixel array2000in response to an output of a column decoder2700. The CMOS image sensor is controlled by a controller2500. The controller2500controls the row decoder2200, the row driver2100, the column decoder2700, and the column driver2600. An output signals from each of the pixels include a pixel reset signal Vrst and a pixel image signal Vsig. The pixel reset signal Vrst corresponds with the potential of the charge collection region when the pixel is in a reset state. The pixel image signal Vsig corresponds with the potential of the charge collection region after signal charges generated from an image have been transferred to the charge collection region. The pixel reset signal Vrst and the pixel image signal Vsig are read out by a sampling/holding circuit2610. An amplifier (AMP)2620generates a difference signal Vrst−Vsig from the reset and image signals Vrst and Vsig. The difference signal is transformed into a digital signal by an analog-digital converter (ADC)2750. An image processor2800generates a digital image from the digitized differential signals. The image sensor2080may be included in a semiconductor chip (e.g., a wafer3000). FIG.7is a block diagram of a processor-based system4000including the image sensor ofFIG.6. The processor-based system400may be, any digital circuit that may employ the image sensor4080. The processor-based system is not limited hereto, but may be a computer system, a camera system, a cell-phone, a scanner, a videophone, a surveillance system, a machine vision system, a vehicle navigation system, an automatic focus system, a star tracking system, a motion detection system, an image stabilization system, a data compression system, or other system compatible with an image sensor. The system4000includes a processor (e.g., central processor unit, CPU)4020communicating with plural devices or peripherals via a bus4040. The devices (peripherals) coupled to bus4040, are e.g., an input/output unit4060and the image sensor4080, provide the system4000with input/output communication. The devices coupled to bus4040, include at least one peripheral memories, such as a RAM4100, a hard disc driver (HDD)4120, a floppy disc driver (FDD)4140, and a compact disc (CD) driver4160. The image sensor4080receives control signals as data from the processor4020or from another device of the system4000. The image sensor4080provides the processor402with a data signal defining an image on basis of the received control signals or data, and the processor4020processes the signal supplied from the image sensor4080. Accordingly in exemplary embodiments of the invention, a fill factor of substantially 100% can be attained because the second semiconductor pattern113is used entirely for the photodiode. In exemplary embodiments of the invention, (seeFIGS.3,4,5) the first semiconductor pattern111including the transistors does not affect the fill factor, and may be formed at the same size (area) as the second semiconductor pattern113. Thus, it is possible to improve the noise characteristic of 1/f and also the performance of light-sensing operations. In addition, exemplary embodiments of the invention facilitate enlargement of charge collection regions411_1and411_2, to extend dynamic range. In exemplary embodiments of the invention, the photodiode113constitutes a vertical PNP structure that avoids an effect of image lag. Image lag occurs in conventional image sensors when traces of a previous frame (image) remain in future frames, i.e. when the pixel is not fully reset. In exemplary embodiments of the invention, since the first semiconductor pattern111is disposed under the second semiconductor pattern113including the photodiode115, it is permissible to variously modify the configuration of the first semiconductor pattern111without reducing the fill factor. For instance, by altering the configuration of the first semiconductor pattern111in various forms, it is possible to design channel patterns suitable for the optimum performance of the transistors. In exemplary embodiments of the invention, since the color filter is disposed close to or directly contacting the photodiode, light passing through the color filter is entirely incident upon the target photodiode. In exemplary embodiments of the invention, since the photodiode is located directly under the color filter, the microlens provided in conventional image sensors may be omitted entirely. In exemplary embodiments of the invention, forming a light shielding pattern under the photodiode does not degrade the fill factor of the pixel, and it is possible to minimize electrical interference more effectively. In this embodiment, the photodiode is formed after formation of almost all of the metal interconnections. Thus, since there is no metal contact on the photodiode, it is able to minimize a dark level thereof. The above-disclosed subject matter is to be considered illustrative, and not limiting, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description. | 20,114 |
11862661 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) First Embodiment As illustrated inFIG.1andFIG.2, an image pickup apparatus9according to the present embodiment includes an image pickup member30, a spacer40, and an optical member50. Note that drawings based on each of embodiments are schematic in the description below. The relationship between thicknesses and widths of respective parts, a ratio of the thickness, the relative angle, and the like of a certain part to those of another part are different from the actual ones. The respective drawings include parts in which the relationships and ratios among the dimensions are different. In addition, illustration of some of constituent elements and impartment of reference numerals to some of the constituent elements are omitted. The image pickup member30includes an image pickup device10and a cover glass20. The image pickup device10includes a light-receiving surface10SA and a rear surface10SB opposed to the light-receiving surface. The light-receiving surface10SA includes a light-receiving region11configured of a CCD or a CMOS light-receiving circuit. On the rear surface10SB, external electrodes12connected to the light-receiving region11are disposed. The image pickup device10may be a front surface irradiation type image sensor or a rear surface irradiation type image sensor. On the light-receiving surface10SA, the cover glass20is disposed by using a transparent adhesive (not illustrated). The cover glass20is a transparent plate that protects the light-receiving region11. Note that the transparent plate may be a resin plate made of polycarbonate, or the like. The spacer40for adjusting the optical path length is made of metal, resin, silicon, or the like, having an optical path region formed as a space. The spacer may be a member having a transparent optical path region. The spacer40has a picture-frame shape in the cross section orthogonal to an optical axis O, and configured to seal the optical path. However, the spacer may have an L-shape, or a U-shape in the cross section orthogonal to the optical axis O, or may be configured as two parallel walls. The optical member50is fixed to the spacer40in a stacked body35by using an adhesive (not illustrated), for example. The stacked body35is formed by the image pickup member30being stacked on the spacer40. The optical member50includes an incident surface50SA and an emission surface50SB opposed to the incident surface50SA. The optical member50is a stacked body in which a first optical element51, a second optical element52, and a third optical element53are stacked. An image of an object, which is condensed by the optical member50, is formed on a focusing surface50SS located at a position separated from the emission surface50SB by a focusing length L50. The image pickup apparatus9configured such that the light-receiving surface10SA of the image pickup device10and the focusing surface50SS coincide with each other has excellent optical characteristics. The optical member50is a wafer-level optical member fabricated by cutting a stacked wafer. The optical member50fabricated from the same stacked wafer has substantially the same focusing length L50. Note that each of the first optical element51, the second optical element52, and the third optical element53has a rectangular outer shape in the cross section in the direction orthogonal to the optical axis, and has the same outer dimension. The plurality of optical elements51to53are stacked such that the optical axes O of the optical elements coincide with each other. The configuration of the optical member50is an example, and the configuration including the type, the number, and the like of the optical elements is set according to the specification. As described later, when a plurality of image pickup apparatuses9are fabricated, the thicknesses D20of the respective cover glasses20of the plurality of image pickup members30are not fixed due to manufacturing errors. The thicknesses D20of the cover glasses20have an error of plus/minus 10%, for example. In other words, when the specification value of the thickness D20of the cover glasses20is 300 μm, the thicknesses D20of the plurality of cover glasses20range from 270 μm to 330 μm. On the other hand, the thicknesses D40of the spacers40can be set by manufacturing conditions. The thicknesses D40of the spacers40range from 50 μm to 110 μm, for example. Any one of the plurality of image pickup members30and any one of the plurality of spacers40are selected such that the sum G of the thickness D20of the cover glass20and the thickness D40of the spacer40has a predetermined specification (plus/minus 20 μm, for example), with the value of the focusing length L50as a center, and the selected image pickup member and spacer are stacked. As described later, the manufacturing method of the image pickup apparatus9includes classification processes for classifying the image pickup members and the spacers into groups depending on the thicknesses thereof. Therefore, the method enables the image pickup apparatus9to be manufactured easily and achieves excellent optical characteristics of the image pickup apparatus9. <Manufacturing Method of Image Pickup Apparatus> Description will be made on the manufacturing method of the image pickup apparatus according to the present embodiment, along the flowchart shown inFIG.3. <Step S10> Fabrication Process of Image Pickup Member and Spacer Although not illustrated, each of the image pickup members30is fabricated by cutting a bonded wafer formed by adhering a glass wafer on the light-receiving surface of the image pickup wafer on which a plurality of light-receiving regions11and the like are formed. After the glass wafer is adhered, polishing processing of the glass wafer is performed on the bonded wafer. Therefore, according to the polishing conditions, etc., the thickness D20of the cover glass20of each of the image pickup members30differs for each bonded wafer. On the other hand, each of the spacers40is fabricated by disposing a metal or a resin on a principal surface of a support plate or by processing a silicon wafer, for example. The thickness of each of the spacers40is set according to the fabrication conditions. Note that the step S10may be a preparing process of the image pickup members and the spacers. In the preparing process, the image pickup devices30and the like, which have been divided into individual pieces, may be purchased. <Step S20> Thickness Measurement Process The thicknesses D20of the cover glasses20(transparent plates) of the plurality of image pickup members30and the thicknesses D40of the plurality of spacers40are measured. It is not necessary to measure the thicknesses of all the image pickup members30and the spacers40. For example, the plurality of image pickup members30, which are fabricated by dividing the same bonded wafer into individual pieces, have the cover glasses20having the same thickness. Therefore, the thickness D20of at least one cover glass20is measured for each bonded wafer. Note that, when the thickness of the image pickup device10is fixed and known, the thickness D20of the cover glass20may be calculated by measuring the thickness of the image pickup member30. <Step S30> First Classification Process As illustrated inFIG.4, the plurality of image pickup members30are classified into three groups, i.e., first groups 1A, 1B, and 1C, depending on the thicknesses D20of the cover glasses20. The thicknesses D20of the cover glasses20in the first groups 1A, 1B, and 1C are within the following ranges, for example.The first group 1A; 270 μm≤D20<290 μmThe first group 1B; 290 μm≤D20<310 μmThe first group 1C; 310 μm≤D20<330 μm <Step S40> Second Classification Process As illustrated inFIG.5, the plurality of spacers40are classified into three groups. i.e., second groups 2A, 2B, and 2C, depending on the thicknesses D40. The thicknesses D40of the spacers40in the second groups 2A, 2B, and 2C are within the following ranges, for example.The second group 2A; 50 μm≤D40<70 μmThe second group 2B; 70 μm≤D40<90 μmThe second group 2C; 90 μm≤D40<110 μm Note that the order of the first classification process S30and the second classification process S40may be reversed, or the processes may be performed concurrently. <Step S50> Selection Process A combination of any one of the plurality of first groups 1A to 1C and any one of the plurality of second groups 2A to 2C is selected such that the sum G of the thickness D20of any one of the cover glasses20and the thickness D40of any one of the spacers40is within a predetermined range with the value of the focusing length L50as a center (for example, plus or minus 20 μm with respect to the focusing length L50of 380 μm). One example of the combinations is shown below.Combination 1: the first group 1A and the second group 2C: 360 μm≤G<400 μmCombination 2: the first group 1B and the second group 2B: 360 μm≤G<400 μmCombination 3: the first group 1C and the second group 2A: 360 μm≤G<400 μm <Step S60> Stack Process (Stacking Process) The stacked body35is fabricated by the image pickup member in the first group and the spacer in the second group in the selected combination being stacked. Furthermore, the optical member50is disposed on the spacer40in the stacked body35, to thereby complete the image pickup apparatus9. The manufacturing method of the image pickup apparatus9includes the first classification process S30and the second classification process S40, for classifying the image pickup members and the spacers into the groups depending on the thicknesses thereof, which enables the image pickup apparatus9to be manufactured easily and achieves the excellent optical characteristics of the image pickup apparatus9. Note that the number of groups in the first classification process S30and the number of groups in the second classification process S40are preferably 3 or more and 20 or less, although not specifically limited. If the number of groups is 3 or more, it is possible to fabricate the image pickup apparatus9with the excellent optical characteristics. If the number of groups is 20 or less, the classifying work is easy. Note that the number of groups in the first classification process S30may be different from the number of groups in the second classification process S40. First Modification of First Embodiment Since an image pickup apparatus9A and a manufacturing method of the image pickup apparatus9A according to the present modification are similar to the image pickup apparatus9and the manufacturing method of the image pickup apparatus9, constituent elements having the same functions as those in the image pickup apparatus9and the manufacturing method thereof are attached with the same reference numerals and descriptions thereof will be omitted. As illustrated inFIG.6, the image pickup apparatus9A is configured such that the side surfaces of the image pickup member30are protected by being covered with a resin60, to thereby enable easy handling. <Manufacturing Method of Image Pickup Apparatus9A> Description will be made on the manufacturing method of the image pickup apparatus9A along the flowchart shown inFIG.7. <Step S10> Fabrication Process of Image Pickup Member and Spacer The fabrication method of the image pickup member30of the image pickup apparatus9A is the same as that in the manufacturing method of the image pickup apparatus9. On the other hand, as illustrated inFIG.8A, in the image pickup apparatus9A, the spacer40is fabricated on a principal surface70SA of a support plate70. For example, the support plate70includes a release layer71and a base body72. The release layer71loses its adhesive force by being subjected to heating treatment or ultraviolet light irradiation, for example. The spacer40is disposed by molding a resin, patterning a photoresist, forming a plating film, or etching a silicon substrate, etc. A plurality of spacers40having different thicknesses D40may be disposed on one support plate70. Alternatively, the spacers40may be disposed on each of the support plates70such that the thicknesses D40of the spacers40differ for each of the support plates70. The step S20(thickness measurement process), the step S30(first classification process), the step S40(second classification process), and the step S50(selection process) are substantially the same as those in the manufacturing method of the image pickup apparatus9. Note that if the plurality of spacers40disposed on one support plate70are fabricated under the same conditions, the spacers40have substantially the same thicknesses D40in many cases. However, the plurality of spacers40having different thicknesses D40can be disposed on one support plate70by changing the fabrication conditions of the plurality of spacers40to be disposed on the one support plate70. In a case where the plurality of spacers40are fabricated by forming an electroplating film, for example, the thicknesses D40of the spacers40change depending on a current density distribution. Since the current density is high in the outer peripheral portion of the support plate70, the spacer40, the thickness D40of which is large, is fabricated at the outer peripheral portion. On the other hand, at the center portion of the support plate70where the current density is low, the spacer40, the thickness D40of which is small, is fabricated. Alternatively, in the manufacturing method of the image pickup apparatus9A, a plurality of spacers40are disposed on each of the plurality of support plates70. The spacer disposition conditions are changed for each of the plurality of support plates70, to thereby fabricate the plurality of spacers40having different thicknesses D40are fabricated. Then, in the step S50(selection step), for example, an optimal support plate70is selected from the plurality of support plates70. <Step S60> Stack Process In the manufacturing method of the image pickup apparatus9A, in the step S60(stack process), a plurality of image pickup members30of the selected combination are stacked on the plurality of spacers40of the selected combination that are disposed on the principal surface70SA of the support plate70. As illustrated inFIG.8B, for example, the plurality of image pickup members30in the first group 1C are adhered respectively, in a stacked manner, to the plurality of spacers40in the second group 2A, and thereby the stacked bodies35are fabricated. <Step S70> Resin Disposition Process As illustrated inFIG.8C, after the stack process S60, the resin60is disposed around the plurality of stacked bodies35disposed on the principal surface70SA of the support plate70. For example, an ultraviolet curable epoxy resin is disposed and ultraviolet light irradiation processing is performed. <Step S80> Cutting Process As illustrated inFIG.8D, the plurality of stacked bodies35integrated by the resin60are divided into individual pieces by cutting the resin60. As illustrated inFIG.8E, the release layer71loses its adhesive force by being subjected to heating treatment, for example, which enables separation process for separating the stacked bodies35from the support plate70to be performed. The support plate70may be formed without the release layer71, as long as the stacked bodies35can be easily separated. Note that the separation process may be performed before the cutting process S80. In the manufacturing method of the image pickup apparatus9, the stacked bodies35are fabricated by stacking the image pickup members30respectively on the plurality of spacers40disposed on the principal surface70SA of the support plate70, which enables the easy fabrication of the plurality of stacked bodies35. In addition, the plurality of image pickup members30which are being manufactured are integrated by the resin60, which enables easy handling. Second Modification of First Embodiment Since an image pickup apparatus9B and a manufacturing method of the image pickup apparatus9B according to the present modification are similar to the image pickup apparatus9A and the manufacturing method of the image pickup apparatus9A, the constituent elements having the same functions as those in the image pickup apparatus9A and the manufacturing method thereof are attached with the same reference numerals and descriptions thereof will be omitted. As illustrated inFIG.9, in the image pickup apparatus9B, a stacked body35B includes a glass plate70B which is a second transparent plate. The glass plate70B is included in the stacked body35in a state where the support plate cut in the cutting process S80is not separated. The dimension of the glass plate70B in the direction orthogonal to the optical axis is the same as those of the resin60and the spacer40. In other words, the separation process may be eliminated when the support plate70is a transparent plate such as a glass plate. In the manufacturing method of the image pickup apparatus9B, the support plate70is also cut in the cutting process S80. The cut support plate70can be regarded as the glass plate70B having the function as the spacer for adjusting the optical path length. Note that it is needless to say that the glass plate70B is regarded as a part of the spacer in the selection process S50. In other words, the sum of the thickness of the spacer40and the thickness of the glass plate70B is regarded as the thickness D40of the spacer. Since the separation process is not necessary, the image pickup apparatus9B can be manufactured more easily than the image pickup apparatus9A. Second Embodiment Since an image pickup apparatus9C and a manufacturing method of the image pickup apparatus9C according to the present embodiment are similar to the image pickup apparatus9and the manufacturing method of the image pickup apparatus9, the constituent elements having the same functions as those in the image pickup apparatus9and the manufacturing method thereof are attached with the same reference numerals and descriptions thereof will be omitted. The image pickup apparatus9C has the same configuration as the configuration of the image pickup apparatus9as illustrated inFIG.1andFIG.2. As already described, the optical members50fabricated by cutting the same stacked wafer have substantially the same focusing lengths L50. However, the optical members50fabricated by cutting different stacked wafers have sometimes different focusing lengths L50. The present manufacturing method, as illustrated inFIG.10, further includes a third classification process (step S45: not illustrated). In the third classification process, the plurality of optical members50having different focusing lengths L50are classified into a plurality of third groups 3A to 3D depending on the focusing lengths L50. The third classification process S45, the first classification process S30, and second classification process S40may be performed in any order, or may be performed concurrently. The focusing lengths L50of the optical members50in the third groups 3A, 3B, 3C, and 3D are within the following ranges, for example.The third group 3A; 360 μm≤L50<370 μmThe third group 3B; 370 μm≤L50<380 μmThe third group 3C; 380 μm≤L50<390 μmThe third group 3D; 390 μm≤L50<400 μm In the selection process S50, a combination of any one of the plurality of first groups 1, any one of the plurality of second groups 2, and any one of the plurality of third groups 3 is selected such that the sum G becomes the focusing length L50of any one of the optical members50. Then, in the stack process S60, the image pickup member30in the first group, the spacer40in the second group, and the optical member50in the third group, in the selected combination, are stacked. Even in a case where the number of image pickup members30classified into the first group 1A is small, for example, if the sum G of the thickness of the image pickup member30in the first group 1 A and the thickness of the spacer40in the second group 2B is within the range of the focusing length L50in any of the third groups 3A to 3D, an image pickup apparatus with desired optical characteristics can be fabricated. Thus, the manufacturing method of the image pickup apparatus9C provides excellent manufacturing efficiency and reduced cost. The number of groups in the third classification process is preferably 3 or more and 20 or less, although not specifically limited. If the number of groups is 3 or more, it is possible to easily fabricate the image pickup apparatus with desired optical characteristics. If the number of groups is 20 or less, the classifying work is easy. In addition, the number of groups in the first classification process S30, the number of groups in the second classification process S40, and the number of groups in the third classification process S45may be different from one another. Note that, needless to say, also in the manufacturing method of the image pickup apparatus9C, the resin60may be disposed and cut similarly as in the image pickup apparatus9A, and furthermore, the transparent plate may be used as the support plate similarly as in the image pickup apparatus9B. Each of the image pickup apparatuses9and9A to9C is ultra-small, with the light-receiving surface10SA of 5 mm square or less, for example. By using such image pickup apparatuses in an endoscope, it is possible to provide a low-invasive endoscope that displays high-quality images. Note that the endoscope may be a rigid endoscope or a flexible endoscope, and may be adopted for a medical use or an industrial use. The present invention is not limited to the above-described embodiments, but various changes, modifications, and the like are possible without changing the gist of the present invention. | 21,701 |
11862662 | MODES FOR CARRYING OUT THE INVENTION In the following, an embodiment of the present disclosure will be described in detail with reference to the drawings. It is to be noted that the description is given in the following order.1. Embodiment (an imaging device including a polishing adjustment section in a semiconductor element)2. Application Example (an electronic apparatus)3. Example of Practical Application Embodiment (Configuration of Imaging Device1) FIG.1schematically illustrates an example of a cross-sectional configuration of a solid-state imaging device (an imaging device1) according to an example of the present disclosure. This imaging device1is, for example, a back-illumination type CMOS (Complementary Metal Oxide Semiconductor) image sensor. The imaging device1includes mainly an imaging element10, a memory chip20, and a logic chip30. The memory chip20and the logic chip30are provided on a support substrate40. The imaging element10is opposed to the support substrate40with the memory chip20and the logic chip30interposed therebetween. Between the support substrate40and the imaging element10, there is provided a buried layer50together with the memory chip20and the logic chip30. A color filter61and an on-chip lens62are provided on a light entrance side (a side opposite to a surface facing the memory chip20and the logic chip30) of the imaging element10. Here, the memory chip20and the logic chip30correspond to a specific example of a “semiconductor element” of the present disclosure. The imaging element10is larger in chip size than each of the memory chip20and the logic chip30, for example. Specifically, a planar shape of the imaging element10is larger in size than a planar shape of each of the memory chip20and the logic chip30. The imaging element10includes, for example, a semiconductor substrate11and a wiring layer12. The semiconductor substrate11is opposed to the memory chip20and the logic chip30with the wiring layer12interposed therebetween, for example. On the semiconductor substrate11, a PD (a photoelectric converter) is provided for each pixel. The semiconductor substrate11is configured by, for example, a silicon (Si) substrate. The wiring layer12is provided between the semiconductor substrate11and the memory chip20, and between the semiconductor substrate11and the logic chip30. The wiring layer12includes, for example, a terminal12a, a first insulating film12b, and a second insulating film12c. The first insulating film12band the second insulating film12care stacked in this order from the semiconductor substrate11side. For example, the first insulating film12bhas a thickness larger than a thickness of the second insulating film12c. The first insulating film12band the second insulating film12cinclude, for example, silicon oxide (SiO) or the like. A plurality of the terminals12aare provided in the wiring layer12, and the plurality of terminals12aare separated from each other by the first insulating film12b. Ones of the plurality of terminals12athat are provided at positions opposed to the memory chip20are each electrically coupled to the memory chip20(more specifically, a terminal22ato be described later) by a wiring line W1. Ones of the plurality of terminals12athat are provided at positions opposed to the logic chip30are each electrically coupled to the logic chip30(more specifically, a terminal32ato be described later) by a wiring line W2. The terminals12ainclude, for example, copper (Cu), aluminum (Al), or the like. FIG.2illustrates a more specific configuration of the memory chip20. (A) ofFIG.2illustrates a cross-sectional configuration of the memory chip20, and (B) ofFIG.2illustrates a planar configuration of a main part of the memory chip20. The memory chip20provided to be opposed to the imaging element10includes a wiring region20A in a middle portion, and a peripheral region20B provided outside the wiring region20A to surround the wiring region20A. For example, the wiring region20A is a region that effectively functions as the memory chip20, and in this wiring region20A, the memory chip20has a memory circuit electrically coupled to the PD of the imaging element10. The wiring region20A has a planar shape (shape in an XY plane in (B) ofFIG.2) that is quadrangular, for example. The memory chip20includes, for example, a semiconductor substrate21and a wiring layer22. Here, the semiconductor substrate21or a semiconductor substrate31to be described later corresponds to one specific example of a “semiconductor substrate” of the present disclosure, and the wiring layer22or a wiring layer32to be described later corresponds to one specific example of a “wiring layer” of the present disclosure. The semiconductor substrate21and the wiring layer22are provided across the wiring region20A and the peripheral region20B. The semiconductor substrate21is, for example, opposed to the imaging element10with the wiring layer22interposed therebetween, and has a front surface Sa on the wiring layer22side, and a back surface Sb provided opposite to the front surface Sa. A plurality of MOS (Metal Oxide Semiconductor) transistors (not illustrated) is provided in the wiring region20A of the semiconductor substrate21. The memory circuit is configured using the plurality of MOS transistors, for example. The semiconductor substrate21is configured by a silicon (Si) substrate, for example. The wiring layer22is provided between the semiconductor substrate21and the imaging element10, that is, on the front surface Sa side of the semiconductor substrate21. The wiring layer22includes, for example, the terminal22a, a first insulating film22b, and a second insulating film22c. The first insulating film22band the second insulating film22care stacked in this order from the semiconductor substrate21side. For example, the first insulating film22bhas a thickness larger than a thickness of the second insulating film22c. The first insulating film22band the second insulating film22cinclude, for example, silicon oxide (SiO) or the like. A plurality of the terminals22aare provided in the wiring region20A, and the plurality of terminals22aare separated from each other by the first insulating film22b. The plurality of terminals22aare electrically coupled to the terminals12aof the imaging element10, each by the wiring line W1. The terminals22ainclude, for example, copper (Cu), aluminum (Al), or the like. The wiring line W1is configured by, for example, a CuCu junction between a pad on the memory chip20side and a pad on the imaging element10side. Here, the terminal22aor the terminal22ato be described later corresponds to one specific example of a “wiring line” of the present disclosure. In the present embodiment, the memory chip20further includes a polishing adjustment section23. The polishing adjustment section23is disposed in the peripheral region20B, and is provided across a thickness direction (a Z direction in (A) ofFIG.2) of the semiconductor substrate21from the back surface Sb. The polishing adjustment section23includes a material that is lower in polishing rate than the constituent material of the semiconductor substrate21. As will be described in detail later, providing such a polishing adjustment section23in the memory chip20suppresses excessive polishing of the peripheral region20B of the semiconductor substrate21in a process of polishing the semiconductor substrate21in forming the memory chip20. In a case where the semiconductor substrate21is configured by a silicon (Si) substrate, the polishing adjustment section23includes, for example, silicon nitride (SiN), silicon oxide (SiO), or the like. The polishing adjustment section23is provided, for example, across the thickness direction of the semiconductor substrate21from the back surface Sb to the front surface Sa. The polishing adjustment section23is exposed in the back surface Sb of the semiconductor substrate21, for example. The polishing adjustment section23is provided, for example, to surround the wiring region20A, and is shaped like a frame in planar shape. The polishing adjustment section23is preferably provided to surround the wiring region20A. This makes it possible to suppress excessive polishing of the semiconductor substrate21in all directions. FIG.3illustrates a more specific configuration of the logic chip30. (A) ofFIG.3illustrates a cross-sectional configuration of the logic chip30, and (B) ofFIG.3illustrates a planar configuration of a main part of the logic chip30. The logic chip30provided to be opposed to the imaging element10includes a wiring region30A in a middle portion, and a peripheral region30B provided outside the wiring region30A to surround the wiring region30A. For example, the wiring region30A is a region that effectively functions as the logic chip30, and in this wiring region30A, the logic chip30has a logic circuit electrically coupled to the PD of the imaging element10. The wiring region30A has a planar shape (shape in the XY plane in (B) ofFIG.3) that is quadrangular, for example. The planar shape of the logic chip30is smaller than the planar shape of the memory chip20, for example. The logic chip30includes, for example, the semiconductor substrate31and the wiring layer32. The semiconductor substrate31and the wiring layer32are provided across the wiring region30A and the peripheral region30B. The semiconductor substrate31is, for example, opposed to the imaging element10with the wiring layer32interposed therebetween, and has a front surface Sc on the wiring layer32side, and a back surface Sd provided opposite to the front surface Sc. A plurality of MOS transistors (not illustrated) is provided in the wiring region30A of the semiconductor substrate31. The logic circuit is configured using the plurality of MOS transistors, for example. The semiconductor substrate31is configured by a silicon (Si) substrate, for example. The wiring layer32is provided between the semiconductor substrate31and the imaging element10, that is, on the front surface Sc side of the semiconductor substrate31. The wiring layer32includes, for example, the terminal32a, a first insulating film32b, and a second insulating film32c. The first insulating film32band the second insulating film32care stacked in this order from the semiconductor substrate31side. For example, the first insulating film32bhas a thickness larger than a thickness of the second insulating film32c. The first insulating film32band the second insulating film32cinclude, for example, silicon oxide (SiO). A plurality of the terminals32aare provided in the wiring region30A, and the plurality of terminals32aare separated from each other by the first insulating film32b. The plurality of terminals32aare electrically coupled to the terminals12aof the imaging element10, each by the wiring line W2. The terminals32ainclude, for example, copper (Cu), aluminum (Al), or the like. The wiring line W2is configured by, for example, a CuCu junction between a pad on the logic chip30side and a pad on the imaging element10side. The logic chip30further includes a polishing adjustment section33. The polishing adjustment section33is disposed in the peripheral region30B, and is provided across the thickness direction (the Z direction in (A) ofFIG.3) of the semiconductor substrate31from the back surface Sd. The polishing adjustment section33includes a material that is lower in polishing rate than the constituent material of the semiconductor substrate31. As with the polishing adjustment section23of the memory chip20described above, providing the polishing adjustment section33suppresses excessive polishing of the peripheral region30B of the semiconductor substrate31in a process of polishing the semiconductor substrate31in forming the logic chip30. In a case where the semiconductor substrate31is configured by a silicon (Si) substrate, the polishing adjustment section33includes, for example, silicon nitride (SiN), silicon oxide (SiO), or the like. The polishing adjustment section33is provided, for example, across the thickness direction of the semiconductor substrate31from the back surface Sd to the front surface Sc. The polishing adjustment section33is exposed in the back surface Sd of the semiconductor substrate31, for example. The polishing adjustment section33is provided, for example, to surround the wiring region30A, and is shaped like a frame in planar shape. The polishing adjustment section33is preferably provided to surround the wiring region30A. This makes it possible to suppress excessive polishing of the semiconductor substrate31in all directions. FIGS.4to6illustrate other examples of the planar shapes of the polishing adjustment sections23and33. The polishing adjustment sections23and33may not be provided continuously. For example, as illustrated inFIG.4, a plurality of the polishing adjustment sections23or33may be provided separately from each other around the wiring region20A or30A. As illustrated inFIG.5, the polishing adjustment sections23and33may include first polishing adjustment sections23-1and33-1and second polishing adjustment sections23-2and33-2. The first polishing adjustment sections23-1and33-1are, for example, provided at a position near the wiring regions20A and30A and surround the wiring regions20A and30A. The second polishing adjustment sections23-2and33-2are, for example, provided at a position farther from the wiring regions20A and30A than the first polishing adjustment sections23-1and33-1, and surround the wiring regions20A and30A. As illustrated inFIG.6, the polishing adjustment sections23and33may be provided in part of the peripheral regions20B and30B. In this case, the polishing adjustment sections23and33are preferably provided at corners of the semiconductor substrates21and31that are quadrangular in planar shape. At the corners of the semiconductor substrates21and31, excessive polishing tends to occur. Providing the polishing adjustment sections23and33at the corners makes it possible to effectively suppress the excessive polishing. FIG.7illustrates another example of the cross-sectional configuration of the memory chip20, andFIG.8illustrates another example of the cross-sectional configuration of the logic chip30. As illustrated, the polishing adjustment sections23and33may be provided across the semiconductor substrates21and31and the wiring layers22and32. The polishing adjustment sections23and33are, for example, exposed in the back surfaces Sb and Sd of the semiconductor substrates21and31, and are also exposed in surfaces of the wiring layers22and32facing the imaging element1. The support substrate40supports such a memory chip20and logic chip30(FIG.1). The support substrate40is, for example, to ensure strengths of the memory chip20and the logic chip30in the manufacturing stage, and is configured by a silicon (Si) substrate, for example. The memory chip20and the logic chip30provided on the support substrate40are covered with the buried layer50(FIG.1). The buried layer50covers the memory chip20and the logic chip30, and is provided around each of the memory chip20and the logic chip30. The buried layer50has a flat surface, and the imaging element10is provided in contact with the flat surface. The flat surface of the buried layer50is formed by, for example, a planarization process such as CMP (Chemical Mechanical Polishing). The buried layer50includes an insulating film of, for example, silicon oxide (SiO) or the like. The buried layer50may be provided between the support substrate40and the memory chip20or between the support substrate40and the logic chip30. For example, the imaging element10, the color filter61, and the on-chip lens62are provided in this order on the buried layer50. The color filter61provided on the light entrance side of the imaging element10is, for example, any one of a red (R) filter, a green (G) filter, a blue (B) filter, and a white (W) filter, and is provided for each pixel. These color filters61are provided in a regular color arrangement (for example, a Bayer arrangement). Providing such color filters61allows the imaging device1to obtain light reception data of a color corresponding to the color arrangement. The on-chip lens62on the color filter61is provided at a position opposed to the PD of the imaging element10for each pixel. Light having entered the on-chip lens62is condensed on the PD for each pixel. A lens system of the on-chip lens62is set at a value corresponding to a size of the pixel. Examples of a lens material for the on-chip lens62include an organic material, a silicon oxide film (SiO), and the like. (Method of Manufacturing Imaging Device1) Such an imaging device1may be manufactured in the following manner (FIGS.9A to9H), for example. Here, a process of manufacturing the memory chip20will be mainly described. First, as illustrated inFIG.9A, a photoresist PR1patterned into a predetermined shape is formed on a semiconductor substrate21W in wafer form. In a later step, the semiconductor substrate21W is to be divided into pieces (FIG.9Fto be described later), and is further to be polished to form the semiconductor substrate21(FIG.9Hto be described later) of the memory chip20. The semiconductor substrate21W is configured by a silicon (Si) substrate, for example. Subsequently, as illustrated inFIG.9B, a plurality of grooves G1is formed in the semiconductor substrate21W using the photoresist PR1. The grooves G1are for forming the polishing adjustment section23of the memory chip20. The plurality of grooves G1shaped like a frame (see (B) ofFIG.2), for example, is formed in the semiconductor substrate21W. After the grooves G1are formed, as illustrated inFIG.9C, a polishing adjustment material23M is formed into a film on the semiconductor substrate21W. The polishing adjustment material23M includes silicon nitride (SiN), for example. The polishing adjustment material23M is filled into the grooves G1from the surface of the semiconductor substrate21W. Subsequently, as illustrated inFIG.9D, the polishing adjustment material23M provided on the surface of the semiconductor substrate21W is removed by using, for example, a wet etching method. This forms the polishing adjustment section23embedded in the semiconductor substrate21W. Next, the memory circuit is formed in each region surrounded by the polishing adjustment section23in the semiconductor substrate21W. Next, as illustrated inFIGS.9E and9F, the wiring layer22is formed on the semiconductor substrate21W (FIG.9E) and thereafter, the wiring layer22and the semiconductor substrate21W are cut along lines DL (FIG.9F). The cutting is performed using dicing, for example. The semiconductor substrate21W in a wafer state and the wiring layer22are thereby divided into pieces. Here, even if contaminants adhere to the semiconductor substrate21W in the vicinity of the lines DL during the cutting along the lines DL, it is possible to suppress entry of the contaminants into the logic circuit (the wiring region20A) because the polishing adjustment section23is provided on the periphery (the peripheral region20B) of the memory circuit. Subsequently, as illustrated inFIG.9G, the semiconductor substrate21W and the wiring layer22divided into pieces are bonded to a semiconductor substrate11W in a wafer state and the wiring layer12. The semiconductor substrate11W and the wiring layer12W are for forming the imaging element1. At this time, the terminal22aof the wiring layer22and the terminal12aof the wiring layer12are coupled to each other by, for example, a CuCu junction (the wiring line W1). Further, in order to form the logic chip30, a semiconductor substrate31W in a wafer state and the wiring layer32are cut to be divided into pieces in a similar manner to the above. The semiconductor substrate31W and the wiring layer32are also bonded to the semiconductor substrate11W in the wafer state and the wiring layer12. The terminal32aof the wiring layer32and the terminal12aof the wiring layer12are coupled to each other by, for example, a CuCu junction (the wiring line W2). Thereafter, as illustrated inFIG.9H, the semiconductor substrates21W and31W are thinned by using, for example, a CMP method. The semiconductor substrate21of the memory chip20and the semiconductor substrate31of the logic chip30are thereby formed. That is, the memory chip20and the logic chip30are formed on the semiconductor substrate11in wafer form. Here, in the present embodiment, local excessive polishing of the semiconductor substrates21W and31W is suppressed because the polishing adjustment sections23and33are provided in the semiconductor substrates21W and31W. Next, the buried section50is formed to cover the memory chip20and the logic chip30. Subsequently, the support substrate40is bonded to the semiconductor substrate11W with the memory chip20and the logic chip30interposed therebetween. Then, the semiconductor substrate11W is thinned by using, for example, a CMP method. Thereafter, the color filter61and the on-chip lens62are formed on the semiconductor substrate11W. Lastly, the semiconductor substrate11W in wafer form and the wiring layer12are cut. It is possible to complete the imaging device1illustrated inFIG.1in this manner, for example. FIGS.10A to10Eillustrate another example of the process of manufacturing the memory chip20(or the logic chip30) in order. For example, by using this method, it is possible to form the memory chip20and the logic chip30illustrated inFIGS.7and8. First, as illustrated inFIG.10A, the wiring layer22is formed on the semiconductor substrate21W in wafer form. Next, as illustrated inFIG.10B, a photoresist PR2patterned into a predetermined shape is formed on the wiring layer22. Subsequently, as illustrated inFIG.10C, a plurality of grooves G2is formed in the wiring layer22and the semiconductor substrate21W using the photoresist PR2. The grooves G2, which are for forming the polishing adjustment section23of the memory chip20, penetrate the wiring layer22and extend partially in the thickness direction of the semiconductor substrate21W. Each of the plurality of grooves G2is shaped like a frame in planar shape (see (B) ofFIG.2), for example. After the grooves G2are formed, as illustrated inFIG.10D, the polishing adjustment material23M is formed into a film on the wiring layer22. The polishing adjustment material23M is filled into the grooves G2from the surface of the wiring layer22. Subsequently, as illustrated inFIG.10E, the polishing adjustment material23M provided on the surface of the wiring layer22is removed by using, for example, a wet etching method. This forms the polishing adjustment section23embedded in the wiring layer22and the semiconductor substrate21W. Thereafter, it is possible to complete the imaging device1in a manner similar to that described above. (Operation of Imaging Device1) With such an imaging device1, signal charges (for example, electrons) are acquired in the following manner, for example. Once light has passed through the on-chip lens62, the color filter61, and the like and entered the imaging device1, this light is detected (absorbed) by the PD of each pixel, and red, green, or blue color light is photoelectrically converted. Among electron-hole pairs generated in the PD, signal charges (for example, electrons) are converted into imaging signals and processed at the memory circuit of the memory chip20and the logic circuit of the logic chip30. (Workings and Effects of Imaging Device1) In the present embodiment, the polishing adjustment section23is provided in the memory chip20, and the polishing adjustment section33is provided in the logic chip30. This suppresses excessive polishing of the peripheral regions20B and30B during polishing of the semiconductor substrates21W and31W (seeFIG.9H) in the process of manufacturing the imaging device1. The workings and the effects are described below with use of a comparative example. FIGS.11A and11Billustrate a method of manufacturing an imaging device according to a comparative example in order of processes. In this method also, first, the semiconductor substrates21W and31W in wafer form and the wiring layers22and32are cut to be divided into pieces in a similar manner to the method of manufacturing the imaging device1described above, following which they are bonded to the semiconductor substrate11W in wafer form (FIG.11A). Next, the semiconductor substrates21W and31W are thinned by using, for example, a CMP method (FIG.11B). A memory chip120and a logic chip130are thereby formed. In the method of manufacturing the imaging device according to the comparative example, neither of the semiconductor substrates21W and31W is provided with a polishing adjustment section (for example, the polishing adjustment section23or33inFIG.2orFIG.3). Therefore, when the semiconductor substrate21W or31W is thinned by using a CMP method, for example, a corner of the semiconductor substrate21W or31W (a corner E inFIG.12to be described later) is more susceptible to polishing as compared with other portions). One reason for this is that a stress of a polishing pad is exerted more greatly on the corner of the semiconductor substrate21W or31W than on the other portions. FIG.12illustrates the logic chip130illustrated inFIG.11Bon an enlarged scale. As illustrated, in the method of manufacturing the imaging device according to the comparative example, the corner E of the semiconductor substrate31W (or the semiconductor substrate21W) is excessively polished, and it is thus difficult to form a flat surface of the semiconductor substrate31W at the corner E. If flatness of the buried layer (see the buried layer50inFIG.1) is degraded due to the corner E of the semiconductor substrate31W, a bonding failure can occur between the support substrate (the support substrate40inFIG.1) and each of the memory chip120and the logic chip130. Further, when the semiconductor substrate21W or31W in wafer form and the wiring layer22or32are divided into pieces, a contaminant1M adhering to a peripheral edge of the semiconductor substrate21W or31W can enter the memory circuit or the logic circuit via the semiconductor substrate21W or31W. The entry of the contaminant degrades the characteristics of the imaging device. In contrast, in the present embodiment, the memory chip20and the logic chip30have the polishing adjustment sections23and33in the peripheral regions20B and30B. The polishing adjustment sections23and33have a lower polishing rate than a polishing rate of the semiconductor substrates21W and31W. Accordingly, even the peripheral regions20B and30B, which are more susceptible to polishing, are polished at a rate similar to that of the other portions, and a flat surface is thus formed across the wiring regions20A and30A and the peripheral regions20B and30B (in particular, corners). This causes the flatness of the buried layer50to be higher as compared with that in the imaging device according to the comparative example described above, thus making it possible to suppress the occurrence of a bonding failure between each of the memory chip20and the logic chip30and the support substrate40. For example, when the semiconductor substrates21W and31W in wafer form and the wiring layers22and32are divided into pieces (FIG.9F), contaminants can adhere to the peripheral edges (in the vicinity of the lines DL) of the semiconductor substrates21W and31W. However, in the imaging device1, the polishing adjustment sections23and33suppress entry of the contaminants into the memory circuit and the logic circuit (the wiring regions20A and30A). In particular, forming the polishing adjustment sections23and33using silicon nitride (SiN) makes it possible to suppress the entry of contaminants effectively. With the imaging device1, it is thus possible to suppress degradation of characteristics caused by the contaminants. As described above, in the present embodiment, the polishing adjustment sections23and33are provided in the memory chip20and the logic chip30. This makes it possible to suppress local excessive polishing of the semiconductor substrates21W and31W in the process of manufacturing the imaging device1. Accordingly, it is possible to suppress the occurrence of a defect during manufacture. Application Example The imaging device1described above is applicable, for example, to various types of electronic apparatuses such as a camera.FIG.13illustrates a schematic configuration of an electronic apparatus5(a camera) as an example thereof. The electronic apparatus5is, for example, a camera that is able to shoot a still image or a moving image. The electronic apparatus5includes the imaging device1, an optical system (an optical lens)310, a shutter device311, a driver313that drives the imaging device1and the shutter device311, and a signal processor312. The optical system310guides image light (incident light) from a subject to the imaging device1. The optical system310may include a plurality of optical lenses. The shutter device311controls a period during which the imaging device1is to be irradiated with light and a period during which the light is to be blocked. The driver313controls a transfer operation of the imaging device1and a shutter operation of the shutter device311. The signal processor312performs various kinds of signal processing on a signal outputted from the imaging device1. An image signal Dout having been subjected to the signal processing is stored in a storage medium such as a memory or outputted to a monitor or the like. <Example of Practical Application to In-Vivo Information Acquisition System> Further, the technology according to the present disclosure (present technology) is applicable to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system. FIG.14is a block diagram depicting an example of a schematic configuration of an in-vivo information acquisition system of a patient using a capsule type endoscope, to which the technology according to an embodiment of the present disclosure (present technology) can be applied. The in-vivo information acquisition system10001includes a capsule type endoscope10100and an external controlling apparatus10200. The capsule type endoscope10100is swallowed by a patient at the time of inspection. The capsule type endoscope10100has an image pickup function and a wireless communication function and successively picks up an image of the inside of an organ such as the stomach or an intestine (hereinafter referred to as in-vivo image) at predetermined intervals while it moves inside of the organ by peristaltic motion for a period of time until it is naturally discharged from the patient. Then, the capsule type endoscope10100successively transmits information of the in-vivo image to the external controlling apparatus10200outside the body by wireless transmission. The external controlling apparatus10200integrally controls operation of the in-vivo information acquisition system10001. Further, the external controlling apparatus10200receives information of an in-vivo image transmitted thereto from the capsule type endoscope10100and generates image data for displaying the in-vivo image on a display apparatus (not depicted) on the basis of the received information of the in-vivo image. In the in-vivo information acquisition system10001, an in-vivo image imaged a state of the inside of the body of a patient can be acquired at any time in this manner for a period of time until the capsule type endoscope10100is discharged after it is swallowed. A configuration and functions of the capsule type endoscope10100and the external controlling apparatus10200are described in more detail below. The capsule type endoscope10100includes a housing10101of the capsule type, in which a light source unit10111, an image pickup unit10112, an image processing unit10113, a wireless communication unit10114, a power feeding unit10115, a power supply unit10116and a control unit10117are accommodated. The light source unit10111includes a light source such as, for example, a light emitting diode (LED) and irradiates light on an image pickup field-of-view of the image pickup unit10112. The image pickup unit10112includes an image pickup element and an optical system including a plurality of lenses provided at a preceding stage to the image pickup element. Reflected light (hereinafter referred to as observation light) of light irradiated on a body tissue which is an observation target is condensed by the optical system and introduced into the image pickup element. In the image pickup unit10112, the incident observation light is photoelectrically converted by the image pickup element, by which an image signal corresponding to the observation light is generated. The image signal generated by the image pickup unit10112is provided to the image processing unit10113. The image processing unit10113includes a processor such as a central processing unit (CPU) or a graphics processing unit (GPU) and performs various signal processes for an image signal generated by the image pickup unit10112. The image processing unit10113provides the image signal for which the signal processes have been performed thereby as RAW data to the wireless communication unit10114. The wireless communication unit10114performs a predetermined process such as a modulation process for the image signal for which the signal processes have been performed by the image processing unit10113and transmits the resulting image signal to the external controlling apparatus10200through an antenna10114A. Further, the wireless communication unit10114receives a control signal relating to driving control of the capsule type endoscope10100from the external controlling apparatus10200through the antenna10114A. The wireless communication unit10114provides the control signal received from the external controlling apparatus10200to the control unit10117. The power feeding unit10115includes an antenna coil for power reception, a power regeneration circuit for regenerating electric power from current generated in the antenna coil, a voltage booster circuit and so forth. The power feeding unit10115generates electric power using the principle of non-contact charging. The power supply unit10116includes a secondary battery and stores electric power generated by the power feeding unit10115. InFIG.14, in order to avoid complicated illustration, an arrow mark indicative of a supply destination of electric power from the power supply unit10116and so forth are omitted. However, electric power stored in the power supply unit10116is supplied to and can be used to drive the light source unit10111, the image pickup unit10112, the image processing unit10113, the wireless communication unit10114and the control unit10117. The control unit10117includes a processor such as a CPU and suitably controls driving of the light source unit10111, the image pickup unit10112, the image processing unit10113, the wireless communication unit10114and the power feeding unit10115in accordance with a control signal transmitted thereto from the external controlling apparatus10200. The external controlling apparatus10200includes a processor such as a CPU or a GPU, a microcomputer, a control board or the like in which a processor and a storage element such as a memory are mixedly incorporated. The external controlling apparatus10200transmits a control signal to the control unit10117of the capsule type endoscope10100through an antenna10200A to control operation of the capsule type endoscope10100. In the capsule type endoscope10100, an irradiation condition of light upon an observation target of the light source unit10111can be changed, for example, in accordance with a control signal from the external controlling apparatus10200. Further, an image pickup condition (for example, a frame rate, an exposure value or the like of the image pickup unit10112) can be changed in accordance with a control signal from the external controlling apparatus10200. Further, the substance of processing by the image processing unit10113or a condition for transmitting an image signal from the wireless communication unit10114(for example, a transmission interval, a transmission image number or the like) may be changed in accordance with a control signal from the external controlling apparatus10200. Further, the external controlling apparatus10200performs various image processes for an image signal transmitted thereto from the capsule type endoscope10100to generate image data for displaying a picked up in-vivo image on the display apparatus. As the image processes, various signal processes can be performed such as, for example, a development process (demosaic process), an image quality improving process (bandwidth enhancement process, a super-resolution process, a noise reduction (NR) process and/or image stabilization process) and/or an enlargement process (electronic zooming process). The external controlling apparatus10200controls driving of the display apparatus to cause the display apparatus to display a picked up in-vivo image on the basis of generated image data. Alternatively, the external controlling apparatus10200may also control a recording apparatus (not depicted) to record generated image data or control a printing apparatus (not depicted) to output generated image data by printing. The description has been given above of one example of the in-vivo information acquisition system to which the technology according to the present disclosure is applicable. The technology according to the present disclosure is applicable to, for example, the image pickup unit10112among the configurations described above. This makes it possible to improve accuracy of detection. <Example of Practical Application to Endoscopic Surgery System> The technology according to the present disclosure (present technology) is applicable to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system. FIG.15is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied. InFIG.15, a state is illustrated in which a surgeon (medical doctor)11131is using an endoscopic surgery system11000to perform surgery for a patient11132on a patient bed11133. As depicted, the endoscopic surgery system11000includes an endoscope11100, other surgical tools11110such as a pneumoperitoneum tube11111and an energy device11112, a supporting arm apparatus11120which supports the endoscope11100thereon, and a cart11200on which various apparatus for endoscopic surgery are mounted. The endoscope11100includes a lens barrel11101having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient11132, and a camera head11102connected to a proximal end of the lens barrel11101. In the example depicted, the endoscope11100is depicted which includes as a rigid endoscope having the lens barrel11101of the hard type. However, the endoscope11100may otherwise be included as a flexible endoscope having the lens barrel11101of the flexible type. The lens barrel11101has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus11203is connected to the endoscope11100such that light generated by the light source apparatus11203is introduced to a distal end of the lens barrel11101by a light guide extending in the inside of the lens barrel11101and is irradiated toward an observation target in a body cavity of the patient11132through the objective lens. It is to be noted that the endoscope11100may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope. An optical system and an image pickup element are provided in the inside of the camera head11102such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU11201. The CCU11201includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope11100and a display apparatus11202. Further, the CCU11201receives an image signal from the camera head11102and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process). The display apparatus11202displays thereon an image based on an image signal, for which the image processes have been performed by the CCU11201, under the control of the CCU11201. The light source apparatus11203includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope11100. An inputting apparatus11204is an input interface for the endoscopic surgery system11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system11000through the inputting apparatus11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope11100. A treatment tool controlling apparatus11205controls driving of the energy device11112for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus11206feeds gas into a body cavity of the patient11132through the pneumoperitoneum tube11111to inflate the body cavity in order to secure the field of view of the endoscope11100and secure the working space for the surgeon. A recorder11207is an apparatus capable of recording various kinds of information relating to surgery. A printer11208is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph. It is to be noted that the light source apparatus11203which supplies irradiation light when a surgical region is to be imaged to the endoscope11100may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head11102are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element. Further, the light source apparatus11203may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head11102in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created. Further, the light source apparatus11203may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus11203can be configured to supply such narrow-band light and/or excitation light suitable for special light observation as described above. FIG.16is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG.15. The camera head11102includes a lens unit11401, an image pickup unit11402, a driving unit11403, a communication unit11404and a camera head controlling unit11405. The CCU11201includes a communication unit11411, an image processing unit11412and a control unit11413. The camera head11102and the CCU11201are connected for communication to each other by a transmission cable11400. The lens unit11401is an optical system, provided at a connecting location to the lens barrel11101. Observation light taken in from a distal end of the lens barrel11101is guided to the camera head11102and introduced into the lens unit11401. The lens unit11401includes a combination of a plurality of lenses including a zoom lens and a focusing lens. The number of image pickup elements which is included by the image pickup unit11402may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit11402is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit11402may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon11131. It is to be noted that, where the image pickup unit11402is configured as that of stereoscopic type, a plurality of systems of lens units11401are provided corresponding to the individual image pickup elements. Further, the image pickup unit11402may not necessarily be provided on the camera head11102. For example, the image pickup unit11402may be provided immediately behind the objective lens in the inside of the lens barrel11101. The driving unit11403includes an actuator and moves the zoom lens and the focusing lens of the lens unit11401by a predetermined distance along an optical axis under the control of the camera head controlling unit11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit11402can be adjusted suitably. The communication unit11404includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU11201. The communication unit11404transmits an image signal acquired from the image pickup unit11402as RAW data to the CCU11201through the transmission cable11400. In addition, the communication unit11404receives a control signal for controlling driving of the camera head11102from the CCU11201and supplies the control signal to the camera head controlling unit11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and/or information that a magnification and a focal point of a picked up image are designated. It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit11413of the CCU11201on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope11100. The camera head controlling unit11405controls driving of the camera head11102on the basis of a control signal from the CCU11201received through the communication unit11404. The communication unit11411includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head11102. The communication unit11411receives an image signal transmitted thereto from the camera head11102through the transmission cable11400. Further, the communication unit11411transmits a control signal for controlling driving of the camera head11102to the camera head11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like. The image processing unit11412performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head11102. The control unit11413performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope11100and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit11413creates a control signal for controlling driving of the camera head11102. Further, the control unit11413controls, on the basis of an image signal for which image processes have been performed by the image processing unit11412, the display apparatus11202to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit11413may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit11413can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device11112is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit11413may cause, when it controls the display apparatus11202to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon11131, the burden on the surgeon11131can be reduced and the surgeon11131can proceed with the surgery with certainty. The transmission cable11400which connects the camera head11102and the CCU11201to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications. Here, while, in the example depicted, communication is performed by wired communication using the transmission cable11400, the communication between the camera head11102and the CCU11201may be performed by wireless communication. The description has been given above of one example of the endoscopic surgery system to which the technology according to the present disclosure is applicable. The technology according to the present disclosure is applicable to, for example, the image pickup unit11402among the configurations described above. Applying the technology according to the present disclosure to the image pickup unit11402makes it possible to improve accuracy of detection. It is to be noted that although the endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to, for example, a microscopic surgery system, and the like. <Example of Practical Application to Mobile Body> The technology according to the present disclosure is applicable to various products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as a vehicle, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, a robot, a construction machine, or an agricultural machine (tractor). FIG.17is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied. The vehicle control system12000includes a plurality of electronic control units connected to each other via a communication network12001. In the example depicted inFIG.17, the vehicle control system12000includes a driving system control unit12010, a body system control unit12020, an outside-vehicle information detecting unit12030, an in-vehicle information detecting unit12040, and an integrated control unit12050. In addition, a microcomputer12051, a sound/image output section12052, and a vehicle-mounted network interface (I/F)12053are illustrated as a functional configuration of the integrated control unit12050. The driving system control unit12010controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit12010functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like. The body system control unit12020controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit12020functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit12020. The body system control unit12020receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle. The outside-vehicle information detecting unit12030detects information about the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit12030is connected with an imaging section12031. The outside-vehicle information detecting unit12030makes the imaging section12031image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit12030may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto. The imaging section12031is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section12031can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like. The in-vehicle information detecting unit12040detects information about the inside of the vehicle. The in-vehicle information detecting unit12040is, for example, connected with a driver state detecting section12041that detects the state of a driver. The driver state detecting section12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section12041, the in-vehicle information detecting unit12040may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing. The microcomputer12051can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040, and output a control command to the driving system control unit12010. For example, the microcomputer12051can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like. In addition, the microcomputer12051can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040. In addition, the microcomputer12051can output a control command to the body system control unit12020on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030. For example, the microcomputer12051can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit12030. The sound/image output section12052transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example ofFIG.17, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display and a head-up display. FIG.18is a diagram depicting an example of the installation position of the imaging section12031. InFIG.18, the imaging section12031includes imaging sections12101,12102,12103,12104, and12105. The imaging sections12101,12102,12103,12104, and12105are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle12100as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section12101provided to the front nose and the imaging section12105provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided to the sideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section12104provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The imaging section12105provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like. Incidentally,FIG.18depicts an example of photographing ranges of the imaging sections12101to12104. An imaging range12111represents the imaging range of the imaging section12101provided to the front nose. Imaging ranges12112and12113respectively represent the imaging ranges of the imaging sections12102and12103provided to the sideview mirrors. An imaging range12114represents the imaging range of the imaging section12104provided to the rear bumper or the back door. A bird's-eye image of the vehicle12100as viewed from above is obtained by superimposing image data imaged by the imaging sections12101to12104, for example. At least one of the imaging sections12101to12104may have a function of obtaining distance information. For example, at least one of the imaging sections12101to12104may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection. For example, the microcomputer12051can determine a distance to each three-dimensional object within the imaging ranges12111to12114and a temporal change in the distance (relative speed with respect to the vehicle12100) on the basis of the distance information obtained from the imaging sections12101to12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle12100and which travels in substantially the same direction as the vehicle12100at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer12051can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like. For example, the microcomputer12051can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections12101to12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer12051identifies obstacles around the vehicle12100as obstacles that the driver of the vehicle12100can recognize visually and obstacles that are difficult for the driver of the vehicle12100to recognize visually. Then, the microcomputer12051determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer12051outputs a warning to the driver via the audio speaker12061or the display section12062, and performs forced deceleration or avoidance steering via the driving system control unit12010. The microcomputer12051can thereby assist in driving to avoid collision. At least one of the imaging sections12101to12104may be an infrared camera that detects infrared rays. The microcomputer12051can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections12101to12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections12101to12104as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer12051determines that there is a pedestrian in the imaged images of the imaging sections12101to12104, and thus recognizes the pedestrian, the sound/image output section12052controls the display section12062so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section12052may also control the display section12062so that an icon or the like representing the pedestrian is displayed at a desired position. The description has been given above of one example of the vehicle control system to which the technology according to the present disclosure is applicable. The technology according to the present disclosure is applicable to, for example, the imaging section12031among the configurations described above. Applying the technology according to the present disclosure to the imaging section12031makes it possible to obtain a captured image that is easier to see. Hence, it is possible to reduce fatigue of the driver. The description has been given with reference to the embodiment; however, the contents of the present disclosure are not limited to the above-described embodiment, and may be modified in a variety of ways. For example, the configuration of the imaging device described in the embodiment above is merely exemplary, and may further include any other layer. In addition, the material and thickness of each layer are merely exemplary as well, and are not limited to those described above. Further, in the embodiment above, description has been given of an example where the imaging device1includes the imaging element10, the memory chip20, and the logic chip30; however, it is sufficient that the imaging device1includes at least two semiconductor chips. Further, the imaging device1may include four or more semiconductor chips. Further, in the embodiment above, description has been given of a case where the CuCu junction is used to couple the memory chip20and the imaging element10to each other, and to couple the logic chip30and the imaging element10to each other; however, they may be coupled using any other method. For example, they may be coupled using a rewiring layer, or alternatively, they may be electrically coupled by any other method such as a through electrode. Further, in the embodiment above, description has been given of a case where the polishing adjustment sections (the polishing adjustment sections23and33) are provided in both of the memory chip20and the logic chip30; however, a polishing adjustment section may be provided in one of the memory chip20and the logic chip30. Further, in the embodiment above, description has been given of a case where the memory chip20and the logic chip30are coupled to the imaging element10; however, any chip to be coupled to the imaging element10may have any other configuration. It is to be noted that the effects described in the embodiment and the like above are merely exemplary, and may be any other effects or may further include any other effects. It is to be noted that the present disclosure may have the following configurations. According to the imaging device having the following configurations, the provision of the polishing adjustment section in the semiconductor element makes it possible to suppress local excessive polishing of the semiconductor substrate in the process of manufacturing the imaging device. Accordingly, it is possible to suppress the occurrence of a defect during manufacture.(1) An imaging device including an imaging element, and a semiconductor element provided to be opposed to the imaging element and electrically coupled to the imaging element, in which the semiconductor element includes: a wiring region provided in a middle portion and a peripheral region outside the wiring region; a wiring layer having a wiring line in the wiring region; a semiconductor substrate opposed to the imaging element with the wiring layer interposed therebetween and having a first surface and a second surface in order from a side of the wiring layer; and a polishing adjustment section including a material that is lower in polishing rate than a constituent material of the semiconductor substrate, the polishing adjustment section being disposed in at least a portion of the peripheral region and provided in a thickness direction of the semiconductor substrate from the second surface.(2) The imaging device according to (1), in which a planar shape of the semiconductor substrate includes a corner, and the polishing adjustment section is provided at least at the corner.(3) The imaging device according to (1) or (2), in which the polishing adjustment section is provided to surround the wiring region.(4) The imaging device according to (1) or (2), in which a plurality of the polishing adjustment sections are disposed to be separated from each other around the wiring region.(5) The imaging device according to any one of (1) to (4), in which the polishing adjustment section includes a first polishing adjustment section, and a second polishing adjustment section disposed at a position farther from the wiring region than the first polishing adjustment section.(6) The imaging device according to any one of (1) to (5), in which the polishing adjustment section is provided in the semiconductor substrate and the wiring layer.(7) The imaging device according to any one of (1) to (6), further including a support substrate opposed to the imaging element with the semiconductor element interposed therebetween.(8) The imaging device according to (7), further including, between the support substrate and the imaging element, a buried layer surrounding the semiconductor element.(9) The imaging device according to any one of (1) to (8), including a plurality of the semiconductor elements.(10) The imaging device according to any one of (1) to (9), in which the polishing adjustment section includes silicon nitride or silicon oxide. This application claims priority from Japanese Patent Application No. 2018-202769 filed on Oct. 29, 2018 with the Japan Patent Office, the entire contents of which are incorporated in the present application by reference. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof. | 70,914 |
11862663 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS In the following, the technical solutions in the embodiments of the present disclosure will be clearly and completely described with reference to the figures. Obviously, the described embodiments are only some embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative steps shall fall within the protection scope of the present disclosure. In the description of the present disclosure, it should be understood that the terms of center, longitudinal, transverse, length, width, thickness, upper, lower, front, rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. or a positional relationship based on orientation or position shown in the figures are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying the device or element referred to must have a specific orientation, structure, or operation. Therefore, it cannot be understood as a limitation of the present disclosure. In addition, the terms “first” and “second” are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of “a plurality” is two or more, unless otherwise specifically limited. In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms “install”, “link”, and “connect” should be understood in a broad sense, for example, it can be fixed connection or detachable connection, or integrally connection; may be mechanical connection, electrical connection, or may be signal connect with each other; which may be directly connected, or may be indirectly connected through an intermediary, may be a connection between two elements or the interaction relationship of two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present disclosure according to specific situations. In the present disclosure, unless otherwise clearly specified and defined, the first feature “above” or “below” the second feature may include a direct contact between the first feature and second feature, or may include the first feature and second feature not contact directly but through another feature between them. Moreover, the first feature is “above”, “on” or “upon” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that a horizontal level of the first feature is higher than a horizontal level of the second feature. The first feature is “below”, “under” and “underneath” the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that a horizontal level of the first feature is less than a horizontal level of the second feature. The following disclosure provides many different implementations or examples for implementing different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and/or reference letters in different embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or settings discussed. In addition, the present disclosure provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and/or the use of other materials. As shown inFIG.1andFIG.2, the present disclosure provides a display panel including a first display area10and a second display area20disposed corresponding to a position of an electronic component, wherein a light transmittance of the second display area20is greater than a light transmittance of the first display area10, and a plurality of pixel units30are disposed in the second display area20. Each of the pixel units comprises a plurality of first sub-pixels301, a plurality of second sub-pixels302, and a plurality of third sub-pixels303; a ratio of a number of the first sub-pixels301to the second sub-pixels302and the third sub-pixels303is 1:1:2 in each of the pixel units30of the second display area20. In one embodiment of the present disclosure, the display panel includes a first display area10and a second display area20disposed corresponding to a position of an electronic component, wherein a light transmittance of the second display area20is greater than a light transmittance of the first display area10, and the plurality of pixel units30are disposed in the second display area20. Each of the pixel units30comprises the plurality of first sub-pixels301, the plurality of second sub-pixels302, and the plurality of third sub-pixels303; the ratio of a number of the first sub-pixels301to the second sub-pixels302and the third sub-pixels303is 1:1:2 in each of the pixel units of the second display area. By providing pixels with larger intervals in the second display area20, a light transmittance above the electronic component in the second display area20is increased. In one embodiment, the plurality of pixel units30are disposed in the first display area10, and each of the pixel units30comprises the plurality of first sub-pixels301, the plurality of second sub-pixels302, and the plurality of third sub-pixels303, the ratio of a number of the first sub-pixels301to the second sub-pixels302and the third sub-pixels303is 1:1:1 in each of the pixel units30of the first display area10. In one embodiment, as shown inFIG.1, an angle between any sub-pixel and two adjacent sub-pixels in the second display area20is 120 degrees. In one embodiment, in the second display area20, the distances between the first sub-pixels301and the plurality of closest third sub-pixels303are the same. In one embodiment, in the second display area20, the distances between the second sub-pixels302and the plurality of closest third sub-pixels303are the same. In one embodiment, as shown inFIG.2, the plurality of third sub-pixels303are red sub-pixels. In this embodiment, the plurality of first sub-pixels301are blue sub-pixels, and the plurality of second sub-pixels302are green sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are green sub-pixels, the plurality of second sub-pixels302are blue sub-pixels. In one embodiment, as shown inFIG.3, wherein the plurality of third sub-pixels303are blue sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are red sub-pixels, the plurality of second sub-pixels302are green sub-pixels. In this embodiment, wherein the plurality of first sub-pixel301are green sub-pixels, the plurality of second sub-pixels302are red sub-pixels. In one embodiment, as shown inFIG.4, wherein the plurality of third sub-pixels303are green sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are red sub-pixels, the second sub-pixel302are blue sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are blue sub-pixels, the second sub-pixel302are red sub-pixels. In one embodiment, the size, shape, and color of any sub-pixel can be designed according to the performance, life, and other performances of the red, green, and blue sub-pixels of the actual light-emitting device. In this embodiment, sizes of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are not the same. In this embodiment, shapes of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are not the same. In one embodiment, the first sub-pixel301is at least one of a rectangular, a circular, a trapezoidal, or a triangular shape. In one embodiment, the second sub-pixel302is at least one of a rectangular, a circular, a trapezoidal, or a triangular shape. In one embodiment, the third sub-pixel303is at least one of a rectangular, a circular, a trapezoidal, or a triangular shape. In one embodiment, a metal trace in the second display area20is arranged around the electronic component. In this embodiment, the metal traces include data lines and scan lines. In this embodiment, the data line is arranged around the electronic component. In this embodiment, the scan line is arranged around the electronic component. In one embodiment, the pixel drive circuit is optimized, conductive lines are disposed under the pixel, and a ratio of the circuit drive clearance area is increased. In one embodiment, distances between the adjacent third sub-pixels303are equal in the pixel unit30of the second display area20. In one embodiment, a ratio of a distance between the adjacent first sub-pixels301to a distance between the adjacent second sub-pixels302and a distance between the adjacent third sub-pixels303is 1:1:1 in the pixel unit30of the second display area20. In one embodiment, the electronic component is a camera. In one embodiment, the electronic component is a speaker or microphone. As shown inFIG.1andFIG.2, the present disclosure provides a display device including a display panel, frame structure, and a backlight source; the display panel including the first display area10and the second display area20disposed corresponding to the position of the electronic component, wherein the light transmittance of the second display area20is greater than the light transmittance of the first display area10, the plurality of pixel units30are disposed in the second display area20, and each of the pixel units30comprises the plurality of first sub-pixels301, the plurality of second sub-pixels302, and the plurality of third sub-pixels303, the ratio of a number of the first sub-pixels301to the second sub-pixels302and the third sub-pixels303is 1:1:2 in each of the pixel units30of the second display area20. In one embodiment of the present disclosure, the display device includes the display panel, the frame structure, and the backlight source, the display panel includes the first display area10and the second display area20disposed corresponding to the position of the electronic component, wherein the light transmittance of the second display area20is greater than the light transmittance of the first display area10, the plurality of pixel units30are disposed in the second display area20, and each of the pixel units30comprises the plurality of first sub-pixels301, the plurality of second sub-pixels302, and the plurality of third sub-pixels303, the ratio of a number of the first sub-pixels301to the second sub-pixels and the third sub-pixels is 1:1:2 in each of the pixel units of the second display area, by providing pixels with larger intervals in the second display area20, increasing the light transmittance above the electronic component in the second display area20. In one embodiment, the plurality of pixel units30are disposed in the first display area10, and each of the pixel units30comprises the plurality of first sub-pixels301, the plurality of second sub-pixels302, and the plurality of third sub-pixels303, the ratio of a number of the first sub-pixels301to the second sub-pixels302and the third sub-pixels303is 1:1:1 in each of the pixel units30of the first display area10of the display device. In one embodiment, as shown inFIG.1, wherein the angle between any sub-pixel and two adjacent sub-pixels in the second display area20of the display device is 120 degrees. In one embodiment, in the second display area20of the display device, the distances between the first sub-pixel301and the plurality of the closest third sub-pixels303are the same. In one embodiment, in the second display area20of the display device, the distances between the second sub-pixels302and the plurality of the closest third sub-pixels303are the same. In one embodiment, as shown inFIG.2, wherein the plurality of third sub-pixels303are red sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are blue sub-pixels, the plurality of second sub-pixels302are green sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are green sub-pixels, the plurality of second sub-pixels302are blue sub-pixels. In one embodiment, as shown inFIG.3, wherein the plurality of third sub-pixels303are blue sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are red sub-pixels, the plurality of second sub-pixels302are green sub-pixels. In this embodiment, wherein the plurality of first sub-pixel301are green sub-pixels, the plurality of second sub-pixels302are red sub-pixels. In one embodiment, as shown inFIG.4, wherein the plurality of third sub-pixels303are green sub-pixels in the display device. In this embodiment, wherein the plurality of first sub-pixels301are red sub-pixels, the second sub-pixel302are blue sub-pixels. In this embodiment, wherein the plurality of first sub-pixels301are blue sub-pixels, the second sub-pixel302are red sub-pixels. In one embodiment, the size, shape, and color of any sub-pixel can be designed according to the performance, life, and other performances of the red, green, and blue sub-pixels of the actual light-emitting device. In this embodiment, sizes of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are not the same. In this embodiment, shapes of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are not the same. In one embodiment, the first sub-pixel301is at least one of a rectangular, a circular, a trapezoidal, or a triangular shape in the display device. In one embodiment, the second sub-pixel302is at least one of a rectangular, a circular, a trapezoidal, or a triangular shape in the display device. In one embodiment, as shown inFIG.5, the third sub-pixel303is at least one of a rectangular, a circular, a trapezoidal, or a triangular shape in the display device. In one embodiment, the metal trace in the second display area20is arranged around the electronic component. In this embodiment, the metal traces include data lines and scan lines. In this embodiment, the data line is arranged around the electronic component. In this embodiment, the scan line is arranged around the electronic component. In one embodiment, the pixel drive circuit is optimized conductive lines are disposed under the pixel and the ratio of the circuit drive clearance area is increased. In one embodiment, distances between the adjacent third sub-pixels303are equal in the pixel unit30of the second display area20. In one embodiment, a ratio of a distance between the adjacent first sub-pixels301to a distance between the adjacent second sub-pixels302and a distance between the adjacent third sub-pixels303is 1:1:1 in the pixel unit30of the second display area20. In one embodiment, the electronic component is a camera. According to the above embodiments: The present disclosure provides a display panel, the display panel includes a first display area and a second display area corresponding to a position of an electronic component, a light transmittance of the second display area is greater than a light transmittance of the first display area, a plurality of pixel units are disposed in the second display area, and each of the pixel units comprises a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, a ratio of a number of the first sub-pixels to the second sub-pixels and the third sub-pixels is 1:1:2 in each of the pixel units of the second display area, by providing pixels with larger intervals in the second display area, increasing a light transmittance above the electronic component. In summary, although the present disclosure has been disclosed as preferred embodiments above, the above preferred embodiments are not intended to limit the present disclosure. Those of ordinary skill in the art can make various changes and retouching without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is subject to the scope defined by the claims. | 16,630 |
11862664 | DETAILED DESCRIPTION Electronic devices may be provided with displays. Displays may be used for displaying images for users. Displays may be formed from arrays of light-emitting diode pixels or other pixels. For example, a device may have an organic light-emitting diode display or a display formed from an array of micro-light-emitting diodes (e.g., diodes formed from crystalline semiconductor dies). A schematic diagram of an illustrative electronic device having a display is shown inFIG.1. Device10may be a cellular telephone, tablet computer, laptop computer, wristwatch device or other wearable device, a television, a stand-alone computer display or other monitor, a computer display with an embedded computer (e.g., a desktop computer), a system embedded in a vehicle, kiosk, or other embedded electronic device, a media player, or other electronic equipment. Configurations in which device10is a cellular telephone, tablet computer, or other portable electronic device may sometimes be described herein as an example. This is illustrative. Device10may, in general, be any suitable electronic device with a display. Device10may include control circuitry20. Control circuitry20may include storage and processing circuitry for supporting the operation of device10. The storage and processing circuitry may include storage such as nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in control circuitry20may be used to gather input from sensors and other input devices and may be used to control output devices. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors and other wireless communications circuits, power management units, audio chips, application specific integrated circuits, etc. During operation, control circuitry20may use a display and other output devices in providing a user with visual output and other output. To support communications between device10and external equipment, control circuitry20may communicate using communications circuitry22. Circuitry22may include antennas, radio-frequency transceiver circuitry (wireless transceiver circuitry), and other wireless communications circuitry and/or wired communications circuitry. Circuitry22, which may sometimes be referred to as control circuitry and/or control and communications circuitry, may support bidirectional wireless communications between device10and external equipment over a wireless link (e.g., circuitry22may include radio-frequency transceiver circuitry such as wireless local area network transceiver circuitry configured to support communications over a wireless local area network link, near-field communications transceiver circuitry configured to support communications over a near-field communications link, cellular telephone transceiver circuitry configured to support communications over a cellular telephone link, or transceiver circuitry configured to support communications over any other suitable wired or wireless communications link). Wireless communications may, for example, be supported over a Bluetooth® link, a WiFi® link, a wireless link operating at a frequency between 6 GHz and 300 GHz, a 60 GHz link, or other millimeter wave link, cellular telephone link, wireless local area network link, personal area network communications link, or other wireless communications link. Device10may, if desired, include power circuits for transmitting and/or receiving wired and/or wireless power and may include batteries or other energy storage devices. For example, device10may include a coil and rectifier to receive wireless power that is provided to circuitry in device10. Device10may include input-output devices such as devices24. Input-output devices24may be used in gathering user input, in gathering information on the environment surrounding the user, and/or in providing a user with output. Devices24may include one or more displays such as display14. Display14may be an organic light-emitting diode display, a liquid crystal display, an electrophoretic display, an electrowetting display, a plasma display, a microelectromechanical systems display, a display having a pixel array formed from crystalline semiconductor light-emitting diode dies (sometimes referred to as microLEDs), and/or other display. Configurations in which display14is an organic light-emitting diode display or microLED display are sometimes described herein as an example. Display14may have an array of pixels configured to display images for a user. The pixels may be formed as part of a display panel that is bendable. This allows device10to be folded and unfolded about a bend axis. For example, a flexible (bendable) display in device10may be folded so that device10may be placed in a compact shape for storage and may be unfolded when it is desired to view images on the display. Sensors16in input-output devices24may include force sensors (e.g., strain gauges, capacitive force sensors, resistive force sensors, etc.), audio sensors such as microphones, touch and/or proximity sensors such as capacitive sensors (e.g., a two-dimensional capacitive touch sensor integrated into display14, a two-dimensional capacitive touch sensor overlapping display14, and/or a touch sensor that forms a button, trackpad, or other input device not associated with a display), and other sensors. If desired, sensors16may include optical sensors such as optical sensors that emit and detect light, ultrasonic sensors, optical touch sensors, optical proximity sensors, and/or other touch sensors and/or proximity sensors, monochromatic and color ambient light sensors, image sensors, fingerprint sensors, temperature sensors, sensors for measuring three-dimensional non-contact gestures (“air gestures”), pressure sensors, sensors for detecting position, orientation, and/or motion (e.g., accelerometers, magnetic sensors such as compass sensors, gyroscopes, and/or inertial measurement units that contain some or all of these sensors), health sensors, radio-frequency sensors, depth sensors (e.g., structured light sensors and/or depth sensors based on stereo imaging devices that capture three-dimensional images), optical sensors such as self-mixing sensors and light detection and ranging (lidar) sensors that gather time-of-flight measurements, humidity sensors, moisture sensors, gaze tracking sensors, and/or other sensors. In some arrangements, device10may use sensors16and/or other input-output devices to gather user input. For example, buttons may be used to gather button press input, touch sensors overlapping displays can be used for gathering user touch screen input, touch pads may be used in gathering touch input, microphones may be used for gathering audio input, accelerometers may be used in monitoring when a finger contacts an input surface and may therefore be used to gather finger press input, etc. If desired, electronic device10may include additional components (see, e.g., other devices18in input-output devices24). The additional components may include haptic output devices, audio output devices such as speakers, light-emitting diodes for status indicators, light sources such as light-emitting diodes that illuminate portions of a housing and/or display structure, other optical output devices, and/or other circuitry for gathering input and/or providing output. Device10may also include a battery or other energy storage device, connector ports for supporting wired communication with ancillary equipment and for receiving wired power, and other circuitry. FIG.2is a perspective view of electronic device10in an illustrative configuration in which device10is a portable electronic device such as a cellular telephone or tablet computer. As shown inFIG.2, device10may have a display such as display14. Display14may cover some or all of the front face of device10. Touch sensor circuitry such as two-dimensional capacitive touch sensor circuitry may be incorporated into display14. Display14may be mounted in housing12. Housing12may form front and rear housing walls, sidewall structures, and/or internal supporting structures (e.g., a frame, an optional midplate member, etc.) for device10. Glass structures, transparent polymer structures, and/or other transparent structures that cover display14and other portions of device10may provide structural support for device10and may sometimes be referred to as housing structures. For example, a transparent housing portion such as a glass or polymer housing structure that covers and protects a pixel array in display14may serve as a display cover layer for the pixel array while also serving as a housing wall on the front face of device10. In configurations in which a display cover layer is formed from glass, the display cover layer may sometime be referred to as a display cover glass or display cover glass layer. The portions of housing12on the sidewalls and rear wall of device10may be formed from glass or other transparent structures and/or opaque structures. Sidewalls and rear wall structures may be formed as extensions to the front portion of housing12(e.g., as integral portions of the display cover layer) and/or may include separate housing wall structures. Housing12may have flexible structures (e.g., bendable housing wall structures) and/or hinge structures such as hinge30. Hinge30may have a hinge axis aligned with device bend axis28. Hinge30and/or flexible housing structures that overlap bend axis28may allow housing12to bend about bend axis28. For example, housing12may have a first portion on one side of bend axis28and a second portion on an opposing side of bend axis28and these two housing portions may be coupled by hinge30for rotational motion about axis28. As housing12is bent about bend axis28, the flexibility of display14allows display14to bend about axis28. In an illustrative configuration, housing12and display14may bend by 180°. This allows display14to be folded back on itself (with first and second outwardly-facing portions of display14facing each other). The ability to place device10in a folded configuration in this way may help make device10compact so that device10can be stored efficiently. When it is desired to view images on display14, device10may be unfolded about axis28to place device10in the unfolded configuration ofFIG.2. This allows display14to lie flat and allows a user to view flat images on display14. The ability to fold display14onto itself allows device10to exhibit an inwardly folding behavior. Display14may be sufficiently flexible to allow device10to be folded outwardly and/or inwardly. Device10ofFIG.2has a rectangular outline (rectangular periphery) with four corners. As shown inFIG.2, a first pair of parallel edges (e.g., the left and right edges of device10in the example ofFIG.2) may be longer than a second pair of parallel edges (e.g., the upper and lower edges of device10ofFIG.2) that are oriented at right angles to the first pair of parallel edges. In this type of configuration, housing12is elongated along a longitudinal axis that is perpendicular to bend axis28. Housing12may have other shapes, if desired (e.g., shapes in which housing12has a longitudinal axis that extends parallel to bend axis28). With an arrangement of the type shown inFIG.2, the length of device10along its longitudinal axis may be reduced by folding device10about axis28. FIG.3is a cross-sectional side view of an illustrative foldable electronic device. Device10ofFIG.3may bend about bend axis28. Bend axis28may be aligned with display cover layer14CG or other structures in device10. For example, bend axis28may pass through a portion of display cover layer14CG or may be located above or below layer14CG. As shown inFIG.3, display14includes an array of pixels P forming display panel14P under an inwardly facing surface of display cover layer14CG. Display panel14P may be, for example, a flexible organic light-emitting diode display or a microLED display in which light-emitting pixels are formed on a flexible substrate layer (e.g., a flexible layer of polyimide or a sheet of other flexible polymer). Flexible support layer(s) for display14may also be formed from flexible glass, flexible metal, and/or other flexible structures. Display cover layer14CG may be formed from polymer, glass, crystalline materials such as sapphire, other materials, and/or combinations of these materials. To enhance flexibility, a portion of layer14CG that overlaps bend axis28may be locally thinned (e.g., this portion may be thinned relative to portions of layer14CG that do not overlap bend axis28). The thickness of layer14CG (e.g., the non-thinned portions of layer14CG) may be 50-200 microns, 70-150 microns, 100-200 microns, 100-600 microns, at least 100 microns, at least 200 microns, less than 600 microns, less than 400 microns, less than 250 microns, less than 150 microns, less than 100 microns, at least 50 microns, or other suitable thickness. In the example ofFIG.3, housing12has a portion on rear face R that forms a rear housing wall and has side portions forming sidewalls 12 W. The rear housing wall of housing12may form a support layer for components in device10. Housing12may also have one or more interior supporting layers (e.g., frame structures such as an optional midplate, etc.). These interior supporting layers and the rear housing wall may have first and second portions that are coupled to opposing sides of a hinge that is aligned with bend axis28(see, e.g., hinge30ofFIG.2) or may be sufficiently flexible to bend around bend axis28. Electrical components32may be mounted in the interior of device10(e.g., between display14and the rear of housing12. Components32may include circuitry of the type shown inFIG.1(e.g., control circuitry20, communications circuitry22, input-output devices24, batteries, etc.). Display14may be mounted on front face F of device10. When device10is folded about axis28, display cover layer14CG, display panel14P, and the other structures of device10that overlap bend axis28may flex and bend to accommodate folding. The outer and/or inner surfaces of display cover layer14GC may be provided with coatings. These coatings may include, for example, antireflection coatings, anti-scratch coatings, anti-smudge coatings, and/or other coating layers. Consider, as an example, the cross-sectional side view of display cover layer14CG ofFIG.4. As shown inFIG.4, display cover layer may have an outer surface (outwardly facing surface) such as surface40and an opposing inner surface (inwardly facing surface) such as surface42. A strip-shaped region of display cover layer14CG that overlaps and runs parallel to bend axis28may be locally thinned (e.g., a groove or other recess that runs parallel to bend axis28may be formed in layer14CG to form locally thinned portion44of layer14CG). Locally thinned portion44of layer14CG may be thinner than other portions of layer14CG such as non-thinned portions46(which may be, for example, planar glass layer portions of layer14CG). The presence of portion44in display cover layer14CG may facilitate bending of display cover layer14CG about bend axis28. To help planarize inner surface42and thereby facilitate mounting of display panel14P against inner surface42(e.g., with a layer of adhesive), the elongated recess (groove) in the inner surface of layer14CG that forms thinned portion44may be filled with polymer50. Polymer50may be sufficiently flexible to bend about bend axis28when device10is opened and closed. The refractive index of polymer50may be matched to that of display cover layer14CG to help minimize light reflections (e.g., by incorporating inorganic nanoparticles in polymer50). For example, at a wavelength of 500 nm, the refractive index of polymer 50 may differ from that of layer14CG by less than 0.15, less than 0.1, or less than 0.05 (as examples). Coating layers52may be formed on outer surface40. Coating layers52may include, for example, anti-scratch layers (sometimes referred to as hard coats), protective polymer layers, anti-smudge layers, anti-fog layers, antireflection layers, anti-static layers, adhesion layers, and/or other coatings. In some configurations, each of these functions may be implemented using a separate respective coating layer. In other configurations, a single layer may serve multiple functions. In general, coatings such as coatings52may be formed on outer surface40and/or inner surface42. In the illustrative configuration ofFIG.4, coatings52are formed on outer surface40. Coatings52may be provided in any suitable order. As one example, the lowermost coating of coatings52(e.g., a coating layer formed directly on surface40ofFIG.4) may be a hard coat or other anti-scratch layer that helps prevent scratches that could damage layer14CG. An antireflection coating may be formed on top of the anti-scratch layer. The antireflection layer may be a thin-film interference filter antireflection coating containing a stack of thin-film layers such as dielectric sublayers of alternating refractive index. One of the thin-film layers may be a conductive layer such as a transparent semiconductor layer (e.g., an indium tin oxide layer) that serves as an antistatic layer. An anti-smudge coating or anti-fog coating may be formed on top of the antireflection layer. Anti-smudge coatings (e.g., hydrophobic polymer coatings) may help reduce fingerprints and other undesired marks on the surfaces of display14. An example of an anti-smudge coating is a fluoropolymer coating (e.g., a fluoropolymer formed from evaporated perfluoropolyether) that serves as an oleophobic layer. Fluoropolymers can be adhered to underlying coating layers using an intervening adhesion layer. It may be desirable to configure the cross-sectional profile of inner surface42of display cover layer12to help avoid distortion of the image on display panel14P due to changes in the refraction of light from thickness variations. As shown inFIG.5, for example, it may be desirable to provide locally thinned region44with varying thickness portions44T. Portions44T may be tapered and characterized by smoothly and slowly varying thicknesses. Portions44T may be located at the outer edges of locally thinned region44and may provide layer14CG with a gradual transition between the thinnest part of portion44(e.g., thinned portion44M of portion44inFIG.5) and the thicker portions of layer14CG such as non-thinned portions46. By gradually changing the thickness of layer14CG, undesired visual artifacts and stress concentration features may be avoided. In the example ofFIG.5, non-thinned portion46of display cover layer14CG have a thickness T1. Minimum thickness portion44M of locally thinned portion44of display cover layer14CG has a thickness T2. In an illustrative configuration, thickness T1is 50-200 microns, 70-150 microns, 100-200 microns, less than 250 microns, less than 150 microns, less than 100 microns, at least 50 microns, or other suitable thickness. Thickness T2, which is less than T1, is 30 microns, 10-50 microns, at least 7 microns, at least 15 microns, at least 25 microns, less than 100 microns, less than 75 microns, less than 50 microns, less than 40 microns, or other suitable thickness that is sufficiently thin to allow layer14CG to be bent about bend axis28satisfactorily. Inner surface42of display cover layer14CG may have a curved or straight cross-sectional profile in portions44T. In the example ofFIG.5, at least some of portions44T have planar areas characterized by a relatively straight cross-sectional profile. As shown inFIG.5, in portions46, surface42(and opposing planar surface40) of layer14CG may be characterized by a vertical surface normal such as surface normal na, whereas in portions44T, surface42of layer14CG may be characterized by surface normal nb, which is angled away from na by angle A. To ensure that the transition between thickness T1and T2is sufficiently gradual, it may be desirable for the angle A between surface normals na and nb (which is equal to the angle of tilt between the planar horizontally extending inner surface of portions46and the planar inner surfaces of portions44T ofFIG.5) to be relatively small. The value of angle A may be less than 45°, less than 30°, less than 20° less than 15°, less than 10°, less than 5°, 2-15° 3-10°, at least 1°, at least 4°, or other of suitable value. The width W2of portion44M may be at least 0.05 mm, at least 0.1 mm, at least 0.2 mm, at least 0.5 mm, at least 1 mm, at least 2 mm, at least 4 mm, at least 8 mm, at least 1.5 cm, less than 3 cm, less than 2 cm, less than 1 cm, less than 5 mm, less than 2 mm, or other suitable value. The width W1of the transitions formed by varying thickness portions44T may at least 1 mm, at least 2 mm, at least 4 mm, at least 8 mm, at least 1.5 cm, at least 3 cm, at least 8 cm, less than 12 cm, less than 5 cm, less than 3 cm, less than 2 cm, less than 1 cm, less than 5 mm, or other suitable value. FIG.6is a cross-sectional side view of a portion of display cover layer14CG in an illustrative configuration in which varying thickness portion44T has a planar inner surface (e.g., a tilted portion of surface42). As shown in the example ofFIG.7, the regions of surface42where portion44M meets portions44T and the regions of surface42where portions44T meet portions46may have curved cross-sectional profiles (e.g., curved cross-sectional profiles characterized by respective radii of curvature R2and R1, respectively). The values of R1and R2may be, for example, at least 0.05 mm, at least 0.1 mm, at least 0.2 mm, at least 1 mm, at least 1 cm, less than 2 cm, less than 5 mm, less than 3 mm, or other suitable value. By using surfaces with curved cross-sectional profiles for the transition zones between varying thickness portions44T and adjacent portions of layer14CG, stresses and visual artifacts due to the shape of display cover layer14CG may be maintained at satisfactorily low levels. As shown inFIG.8, inner surface42of display cover layer14CG may be provided with a rough texture. The texture of surface42may have a random or pseudorandom pattern and be provided on portion44of display cover layer14CG and/or other portions of display cover layer14CG. Polymer50may be deposited as a liquid in the groove formed from thinned portion44(e.g., under a vacuum) and subsequently cured (e.g., by applying light such as ultraviolet light, by applying heat, by using catalyst, and/or by using other curing techniques). Polymer50may be formed from a flexible material such as silicone or urethane acrylate (as examples). The presence of the rough random texture in surface42may help adhere polymer50to display cover layer14CG. The texture may also help create a gradual change in effective refractive index as layer14CG transitions to polymer50, thereby helping to index discontinuities that could lead to light reflections at the glass-polymer interface. The random pattern of the texture may also help reduce specular light reflections at the interface between layer14CG and polymer50. FIG.9is a cross-sectional side view of a portion of inner surface42having an illustrative rough texture. This texture may be formed, for example, by using a silicone mold or other structure to nano-imprint photoresist with desired surface relief features followed by plasma etching of surface42through the textured photoresist. If desired, thinned portion44and the texture of inner surface42in portion44may be formed using other techniques (e.g., machining, laser processing, wet etching in an etchant such as HF, plasma etching, and/or other glass thinning and texturing techniques). The use of plasma etching through a textured photoresist mask on inner surface42of portion44is illustrative. The rough texture of surface42may be formed by randomly distributed protrusions (peaks). To help prevent light scattering from the features in the textured surface, the textured surface may be configured to exhibit small lateral roughness dimensions LF (e.g., peak-to-peak spacings and/or protrusion full-width-half-maximum values) of less than 1 micron. As an example, LF may be subwavelength in size (e.g., the mean value of the lateral surface roughness dimensions LF may be less than 400 nm, less than 300 nm, less than 200 nm, 50-300 nm, 30-400 nm, etc.). The mean height VF of the protrusions and/or other surface roughness features on surface42may be 200-400 nm, at least 50 nm, at least 100 nm, at least 300 nm, at least 500 nm, less than 1000 nm (1 micron), less than 700 nm, less than 500 nm, less than 350 nm, or less than 120 nm (as examples). As shown inFIG.10, the inner and/or outer surface of display cover layer14CG (in portions44and/or other portions of layer14CG) may be chemically strengthened to form strengthened surface layers60. As an example, layer14CG may be formed from a glass (e.g., aluminosilicate glass) that is chemically strengthened by performing an ion-exchange process on the glass. During the ion-exchange process, smaller ions in the glass are replaced with larger ions. For example, sodium in the glass at the surface of layer14CG may be replaced by potassium. This creates compressive stress in treated surface layers60that helps the glass resist damage from scratching and other wear. As described above, one aspect of the present technology is the gathering and use of information such as information from input-output devices. The present disclosure contemplates that in some instances, data may be gathered that includes personal information data that uniquely identifies or can be used to contact or locate a specific person. Such personal information data can include demographic data, location-based data, telephone numbers, email addresses, twitter ID's, home addresses, data or records relating to a user's health or level of fitness (e.g., vital signs measurements, medication information, exercise information), date of birth, username, password, biometric information, or any other identifying or personal information. The present disclosure recognizes that the use of such personal information, in the present technology, can be used to the benefit of users. For example, the personal information data can be used to deliver targeted content that is of greater interest to the user. Accordingly, use of such personal information data enables users to calculated control of the delivered content. Further, other uses for personal information data that benefit the user are also contemplated by the present disclosure. For instance, health and fitness data may be used to provide insights into a user's general wellness, or may be used as positive feedback to individuals using technology to pursue wellness goals. The present disclosure contemplates that the entities responsible for the collection, analysis, disclosure, transfer, storage, or other use of such personal information data will comply with well-established privacy policies and/or privacy practices. In particular, such entities should implement and consistently use privacy policies and practices that are generally recognized as meeting or exceeding industry or governmental requirements for maintaining personal information data private and secure. Such policies should be easily accessible by users, and should be updated as the collection and/or use of data changes. Personal information from users should be collected for legitimate and reasonable uses of the entity and not shared or sold outside of those legitimate uses. Further, such collection/sharing should occur after receiving the informed consent of the users. Additionally, such entities should consider taking any needed steps for safeguarding and securing access to such personal information data and ensuring that others with access to the personal information data adhere to their privacy policies and procedures. Further, such entities can subject themselves to evaluation by third parties to certify their adherence to widely accepted privacy policies and practices. In addition, policies and practices should be adapted for the particular types of personal information data being collected and/or accessed and adapted to applicable laws and standards, including jurisdiction-specific considerations. For instance, in the United States, collection of or access to certain health data may be governed by federal and/or state laws, such as the Health Insurance Portability and Accountability Act (HIPAA), whereas health data in other countries may be subject to other regulations and policies and should be handled accordingly. Hence different privacy practices should be maintained for different personal data types in each country. Despite the foregoing, the present disclosure also contemplates embodiments in which users selectively block the use of, or access to, personal information data. That is, the present disclosure contemplates that hardware and/or software elements can be provided to prevent or block access to such personal information data. For example, the present technology can be configured to allow users to select to “opt in” or “opt out” of participation in the collection of personal information data during registration for services or anytime thereafter. In another example, users can select not to provide certain types of user data. In yet another example, users can select to limit the length of time user-specific data is maintained. In addition to providing “opt in” and “opt out” options, the present disclosure contemplates providing notifications relating to the access or use of personal information. For instance, a user may be notified upon downloading an application (“app”) that their personal information data will be accessed and then reminded again just before personal information data is accessed by the app. Moreover, it is the intent of the present disclosure that personal information data should be managed and handled in a way to minimize risks of unintentional or unauthorized access or use. Risk can be minimized by limiting the collection of data and deleting data once it is no longer needed. In addition, and when applicable, including in certain health related applications, data de-identification can be used to protect a user's privacy. De-identification may be facilitated, when appropriate, by removing specific identifiers (e.g., date of birth, etc.), controlling the amount or specificity of data stored (e.g., collecting location data at a city level rather than at an address level), controlling how data is stored (e.g., aggregating data across users), and/or other methods. Therefore, although the present disclosure broadly covers use of information that may include personal information data to implement one or more various disclosed embodiments, the present disclosure also contemplates that the various embodiments can also be implemented without the need for accessing personal information data. That is, the various embodiments of the present technology are not rendered inoperable due to the lack of all or a portion of such personal information data. The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination. | 31,432 |
11862665 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIG.s. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various embodiments of the disclosure are directed to provide a MIM capacitor and method of forming the same, which use minimum mask (e.g., photomask) to form the MIM capacitor. FIG.1AtoFIG.1Rare schematic cross-sectional views illustrating a method of manufacturing a semiconductor structure including a metal-insulator-metal (MIM) capacitor according to some embodiments of the disclosure. Referring toFIG.1A, a substrate100is provided. In some embodiments, the substrate100is a semiconductor substrate such as a silicon substrate. The substrate100may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type and/or an n-type dopant) or undoped. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate100may include silicon; germanium; a compound semiconductor including silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some embodiments, a plurality of devices (not shown) are formed in and/or on the substrate100. The devices may include active devices, passive devices, or combinations thereof. For example, the devices may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or the like, or combinations thereof. In some embodiment, transistors may be formed on the substrate100. The transistors may be or include metal-oxide-semiconductor field-effect transistors (MOSFETs), fin type field-effect transistors (FinFETs), gate-all-around (GAA) transistors, or the like, or combinations thereof. In some embodiments, an interconnection structure including a dielectric structure and interconnect wirings are formed over the devices (e.g., transistors) on the substrate100. The interconnection wirings are embedded in the dielectric structure and electrically connected to the devices to form a functional circuit. In some embodiments, the dielectric structure includes inter-layer dielectric layers (ILDs) and inter-metal dielectric layers (IMDs). The interconnect wirings may include multi-layers of conductive lines, conductive vias, and conductive contacts. The conductive contacts may be formed in the ILDs to electrically connect the conductive lines to the devices; the conductive vias may be formed in the IMDs to electrically connect the conductive lines in different tiers. The interconnect wirings may include metal, metal alloy or a combination thereof, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. FIG.1Aschematically illustrates a dielectric layer101of the dielectric structure and conductive features102of the interconnect wirings of the interconnection structure. The conductive features102may be embedded in the dielectric layer101. In some embodiments, the conductive feature102includes a barrier layer and a conductive layer disposed on the barrier layer. The barrier layer may include metal, metal nitride, or a combination thereof, such as titanium, titanium nitride, tantalum nitride, or combinations thereof. The conductive layer may include copper or other suitable metal. In some embodiments, the dielectric layer101and the conductive features102may be located at any suitable tier of the interconnection structure, such as a tier lower than the topmost tier of the interconnection structure. It is understood that, the interconnection structure may include multiple dielectric layers and conductive features underlying and/or overlying the dielectric layer101and the conductive features102, which are not specifically shown inFIG.1A, for the sake of brevity. In some embodiments, a dielectric structure103is formed on the dielectric layer101and the conductive features102. The dielectric structure103includes suitable dielectric materials, such as silicon oxide, tetraethylorthosilicate (TEOS) silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass (USG), plasma enhanced oxide (PEOX)-USG, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), a low-k material having a dielectric constant less than 4 or combinations thereof. The low-k material may include fluorine-doped silicon glass (FSG), hydrogen silsesquioxnane (HSQ), methyl silsesquioxane (MSQ), hybrido-organo siloxane polymer (HOSP); aromatic hydrocarbon such as SiLK, or the like. The dielectric structure103may be a single-layer structure or a multi-layer structure. In some embodiments, the dielectric structure103is a multi-layer structure and includes a dielectric layer103aand a dielectric layer103bdisposed on the dielectric layer103a. The materials of the dielectric layers103aand103bmay be the same or different. In an embodiment, the dielectric layer103amay include SiCN, while the dielectric layer103bmay include SiN. The method of forming the dielectric layers103aand103bmay include suitable deposition process(es) such as chemical vapor deposition (CVD) process, or spin-coating process. Still referring toFIG.1A, a conductive layer104a′ is formed on the dielectric structure103. The conductive layer104a′ may include various conductive materials, such as a metal, a metal alloy, a metal nitride, a metal silicide, a metal oxide, graphene or combinations thereof. For example, the conductive layer104a′ may include aluminum (Al), titanium (Ti), copper (Cu), tungsten (W), platinum (Pt), palladium (Pd), osmium (Os), ruthenium (Ru), tantalum (Ta), or an alloy thereof, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), TaSiN, TiSiN, WSiN, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, indium tin oxide (ITO), iridium oxide (IrO2), rhenium oxide (ReO2), rhenium trioxide (ReO3), or combinations thereof. The formation of the conductive layer104a′ may include a suitable technique such as a physical vapor deposition (PVD) process. Referring toFIG.1B, an insulating layer105a′ is formed on the conductive layer104a′. The insulating layer105a′ may include oxide, nitride, oxynitride, a high-k dielectric material or combinations thereof. The insulating layer105a′ includes, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide-nitride-oxide (ONO) structure, a high-k dielectric material having a dielectric constant greater than that of silicon oxide, or combinations thereof. In some embodiments, the dielectric constant of the high-k dielectric material is greater than 4, greater than 7 or even greater than 10. The high-k dielectric material may include hafnium oxide (HfO2), hafnium silicate (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2Os), titanium oxide (TiO2), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), strontium bismuth tantalite (SrBi2Ta2O9, SBT) or combinations thereof. The insulating layer105a′ may be a single-layer structure or a multi-layer structure. In the embodiments in which the insulating layer105′ is a multi-layer structure, the thicknesses of the respective layers of the multi-layer structure may be the same or different. In some embodiments, the formation of the insulating layer105a′ may include, a CVD process, a spin coating process, an atomic layer deposition (ALD) process or the like. Referring toFIG.1C, the formations of the conductive layer and insulating layer are repeated to form a stack structure ST1including a plurality of conductive layers and a plurality of insulating layers alternatively stacked over the substrate100. For example, the stack structure may include conductive layers104a′,104b′,104c′,104d′ and104e′ and insulating layers105a′,105b′105c′ and105d′ alternatively stacked on the dielectric structure103. The materials and forming methods of the conductive layers104b′,104c′,104d′ and104e′ and insulating layers105b′105c′ and105d′ are selected from the same candidate materials and forming methods of the conductive layer104a′ and the insulating layer105a′, respectively. The materials of the conductive layer104a′-104e′ may be the same or different, and the materials of the insulating layers105a′-105d′ may be the same or different. In some embodiments, the conductive layers104a′-104e′ may also be referred to as electrode material layers, and the insulating layer105a′-105d′ may also be referred to as insulating material layers. As shown inFIG.1C, the insulating layers105a′-105d′ are vertically sandwiched between corresponding adjacent two conductive layers, respectively, such that the conductive layers104a′-104e′ are separated from each other by corresponding insulating layers105a′-105d′. It is noted that, the numbers of the conductive layers104a′-104e′ and the insulating layers105a′-105d′ shown in the figures are merely for illustration, and the disclosure is not limited thereto. Referring toFIG.1D, in some embodiments, a mask layer106ais formed on the topmost layer (e.g., the conductive layer105d′) of the stack structure ST1. The mask layer106amay include a photoresist, or the like. In some embodiments, the mask layer106amay include a patterned photoresist, and may be formed by the following processes. A photoresist layer is formed on the stack structure ST1by a spin coating process, or a suitable deposition process. Thereafter, a photolithography process including exposure and development processes is performed on the photoresist layer, so as to pattern the photoresist layer. For example, the photoresist layer is exposed to a patterned irradiation (e.g., light) through a photomask (not shown). Thereafter, the development process is performed on the photoresist layer to remove the exposed portion of the photoresist layer when the photoresist layer is a positive photoresist, or remove the masked portion of the photoresist layer when the photoresist layer is a negative photoresist. As a result, the pattern of the photomask is transferred into the photoresist layer. Still referring toFIG.1D, in some embodiments, the mask layer106ais disposed on the topmost layer (e.g., conductive layer104e′) of the stack structure ST1, and portions of the topmost layer are exposed by the mask layer106a. For example, the mask layer106ais configured for exposing portions of the conductive layer104e′ in the regions107, and masking the remaining portions of the stack structure ST1. The regions107may also be referred to as openings of the mask layer106a. In some embodiments, the top view of the mask layer106amay be square, rectangular, circular, oval, or the like, or other suitable shaped. The mask layer106amay have a width Wa. Referring toFIG.1DandFIG.1E, in some embodiments, thereafter, etching processes are performed on the stack structure ST1using the mask layer106aas an etching mask, such that the pattern of the mask layer106ais transferred into a portion of the stack structure ST1(e.g., the top conducive layer104e′ and the top insulating layer105d′). Portions of the stack structure ST1exposed by the openings107of the mask layer106aare removed by the etching processes. In some embodiments, the etching process may be or include any acceptable etch process, such as wet etch or dry etch, reactive ion etch (RIE), neutral beam etch (NBE), the like, or combinations thereof. The etching process may be anisotropic. The etching may remove portions of the conductive layer104e′ and the insulating layer105d′ exposed in the regions107and define recesses108in the conductive layer104e′ and the insulating layer105d′. The area of the recesses108corresponds to that of the regions107. In some embodiments, different etchants are used to etch the conductive layer104e′ and the insulating layer105d′. For example, a first sub-etching process is performed to remove portions of the conductive layer104e′ exposed by the openings107of the mask layer106a. During the first sub-etching process, the insulating layer105d′ may serve as an etching stop layer. Thereafter, a second sub-etching process is performed to remove portions of the insulating layer105d′ exposed by the mask layer106aand the conductive layer104e′. During the second sub-etching process, the underlying conductive layer104d′ may serve as an etching stop layer. As a result, the portions of the conductive layer104e′ and the insulating layer105d′ may be selectively removed without removing remaining layers of the stack structure ST1, and recesses108amay be formed to extend through the conductive layer104e′ and the insulating layer105d′, and expose portions of the conductive layer104d′. In some embodiments, after the etching process is performed, the footprint of the conductive layer104e′/insulating layer105d′ is substantially the same as the footprint of the mask layer106a. Referring toFIG.1EandFIG.1F, in some embodiments, a trimming process is then performed on the mask layer106ato reduce the size (e.g., width) of the mask layer106a, and a mask layer106bis formed. The mask layer106bmay also be referend to as a first trimmed mask layer106b. The trimming process may include an etching process, such as a dry etching process. For example, a suitable amount of etching gas is applied to the mask layer106ato remove a portion of the mask layer106a. In some embodiments, no photomask is used for the trimming process of the mask layer106b. In some embodiments, both the width and thickness of the mask layer106may be reduced by the trimming process. For example, the mask layer106bhas a width Wb that is less than the width Wa of the mask layer106a. Accordingly, the size (e.g., width) of the regions that expose the stack structure ST1is increased. For example, the trimming of the mask layer106bcreate a trimmed regions109athat further expose a portion of the top conductive layer104e′ of the stack structure ST1. Herein, the term “trimmed region” refers to the region previously occupied by the portion of mask layer that has been trimmed. In some embodiments, the present trimming process may also be referred to as a first trimming process, and the trimmed region109amay also be referred to as a first trimmed region. Referring toFIG.1F, after the trimming process is performed, portions of the top surface of the conductive layer104e′ are exposed by the trimmed region109aof mask layer106b, and portions of the top surface of the conductive layer104d′ are exposed by the mask layer106band the recess108aof the overlying conductive layer104e′ and insulating layer105d′. Referring toFIG.1FandFIG.1G, etching processes are performed to remove portions of the stack structure ST1exposed by the mask layer106b. In some embodiments, the etching processes are similar to those described inFIG.1DtoFIG.1E. For example, the etching processes may remove portions of the conductive layer104e′ and the insulating layer105d′ exposed by the trimmed region109aof the mask layer106b, and remove portions of the conductive layer104d′ and the insulating layer105c′ exposed by the mask layer106b, the conductive layer104e′ and the insulating layer105d′ (i.e., portions of the conductive layer104d′ and the insulating layer105c′ exposed by the recess108a). The etching of the conductive layer104e′ and the insulating layer105d′ uses the mask layer106bas an etching mask, and etching of the conductive layer104d′ and the insulating layer105c′ uses the mask layer106b, the conductive layer104e′ and the insulating layer105d′ as an etching mask. In some embodiments, the etching process includes a first sub-etching process for removing the exposed conductive layer104e′ and104d′, and a second sub-etching process for partially removing the insulating layers105d′ and105c′. During the first sub-etching process, the insulating layers105d′ and105c′ may serve as etch stop layers and portions of the insulating layers105d′ and105c′ are exposed after the conductive layer104e′ and104d′ are removed. During the second sub-etching process, the exposed portions of the insulating layers105d′ and105c′ are removed, and the conductive layer104d′ and104c′ serve as etch stop layers. During the etching process, since the underlying layers of the stack structure are covered by the insulating layer105c′ and the conductive layer104d′, the underlying layers are not etched. Referring toFIG.1G, through the etching process, the pattern of the mask layer106bis transferred into the conductive layer104e′ and the insulating layer105d′, while the previous pattern of the conductive layer104e′ and the insulating layer105d′ shown inFIG.1Fis transferred into the conductive layer104d′ and the insulating layer105c′. After the etch process is performed, the conductive layer104e′ and the insulating layer105d′ have footprints substantially the same that of the mask layer106b. For example, the widths of the conductive layer104e′ and the insulating layer105d′ may be substantially equal to the width Wb of the mask layer106b. The recess108ain the conductive layer104e′ and the insulating layer105d′ are widened, and may correspond to (e.g., have the same size as) the region107and the trimmed region109a. The recess108aexpose portions of the top surface of the conductive layer104d′. Still referring toFIG.1G, the recess is further extended downward into the stack structure ST1. For example, a recess108bis formed in and extended through the conductive layer104d′ and the insulating layer105c′, and portions of the top surface of the conductive layer104c′ are exposed by the recess108b. The recess108bis in spatial communication with the recess108a, and may correspond to (e.g., have the same size as) the region107. In other words, the recess in the stack structure ST1is widened and deepened. In some embodiments, the conducive layer104d′ and the insulating layer105c′ have sizes (e.g., width) substantially equal to the size (e.g., width Wa) of the mask layer106a(FIG.1E). Thereafter, the trimming process of the mask layer and the etching processes for removing the conductive layers and insulating layers may be repeated to pattern the stack structure ST1. During the etching processes, the etching of the topmost conductive layer and insulating layer uses the trimmed mask layer as the etching mask, and the etching of the conductive layer and insulating layer at lower tier use the trimmed mask layer and overlying conductive layer and insulating layer as the etching mask. For example, referring toFIG.1GtoFIG.1H, a trimming process is then performed on the mask layer106bto remove portions of the mask layer106b, so as to form a mask layer106cand generate a trimmed region109b. The trimming process may also be referred to as a second trimming process, and the trimmed region109bmay also be referred to as a second trimmed region. The method of performing second trimming process is substantially the same as that of the first trimming process, which is not described again here. Referring toFIG.1H, after the second trimming process, the size (e.g., width) of the mask layer106cis decreased. The mask layer106chas a width We less than the width Wb of the mask layer106b(FIG.1G). As such, portions of the top surface of the conductive layer104e′ are further exposed by the trimmed region109b. Referring toFIG.1HandFIG.1I, etching processes are performed to remove portions of the stack structure ST1exposed by the mask layer106c. For example, the etching processes may remove portions of the conductive layer104e′ and the insulating layer105d′ exposed by the trimmed region109bof the mask layer106b, portions of the conductive layer104d′ and the insulating layer105c′ exposed by the mask layer106b, and the overlying conductive layer104e′ and the insulating layer105d′ (i.e., portions of the conductive layer104d′ and the insulating layer105c′ exposed by the recess108aand the trimmed region109a), and portions of the conductive layer104c′ and105b′ exposed by the mask layer106cand the overlying conductive layers and insulating layers (e.g., portions of the conductive layer104c′ and the insulating layer105b′ exposed by the recess108band the region107). The etching of the conductive layer104e′ and the insulating layer105d′ uses the trimmed mask layer106cas the etching mask; the etching of the conductive layer104d′ and the insulating layer105c′ uses the trimmed mask layer106c, the conductive layer104e′ and the insulating layer105d′ as the etching mask, while the etching of the conductive layer104c′ and the insulating layer105b′ uses the trimmed mask layer106c, the conductive layers104e′,104d′ and the insulating layers105d′,105c′ as the etching mask. As such, the pattern of the mask layer106cis transferred into the conductive layer104e′ and the insulating layer105d′; the previous pattern of the conductive layer104e′ and the insulating layer105d′ shown inFIG.1His transferred into the conductive layer104d′ and the insulating layer105c′; and the previous pattern of the conductive layer104d′ and the insulating layer105c′ shown inFIG.1His transferred into the conductive layer104c′ and the insulating layer105b′. The etching process includes a first sub-etching process during which the exposed conductive layer104e′,104d′ and104c′ are removed, with the insulating layers105d′,105c′ and105b′ serving as etch stop layers, and after the first sub-etching process, portions of the insulating layers105d′,105c′ and105b′ previously covered by the removed conductive layer104e′,104d′ and104c′ are exposed. The etching process further includes a second sub-etching process during which the exposed portions of the insulating layers105d′,105c′ and105b′ are removed, with the conductive layers104d′,104c′ and104b′ serving as etch stop layers, and after the second sub-etching process, portions of the conductive layers104d′,104c′,104b′ previously covered by the removed insulating layers are exposed. During the etching process, since the underlying layers of the stack structure are covered by the insulating layer105b′ and the conductive layer104c′, the underlying layers are not etched. Still referring toFIG.1I, after the etching process, the recess of the stack structure ST1is further widened and deepened. For example, the recesses108ain the conductive layer104e′ and the insulating layer105d′ are widened and correspond to the trimmed regions109b,109aand the region107. The recess108bin the conductive layer104′ and the insulating layer105c′ are widened and correspond to the trimmed region109aand the region107. A recess108cis formed in and penetrating through the conductive layer104c′ and the insulating layer105b′. The recess108ccorresponds to the region107, and expose portions of the top surface of the conductive layer104b′. Referring toFIG.1IandFIG.1J, in some embodiments, a trimming process is then performed on the mask layer106cto remove portions of the mask layer106c, so as to form a mask layer106dand generate a trimmed region109c. The trimming process may also be referred to as a third trimming process, and the trimmed region109cmay also be referred to as a third trimmed region. The method of performing third trimming process is substantially the same as that of the foregoing trimming process, which is not described again here. Referring toFIG.1J, after the second trimming process, the size (e.g., width) of the mask layer106dis decreased. The mask layer106dhas a width Wd less than the width We of the mask layer106c(FIG.1I). As such, portions of the top surface of the conductive layer104e′ are further exposed by the trimmed region109c. Referring toFIG.1JandFIG.1K, etching processes are performed to remove portions of the stack structure ST1exposed by the mask layer106b. For example, the etching processes may remove portions of the conductive layer104e′ and the insulating layer105d′ exposed by the trimmed region109cof the mask layer106b, portions of the conductive layer104d′ and the insulating layer105c′ exposed by the mask layer106b, the conductive layer104e′ and the insulating layer105d′ (i.e., portions of the conductive layer104d′ and the insulating layer105c′ exposed by the recess108aand the trimmed region109b), portions of the conductive layer104c′ and the insulating layer105b′ exposed by the mask layer106cand the overlying conductive layers and insulating layers (e.g., portions of the conductive layer104c′ and105b′ exposed by the recess108band the trimmed region109a), and portions of the conductive layer104b′ and the insulating layer105a′ exposed by the recess108cand the region107. Similar to the above-described etching processes, the etching of the top conducive layer104e′ and the insulating layer105d′ uses the mask layer106das the etching mask, while the etching of the conductive layer and insulating layer at lower tier uses the mask layer106dand overlying conductive layer(s) and insulating layer(s) as the etching mask. For example, the etching of the conductive layer104b′ and the insulating layer105a′ uses the mask layer106dand the overlying conductive layers104e,104d′,104c′ and insulating layers105d′,105c′,105b′ as the etching mask. As such, the pattern of the mask layer106dis transferred into the conductive layer104e′ and the insulating layer105d′; the previous pattern of the conductive layer104e′ and the insulating layer105d′ shown inFIG.1Jis transferred into the conductive layer104d′ and the insulating layer105c′; the previous pattern of the conductive layer104d′ and the insulating layer105c′ shown inFIG.1Jis transferred into the conductive layer104c′ and the insulating layer105b′; and the previous pattern of the conductive layer104c′ and the insulating layer105b′ shown inFIG.1Jis transferred into the conductive layer104b′ and the insulating layer105a′. In some embodiments, the etching process includes a first sub-etching process for removing the conductive layers and a second sub-etching process for removing the insulating layers. For example, during the first sub-etching process, portions of the conductive layers104e,104d′,104c′ and104b′ exposed by the mask layer106dare removed, with the insulating layers105d′,105c′,105band105a′ serve as etching stop layers. After the first sub-etching process, portions of the insulating layers105d′,105c′,105band105a′ are exposed. During the second sub-etching process, the exposed portions of the insulating layers105d′,105c′,105band105a′ are removed, with the conductive layers104d′,104c′,104b′ and104a′ serving as etching stop layers. Referring toFIG.1K, the recesses108a,108b,108care widened. The recess108acorresponds to the trimmed regions109a-109cand the region107. The recess108bcorresponds to the trimmed regions109a-109band the region107. The recess108ccorresponds to the trimmed region109aand the region107. A recess108dis further formed in and penetrating through the conductive layer104b′ and the insulating layer105a′, and portions of the top surface of the conductive layer104a′ are exposed. Referring toFIG.1KandFIG.1L, a trimming process is then performed on the mask layer106dto remove portions of the mask layer106d, so as to form a mask layer106eand generate a trimmed region109d. The trimming process may also be referred to as a fourth trimming process, and the trimmed region109dmay also be referred to as a fourth trimmed region. The method of performing the fourth trimming process is substantially the same as that of the foregoing trimming process, which is not described again here. Referring toFIG.1L, after the second trimming process, the size (e.g., width) of the mask layer106eis decreased. The mask layer106ehas a width We less than the width Wd of the mask layer106d(FIG.1K). As such, portions of the top surface of the conductive layer104e′ are further exposed by the trimmed region109d. Referring toFIG.1LandFIG.1M, thereafter, etching processes are performed to remove portions of the stack structure ST1exposed by the mask layer106e. For example, the etching processes may remove portions of the conductive layer104e′ and the insulating layer105d′ exposed by the trimmed region109dof the mask layer106e, portions of the conductive layer104d′ and the insulating layer105c′ exposed by the mask layer106e, the conductive layer104e′ and the insulating layer105d′ (i.e., portions of the conductive layer104d′ and the insulating layer105c′ exposed by the recess108aand the trimmed region109c), portions of the conductive layer104c′ and the insulating layer105b′ exposed by the mask layer106eand the overlying conductive layers and insulating layers (e.g., portions of the conductive layer104c′ and the insulating layer105b′ exposed by the recess108band the trimmed region109b), portions of the conductive layer104b′ and the insulating layer105a′ exposed by the mask layer106eand the overlying conductive layers and insulating layers (e.g., portions of the conductive layer104b′ and the insulating layer105a′ exposed by the recess108cand the trimmed region109a, and portions of the conductive layer104a′ exposed by the mask layer106eand the overlying conductive layers and insulating layers (e.g., portions of the conducive layer104a′ exposed in the region107). The etching of the conductive layer104a′ uses the mask layer106eand the overlying conductive layers104e′,104d′,104c′,104b′ and insulating layers105d′,105c′,105b′,105a′ as the etching mask. Through the etching process, the pattern of the mask layer106eis transferred into the conductive layer104e′ and the insulating layer105d′; the previous pattern of the conductive layer104e′ and the insulating layer105d′ shown inFIG.1Lis transferred into the conductive layer104d′ and the insulating layer105c′; the previous pattern of the conductive layer104d′ and the insulating layer105c′ shown inFIG.1Lis transferred into the conductive layer104c′ and the insulating layer105b′; the previous pattern of the conductive layer104c′ and the insulating layer105b′ shown inFIG.1Lis transferred into the conductive layer104b′ and the insulating layer105a′; and the previous pattern of the conductive layer104b′ and the insulating layer105a′ shown inFIG.1Lis transferred into the conductive layer104a′. In some embodiments, the etching process includes a first sub-etching process for removing the conductive layers and a second sub-etching process for removing the insulating layers. For example, during the first sub-etching process, portions of the conductive layers104e,104d′,104c′,104b′ and104a′ exposed by the mask layer106eare removed, with the insulating layers105d′,105c′,105b,105a′ and the dielectric structure103serving as etching stop layers. During the second sub-etching process, portions of the insulating layers105d′,105c′,105band105a′ are removed, with the conductive layers104d′,104c′,104b′ and104a′ serving as etching stop layers. After the etching process is performed, conductive layers104a-104eand insulating layers105a-105dare formed to constitute a capacitor110. The capacitor110may also be referred to as MIM capacitor, and the conductive layers104a-104eserve as electrodes of the capacitor110, while the insulating layers105a-105dserve as insulators of the capacitor110. In some embodiments, the dielectric structure103includes a material different from the insulating layers105a′-105d′, during the second sub-etching process, the dielectric structure103may also serve as an etching stop layer and may be substantially not removed. However, the disclosure is not limited thereto. In some other embodiments, the dielectric structure103may be slightly removed. Referring toFIG.1M, the recesses108a-108dare widened, and a recess108eis formed in and penetrating through the conductive layer104a. Portions of the top surface of the dielectric structure103are exposed by the recess108e. In some embodiments, the top surface of the dielectric structure103includes a first top surface portion103t1covered by the conductive layer104aand a second top surface portion103t2exposed by the conductive layer104a. The first top surface portion103t1may be substantially coplanar with the second top surface portion103t2, but the disclosure is not limited thereto. In some other embodiments in which the dielectric structure103is partially removed during the etching process of the stack structure ST1, the second top surface portion103t2may be lower than the first top surface portion103t1. Referring toFIG.1MandFIG.1N, the mask layer106eis removed by, for example, a stripping process or an ashing process. In some embodiments, the capacitor110includes the electrodes104a-104eand insulating layers105a-105dalternately stacked over the substrate100. It is noted that, the numbers of the electrodes and insulating layers included in the capacitor110are merely for illustration, and the disclosure is not limited thereto. Referring toFIG.1N, the capacitor110has a stepped structure or a ladder structure, in which the electrodes at a lower level height laterally protrudes from sidewalls of the electrodes at higher level height. In some embodiments, the insulating layer105ais vertically sandwiched between and physically contact the electrodes104aand104b, the sidewalls of the insulating layer105amay be substantially aligned with sidewalls of the overlying electrodes104b, and the sidewalls of the electrode104alaterally extends beyond sidewalls of the insulating layer105aand the electrode104b. The insulating layer105bis vertically sandwiched between and physically contact the electrodes104band104c, the sidewalls of the insulating layer105bmay be substantially aligned with sidewalls of the overlying electrodes104c, and the sidewalls of the electrode104blaterally extend beyond sidewalls of the insulating layer105band the electrode104c. The insulating layer105cis vertically sandwiched between and physically contact the electrodes104cand104d, the sidewalls of the insulating layer105cmay be substantially aligned with sidewalls of the overlying electrodes104d, and the sidewalls of the electrode104claterally extend beyond sidewalls of the insulating layer105cand the electrode104d. The insulating layer105dis vertically sandwiched between and physically contact the electrodes104dand104e, the sidewalls of the insulating layer105dmay be substantially aligned with sidewalls of the overlying electrodes104e, and the sidewalls of the electrode104dlaterally extend beyond sidewalls of the insulating layer105dand the electrode104e. The footprint of the insulating layer105ais substantially equal to the footprint of the electrode104b. The footprint of the insulating layer105bis substantially equal to the footprint of the electrode104c. The footprint of the insulating layer105cis substantially equal to the footprint of the electrode104d. The footprint of the insulating layer105dis substantially equal to the footprint of the electrode104e. The footprints (e.g., areas) of the electrodes of the capacitor101are gradually decreased from bottom to top. For example, the footprint (e.g., area) of the electrode104ais larger than the footprint of the electrode104b, the footprint of the electrode104bis larger than the footprint of the electrode104c, the footprint of the electrode104cis larger than the footprint of the electrode104d, and the footprint of the electrode104dis larger than the footprint of the electrode104e. In some embodiments, the widths of the electrode104eand the insulating layer105dare substantially equal to the width We of the mask layer106e(FIG.1M); the widths of the electrode104dand the insulating layer105care substantially equal to the width Wd of the mask layer106d(FIG.1K); the widths of the electrode104eand the insulating layer105bare substantially equal to the width We of the mask layer106c(FIG.1I); the widths of the electrode104band the insulating layer105aare substantially equal to the width Wb of the mask layer106b(FIG.1G); and the width of the electrode104ais substantially equal to the width Wa of the mask layer106a(FIG.1E). In the embodiments, during the formation of the electrodes and insulating layers of the capacitor110, one mask layer is used for patterning the stack structure to form the capacitor, and the capacitor is formed to have a stepped structure through trimming the mask layer and etching the stack structure. In some embodiments, the trimming process does not include photolithograph and does not use photomask. As such, only one mask layer and only one photomask may be used for forming the capacitor. The one photomask is used at the process shown inFIG.1Dwhere the mask layer106ais initially formed. However, the disclosure is not limited thereto. Referring toFIG.1O, thereafter, a dielectric structure111is formed over the substrate100, and a plurality of contact vias CV1-CV5and conductive lines M1/M2are formed in the dielectric structure111and electrically connected to the capacitor110. The dielectric structure111may be a single layer structure or a multi-layer structure. For example, the dielectric structure111may include a dielectric layer111aand a dielectric layer111bdisposed on the dielectric layer111a. The forming method and materials of the dielectric structure111may be selected from the same candidate forming methods and materials of the dielectric layer103or the dielectric layer101, which are not described again here. In some embodiments, the contact vias CV1-CV5penetrate through the dielectric layer111aand landing on the electrodes104a-104e, respectively. The contact vias CV1-CV5may also be referred to as conductive contacts. The conductive lines M1and M2may penetrate through the dielectric layer111bto electrically connect to the contact vias CV1-CV5. In some embodiments, the top surfaces of the conductive lines M1and M2are substantially coplanar or level with the top surface of the dielectric layer111bof the dielectric structure111. The contact vias and the conductive lines may include conductive materials, such as metal, metal alloy or a combination thereof. For example, the contact vias and the conductive lines may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. In some embodiments, the contact vias and the conductive lines respectively includes a barrier layer and a conductive layer disposed on the barrier layer. The barrier layer may include metal, metal nitride, or a combination thereof, such as titanium, titanium nitride, tantalum nitride, or combinations thereof. The conductive layer may include copper or other suitable metal. In some embodiments, the contact vias CV1-CV5and the conductive lines M1, M2may be formed by single damascene processes, dual-damascene processes, or the like. In some embodiments, the conductive lines M1and M2are separated (e.g., electrically separated) from each other and connected to different contact vias of the contact vias CV1-CV5. For example, the conductive line M1is electrically connected to the conductive vias CV1, CV3, CV5that are landing on the electrodes104a,104c, and104e, while the conductive line M2is electrically connected to the conductive vias CV2, CV4that are landing on the electrodes104band104d. That is to say, the electrodes104a,104c, and104eof the capacitor110are electrically connected to each other through the contact vias CV1, CV3, CV5, and the conductive line M1, and the electrodes104band104dare electrically connected to each other through the contact vias CV2, CV4and the conductive line M2. However, the disclosure is not limited thereto. For example, the connection manner of the electrodes104a-104e, the number of the conductive lines, and the connection manner between the contact vias and the conductive lines are not limited thereto. In some other embodiments, the electrodes of the capacitor110may be divided into three sets of electrodes. The three sets of the electrodes are electrically connected to three separate conductive lines through contact vias landing thereon. In some embodiments, one of the three sets of electrodes includes a single electrode, while the other two sets of the electrodes each include multiple electrodes that are connected to each other. For example, a first conductive line may be electrically connected to the contact via CV5, and further electrically connected to the electrode104ethrough the contact via CV5; a second conductive line may be electrically connected to the contact vias CV1and CV3, such that the electrodes104aand104care electrically connected to each other through the contact vias CV1, CV3and the second conductive line; and a third conductive line may be electrically connected to the contact vias CV2and CV4, such that the electrodes104band104dare electrically connected to each other through the contact vias CV2, CV4and the third conductive line. Alternatively, a first conductive line may be electrically connected to the contact via CV1, and further electrically connected to the electrode104athrough the contact via CV1; a second conductive line may be electrically connected to the contact vias CV2and CV4, such that the electrodes104band104dare electrically connected to each other through the contact vias CV2, CV4and the second conductive line; and a third conductive line may be electrically connected to the contact vias CV3and CV5, such that the electrodes104cand104eare electrically connected to each other through the contact vias CV3, CV5and the third conductive line. In some other embodiments, two of the three sets of electrodes each includes a single electrode, while the other one set of the electrodes includes multiple electrodes that are connected to each other. For example, a first conductive line is electrically connected to the contact via CV2, and further electrically connected to the electrode104bthrough the contact via CV2; a second conductive line is electrically connected to the contact via CV4, and further electrically connected to the electrode104dthrough the contact via CV4; and a third conductive line is electrically connected to the contact vias CV1, CV3, CV5, such that the electrodes104a,104c, and104eare electrically connected to each other through the contact vias CV1, CV3, CV5and the third conductive line. In yet another embodiment, the electrodes of the capacitor may be divided into four sets of electrodes electrically connected to four separated conductive lines. For example, a first conductive line is electrically connected to the electrode104athrough the contact via CV1; a second conductive line is electrically connected to the electrode104cthrough the contact via CV3; a third conductive line is electrically connected to the electrode104ethrough the contact via CV5; and a fourth conductive line is electrically connected to the contact vias CV2, and CV4, such that the electrodes104band104dare electrically connected to each other through the contact vias CV2, CV4and the fourth conductive line. Other suitable connection manner may also be used. Referring toFIG.1P, in some embodiments, dielectric layers112and113are formed over the capacitor101and the dielectric structure111. In some embodiments, the dielectric layers112and113may include different materials. For example, the dielectric layer112may include an inorganic dielectric material, such as silicon nitride. The dielectric layer113may include an organic dielectric material (e.g., a polymer material), such as polyimide. However, the disclosure is not limited thereto. Other suitable dielectric materials may also be used to form the dielectric layers112and113. In some embodiments, the dielectric layer112may also be referred to as a passivation layer, and the dielectric layer113may also be referred to as a protection layer. The dielectric layers112and113may be formed by suitable deposition processes, such as CVD. Referring toFIG.1PandFIG.1Q, in some embodiments, openings115aand115bare formed through the dielectric layers, such as the dielectric layer113,112, the dielectric structure111and the dielectric layer103, so as to expose portions of the conductive lines M1, M2, and portions of the conductive features102of the interconnection structure. The formation of the openings115aand115bmay include the following processes: a patterned mask layer may be formed on the dielectric layer113; the patterned mask layer has openings exposing portions of the top surface of the dielectric layer113; thereafter, etching process(es) may be formed using the patterned mask layer as an etching mask, so as to remove portions of the dielectric layers113,112,111,103exposed by the patterned mask layer, thereby forming openings in the dielectric materials and exposing the conductive material. The etching process may have high etching selectivity ratio of the dielectric material to conducive material and may stop at which the conductive material (e.g., the conductive lines M1, M2, and the conductive features102a,102b) is exposed. In some embodiments, the openings115aand115bexpose portions of the top surfaces and sidewalls of the conductive lines M1and M2, and portions of the top surfaces of the conductive features102, but the disclosure is not limited thereto. In some embodiments, portions of the dielectric layers113/112directly over the conductive lines M1and M2are removed by the etching processes, while portions of the dielectric layers111aand103directly below the conductive lines M1and M2are masked by the conductive lines and are not removed by the etching process. Referring toFIG.1QandFIG.1R, thereafter, conductive plug120aand120bare formed in the openings115aand115band may further protrude from top surface of the dielectric layer113. The conductive plugs120aand120bare electrically connected to the conductive lines M1and M2and the conductive features102of the interconnection structure, respectively. The conductive plugs120a/120bmay include plug portions118embedded in the dielectric layer, and protruding portions119protruding over the top surface of the dielectric layer13. The materials of the conductive plug may include metal, metal alloy, or a combination thereof, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. The plug portion118and the protruding portion119may be formed the same material or different materials. In some embodiments, the plug portion118include metallic materials, while the protruding portion119may include metallic materials and/or solder materials. In some embodiments, at least the plug portion118of the conductive plug120a/120bincludes a barrier layer and a conductive layer disposed on the barrier layer. The barrier layer may line the surfaces of the opening115a/115band surrounds sidewalls and bottom surfaces of the conductive layer. The barrier layer may include metal, metal nitride, or a combination thereof, such as titanium, titanium nitride, tantalum nitride, or combinations thereof. The conductive layer may include copper or other suitable metal. In some embodiments, the conducive plugs120aand120bmay be formed by forming conductive materials over the substrate100to fill in the openings115aand115band cover the top surface of the dielectric layer113. Thereafter, the conductive materials may be patterned by photolithograph and etching processes. However, the disclosure is not limited thereto. Other suitable technique may also be used to form the conducive plugs120aand120b. Referring toFIG.1R, in some embodiments, the plug portion118may include a lower part P1and an upper part P2disposed on the lower part P1. The lower part P1may be embedded in the dielectric structure111and the dielectric structure103, and the top surface of the lower part P1may be substantially coplanar with the top surfaces of the conductive lines M1/M2and the dielectric structure111. The upper part P2may be embedded in the dielectric layers112and113, and overlies the lower part P1and the corresponding conductive line M1/M2. In some embodiments, the lower part P1is laterally aside and in physical and electrical contact with the conductive line M1/M2. The top portion of the lower part P1may border and physical contact a sidewall of the conductive line M1/M2. The upper part P2is disposed on the lower part P1and covers a portion of the top surface of the conductive line M1/M2. The bottom width of the upper part P2is larger than the top width of the lower part P1. Herein, the bottom width of the upper part P2and the top width of the lower part P1are the widths thereof measured at the cross-section taken along the top surfaces of the dielectric structure111and the conductive lines M1and M2(or, the plane including the top surfaces of the dielectric structure111and the conductive lines M1and M2). In other words, the upper part P2has an extending portion that extends beyond a sidewall of the lower part P1and covers a portion of the top surface of the conductive line M1/M2. As shown inFIG.1R, the first sidewalls of the lower part P1and the upper part P2are continuous and aligned, while the second sidewalls of the lower part P1and the upper part P2are non-continuous and not aligned. In some embodiments, the second sidewalls of the lower part P1and the upper part P2may be connected to each other through the bottom surface of the upper part P2that is in contact with the corresponding conductive line M1/M2. As such, a semiconductor structure S1including the capacitor110is formed. In some embodiments, the protruding portions119of the conductive plugs120a/120bmay serve as an external connection of the semiconductor structure S1, and may also be referred to as a conductive connector. In some embodiments, the protruding portion119may have a curved, or a rounding surface, but the disclosure is not limited thereto. In some other embodiments, the cross-sectional shape of the protruding portion119may be square, rectangular, or the like, or any other suitable shape. In some embodiments, the capacitor110may be electrically connected to the interconnect wirings underlying the dielectric structure103through the conductive plugs120a/120band may further electrically coupled to the devices disposed in and/or on the substrate100, but the disclosure is not limited thereto. In some embodiments, the capacitor110is embedded in and surrounded by the dielectric layer111aat back-end-of-line (BEOL) and may be physically separated from other devices (e.g., memory devices). However, the disclosure is not limited thereto. FIG.2AandFIG.2Bare cross-sectional views illustrating semiconductor structures including MIM capacitors according to some other embodiments of the disclosure. FIG.2Aillustrates a semiconductor structure S2similar to the semiconductor S1, except that the dielectric structure103has a less width. In some embodiments, the dielectric structure103may be patterned to have substantially the same footprint as the bottommost electrode104aof the capacitor110. The patterning of the dielectric structure103may be performed during the etching process (e.g., second sub-etching process) shown inFIG.1LtoFIG.1M. Additionally, or alternatively, the patterning of the dielectric structure103may be performed after the etching process shown inFIG.1LtoFIG.1M(e.g., after the stack structure ST1has been patterned as the capacitor101). Referring toFIG.2A, in some embodiments, the sidewalls of the dielectric structure103may be substantially aligned with the sidewalls of the electrode104aof the capacitor110, and may be covered by the dielectric structure108. The dielectric structure108further extends to cover the top surface of the dielectric layer101and/or the top surfaces of the conductive features102. FIG.2Billustrates a semiconductor structure S3similar to the semiconductor structure S1, except that the conductive plugs120a/120bfurther extend through the dielectric layer101and are electrically connected to conductive features80of the interconnection structure over the substrate100. The conductive features80may be embedded in the dielectric layer81underlying the dielectric layer101. In the foregoing embodiments, both opposite sides of the capacitor110have stepped structure or ladder structure, and the capacitor110may have symmetric structure or asymmetric structure. FIG.3AandFIG.3Bare cross-sectional views illustrating MIM capacitors according to some other embodiments of the disclosure. For the sake of brevity, the components over the capacitors are not specifically shown inFIG.3A/3B. Referring toFIG.3A, in some embodiments, a capacitor210includes a plurality of electrodes204a-204eand a plurality of insulating layers205a-205dalternately stacked over the substrate100. The capacitor210has a first side Sd1and a second side Sd2opposite to each other. In some embodiments, one of the first side Sd1and the second side Sd2has a stepped structure, while the other one of the first side Sd1and the second side Sd2does not have a stepped structure. For example, the second side Sd2of the capacitor210has the stepped structure, which is similar to that described in the capacitor110. In some embodiments, the sidewalls of the electrodes204a-204eand the insulating layers205a-205dat the first side Sd1are substantially aligned with each other. Referring toFIG.3B, in some embodiments, a capacitor310includes a plurality of electrodes304a-304eand a plurality of insulating layers305a-305dalternately stacked over the substrate100. The capacitor310is similar to the capacitor210, except that the first side Sd1of the capacitor310has the stepped structure, while the sidewalls of the electrodes304a-304eand the insulating layers305a-305dat the second side Sd2are substantially aligned with each other. FIG.4AtoFIG.4Jare cross-sectional views illustrating a method of forming a semiconductor structure including the capacitor210. It is understood that, the capacitor310may be formed by similar processes descried below. The method of forming the capacitor210is similar to the above-described method for forming the capacitor110, except that one of the opposite sides of the mask layer is trimmed, while the other one of the opposite sides of the mask layer is not trimmed during the trimming process. Referring toFIG.4A, in some embodiments, processes similar to those illustrated inFIG.1AtoFIG.1Eare performed. For example, a stack structure ST2is formed on the dielectric structure103over the substrate100. The stack structure ST2includes a plurality of conductive layers204a′-204e′ and a plurality of insulating layers205a′-205d′ alternately stacked over the substrate100. A mask layer206ais formed over the stack structure ST2. The mask layer206ahas openings207aand207bat opposite sides of the mask layer206a. Etching process(es) are performed to remove portions of the conductive layer204e′ and the insulating layer205d′ exposed by the mask layer206a. Referring toFIG.4AandFIG.4B, in some embodiments, a trimming process is performed to remove a portion of the mask layer206a, so as to form a mask layer206bhaving a size (e.g., width) smaller than that of the mask layer206a, and a portion of the top surface of the conductive layer204e′ is further exposed by the mask layer206a. In some embodiments, the mask layer206ahas a first side Sd1′ and a second side Sd2′ opposite to each other. In some embodiments, one of the opposite sides Sd1′ and Sd2′ is trimmed, while the other one of the opposite sides Sd1′ and Sd2′ is substantially not trimmed. For example, the trimming process may partially remove the mask layer206afrom the second side Sd2′, and the first side Sd1′ of the mask layer206ais substantially not removed by the trimming process. As such, a trimmed region209ais formed adjacent to the opening207a, while no trimmed region is formed adjacent to the opening207b. In some embodiments, before the trimming process is performed, the structure shown inFIG.4A(e.g., a wafer in the manufacturing process) may be tilted, for example, toward the first side Sd1′, such that the second side Sd2′ is over the first side Sd1′. Thereafter, with the structure being tilted, etching gas or etchant is applied to the structure, so as to remove a portion of the mask layer206afrom the second side Sd2′. The tilt of the structure may protect the first side Sd1′ from being removed by the etching gas or etchant. As such, the trimming process may remove a portion of the mask layer206afrom the second side Sd2′, while the first side Sd1′ is substantially not removed. The above-described method for forming such a trimming process is merely for illustration, and the disclosure is not limited thereto. Other suitable method may also be used. Referring toFIG.4BandFIG.4C, etching processes are performed to removed portions of the stack structure ST2(e.g., portion of the conductive layers204e′,204d′ and insulating layers205d′ and105c′) exposed by the mask layer206b, and portions of the conductive layer204c′ are exposed. Thereafter, the trimming process of the mask layer and the etching process of the conductive layers and insulating layers are repeated, so as to form the capacitor. In the embodiments, the structure are tilted while performing the trimming process, such that the second side Sd2′ is trimmed, while the other side Sd1′ is substantially not trimmed. For example, as shown inFIG.4D, the mask layer206bis trimmed to form a mask layer206c, and a trimmed region209bis formed adjacent to the trimmed region209a. Referring toFIG.4DandFIG.4E, portions of the conductive layers204c′-204e′ and the insulating layers205b′-205d′ exposed by the mask layer206care removed by etching processes using the mask layer206cas an etching mask, and portions of the conductive layer204b′ are exposed. Referring toFIG.4F, the mask layer206cis trimmed to form a mask layer206d, and a trimmed region209cis formed adjacent to the trimmed region209b. Referring toFIG.4FandFIG.4G, portions of the conductive layers204b′-204e′ and the insulating layers205a′-205d′ exposed by the mask layer206dare removed by etching processes using the mask layer206das an etching mask, and portions of the conductive layer204a′ are exposed. Referring toFIG.4H, the mask layer206eis trimmed to form a mask layer206e, and a trimmed region209dis formed adjacent to the trimmed region209c. Referring toFIG.4HandFIG.4I, portions of the conductive layers204a′-204e′ and the insulating layers205a′-205d′ exposed by the mask layer206eare removed by etching processes using the mask layer206eas an etching mask, and conductive layers204a-204eand insulating layers205a-205dare formed. Referring toFIG.4IandFIG.4J, the mask layer206eis removed, and the capacitor210is formed. The capacitor210includes the conductive layers204a-204eand the insulating layers205a-205dalternately stacked on the substrate100. The conductive layer204a-204eserve as electrodes of the capacitor210. In the embodiments of the disclosure, the electrode material layers and insulating layers for capacitor are initially stacked over the substrate at back-end-of-line (BEOL), and one mask layer is formed over the stack structure. Thereafter, the stack structure is patterned using the one mask layer to form the capacitor, and the capacitor is formed to have a stepped structure. The number of the mask used for forming the capacitor is independent of and less than the number of the layers includes in the capacitor. Therefore, the number of the mask and photomask used for the process is decreased and minimum, the forming process is easier and the cost is saved, and it may have non-breaking vacuum during the fabrication. The throughput of product may be increased. On the other hand, contacts are formed to land on the stepped structure of the capacitor, which may achieve lower contact resistance. In accordance with some embodiments of the disclosure, a method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer. In accordance with some embodiments of the disclosure, a method of forming a semiconductor structure including a MIM capacitor include: forming a stack structure including a bottom electrode layer, a lower insulating layer, a middle electrode layer, an upper insulating layer and a top electrode layer over a dielectric structure; forming a mask layer over the top electrode layer; performing a first etching process to remove portions of the top electrode layer and the upper insulating layer exposed by the mask layer; performing a first trimming process on the mask layer to form a first trimmed mask layer having a width less than that of the mask layer, such that a portion of the top electrode layer is further exposed by the first trimmed mask layer; performing a second etching process to remove portions of the top electrode layer, the upper insulating layer, the middle electrode layer and the lower insulating layer exposed by the first trimmed mask layer; and performing a second trimming process on the first trimmed mask layer to form a second trimmed mask layer; and performing a third etching process to remove portions of the top electrode layer, the upper insulating layer, the middle electrode layer, the lower insulating layer, and the bottom electrode layer exposed by the second trimmed mask layer. In accordance with some embodiments of the disclosure, a semiconductor structure includes a dielectric structure and a MIM capacitor disposed over the dielectric structure. The MIM capacitor includes: a bottom electrode; a lower insulator, disposed over the bottom electrode; a middle electrode, disposed over the lower insulator, wherein the bottom electrode laterally extends beyond first sidewalls of the middle electrode and the lower insulator; an upper insulator, disposed over the middle electrode; and a top electrode, disposed over the upper insulator, wherein the first sidewall of the middle electrode laterally extends beyond first sidewalls of the top electrode and the upper insulator. A contact via lands on one of the bottom electrode, the middle electrode and the top electrode. A conductive line is disposed on and electrically connected to the contact via. A conductive plug is disposed laterally aside the contact via, and electrically connected to the conductive line. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure. | 65,425 |
11862666 | DETAILED DESCRIPTION To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure. Please refer toFIG.1.FIG.1is a schematic drawing illustrating a capacitor structure101according to a first embodiment of the present invention. As shown inFIG.1, the capacitor structure101includes a first electrode20, a second electrode60, and a capacitor dielectric stacked layer DS. The capacitor dielectric stacked layer DS is disposed between the first electrode20and the second electrode60, and the capacitor dielectric stacked layer DS includes a first dielectric layer (such as a dielectric layer30illustrated inFIG.1). The dielectric layer30includes a first zirconium oxide layer (such as a zirconium oxide layer34illustrated inFIG.1) and a first zirconium silicon oxide layer (such as a zirconium silicon oxide layer32illustrated inFIG.1). The zirconium silicon oxide layer32may be used to change the energy band distribution in the dielectric layer30and the capacitor dielectric stacked layer DS and/or reduce the leakage current path (such as a leakage current path generated by crystalline grain boundary of crystalline zirconium oxide, but not limited thereto), and the leakage current of the capacitor structure101may be reduced accordingly for enhancing the operation performance of the capacitor structure101. In some embodiments, the capacitor structure101may be disposed on a substrate10, the first electrode20may be disposed between the capacitor dielectric stacked layer DS and the substrate10in a vertical direction Z, and the capacitor dielectric stacked layer DS may be disposed between the first electrode20and the second electrode60in the vertical direction Z. Therefore, the first electrode20may be regarded as a bottom electrode and the second electrode60may be regarded as a top electrode, but not limited thereto. In some embodiments, the substrate10may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include a silicon substrate, a silicon germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, and the non-semiconductor substrate may include a glass substrate, a plastic substrate, or a ceramic substrate, but not limited thereto. Additionally, other active components (such as a transistor structure, not illustrated) and/or other passive components may be disposed in the substrate according to some design considerations, and the capacitor structure101may be electrically connected with the active component and/or the passive component. For example, the capacitor structure101may be electrically connected with a transistor structure for forming a memory unit, but not limited thereto. In some embodiments, the first electrode20and the second electrode60may respectively include a single layer or multiple layers of electrically conductive materials, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), platinum (Pt), or other suitable metallic conductive materials or non-metallic conductive materials. Additionally, in some embodiments, the zirconium oxide layer34may be pure zirconium oxide (such as consisting of zirconium oxide only) or be nearly pure zirconium oxide (such as including zirconium oxide and some unintentionally doped impurities), and an atomic percentage (at. %) of zirconium in the zirconium oxide layer34may be higher than an atomic percentage of zirconium in the zirconium silicon oxide layer32accordingly. In addition, the zirconium silicon oxide layer32may be used to reduce the leakage current, but the dielectric constant of the zirconium silicon oxide layer32is lower than that of the zirconium oxide layer34. Therefore, a thickness T34of the zirconium oxide layer34in the vertical direction Z may be greater than a thickness T32of the zirconium silicon oxide layer32in the vertical direction Z for reducing the influence on the permittivity and/or the capacitance density of the capacitor dielectric stacked layer DS, but not limited thereto. In some embodiments, the zirconium silicon oxide layer32may be disposed between the zirconium oxide layer34and the first electrode20in the vertical direction Z, but not limited thereto. In other words, in some embodiments, the zirconium oxide layer34may be disposed between the zirconium silicon oxide layer32and the first electrode20in the vertical direction Z. In some embodiments, the capacitor dielectric stacked layer DS may further include an aluminum oxide layer40, and the dielectric layer30may be disposed between the aluminum oxide layer40and the first electrode20, but not limited thereto. In other words, in some embodiments, the dielectric layer30including the zirconium oxide layer34and the zirconium silicon oxide layer32may be disposed between the aluminum oxide layer40and the second electrode60in the vertical direction Z according to some design considerations. In some embodiments, the aluminum oxide layer40may have relatively higher crystallization temperature and/or greater energy barrier for reducing the leakage current generated by the zirconium oxide layer, but the dielectric constant of the aluminum oxide layer40is relatively lower (such as being lower than that of the zirconium oxide layer34and being lower than that of the zirconium silicon oxide layer32). Therefore, the thickness T34of the zirconium oxide layer34may be greater than a thickness T40of the aluminum oxide layer40in the vertical direction Z for reducing the influence of the aluminum oxide layer40on the permittivity and/or the capacitance density of the capacitor dielectric stacked layer DS. Additionally, in some embodiments, the zirconium oxide layer34in the dielectric layer30may be disposed between the zirconium silicon oxide layer32and the aluminum oxide layer40in the vertical direction Z for reducing the influence of silicon in the zirconium silicon oxide layer32on the aluminum oxide layer40, but not limited thereto. In some embodiments, the capacitor dielectric stacked layer DS may further include a second dielectric layer (such as a dielectric layer50illustrated inFIG.1) disposed between the aluminum oxide layer40and the second electrode60. The dielectric layer50may include a zirconium oxide layer54, and the material composition of the zirconium oxide layer54may be identical to the material composition of the zirconium oxide layer34, but not limited thereto. In some embodiments, the zirconium oxide layer54may be pure zirconium oxide (such as consisting of zirconium oxide only) or be nearly pure zirconium oxide (such as including zirconium oxide and some unintentionally doped impurities). Therefore, an atomic percentage of zirconium in the zirconium oxide layer54may be higher than the atomic percentage of zirconium in the zirconium silicon oxide layer32, and a thickness T54of the zirconium oxide layer54in the vertical direction Z may be greater than the thickness T32of the zirconium silicon oxide layer32, but not limited thereto. Please refer toFIGS.1-4.FIG.2is a flow chart of an atomic layer deposition process for forming a zirconium silicon oxide layer according to an embodiment of the present invention,FIG.3is a flow chart of an atomic layer deposition process for forming a zirconium silicon oxide layer according to another embodiment of the present invention, andFIG.4is a flow chart of an atomic layer deposition process for forming a zirconium oxide layer according to an embodiment of the present invention. As shown inFIG.1, the manufacturing method of the capacitor structure101may include the following steps. The capacitor dielectric stacked layer DS is formed on the first electrode20, and the capacitor dielectric stacked layer DS includes a first dielectric layer (such as the dielectric layer30described above). The dielectric layer30includes a first zirconium oxide layer (such as the zirconium oxide layer34described above) and a first zirconium silicon oxide layer (such as the zirconium silicon oxide layer32described above). Subsequently, the second electrode60is formed on the capacitor dielectric stacked layer DS, and the capacitor dielectric stacked layer DS is located between the first electrode20and the second electrode60. In some embodiments, the manufacturing method of the capacitor structure101may include but is not limited to the following steps. The first electrode20may be formed on the substrate10, and the first electrode20and the second electrode60may be formed by sputtering processes, atomic layer deposition (ALD) processes, or other suitable film forming approaches. In some embodiments, the first electrode20, the second electrode60, and the material layers in the capacitor dielectric stacked layer DS may be respectively formed on the substrate10by corresponding film forming approaches and one or a plurality of patterning processes (such as photolithography processes). In some embodiments, the zirconium silicon oxide layer32and the zirconium oxide layer34in the dielectric layer30may be formed by corresponding atomic layer deposition processes, respectively. For example, the zirconium silicon oxide layer32may be formed by an atomic layer deposition process91shown inFIG.2or an atomic layer deposition process91′ shown inFIG.3, and the zirconium oxide layer34may be formed by an atomic layer deposition process92shown inFIG.4, but not limited thereto. As shown inFIG.1andFIG.2, in some embodiments, the atomic layer deposition process91may include the following steps. Firstly, a step S11may be performed for introducing a zirconium precursor. In some embodiments, the zirconium precursor may be introduced into a process chamber for the atomic layer deposition process91, and the substrate10with the first electrode20formed thereon may be placed in the process chamber before the step S11. The zirconium precursor described above may include zirconium halide, such as zirconium chloride, or other suitable zirconium precursor materials. Subsequently, a step S12may be performed after the step S11for carrying out a purge step configured to remove the zirconium precursor and/or other possible reaction byproducts. The zirconium precursor described above may be introduced into the process chamber and kept in the process chamber for a predetermined period (the step S11may be regarded as a pulse step, for example) so as to make zirconium in the zirconium precursor be adsorbed on a surface of a target (such as the first electrode20) and form a zirconium atomic monolayer accordingly. The purge step described above may be used to remove the redundant zirconium precursor and/or possible reaction byproducts in the process chamber from the process chamber. A step S13may be performed after the step S12for introducing an oxidizing agent. The oxidizing agent may be introduced into the process chamber and kept in the process chamber for a predetermined period so as to bond oxygen atoms to zirconium atoms and form zirconium oxide accordingly. A step S14may be performed after the step S13for carrying out a purge configured to remove the oxidizing agent. The purge in the step S14may be used to remove the redundant oxidizing agent and/or possible reaction byproducts in the process chamber from the process chamber. A step S15may be performed after the step S14for introducing a silicon precursor. The silicon precursor may be introduced into the process chamber and kept in the process chamber for a predetermined period so as to make silicon in the silicon precursor be adsorbed on a surface of a target (such as the zirconium oxide formed in the step S13described above) and form a silicon atomic monolayer accordingly. In some embodiments, the silicon precursor may include silicon halide, such as silicon fluoride, silicon chloride, or other suitable silicon precursor materials. A step S16may be performed after the step S15for carrying out a purge configured to remove the silicon precursor. The purge in the step S16may be used to remove the redundant silicon precursor and/or possible reaction byproducts in the process chamber from the process chamber. A step S17may be performed after the step S16for introducing an oxidizing agent. The oxidizing agent may be introduced into the process chamber and kept in the process chamber for a predetermined period so as to bond oxygen atoms to silicon atoms. A step S18may be performed after the step S17for carrying out a purge configured to remove the oxidizing agent and/or possible reaction byproducts in the process chamber from the process chamber. The purge using inert gases and/or other suitable approaches may be applied in the step S12, the step S14, the step S16, and the step S18described above for achieving the purpose of removing the precursors, the oxidizing agents, and/or the reaction byproducts. In addition, the oxidizing agents used in the step S13and the step S17described above may include oxygen, ozone, water vapor, hydrogen peroxide, nitrogen oxide, or other suitable oxidizing agent materials. The material composition of the oxidizing agent used in the step S13may be identical to or different from the material composition of the oxidizing agent used in the step S17according to some design considerations. The step S11to the step S18described above may be regarded as a cycle in the atomic layer deposition process91, and the thickness of the zirconium silicon oxide layer (such as the zirconium silicon oxide layer32) formed by the atomic layer deposition process91may be increased by repeating the cycle (i.e. repeating the step S11to the step S18). In other words, the zirconium silicon oxide layer32may include zirconium atomic monolayers, oxygen atomic monolayers, and silicon atomic monolayers alternately stacked and disposed in the vertical direction Z. In addition, the number of the cycles required to be performed may be calculated with the thickness design value of the zirconium silicon oxide layer32. If the expected thickness calculated with the number of the cycles performed after the step S18does not reached the predetermined thickness, the cycle described above has to be performed again, and if the expected thickness calculated with the number of cycles performed after the step S18reaches the predetermined thickness, then a step S19can be carried out for performing subsequent manufacturing processes. In some embodiments, the steps in the cycle described above may be adjusted according to the silicon atomic percentage designed in the zirconium silicon oxide layer to be formed. For example, the steps S15to the step S18in some of the cycles repeated may be removed for lowering the atomic percentage of silicon in the zirconium silicon oxide layer, but not limited thereto. In other words, the atomic percentage of zirconium in the zirconium silicon oxide layer may be equal to or different from the atomic percentage of silicon in the zirconium silicon oxide layer. In some embodiments, the cycle (i.e. the step S11to the step S18) described above may be repeated at least three times, and an end step may be the step S14for forming the zirconium silicon oxide layer including zirconium oxide monolayer structures at two opposite ends of the zirconium silicon oxide layer in the vertical direction Z, respectively, but not limited thereto. As shown inFIG.1andFIG.3, in some embodiments, the atomic layer deposition process91′ may include the following steps. Firstly, the step S15may be performed for introducing the silicon precursor. The step S16may be performed after the step S15for carrying out the purge configured to remove the silicon precursor and/or possible reaction byproducts. The step S17may be performed after the step S16for introducing the oxidizing agent so as to bond oxygen atoms to silicon atoms. The step S18may be performed after the step S17for carrying out the purge configured to remove the oxidizing agent and/or possible reaction byproducts. The step S11may be performed after the step S18for introducing the zirconium precursor. The step S12may be performed after the step S11for carrying out the purge configured to remove the zirconium precursor and/or other possible reaction byproducts. The step S13may be performed after the step S12for introducing the oxidizing agent so as to bond oxygen atoms to zirconium atoms and form zirconium oxide accordingly. The step S14may be performed after the step S13for carrying out the purge configured to remove the oxidizing agent and/or possible reaction byproducts. The step S15, the step S16, the step S17, the step S18, the step S11, the step S12, the step S13, and the step S14described above may be regarded as a cycle in the atomic layer deposition process91′, and the thickness of the zirconium silicon oxide layer (such as the zirconium silicon oxide layer32) formed by the atomic layer deposition process91′ may be increased by repeating the cycle. If the expected thickness calculated with the number of the cycles performed after the step S14does not reached the predetermined thickness, the cycle described above has to be performed again, and if the expected thickness calculated with the number of cycles performed after the step S14reaches the predetermined thickness, then the step S19can be carried out for performing subsequent manufacturing processes. In some embodiments, the cycle (i.e. the step S15, the step S16, the step S17, the step S18, the step S11, the step S12, the step S13, and the step S14) described above may be repeated at least three times, and an end step may be the step S18for forming the zirconium silicon oxide layer including silicon oxide monolayer structures at two opposite ends of the zirconium silicon oxide layer in the vertical direction Z, respectively, but not limited thereto. In other words, the difference between the atomic layer deposition process91′ and the atomic layer deposition process91shown inFIG.2is that the step S11to the step S14are performed firstly in the atomic layer deposition process91for forming the zirconium oxide first, and the step S15to the step S18are performed firstly in the atomic layer deposition process91′for forming the silicon oxide first. As shown inFIG.1andFIG.4, in some embodiments, the atomic layer deposition process92may include the following steps. Firstly, a step S21may be performed for introducing a zirconium precursor. The zirconium precursor may be introduced into a process chamber for the atomic layer deposition process92. In some embodiments, different atomic layer deposition processes may be carried out sequentially in the same process chamber. For example, the atomic layer deposition process92may be carried out directly in the same process chamber after the atomic layer deposition process91shown inFIG.2or the atomic layer deposition process91′shown inFIG.3for avoiding the influence of the external environment, but not limited thereto. In some embodiments, the different atomic layer deposition processes described above may also be performed respectively in different process chambers within the same process apparatus according to some design considerations. Subsequently, a step S22may be performed after the step S21for carrying out a purge step configured to remove the zirconium precursor and/or other possible reaction byproducts. In the step S21, zirconium in the zirconium precursor may be adsorbed on a surface of a target (such as the zirconium silicon oxide layer32) and form a zirconium atomic monolayer accordingly. The purge step described above may be used to remove the redundant zirconium precursor and/or possible reaction byproducts in the process chamber from the process chamber. A step S23may be performed after the step S22for introducing an oxidizing agent. The oxidizing agent may be introduced into the process chamber and kept in the process chamber for a predetermined period so as to bond oxygen atoms to zirconium atoms and form zirconium oxide accordingly. A step S24may be performed after the step S23for carrying out a purge configured to remove the redundant oxidizing agent and/or possible reaction byproducts in the process chamber from the process chamber. In some embodiments, the process conditions of the step S21to the step S24may be identical to or similar to the process conditions of the step S11to the step S14shown inFIG.2described above. In some embodiments, the step S21to the step S24described above may be regarded as a cycle in the atomic layer deposition process92, and the thickness of the zirconium oxide layer (such as the zirconium oxide layer34) formed by the atomic layer deposition process92may be increased by repeating the cycle (i.e. repeating the step S21to the step S24). In other words, the zirconium oxide layer34may include zirconium atomic monolayers and oxygen atomic monolayers alternately stacked and disposed in the vertical direction Z. In addition, the number of the cycles required to be performed may be calculated with the thickness design value of the zirconium oxide layer34. If the expected thickness calculated with the number of the cycles performed after the step S24does not reached the predetermined thickness, the cycle described above has to be performed again, and if the expected thickness calculated with the number of cycles performed after the step S24reaches the predetermined thickness, then a step S25can be carried out for performing subsequent manufacturing processes. As shown inFIG.1, in some embodiments, the capacitor dielectric stacked layer DS may further include the aluminum oxide layer40and the dielectric layer50, and the dielectric layer50may include the zirconium oxide layer54. The aluminum oxide layer40and the zirconium oxide layer54may be formed by corresponding atomic layer deposition processes, respectively. For example, the aluminum oxide layer40may be formed on the dielectric layer30by an atomic layer deposition process, and the zirconium oxide layer54may be formed on the aluminum oxide layer40by the atomic layer deposition process92shown inFIG.4, but not limited thereto. The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described. Please refer toFIG.5.FIG.5is a schematic drawing illustrating a capacitor structure102according to a second embodiment of the present invention. As shown inFIG.5, in the capacitor structure102, the dielectric layer30may further include a third zirconium oxide layer (such as a zirconium oxide layer36illustrated inFIG.5) and a silicon oxide layer38. The zirconium silicon oxide layer32may be disposed between the zirconium oxide layer34and the zirconium oxide layer36in the vertical direction Z, and the silicon oxide layer38may be disposed between the zirconium oxide layer34and the zirconium oxide layer36in the vertical direction Z also. In some embodiments, the silicon oxide layer38may be used to reduce the leakage current generated by the crystallization of the zirconium oxide layer34, but the dielectric constant of the silicon oxide layer38is relatively lower (such as being lower than the dielectric constant of the zirconium oxide layer34, the dielectric constant of the zirconium oxide layer36, and the dielectric constant of the zirconium silicon oxide layer32, respectively). Therefore, a thickness T38of the silicon oxide layer38in the vertical direction Z may be less than a thickness T36of the zirconium oxide layer36in the vertical direction Z and/or the thickness T34of the zirconium oxide layer34in the vertical direction Z for reducing the influence of the silicon oxide layer38on the permittivity and/or the capacitance density of the capacitor dielectric stacked layer DS. Additionally, in some embodiments, the zirconium oxide layer36and the silicon oxide layer38may be formed by corresponding atomic layer deposition processes, respectively. For example, the zirconium oxide layer36may be formed by the atomic layer deposition process92shown inFIG.2, and the silicon oxide layer38may be formed by an atomic layer deposition process93shown inFIG.6, but not limited thereto. As shown inFIG.5andFIG.6, in some embodiments, the atomic layer deposition process93may include the following steps. Firstly, a step S31may be performed for introducing a silicon precursor. The silicon precursor may be introduced into a process chamber for the atomic layer deposition process93. In some embodiments, different atomic layer deposition processes may be carried out sequentially in the same process chamber. For example, the atomic layer deposition process93may be carried out directly in the same process chamber after the atomic layer deposition process of forming the zirconium oxide layer36, but not limited thereto. Subsequently, a step S32may be performed after the step S31for carrying out a purge step configured to remove the silicon precursor and/or possible reaction byproducts. In the step S31, silicon in the silicon precursor may be adsorbed on a surface of a target (such as the zirconium oxide layer36) and form a silicon atomic monolayer accordingly. The purge step described above may be used to remove redundant silicon precursor and/or possible reaction byproducts in the process chamber from the process chamber. A step S33may be performed after the step S32for introducing an oxidizing agent. The oxidizing agent may be introduced into the process chamber and kept in the process chamber for a predetermined period so as to bond oxygen atoms to silicon atoms and form silicon oxide. A step S34may be performed after the step S33for carrying out a purge configured to remove redundant oxidizing agent and/or possible reaction byproducts in the process chamber from the process chamber. In some embodiments, the process conditions of the step S31to the step S34may be identical to or similar to the process conditions of the step S15to the step S18shown inFIG.2described above. In some embodiments, the step S31to the step S34described above may be regarded as a cycle in the atomic layer deposition process93, and the thickness of the silicon oxide layer (such as the silicon oxide layer38) formed by the atomic layer deposition process93may be increased by repeating the cycle (i.e. repeating the step S31to the step S34). In other words, the silicon oxide layer38may include silicon atomic monolayers and oxygen atomic monolayers alternately stacked and disposed in the vertical direction Z. In addition, the number of the cycles required to be performed may be calculated with the design thickness of the silicon oxide layer38. If the expected thickness calculated with the number of the cycles performed after the step S34does not reached the predetermined thickness, the cycle described above has to be performed again, and if the expected thickness calculated with the number of cycles performed after the step S34reaches the predetermined thickness, then a step S35can be carried out for performing subsequent manufacturing processes (such as a manufacturing process for forming the zirconium silicon oxide layer32). Please refer toFIG.7.FIG.7is a schematic drawing illustrating a capacitor structure103according to a third embodiment of the present invention. As shown inFIG.7, in the capacitor structure103, the dielectric layer50may further include a second zirconium silicon oxide layer (such as a zirconium silicon oxide layer52), and the zirconium silicon oxide layer52and the zirconium oxide layer54in the dielectric layer50may be stacked and disposed in the vertical direction Z. In some embodiments, the zirconium silicon oxide layer52may be disposed between the second electrode60and the zirconium oxide layer54, and the zirconium silicon oxide layer32may be disposed between the first electrode20and the zirconium oxide layer34. Therefore, the zirconium silicon oxide layer52and the zirconium silicon oxide layer32may be located at two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z, respectively, but not limited thereto. In some embodiments, the zirconium oxide layer54may be pure zirconium oxide (such as consisting of zirconium oxide only) or be nearly pure zirconium oxide. Therefore, an atomic percentage of zirconium in the zirconium oxide layer54may be higher than an atomic percentage of zirconium in the zirconium silicon oxide layer52, and a thickness T52of the zirconium silicon oxide layer52in the vertical direction Z may be less than the thickness T54of the zirconium oxide layer54in the vertical direction Z, but not limited thereto. In some embodiments, the zirconium oxide layer54and the zirconium silicon oxide layer52may be formed by corresponding atomic layer deposition processes, respectively. For example, the zirconium oxide layer54may be formed on the aluminum oxide layer40by the atomic layer deposition process92shown inFIG.4, and the zirconium silicon oxide layer52may be formed on the zirconium oxide layer54by the atomic layer deposition process91shown inFIG.2the an atomic layer deposition process91′ shown inFIG.3, but not limited thereto. Please refer toFIG.8.FIG.8is a schematic drawing illustrating a capacitor structure104according to a fourth embodiment of the present invention. As shown inFIG.8, in the capacitor structure104, the dielectric layer30may include the zirconium oxide layer34only, and the zirconium silicon oxide layer52in the capacitor dielectric stacked layer DS may be located at a side adjacent to the second electrode60. Please refer toFIG.9.FIG.9is a schematic drawing illustrating a capacitor structure105according to a fifth embodiment of the present invention. As shown inFIG.9, in the capacitor structure105, the zirconium silicon oxide layer32may be disposed between the zirconium oxide layer34and the aluminum oxide layer40, and the zirconium silicon oxide layer52may be disposed between the zirconium oxide layer54and the aluminum oxide layer40. Therefore, the zirconium silicon oxide layer52and the zirconium silicon oxide layer32may be located at two opposite ends of the aluminum oxide layer40in the vertical direction Z, respectively, and directly connected with the aluminum oxide layer40, but not limited thereto. In other words, the position of each zirconium silicon oxide layers in the capacitor dielectric stacked layer DS may be adjusted according to some design considerations (such as the approach for applying voltages respectively to the first electrode20and the second electrode60during operation and/or the mechanism of transmitting electrons in the capacitor structure). Please refer toFIG.10andFIG.11.FIG.10is a schematic drawing illustrating a capacitor structure106according to a sixth embodiment of the present invention, andFIG.11is a flow chart of a process for forming a capacitor dielectric stacked layer according to an embodiment of the present invention. As shown inFIG.10, in the capacitor structure106, the dielectric layer30may include a plurality of the zirconium oxide layers34and a plurality of the zirconium silicon oxide layers32alternately stacked and disposed, and there may be not any aluminum oxide layer, which is described in the embodiments above, disposed in the capacitor dielectric stacked layer DS. Additionally, in some embodiments, each of the zirconium oxide layers34and each of the zirconium silicon oxide layers32in the dielectric layer30may be formed by corresponding atomic layer deposition processes, respectively. For example, as shown inFIG.10andFIG.11, the process for forming the capacitor dielectric stacked layer DS in this embodiment may include the following steps. A step S41may be carried out for performing a second atomic layer deposition process (such as the atomic layer deposition process92shown inFIG.4described above), so as to form the zirconium oxide layer34on the first electrode20. Subsequently, a step S42may be carried out for performing a first atomic layer deposition process (such as the atomic layer deposition process91shown inFIG.2described above or the atomic layer deposition process91′ shown inFIG.3described above), so as to form the zirconium silicon oxide layer32on the zirconium oxide layer34. In some embodiments, the step S41and the step S42described above may be regarded as a cycle in the atomic layer deposition process for forming the capacitor dielectric stacked layer DS including the zirconium oxide layers34and the zirconium silicon oxide layers32alternately stacked and disposed, and the number of the zirconium oxide layers34and the zirconium silicon oxide layers32may be increased by repeating this cycle. Therefore, the number of the cycles required to be performed may be calculated with the designed number of the zirconium oxide layers34and the zirconium silicon oxide layers32in the capacitor dielectric stacked layer DS. If the expected number of the layers calculated with the number of the cycles performed after the step S42does not reached the predetermined number of the layers, the cycle described above has to be performed again, and if the expected number of the layers calculated with the number of cycles performed after the step S42reaches the predetermined number of the layers, then a step S43can be carried out for performing subsequent manufacturing processes (such as a manufacturing process for forming the second electrode20). In other words, the process of forming the dielectric layer30in this embodiment may include different atomic layer deposition processes (such as the atomic layer deposition process92shown inFIG.4and the atomic layer deposition process91shown inFIG.2or the atomic layer deposition process91′ shown inFIG.3) performed alternately and repeatedly for forming the dielectric layer30including the zirconium oxide layers34and the zirconium silicon oxide layers32alternately stacked and disposed. Please refer toFIG.12andFIG.13.FIG.12is a schematic drawing illustrating a capacitor structure107according to a seventh embodiment of the present invention, andFIG.13is a flow chart of a process for forming a capacitor dielectric stacked layer according to another embodiment of the present invention. As shown inFIG.12, in the capacitor structure107, the dielectric layer30may include the zirconium oxide layers34and the zirconium silicon oxide layers32alternately stacked and disposed, and the material layers located at two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z may be the same. For example, the two material layers located at two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z, respectively, may be the zirconium oxide layers34for reducing the ratio of the zirconium silicon oxide layers32in the capacitor dielectric stacked layer DS, but not limited thereto. In some embodiments, the capacitor dielectric stacked layer DS may include the zirconium oxide layers34and the zirconium silicon oxide layers32alternately stacked and disposed, and the two material layers located at two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z, respectively, may be the zirconium silicon oxide layers32according to some design considerations. As shown inFIG.12andFIG.13, the process for forming the capacitor dielectric stacked layer DS in this embodiment may include performing the step S41and the step S42alternately and repeatedly, and the end step may be the same as the initial step (both of them may be the step S41) for forming the capacitor dielectric stacked layer DS with the zirconium oxide layers34located at the two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z, respectively. Please refer toFIG.14.FIG.14is a schematic drawing illustrating a capacitor structure108according to an eighth embodiment of the present invention. As shown inFIG.14, in the capacitor structure108, the capacitor dielectric stacked layer DS may include the zirconium oxide layers34and the zirconium silicon oxide layers32alternately stacked and disposed in the vertical direction Z, the thicknesses of at least some of the zirconium oxide layers34may be different from each other, and the thicknesses of at least some of the zirconium silicon oxide layers32may be different from each other. For example, a thickness TK2of the zirconium oxide layer34located close to the center portion of the capacitor dielectric stacked layer DS in the vertical direction Z may be greater than a thickness TK1of each of the zirconium oxide layers34located at two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z, and a thickness TK4of the zirconium silicon oxide layer32located close to the center portion of the capacitor dielectric stacked layer DS in the vertical direction Z may be greater than a thickness TK3of each of the zirconium silicon oxide layers32located close to the two opposite ends of the capacitor dielectric stacked layer DS in the vertical direction Z for adjusting the electric field distribution in the capacitor dielectric stacked layer DS during the operation of the capacitor structure108, but not limited thereto. In some embodiments, the relative relation between the thicknesses of the zirconium oxide layers34and/or the relative relation between the thicknesses of the zirconium silicon oxide layers32in the capacitor dielectric stacked layer DS may be different from the condition described above according to some design considerations. In addition, the zirconium oxide layers34with different thicknesses and/or the zirconium silicon oxide layers32with different thicknesses described above may be formed by adjusting the number of the cycles performed in the corresponding atomic layer deposition processes. For instance, the number of the cycles (such as the number of times to repeat the step S21to the step S24shown inFIG.4) performed in the atomic layer deposition process for forming the relatively thicker zirconium oxide layer34may be relatively more, and the number of the cycles (such as the number of times to repeat the step S11to the step S18shown inFIG.2or the number of times to repeat the step S15to the step S18and the step S11to the step S14shown inFIG.3) performed in the atomic layer deposition process for forming the relatively thicker zirconium silicon oxide layer32may be relatively more also, but not limited thereto. To summarize the above descriptions, in the capacitor structure and the manufacturing method thereof according to the present invention, the capacitor dielectric stacked layer including the zirconium oxide layer and the zirconium silicon oxide layer may be disposed between two electrodes of the capacitor structure. The leakage current of the capacitor structure may be reduced by the zirconium silicon oxide layer, and the operating performance of the capacitor structure may be enhanced accordingly. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 39,799 |
11862667 | DETAILED DESCRIPTION According to an aspect, there is provided a capacitor comprising: a conductive substrate having a first main surface and a second main surface and provided with a plurality of recesses on the first main surface, the conductive substrate further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the plurality of recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface; a conductive layer covering the first main surface, side walls and bottom surfaces of the plurality of recesses, and walls of the plurality of holes; and a dielectric layer interposed between the conductive substrate and the conductive layer. Embodiments will be explained in detail below with reference to the accompanying drawings. Note that the same reference numerals denote constituent elements which achieve the same or similar functions throughout all the drawings, and a repetitive explanation will be omitted. First Embodiment FIG.1is a cross-sectional view schematically showing a capacitor according to a first embodiment.FIG.2is a cross-sectional view showing a part of the capacitor shown inFIG.1in an enlarged manner. A capacitor1shown inFIG.1includes a conductive substrate10, a conductive layer20b, and a dielectric layer50. Incidentally, in each figure, an X direction is a direction parallel to a main surface of the conductive substrate10, and a Y direction is a direction parallel to the main surface of the conductive substrate10and perpendicular to the X direction. In addition, a Z direction is a thickness direction of the conductive substrate10, i.e., a direction perpendicular to the X direction and the Y direction. The conductive substrate10has electrical conductivity in its entire part. The conductive substrate10is, for example, a semiconductor substrate made of a semiconductor doped with P-type or N-type impurities, or a metal substrate. The conductive substrate10is preferably a substrate containing silicon such as a silicon substrate. Such a substrate can be processed using semiconductor processes. The conductive substrate10has a first main surface S1, and a second main surface S2which is a back surface of the first main surface S1. As shown inFIGS.1and2, the first main surface S1is provided with a plurality of recesses R. Here, these recesses R are trenches each having a shape extending in the X direction as a first direction. As shown inFIG.1, the recesses R are arranged in the Y direction as a second direction. A depth D of the recesses R is preferably within a range of 1% to 90%, and more preferably within a range of 1% to 50% of a thickness T of the conductive substrate10. When this ratio is increased, a capacitance of the capacitor1becomes larger. However, when this ratio is increased, the mechanical strength of the capacitor1decreases. A dimension of openings of the recesses R is preferably 0.3 μm or more. Incidentally, the dimension of the opening of the recess R is a diameter or width of the opening of the recess R. Here, the dimension of the opening of the recess R is a dimension in a direction perpendicular to its length direction, i.e., a dimension in a direction perpendicular to a length direction of an orthogonal projection of the recess R onto a plane perpendicular to the thickness direction of the conductive substrate10. When this dimension is reduced, a larger electric capacitance can be achieved. However, when this dimension is reduced, it is difficult to form a stacked structure including the dielectric layer50, and a first layer20b1to be described later, in the recess R. A distance between adjacent recesses R is preferably 0.1 μm or more. When this distance is reduced, a larger electric capacitance can be achieved. However, when this distance is reduced, portions P of the conductive substrate10each sandwiched between two adjacent ones of the recesses R are likely to be damaged. The recesses R can have various shapes. For example, the recess R may have a shape whose orthogonal projection onto a plane perpendicular to the Z direction is linear, curved or bent, or circular or square. Here, a cross section of the recess R parallel to the depth direction is rectangular. This cross section may not be rectangular. For example, this cross section may have a tapered shape. One or more portions P of the conductive substrate10each sandwiched between two adjacent ones of the recesses R are provided with a plurality of holes H. These holes H are not uniformly provided in the portions P. In the portion P, the holes H are provided such that a region on its first main surface S1side has a larger porosity in than a region on its second main surface S2side. Here, each of the portions P is provided with the holes H only in the region on the first main surface S1side. That is, here, each of the portions P includes a first region RS1that is porous, and a second region RS2that is non-porous and interposed between the first region RS1and the second main surface S2. If the holes H are provided only in the region on the first main surface S1side of the portion P, a ratio of a dimension L1of the first region RS1in the depth direction of the recess R to a dimension L2of the second region RS2in the depth direction of the recess R is arbitrary. That is, a ratio of the dimension L1to the depth D of the recess R, and a ratio of the dimension L2to the depth D of the recess R, are arbitrary. However, when the ratio L1/D of the dimension L1to the depth D is increased, the portion P is likely to be damaged in a manufacturing process of the capacitor1, and a parasitic resistance of the capacitor1increases, although the capacitance of the capacitor1can be easily increased. The ratio L1/D is preferably within a range of 1% to 50%, and more preferably within a range of 3% to 10%. The dimension L1is preferably within a range of 1 μm to 50 μm, and more preferably within a range of 3 μm to 10 μm. As long as the region on the first main surface S1side has a larger porosity than the region on the second main surface S2side, the holes H may be provided not only in the region on the first main surface S1side but also in the region on the second main surface S2side. In this case, the porosity of the portion P may change in a continuous or stepwise manner in the depth direction of the recess R. In each portion P, the minimum value of the porosity is preferably 1% or less, and more preferably 0%. In addition, in each portion P, the maximum value of the porosity is preferably within a range of 10% to 90%, and more preferably within a range of 30% to 70%. Note that “the porosity” mentioned here is a value obtained by the following method. First, a cross section of the portion P parallel to the depth direction of the recess R is photographed using a scanning electron microscope at a magnification of ×20,000 to ×100,000. Then, a proportion of the area of the holes H in the area of the portion P is obtained in this image. The value obtained in this way is the porosity. Each of the holes H may be a blind hole or a through hole. Each of the holes H may be branched or may not be branched. Each of the holes H may be connected to other holes H or may not be connected. An average diameter of the holes H is preferably 0.05 μm or more. When the diameter of the holes H is reduced, more holes H can be disposed, thereby achieving a larger electric capacitance. However, when the diameter of the holes H is reduced too much, there is a possibility that it may be difficult to form, in the holes H, a stacked structure including the dielectric layer50and the first layer20b1to be described later. The conductive layer20bcovers the first main surface S1, side walls and bottom surfaces of the recesses R, and walls of the holes H. The conductive layer20bmay have a single-layer structure, or may have a multi-layer structure. Here, the conductive layer20bhas a double-layer structure of the first layer20b1and a second layer20b2. The first layer20b1is a layer having electrical conductivity. The first layer20b1covers the first main surface S1, the side walls and the bottom surfaces of the recesses R, and the walls of the holes H. Here, portions of the first layer20b1that face the first main surface S1and the side walls and the bottom surfaces of the recesses R are conformal to a surface of the conductive substrate10. That is, here, the first layer20b1is a layer having an approximately uniform thickness. Portions of the first layer20b1that face the first main surface S1and the side walls and the bottom surfaces of the recesses R may not be conformal to the surface of the conductive substrate10. The first layer20b1and the dielectric layer50fill the holes H. That is, the holes H are filled with the dielectric layer50and the first layer20b1, without leaving a gap. With this structure, a possibility that the portion P may be damaged during a period from forming the first layer20b1until forming the second layer20b2can be reduced. Portions of the first layer20b1positioned in the holes H may be conformal to the walls of the holes H. The second layer20b2is a layer having electrical conductivity. The second layer20b2faces the first main surface S1, the side walls and the bottom surfaces of the recesses R, and the walls of the holes H, with the first layer20b1interposed therebetween. The second layer20b2, the dielectric layer50, and the first layer20b1fill the recesses R. Portions of the second layer20b2that face the side walls and the bottom surfaces of the recesses R may be conformal to the side walls and the bottom surfaces of the recesses R. The conductive layer20band the dielectric layer50fill the holes H. That is, the holes H are filled with the dielectric layer50and the conductive layer20b, without leaving a gap. With this structure, a possibility that the portion P may be damaged after forming the conductive layer20bcan be reduced. Portions of the conductive layer20bpositioned in the holes H may be conformal to the walls of the holes H. The conductive layer20band the dielectric layer50fill the recesses R. Portions of the conductive layer20bthat face the side walls and the bottom surfaces of the recesses R may be conformal to the side walls and the bottom surfaces of the recesses R. Each layer constituting the conductive layer20bis made of, for example, polysilicon doped with impurities to improve electrical conductivity. Each layer constituting the conductive layer20bmay be a layer made of a metal or alloy such as nickel, copper, or tungsten. The material of the first layer20b1and the material of the second layer20b2may be the same or different. Here, it is supposed that the first layer20b1and the second layer20b2are made of polysilicon doped with P-type or N-type impurities. The thickness of the first layer20b1is preferably within a range of 0.05 μm to 1 μm, and more preferably within a range of 0.1 μm to 0.3 μm. If the first layer20b1is thin, there is a possibility that a discontinuous portion may be generated in the first layer20b1, or a sheet resistance of the first layer20b1may be excessively increased. If the first layer20b1is thick, it may be difficult to form the dielectric layer50with a sufficient thickness. The dielectric layer50is interposed between the conductive substrate10and the conductive layer20b. The dielectric layer50is conformal to the surface of the conductive substrate10, specifically, to the first main surface S1, the side walls and the bottom surfaces of the recesses R, and the inner walls of the holes H. The dielectric layer50electrically insulates the conductive substrate10and the conductive layer20bfrom each other. The dielectric layer50may have a single-layer structure or a multi-layer structure. The dielectric layer50is made of, for example, an inorganic dielectric. As the inorganic dielectric, a ferroelectric, e.g., HfSiO, HfSiON, or HfO2, can also be used. For example, paraelectrics such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, alumina, and tantalum oxide are preferable. These paraelectrics have a small change in dielectric constant with temperature. Therefore, when the paraelectrics are used for the dielectric layer50, the heat resistance of the capacitor1can be improved. The dielectric layer50preferably includes a silicon oxide layer. The dielectric layer50including a silicon oxide layer is, for example, a silicon oxide layer, or a layer having a multi-layer structure including one or more silicon oxide layers and one or more other layers. This layer having a multi-layer structure is, for example, a layer including a silicon oxide layer and a silicon nitride layer, a layer including a silicon oxide layer and a silicon oxynitride layer, or a layer including a silicon oxide layer and a metal oxide layer. Incidentally, if a silicon substrate is used as the conductive substrate10, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer can be formed respectively by oxidizing, nitriding, or oxynitriding a surface region of the conductive substrate10. The thickness of the dielectric layer50is preferably within a range of 0.005 μm to 0.5 μm, and more preferably within a range of 0.01 μm to 0.1 μm. If the dielectric layer50is thin, there is a possibility that a discontinuous portion may be generated in the dielectric layer50, and the conductive substrate10and the conductive layer20bmay be short-circuited. Further, when the dielectric layer50is thinned, a withstand voltage is lowered even if there is no short circuit, and a possibility of short-circuiting on voltage application increases. When the dielectric layer50is thickened, the withstand voltage increases, but the electric capacitance decreases. This capacitor1further includes a first electrode70aand a second electrode70b. The first electrode70afaces the first main surface S1, and is electrically connected to the conductive layer20b. Here, the first electrode70ais provided on the conductive layer20b, and the second electrode70bis provided on the second main surface S2. As long as the first electrode70aand the second electrode70bare electrically insulated from the conductive substrate10and the conductive layer20b, respectively and electrically connected to the conductive layer20band the conductive substrate10, respectively, both of them may be provided on one main surface of the capacitor1. The first electrode70aand the second electrode70bmay have a single-layer structure or a multi-layer structure. Each layer constituting the first electrode70aand the second electrode70bis made of a metal or alloy such as aluminum, copper, nickel, or a nickel alloy. This capacitor1is manufactured, for example, by the following method. FIG.3is a cross-sectional view schematically showing a process in the manufacture of the capacitor shown inFIG.1.FIG.4is a cross-sectional view schematically showing another process in the manufacture of the capacitor shown inFIG.1.FIG.5is a cross-sectional view schematically showing an example of a structure obtained by the process ofFIG.4.FIG.6is a cross-sectional view schematically showing still another process in the manufacture of the capacitor shown inFIG.1.FIG.7is a cross-sectional view schematically showing still another process in the manufacture of the capacitor shown inFIG.1.FIG.8is a cross-sectional view schematically showing an example of a structure obtained by the process ofFIG.7.FIG.9is a cross-sectional view schematically showing still another process in the manufacture of the capacitor shown inFIG.1. In this method, the conductive substrate10shown inFIG.3is first prepared. Here, as an example, it is supposed that the conductive substrate10is a single-crystal silicon wafer doped with P-type or N-type impurities. A plane orientation of the single-crystal silicon wafer is not particularly limited, but in this example, a silicon wafer whose first main surface S1is a (100) plane is used. As the conductive substrate10, a silicon wafer whose first main surface S1is a (110) plane can also be used. Next, the recesses R are formed on the conductive substrate10by MacEtch (Metal-Assisted Chemical Etching). That is, as shown inFIG.3, a first catalyst layer80acontaining a first noble metal is first formed on the first main surface S1of the conductive substrate10. The first catalyst layer80ais formed so as to partially cover the first main surface S1. Specifically, a first mask layer90ais first formed on the first main surface S1of the conductive substrate10. The first mask layer90ais opened at positions corresponding to the recesses R. The first mask layer90aprevents the first noble metal to be described later from coming into contact with a portion of the first main surface S1that is covered with the first mask layer90a. Examples of the material of the first mask layer90ainclude organic materials such as polyimide, fluororesin, phenol resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride. The first mask layer90acan be formed by, for example, existing semiconductor processes. The first mask layer90amade of an organic material can be formed by, for example, photolithography. The first mask layer90amade of an inorganic material can be formed by, for example, the deposition of an inorganic material layer by vapor phase deposition, formation of a mask by photolithography, and patterning of the inorganic material layer by etching. Alternatively, the first mask layer90amade of an inorganic material can be formed by oxidation or nitriding of the surface region of the conductive substrate10, formation of a mask by photolithography, and patterning of an oxide or nitride layer by etching. Next, the first catalyst layer80ais formed on regions of the first main surface S1that are not covered with the first mask layer90a. The first catalyst layer80ais, for example, a discontinuous layer containing the first noble metal. Here, as an example, it is supposed that the first catalyst layer80ais a particulate layer formed of first catalyst particles81acontaining the first noble metal. The first noble metal is, for example, one or more of gold, silver, platinum, rhodium, palladium, and ruthenium. The first catalyst layer80aand the first catalyst particles81amay further contain a metal other than a noble metal, e.g. titanium. The first catalyst layer80acan be formed by, for example, electroplating, reduction plating, or displacement plating. The first catalyst layer80amay also be formed by application of a dispersion containing noble metal particles, or vapor deposition such as evaporation and sputtering. Of these methods, the displacement plating is particularly favorable because it is possible to directly and evenly deposit the first noble metal on regions of the first main surface S1that are not covered with the first mask layer90a. Next, the conductive substrate10is etched with an assist from the first noble metal as a catalyst to form the recesses R shown inFIGS.1and5on the substrate10. Specifically, as shown inFIG.4, the conductive substrate10is etched with a first etchant100a. For example, the conductive substrate10is immersed in the first etchant100ain liquid form to bring the first etchant100ainto contact with the first main surface S1of the conductive substrate10. The first etchant100acontains an oxidizer and hydrogen fluoride. The concentration of hydrogen fluoride in the first etchant100ais preferably within a range of 1 mol/L to 20 mol/L, and more preferably within a range of 5 mol/L to 10 mol/L. When the hydrogen fluoride concentration is low, it is difficult to achieve a high etching rate. When the hydrogen fluoride concentration is high, excess side etching may occur. The oxidizer can be selected from, for example, hydrogen peroxide, nitric acid, AgNO3, KAuCl4, HAuCl4, K2PtCl6, H2PtCl6, Fe(NO3)3, Ni(NO3)2, Mg(NO3)2, Na2S2O8, K2S2O8, KMnO4, and K2Cr2O7. Hydrogen peroxide is preferable as the oxidizer, since no harmful byproduct is produced and no contamination of the semiconductor element occurs. The concentration of the oxidizer in the first etchant100ais preferably within a range of 0.2 mol/L to 8 mol/L, and more preferably within a range of 2 mol/L to 4 mol/L. The first etchant100amay further contain a buffering agent. The buffering agent contains, for example, at least one of ammonium fluoride and ammonia. As an example, the buffering agent is ammonium fluoride. As another example, the buffering agent is a mixture of ammonium fluoride and ammonia. The first etchant100amay further contain other components such as water. When such a first etchant100ais used, the material of the conductive substrate10, i.e. silicon in this example, is oxidized only in regions of the conductive substrate10that are close to the first catalyst particles81a. Oxide generated thereby is dissolved and removed by hydrofluoric acid. Therefore, only the portions close to the first catalyst particles81aare selectively etched. The first catalyst particles81amove toward the second main surface S2with the progress of etching, where etching similar to the above is performed. As a result, as shown inFIG.4, at the position of the first catalyst layer80a, etching proceeds from the first main surface S1toward the second main surface S2in a direction perpendicular to the first main surface S1. In this way, as shown inFIG.5, the recesses R are formed on the first main surface S1. Thereafter, the first mask layer90aand the first catalyst layer80aare removed from the conductive substrate10. At least one of the first mask layer90aand the first catalyst layer80amay not be removed from the conductive substrate10. Next, as shown inFIG.6, a second mask layer90bis formed on the conductive substrate10. The second mask layer90bis formed such that top surfaces of the portions P and regions of the side surfaces of the portions P adjacent to the openings of the recesses R are exposed, and a region of each recess R that is on its bottom portion side is filled. The second mask layer90bprevents the noble metal to be described later from contacting the bottom surfaces of the recesses R and the regions of the side walls of the recesses R adjacent to the bottom surfaces. As a material of the second mask layer90b, for example, those exemplified for the first mask layer90acan be used. The second mask layer90bcan be formed, for example, by the method exemplified for the first mask layer90a. Next, the second catalyst layer80bis formed on the top surfaces of the portions P and the regions of the side surfaces of the portions P that are adjacent to the openings of the recesses R. The second catalyst layer80bis a discontinuous layer containing a second noble metal. Specifically, the second catalyst layer80bis a particulate layer formed of second catalyst particles81bcontaining the second noble metal. As the second noble metal, for example, those exemplified for the first noble metal can be used. The second catalyst layer80band the second catalyst particles81bmay further contain a metal other than a noble metal, e.g. titanium. The second catalyst layer80bcan be formed, for example, by the method exemplified for the first catalyst layer80a. Note that the second catalyst layer80bis formed, for example, so as to generate larger gaps between the second catalyst particles81bthan the gaps between the first catalyst particles81a. Next, the conductive substrate10is etched with an assist from the second noble metal as a catalyst to form the holes H shown inFIGS.1,2, and8on the conductive substrate10. Specifically, as shown inFIG.7, the conductive substrate10is etched with a second etchant100b. For example, the conductive substrate10is immersed in the liquid second etchant100bto bring the second etchant100binto contact with the top surfaces of the portions P and the regions of the side surfaces of the portions P that are adjacent to the openings of the recesses R. As the second etchant100b, for example, those exemplified for the first etchant100acan be used. In this way, as shown inFIG.8, the holes H are formed in the portions P. Thereafter, the second mask layer90band the second catalyst particles81bare removed from the conductive substrate10. The second catalyst particles81bmay not be removed from the conductive substrate10. Next, the dielectric layer50and the first layer20b1shown inFIG.9are formed in this order on the conductive substrate10. The dielectric layer50can be formed by, for example, CVD (chemical vapor deposition). Alternatively, the dielectric layer50can be formed by oxidizing, nitriding, or oxynitriding the surface of the conductive substrate10. If the first layer20b1is made of polysilicon doped with P-type or N-type impurities, such a first layer20b1can be formed by, for example, LPCVD (low pressure chemical vapor deposition). Subsequently, the second layer20b2and the first electrode70ashown inFIG.1are formed in this order, and the second electrode70bis further formed. If the second layer20b2is made of polysilicon doped with P-type or N-type impurities, such a second layer20b2can be formed by, for example, LPCVD. The first electrode70aand the second electrode70bcan be formed by, for example, sputtering or plating. In the manner described above, the capacitor1shown inFIG.1is obtained. FIG.10is an electron micrograph showing an example of a structure obtained by the process shown inFIG.9. The photograph shown inFIG.10is obtained by photographing a cross section of the portion P shown inFIG.9that is perpendicular to the X direction. FromFIG.10, it can be seen that the holes H are provided in the portions P, and each of these holes H is filled with a stacked structure of the dielectric layer50and the first layer20b1. In the above-described manufacturing method, if at least one of the first layer20b1and the second layer20b2is a metal layer, such a metal layer can be formed by, for example, electroplating, reduction plating, or displacement plating. A plating solution is a liquid containing a salt of a metal to be plated. As the plating solution, a general plating solution, such as a copper sulfate plating solution containing copper sulfate pentahydrate and sulfuric acid, a copper pyrophosphate plating solution containing copper pyrophosphate and potassium pyrophosphate, and a nickel sulfamate plating solution containing nickel sulfamate and boron, can be used. This metal layer is preferably formed by a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state. In this plating method, the surfactant is interposed between particles made of supercritical carbon dioxide and a continuous phase of a solution containing a salt of a metal to be plated. That is, micelles are formed on the surfactant in the plating solution, and supercritical carbon dioxide is incorporated into these micelles. In a normal plating method, the supply of a metal to be plated may be insufficient in the vicinity of the bottom portions of the recesses R and in the holes H. This is particularly noticeable when a ratio D/W of the depth D to a width or diameter W of the recess R, or a ratio L/d of a length L to a diameter d of the hole H is large. The micelles incorporating supercritical carbon dioxide can easily enter narrow gaps. As the micelles move, the solution containing a salt of a metal to be plated also moves. Therefore, according to a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state, a metal layer having a uniform thickness can be easily formed. In addition, in the above manufacturing method, the recesses R and the holes H are formed by performing etching twice. Thereby, non-porous regions and porous regions are generated in the portions P. In this method, if the second etching is repeated while changing the condition, it is possible to generate, in the portions P, non-porous regions, and two or more porous regions having mutually different porosities and arranged such that the porosity increases as the distance from the non-porous regions increases. For example, if the cycle including the processes described with reference toFIGS.6and7is repeated so that the thickness of the second mask layer90bsuccessively decreases for every cycle, it is possible to generate non-porous regions, and two or more porous regions having mutually different porosities and arranged such that the porosity increases as the distance from the non-porous regions increases. Alternatively, in this method, if a plating solution having a high viscosity is used without forming the second mask layer90bwhen forming the second catalyst layer80b, the second catalyst layer80bin which the number of the second catalyst particles81bper unit area on the side walls of the recesses R consecutively decreases from the openings toward the bottom portions of the recesses R can be obtained. By performing the MacEtch using such a second catalyst layer80b, a structure in which the porosity of the portions P continuously decreases from the first main surface S1side toward the second main surface S2side can be obtained. In addition, it is also possible to simultaneously form the recesses R and the holes H by one-time etching if the etching conditions are set appropriately. In this capacitor1, the stacked structure including the dielectric layer50and the first layer20b1is provided not only on the first main surface S1but also on the side walls and the bottom surfaces of the recesses R. Therefore, this capacitor1can achieve a large electric capacitance. In addition, in this capacitor1, the portions P of the conductive substrate10each sandwiched between two adjacent ones of the recesses R are provided with the holes H. The stacked structure including the dielectric layer50and the first layer20b1is also provided on the walls of the holes H. Therefore, the capacitor1adopting this structure can achieve a larger electric capacitance than a capacitor in which the holes H are omitted. In a capacitor having a uniform porosity in the entire portions P, electric charges are difficult to move between the second electrode70band the first main surface S1side regions of the portions P, and a parasitic resistance is large. In contrast, in the above-described capacitor1, the holes H are provided in the portions P in such a manner that the first main surface S1side regions have a larger porosity than the second main surface S2side regions. Therefore, this capacitor1can achieve a small parasitic resistance. In a capacitor having a uniform porosity in the entire portions P, the portions P are likely to be damaged especially in its manufacturing process. In contrast, in the above-described capacitor1, the holes H are provided in the portions P in such a manner that the first main surface S1side regions have a larger porosity than the second main surface S2side regions. Therefore, the portions P of this capacitor1are less likely to be damaged, for example, in its manufacturing process, enabling the manufacture at a high yield. Second Embodiment FIG.11is a cross-sectional view showing a part of a capacitor according to a second embodiment in an enlarged manner. The capacitor according to the second embodiment is the same as the capacitor1according to the first embodiment except for the following points. That is, in the capacitor according to the second embodiment, the conductive substrate10includes a substrate main body10aand a conductive layer20a. The substrate main body10aincludes two main surfaces. On one main surface of the substrate main body10a, recesses corresponding to the recesses R are provided. In addition, in a portion of the substrate main body10athat is sandwiched between two adjacent ones of the recesses R, holes corresponding to the holes H are provided. The substrate main body10amay or may not have electrical conductivity. Here, as an example, it is supposed that the substrate main body10ahas electrical conductivity. The conductive layer20acovers the main surface of the substrate main body10aon which the recesses are provided, side walls and bottom surfaces of these recesses, and walls of the holes provided in the portions of the substrate main body10aeach sandwiched between two adjacent ones of the recesses R. The conductive layer20amay further cover an end face and the main surface not provided with the recesses, of the substrate main body10a. The conductive layer20ais conformal to a surface of the substrate main body10a. That is, the conductive layer20ais a layer having an approximately uniform thickness, and together with the substrate main body10a, forms the recesses R and the holes H on the surface of the conductive substrate10. As a material of the conductive layer20a, for example, those exemplified for the conductive layer20bcan be used. In addition, the conductive layer20amay be formed by lowering a resistance of the substrate main body10aby ion doping, etc. According to an example, the conductive layer20ahas high electrical conductivity as compared with the substrate main body10a. The thickness of the conductive layer20ais preferably within the range described above for the first layer20b1. The conductive layer20acan be formed, for example, by the method exemplified for the conductive layer20b. The capacitor adopting this structure has the same effects as those of the capacitor1according to the first embodiment. Furthermore, the capacitor adopting this structure can achieve a smaller parasitic resistance if the substrate main body10ahas electrical conductivity and the conductive layer20ahas high electrical conductivity as compared with the substrate main body10a. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 34,537 |
11862668 | DETAILED DESCRIPTION Memory devices may include various arrangements of memory arrays and supporting circuitry formed with or over a substrate. For example, a memory device may include one or more decks of memory arrays over a substrate, where a deck may refer to a plane or level of memory cells (e.g., of one or more memory arrays) above the substrate and, in some examples, generally parallel to the substrate. In some examples, circuitry that supports accessing or operating the memory arrays may be located below the memory arrays, which may refer to a location that is at least in part between the memory arrays and the substrate (e.g., in a vertical direction). For example, sensing circuitry, decoding circuitry, periphery circuitry, or other logic and circuitry may be located below the memory arrays but at least in part above the substrate and, in some examples, may include transistors that are formed at least in part by doping portions of the substrate (e.g., substrate-based transistors, transistors having channels formed from doped crystalline silicon or another semiconductor substrate). But as memory devices scale with and have a greater quantity of layers or decks of memory arrays above a substrate, the area of a substrate used for such substrate-based circuitry may increase, which may lead to additional limitations (e.g., related to the limited area of a substrate to support a growing quantity of decks and, by extension, a growing quantity and area for such substrate-based circuitry, related to routing challenges associated with locating some circuitry below a stack of decks but not above the stack of decks). In accordance with examples as disclosed herein, a memory device may include one or more decks of memory cells and circuitry for accessing or operating the memory cells (e.g., semiconductor circuitry, transistor circuitry, complementary metal-oxide-semiconductor (CMOS) circuitry) with some of the circuitry being located above the one or more decks and some being located below the one or more decks. For example, the memory device may include lower substrate-based circuitry formed, in some examples, at least in part by doping portions of a lower semiconductor substrate (e.g., a base substrate, a silicon substrate, a crystalline semiconductor substrate, a chip or wafer) to form a first set of components, such as transistors. Above the lower substrate-based circuitry, the memory device may include one or more decks of memory cells and upper circuitry (e.g., transistors of the upper circuitry) formed, in some examples, at least in part by a semiconductor that is deposited over the one or more decks and formed in a crystalline arrangement based on a heating and a cooling of the deposited semiconductor. The semiconductor material may be deposited into tapered cavities that are etched into one or more dielectric or oxide materials, where the tapering may promote nucleation of the crystalline arrangement at a respective single location (e.g., at a bottom end of the cavity), rather than multiple nucleation locations that may result in a polycrystalline or multi-grain arrangement. In some examples, the described techniques may include depositing a seed material at the bottom of the cavities to further promote such cohesive single-grain nucleation. Channel portions of one or more transistors may be formed at least in part by doping regions of the single crystalline arrangement of the deposited semiconductor material. Accordingly, operation of the one or more decks of memory cells may be supported by lower circuitry, which may be formed at least in part by doped portions of a crystalline semiconductor substrate (e.g., a crystalline chip or wafer), and upper circuitry, which may be formed at least in part by doped portions of a semiconductor deposited over the one or more decks and formed with a crystalline arrangement in-situ. Features of the disclosure are initially described in the context of a memory device and related circuitry as described with reference toFIGS.1and2. Features of the disclosure are described in the context of a memory device layout and illustrative fabrication techniques with reference toFIGS.3-7. These and other features of the disclosure are further illustrated by and described with reference to flowcharts that relate to single-crystal transistors for memory devices as described with reference toFIGS.8and9. FIG.1illustrates an example of a memory device100that supports single-crystal transistors for memory devices in accordance with examples as disclosed herein. The memory device100may also be referred to as an electronic memory apparatus. The memory device100may include memory cells105that are programmable to store different logic states. In some cases, a memory cell105may be programmable to store two logic states, denoted a logic 0 and a logic 1. In some cases, a memory cell105may be programmable to store more than two logic states (e.g., as a multi-level cell). The set of memory cells105may be part of a memory array110of the memory device100, where, in some examples, a memory array110may refer to a contiguous tile of memory cells105(e.g., a contiguous set of elements of a semiconductor chip). In some examples, a memory cell105may store an electric charge representative of the programmable logic states (e.g., storing charge in a capacitor, capacitive memory element, capacitive storage element). In one example, a charged and uncharged capacitor may represent two logic states, respectively. In another example, a positively charged (e.g., a first polarity, a positive polarity) and negatively charged (e.g., a second polarity, a negative polarity) capacitor may represent two logic states, respectively. DRAM or FeRAM architectures may use such designs, and the capacitor employed may include a dielectric material with linear or para-electric polarization properties as an insulator. In some examples, different levels of charge of a capacitor may represent different logic states, which, in some examples, may support more than two logic states in a respective memory cell105. In some examples, such as FeRAM architectures, a memory cell105may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between terminals of the capacitor. Different levels or polarities of polarization of a ferroelectric capacitor may represent different logic states (e.g., supporting two or more logic states in a respective memory cell105). In some examples, a memory cell105may include or otherwise be associated with a configurable material, which may be referred to as a material memory element, a material storage element, a material portion, and others. The configurable material may have one or more variable and configurable characteristics or properties (e.g., material states) that may represent different logic states. For example, a configurable material may take different forms, different atomic configurations, different degrees of crystallinity, different atomic distributions, or otherwise maintain different characteristics that may be leveraged to represent one logic state or another. In some examples, such characteristics may be associated with different electrical resistances, different threshold characteristics, or other properties that are detectable or distinguishable during a read operation to identify a logic state written to or stored by the configurable material. In some cases, a configurable material of a memory cell105may be associated with a threshold voltage. For example, electrical current may flow through the configurable material when a voltage greater than the threshold voltage is applied across the memory cell105, and electrical current may not flow through the configurable material, or may flow through the configurable material at a rate below some level (e.g., according to a leakage rate), when a voltage less than the threshold voltage is applied across the memory cell105. Thus, a voltage applied to memory cells105may result in different current flow, or different perceived resistance, or a change in resistance (e.g., a thresholding or switching event) depending on whether a configurable material portion of the memory cell105was written with one logic state or another. Accordingly, the magnitude of current, or other characteristic (e.g., thresholding behavior, resistance breakdown behavior, snapback behavior) associated with the current that results from applying a read voltage to the memory cell105, may be used to determine a logic state written to or stored by memory cell105. In the example of memory device100, each row of memory cells105may be coupled with one or more word lines120(e.g., WL1through WLM), and each column of memory cells105may be coupled with one or more digit lines130(e.g., DL1through DLN). Each of the word lines120and digit lines130may be an example of an access line of the memory device100. In general, one memory cell105may be located at the intersection of (e.g., coupled with, coupled between) a word line120and a digit line130. This intersection may be referred to as an address of a memory cell105. A target or selected memory cell105may be a memory cell105located at the intersection of an energized or otherwise selected word line120and an energized or otherwise selected digit line130. In some architectures, a storage component of a memory cell105may be electrically isolated (e.g., selectively isolated) from a digit line130by a cell selection component, which, in some examples, may be referred to as a switching component or a selector device of or otherwise associated with the memory cell105. A word line120may be coupled with the cell selection component (e.g., via a control node or terminal of the cell selection component), and may control the cell selection component of the memory cell105. For example, the cell selection component may be a transistor and the word line120may be coupled with a gate of the transistor (e.g., where a gate node of the transistor may be a control node of the transistor). Activating a word line120may result in an electrical connection or closed circuit between a respective logic storing component of one or more memory cells105and one or more corresponding digit lines130. A digit line130may then be accessed to read from or write to the respective memory cell105. In some examples, memory cells105may also be coupled with one or more plate lines140(e.g., PL1through PLN). In some examples, each of the plate lines140may be independently addressable (e.g., supporting individual selection or biasing). In some examples, the plurality of plate lines140may represent or be otherwise functionally equivalent with a common plate, or other common node (e.g., a plate node common to each of the memory cells105in the memory array110). When a memory cell105employs a capacitor for storing a logic state, a digit line130may provide access to a first terminal or a first plate of the capacitor, and a plate line140may provide access to a second terminal or a second plate of the capacitor. Although the plurality of plate lines140of the memory device100are shown as substantially parallel with the plurality of digit lines130, in other examples, a plurality of plate lines140may be substantially parallel with the plurality of word lines120, or in any other configuration (e.g., a common planar conductor, a common plate layer). Access operations such as reading, writing, rewriting, and refreshing may be performed on a memory cell105by activating or selecting a word line120, a digit line130, or a plate line140coupled with the memory cell105, which may include applying a voltage, a charge, or a current to the respective access line. Upon selecting a memory cell105(e.g., in a read operation), a resulting signal may be used to determine the logic state stored by the memory cell105. For example, a memory cell105with a capacitive memory element storing a logic state may be selected, and the resulting flow of charge via an access line or resulting voltage of an access line may be detected to determine the programmed logic state stored by the memory cell105. Accessing memory cells105may be controlled using a row component125(e.g., a row decoder), a column component135(e.g., a column decoder), or a plate component145(e.g., a plate decoder), or a combination thereof. For example, a row component125may receive a row address from the memory controller170and activate the appropriate word line120based on the received row address. Similarly, a column component135may receive a column address from the memory controller170and activate the appropriate digit line130. In some examples, such access operations may be accompanied by a plate component145biasing one or more of the plate lines140(e.g., biasing one of the plate lines140, biasing some or all of the plate lines140, biasing a common plate). In some examples, the memory controller170may control operations (e.g., read operations, write operations, rewrite operations, refresh operations) of memory cells105using one or more components (e.g., row component125, column component135, plate component145, sense component150). In some cases, one or more of the row component125, the column component135, the plate component145, and the sense component150may be co-located or otherwise included with the memory controller170. The memory controller170may generate row and column address signals to activate a desired word line120and digit line130. The memory controller170may also generate or control various voltages or currents used during the operation of memory device100. A memory cell105may be read (e.g., sensed) by a sense component150when the memory cell105is accessed (e.g., in cooperation with the memory controller170) to determine a logic state written to or stored by the memory cell105. For example, the sense component150may be configured to evaluate a current or charge transfer through or from the memory cell105, or a voltage resulting from coupling the memory cell105with the sense component150, responsive to a read operation. The sense component150may provide an output signal indicative of the logic state read from the memory cell105to one or more components (e.g., to the column component135, the input/output (I/O) component160, to the memory controller170). A sense component150may include various switching components, selection components, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify a difference in sensing signals (e.g., a difference between a read voltage and a reference voltage, a difference between a read current and a reference current, a difference between a read charge and a reference charge), which, in some examples, may be referred to as latching. In some examples, a sense component150may include a collection of components (e.g., circuit elements) that are repeated for each of a set of digit lines130connected to the sense component150. For example, a sense component150may include a separate sensing circuit (e.g., a separate or duplicated sense amplifier, a separate or duplicated signal development component) for each of a set of digit lines130coupled with the sense component150, such that a logic state may be separately detected for a respective memory cell105coupled with a respective one of the set of digit lines130. A memory cell105may be set, or written, by activating the relevant word line120, digit line130, or plate line140(e.g., via a memory controller170). In other words, a logic state may be stored in a memory cell105. A row component125, a column component135, or a plate component145may accept data, for example, via I/O component160, to be written to the memory cells105. In some examples, a write operation may be performed at least in part by a sense component150, or a write operation may be configured to bypass a sense component150. In the case of a capacitive memory element, a memory cell105may be written by applying a voltage to or across a capacitor, and then isolating the capacitor (e.g., isolating the capacitor from a voltage source used to write the memory cell105, floating the capacitor) to store a charge in the capacitor associated with a desired logic state. In the case of ferroelectric memory, a ferroelectric memory element (e.g., a ferroelectric capacitor) of a memory cell105may be written by applying a voltage with a magnitude sufficient to polarize the ferroelectric memory element (e.g., applying a saturation voltage) with a polarization associated with a desired logic state, and the ferroelectric memory element may be isolated (e.g., floating), or a zero net voltage or bias may be applied across the ferroelectric memory element (e.g., grounding, virtually grounding, or equalizing a voltage across the ferroelectric memory element). In the case of a material memory architecture, a memory cell105may be written by applying a current, voltage, or other heating or biasing to a material memory element to configure the material according to a corresponding logic state. In some examples, the memory device100may include multiple memory arrays110arranged in a stack of decks or levels relative to a substrate of the memory device100(e.g., a semiconductor substrate, a crystalline silicon substrate, a crystalline semiconductor substrate, a portion of a semiconductor chip or wafer). In some cases, circuitry that supports accessing or operating the multiple memory arrays110(e.g., semiconductor circuitry, transistor circuitry, CMOS circuitry) may be located below the memory arrays110, which may refer to a location that is at least in part between the memory arrays110and the substrate. For example, one or more row components125, one or more column components135, one or more plate components145, one or more sense components150, or one or more I/O components160, or any combination thereof, may be located below the memory arrays110and above the substrate and, in some examples, may include transistors that are formed at least in part by doping portions of the substrate (e.g., substrate-based transistors, transistors having channels formed from doped crystalline silicon or other semiconductor). When scaling the memory device100with a greater quantity of decks or levels of memory arrays110, the area of a substrate used for supporting circuitry may increase, which may lead to scaling limitations (e.g., related to the limited area of a substrate to support circuitry for accessing a growing quantity of decks or levels of memory arrays110and, by extension, a growing quantity and area for such decoders or other supporting circuitry, related to routing challenges associated with locating certain circuitry below a stack of decks but not above the stack of decks), among other challenges. In accordance with examples as disclosed herein, the memory device100may include one or more memory arrays110, which may include memory arrays110arranged in a stack of decks formed above a substrate, and transistor circuitry formed both above and below the one or more memory arrays110to support accessing or operating the respective memory cells105. For example, the memory device100may include lower substrate-based circuitry formed at least in part by doping portions of a semiconductor substrate (e.g., a base substrate, a silicon substrate, a crystalline semiconductor substrate, a chip or wafer) to form a first set of transistors. Above the lower substrate-based circuitry, the memory device100may include one or more decks of memory cells105and upper circuitry (e.g., transistors of the upper circuitry) formed at least in part by a semiconductor material that is deposited over the one or more decks and formed in a crystalline arrangement based on heating and cooling of the deposited semiconductor. The semiconductor material may be deposited into tapered cavities that are etched into one or more dielectric or oxide materials, where the tapering may promote nucleation of the crystalline arrangement at a respective single location (e.g., at a bottom end of the respective cavity), rather than multiple nucleation locations that may result in a polycrystalline or multi-grain arrangement. In some examples, the described techniques may include depositing a seed material at the bottom of the cavities to further promote such cohesive single-grain nucleation. Channel portions of a second set of transistors (e.g., of the upper circuitry) may be formed at least in part by doping regions of the single crystalline arrangement of the deposited semiconductor material. Thus, operation of the one or more decks of memory cells105may be supported by lower circuitry, which may be formed at least in part by doped portions of a crystalline semiconductor substrate (e.g., a crystalline chip or wafer), and upper circuitry, which may be formed at least in part by doped portions of a semiconductor deposited over the one or more decks and formed with a crystalline arrangement in-situ. A combination of lower substrate-based circuitry and upper circuitry using a semiconductor crystallized in-situ may support accessing or operating of the decks of memory cells105in accordance with various techniques. For example, circuitry associated with a row component125, a column component135, a plate component145, or a sense component150, among other components or circuitry, may be divided between or distributed among lower circuitry and upper circuitry, including various allocations of circuitry associated with operating certain decks of a stack of decks of memory arrays110. In some examples, circuitry that is common to or shared by each deck of the stack (e.g., one or more portions of an I/O component160, or a memory controller170, among other components or circuitry) may be coupled with lower circuitry and upper circuitry and, in some examples, may be formed above the upper circuitry. Implementing operating circuitry across regions of crystalline semiconductor both above and below one or more memory arrays110may increase an area available for such circuitry compared to memory devices that include a single level of substrate-based semiconductor circuitry. Such techniques may support the memory device100leveraging crystalline semiconductor materials for a greater quantity of components, or larger components, for circuitry such as sensing circuitry, decoding circuitry, or periphery circuitry, among other circuitry used for accessing or otherwise operating memory arrays110of the memory device100. In some examples, implementing such circuitry in multiple levels of crystalline semiconductor may alleviate or mitigate area utilization challenges or routing challenges of a single substrate level, which may improve scaling in memory devices100by supporting a greater quantity of decks for a given footprint. Accordingly, utilizing multiple levels of crystalline semiconductor circuitry may enable a greater scaling of decks, or improved scaling of memory storage, among other advantages. FIG.2illustrates an example of a transistor structure200that supports single-crystal transistors for memory devices in accordance with examples as disclosed herein. The transistor structure200illustrates an example of a transistor that is formed at least in part by portions of a semiconductor material220(e.g., doped portions240of the semiconductor material220), and may illustrate an arrangement of features for a transistor that is configured in a planar transistor arrangement. In some examples, the semiconductor material220, or some portion thereof, may be formed with a crystalline arrangement, which may support favorable operational characteristics of the transistor structure200, such as improved channel or charge carrier characteristics, among other characteristics. For example, the semiconductor material220may be formed such that at least adjacent doped portions240of the semiconductor material (e.g., doped portions240-a-1,240-b, and240-a-2) are formed with a same or continuous atomic arrangement (e.g., a continuous crystalline arrangement), or are formed without grain boundaries or other discontinuities between different atomic arrangements. For illustrative purposes, aspects of the transistor structure200may be described with reference to an x-direction, a y-direction, and a z-direction (e.g., a height direction) of a coordinate system210. In some examples, the z-direction may be illustrative of a direction perpendicular to a surface of a substrate (e.g., a surface in an xy-plane, a surface upon or over which other materials may be deposited, a surface of a semiconductor chip or wafer), and each of the structures, illustrated by their respective cross section in an xz-plane, may extend for some distance (e.g., length) in the y-direction. The transistor structure200illustrates an example of a transistor channel, electrically coupled between a terminal270-a-1and a terminal270-a-2, that may include one or more doped portions240of the semiconductor material220. In various examples, one of the terminals270-a-1or270-a-2may be referred to as a source terminal, and the other of the terminals270-a-1or270-a-2may be referred to as a drain terminal, where such a designation may be based on a configuration or relative biasing of a circuit that includes the transistor structure200. The channel (e.g., the channel portion) of the transistor may include or refer to one or more portions of the transistor structure200that are operable to open or close a conductive path (e.g., to modulate a conductivity, to form a channel, to open a channel, to close a channel) between a source and drain (e.g., between the terminal270-a-1and the terminal270-a-2) based at least in part on a voltage of a gate (e.g., a gate terminal, a gate portion250). In other words, a channel portion of a transistor structure may be configured to be activated, deactivated, made conductive, or made non-conductive, based at least in part on a voltage of a gate portion, such as gate portion250. In some examples of transistor structure200(e.g., a planar transistor arrangement), the channel portion formed by one or more doped portions240of the semiconductor material220may support a conductive path in a generally horizontal or in-plane direction (e.g., along the x-direction, within an xy-plane, in a direction within or parallel to a surface of a substrate). In some examples, the gate portion250may be physically separated from the channel portion (e.g., separated from the semiconductor material220, separated from one or more of the doped portions240) by a gate insulation portion260(e.g., a gate dielectric). Each of the terminals270-amay be in contact with or otherwise coupled with (e.g., electrically, physically) a respective doped portion240-a, and each of the terminals270-aand the gate portion250may be formed from an electrically conductive material such as a metal or metal alloy, or a polycrystalline semiconductor (e.g., polysilicon). In some examples, the transistor structure200may be operable as an n-type or n-channel transistor, where applying a relatively positive voltage to the gate portion250that is above a threshold voltage (e.g., an applied voltage having a positive magnitude, relative to a source terminal, that is greater than a threshold voltage) activates the channel portion or otherwise enables a conductive path between the terminals270-a-1and270-a-2(e.g., along a direction generally aligned with the x-direction within the semiconductor material220). In such examples, the doped portions240-amay refer to portions having n-type doping or n-type semiconductor, and doped portion240-bmay refer to portions having p-type doping or p-type semiconductor (e.g., a channel portion having an NPN configuration along the x-direction or channel direction). In some examples, the transistor structure200may be operable as a p-type or p-channel transistor, where applying a relatively negative voltage to the gate portion250that is above a threshold voltage (e.g., an applied voltage having a negative magnitude, relative to a source terminal, that is greater than a threshold voltage) activates the channel portion or otherwise enables a conductive path between the terminals270-a-1and270-a-2. In such examples, the doped portions240-amay refer to portions having p-type doping or p-type semiconductor, and doped portion240-bmay refer to portions having n-type doping or n-type semiconductor (e.g., a channel portion having a PNP configuration along the x-direction or channel direction). In some examples, circuitry operable to support access operations on memory cells105(e.g., a row component125, a column component135, a plate component145, a sense component150, a memory controller170, or various combinations thereof) may be formed at least in part by respective sets of transistors each having the arrangement of the transistor structure200, where each of the transistors may have a channel portion formed by respective doped portions240of the semiconductor material220. Some examples of such an arrangement may be implemented in a CMOS configuration, which may refer to various examples of a complementary and symmetrical pair of a p-type transistor and an n-type transistor (e.g., for logic functions). In some examples, such transistors may leverage a crystalline arrangement of the semiconductor material220(e.g., a single crystalline arrangement) for various performance characteristics or manufacturing characteristics of such a material or an arrangement. For example, at least the doped portions240of a given transistor (e.g., doped portions240-a-1,240-b, and240-a-2) may be collectively formed from a single crystal grain or other continuous atomic arrangement of the semiconductor material220(e.g., with relatively few or no grain boundaries or other discontinuities within at least the adjacent, contacting, or otherwise cooperative doped portions240). However, in some examples, such structures or arrangements of transistors may be limited by an available area of a crystalline substrate (e.g., a crystalline structure of a chip or wafer underneath a memory array110or stack of levels or decks of memory arrays110). In accordance with examples as disclosed herein, a memory device100may include upper circuitry (e.g., transistors of the upper circuitry) formed at least in part by a semiconductor material220that is deposited over one or more decks of memory cells105and formed in a crystalline arrangement based on heating and cooling of the deposited semiconductor material220. The semiconductor material220may be deposited at least in part into tapered cavities that are etched into one or more dielectric or oxide materials, where the tapering may promote nucleation of the crystalline arrangement at a respective single location (e.g., at a bottom end of the respective cavity), rather than multiple nucleation locations that may result in a polycrystalline or multi-grain arrangement. The doped portions240of the upper circuitry transistors may be formed at least in part by doping regions of the single crystalline arrangement (e.g., single crystal grain or other continuous atomic arrangement of the semiconductor material) of the deposited semiconductor material220. In some examples, such techniques may be leveraged for operating the one or more decks of memory cells105using a combination of lower circuitry, which may be formed at least in part by doped portions of a crystalline semiconductor substrate (e.g., a crystalline chip or wafer), and upper circuitry, which may be formed at least in part by doped portions of a semiconductor deposited over the one or more decks and formed with a crystalline arrangement in-situ. FIG.3illustrates an example of a memory device300that supports single-crystal transistors for memory devices in accordance with examples as disclosed herein. The memory device300may be an example of a memory device100described with reference toFIG.1, and may include multiple levels of semiconductor circuitry (e.g., transistor circuitry, CMOS circuitry) for accessing and operating multiple decks or levels of memory arrays110-a. For illustrative purposes, aspects of the memory device300may be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system301. In some examples, the z-direction may be illustrative of a direction perpendicular to a surface of a substrate (e.g., a surface in an xy-plane, a surface upon or over which other materials may be deposited), and each of the related regions, illustrated by their respective cross-section in an xz-plane, may extend for some distance along the y-direction. In some examples, the x-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells105), and the y-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells105), or vice versa. Each of the illustrative regions of the memory device300may be associated with a region of components or circuitry that may be formed using various techniques. In some examples, functional components such as transistors in various configurations or arrangements within the illustrative regions may be interconnected by routing conductors (e.g., metal conductors) of the respective regions, which may include various arrangements of through-silicon vias (TSVs) or socket conductors that may be aligned along the z-direction, or various arrangements of in-plane conductors that may be aligned in one or more directions parallel to an xy-plane, or combinations thereof. Such interconnection may be associated with signal routing, or power or voltage distribution, among other functions. The memory device300may include a lower circuitry region305, which may include first (e.g., lower) set of transistors (e.g., first transistor circuitry, first CMOS circuitry). In some cases, the first set of transistors may be substrate-based transistors (e.g., formed by doping portions of a semiconductor substrate, a crystalline silicon substrate, a crystalline semiconductor substrate, a portion of a semiconductor wafer). A substrate of the lower circuitry region305may be a base or initial substrate of the memory device300, upon which other components or circuitry are formed, and over which another upper circuitry region320may be added. In some examples, transistors of the lower circuitry region305may include transistors formed or configured in accordance with the transistor structure200, including such transistors in a CMOS arrangement. Above the lower circuitry region305, the memory device300may include a stack of decks315-a, where each deck315-amay be located at a different position along the z-direction. The memory device300illustrates an example that includes four decks315-a(e.g., decks315-a-1through315-a-4), but a memory device100in accordance with examples as disclosed herein may include any quantity of one or more decks315. Each deck315-amay include a respective memory array110-a, which may include a plurality of memory cells105that are distributed in an xy-plane. In some examples, memory cells105of a memory array110-amay be arranged in rows that are aligned along the x-direction and columns that are aligned along the y-direction. Each of the memory arrays110-amay include respective word lines120(e.g., along the x-direction), digit lines130(e.g., along the y-direction), and plate lines140(e.g., where applicable) for accessing the respective memory cells105, among other circuitry. The memory arrays110-aof the memory device300may include memory cells105in accordance with various memory architectures. In some examples, memory cells105of a memory array110-amay each include a respective storage component (e.g., a capacitor) and a respective cell selection component (e.g., a cell selection transistor). In some examples (e.g., in an FeRAM application), capacitors of the memory cells105may be ferroelectric capacitors operable to store a charge or polarization corresponding to a logic state. A ferroelectric material used in a ferroelectric capacitor may be characterized by an electric polarization where the material maintains a non-zero electric charge in the absence of an electric field. In some examples, memory cells105of the memory arrays110-amay include storage elements of different memory architectures, such as linear capacitors (e.g., in a DRAM application), transistors (e.g., in a NAND application, in an SRAM application), or material memory elements (e.g., in a RRAM application or a PCM application, which may include chalcogenide storage elements, resistive storage elements, thresholding storage elements), among other types of storage elements. In some examples, the decks315-amay include various transistors, such as cell selection transistors of or associated with the memory cells105of the respective memory arrays110-a, among other examples. Transistors of the decks315-amay be formed in accordance with various thin film manufacturing techniques, including deposition of polycrystalline semiconductor materials (e.g., polysilicon) over the lower circuitry region305. In some examples, transistors of the decks315-amay include vertical transistors, which may support a respective channel formed at least in part along the z-direction. Above the decks315-a, the memory device300may include an upper circuitry region320, which may include second (e.g., upper) set of transistors (e.g., second transistor circuitry, second CMOS circuitry). The second set of transistors may be formed at least in part by a semiconductor material220of the upper circuitry region320that is deposited over the decks315-a, and that has been heated and cooled to form one or more portions of the semiconductor material220in a crystalline arrangement (e.g., a single crystal grain or other continuous atomic arrangement of the semiconductor material220that supports the formation of at least one transistor). In some examples, the semiconductor material220may be deposited at least partially in tapered cavities, etched or otherwise formed in a dielectric portion deposited over the decks315-a(e.g., in the upper circuitry region320), where the tapering may facilitate nucleation of the single crystalline arrangement. The second set of transistors of the upper circuitry region320may be formed by doping portions of the semiconductor material220in the single crystalline arrangement. In some examples, transistors of the upper circuitry region320may include transistors formed or configured in accordance with the transistor structure200, including such transistors in a CMOS arrangement. Above the upper circuitry region320, the memory device300may include an I/O circuitry region350, which may include circuitry to route signals for communication with a host device coupled to the memory device300, among other signals. For example, the I/O circuitry region350may include one or more pads360-a(e.g., pads360-a-1through360-a-n, conductive interfaces) that support various coupling or electronic communication between the memory device300and a host device (e.g., for signaling associated with read or write commands, among other signaling). In some examples, the pads360-amay be associated with signaling of one or more channels (e.g., data channels, control channels) for communicating information, commands, or diagnostic information between the memory device300and a host device. In some examples, the pads360-amay be configured for supplying power or voltages to various components of the memory device300, among other purposes. The I/O circuitry region350may include various circuitry for communicating signals with both the upper circuitry region320and the lower circuitry region305. In some examples, the memory device300may include a backend interconnect region330above the lower circuitry region305, which may support interconnection between the lower circuitry region305and the upper circuitry region320, or interconnection between the lower circuitry region305and the I/O circuitry region350, or both. The memory device300may use circuitry of the lower circuitry region305and the upper circuitry region320to access and operate memory cells105of the memory arrays110-a. In some examples, circuitry of the lower circuitry region305, or circuitry of the upper circuitry region320, or both may include circuitry for performing sense operations, circuitry for performing access operations, circuitry for performing decoding operations, or circuitry for performing I/O operations, or a combination thereof, among other operations. For example, circuitry of the lower circuitry region305, or circuitry of the upper circuitry region320, or both may include one or more portions of a row component125, a column component135, or a plate component145, such as decoders, buffers, multiplexers, or drivers (e.g., word line drivers, sub-word line drivers, digit line drivers, sub-digit line drivers, plate line drivers, sub-plate line drivers, among other drivers), among other circuitry configured to address, decode, or bias access lines of one or more memory arrays110-aof the memory device300. Additionally or alternatively, circuitry of the lower circuitry region305, or circuitry of the upper circuitry region320, or both may include one or more portions of a sense component150, such as one or more sense amplifiers, or one or more signal development components, among other circuitry for sensing or writing to memory cells105of the memory device300. In some examples, subsets of transistors of the lower circuitry region305, or of the upper circuitry region320, or both may be dedicated or allocated for a given purpose (e.g., function, operation). For example, sensing circuitry may include a subset of transistors that are configured to support sense operations, access circuitry (e.g., row access circuitry, column access circuitry, plate access circuitry) may include a subset of transistors that are configured to support activating or biasing access lines, decoding circuitry may include a subset of transistors that are configured to support decoding operations, I/O circuitry may include a subset of transistors that are configured to support I/O operations, and so on. That is, transistors of the lower circuitry region305, or of the upper circuitry region320, or both may be divided into various subsets of transistors that each support different operations and functions of the memory device300. In some examples, one or more portions of the lower circuitry region305may be dedicated or allocated to supporting operation of some memory arrays110-aof the memory device300but not others, and one or more portions of the upper circuitry region320may be dedicated or allocated to supporting operation of some memory arrays110-aof the memory device300but not others. For example, in an example with multiple decks315-a, the decks315-amay be divided into a first set310-a(e.g., a lower set, including decks315-a-1and315-a-2) and a second set310-b(e.g., an upper set, including decks315-a-3and315-a-4). In some examples, a division of the decks315into sets310may refer to how decks315are coupled to substrate-based circuitry of the memory device300. For example, a set310-amay refer to any quantity of decks315-athat are coupled at least in part to lower substrate-based circuitry and a set310-bmay refer to any quantity of decks315-athat are coupled at least in part to upper substrate-based circuitry. Although the example of memory device300illustrates two sets310having a same quantity of decks315-a, in some examples, a memory device100may include sets310having different quantities of decks315. The components and circuitry of the memory device300may be coupled through various interconnection regions370. Each of the interconnection regions370may illustrate portions of the memory device300that support electrical coupling or interconnection along at least the z-direction between components or circuitry of the illustrated regions. For example, each interconnection region370may include various arrangements of TSVs or socket conductors that may be aligned along the z-direction. In some examples, the interconnection regions370may include various arrangements of in-plane conductors (e.g., in-plane routing between or among interconnections along the z-direction) that may be aligned in one or more directions parallel to an xy-plane, or combinations thereof. The interconnection region370-amay illustrate an example of a coupling between each of the memory arrays110-aand the lower circuitry region305and the upper circuitry region320. In some examples, the interconnection region370-amay be an example of a word line socket region which may be used to select and activate one or more word lines of each of the decks315-a,315-b,315-c, and315-d. For example, the interconnection region370-amay include interconnects that couple word lines of decks315-a-1through315-a-4to decoders (e.g., row components125) or word line drivers (e.g., sub-word line drivers) included in the lower circuitry region305, in the upper circuitry region320, or both. Although the interconnection region370-aillustrates coupling between the memory arrays110-aand both the lower circuitry region305and the upper circuitry region320, in some examples, an interconnection region370-amay be implemented for coupling between the memory arrays110-aand one of the lower circuitry region305or the upper circuitry region320, but not both (e.g., in examples where CMOS or other circuitry of a row component125, common to all of the memory arrays110-a, is located in one of the lower circuitry region305or the upper circuitry region320). The interconnection regions370-bmay illustrate examples of a coupling between memory arrays110-aof a set310and one of the lower circuitry region305or the upper circuitry region320. In some examples, interconnection regions370-bmay be examples of a digit line socket region, which may be used to select and activate one or more digit lines of the decks315-a. For example, the memory device300may include an interconnection region370-b-1that couples digit lines of decks315-a-1and315-a-2of the set310-ato decoders (e.g., column components135), digit line drivers (sub-digit line drivers), sense amplifiers, or a combination thereof, of the lower circuitry region305. In some examples, the memory device300may include an interconnection region370-b-2that includes interconnects that couple digit lines of decks315-a-3and315-a-4of the set310-bto such circuitry of the upper circuitry region320. The interconnection region370-cmay illustrate an example of a coupling between the lower circuitry region305and the upper circuitry region320. For example, the upper circuitry region320may include pad logic or other CMOS circuitry associated with functionality for all of decks315-a-1through315-a-4, which may be coupled with decks315-a-1and315-a-2via the interconnection region370-cand via the lower circuitry region305. Locating such pad logic or other shared CMOS circuitry in the upper circuitry region320may provide favorable proximity to components or circuitry of the I/O circuitry region350, or may reduce area utilization of a substrate (e.g., a chip or wafer associated with the lower circuitry region305) for favorable scaling or routing flexibility, or both, among other advantages. The interconnection region370-dmay illustrate an example of a coupling between the lower circuitry region305and the I/O circuitry region350, and the interconnection region370-emay illustrate an example of an interconnection between the upper circuitry region320and the I/O circuitry region350. By including both the lower circuitry region305and the upper circuitry region320, the memory device300may support a distribution of transistor circuitry for accessing and operating a stack or multiple decks315-abetween multiple regions or levels of crystalline semiconductor, which may reduce the area or footprint of a substrate (e.g., a chip or wafer) that is occupied by such circuitry. A distribution of circuitry between such regions may enable greater scaling of the memory device300(e.g., using a greater quantity of decks315-a) within a given area or footprint. Moreover, in some examples, pad logic or other circuitry associated with both the lower set310-aand the upper set310-bmay be included in the upper circuitry region320(e.g., rather than being distributed between the upper circuitry region320and the lower circuitry region305, or included entirely in the lower circuitry region305), which may support allocating more of a lower substrate for other purposes, such as interconnect circuitry that supports an increased quantity of decks315-a. FIGS.4A through4Cillustrate examples of operations that support forming single-crystal transistors for memory devices in accordance with examples as disclosed herein. For example,FIGS.4A through4Cmay illustrate aspect of a sequence of operations for fabricating a material layout400, which may be a portion of a memory device (e.g., a memory device100, a memory device300, a memory die), such as a portion of an upper circuitry region320described with reference toFIG.3. However, the described techniques may be implemented to support fabricating other portions of a memory device, or other types of semiconductor apparatuses (e.g., semiconductor dies) that include forming crystalline atomic arrangements of a semiconductor material that is deposited over a substrate. Each of the figures may be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system410. Operations illustrated in and described with reference toFIGS.4A through4Cmay be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations such as deposition or bonding, subtractive operations such as etching, trenching, planarizing, or polishing, and supporting operations such as masking, photolithography, or aligning, among other operations that support the described techniques. FIG.4Aillustrates a first portion of the material layout400after a first set of manufacturing operations, including aspects of a dielectric material415-aand a dielectric material415-b. In some examples, the dielectric material415-aand the dielectric material415-bmay be deposited over one or more arrays of memory cells105(e.g., in an upper circuitry region320). In some examples, the dielectric material415-amay include an oxide material (e.g., where the dielectric material415-ais an oxide, such as an oxide of silicon) and the dielectric material415-bmay include a nitride material (e.g., where the dielectric material415-bis a nitride, such as a nitride of silicon). Although two dielectric materials415are illustrated, a material layout in accordance with the described techniques may include any quantity of one or more layers of dielectric material415, which may include multiple layers of a same material, or layers of two or more different materials, or both. The dielectric materials415may be associated with a thermal conductivity, which may be leveraged to manage heat transfer (e.g., heat transfer rate, heat transfer direction) through the material layout400to support preferential nucleation of a crystalline semiconductor arrangement. In the example of material layout400, the dielectric material415-amay be associated with a first thermal conductivity and the dielectric material415-bmay be associated with a second thermal conductivity. In some examples, the second thermal conductivity may be less than the first thermal conductivity, which may encourage heat transfer along a downward direction through the material layout400. In some examples, one or more dielectric materials415may be deposited over or around a metal portion405(e.g., of an upper circuitry region320, of a deck315). The metal portion405may be an access line of a deck315or an upper circuitry region320, or a portion of an interconnection region370, such as a coupling between an upper circuitry region320and a deck315. In some examples, a metal portion405also may be leveraged to manage heat transfer (e.g., heat transfer rate, heat transfer direction) through the material layout400to support preferential nucleation of a crystalline semiconductor arrangement. In some examples, such a configuration may include not aligning the metal portion405directly underneath the cavities420(e.g., along the z-direction), which may support a relatively slower heat transfer from a semiconductor material that is deposited in the cavities420. The dielectric material415-amay be deposited over (e.g., in contact with) the metal portion405, and the dielectric material415-bmay be deposited over the dielectric material415-a. In some examples, a metal portion405may be omitted, or may be otherwise negligible in the processing in the material layout400. Each of the dielectric materials415may be associated with a respective thickness (e.g., along the z-direction), which may be selected or defined to support characteristics of the material layout400. In some examples, the dielectric material415-a(e.g., an oxide) may have a thickness between 100 and 500 nanometers (e.g., approximately 300 nanometers), and the dielectric material415-b(e.g., a nitride) may have a thickness between 20 and 100 nanometers (e.g., approximately 60 nanometers). In examples that include a single dielectric material415(e.g., a single layer), a thickness of the single dielectric material415may be similar to a total thickness of the dielectric materials415-aand415-b, such as having a thickness between 100 and 600 nanometers (e.g., 360 nanometers). As illustrated in the material layout400, cavities420may be etched or otherwise formed in the one or more dielectric materials415. Each of the cavities420may extend through at least a portion of the dielectric materials415(e.g., corresponding to a depth of the cavities along the z-direction). In the example of material layout400, the cavities420may extend through the entire depth of the dielectric material415-band a portion of the dielectric material415-a. In examples where a material layout includes a single dielectric material415, cavities420may extend a similar depth, but may not extend through an entire thickness of the single dielectric material415. In some examples, the depth of the cavities420may be between100and300nanometers. Each of the cavities420may be separated from adjacent cavities by a separation distance (e.g., along the x-direction, along the y-direction, in an xy-plane), which may refer to a centerline distance (e.g., between centerlines along the z-direction), or a minimum separation distance (e.g., in an xy-plane, at a top surface of the dielectric material415-b. For example, the cavity420-amay be separated from the cavity420-bby a distance between 0.5 and 1.5 micrometers (e.g., 1 micrometer). Each of the cavities420may be tapered along the z-direction, which may refer to various examples of a reduction in cross-sectional dimension (e.g., width along the x-direction, along the y-direction, or both) or area (e.g., in an xy-plane) of a cavity420from an opening of the cavity420to a bottom of the cavity420(e.g., along a negative z-direction). In some examples, such a configuration may include or be referred to as having a taper toward a point, such as a taper having a conical or pyramidal shape, or a partial conical or pyramidal shape (e.g., a frustum). Although a cavity420may include a taper toward a point, a bottom of the cavity420may not reach an explicit point or singularity, and may have a degree of rounding or otherwise non-zero cross sectional area at the bottom of the cavity420. In some examples, each cavity420may have a first cross-sectional area (e.g., at the top surface of the dielectric material415-b, at an opening of the cavity420) with a width (e.g., along the x-direction, along the y-direction) or a diameter (e.g., in an xy-plane) between 20 and 200 nanometers. In some examples, each cavity420may have a second cross-section area (e.g., opposite an opening of the cavity420, at or near a bottom of cavity420) with a width or diameter that is less than or equal to a threshold dimension, such as being less than or equal to 10 nanometers, or less than or equal to 7 nanometers, among other threshold dimensions. In some examples, a taper of a cavity420may be expressed as a ratio of cross-sectional areas or widths, including such ratios between a first cross-sectional area (e.g., at a top surface of the dielectric material415-b) and a second cross-sectional area that is smaller than the first cross-sectional area (e.g., opposite the first cross-sectional area, at or near a bottom of the cavity420). For example, a taper of a cavity420may be associated with a lower cross-section having an area or width that is less than 50% of the corresponding dimension of an upper cross-section, or less than 30% of the corresponding dimension of an upper cross-section. In some examples, a taper of a cavity420may be expressed as an angle relative to the z-axis, or an included angle of the cavity420, such as a cavity420having an included angle between 25 degrees and 75 degrees (e.g., between 35 and 55 degrees). In some examples, the cavities420may taper uniformly, or uniformly within a threshold (e.g., related to a surface roughness or irregularity), from an opening of the cavity420. For example, the cavities420may be described as being at least partially v-shaped, conical, or pyramidal. In some examples, the cavities420may extend through at least a portion of one or more dielectric materials415without tapering, and then taper along the z-direction from the first cross-section to the second, smaller, cross-section. For example, a top section of a cavity420may be substantially cylindrical and a bottom portion of the cavity420may be substantially conical (e.g., for a zero or near-zero second cross-section) or partially conical (e.g., as a frustum, for a cross section with a non-negligible width dimension). FIG.4Billustrates a second portion of the material layout400after a second set of manufacturing operations, including aspects of a semiconductor material425and an optional dielectric material415-cthat may be deposited over the dielectric materials415-aand415-b. The semiconductor material425may be deposited in the cavities420, and above the dielectric material415-b(e.g., with a thickness dimension above a surface of the dielectric material415-balong the z-direction). For example, a thickness of the semiconductor materials425may be between 50 and 100 nanometers above the top surface of the dielectric material415-b(e.g., between 60 and 80 nanometers). In some examples, the semiconductor materials425may be formed by depositing a semiconductor layer (e.g., comprising the semiconductor materials425) in contact with the top surface of the dielectric material415-b. In such examples, the semiconductor materials425-aand425-bmay be formed by etching portions of the semiconductor layer to expose a top surface of the dielectric material415-b. In another example, the semiconductor materials425may be formed by depositing a masking material in a pattern and depositing the semiconductor materials425in openings of the masking. In some examples, the masking material may be removed to expose the top surface of the dielectric material415-bbetween the semiconductor materials425. The semiconductor materials425may be deposited without a particular atomic arrangement, such as depositing the semiconductor materials425with an amorphous or polycrystalline arrangement. In some examples, after forming the semiconductor materials425, the dielectric material415-cmay optionally be deposited over the semiconductor materials425and the dielectric material415-b. In some cases, the dielectric material415-cmay include a tetraethoxysilane material. FIG.4Cillustrates a third portion of the material layout400after a third set of manufacturing operations, including aspects of converting the deposited semiconductor materials425into single crystalline semiconductor materials430. In some examples, such a conversion may be supported by a heating and cooling (e.g., annealing) of each of the deposited semiconductor materials425to form the semiconductor with respective crystalline (e.g., single crystal) arrangements. In some cases, heating of the material layout400may be provided by applying a laser to the semiconductor materials425or the dielectric material415-c(e.g., where applicable). In some examples, a laser may be applied with a single pulse (e.g., over a single duration). For example, a laser having a wavelength between 400 and 700 nanometers (e.g., 532 nanometers) may be applied for a duration that is between 5 and 100 nanoseconds. In some examples, a laser may be applied with multiple pulses. For example, a laser having a wavelength between 150 and 450 nanometers (e.g., between 250 and 350 nanometers) may be applied for a quantity of pulses each having a duration between 50 and 250 nanoseconds. In some examples, a duration for applying a laser to the semiconductor materials425may be between 10 nanoseconds and 1 microsecond. According to these and other examples, applied heating may cause each of the semiconductor materials425to melt, and the molten semiconductor materials425may cool to form respective single crystalline semiconductor materials430. During the cooling, the respective crystalline arrangements may nucleate at each of the nucleation sites435, which may be located at the bottom of the tapered cavities420. Such nucleation sites435may be configured or otherwise encouraged based at least in part on heat transfer through the material layout400(e.g., with heat flowing downward through the material layout400, based at least in part on heating being applied at an upper portion of the semiconductor materials425and insulative properties of one or more dielectric materials415), such that locations of the molten semiconductor materials425near nucleation sites435may be associated with a relatively lower temperature than other locations of the melted semiconductor materials425. Accordingly, nucleation sites435may be relatively more-likely to be associated with an initiation of an ordering of an atomic arrangement, and such an atomic arrangement may grow along the positive z-direction (e.g., with a vertically upward crystallization growth through the cavities. Having a relatively small cross-section at the bottom of the cavities420(e.g., less than or equal to a threshold dimension, a taper towards a point) may increase a likelihood that nucleation begins at a single location, rather than having multiple nucleation sites in each cavity420. Growth of the single crystalline arrangement may continue to spread through the semiconductor materials425, including a lateral growth (e.g., along the x-direction, along the y-direction) as a boundary between crystalline and molten portions extends beyond a top surface of the dielectric material415-b. The growth of the crystalline arrangement may be supported by relatively slow cooling of the molten semiconductor material425, which may include maintaining a chuck or other fixturing, or a chamber or other ambient environment, or both at a controlled temperature that may be relatively high, but lower than a temperature of the molten semiconductor materials425(e.g., supporting heat flux in a downward direction through the semiconductor materials425). Each of the single crystalline semiconductor materials430may be used to form one or more transistors, such as transistors in accordance with the transistor structure200, which may include various techniques of doping the single crystalline semiconductor materials430. For example, each of the single crystalline semiconductor materials430may be an example of a respective semiconductor material220, and may be doped to form one or more doped portions240. In examples of the material layout400that omit the dielectric material415-c, the single crystalline semiconductor materials430may expand beyond an original volume of the respective semiconductor materials425. In such examples, the single crystalline semiconductor materials430may be etched, polished, or planarized before doping operations to form one or more transistors. In examples of the material layout400that include the dielectric material415-c, the dielectric material415-cmay be removed partially or entirely (e.g., using a chemical mechanical polishing (CMP) process) before doping operations to form one or more transistors. FIGS.5A through5Fillustrate examples of operations that support forming single-crystal transistors for memory devices in accordance with examples as disclosed herein. For example,FIGS.5A through4Fmay illustrate aspect of a sequence of operations for fabricating a material layout500, which may be a portion of a memory device (e.g., a memory device100, a memory device300, a memory die), such as a portion of an upper circuitry region320described with reference toFIG.3. However, the described techniques may be implemented to support fabricating other portions of a memory device, or other types of semiconductor dies that include forming crystalline atomic arrangements of a semiconductor material that is deposited over a substrate. Each of the figures may be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system510. Operations illustrated in and described with reference toFIGS.5A through5Fmay be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations such as deposition or bonding, subtractive operations such as etching, trenching, planarizing, or polishing, and supporting operations such as masking, photolithography, or aligning, among other operations that support the described techniques. FIG.5Aillustrates a first portion of the material layout500after a first set of manufacturing operations, which may be similar to aspects of the first portion of the material layout400described with reference toFIG.4A. For example, the first portion of the material layout500may include a dielectric material515-aand a dielectric material515-b, which may be deposited over one or more arrays of memory cells105(e.g., in an upper circuitry region320) or in another portion of semiconductor die. In some examples, the dielectric material515-amay include an oxide material (e.g., an oxide of silicon having a thickness between 300 and 500 nanometers) and the dielectric material515-bmay include a nitride material (e.g., a nitride of silicon having a thickness between 20 and 60 nanometers). Although two dielectric materials515are illustrated, a material layout in accordance with the described techniques may include any quantity of one or more layers of dielectric material515, which may include multiple layers of a same material, or layers of two or more different materials, or both. As illustrated in the material layout500, cavities520may be etched or otherwise formed in the one or more dielectric materials515, and may have one or more characteristics similar to those described with reference to the cavities420of the material layout400. For example, each of the cavities520may include a taper along the z-direction (e.g., toward a point), which may refer to various examples of a reduction in cross-sectional dimension or area of a cavity520from an opening of the cavity520to a bottom of the cavity520. The example of cavities520include a first cross section (e.g., an upper cross section having a width or diameter between 20 and 100 nanometers) that is constant (e.g., cylindrical, prismatic) from a location at the opening to some distance into the one or more dielectric materials515(e.g., through the dielectric material515-band a portion of the thickness of the dielectric material515-a), with a taper being below the first cross section (e.g., beginning at a location along the z-direction that is below an upper surface of the dielectric material515-b). In some examples, the cavities520may have an opening diameter between 20 and 100 nanometers, and an overall depth between 100 and 300 nanometers. In some examples, the cavities520may be associated with a pitch dimension (e.g., distance of repetition along the x-direction, along the y-direction, or both, a distance between the cavity520-aand the cavity520-b) between 40 nanometers and 1 micrometer. FIG.5Billustrates a second portion of the material layout500after a second set of manufacturing operations, which may be similar to aspects of the second portion of the material layout400described with reference toFIG.4B. For example, semiconductor materials525may be deposited in the cavities520, and above the dielectric material515-b(e.g., with a thickness dimension above a surface of the dielectric material515-bbeing between 200 and 800 nanometers). In various examples, the deposited semiconductor materials525may include amorphous or polycrystalline silicon which, in the example of material layout500, may be provided for the purpose of seeding respective crystalline arrangements. In some examples, the semiconductor materials525, or a portion thereof (e.g., a portion above the dielectric material515-b) may be patterned into islands which may be twenty percent smaller than the pitch dimension, among other percentages. FIG.5Cillustrates a third portion of the material layout500after a third set of manufacturing operations, including aspects of converting the deposited semiconductor materials525into single crystalline semiconductor materials530. In some examples, such a conversion may be supported by a heating and cooling (e.g., melting and annealing) of the deposited semiconductor materials525to form the semiconductor with respective crystalline (e.g., single crystal) arrangements. In some cases, heating of the material layout500may be provided by applying a laser to the semiconductor materials525, which may be selected or defined according to low temperature circuit applications (e.g., to avoid or mitigate thermal degradation of components below the dielectric material515-a). For example, a laser may be applied with a wavelength between 250 and 350 nanometers (e.g., 308 nanometers) for multiple pulses each having a duration of 160 nanoseconds, or a laser may be applied with a wavelength between 500 and 600 nanometers (e.g., 532 nanometers) for a single pulse having a duration between 13 and 60 nanoseconds, among other configurations. In some examples, a duration for applying a laser to the semiconductor materials525may be between 10 nanoseconds and 1 microsecond. Applying the laser may melt the semiconductor materials525to the bottom of the cavities520, which may be followed by a relatively slow cooling to facilitate the formation of relatively large crystalline grains (e.g., as initiated at nucleation sites535). In some examples, the formation of the crystalline arrangement may force a protrusion of the single crystalline semiconductor materials530to form humps (e.g., along the positive z-direction). In some examples, as a crystalline structure aligns in a particular direction, is may reveal structures resembling a single crystal (e.g., where a structure at 120 degrees may align with a 111 direction of the crystalline arrangement). FIG. D illustrates a fourth portion of the material layout500after a fourth set of manufacturing operations, including aspects of forming a flat surface on top of the single crystalline semiconductor materials530. For example, respective portions of the single crystalline semiconductor materials530may be removed by performing a CMP process, a multi-layer resist (MLR) process, a dry etching process, or a polishing process, among other techniques. In some examples, such processes may also include removing the dielectric material515-b. In some examples, the remaining portion of the single crystalline semiconductor material530illustrated by the fourth portion may provide a seed material for subsequent growth of crystalline structures. FIG.5Eillustrates a fifth portion of the material layout500after a fifth set of manufacturing operations, including aspects of depositing a semiconductor material545over the remaining portions of the single crystalline semiconductor material530of the fourth portion. The semiconductor material545may be deposited without a particular atomic arrangement, such as depositing the semiconductor material545with an amorphous or polycrystalline arrangement (e.g., with a thickness between 60 and 80 nanometers, among other thicknesses). In various examples, the semiconductor material545may be a same material as the semiconductor materials525, or the semiconductor material545may be a different material than the semiconductor materials525. FIG.5Fillustrates a sixth portion of the material layout500after a sixth set of manufacturing operations, including aspects of converting the deposited semiconductor material545into respective single crystalline semiconductor materials550(e.g., single crystalline semiconductor materials550-aand550-b). In some examples, such a conversion may be supported by a heating and cooling (e.g., melting and annealing) of the deposited semiconductor material545to form the semiconductor with respective crystalline (e.g., single crystal) arrangements, which may leverage aspects of a liquid-phase epitaxy. In some cases, heating of the material layout500may be provided by applying a laser to the semiconductor material545(e.g., to melt the semiconductor material545). Such melting may leverage a characteristic where an amorphous or polycrystalline arrangement of the semiconductor material545may have a lower melting temperature than the crystalline arrangements of the single crystalline semiconductor materials530-aand530-b. Based at least in part on such characteristics, applying the laser to the semiconductor material545may target melting the amorphous semiconductor material and leverage the single crystalline semiconductor materials530-aand530-bto grow relatively large grains (e.g., as initiated at nucleation sites555-aand555-b, which may refer to interfacing surfaces between the single crystalline semiconductor materials530-aand530-band the semiconductor material545. In some examples, germanium may be deposited as well (e.g., as at least a portion of the semiconductor material545, or as a layer on top of the semiconductor material545), which may support forming high-grade silicon germanium (e.g., in a crystalline atomic arrangement). In some examples, growth of a crystalline arrangement may be initiated at respective nucleation sites555, and proceed upward along the positive z-direction and laterally in an xy-plane to form respective single crystalline semiconductor materials550associated with each of the single crystalline semiconductor materials530(e.g., single crystalline semiconductor material550-agrown from or seeded by the single crystalline semiconductor material530-a, single crystalline semiconductor material550-bgrown from or seeded by the single crystalline semiconductor material530-b). Uniformly growing grains may converge at isolation locations, such as a convergence at a separation line560. Each of the single crystalline semiconductor materials550may be used to form one or more transistors, such as transistors in accordance with the transistor structure200, which may include various techniques of doping the single crystalline semiconductor materials550. For example, each of the single crystalline semiconductor materials550may be an example of a respective semiconductor material220, and may be doped to form one or more doped portions240. In some examples, separation lines560, and adjacent portions of the single crystalline semiconductor materials550, may be removed and replaced with isolation features during die fabrication (e.g., to form one or more transistors from the single crystalline semiconductor materials550), which may support forming circuitry using relatively high quality semiconductor (e.g., for doped portions240that do not include grain boundaries, such as the separation line560). FIGS.6A through6Fillustrate examples of operations that support forming single-crystal transistors for memory devices in accordance with examples as disclosed herein. For example,FIGS.6A through6Fmay illustrate aspect of a sequence of operations for fabricating a material layout600, which may be a portion of a memory device (e.g., a memory device100, a memory device300, a memory die), such as a portion of an upper circuitry region320described with reference toFIG.3. However, the described techniques may be implemented to support fabricating other portions of a memory device, or other types of semiconductor dies that include forming crystalline atomic arrangements of a semiconductor material that is deposited over a substrate. Each of the figures may be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system510. Operations illustrated in and described with reference toFIGS.6A through6Fmay be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations such as deposition or bonding, subtractive operations such as etching, trenching, planarizing, or polishing, and supporting operations such as masking, photolithography, or aligning, among other operations that support the described techniques. FIG.6Aillustrates a first portion of the material layout600after a first set of manufacturing operations, which may be similar to aspects of the first portion of the material layout400described with reference toFIG.4A. For example, the first portion of the material layout500may include a dielectric material615-aand a dielectric material615-b, which may be deposited over one or more arrays of memory cells105(e.g., in an upper circuitry region320) or in another portion of semiconductor die. In some examples, the dielectric material615-amay include an oxide material (e.g., an oxide of silicon having a thickness between 300 and 500 nanometers) and the dielectric material615-bmay include a nitride material (e.g., a nitride of silicon having a thickness between 20 and 60 nanometers). Although two dielectric materials615are illustrated, a material layout in accordance with the described techniques may include any quantity of one or more layers of dielectric material615, which may include multiple layers of a same material, or layers of two or more different materials, or both. As illustrated in the material layout600, cavities620may be etched or otherwise formed in the one or more dielectric materials615, and may have one or more characteristics similar to those described with reference to the cavities420of the material layout400. For example, each of the cavities620may include a taper along the z-direction (e.g., toward a point), which may refer to various examples of a reduction in cross-sectional dimension or area of a cavity620from an opening of the cavity620to a bottom of the cavity620. In some examples, the cavities620may have an opening diameter between 20 and 100 nanometers, and an overall depth between 100 and 300 nanometers. In some examples, the cavities520may be associated with a pitch dimension (e.g., distance of repetition along the x-direction, along the y-direction, or both, a distance between the cavity520-aand the cavity520-b) between 40 nanometers and 1 micrometer. FIG.6Billustrates a second portion of the material layout600after a second set of manufacturing operations, which may include aspects of a seeding material640(e.g., a seed layer) deposited over the dielectric materials615. In some examples, the seeding material640may include nickel, which may support aspects of metal-induced semiconductor crystallization. In some examples, the seeding material640may include silicon-germanium, amorphous silicon, a metal silicide, or polysilicon, among other seeding materials. FIG.6Cillustrates a third portion of the material layout600after a third set of manufacturing operations, which may include aspects of removing a portion of the seeding material640. For example, the seeding material640may be recessed such that each cavity620is at least partially filled with the seeding material640, such that remaining portions of the seeding material (e.g., seeding material640-aand640-b) may be within a tapered region of the cavities620. FIG.6Dillustrates a fourth portion of the material layout600after a fourth set of manufacturing operations, including aspects of a semiconductor material625deposited over the dielectric materials615and remaining seeding materials640-aand640-b. In some examples, the deposition of the semiconductor material625may be similar to aspects of the deposition of the semiconductor materials425,525, or545described with reference toFIGS.4B,5B, and5E. For example, the semiconductor material625may be deposited without a particular atomic arrangement, such as depositing the semiconductor material625with an amorphous or polycrystalline arrangement. In some examples, the semiconductor material625may be deposited with a thickness dimension above a surface of the dielectric material615-bbeing between 200 and 800 nanometers. FIG.6Eillustrates a fifth portion of the material layout600after a fifth set of manufacturing operations, including aspects of dividing or patterning the semiconductor material625into islands (e.g., semiconductor materials625-aand625-b). In some examples, the semiconductor material625may be patterned into islands that are twenty percent smaller than a pitch dimension between cavities620, among other percentages. In some examples, after forming the semiconductor materials625-aand625-b, a dielectric material615-cmay optionally be deposited over the semiconductor materials625-aand625-band the dielectric material615-b, which may encapsulate structures, reduce or eliminate interference or contamination from a chamber environment, or help to control heat transfer, among other benefits. In some cases, the dielectric material415-cmay include a tetraethoxysilane material or an oxide material. FIG.6Fillustrates a sixth portion of the material layout600after a sixth set of manufacturing operations, including aspects of converting the portions of deposited semiconductor material625into respective single crystalline semiconductor materials630(e.g., single crystalline semiconductor materials630-aand630-b). In some examples, such a conversion may be supported by a heating and cooling (e.g., melting and annealing) of the portions of deposited semiconductor material625to form the semiconductor with respective crystalline (e.g., single crystal) arrangements, which may leverage aspects of a liquid-phase epitaxy (e.g., when the seeding materials640have a different composition than the semiconductor material625) or aspects of a liquid-phase homoepitaxy (e.g., when the seeding materials640have a same composition as the semiconductor material625). In some cases, heating of the material layout600may be provided by applying a laser to the semiconductor materials625or the dielectric material615-c(e.g., where applicable). In some examples, a laser may be applied with a single pulse (e.g., over a single duration). For example, a laser having a wavelength between 400 and 700 nanometers (e.g., 532 nanometers) may be applied for a configured duration, which may include a 60-second dwell time. In some examples, a laser may be applied with multiple pulses. For example, a laser having a wavelength between 150 and 450 nanometers (e.g., between 250 and 350 nanometers, 308 nanometers) may be applied for a quantity of pulses each having a configured duration or energy (e.g., 0.4 joules, 0.5 joules, 0.6 joules). In some examples, a duration for applying a laser to the semiconductor materials625may be between 10 nanoseconds and 1 microsecond. In some examples, such melting may leverage a characteristic where an amorphous or polycrystalline arrangement of the semiconductor material625may have a lower melting temperature than the seeding material640. In some examples, growth of a crystalline arrangement may be initiated at respective nucleation sites635, and proceed upward along the positive z-direction and laterally in an xy-plane to form respective single crystalline semiconductor materials630associated with each of the seeding materials640(e.g., single crystalline semiconductor material630-aseeded by the seeding material640-a, single crystalline semiconductor material630-bseeded by the seeding material640-b). Each of the single crystalline semiconductor materials630may be used to form one or more transistors, such as transistors in accordance with the transistor structure200, which may include various techniques of doping the single crystalline semiconductor materials630. For example, each of the single crystalline semiconductor materials630may be an example of a respective semiconductor material220, and may be doped to form one or more doped portions240. In examples of the material layout600that include the dielectric material615-c, the dielectric material615-cmay be removed partially or entirely (e.g., using a chemical mechanical polishing (CMP) process) before doping operations to form one or more transistors. FIG.7illustrates an example of a transistor layout700that supports single-crystal transistors for memory devices in accordance with examples as disclosed herein. For example, the transistor layout700may be formed using additional fabrication operations performed on any of the material layouts400,500or600(e.g., as illustrated inFIGS.4C,5F, or6F). Accordingly, the transistor layout700may be illustrative of transistors that may be formed above a deck or array of memory cells105. The transistor layout700may include a dielectric material715, which may be an example of any of dielectric materials415,515, or615, and single crystalline semiconductor materials730, which may be examples of any of the single crystalline semiconductor materials430,550, or630(e.g., formed based on heating and cooling a deposited semiconductor material). The single crystalline semiconductor materials730may each include a single crystal grain (e.g., a single atomic arrangement), at least in portions of the respective single crystalline semiconductor material730that support a channel of a corresponding transistor (e.g., doped regions705or other portions of the single crystalline semiconductor material730between doped regions705that support a channel of the corresponding transistor). For example, outside a channel portion of a given transistor, the volume of a respective single crystalline semiconductor material730may include other crystalline grains, or inadvertent or otherwise insignificant grain nucleations (e.g., near a surface adjacent to dielectric material715), or other dislocations, that may not adversely affect the operation or characteristics of the given transistor. To form transistors, the transistor layout700illustrates channel portions formed at least in part by doping the single crystalline semiconductor materials730. For example, the transistor layout700may include doped regions705, which may correspond to doped portions240(e.g., doped portions240-a-1and240-a-2) described with reference to the transistor structure200ofFIG.2. In some examples, at least a portion of the single crystalline semiconductor materials730that are outside the illustrated doped regions705may also be doped, such that a boundary between a doped region705and adjacent portions of the single crystalline semiconductor materials730may correspond to a boundary between one type of doped semiconductor and another type of doped semiconductor (e.g., to form an NPN configuration or a PNP configuration). In various examples, portions of the single crystalline semiconductor materials730located in respective cavities may or may not be used to support a channel (e.g., may not be used to support electrical conductivity between terminals720), and accordingly may or may not be doped (e.g., when such portions of the single crystalline semiconductor materials730are dedicated to nucleation and grain growth). The transistor layout700may also include terminals720that may be deposited over (e.g., in contact with) the doped regions705, which may correspond to terminals270as described with reference toFIG.2). For example, the terminal720-amay be deposited over and in contact with the doped region705-aand the terminal720-bmay be deposited over and in contact with the doped region705-b, and so on. The transistor layout700may also include gate dielectric portions725, and gate conductors735that may be formed over the gate dielectric portions725, which may be examples of gate insulation portions260and gate portions250, respectively. Thus, according to these and other techniques and transistor configurations, transistor circuitry may be formed from one or more portions of a semiconductor that is formed in a crystalline arrangement by heating and cooling (e.g., melting and annealing) a semiconductor material that is deposited over a substrate, such as a semiconductor material that is deposited over an array of memory cells105. In some examples, such transistors, or channel portions thereof, may be isolated from each other by a dielectric material710. FIG.8shows a flowchart illustrating a method800that supports single-crystal transistors for memory devices in accordance with examples as disclosed herein. The operations of method800may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using special-purpose hardware. At805, the method may include forming a cavity extending through at least a portion of one or more dielectric materials, where the cavity includes a taper from a first cross-sectional area toward a point. The operations of805may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At810, the method may include depositing a semiconductor material in the cavity and above the one or more dielectric materials. The operations of810may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At815, the method may include forming the semiconductor material in a single crystalline arrangement based at least in part on heating and cooling the semiconductor material. The operations of815may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At820, the method may include forming a channel portion of a transistor based at least in part on doping the single crystalline arrangement of the semiconductor material. The operations of820may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. In some examples, an apparatus as described herein may be manufactured (e.g., fabricated) according to a method or methods, such as the method800. A system for manufacturing the apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a cavity extending through at least a portion of one or more dielectric materials, where the cavity includes a taper from a first cross-sectional area toward a point, depositing a semiconductor material in the cavity and above the one or more dielectric materials, forming the semiconductor material in a single crystalline arrangement based at least in part on heating and cooling the semiconductor material, and forming a channel portion of a transistor based at least in part on doping the single crystalline arrangement of the semiconductor material. In some examples of the method800and the system for manufacturing described herein, forming the single crystalline arrangement of the semiconductor material may include operations, features, circuitry, logic, means, or instructions for nucleating the single crystalline arrangement of the semiconductor material at a nucleation site at an end of the cavity opposite from an opening of the cavity. In some examples of the method800and the system for manufacturing described herein, heating the semiconductor material may include operations, features, circuitry, logic, means, or instructions for applying a laser to the semiconductor material. In some examples of the method800and the system for manufacturing described herein, applying the laser to the semiconductor material may include operations, features, circuitry, logic, means, or instructions for applying the laser with a wavelength between 500 and 600 nanometers, or for a single pulse having a duration between 10 nanoseconds and 1 microsecond (e.g. between 10 and 70 nanoseconds), or both. In some examples of the method800and the system for manufacturing described herein, applying the laser to the semiconductor material may include operations, features, circuitry, logic, means, or instructions for applying the laser with a wavelength between 250 and 350 nanometers, or for a set of one or more pulses each having a duration between 100 and 200 nanoseconds, or both. In some examples of the method800and the system for manufacturing described herein, a cross-sectional area of the cavity at an end opposite from an opening of the cavity may be less than 30% of a cross-sectional area of the opening of the cavity. In some examples of the method800and the system for manufacturing described herein, the taper of the cavity may be associated with an included angle that is between 35 degrees and 55 degrees. In some examples of the method800and the system for manufacturing described herein, a cross-sectional area of the cavity at an end opposite from an opening of the cavity may have a width of less than or equal to 7 nanometers. In some examples of the method800and the system for manufacturing described herein, depositing the semiconductor material may include operations, features, circuitry, logic, means, or instructions for depositing the semiconductor material with an amorphous arrangement or a polycrystalline arrangement. Some examples of the method800and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for depositing a dielectric material over the semiconductor material. In some examples, forming the semiconductor material in the single crystalline arrangement may be based at least in part on depositing the dielectric material. Some examples of the method800and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for depositing, in the cavity, a second material before depositing the semiconductor material. In some examples, forming the single crystalline arrangement of the semiconductor material may be based at least in part on a nucleation of the single crystalline arrangement at an interface between the second material and the semiconductor material. In some examples of the method800and the system for manufacturing described herein, the second material may include silicon-germanium, amorphous silicon, nickel, a metal silicide, or polysilicon. Some examples of the method800and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions forming the one or more dielectric materials based at least in part on depositing a first dielectric material and depositing a second dielectric material over the first dielectric material. In some examples, forming the cavity may include forming the cavity with the taper through at least a portion of the first dielectric material. In some examples of the method800and the system for manufacturing described herein, the first dielectric material may have a first thermal conductivity, and the second dielectric material may have a second thermal conductivity that is less than the first thermal conductivity. In some examples of the method800and the system for manufacturing described herein, the first dielectric material may include an oxide material, and the second dielectric material may include a nitride material. Some examples of the method800and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions forming a first terminal conductor of the transistor in contact with a first portion of the channel portion, forming a second terminal conductor of the transistor in contact with a second portion of the channel portion, forming a gate dielectric in contact with a third portion of the channel portion that is between the first portion and the second portion, and forming a gate conductor of the transistor over the gate dielectric. FIG.9shows a flowchart illustrating a method900that supports single-crystal transistors for memory devices in accordance with examples as disclosed herein. The operations of method900may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using special-purpose hardware. At905, the method may include forming a deck of memory cells. In some examples, aspects of the operations of905may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At910, the method may include depositing one or more dielectric materials over the deck of memory cells. The operations of910may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At915, the method may include forming a plurality of cavities each extending through at least a portion of the one or more dielectric materials, where each of the plurality of cavities may include a taper from a first cross-sectional area toward a point. The operations of915may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At920, the method may include depositing a semiconductor material in each of the plurality of cavities and above the one or more dielectric materials. The operations of920may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At925, the method may include forming a plurality of single crystalline arrangements of the semiconductor material, each associated with one of the plurality of cavities, based at least in part on heating and cooling the semiconductor material. The operations of925may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. At930, the method may include forming, from each of the plurality of single crystalline arrangements of the semiconductor material, a respective channel portion of a transistor based at least in part on doping the single crystalline arrangement of the semiconductor material. The operations of930may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through7. In some examples, an apparatus as described herein may be manufactured (e.g., fabricated) according to a method or methods, such as the method900. A system for manufacturing the apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a deck of memory cells, depositing one or more dielectric materials over the deck of memory cells, forming a plurality of cavities each extending through at least a portion of the one or more dielectric materials, where each of the plurality of cavities may include a taper from a first cross-sectional area toward a point, depositing a semiconductor material in each of the plurality of cavities and above the one or more dielectric materials, forming a plurality of single crystalline arrangements of the semiconductor material, each associated with one of the plurality of cavities, based at least in part on heating and cooling the semiconductor material, and forming, from each of the plurality of single crystalline arrangements of the semiconductor material, a respective channel portion of a transistor based at least in part on doping the single crystalline arrangement of the semiconductor material. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for patterning the semiconductor material that is above the one or more dielectric materials and between each of the plurality of cavities to expose a surface of the one or more dielectric materials between each of the plurality of cavities. In some examples, forming the plurality of single crystalline arrangements of the semiconductor material may be based at least in part on the patterning. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for depositing a dielectric material in contact with the patterned semiconductor material and the exposed surface of the one or more dielectric materials. In some examples, forming the plurality of single crystalline arrangements of the semiconductor material may be based at least in part on depositing the dielectric material. In some examples of the method900and the system for manufacturing described herein, forming the plurality of single crystalline arrangements of the semiconductor material may include operations, features, circuitry, logic, means, or instructions for nucleating each of the single crystalline arrangements of the semiconductor material at a respective nucleation site at an end of a respective cavity opposite from an opening of the respective cavity. In some examples of the method900and the system for manufacturing described herein, heating the semiconductor material may include operations, features, circuitry, logic, means, or instructions for applying a laser to at least the dielectric material and the semiconductor material. In some examples of the method900and the system for manufacturing described herein, depositing the semiconductor material may include operations, features, circuitry, logic, means, or instructions for depositing the semiconductor material with an amorphous arrangement or a polycrystalline arrangement. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for, depositing, in each of the plurality of cavities, a second material before depositing the semiconductor material. In some examples, forming the plurality of single crystalline arrangements of the semiconductor material may be based at least in part on a nucleation of the single crystalline arrangements at respective interfaces between the second material and the semiconductor material. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming the one or more dielectric materials based at least in part on depositing a first dielectric material and depositing a second dielectric material over the first dielectric material. In some examples, forming the plurality of cavities may include forming each of the plurality of cavities with the respective taper through at least a portion of the first dielectric material. Some examples of the method900and the system for manufacturing described herein, may further include operations, features, circuitry, logic, means, or instructions for forming, for each transistor of the plurality, a first terminal conductor of the transistor in contact with a first portion of the channel portion, a second terminal conductor of the transistor in contact with a second portion of the channel portion, a gate dielectric in contact with a third portion of the channel portion that is between the first portion and the second portion, and a gate conductor of the transistor over the gate dielectric. It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined. Another apparatus is described. The apparatus may include a dielectric portion and a semiconductor portion in contact with a top surface of the dielectric portion and extending into the dielectric portion with a tapered projection, the semiconductor portion including a single-grain crystalline arrangement. The apparatus may further include a first transistor terminal in contact with a top surface of the semiconductor portion at a first location, a second transistor terminal in contact with the top surface of the semiconductor portion at a second location, a transistor gate dielectric in contact with the top surface of the semiconductor portion at a third location between the first location and the second location, and a transistor gate conductor in contact with a top surface of the transistor gate dielectric. In some examples of the apparatus, the semiconductor portion may include a first doped region in contact with the first transistor terminal and a second doped region in contact with the second transistor terminal. In some examples of the apparatus, the dielectric portion may include a first dielectric layer having a first thermal conductivity and a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thermal conductivity that is less than the first thermal conductivity. In some examples of the apparatus, the first dielectric layer may include an oxide material and the second dielectric layer may include a nitride material. In some examples, the apparatus may include a material portion between an end of the tapered projection of the semiconductor portion and the dielectric portion, the material portion including silicon-germanium, nickel, a metal silicide, or polysilicon. Another apparatus is described. The apparatus may include a deck of memory cells, a dielectric portion above the deck of memory cells, and a plurality of transistors coupled with the deck of memory cells. Each transistor of the plurality of transistors may include a semiconductor portion in contact with a top surface of the dielectric portion, the semiconductor portion including a single-grain crystalline arrangement and having a tapered extension into the dielectric portion, a first terminal in contact with a first portion of a top surface of the semiconductor portion, a second terminal in contact with a second portion of the top surface of the semiconductor portion, and a gate conductor operable to modulate a conductivity of the semiconductor portion between the first terminal and the second terminal. In some examples, the apparatus may include a second dielectric material between each of the plurality of transistors. In some examples, each sidewall of the second dielectric material may be in contact with a sidewall of the semiconductor portion, and a bottom surface of the second dielectric material may be in contact with a top surface of the dielectric portion. In some examples of the apparatus, the dielectric portion may include a first dielectric layer having a first thermal conductivity and a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thermal conductivity that is less than the first thermal conductivity. A transistor is described. The transistor may be formed by a process of forming a cavity extending through at least a portion of one or more dielectric materials, where the cavity includes a taper from a first cross-sectional area toward a point, depositing a semiconductor material in the cavity and above the one or more dielectric materials, forming the semiconductor material in a single crystalline arrangement based at least in part on heating and cooling the semiconductor material, and forming a channel portion of the transistor based at least in part on doping the single crystalline arrangement of the semiconductor material. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths. The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors. The term “coupling” refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow. The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow. The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, and/or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels. As used herein, the term “electrode” may refer to an electrical conductor, and in some examples, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array. The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means. A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate. The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label. The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.” Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media. The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein. | 121,298 |
11862669 | Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows. DETAILED DESCRIPTION Definitions and General Techniques Unless otherwise defined herein, scientific and technical terms used herein shall have the meanings that are commonly understood by those of ordinary skill in the art. Further, unless otherwise required by context, singular terms shall include pluralities and plural terms shall include the singular. Generally, nomenclatures used in connection with, and techniques of, semiconductor processing described herein are those well-known and commonly used in the art. The methods and techniques described herein are generally performed according to conventional methods well known in the art and as described in various general and more specific references that are cited and discussed throughout the present specification unless otherwise indicated. The nomenclatures used in connection with, and the procedures and techniques of semiconductor device technology, semiconductor processing, and other related fields described herein are those well-known and commonly used in the art. For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present disclosure. The same reference numerals in different figures denotes the same elements. No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include items, and may be used interchangeably with “one or more.” Furthermore, as used herein, the term “set” is intended to include items (e.g., related items, unrelated items, a combination of related items, and unrelated items, etc.), and may be used interchangeably with “one or more.” Where only one item is intended, the term “one” or similar language is used. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. As defined herein, two or more elements are “integral” if they are comprised of the same piece of material. As defined herein, two or more elements are “non-integral” if each is comprised of a different piece of material. The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “include,” and “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, device, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, system, article, device, or apparatus. The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the apparatus, methods, and/or articles of manufacture described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The following terms and phrases, unless otherwise indicated, shall be understood to have the following meanings. The term “unit cell” as used herein refers to a piece of a pattern in a semiconductor which is repeated in the semiconductor. The term “SiC” as used herein refers to silicon carbide which is a compound semiconductor and is a mixture of silicon and carbon with the chemical formula SiC. Silicon is covalently bonded with carbon. In 4H—SiC, 4H is written in the Ramsdell classification scheme where the number indicates the layer and the letter indicates the Bravais lattice. That means in a 4H—SiC structure four hexagonal layers of SiC are present. SiC exists in a kind of polymorphic crystalline building known as a polytype, e.g. 3C—SiC, 4H—SiC, 6H—SiC. Presently 4H—SiC is used in power device manufacturing. The term “substrate” as used herein refers to the supporting material on or in which the components of an integrated circuit are fabricated or attached. The term “MOSFET” as used herein refers to metal oxide semiconductor field-effect transistor. which is a four-terminal device with source (S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently connected to the source terminal so making it a three-terminal device like field effect transistor. The term “DMOSFET” as used herein refers to double-implantation metal oxide semiconductor field-effect transistor. A common physical structure of SiC MOSFETs is the planar double-implanted MOSFET in 4H—SiC (SiC-DMOSFET). The term “dopant” as used herein refers to an impurity added from an external source to a material by diffusion, coating, or implanting into a substrate, and changing the properties thereof. In semiconductor technology, an impurity may be added to a semiconductor to modify its electrical properties or to a material to produce a semiconductor having desired electrical properties. N-type (negative) dopants (e.g., such as phosphorus for a group IV semiconductor) typically come from group V of the periodic table. When added to a semiconductor, n-type dopants create a material that contains conduction electrons. P-type (positive) dopants (e.g., such as boron for a group IV semiconductor) typically come from group III and result in conduction holes (i.e., vacancies in the electron shells). The term “drain” as used herein refers to the electrode of a field effect transistor which receives charge carriers which pass through the transistor channel from the source electrode. The term “source” as used herein refers to the active region/electrode to which the source of charge carriers is connected in a field effect transistor, The term “gate” as used herein refers to the control electrode or control region that exerts an effect on a semiconductor region directly associated therewith, such that the conductivity characteristic of the semiconductor region is altered in a temporary manner, often resulting in an on-off type switching action. The control electrode or control region of a field effect transistor is located between the source and drain electrodes, and regions thereof. The term “topside” as used herein refers to outer side/top of the MOSFET. The topside of the vertical MOSFET may comprise a source terminal. The term “bottom side” as used herein refers to underside/base of the MOSFET. The bottom side of the vertical MOSFET may comprise a drain terminal. The term “impurity” as used herein refers to a foreign material present in a semiconductor crystal, such as boron or arsenic in silicon, which is added to the semiconductor to produce either p-type or n-type semiconductor material, or to otherwise result in material whose electrical characteristics depend on the impurity dopant atoms. The term “trench sidewalls” as used herein refers to walls that form sides of the trench region. The term “bottom portion” as used herein refers to base of the trench region. The term “crystal plane” as used herein refers to imaginary plane inside a crystal of a semiconductor substrate in which large concentration of atoms are present. The term “MOS interface” as used herein refers to a region/path that electrically interconnects two regions. The term “horizontal surface” as used herein refers to an unetched surface on topside of the semiconductor substrate. The term “PN junction” as used herein refers to the interface and region of transition between p-type and n-type semiconductors. The term “polysilicon” as used herein refers to a polycrystalline form of silicon. The term “p-type” as used herein refers to extrinsic semiconductor in which the hole density exceeds the conduction electron density. The term “channel” as used herein refers to a path for conducting current between a source and drain of a field effect transistor. The term “chip” as used herein refers to a single crystal substrate of semiconductor material on which one or more active or passive solid-state electronic devices are formed. A chip may contain an integrated circuit. A chip is not normally ready for use until packaged and provided with external connectors. The term “contact” as used herein refers to the point or part of a conductor which touches another electrical conductor or electrical component to carry electrical current to or from the conductor or electrical component. The term “drift layer” as used herein refers to lightly doped region to support the high voltage in power MOSFET. The term “well” used herein refers certain regions in a metal-oxide-semiconductor (MOS) transistor. MOS transistors are always created in a “well” region. A PMOS (positive-channel MOS) transistor is made in an N-doped region, called “n-well” region. Similarly, an NMOS transistor (negative-channel MOS) is made in a “p-type” region called “p-well”. This ensures that the leakage between two transistors, through the bottom side, is low due to the reverse bias between the transistor areas and the well region. The term “device” as used herein refers to the physical realization of an individual electrical element in a physically independent body which cannot be further divided without destroying its stated function. The term “surface” as used herein refers to the outer or exterior boundary of a thing. The term “trench” as used herein refers to electrical isolation of electronic components in a monolithic integrated circuit by the use of grooves or other indentations in the surface of the substrate, which may or may not be filled with electrically insulative (i.e., dielectric) material. The term “dielectric” as used herein refers to a non-conductor of electricity, otherwise known as an insulator. The term “ILD” as used herein refers to interlayer dielectric material used to electrically separate closely spaced interconnect lines arranged in several levels (multilevel metallization) in an advanced integrated circuit. The term “work function” as used herein refers to minimum quantity of energy required to remove an electron to infinity from the surface of a given metal. The term “mobility” as used herein refers to the facility with which carriers move through a semiconductor when subjected to an applied electric field. Electrons and holes typically have different mobilities in the same semiconductor. The term “RIE” as used herein refers to reactive ion etching which is an etching technology used in microfabrication. RIE is a type of dry etching which has different characteristics than wet etching. RIE uses chemically reactive plasma to remove material deposited on wafers. The plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the plasma attack the wafer surface and react with it. The term “ICP” as used herein refers to inductively coupled plasma etching technology often used in specialty semiconductor markets for device manufacturing. This technology can combine both chemical reactions and ion-induced etching. The independent control of ion flux enables high process flexibility. ICP etching is based on the use of an inductively coupled plasma source. The ICP source generates a high-density plasma due to inductive coupling between the RF antenna and the plasma. The antenna, located in the plasma generation region, creates an alternating RF magnetic field and induces RF electric fields, which energize electrons that participate in the ionization of gas molecules and atoms at low pressure. Due to the absence of an electric field near the reactor walls there is virtually no ion bombardment or erosion of the walls. The term “CVD” as used herein refers to chemical vapor deposition is method used to produce high quality, high-performance, solid materials, typically under vacuum. The process is often used in the semiconductor industry to produce thin films. In typical CVD, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile by-products are also produced, which are removed by gas flow through the reaction chamber. The term “RF” as used herein refers to Radio frequency. Radio frequency is an oscillation rate of an alternating electric current or voltage or of a magnetic, electric or electromagnetic field or mechanical system. The terms “first conductivity type region” and “second conductivity type region” as used herein, are used to describe n-type and p-type regions respectively for a N type device. For a P type device “first conductivity type region” and “second conductivity type region” are used to describe p-type and n-type regions respectively. Embodiments relate to MOSFET power device having inversion channels. An embodiment relates to the MOSFET comprising a first metal oxide semiconductor (MOS) interface at a first section and a second metal oxide semiconductor (MOS) interface at a second section. An embodiment relates to the MOSFET comprising the first metal oxide semiconductor (MOS) interface at the first section and a metal region formed adjacent to a first conductivity type layer at the second section. An embodiment relates to the MOSFET comprising the first section and the second section arranged in at least one sequence along a lateral direction. An embodiment relates to the MOSFET comprising a higher channel density. An embodiment relates to the MOSFET comprising an effective channel mobility. An embodiment relates to reducing differential on-resistance for a given chip size. An embodiment relates to the MOSFET for minimizing specific on-resistance. An embodiment relates to the MOSFET for adjusting short-circuit withstand time. An embodiment relates to the MOSFET for adjusting unclamped inductive switching energy. An embodiment relates to the MOSFET for adjusting gate threshold voltage stability. An embodiment relates to the MOSFET for increasing effective channel length for a given on-resistance target. An embodiment relates to the MOSFET comprising the first metal region in direct contact with a first conductivity type drift layer. An embodiment relates to the MOSFET comprising the first MOS interface comprising a first contact with a horizontal surface of a semiconductor substrate and a second contact with a trench sidewall of a trench region. An embodiment relates to the MOSFET comprising the second MOS interface comprising a third contact solely with the trench sidewall of the trench region. An embodiment relates to the formation of the second MOS interface at the second section, in which the trench region is in contact with the first conductivity type drift layer through a gap between a second conductivity type first well region and a second conductivity type second well region. An embodiment relates to the MOSFET comprising the metal region at the second section, in which the trench region is not in contact with the first conductivity type drift layer. An embodiment relates to the MOSFET comprising the metal region at the second section, in which the second conductivity type first well region and the second conductivity type second well region encloses bottom portion of the trench region. An embodiment relates to the MOSFET, in which the second conductivity type first well region and the second conductivity type second well region overlaps at the first section. An embodiment relates to the MOSFET, in which the second conductivity type first well region and the second conductivity type second well region overlaps at the first section and the second section. FIG.1illustrates an embodiment of a cross-sectional structure of one or more unit cells of a power MOSFET, a first unit cell of the one or more unit cells comprising a first metal oxide semiconductor (MOS) interface on a horizontal surface of a semiconductor substrate and a trench sidewall, and a second unit cell of the one or more unit cells comprising a second metal oxide semiconductor (MOS) interface formed solely on the trench sidewall. The MOSFET (shown inFIG.1) is a n-type MOSFET. For the n-type MOSFET, the terms “first conductivity type” and “second conductivity type”, are used to describe n-type and p-type respectively. In an embodiment, the MOSFET is a p-type MOSFET. For the p-type MOSFET, the terms “first conductivity type” and “second conductivity type”, are used to describe p-type and n-type respectively. The MOSFET (shown inFIG.1) comprises the semiconductor substrate. The semiconductor substrate comprises a N+ substrate102(i.e. a first conductivity type substrate) and a N− drift layer104(i.e. a first conductivity type drift layer). In an embodiment, the semiconductor substrate comprises a silicon carbide (SiC) substrate. The MOSFET comprises a first section and a second section that are contiguously located along a lateral direction within the MOSFET. The first section comprises the first metal oxide semiconductor (MOS) interface, and the second section comprises the second metal oxide semiconductor (MOS) interface. The first section and the second section are arranged in at least one sequence from left to right or right to left. In an embodiment, the at least one sequence comprises the first section (i.e. section A as shown inFIG.1) at a first location and the second section (i.e. section B as shown inFIG.1) at a second location along the lateral direction. In another embodiment, the at least one sequence comprises the second section at the first location and the first section at the second location along the lateral direction. In yet another embodiment, the at least one sequence comprises the first section at the first location and the second location along the lateral direction. In yet another embodiment, the at least one sequence comprises the second section at the first location and the second location along the lateral direction. In yet another embodiment, at the least one sequence comprises the first section at the first location and a third location, and the second section at the second location along the lateral direction. In yet another embodiment, at the least one sequence comprises the second section at the first location and the third location, and the first section at the second location along the lateral direction. For example, assume the first section as ‘A’ and the second section as ‘B’, then the at least one sequence comprises ‘AB’, ‘BA’, ‘AA’, ‘BB’, ‘ABA’, ‘AAB’, ‘BAA’, ‘ABB’, ‘BAB’, ‘BBA’, ‘ABAB’, ‘ABBA’, ‘BAAB’, etc. The MOSFET comprises a first P-well region106(i.e. a second conductivity type first well region), a second P-well region112(i.e. a second conductivity type second well region), a first source region108, a second source region114and a trench region110. The first source region108and the second source region114are two distinct source regions. Similarly, the first P-well region106and the second P-well region112are two distinct well regions. The first source region108is positioned (e.g. confined) within the first P-well region106. The second source region114is positioned (e.g. confined) within the second P-well region112. The second source region114and the second P-well region112are positioned closer to the first section and far away from the second section. The second P-well region112overlaps the first P-well region106at the first section. The MOSFET comprises a gap between the first P-well region106and the second P-well region112at the second section. The second P-well region112do not overlaps the first P-well region106at the second section. The trench region110is extended through the first P-well region106and the first source region108. The trench region110comprises a contact with the N-drift layer104through the gap between the first P-well region106and the second P-well region112. The MOSFET comprises silicide layers122,124on top of the first source region108, the second source region114and bottom of the N+ substrate102. The silicide layer122on top of the second source region114is partly positioned on top of the second P-well region112. The first section comprises the first metal oxide semiconductor (MOS) interface. The first MOS interface comprises a first portion and a second portion. The first portion comprises a first contact with a horizontal surface (e.g. an unetched surface) of the semiconductor substrate. In an embodiment, the first portion of the first MOS interface is positioned parallel to 0001 crystal plane of the semiconductor substrate. In another embodiment, the first portion of the first MOS interface is positioned parallel to 11-20 crystal plane of the semiconductor substrate. The second portion of the first MOS interface comprises a second contact with the trench sidewall of the trench region110. In an embodiment, the second portion of the first MOS interface is positioned parallel to one of 11-20 crystal plane and 1-100 crystal plane of the semiconductor substrate. The first section comprises a combination of a planar MOSFET structure and a trench MOSFET structure. The second section comprises the second MOS interface. The second MOS interface comprises a third contact with the trench sidewall of the trench region110. The second section comprises solely the trench MOSFET structure. The MOSFET (shown inFIG.1), comprising the first section and the second section, comprises a higher channel density and reduced on-resistance of the MOSFET. The trench region comprises the trench sidewall. In an embodiment, the trench sidewall of the trench region110comprises a sloped sidewall. The sloped sidewall comprises a sidewall angle ranging from 30° to 90°. In an embodiment, the trench region110comprises a depth ranging from 0.2 μm to 2.0 μm. A slope of the sloped sidewall is selected appropriately to orient the first MOS interface along a predefined crystal plane that comprises a low trap density. In an embodiment, the first portion of the first MOS interface is positioned parallel to one of 11-20 crystal plane and 0338 crystal plane of the sloped sidewall of the semiconductor substrate, when the trench sidewall comprises the sloped sidewall. The MOSFET comprising the sloped sidewall further comprises a higher channel mobility in addition to the higher channel density. The MOSFET structure provides flexibility to a designer to increase/lower density of the first section comprising at least one of the trench MOSFET structure and the planar MOSFET structure, and the second section comprising the trench MOSFET structure alone. The density of the first section and the second section is increased or lowered depending on requirement of at least one of a specific on-resistance of the MOSFET and robustness metric such as a short-circuit withstand time, an unclamped inductive switching energy and a gate threshold voltage stability. The MOSFET shown inFIG.1further provides the flexibility to at least one of (a) increase an effective channel length for the given on-resistance and (b) reduce the on-resistance for a given chip size based on requirement. FIGS.2ato2abare cross-sectional views illustrating an embodiment of a process of manufacturing the MOSFET structure shown inFIG.1. The process of manufacturing the MOSFET structure shown inFIG.1comprises preparing a semiconductor substrate having a N+ substrate202(i.e. a first conductivity type substrate) and a N− drift layer204(i.e. a first conductivity type drift layer) as shown inFIG.2a. The N− drift layer204is grown on top of the N+ substrate202. The N+ substrate202comprises a heavily doped substrate. A first patterned hard mask layer205is formed on topside of the semiconductor substrate as shown inFIG.2b. A first p-type ion implantation (e.g. Aluminum, Boron) is formed on the topside of the semiconductor substrate through the first patterned hard mask layer205to form a first p-well region206as shown inFIG.2c. The first patterned hard mask layer205is then removed from the topside of the semiconductor substrate as shown inFIG.2d. In an embodiment, the first p-well region206is formed by a first epitaxial growth using a p-type impurity (e.g. Aluminum, Boron) into the N− drift layer204. The first P-well region206comprises a first predefined implantation energy and a first predefined dosage. In an embodiment, the first predefined implantation energy ranges from 5 keV to 5 MeV and the first predefined dosage ranges from 1E13 cm−2 to 5E16 cm−2. In another embodiment, the first P-well region206is formed using a first single ion-implantation step comprising combination of the predefined implantation energy and the predefined dosage. In yet another embodiment, the first P-well region206is formed using a first sequence of multiple ion-implantation steps. An ion-implantation step of the first sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the first P-type ion implantation (i.e. second conductivity type first ion implantation) is performed at one of room temperature and at elevated temperature up to 1000° C. A second patterned masking layer207is formed on the topside of the semiconductor substrate as shown inFIG.2e. A first n-type ion (e.g. Nitrogen, Phosphorous) implantation is formed on the topside of the semiconductor substrate through the second patterned masking layer207to form a first source region208within the first P-well region206as shown inFIG.2fThe second patterned masking layer207is then removed from the semiconductor substrate as shown inFIG.2g. In an embodiment, the first source region208is formed by a second epitaxial growth using a n-type impurity (e.g. Nitrogen, Phosphorous) into the first P-well region206. The first source region208comprises a second predefined implantation energy and a second predefined dosage. In an embodiment, the second predefined implantation energy ranges from 5 keV to 1 MeV and the second predefined dosage ranges from 5E13 cm−2 to 5E16 cm−2. In another embodiment, the first source region208is formed using a second single ion-implantation step comprising combination of the second predefined implantation energy and the second predefined dosage. In yet another embodiment, the first source region208is formed using a second sequence of multiple ion-implantation steps. An ion-implantation step of the second sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the first n-type ion implantation is performed at one of the room temperature and at the elevated temperature up to 1000° C. A third patterned hard mask layer209is formed on the topside of the semiconductor substrate as shown inFIG.2h. A trench region210is then formed by performing etching onto the topside (e.g. a top surface) of the semiconductor substrate through the third patterned hard mask layer209as shown inFIG.2i. In an embodiment the etching is performed using one of a reactive ion etching (RIE) and an inductively coupled plasma (ICP) etching. In another embodiment, the etching is controlled appropriately to form the trench region210. The trench region210comprises a predefined depth and a predefined sidewall angle. The predefined depth of the trench region210ranges from 0.2 μm to 2.0 μm. The predefined sidewall angle ranges from 30° to 90°. The predefined depth of the trench region210is deeper than a depth of the first P-well region206(i.e. bottom portion of the trench region210may be in contact with the N− drift layer204). The trench region210comprises a first section and a second section. A first spacer211(i.e. sidewall spacer) is then formed on the semiconductor substrate along the trench sidewalls of the trench region210and the third patterned hard mask layer209as shown inFIG.2j. In an embodiment, the first spacer211is formed using a dielectric material (e.g. silicon dioxide, silicon nitride). In an embodiment, the first spacer211and the hard mask layers (e.g. the first patterned hard mask layer205, the second patterned hard mask layer207) are formed using dis-similar dielectric materials to enable selective removal of one or more portions of the first spacer211without removal of the hard mask layers. The one or more portions of the first spacer211, that are not in contact with the first source region208, are selectively removed as shown inFIG.2k. A second p-type ion implantation (e.g. Aluminum, Boron) is then performed to form a second P-well region212below the first P-well region206as shown inFIG.2l. In an embodiment, the second p-type ion implantation (i.e. second conductivity type second ion implantation) comprises an angled implantation (i.e. at a predefined angle) to electrically short a portion of the second P-well region212and the first P-well region206at the first section. In an embodiment, the angled implantation is performed using a tilt angle away from normal incidence. The tilt angle for the angled implantation may range from 0° (normal incidence) to 60°. The second P-well region212comprises a third predefined implantation energy and a third predefined dosage. In an embodiment, the third predefined implantation energy ranges from 5 keV to 5 MeV and the third predefined dosage ranges from 5E13 cm−2 to 5E16 cm−2. In another embodiment, the second P-well region212is formed using a third single ion-implantation step comprising combination of the third predefined implantation energy and the third predefined dosage. In yet another embodiment, the second P-well region212is formed using a third sequence of multiple ion-implantation steps. An ion-implantation step of the third sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the second P-type ion implantation (i.e. the second conductivity type second ion implantation) is performed at one of the room temperature and the elevated temperature up to 1000° C. A second spacer213(i.e. sidewall spacer) is then formed on the semiconductor substrate along the trench sidewalls of the trench region210and the third patterned hard mask layer209as shown inFIG.2m. One or more portions of the second spacer213, that are in contact with the first p-well region206(i.e. in contact with the first section), are selectively removed as shown inFIG.2n. A second n-type ion implantation (e.g. Nitrogen, Phosphorous) is then performed through the second spacer213to form a second source region214within the second P-well region212as shown inFIG.2o. The second source region214and the second P-well region212are formed closer to the first section and far away from the second section. The second source region214comprises a fourth predefined implantation energy and a fourth predefined dosage. In an embodiment, the fourth predefined implantation energy ranges from 5 keV to 1 MeV and the fourth predefined dosage ranges from 5E13 cm−2 to 5E16 cm−2. In another embodiment, the second source region214is formed using a fourth single ion-implantation step comprising combination of the fourth predefined implantation energy and the fourth predefined dosage. In yet another embodiment, the second source region214is formed using a fourth sequence of multiple ion-implantation steps. An ion-implantation step of the fourth sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the second n-type ion implantation is performed at one of the room temperature and the elevated temperature up to 1000° C. The hard mask layers (e.g. the first spacer211, the second spacer213, the third patterned hard mask layer209) are removed as shown inFIG.2p. The semiconductor substrate (e.g. wafers) is then subjected to high-temperature heat treatment for activating implanted ions and for implant damage alleviation. In an embodiment, the heat treatment or annealing is performed at a temperature ranging from 1700° C.-2000° C., for a duration ranging from 10 min to 2 hours. A gate dielectric layer216is then formed onto the topside of exposed portions of the semiconductor substrate as shown inFIG.2q. In an embodiment, the gate dielectric layer216is an oxide layer. In another embodiment, the gate dielectric layer216is formed by one of a thermal oxidation and a chemical vapor deposition (CVD) of a dielectric layer (e.g. silicon dioxide, silicon nitride, silicon oxynitride, etc.). Then a poly silicon layer218is formed onto the topside of the semiconductor substrate as shown inFIG.2r. In an embodiment, the poly silicon layer218comprises a n-type doped layer. The n-type doped layer is doped using a n-type dopant (e.g. phosphorous). A fourth patterned masking layer215is then formed on top of the poly silicon layer218as shown inFIG.2s. The poly silicon layer218is then selectively etched using the fourth patterned masking layer215to form one or more poly silicon regions as shown inFIG.2t. The fourth patterned masking layer215is removed as shown inFIG.2u. Then an interlayer dielectric (ILD)220is formed onto the topside of the semiconductor substrate as shown inFIG.2v. A fifth patterned masking layer217is formed on top of the interlayer dielectric (ILD)220as shown inFIG.2w. The interlayer dielectric (ILD)220is then selectively etched using the fifth patterned masking layer217as shown inFIG.2x. The gate dielectric layer216is also selectively etched using the fifth patterned masking layer217as shown inFIG.2y. The fifth patterned masking layer217is then removed from the semiconductor substrate and the semiconductor substrate is exposed to air as shown inFIG.2z. A first silicide region222and a second silicide region224are then formed on the topside and bottom side of the semiconductor substrate to form a source terminal and a drain terminal respectively as shown inFIG.2aa. The first silicide region222is formed on top of the first source region208and the second source region214. The second silicide region224is formed on bottom of the N+ substrate202. A first inter-connect metal layer226and a second inter-connect metal layer228is then formed on the topside and the bottom side of the semiconductor substrate respectively as shown inFIG.2ab. FIG.3illustrates an embodiment of a cross-sectional structure of one or more unit cells of a power MOSFET, a first unit cell of the one or more unit cells comprising a first metal oxide semiconductor (MOS) interface on a horizontal surface of a semiconductor substrate and a trench sidewall, and a second unit cell of the one or more unit cells comprising a metal region330formed adjacent to a first conductivity type drift layer of the MOSFET. The MOSFET (shown inFIG.3) is a n-type MOSFET. For the n-type MOSFET, the terms “first conductivity type” and “second conductivity type”, are used to describe n-type and p-type respectively. In an embodiment, the MOSFET is a p-type MOSFET. For the p-type MOSFET, the terms “first conductivity type” and “second conductivity type”, are used to describe p-type and n-type respectively. The MOSFET (shown inFIG.3) comprises the semiconductor substrate. The semiconductor substrate comprises a N+ substrate302(i.e. a first conductivity type substrate) and a N− drift layer304(i.e. a first conductivity type drift layer). In an embodiment, the semiconductor substrate comprises a silicon carbide (SiC) substrate. The MOSFET comprises a first section and a second section that are contiguously located along a lateral direction within the MOSFET. The first section comprises the first metal oxide semiconductor (MOS) interface, and the second section comprises the metal region330. In an embodiment, the metal region comprises a junction barrier Schottky (JBS) diode region. The first section and the second section are arranged in at least one sequence from left to right or right to left. In an embodiment, the at least one sequence comprises the first section at a first location and the second section at a second location along the lateral direction. In another embodiment, the at least one sequence comprises the second section at the first location and the first section at the second location along the lateral direction. In yet another embodiment, the at least one sequence comprises the first section at the first location and the second location along the lateral direction. In yet another embodiment, the at least one sequence comprises the second section at the first location and the second location along the lateral direction. In yet another embodiment, the at least one sequence comprises the first section at the first location and a third location, and the second section at the second location along the lateral direction. In yet another embodiment, the at least one sequence comprises the second section at the first location and the third location, and the first section at the second location along the lateral direction. For example, assume the first section as ‘A’ and the second section as ‘B’, then the at least one sequence comprises ‘AB’, ‘BA’, ‘AA’, ‘BB’, ‘ABA’, ‘AAB’, ‘BAA’, ‘ABB’, ‘BAB’, ‘BBA’, ‘ABAB’, ‘ABBA’, ‘BAAB’, etc. The MOSFET comprises a first P-well region306(i.e. a second conductivity type first well region), a second P-well region312(i.e. a second conductivity type second well region), a source region314, a metal region330and a trench region310. The first P-well region306and the second P-well region312are two distinct well regions. The source region314is positioned (e.g. confined) within the second P-well region312. The source region314and the second P-well region312are positioned closer to the first section and far away from the second section. The second P-well region312overlaps the first P-well region306at the first section and the second section. The trench region310is completely contained within the second P-well region312. The trench region310is extended through the first P-well region306. The first P-well region306and the second P-well region312completely enclose bottom portion (i.e. base) of the trench region310to shield the bottom portion from first high electric fields in off-state or during high-voltage blocking operation of the MOSFET. At the second section, the metal region (i.e. the junction barrier Schottky diode region) is shielded from second high electric fields present during high-voltage blocking condition. In an embodiment, spacing between the first P-well region306and the second P-well region312at the second section and the first section is adjusted suitably for maintaining a good trade-off between an on-state resistance, and a third electric field at the metal region and the first MOS interface. In another embodiment, a depth and a doping concentration of the first P-well region306and the second P-well region312are adjusted for maintaining the good trade-off between the on-state resistance, and the third electric field at the metal region and the first MOS interface. In yet another embodiment, a width and a depth of the trench region310, and the implantation energy and the dosage of the first P-well region306and the second P-well region312are adjusted to control total extent and distribution of the first MOS interface. The MOSFET further comprises silicide layers322,324on top of the source region314, and bottom of the N+ substrate (302). The silicide layer322on top of the source region314is partly positioned on top of the second P-well region312and the first P-well region306. The first section comprises the first metal oxide semiconductor (MOS) interface. The first MOS interface comprises a first portion and a second portion. The first portion comprises a first contact with a horizontal surface (e.g. an unetched surface) of the semiconductor substrate. In an embodiment, the first portion of the first MOS interface is positioned parallel to 0001 crystal plane of the semiconductor substrate. In another embodiment, the first portion of the first MOS interface is positioned parallel to 11-20 crystal plane of the semiconductor substrate. The second portion of the first MOS interface comprises a second contact with a trench sidewall of the trench region310. In an embodiment, the second portion of the first MOS interface is positioned parallel to one of 11-20 crystal plane and 1-100 crystal plane of the semiconductor substrate. The first section comprises a combination of a planar MOSFET structure and a trench MOSFET structure. The second section comprises the metal region330(e.g. the junction barrier Schottky diode region). The metal region330comprises a fourth contact with the N− drift layer404of the semiconductor substrate. The metal region330comprises a predefined work function. The metal region330comprises one of Ti, W, Mo, Au, Pt, TiW, TiN, etc. The trench region310comprises the trench sidewall. In an embodiment, the trench sidewall of the trench region310comprises a sloped sidewall. The sloped sidewall comprises a sidewall angle ranging from 30° to 90°. In an embodiment, the trench region310comprises a depth ranging from 0.2 μm to 2.0 μm. A slope of the sloped sidewall is selected appropriately to orient the first MOS interface along a predefined crystal plane that comprises a low trap density. In an embodiment, the first portion of the first MOS interface is positioned parallel to 11-20 crystal plane and 0338 crystal plane of the sloped sidewall of the semiconductor substrate, when the trench sidewall comprises the sloped sidewall. The MOSFET turns on when a drain terminal is biased positively as compared to a source terminal and the metal region turns on when the drain terminal is biased negatively with respect to the source terminal. The MOSFET shown inFIG.3depicts an equal number of unit cells of the metal regions and unit cells of the first MOS interfaces. In an embodiment, the MOSFET comprises an unequal number of the unit cells of the metal regions and the unit cells of the first MOS interfaces based on requirements. In another embodiment, a ratio of the number of the unit cells of the metal regions to the unit cells of first MOS interfaces is varied (e.g. increased, decreased) based on application. FIGS.4to4aaare cross-sectional views illustrating an embodiment of a process of manufacturing the MOSFET structure shown inFIG.3. The process of manufacturing the MOSFET structure shown inFIG.3comprises preparing a semiconductor substrate having a N+ substrate402and a N− drift layer404as shown inFIG.4a. The N− drift layer404is grown on top of the N+ substrate402. The N+ substrate402comprises a heavily doped substrate. A first patterned hard mask layer405is formed on topside of the semiconductor substrate as shown inFIG.4b. A first p-type ion (e.g. Aluminum, Boron) implantation is formed on the topside of the semiconductor substrate through the first patterned hard mask layer405to form a first p-well region406as shown inFIG.4c. The first patterned hard mask layer405is removed from the topside of the semiconductor substrate as shown inFIG.4d. In an embodiment, the first p-well region406is formed by a first epitaxial growth using a p-type impurity (e.g. Aluminum, Boron) into the N− drift layer404. The first P-well region406comprises a first predefined implantation energy and a first predefined dosage. In an embodiment, the first predefined implantation energy ranges from 5 keV to 5 MeV and the first predefined dosage ranges from 1E13 cm−2 to 5E16 cm−2. In another embodiment, the first P-well region406is formed using a first single ion-implantation step comprising combination of the predefined implantation energy and the predefined dosage. In yet another embodiment, the first P-well region406is formed using a first sequence of multiple ion-implantation steps. An ion-implantation step of the first sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the first P-type ion implantation (i.e. second conductivity type first ion implantation) is performed at one of room temperature and at elevated temperature up to 1000° C. A second patterned hard mask layer407is formed on the topside of the semiconductor substrate as shown inFIG.4e. A trench region410is formed by performing etching onto the topside (e.g. a top surface) of the semiconductor substrate through the second patterned hard mask layer407as shown inFIG.4fIn an embodiment the etching is performed using one of a reactive ion etching (RIE) and an inductively coupled plasma (ICP) etching. In another embodiment, the etching is controlled appropriately to form the trench region410. The trench region410comprises a predefined depth and a predefined sidewall angle. The predefined depth of the trench region410ranges from 0.2 μm to 2.0 μm. The predefined sidewall angle ranges from 30° to 90°. The predefined depth of the trench region410is deeper than a depth of the first P-well region406(i.e. bottom portion of the trench region410may be in contact with the N− drift layer404). The trench region410comprises a first section and a second section. In an embodiment, the trench region410is located within the MOSFET to delineate the first p-well region406to be in contact with the horizontal (or unetched) surface of the semiconductor substrate and the trench sidewall. A second p-type ion implantation (e.g. Aluminum, Boron) is then performed to form a second P-well region412below the first P-well region406as shown inFIG.2g. In an embodiment, the second p-type ion implantation (i.e. second conductivity type second ion implantation) comprises an angled implantation (i.e. at a predefined angle) to electrically short a portion of the second P-well region412and the first P-well region406at the first section and the second section (i.e. the second P-well region412overlaps the first P-well region406at the first section and the second section). In an embodiment, the angled implantation is performed using a tilt angle away from normal incidence. The tilt angle for the angled implantation may range from 0° (normal incidence) to 60°. The second P-well region412comprises a second predefined implantation energy and a second predefined dosage. In an embodiment, the second predefined implantation energy ranges from 5 keV to 5 MeV and the second predefined dosage ranges from 5E13 cm−2 to 5E16 cm−2. In another embodiment, the second P-well region412is formed using a second single ion-implantation step comprising combination of the predefined implantation energy and the predefined dosage. In yet another embodiment, the second P-well region412is formed using a second sequence of multiple ion-implantation steps. An ion-implantation step of the second sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the second P-type ion implantation is performed at one of the room temperature and the elevated temperature up to 1000° C. In an embodiment, the overlap between the first P-well region406and the second P-well region412are adjusted by varying at least one of the tilt angle and the second predefined implantation energy. The first P-well region406and the second P-well region412encloses the bottom portion of the trench region410. The trench region410do not comprises a direct contact with the N− drift layer404. A first spacer409(i.e. sidewall spacer) is then formed on the semiconductor substrate along the trench sidewalls of the trench region410and the second patterned hard mask layer407as shown inFIG.4h. In an embodiment, the first spacer409is formed using a dielectric material (e.g. silicon dioxide, silicon nitride). In an embodiment, the first spacer409and the hard mask layers (e.g. the first patterned hard mask layer405, the second patterned hard mask layer407) are formed using dis-similar dielectric materials to enable selective removal of one or more portions of the first spacer409without removal of the hard mask layers. The one or more portions of the first spacer409, that are not in contact with the source region414, are selectively removed as shown inFIG.4i. An n-type ion implantation (e.g. Nitrogen, Phosphorous) is then performed through the first spacer409to form the source region414within the second P-well region412as shown inFIG.4j. The source region414and the second P-well region412are formed closer to the first section and far away from the second section. The source region414comprises a third predefined implantation energy and a third predefined dosage. In an embodiment, the third predefined implantation energy ranges from 5 keV to 1 MeV and the third predefined dosage ranges from 5E13 cm−2 to 5E16 cm−2. In another embodiment, the source region414is formed using a third single ion-implantation step comprising combination of the third predefined implantation energy and the third predefined dosage. In yet another embodiment, the source region414is formed using a third sequence of multiple ion-implantation steps. An ion-implantation step of the third sequence of multiple ion-implantation steps is performed with a different implantation energy or a different dosage. In an embodiment, the n-type ion implantation (i.e. first conductivity type ion implantation) is performed at one of the room temperature and the elevated temperature up to 1000° C. The hard mask layers (e.g. the first spacer409, the second patterned hard mask layer407) are removed as shown inFIG.4k. The semiconductor substrate (e.g. wafers) is then subjected to high-temperature heat treatment for activating implanted ions and for implant damage alleviation. In an embodiment, the heat treatment or annealing is performed at a temperature ranging from 1700° C.-2000° C., for a duration ranging from 10 min to 2 hours. A gate dielectric layer416is formed onto the topside of exposed portions of the semiconductor substrate as shown inFIG.4l. In an embodiment, the gate dielectric layer416is an oxide layer. In another embodiment, the gate dielectric layer416is formed by one of a thermal oxidation and a chemical vapor deposition (CVD) of a dielectric layer (e.g. silicon dioxide, silicon nitride, silicon oxynitride, etc.). Then a poly silicon layer418is formed onto the topside of the semiconductor substrate as shown inFIG.4m. In an embodiment, the poly silicon layer418comprises a n-type doped layer. The n-type doped layer is using a n-type dopant (e.g. phosphorous). A third patterned masking layer411is formed on top of the poly silicon layer418as shown inFIG.4n. The poly silicon layer418is then selectively etched using the third patterned masking layer411to form one or more poly silicon regions as shown inFIG.4o. The third patterned masking layer411is removed as shown inFIG.4p. Then an interlayer dielectric (ILD)420is formed onto the topside of the semiconductor substrate as shown inFIG.4q. A fourth patterned masking layer413is formed on top of the interlayer dielectric (ILD)420as shown inFIG.4r. The interlayer dielectric (ILD)420is then selectively etched using the fourth patterned masking layer413as shown inFIG.4s. The gate dielectric layer416is also selectively etched using the fourth patterned masking layer413as shown inFIG.4t. The fourth patterned masking layer413is then removed from the semiconductor substrate and the semiconductor substrate is exposed to air as shown inFIG.4u. Silicide layers422,424are then formed on the topside and bottom side of the semiconductor substrate to form a source terminal and a drain terminal respectively as shown inFIG.4v. The silicide layer422on the topside of the semiconductor substrate is formed partly on the first P-well region406, the second P-well region412and the source region414. A fifth patterned masking layer415is formed on the topside of the semiconductor substrate as shown inFIG.4w. Then the interlayer dielectric (ILD)420is selectively etched through the fifth patterned masking layer415as shown inFIG.4x. Then a metal region430is deposited and patterned on the topside of the semiconductor substrate through the fifth patterned masking layer415as shown inFIG.4y. In an embodiment, the metal region430comprises a junction Schottky barrier diode region. The metal region comprises a predefined work function. The metal region comprises one of Ti, W, Mo, Au, Pt, TiW, TiN, etc. The fifth patterned masking layer415is then removed to lift off the metal region430on top of the fifth patterned masking layer as shown inFIG.4z. A first inter-connect metal layer426and a second inter-connect metal layer428is then formed on the topside and the bottom side of the semiconductor substrate respectively as shown inFIG.4aa. The present disclosure may be embodied in other specific forms without departing from its spirit or characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. Other embodiments are also within the scope of the following claims. Although, various embodiments which incorporate the teachings described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. For example, a complementary MOSFET device with a P+ substrate, P− drift layer and P+ source can be created in a N-well region. The embodiments described are all applicable to the complementary MOSFET as well. All documents (patents, patent publications or other publications) mentioned in the specification are incorporated herein in their entirety by reference. INCORPORATION BY REFERENCE All publications, patents, and patent applications cited in this Specification are hereby incorporated by reference in their entirety.T. Kimoto, J. A. Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press (2014)U.S. patent application Ser. No. 16/374,025, filed Apr. 3, 2019, entitled “DESIGN AND MANUFACTURE OF POWER DEVICES HAVING INVERSION CHANNEL”U.S. patent application Ser. No. 16/945,781, filed Jul. 31, 2020, entitled “DESIGN AND MANUFACTURE OF POWER DEVICES HAVING INCREASED CROSS OVER CURRENT” | 55,371 |
11862670 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “above,” “over,” “underneath,” “beneath,” “proximate,” “distal,” “lower,” “higher,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The present disclosure is directed to semiconductor devices and methods for manufacturing the same. The semiconductor devices may be power MOSFETs, which may be bipolar, complementary metal-oxide semiconductor (CMOS) diffusion metal-oxide semiconductor (DMOS) devices (bipolar-CMOS-DMOS (BCD) devices), for example, but not limited to, LDMOS transistors (lateral diffused metal oxide semiconductor field effect transistors) or other suitable transistors/power devices. FIG.1is a flow diagram illustrating a method100for manufacturing a semiconductor device in accordance with some embodiments.FIGS.2to11illustrate schematic views of the intermediate stages of the method100. Referring toFIGS.1and2, the method100begins at step101, where a trench210is formed in a semiconductor layer21. In some embodiments, the semiconductor layer21may include crystalline silicon, polycrystalline silicon, or a combination thereof. Other suitable semiconductor materials are within the contemplated scope of the present disclosure. The trench210may be formed using a photolithography process and an etching process. The photolithography process may include, for example, but not limited to, coating a photoresist (not shown), soft-baking, exposing the photoresist through a photomask, post-exposure baking, and developing the photoresist, followed by hard-baking so as to form a patterned photoresist on the semiconductor layer21. The etching process may be implemented by etching the semiconductor layer21through the patterned photoresist using, for example, but not limited to, a dry etching process, a wet etching process, other suitable processes, or combinations thereof. Referring toFIGS.1and3, the method100proceeds to step102, where a dielectric layer220is formed on the semiconductor layer21to fill the trench210shown inFIG.2. The dielectric layer220may include, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Other suitable dielectric materials are within the contemplated scope of the present disclosure. The dielectric layer220may be deposited by, for example, but not limited to, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes. Referring toFIGS.1and4, the method100proceeds to step103, where a planarization process is conducted to remove an excess of the dielectric layer220shown inFIG.3, to expose the semiconductor layer21so as to obtain a dielectric film22. The dielectric film22may also be referred to as a shallow trench isolation (STI) region. Step103may be implemented using a chemical mechanical polishing (CMP) process or other suitable techniques. Other suitable processes may be used for formation of the STI region22. Referring toFIGS.1and5, the method100proceeds to step104, where an anti-type doping layer23is formed beneath the STI region22. In some embodiments, the anti-type doping layer23may have a thickness (T) ranging from about 50 Å to about 200 Å, although a slightly larger or smaller thickness may be used based on the device performance or the designs of the product to be produced. Step104may be implemented by (i) forming a patterned mask24on the semiconductor layer21to expose the STI region22and a first surrounding surface of the semiconductor layer21around the STI region22, and (ii) doping a region beneath the STI region22through the patterned mask24using an ion implantation process or other suitable processes so as to form the anti-type doping layer23. After step104, the patterned mask24may be removed. For an N-type MOS device, a P-type dopant is used in the ion implantation process for forming the anti-type doping layer23with a P-type conductivity, and may include, for example, but not limited to, boron, BF2, indium, the like, or combinations thereof. For a P-type MOS device, an N-type dopant is used in the ion implantation process for forming the anti-type doping layer23with an N-type conductivity, and may include, for example, but not limited to, arsenic, phosphorus, the like, or combinations thereof. Other suitable P-type dopants and N-type dopants are within the contemplated scope of the present disclosure. In alternative embodiments, the patterned mask24may be replaced by a patterned photoresist. Other suitable processes may be used for formation of the anti-type doping layer23. Referring toFIGS.1and6, the method100proceeds to step105, where a drift region211is formed in the semiconductor layer21to have a doping concentration lower than that of the anti-type doping layer23. After step105, the anti-type doping layer23is located between the drift region211and the STI region22. Step105may be implemented by (i) forming a patterned mask25on the semiconductor layer21to expose the STI region22and a second surrounding surface of the semiconductor layer21around the STI region22and the anti-type doping layer23, and (ii) doping the semiconductor layer21through the patterned mask25using an ion implantation process or other suitable processes so as to form the drift region211. After step105, the patterned mask25may be removed. In some embodiments, the drift region211has a first type conductivity, and the anti-type doping layer23has a second type conductivity opposite to the first type conductivity. Thus, the drift region211may be formed using the above-mentioned N-type dopant for forming the N-type MOS device, or using the above-mentioned P-type dopant for forming the P-type MOS device. In some embodiments, an upper surface of the drift region211(which corresponds to the second surrounding surface of the semiconductor layer21mentioned above) may have a first surface portion211aand a second surface portion211bwhich are located at two opposite sides of the STI region22and the anti-type doping layer23. In alternative embodiments, the patterned mask25may be replaced by a patterned photoresist. Other suitable processes may be used for formation of the drift region211. Please note that the term “anti-type doping layer” means a layer having a conductivity type opposite to that of the drift region211. Referring toFIGS.1and7, the method100proceeds to step106, where a well region212is formed in the semiconductor layer21. Step106may be implemented by (i) forming a patterned mask26on the semiconductor layer21to cover the STI region22, the anti-type doping layer23, and the drift region211, and (ii) doping the semiconductor layer21through the patterned mask26using an ion implantation process or other suitable processes so as to form the well region212. After step106, the patterned mask26may be removed. In some embodiments, the well region212has the second type conductivity, and thus may be formed using the above-mentioned P-type dopant for forming the N-type MOS device, or using the above-mentioned N-type dopant for forming the P-type MOS device. In some embodiments, an upper surface of the well region212may have a first surface portion212aand a second surface portion212bwhich are proximate to and distal from the STI region22, respectively. In alternative embodiments, the patterned mask26may be replaced by a patterned photoresist. Other suitable processes may be used for formation of the well region212. Referring toFIGS.1and8, the method100proceeds to step107, where a gate structure27is formed on the semiconductor layer21. In some embodiments, the gate structure27includes a gate dielectric271formed on the semiconductor layer21, a gate electrode272formed on the gate dielectric271, and two spacers273formed at two opposite sides of a stack of the gate electrode272and the gate dielectric271. The gate dielectric271may include, for example, but not limited to, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. Other suitable gate dielectric materials are within the contemplated scope of the present disclosure. The gate electrode272may include, for example, but not limited to, a metallic material, a metal compound, polycrystalline silicon, or doped silicon. Other suitable gate materials are within the contemplated scope of the present disclosure. The metallic material may include, for example, but not limited to, silver, aluminum, copper, tungsten, nickel, other suitable materials, alloys thereof, or combinations thereof. The metal compound may include, for example, but not limited to, titanium nitride, tantalum nitride, metal silicide, other suitable materials, or combinations thereof. The spacers273may include, for example, but not limited to, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. Other suitable spacer materials are within the contemplated scope of the present disclosure. The stack of the gate electrode272and the gate dielectric271may be formed by, for example, a process including (i) sequentially depositing a gate dielectric layer (not shown) and a gate electrode layer (not shown), and (ii) patterning the gate dielectric layer and the gate electrode layer to form the gate dielectric271and the gate electrode272using a photolithography process and an etching process similar to those described in step101. The spacers273may be formed by, for example, a process including (i) depositing a spacer-forming layer over the stack of the gate electrode272and the gate dielectric271, and (ii) anisotropically etching the spacer-forming layer. In some embodiments, the stack of the gate dielectric271and the gate electrode272may be formed over a portion of the STI region22, a portion of the anti-type doping layer23, the second surface portion211bof the drift region211, and a part212a1of the first surface portion212aof the well region212. Other suitable processes may be also used for forming the gate structure27. Referring toFIGS.1and9, the method100proceeds to step108, where a body contact28is formed in the well region212. Step108may be implemented by (i) forming a patterned mask29on the semiconductor layer21to expose the second surface portion212bof the well region212, and (ii) doping the well region212through the patterned mask29using an ion implantation process or other suitable processes so as to form the body contact28within the well region212. After step108, the patterned mask29may be removed. In some embodiments, the body contact28has the second type conductivity, and thus may have a higher doping concentration than that of the well region212. Therefore, the body contact28may be formed using the above-mentioned P-type dopant for forming the N-type MOS device, or using the above-mentioned N-type dopant for forming the P-type MOS device. In alternative embodiments, the patterned mask29may be replaced by a patterned photoresist. Other suitable processes may be also used for forming the body contact28. Referring toFIGS.1and10, the method100proceeds to step109, where a source area31and a drain area32are respectively formed within the well region212and the drift region211and may have a doping concentration higher than that of the anti-type doping layer23. Step109may be implemented by (i) forming a patterned mask30on the semiconductor layer21to expose a remaining part212a2of the first surface portion212aof the well region212and to expose the first surface portion211aof the drift region211, and (ii) doping the well region212and the drift region211through the patterned mask30using an ion implantation process or other suitable processes so as to form the source area31within the well region212and the drain area32within the drift region211. After step109, the patterned mask30may be removed. In some embodiments, the source area31and the drain area32have the first type conductivity, and thus may be formed using the above-mentioned N-type dopant for forming the N-type MOS device, or using the above-mentioned P-type dopant for forming the P-type MOS device. In alternative embodiments, the patterned mask30may be replaced by a patterned photoresist. Other suitable processes may be also used for forming the source area31and the drain area32. Referring toFIG.11, after removing the patterned mask30, a semiconductor device200is obtained and a channel length (L) is defined by a distance between the drift region211and the source area31. The anti-type doping layer23is located between the drift region211and the STI region22. The STI region22is located between the source area31and the drain area32. The well region212is disposed to separate the source area31and the body contact28from the drift region211. In some embodiments, in the semiconductor device200, the doping concentration of the anti-type doping layer23may be higher than that of the drift region211by two orders of magnitude and may be lower than that of the drain area32by two orders of magnitude. For example, when the doping concentration of the anti-type doping layer23ranges from about 1×1018atom/cm3to about 1×1019atom/cm3, the doping concentration of the drift region211may range from about 1×1016atom/cm3to about 1×1017atom/cm3, and the doping concentration of the drain area32may range from about 1×1020atom/cm3to about 1×1021atom/cm3. In some embodiments, steps101to109may not be performed in the above order. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200. In yet alternative embodiments, additional features may be added in the semiconductor device200, and some features in the semiconductor device200may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure. In the semiconductor device200, dielectric damages (electron trapping) may be induced by certain operations or process fabrications, and may be formed on a bottom wall and/or sidewalls of the dielectric film (STI region)22. During a reading operation, an on-current flows from the source area31, through the well region212and the drift region211, and then into the drain area32. When the anti-type doping layer23is not provided, the electron trapping may produce coulomb forces affecting the mobility of the electrons of the on-current. Although this disclosure is not bound by any theory, it is believed that in the semiconductor device200, because the anti-type doping layer23with the thickness (T) is provided underneath the dielectric film22and has a conductivity type opposite to that of the drift region211, a current path of an on-current in the drift region211may be changed, for example, to flow away from the dielectric film22. Therefore, the on-current is less likely to be influenced by coulomb forces of the electron trapping (i.e., the influence of the dielectric damages on the on-current is reduced), and the semiconductor device200may have improved operation performance and reliability. In alternative embodiments, a doping layer (which may be also exemplified as the anti-type doping layer23) is formed between a semiconductor region (which may be also exemplified as the drift region211) and a dielectric film (which may be also exemplified as the STI region22), and has a conductivity type to direct a current path away from the dielectric film, thereby reducing an influence of dielectric damages of the dielectric film on the semiconductor region. FIG.12illustrates a schematic view of a semiconductor device200A in accordance with some embodiments. The semiconductor device200A is similar to the semiconductor device200except that, in the semiconductor device200A, an additional STI region22′ is formed between the source area31and the body contact28to isolate the source area31from the body contact28. The semiconductor device200A may be made using a method100A similar to the method100except for steps101,102,103, and106.FIGS.13to16illustrate schematic views of the intermediate stages in steps101,102,103, and106of the method100A. Referring toFIG.13, the method100A begins at step101, where a trench210and a trench210′ are formed in the semiconductor layer21. The formation of the trenches210,210′ is similar to that described in step101of the method100, and the details thereof are omitted for the sake of brevity. Referring toFIG.14, the method100A proceeds to step102, a dielectric layer220is formed on the semiconductor layer21to fill the trenches210,210′ shown inFIG.13. The materials and formation for the dielectric layer220are similar to those described in step102of the method100, and the details thereof are omitted for the sake of brevity. Referring toFIG.15, the method100A proceeds to step103, where a planarization process is conducted to remove an excess of the dielectric layer220shown inFIG.14, to expose the semiconductor layer21so as to obtain the STI region22and the additional STI region22′. The planarization process may be similar to that described in step103of the method100, and the details thereof are omitted for the sake of brevity. Referring toFIG.16, the method100A proceeds to step106, where the well region212is formed in the semiconductor layer21to have a first surface portion212aand a second surface portion212bat two opposite sides of the additional STI region22′. Step106of the method100A may be similar to step106of the method100, and the details thereof are omitted for the sake of brevity. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200A. In yet alternative embodiments, additional features may be added in the semiconductor device200A, and some features in the semiconductor device200A may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure. FIG.17illustrates a schematic view of a semiconductor device200B in accordance with some embodiments. The semiconductor device200B is similar to the semiconductor device200A except that, in the semiconductor device200B, a drift region211and a lightly doped source region311are formed within the semiconductor layer21, and a remaining part of the semiconductor layer21serves as a well region213. The well region213is located between the lightly doped source region311and the drift region211. In addition, a channel length (L) is defined by a distance between the lightly doped source region311and the drift region211. The lightly doped source region311may have the first type conductivity, and may have a doping concentration lower than that of the source area31. The well region213has the second type conductivity. The lightly doped source region311is disposed to separate the source area31and the body contact28from the well region213. The semiconductor device200B may be made using a method100B similar to the method100A except that in the method100B: (i) the semiconductor layer21may be lightly doped to have a P-type conductivity for the N-type MOS device or to have an N-type conductivity for the P-type MOS device; (ii) in step105, the drift region211, the lightly doped source region311, and the well region213may be formed simultaneously; and (iii) step106may be omitted. FIG.18illustrates a schematic view of the intermediate stage in step105of the method100B. In step105of the method100B, the drift region211and the lightly doped source region311may be formed simultaneously by (i) forming a patterned mask33on the semiconductor layer21to permit the patterned mask33to be spaced apart from the STI region22and the anti-type doping layer23by a predetermined distance, and (ii) doping the semiconductor layer21through the patterned mask33using an ion implantation process or other suitable processes so as to form the drift region211and the lightly doped source region311at two opposite sides of the patterned mask33. After step105of the method100B, the patterned mask33may be removed, and a remaining part of the semiconductor layer21may serve as the well region213. In alternative embodiments, the patterned mask33may be replaced by a patterned photoresist. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200B. In yet alternative embodiments, additional features may be added in the semiconductor device200B, and some features in the semiconductor device200B may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure. FIG.19illustrates a schematic view of a semiconductor device200C in accordance with some embodiments. The semiconductor device200C is similar to the semiconductor device200except that in the semiconductor device200C, a dielectric film (field oxide region)33and a gate structure37are formed to replace the STI region22and the gate structure27of the semiconductor device200, respectively. The semiconductor device200C may be made using a method100C similar to the method100except that in the method100C, steps301to307are used for replacement of steps101to107of the method100.FIG.20is a flow diagram illustrating steps301to307of the method100C in accordance with some embodiments.FIGS.21to28illustrate schematic views of the intermediate stages of the method100C. Referring toFIGS.20and21, the method100C begins at step301, where a first dielectric layer34and a second dielectric layer35are sequentially formed over a semiconductor layer21. The materials for the semiconductor layer21is similar to those described in step101, and the details thereof are omitted for the sake of brevity. In some embodiments, the first dielectric layer34may be formed by deposition similar to that for the dielectric layer220described in step102, and/or by a thermal oxidation process which may implemented by introducing a thermal vapor to oxidize a surface of the semiconductor layer21. In some embodiments, the second dielectric layer35has a material different from that of the first dielectric layer34, and may be formed by deposition similar to that for the dielectric layer220described in step102. Other suitable processes may be used for formation of the first dielectric layer34and the second dielectric layer35. Referring toFIGS.20and22, the method100C proceeds to step302, where a selective etching process is conducted through a patterned photomask36to partially and selectively etching the second dielectric layer35and to expose a portion of the dielectric layer34. Step302may be implemented using, for example, but not limited to, a dry etching process, a wet etching process, other suitable processes, or combinations thereof. In alternative embodiments, the patterned photomask36may be replaced by a patterned mask layer. Referring toFIGS.20and23, the method100C proceeds to step303, where a dielectric film33is formed in replacement of the exposed portion of the first dielectric layer34. The dielectric film33may include a dielectric material similar to those for the dielectric layer220described in step102, but the material of the dielectric film33is different from those of the first dielectric layer34and the second dielectric layer35. Step303may be implemented by (i) removing the patterned mask layer36shown inFIG.22using an etchant which also etches the exposed portion of the first dielectric layer34and the semiconductor layer21beneath the first dielectric layer34to expose a portion of the semiconductor layer21, (ii) forming the dielectric film33on the exposed portion of the semiconductor layer21(which is not covered by the second dielectric layer35), and (iii) removing the second dielectric layer35and the remaining first dielectric layer34. Other suitable processes may be used for formation of the dielectric film33. The dielectric film33may be also referred to as a field oxide (FOX) region. Referring toFIGS.20and24, the method100C proceeds to step304, where an anti-type doping layer23is formed beneath the FOX region33using a patterned mask24. The formation of the anti-type doping layer23in step304may be similar to that described in step104, and the details thereof are omitted for the sake of brevity. Referring toFIGS.20and25, the method100C proceeds to step305, where a drift region211is formed in the semiconductor layer21using a patterned mask25. Step305may be implemented in a manner similar to step105, and the details thereof are omitted for the sake of brevity. After step305, an upper surface of the drift region211may have a first surface portion211aand a second surface portion211bwhich are located at two opposite sides of the FOX region33and the anti-type doping layer23. Referring toFIGS.20and26, the method100C proceeds to step306, where a well region212is formed in the semiconductor layer21. Step306may be implemented in a manner similar to step106, and the details thereof are omitted for the sake of brevity. After step306, an upper surface of the well region212may have a first surface portion212aand a second surface portion212bwhich are proximate to and distal from the FOX region33, respectively. Referring toFIGS.20and27, the method100C proceeds to step307, where a gate structure37is formed on the semiconductor layer21. The gate structure37includes a gate dielectric371formed on the semiconductor layer21and a gate electrode372formed on the gate dielectric371. The materials and formation for the gate dielectric371and the gate electrode372may be similar to those for the gate dielectric271and the gate electrode272described in step107, and the details thereof are omitted for the sake of brevity. In some embodiments, the gate structure37may be formed over a portion of the FOX region33, a portion of the anti-type doping layer23, the second surface portion211bof the drift region211, and a part212a1of the first surface portion212aof the well region212. The subsequent steps for manufacturing the semiconductor device200C may be similar to steps108and109, and are omitted for the sake of brevity. In some embodiments, the steps for manufacturing the semiconductor device200C may not be performed in the above order. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200C. In yet alternative embodiments, additional features may be added in the semiconductor device200C, and some features in the semiconductor device200C may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure. In the semiconductor device200,200A,200B,200C of this disclosure, because the anti-type doping layer23is provided between the drift region211and the dielectric film (the STI region22or the FOX region33) and has a conductivity type opposite to that of the drift region211, a current in the drift region211is less likely to be influenced by dielectric damages (if any) of the dielectric film22or23. Therefore, the semiconductor device200,200A,200B,200C of this disclosure may have improved performance, such as improved reliability, less leakage current, and so on. In addition, the formation of the anti-type doping layer23may be implanted simply after formation of the dielectric film22or33, and may not influence formation of other elements in the semiconductor device200,200A,200B,200C. In alternative embodiments of this disclose, a doping layer (which may be also exemplified as the anti-type doping layer23) may be provided to direct a current path in a semiconductor region (which may be also exemplified as the drift region211) away from a dielectric film (which may be also exemplified as the STI region22or the FOX region33), thereby reducing an influence of dielectric damages of the dielectric film on the semiconductor region. In accordance with some embodiments of the present disclosure, a semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a dielectric film in a semiconductor layer; forming an anti-type doping layer in the semiconductor layer beneath the dielectric film; and forming a drift region in the semiconductor layer such that the anti-type doping layer is located between the dielectric film and the drift region. The drift region has a first type conductivity and the anti-type doping layer has a second type conductivity opposite to the first type conductivity. In accordance with some embodiments of the present disclosure, a method for reducing an influence of a dielectric film on a semiconductor region is provided. The method includes forming a doping layer which is located between the semiconductor region and the dielectric film and which has a conductivity type so as to direct a current path away from the dielectric film, thereby reducing the influence of the dielectric film. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 31,219 |
11862671 | DETAILED DESCRIPTION OF THE INVENTION (Structure of Semiconductor Device1) An embodiment of the present invention is described below in detail, with reference toFIGS.1to5. FIG.1is a vertical cross-sectional view of a cross-sectional structure of a semiconductor device1according to this embodiment. In this embodiment, the semiconductor device1is an N-channel laterally-diffused MOS (LDMOS) transistor for a breakdown voltage of 60 V. As illustrated inFIG.1, the semiconductor device1includes: a P-type semiconductor substrate2(a semiconductor substrate); a P-type diffusion region3(a semiconductor region); a P-type body region4(a body region); an N-type drift region5(a drift region); an N-type source region6(a source region); a source electrode6a; a P-type body contact region7; an N-type drain region8(a drain region); a drain electrode8a; a gate electrode9; a gate insulating film10; a thick oxide film11; and a shallow trench isolation (STI) structure12. Note that, inFIG.1, a layer denoted with “p” contains a P-type impurity, and a layer denoted with “n” contains an N-type impurity. Moreover, a layer denoted with “p+” contains a P-type impurity higher in concentration than the P-type impurity of the layer denoted with “p”. A layer denoted with “n+” contains an N-type impurity higher in concentration than the N-type impurity of the layer denoted with “n”. The P-type body region4is of the P-type (a first conductivity type). The P-type body region4is formed in a surface layer of the P-type semiconductor substrate2, with, for example, boron ions (11B+) implanted into the surface layer for several times at different acceleration energies (60 to 500 keV). A dose of the ions to be implanted ranges from 1.0E12 to 1.0E13/cm2. The P-type body region4is formed to have a portion exposed to a top face2aof the P-type semiconductor substrate2. The P-type diffusion region3is of the P-type. The P-type diffusion region3has a top face positioned deep in the P-type semiconductor substrate2so that the top face is in contact with a bottom face of the P-type body region4. The P-type diffusion region3is formed to extend, along the top face2aof the P-type semiconductor substrate2, from below the P-type body region4over an area below any of the gate insulating film10, the thick oxide film11, and the STI structure12to be described later. The P-type diffusion region3is formed with, for example, boron ions (11B+) implanted therein at an acceleration energy of 500 to 5000 keV. A dose of the ions to be implanted ranges from 5.0E11 to 5.0E12/cm2. The N-type source region6is of the N-type (a second conductivity type). The N-type source region6in the surface layer of the P-type semiconductor substrate2is formed above, and in contact with, the P-type body region4. The N-type source region6is also exposed to the top face2aof the P-type semiconductor substrate2. The N-type source region6is formed with, for example, phosphorus ions (31P+) implanted therein at an acceleration energy of 35 to 60 KeV. The P-type body contact region7is of the P-type. The P-type body contact region7in the surface layer of the P-type semiconductor substrate2is formed above, and in contact with, the P-type body region4. The P-type body contact region7is also exposed to the top face2aof the P-type semiconductor substrate2. The P-type body contact region7is adjacent to, and in contact with, the N-type source region6. The P-type source region7is formed with, for example, boron ions (31P+) implanted therein at an acceleration energy of 5 to 30 KeV. The source electrode6ais formed on the N-type source region6and the P-type body contact region7. The N-type drift region5is of the N-type. The N-type drift region5is disposed in the surface layer of the P-type semiconductor substrate2, and positioned closer to the top face2aof the semiconductor substrate than to the P-type diffusion region3. The N-type drift region5is formed in contact with the N-type drain region8. The N-type drift region5includes an end portion5apositioned between the P-type body region4and the N-type drain region8. The end portion5ahas a top face exposed to the top face2aof the P-type semiconductor substrate2. Such a structure of the N-type drift region5can avoid contact between the P-type diffusion region3and the N-type drift region5, both of which are high in impurity concentration. Moreover, the N-type drift region5is lower in impurity concentration than the N-type drain region8. The N-type drift region5is formed with, for example, phosphorus ions (31P+) implanted therein for several times at different acceleration energies (140 to 540 keV). A dose of the ions to be implanted ranges from 7.5E11 to 3.5E12/cm2. Note that, in the implantations of the ions to form the N-type drift region5and the P-type diffusion region3, the acceleration energies for the respective implantations are adjusted so that the N-type drift region5avoids contact with the P-type diffusion region3in the depth direction. The N-type drain region8is of the N-type. The N-type drain region8in the surface layer of the P-type semiconductor substrate2is disposed away from the P-type body region4. The N-type drain region8is formed simultaneously with the N-type source region6. The drain electrode8ais formed on the N-type drain region8. The gate insulating film10is formed in an area including: the top face2aof the P-type semiconductor substrate2; a top face of the P-type body region4; and a top face of the end portion of the N-type drift region5. The gate insulating film10is not formed on the top faces of: the N-type source region6; the P-type body contact region7; the N-type drain region8; or the STI structure12. The thick oxide film11is an oxide film formed thickly on the top face of the N-type drift region5to extend from an end, of the gate insulating film10, closer to the N-type drain region8toward the N-type drain region8. The thick oxide film11to be suitably used includes, for example, a local-oxidation-of-silicon (LOCOS) oxide film to be formed by thermal oxidation, or an oxide film (a high temperature oxidation (HTO) film) to be formed by high-temperature oxidation using chemical vapor deposition (CVD). The thick oxide film11is provided to alleviate an electric field. The thick oxide film11is formed thicker than the gate insulating film10. The gate electrode9is disposed above the P-type semiconductor substrate2, between the N-type source region6and the N-type drain region8. The gate electrode9is formed on the gate insulating film10and the thick oxide film11. Hence, the gate electrode9is formed so that, of the gate electrode9, a top face of a portion overlapping the thick oxide film11and of another portion continuing from the portion and overlapping the gate insulating film10is positioned above a top face of the rest of the gate electrode9. Hence, the gate electrode9has a level difference in the intermediate portion. The STI structure12is formed, through the thick oxide film11, at least under an end portion, of the gate electrode9, toward the N-type drain region8. The STI structure12is formed in the thickness direction of the P-type semiconductor substrate2. Moreover, the STI structure12is formed to be buried to a predetermined depth from the top face2aof the P-type semiconductor substrate2(more specifically, from a top face of the N-type drain region8). Furthermore, the STI structure12is formed in an area between: a position away from a boundary between the gate insulating film10and the thick oxide layer11slightly toward the N-type drain region8; and an end of the N-type drain region8. The STI structure12is provided to alleviate an electric field. Note that, in this embodiment, the P-type body region4and the N-type source region6are connected together with the source electrode6a, in order to have the same electric potential. Here, the P-type diffusion region3has an end that defines the area in which the P-type diffusion region3extends. The end is determined by a distance L1(a first distance) and a distance L2(a second distance). The distance L1is a distance in a direction from a first reference position P1below an end, of the P-type body region4, toward the N-type drain region8to the end of the P-type diffusion region3. The distance L1is along the top face2aof the P-type semiconductor substrate2. The distance L2is a distance in a direction from a second reference position P2below an end, of the N-type drain region8, toward the STI structure12to the end of the P-type diffusion region3. The distance L2is along the top face2aof the P-type semiconductor substrate2. The sum of the distance L1and the distance L2is a predetermined value. (Operation of Semiconductor Device1) Here, an operation of the semiconductor device1is described. When a positive electric potential with respect to the P-type body region4is applied to the gate electrode9, a channel is formed between the N-type source region6and the N-type drift region5. The channel is formed in a portion, of the P-type body region4and the P-type semiconductor substrate2, directly below the gate electrode9. As a result, electrons move in a route from the source electrode6ato the drain electrode8athrough the channel. Hence, a current flows between the source electrode6aand the drain electrode8a. (Improvement in Breakdown-Voltage of Semiconductor Device1) As to the semiconductor device1for a breakdown-voltage of 60 V, a simulation of a potential distribution is conducted, while a GND electric potential is provided to the source electrode6aand the gate electrode9, and a voltage of 60 V is applied to the drain electrode8a. Described below is a case where the sum of the distances L1and L2is 3.7 μm. FIG.2is a graph showing a potential distribution in a simulation of the semiconductor device1in a case where the distance L1is 1.2 μm and the distance L2is 2.5 μm.FIG.3is a graph enlarging the above potential distribution in a region A ofFIG.1.FIG.4is a graph enlarging the above potential distribution in a region B ofFIG.1. In the case where the distance L1is 1.2 μm and the distance L2is 2.5 μm,FIGS.2and3show that the region A (a first region), including the end portion5aof the N-type drift region5, has equipotential lines spaced relatively widely, and the potential distribution in the region A is sparse. In contrast, in the case where the distance L1is −0.3 μm and the distance L2is 4.0 μm, although not shown, the region A has the equipotential lines spaced narrower than those in the case where the distance L1is 1.2 μm and the distance L2is 2.5 μm. The potential distribution in the region A is dense. As can be seen, in the case where the distance L1is 1.2 μm and the distance L2is 2.5 μm, the potential distribution in the region A is relatively sparse. It shows that the concentration of the electric field is alleviated in the region A, and so is the electric field on the surface of the semiconductor device1. This means an increase in breakdown voltage. Hence, when the distance L1increases to some extent, an improvement in breakdown-voltage is expected in the region A. If the improvement in breakdown-voltage is sufficient, the breakdown-voltage of the semiconductor device1is determined not by the breakdown-voltage in the region A but by the breakdown voltage in the region B (a second region) between the end of the P-type diffusion region3and the N-type drain region8illustrated inFIG.1. Next, in the case where the distance L1is 1.2 μm and the distance L2is 2.5 μm,FIGS.2and4show that the region B has equipotential lines spaced relatively widely, and the potential distribution in the region B is sparse. In contrast, in the case where the distance L1is 3.7 μm and the distance L2is 0 μm, although not shown, the region B has the equipotential lines spaced narrower than those in the case where the distance L1is 1.2 μm and the distance L2is 2.5 μm. The potential distribution in the region B is dense. As can be seen, in the case where the distance L1is 1.2 μm and the distance L2is 2.5 μm, the potential distribution in the region B is relatively sparse. It shows that the concentration of the electric field is alleviated in the region B. This means that the breakdown-voltage increases as the distance L2increases. In view of the improvement in the breakdown-voltage in the regions A and B, the distances L1and L2are appropriately set to obtain a desired breakdown-voltage. Described next is an improvement in breakdown-voltage observed when the distances L1and L2are set most appropriately.FIG.5is a graph illustrating a relationship between the maximum electric field value and the breakdown-voltage, in the regions A and B, for the two distances L1and L2that define a position of the end of the P-type diffusion region3. InFIG.5, the horizontal axis on the top represents the distance L1. The horizontal axis on the bottom represents the distance L2. The vertical axis on the left represents the maximum electric field value. The vertical axis on the right represents the breakdown-voltage. The sum of the values of the opposing distances L1and L2between the horizontal axes on the top and the bottom is 3.7 μm. As illustrated by the solid line inFIG.5, the maximum electric field value shows a tendency to: decrease as the distance L1increases since the distance L1is −0.3 μm and the distance L2is 4 μm; become smallest when the distance L1is 1 μm and the distance L2is 2.7 μm; and then increase as the distance L1increases. Meanwhile, as illustrated by the dashed line inFIG.5, the breakdown-voltage shows a tendency to: increase as the distance L1increases since the distance L1is −0.3 μm and the distance L2is 4 μm; become largest when the distance L1is 1 μm and the distance L2is 2.7 μm; and then decrease as the distance L1increases. Thanks to such a relationship between the maximum electric field value and the breakdown voltage, the breakdown-voltage is determined to reach 60 V or more among the combinations of the distances L1and L2in which the maximum electric field value is in a range of 0.35 MV/cm or less in the regions A and B. The combinations range from the distance L1of −0.2 μm and the distance L2of 3.9 μm to the distance L1of 2.45 μm and the distance L2of 1.25 μm. Among these combinations, the combination of the distance L1of 1 μm and the distance L2of 2.7 μm achieves the optimum electric field value providing the maximum breakdown-voltage. As can be seen, in this embodiment, a combination of the distances L1and L2is appropriately selected and set, so that the intensity of the electric fields in the regions A and B is 0.35 MV/cm or less. This feature makes it possible to readily avoid reduction in breakdown-voltage caused by avalanche breakdown in the regions A and B, and obtain a breakdown-voltage of 60 V or more. Note that this embodiment shall not be limited to the example described above, and may include various modifications. For example, the above semiconductor device1is described in detail so that an aspect of the present invention is readily understood. The semiconductor device1shall not necessarily be limited to the one including all the constituent features described above. For example, the conditions of the ion implantations to form the respective semiconductor layers are examples, and can be modified as appropriate. In such a case, the sum of the most appropriate distances L1and L2is constant. The sum varies within a range from a combination in which the distance L1has a lowermost value of the first distance and the distance L2has an uppermost value of the second distance to a combination in which the distance L1has an uppermost value of the first distance and the distance L2has a lowermost value of the second distance. Specifically, the distances L1and L2vary within a range of the combinations described above as a preferred example, that is, from the combination of the distance L1of −0.2 μm (the lowermost value of the first distance) and the distance L2of 3.9 μm (the uppermost value of the second distance) to the combination of the distance L1of 2.45 μm (the uppermost value of the first distance) and the distance L2of 1.25 μm (the lowermost value of the second distance). As can be seen, the distances L1and L2can have values of any given combination within the above range. Hence, within the range, the most appropriate distances L1and L2can be selected. Moreover, the embodiment may have a configuration partially replaced with another configuration. The embodiment may also have a configuration additionally including another configuration. Furthermore, the embodiment have a configuration that can be partially subjected to any one of the following; that is, additionally including another configuration, deleted, or replaced with another configuration. As such an example, the semiconductor device1of this embodiment does not have to be limited to an N-channel LDMOS transistor. The semiconductor device1may also be a P-channel LDMOS transistor. Moreover, the target breakdown-voltage of a target device shall not be limited to a particular breakdown-voltage. The lateral size of each of the constituent features, including the distances L1and L2, shall not be limited to a particular size. Furthermore, in the semiconductor device1, such a feature as a lightly doped drain (LDD) implantation may be additionally included to form another transistor. In addition, the semiconductor device1(the N-channel LDMOS transistor) of this embodiment is formed on the P-type semiconductor substrate2. This P-type semiconductor substrate2may be a P-type semiconductor region formed on an N-type epitaxially-buried layer. In such a case, the source electrode and the P-type semiconductor region can be set to have an electric potential different from that of the P-type semiconductor substrate provided through the N-type epitaxially-buried layer. This is a case where the semiconductor device1is assumed to operate as a high-side switch. The breakdown voltage in such a case is defined by a difference in electric potential between the drain electrode and the source electrode. Moreover, this embodiment is assumed to provide an advantageous effect of an aspect of the present invention to an N-channel LDMOS transistor in an N-type diffusion region as described in the Japanese Unexamined Patent Application Publication No. 2009-059949. The thick oxide film11is disposed closer to the N-type source region6than to the STI structure12. This structure varies the distribution of the electric field in the region A, and increases the breakdown-voltage. SUMMARY The semiconductor device1according to a first aspect of the present invention includes: a semiconductor substrate of a first conductivity type; a body region of the first conductivity type, the body region being formed in a surface layer of the semiconductor substrate; a source region of a second conductivity type, the source region being formed in contact with the body region; a drain region of the second conductivity type, the drain region being formed away from the body region; a gate electrode formed between the source region and the drain region; a drift region of the second conductivity type, the drift region being formed in contact with the drain region in the surface layer of the semiconductor substrate, and the drift region having an end portion between the body region and the drain region; a buried oxide layer provided at least under an end portion, of the gate electrode, toward the drain region, the buried oxide layer being formed to be buried from a top face of the semiconductor substrate, and the buried oxide layer being configured to alleviate an electric field; and a semiconductor region of the first conductivity type, the semiconductor region being formed in a position deeper than the body region in order to have contact with a bottom face of the body region, wherein, the semiconductor region is formed to extend in a direction along the top face of the semiconductor substrate, a first distance is in a direction from a first reference position below an end, of the body region, toward the drain region to an end of the semiconductor region, the first distance being along the top face of the semiconductor substrate, a second distance is in a direction from a second reference position below an end, of the drain region, toward the buried oxide layer to the end of the semiconductor region, the second distance being along the top face of the semiconductor substrate, and the first distance and the second distance are set so that an intensity of 0.35 MV/cm or less is observed in an electric field of a first region including the end portion of the drift region and in an electric field of a second region between the end of the semiconductor region and the drain region. Thanks to above configuration, a breakdown-voltage of a desired voltage or more can be obtained when the intensity of the electric fields in the first region and the second region is alleviated to 0.35 MV/cm or less. In the semiconductor device, of a second aspect of the present invention, according to the first aspect, the drift region may be positioned closer to the top face of the semiconductor substrate than to the semiconductor region. Thanks to the above configuration, the semiconductor region and the drift region, both of which are high in concentration, can be kept from contact with each other. In the semiconductor device, of a third aspect of the present invention, according to the first or second aspect, a sum of the first distance and the second distance may be constant, and the sum may be allowed to have a value within a range from a combination in which the first distance has a lowermost value of the first distance and the second distance has an uppermost value of the second distance to a combination in which the first distance has an uppermost value of the first distance and the second distance has a lowermost value of the second distance. Thanks to the above configuration, the most suitable combination of the first distance and the second distance can be selected in the range. While there have been described what are at present considered to be certain embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention. | 22,432 |
11862672 | MODES FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention are described in detail with reference to the accompanying drawings. FIG.1is a plan view of a semiconductor device according to a first preferred embodiment of the present invention.FIG.2is a sectional view taken along a cross-sectional line II-II inFIG.1. InFIG.1andFIG.2, for easy understanding of the contents of the present invention, semiconductor devices before being divided into individual pieces from a wafer are shown. The semiconductor device1is a device using silicon carbide (SiC). A number of semiconductor devices1are regularly aligned and formed on one SiC wafer2. On the SiC wafer2(hereinafter, also referred to as “SiC layer2”), a dicing region4with a predetermined width α (for example, 30 μm to 80 μm) is set to segment a plurality of device regions3. In the present preferred embodiment, the dicing region4is formed in a grid manner, and the plurality of device regions3are aligned in a matrix as a whole. The semiconductor device1is formed in each device region3, and the semiconductor devices are divided into individual pieces by cutting the SiC wafer2along the dicing region4. The semiconductor device1according to the first preferred embodiment is a Schottky barrier diode. The SiC layer2of each semiconductor device cut out by dividing into individual pieces has a first surface2A and a second surface2B, and end faces2C surrounding the first surface2A and the second surface2B. The end faces2C are SiC layer cutting surfaces (side surfaces) appearing by dividing into individual pieces, and segment the outer peripheries of the first surface2A and the second surface2B. In the present preferred embodiment, each semiconductor device1has a chip shape square in a plan view. As the size of the chip, the lengths in the up-down direction and the left-right direction of the sheet ofFIG.1are 0.5 mm to 20 mm. Specifically, the chip size of the semiconductor device1is, for example, 0.5 mm square to 20 mm square. The SiC layer2includes a substrate5composed of n+-type SiC and an epitaxial layer6composed of n−-type SiC formed on the substrate5. The thickness of the substrate5may be 50 μm to 1000 μm, and the thickness of the epitaxial layer6may be 5 μm or more (preferably 6 pm to 20 pm). As an n-type dopant contained in the substrate5and the epitaxial layer6, for example, N (nitrogen), P (phosphorus), As (arsenic), etc., can be used (the same applies to the description given below). As a relationship between the dopant concentration of the substrate5and the dopant concentration of the epitaxial layer6, the dopant concentration of the substrate5is relatively high, and the dopant concentration of the epitaxial layer6is relatively lower than that of the substrate5. In detail, the dopant concentration of the substrate5may be 1×1017to 1×1022cm−3, and the dopant concentration of the epitaxial layer6may be 1×1016cm−3or less (preferably 1×1015to 9×1015cm−3). In the surficial portion of the epitaxial layer6, a p-type voltage relaxing layer7is formed to be exposed to the end portion of the first surface2A. In the present preferred embodiment, the voltage relaxing layer7is formed to be annular along the outer peripheral edge of the SiC layer2so as to be exposed to the corner portions on the first surface2A side of the SiC layer2defined by the first surface2A and the end faces2C of the SiC layer2. Accordingly, the voltage relaxing layer7is exposed to both of the first surface2A and the end faces2C, and the regions exposed to the faces2A and2C are integrated at the corner portion of the SiC layer2. As a p-type dopant contained in the voltage relaxing layer7, for example, B (boron), Al (aluminum), etc., can be used. The voltage relaxing layer7is formed so that the bottom portion thereof is positioned on the first surface2A side with respect to the boundary between the substrate5and the epitaxial layer6. In detail, the depth of the voltage relaxing layer7may be, for example, 1000 to 10000 angstroms. On the SiC layer2, an insulating layer8and an anode electrode9as a surface electrode are formed. The insulating layer8is formed to cover the voltage relaxing layer7, and has a structure consisting of a plurality of layers including a first layer81and a second layer82laminated in order from the SiC layer2. When the insulating layer8has a structure consisting of a plurality of layers, according to the magnitude of the maximum applied voltage (BV) required for the Schottky barrier diode, the kind of insulating layer8can be variously changed. In the present preferred embodiment, the first layer81is formed on the entire first surface2A of the SiC layer2. On the other hand, the second layer82is formed so as to expose the portions on the corners of the first surface2A of the SiC layer2in the first layer81, and has an outer peripheral edge83retreated to the inner side of the SiC layer2with respect to the end faces2C. In detail, the voltage relaxing layer7covered by the insulating layer8is formed to overlap the outer peripheral edge83of the second layer82in the thickness direction of the SiC layer2. Specifically, the inner peripheral edge71of the voltage relaxing layer7is positioned on the inner side of the SiC layer2as compared with the outer peripheral edge83of the second layer82. In the first layer81, a contact hole84that selectively exposes the first surface2A of the SiC layer2is formed. The anode electrode9includes a lower end portion91embedded in the contact hole84and an upper end portion92protruding upward from the first layer81, and the bottom surface of the lower end portion91is connected as a connected portion93to the first surface2A of the SiC layer2inside the contact hole84. The upper end portion92of the anode electrode9further includes a drawn-out portion94as a peripheral edge portion uniformly drawn-out in the horizontal direction (direction along the first surface2A of the SiC layer2) from the outer peripheral edge of the contact hole84. Accordingly, the anode electrode9is formed to have a size larger than the opening diameter of the contact hole84in a plan view. The peripheral edge portion of the upper end portion92of the anode electrode9is covered by the second layer82higher than the anode electrode. That is, in the second layer82, a contact hole85that selectively exposes the central portion of the anode electrode9as a pad area95is formed. The contact hole85is formed so that the relative position of the outer peripheral edge to the end faces2C of the SiC layer2is further inside than the outer peripheral edge of the contact hole84. The detailed size of the contact hole85is, for example, 500 pm×300 pm when a bonding wire with a 125 μm diameter is connected to the pad area95. In the insulating layer8, in the present preferred embodiment, the first layer81is composed of silicon oxide (SiO2) with a thickness of 1 μm or more, and the second layer82is composed of polyimide with a thickness of 0.2 μm or more. However, the materials of the insulating layer8are not limited to these. For example, the first layer81may be composed of polyimide with a thickness of 0.2 μm or more or silicon nitride (SiN) with a thickness of 1 μm or more. Among these materials, in terms of adhesiveness to the SiC layer2, SiO2is most preferable. The anode electrode9can be composed of a material that forms a Schottky barrier or hetero junction with respect to the n-type SiC layer2, specifically, Mo (molybdenum), Ti (titanium), Ni (nickel), or Al (aluminum) as an example of the former material, or polysilicon as an example of the latter material, or the like. That is, the anode electrode9forming a Schottky barrier in this semiconductor device1may be either of a metal electrode that forms a Schottky barrier between the electrode and the SiC layer2, and a semiconductor electrode that is composed of a semiconductor having a band gap different from that of the SiC layer2, and makes a hetero junction to the SiC layer2(junction forming a potential barrier between the electrode and the SiC layer2by utilizing a band gap difference). In this semiconductor device1, when it turns into a forward bias state where a positive voltage is applied to the anode electrode9and a negative voltage is applied to the cathode electrode (not illustrated), electrons (carriers) move from the cathode electrode to the anode electrode9through the SiC layer9and an electric current flows. Accordingly, the semiconductor device1(Schottky barrier diode) operates. Next, a method for manufacturing the semiconductor device1is described with reference toFIG.1toFIG.3.FIG.3is a flowchart for describing an example of a manufacturing process for manufacturing the semiconductor device. First, an SiC wafer2formed of the substrate5and the epitaxial layer6is prepared. In this SiC wafer2, as described above, device regions3in which a plurality of semiconductor devices1are formed, and a dicing region4that segments the device regions3and defines the end faces2C of the plurality of semiconductor devices1to be finally divided into individual pieces and separated from each other, are set in a grid manner. Next, for example, by selectively applying ion implantation and annealing to the first surface2A of the SiC layer2, the voltage relaxing layer7is formed (Step S1). The voltage relaxing layer7is formed along the dicing region4so as to have a width β that is wider than the width α of the dicing region4and across the device regions3adjacent to each other in the middle of manufacturing. That is, in the present preferred embodiment, the voltage relaxing layer7is formed in a grid manner with a width β wider than the width a of the dicing region4(refer to the alternate long and short dash line inFIG.1). Next, according to a known film formation method such as CVD, the first layer81is formed on the entire first surface2A of the SiC layer2(Step S2). Next, the contact holes84that selectively expose the first surface2A of the SiC layer2are formed in the first layer81, and then, for example, by sputtering, the material of the anode electrodes9is deposited and patterned to define the anode electrodes9(Step S3). The anode electrodes9are connected to the SiC layer2(epitaxial layer6) through the contact holes84of the first layer81. Next, by a known film formation method such as CVD, the second layer82is formed on the first layer81so as to cover the entire anode electrodes9(Step S4). Next, by patterning the second layer82, the contact holes85that selectively expose the central portions of the anode electrodes9as pad areas95are formed (Step S5). Simultaneously, the grid-shaped portion along the dicing region4of the second layer82is selectively removed, and the outer peripheral edge83of the second layer82is retreated to the inner side of each device region3with respect to the lines representing the end faces2C. Through the above-described steps, in each device region3, a Schottky barrier diode (semiconductor device structure) is defined by junction between the SiC layer2and the anode electrode9. The next step is measurement of the electric characteristics of each Schottky barrier diode (Step S6). In detail, the anode electrode9of one device region3is set to 0 V, and the second surface of the SiC wafer2is set to 1000 V or more (for example, 1700 V). Accordingly, a maximum applied voltage (BV) that generates a potential difference of 1000 V or more is applied between the anode electrode9and the SiC wafer2, and a withstand voltage of each Schottky barrier diode is measured. At this time, the n-type portion of the SiC wafer2including a part (except for the voltage relaxing layer7) of the dicing region4is fixed to a potential of 1000 V or more, so that between the dicing region4and the anode electrode9, a potential difference of 1000 V or more is generated. Even in this case, according to the present preferred embodiment, the voltage relaxing layer7is formed along the dicing region4, and the voltage relaxing layer7is further covered by the insulating layer8. Therefore, the maximum applied voltage (BV) of 1000 V or more applied between the dicing region4and the anode electrode9can be relaxed in two stages of the insulating layer8and the voltage relaxing layer7. Accordingly, the burden of the voltage on the atmosphere between the dicing region4and the anode electrode9can be eased. In other words, as shown inFIG.2, the voltage applied between the dicing region4and the anode electrode9can be divided by the atmosphere section10, the insulating layer section11, and the voltage relaxing layer section12. Therefore, even when the discharge starting voltage V in the atmosphere section10is made lower than conventionally, the relationship of the discharge starting voltage V>the maximum applied voltage (BV) can be maintained. Here, based on Paschen's Law, the discharge starting voltage V between two electrodes is expressed by a function of the product of a gas pressure P and the interval between the electrodes (in the present preferred embodiment, the distance X1 from the end of the pad area95(outer peripheral edge of the contact hole85) to the dicing region4) (V=f (P·X1)). With this semiconductor device1, the discharge starting voltage V of the atmosphere section10can be made lower than conventionally, so that according to Paschen's Law, the distance X1 can be made shorter than conventionally. Therefore, when the size of the semiconductor device1(chip size) is made equal to the conventional one, the outer edge of the pad area95can be widened to the end face2C side of the SiC layer2, so that the pad area95can be made wider than conventionally. On the other hand, when the size of the pad area95is made equal to the conventional size, the end faces2C of the SiC layer2can be shortened to the pad area95side, so that the number of semiconductor devices1(number of chips) to be obtained from one SiC wafer2can be increased to be larger than conventionally. Furthermore, even if a defect (for example, a hole, etc., caused by a process failure) occurs in one of the insulating layer8and the voltage relaxing layer7, the defect can be covered by the other. Therefore, discharge between the dicing region4and the anode electrode9can be effectively prevented from occurring. Measurement of the electric characteristics of the Schottky barrier diode can be performed in a gas atmosphere of, for example, the atmosphere, nitrogen (N2), hydrogen (H2), argon (Ar), neon (Ne), helium (He), or the like. The gas pressure P at this time is preferably, for example, 720 Torr to 1520 Torr. According to the function V=f (P·X1) of Paschen's Law, as the gas pressure P increases, the discharge starting voltage V also becomes higher. Therefore, by setting the gas pressure P for measurement of the electric characteristics in the above-described range, the distance X1 from the end of the pad area95to the dicing region4(end face2C of the SiC layer2) can be further shortened. Thereafter, the electric characteristics of the Schottky barrier diodes in all device regions3are measured according to the same method. After the measurement, the SiC wafer2is cut into the individual semiconductor devices1by cutting along the dicing region4. Thus, the semiconductor devices1having the structure shown inFIG.2, etc., are obtained. Next, effects relating to the distance X1 from the end of the pad area95to the end face2C of the SiC layer2are described with reference toFIG.4. In the semiconductor device1, it is preferable that the maximum applied voltage (BV) Y (≥1000 V) to be applied to the Schottky barrier diode and the distance X1 from the end of the pad area95to the end face2C of the SiC layer2satisfy the following relational expression (1). In the manufacturing process, it is preferable that the size of the pad area95(the size of the contact hole85) is set so that the maximum applied voltage (BV) Y (≥1000 V) to be applied to the Schottky barrier diode and the distance X1 from the end of the pad area95to the dicing region4satisfy the following relational expression (1) when exposing the pad area95by patterning the second layer82(Step S5). [Numerical expression 2] [Numericalexpression2](855·lnY1053)≦X1≦(855·lnY1053)+100(1) As described above, by providing the insulating layer8and the voltage relaxing layer7, in addition to the atmosphere section10, the insulating layer section11and the voltage relaxing layer section12are interposed between the dicing region4and the anode electrode9. The interposition of the insulating layer8and the voltage relaxing layer7effectively prevents discharge between the dicing region4and the anode electrode9. On the other hand, in the section (section13) between the anode electrode9of one device region3and the anode electrode9of the device region3adjacent to the device region3mentioned above, pad areas95individually exposed are linked to each other via only the atmosphere. Therefore, at the time of measurement of the electric characteristics of the Schottky barrier diode (Step S6), if the maximum applied voltage (BV) (≥1000 V) exceeds the discharge starting voltage V in the atmosphere, discharge may occur between the anode electrodes9adjacent to each other. According to the function V=f (P·X1) of Paschen's Law, as X1 decreases, the discharge starting voltage V also lowers. That is, as a result of the present invention, the distance X1 from the end of the pad area95to the dicing region4(end face2C of the SiC layer2) can be made shorter, however, according to this, the discharge starting voltage V in the section13linked via only the atmosphere also lowers. Therefore, discharge in the section13must be prevented by preventing the maximum applied voltage (BV) from exceeding the discharge starting voltage V in the atmosphere while the distance X1 is kept as short as possible. Therefore, in this semiconductor device1, by satisfying the above-described relational expression (1), discharge between anode electrodes9adjacent to each other can be reliably prevented while the distance X1 from the end of the pad area95to the dicing region4(end face2C of the SiC layer2) can be made shorter than conventionally. In detail, as a result of investigation performed by the inventor of the present invention, the relationship between the discharge starting voltage V between two electrodes linked to each other via only the atmosphere and the discharge distance can be shown by the graph (Y=1.053E+03e5.846E−04X) ofFIG.4(a). In this expression, “E” is an exponential expressed in decimal (the same applies to the description hereinafter). For example, 1.053E+03 expresses 1.053×103. e5.846E−04Xexpresses exp(5.846×10−04−X). Referring toFIG.4(a), in the case where the discharge distance (distance between two electrodes) is 200 μm, 400 μm, or 700 μm, discharge may occur when a potential difference of 1200 V or more, 1300 V or more, or 1600 V or more occurs between the two electrodes. That is, inFIG.4(a), discharge may occur in the case where the coordinates are included in the upper side region (shaded portion) of the graph. The inventor of the present invention further examined the relationship between the maximum applied voltage (BV) Y and the distance X1 in the semiconductor device1based onFIG.4(a). In the semiconductor device1, the distance corresponding to the discharge distance ofFIG.4(a)is the shortest distance between anode electrodes9adjacent to each other. This shortest distance corresponds to 2 times (2(X1)) the distance X1 from the end of each pad area95(outer peripheral edge of the contact hole85) to the dicing region4(to be exact, 2 (X1)+α, however, the width α is ignored here). Therefore, in the semiconductor device1, in the case where the distance X1=100 μm, 200 μm, or 350 pm, when a potential difference of 1200 V or more, 1300 V or more, or 1600 V or more occurs between the anode electrodes9adjacent to each other at the time of measurement of the electric characteristics of the Schottky barrier diode, discharge may occur between these. That is, when the maximum applied voltage (BV) that generates this potential difference is applied to the anode electrode9of one device region3, discharge may occur between this anode electrode and the anode electrode9of the device region3adjacent to the device region3mentioned above. The graph ofFIG.4(b)shows graphically the relationship between the maximum applied voltage (BV) Y and the distance X1 in the semiconductor device1in consideration of the description given above. The graph ofFIG.4(b)shows the function of Y=1.053E+03e1.169E−03X1. By converting this function into an expression for X1, X1=855·In (Y/1053) is obtained. InFIG.4(b), discharge may occur when the coordinates are included in the upper region (shaded portion) of the graph, and discharge is unlikely to occur when the coordinates are included in the lower region. Therefore, in order to reliably prevent discharge from occurring between anode electrodes9adjacent to each other, the coordinates of the maximum applied voltage (BV) Y and the distance X1 must be included in the lower region of the graph. However, even when the coordinates are included in the lower region, the distance X1 is preferably as short as possible to obtain the effects of widening the pad area95and increasing the number of semiconductor devices1to be obtained. Therefore, in the present preferred embodiment, as described above, setting is made so that the maximum applied voltage (BV) Y and the distance X1 satisfy the following relational expression (1). [Numerical expression 3] [Numericalexpression3](855·lnY1053)≦X1≦(855·lnY1053)+100(1) This relational expression (1) shows that the coordinates of the maximum applied voltage (BV) Y and the distance X1 are included in the region (hatched portion) surrounded by X1=855·In (Y/1053) and X1=855·In (Y/1053)+100. Accordingly, while the distance X1 from the end of the pad area95to the dicing region4(end face2C of the SiC layer2) can be made shorter than conventionally, discharge between the anode electrodes9adjacent to each other can be reliably prevented. Next, effects relating to the distance X2 from the end of the connected portion93connected to the SiC layer2of the anode electrode9to the end face2C are described. In the semiconductor device1, the distance X2 from the end of the connected portion93(outer peripheral edge of the contact hole84) connected to the SiC layer2of the anode electrode9to the end face2C is preferably longer than the width X3 of the depletion layer14spreading in the horizontal direction along the first surface2A of the SiC layer2from the connected portion93when the maximum applied voltage (BV) is applied to the Schottky barrier diode. In the manufacturing process, the contact hole84is formed in the first layer81, and when the anode electrode9is connected to the SiC layer2through the contact hole84(Step S3), the relative position of the connected portion93to the dicing region4is preferably set so that the distance X2 from the end of the connected portion93to the dicing region4becomes longer than the width X3 of the depletion layer14. Generally, it is said that the depletion layer in the semiconductor layer composed of SiC extends to two times in the orthogonal direction (horizontal direction) with respect to the thickness direction (vertical direction) of the semiconductor layer. If the distance X2 is shorter than the width X3 of the depletion layer14at the time of application of the maximum applied voltage (BV), when the maximum applied voltage (BV) is applied to each of the semiconductor devices1divided into individual pieces, the depletion layer14may extend to the end face2C of the SiC layer2. Therefore, in this semiconductor device1, by setting distance X2>width X3, the depletion layer14can be prevented from reaching the end face2C of the SiC layer2. In addition, in this semiconductor device1, the outer peripheral edge of the contact hole85which becomes the starting point of the distance X1 is positioned on the inner side of the end faces2C of the SiC layer2as compared with the outer peripheral edge of the contact hole84which becomes the starting point of the distance X2. Therefore, the distance X1 and the distance X2 satisfy X1>X2. Accordingly, by making the setting so that the distance X2 satisfies the relational expression (1) described above, the depletion layer14can be prevented from being exposed at the end face2C, and simultaneously, discharge between the anode electrodes9adjacent to each other can be reliably prevented. Here, an example of the distance X2 is described by using detailed numerical values. For example, when the impurity concentration of the epitaxial layer6is 7×1015cm−3and the thickness thereof is 7 pm, the maximum applied voltage (BV) becomes 1450V, theoretically. In this case, theoretically, the depletion layer14extends by 15.2 pm in the vertical direction of the epitaxial layer6. Therefore, theoretically, the width X3 in the horizontal direction of the depletion layer14becomes 30.4 μm. The distance X2 is required to be longer than the width X3, so that under this condition, the distance becomes X2>30.4 pm. On the other hand, when the maximum applied voltage (BV) is 1450 V, the discharge distance in the atmosphere becomes 550 μm with reference toFIG.4(a). To reliably prevent discharge between the adjacent anode electrodes9, the distance X2 is required to be longer than ½ of this discharge distance, so that the distance becomes X2>275 μm. That is, to prevent only exposure of the depletion layer14at the end face2C, the distance becomes X2>30.4 pm, and to prevent discharge between the anode electrodes9adjacent to each other as well, the distance X2>275 pm. FIG.6toFIG.14are drawings for describing constitutions of semiconductor devices according to the second to eighth preferred embodiments of the present invention. InFIG.6toFIG.14, portions corresponding to each portion shown inFIG.2described above are designated by the same reference symbols. In the semiconductor device102shown inFIG.6according to the second preferred embodiment, a termination structure15is further formed in the SiC layer2. The termination structure15is formed to be annular along the periphery of the anode electrode9, and is across the inside and the outside of the contact hole84of the first layer81. By this termination structure15, the degree of spreading of the depletion layer14(refer toFIG.5) from the connected portion93of the anode electrode9can be adjusted. Furthermore, by adjusting the impurity concentration of the termination structure15, the maximum applied voltage (BV) of the Schottky barrier diode can also be adjusted. Furthermore, a plurality of termination structures may be formed concentrically as in the semiconductor device103(third preferred embodiment) shown inFIG.7. In the first preferred embodiment, the voltage relaxing layer7is formed to overlap the outer peripheral edge83of the second layer82in the thickness direction of the SiC layer2, however, the voltage relaxing layer7may be formed so as not to overlap the outer peripheral edge83of the second layer82as in the semiconductor device104(fourth preferred embodiment) shown inFIG.8. Specifically, the inner peripheral edge71of the voltage relaxing layer7may be positioned on the outer side of the SiC layer2as compared with the outer peripheral edge83of the second layer82. In the first preferred embodiment, only the first layer81is formed on the entire first surface2A of the SiC layer2, however, both of the first layer81and the second layer82may be formed on the entire first surface2A of the SiC layer2as in the semiconductor deice105(fifth preferred embodiment) shown inFIG.9. In the semiconductor devices106and107shown inFIG.10andFIG.11according to the sixth and seventh preferred embodiments, the second layer82has a convex portion86that selectively penetrates the first layer81and reaches the first surface2A of the SiC layer2. Only one convex portion86may be formed as shown inFIG.10, or a plurality of the convex portions may be formed as shown inFIG.11. With this arrangement, even if the first layer81peels from the end face2C of the SiC layer2, this peeling can be stopped by the convex portion86of the second layer82. Therefore, adhesion of the insulating layer8to the SiC layer2can be improved. In the first preferred embodiment, the insulating layer8has a structure composed of a plurality of layers including the first layer81and the second layer82, however, the insulating layer8may have a structure composed of a single layer as in the semiconductor device108(eighth preferred embodiment) shown inFIG.12. In the first preferred embodiment described above, the semiconductor device structure formed in the SiC layer2is a Schottky barrier diode structure including the SiC layer2and the anode electrode9that forms a Schottky barrier between the anode electrode and the SiC layer2, however, in the semiconductor device109shown inFIG.13, an MIS (Metal Insulator Semiconductor) transistor structure is formed as a semiconductor device structure. The MIS transistor structure includes the SiC layer2, the p-type channel regions16, the n+-type source regions17, the p+-type channel contact regions18, the gate insulating film19, and the gate electrode20. The semiconductor device109further includes an interlayer insulating film21and a source electrode22as a surface electrode as components attached to the MIS transistor structure. The channel regions16are selectively formed in the surficial portion of the epitaxial layer6, for example, in a plurality of regions discretely disposed periodically on the SiC layer2. The channel regions16may be disposed in, for example, a matrix, zigzag, or striped manner. The source region17is formed in the inside region of the channel region16. In this region, the source region17is selectively formed in the surficial portion of the channel region16. The source region17is formed inside the channel region16so as to be positioned at a predetermined distance inward from the interface between the channel region16and the epitaxial layer6. Accordingly, in the surface layer region of the semiconductor layer including the epitaxial layer6and the channel region16, etc., between the source region17and the epitaxial layer6, the surficial portion of the channel region16is interposed, and this interposed surficial portion provides the channel portion23. The channel contact region18penetrates through the source region17and is connected to the channel region18. The gate insulating film19may be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, or the like. The gate insulating film19is formed to cover at least the surfaces of the channel regions16in the channel portions23. The gate electrode20is formed such that it is opposed to the channel portions23via the gate insulating film19. The gate electrode20may be composed of polysilicon that is reduced in resistance by implanting impurities. In the present preferred embodiment, the gate electrode20is formed in almost the same pattern as that of the gate insulating film19, and covers the surfaces of the gate insulating film19. Accordingly, a planar gate structure is arranged. The interlayer insulating film21can be formed as, for example, an extended portion obtained by extending the first layer81along the first surface2A of the SiC layer2. The interlayer insulating film21is formed in a pattern that covers the upper surfaces and side surfaces of the gate electrode20and has contact holes24in the central regions of the channel regions16and the inner edge regions of the source regions17linked to the central regions. The source electrode22is composed of aluminum (Al) and other metals. The source electrode22is formed to cover the surfaces of the interlayer insulating film21and be embedded in the contact holes24. Accordingly, the source electrode22forms an ohmic contact with the source regions17. Examples of a planar profile of the source electrode22are shown inFIG.14(a)toFIG.14(c). InFIG.14(a)toFIG.14(c), the source electrode22is formed to cover almost the entire area of the surface of the semiconductor device109. In a part of the source electrode22, a removed region25is selectively formed. In the removed region25, a terminal to be electrically connected to the gate electrode20is formed. In detail, inFIG.14(a)andFIG.14(b), gate pads26and27are respectively formed, and inFIG.14(c), gate fingers28are formed. A part of the source electrode22is exposed as a pad area221from the contact hole85of the second layer82of the insulating layer8. This semiconductor device109may include a p-type annular region29surrounding the MIS transistor structure in the SiC layer2, and a contact region30formed in the surficial portion of the annular region29. The annular region29and the contact region30may be exposed from the contact hole84of the first layer81. That is, when the source electrode22as a surface electrode is connected at a plurality of points of the SiC layer2, the outermost connected portion (in the present preferred embodiment, the connected portion222connected to the contact region30) corresponds to the “connected portion connected to the SiC layer of the surface layer” of the present invention. In this ninth preferred embodiment, a planar gate structure is described as an example of the MIS transistor structure, however, the MIS transistor structure may be a trench-gate structure. Preferred embodiments of the present invention are described above, however, the present invention may be carried out in other modes. For example, an arrangement in which the conductive-types of each semiconductor portion of the semiconductor devices1,101to109are inverted may be adopted. For example, in the semiconductor device1, the p-type portion may be n-type, and the n-type portion may be p-type. The voltage relaxing layer7must be a conductive-type (in the preferred embodiments described above, p-type) different from that of the SiC layer2, However, a portion of its inside region may have the same conductive-type as that of the SiC layer2. For example, the voltage relaxing layer7may have an n-type region positioned at a predetermined distance inward from the interface between the voltage relaxing layer7and the epitaxial layer6. As the n-type region is formed, for example, in the arrangement shown inFIG.13, charge-up can be prevented when forming the n+-type source region17by ion implantation. The semiconductor device (semiconductor power device) according to the present invention can be installed in a power module that is used in an inverter circuit constituting a drive circuit for driving an electric motor to be used as a power source of, for example, an electric vehicle (including a hybrid vehicle), train, an industrial robot, or the like. The semiconductor device can also be installed in a power module to be used in an inverter circuit that converts electric power generated by a power generator (in particular, private electric generator) such as a solar cell, a wind power generator, or the like, so as to match electric power of a commercial power source. The features understood from the disclosure of the above-described preferred embodiments may also be combined between different preferred embodiments. Furthermore, the components presented in the preferred embodiments may be combined within the scope of the present invention. In addition, various design changes are possible within the scope of the matters described in the claims. DESCRIPTION OF REFERENCE SIGNS 1: semiconductor device2: SiC wafer (SiC layer)2A: first surface2B: second surface2C: end face3: device region4: dicing region5: substrate6: epitaxial layer7: voltage relaxing layer8: insulating layer81: first layer82: second layer83: outer peripheral edge86: convex portion9: anode electrode93: connected portion95: pad area14: depletion layer15: termination structure16: channel region17: source region19: gate insulating film20: gate electrode22: source electrode221: pad area222: connected portion102: semiconductor device103: semiconductor device104: semiconductor device105: semiconductor device106: semiconductor device107: semiconductor device108: semiconductor device109: semiconductor device | 36,430 |
11862673 | DETAILED DESCRIPTION Embodiments generally relate to semiconductor devices. More particularly, some embodiments relate to Schottky diode devices. Aspects of the present disclosure and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the disclosure in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the disclosure, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. The non-limiting embodiments described below in context of the devices are analogously valid for the respective methods, and vice versa. Furthermore, it will be understood that the embodiments described below may be combined; for example, a part of one embodiment may be combined with a part of another embodiment. Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. The word “or” is intended to include “and” unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains”one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed. It should be understood that the terms “on”, “over”, “top”, “bottom”, “down”, “side”, “back”, “left”, “right”, “front”, “lateral”, “vertical”, “side”, “up”, “down” etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of any device, or structure or any part of any device or structure. Similarly, the term “in” as used herein is not intended to limit a thing to be fully enclosed by something else. Further, the term “width” is intended to mean a length extending in the lateral direction with reference to the relevant drawings; the term “depth” is intended to mean a length extending in the vertical direction with reference to the relevant drawings. As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,”however, can mean a direct connection or a connection through one or more intermediary elements. The term “coupled” (or “connected”) herein may be understood as electrically coupled or as mechanically coupled, for example attached or fixed, or just in contact without any fixation, and it will be understood that both direct coupling or indirect coupling (in other words: coupling without direct contact) may be provided. According to various non-limiting embodiments, a device may include: a buried oxide layer disposed on a substrate; a first region disposed on the buried oxide layer; a first ring region disposed in the first region, the first ring region comprising a portion of a guardring; a first terminal region disposed in the first ring region, the first terminal region being connected to an anode; a second ring region disposed in the first region; a second terminal region disposed in the second ring region, the second terminal region being connected to a cathode; wherein the first region has a graded doping concentration; wherein the first region, the second ring region, and the second terminal region have a first conductivity type; wherein the first ring region and the first terminal region have a second conductivity type; and wherein the first conductivity type is different from the second conductivity type. According to various non-limiting embodiments, the first region may have a rounded shape and the doping concentration of the first region may increase in a radial direction from a center of the first region to a perimeter of the first region. According to various non-limiting embodiments, the first region may comprise a plurality of concentric ring portions that has been annealed, and the doping concentration of the first region may increase in a radial direction from a center ring portion to a perimeter ring portion. According to various non-limiting embodiments, the plurality of the concentric ring portions may be located concentric with the first ring region and the second ring region. According to various non-limiting embodiments, the first region may further comprise a plurality of substrate portions in between the plurality of concentric ring portions. According to various non-limiting embodiments, the device may further comprise a first isolation region disposed in the first region, an inner edge of the first isolation region being in direct contact with the first ring region, an outer edge end of the first isolation region being in contact with the second terminal region and the second ring region. According to various non-limiting embodiments, the device may further comprise a first field poly plate disposed over the first isolation region, the first field poly plate being connected to the anode. According to various non-limiting embodiments, the first field poly plate may be disconnected with the first and second terminal regions. According to various non-limiting embodiments, the first ring region may comprise a discontinuous guardring portion. According to various non-limiting embodiments, the discontinuous guardring portion may comprise a plurality of guardring portions spaced apart by a plurality of gap portions. According to various non-limiting embodiments, the plurality of guardring portions may have a length larger than a length of the plurality of gap portions. According to various non-limiting embodiments, the device may further comprise a second isolation region at least partially disposed in the first region, the second isolation region extends laterally from the second ring region, a first end of the second isolation region being in direct contact with the second terminal region and the second region; and a deep isolation region in direct contact with the second isolation region and extending to the buried oxide layer. According to various non-limiting embodiments, the device may further comprise a silicide layer disposed over the first terminal region, the first ring region and the first region, wherein the first terminal region is connected to the anode through the silicide layer. According to various non-limiting embodiments, the device may further comprise a second region; a third region disposed in the second region, the third region being connected to a drain and in direct contact with the buried oxide layer; a third ring region disposed in the second region, the third ring region being connected to a source and in direct contact with the buried oxide layer; and a third isolation region disposed in the second region extending between the third region and the third ring region, the third isolation region being in direct contact with the third region, wherein a second end of the second isolation region is in direct contact with the third ring region; wherein the deep isolation region is located between the second ring region and the third ring region; wherein the second region and the third region have a first conductivity type; and wherein the third ring region has a second conductivity type. According to various non-limiting embodiments, the device may further comprise a second field poly plate disposed over the third isolation region, the second region and the third ring region. According to various non-limiting embodiments, the first, second terminal regions may comprise a first, second terminal ring regions. According to various non-limiting embodiments, a doping concentration of the second ring region may be lower than a doping concentration of the first region. According to various non-limiting embodiments, the first region may be a drift region. According to various non-limiting embodiments, a method for manufacturing a device may include: providing a buried oxide layer on a substrate; providing a first region on the buried oxide layer; providing a first ring region and a second ring region in the first region; and providing a first terminal region disposed in the first ring region and a second terminal region in the second ring region, the first terminal region being connected to an anode and the second terminal region being connected to a cathode, wherein providing the first region comprises: using a photoresist mask when doping the first region; and annealing the first region after doping the first region; wherein the photoresist mask has a plurality of concentric rings; and wherein the first region, the second ring region, and the second terminal region have a first conductivity type; wherein the first ring region and the first terminal region have a second conductivity type; and wherein the first conductivity type is different from the second conductivity type. FIG.1Ashows a top view of a device100aandFIG.1Bshows a top view of a device100bfor high voltage applications according to various embodiments of the present disclosure.FIG.2shows a cross-sectional view of the device100aand the device100b(hereafter “the device100”) along the A-A′ line. The device100will be described in details below with reference toFIG.1A and1BandFIG.2. The device100may include a buried oxide layer109disposed on a substrate108. The substrate108may be an Epitaxial (EPI) or Silicon-on-Insulator (SOI) substrate for high reverse breakdown voltages. The buried oxide layer109may isolate any regions disposed thereabove as introduced later from the substrate108. The device100may further include a first region110disposed on the buried oxide layer109, and a first ring region120(shown as120ainFIG.1A and120binFIG.1B) disposed in the first region110, the first ring region120may be a well region. The first ring region120may include a portion of a guardring that is lightly doped to prevent leakage current under reverse state. Referring toFIG.2, the first ring region120, in a cross-sectional view, may include a first portion121and a second portion122of the first ring region120. The device100may further include a first terminal region130disposed in the first ring region120, and the first terminal region130may be connected to an anode101. The first terminal region130may also be a ring-shaped region. The first terminal region130, in a cross-sectional view, may include a first portion131and a second portion132of the first terminal region130disposed in the first portion121and the second portion122of the first ring region120, respectively. The device100may further include a second ring region140at least partially disposed in the first region110and a second terminal region150disposed in the second ring region140, and the second terminal region150may be connected to a cathode102. The second ring region140may be a middle voltage well region that is low doped to obtain high reverse breakdown voltage in cathode area. Referring toFIG.2, the second ring region140, in a cross-sectional view, may include a first portion141and a second portion142of the second ring region140. The second terminal region150may also be a ring-shaped region. The second terminal region150, in a cross-sectional view, may include a first portion151and a second portion152of the second terminal region150disposed in the first portion141and the second portion142of the second ring region140, respectively. The second ring region140may surround the first ring region120. The second ring region140may be spaced away from the first ring region120. Additionally, the second ring region140may be concentric with the first ring region120. Furthermore, the first ring region120may be disposed near a center of the first region110and the second ring region140may be disposed at or near a perimeter of the first region110. The first region110, the second ring region140, and the second terminal region150may have a first conductivity type, and the substrate108, the first ring region120and the first terminal region130may have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type may be n-type and the second conductivity type may be p-type. The first region110may be a drift region and have a graded doping concentration. That is, the doping concentration of the first region110may vary across the first region110rather than being uniformly distributed throughout the first region110. The first region110may have a rounded shape, for example a circle shape or an oval shape. The doping concentration of the first region110may increase in a radial direction from a center area of the first region110to a perimeter area of the first region110. Said differently, the doping concentration of the first region110may be lowest at the center area of the first ring region120and may gradually increase in a direction moving towards the second ring region140. To provide the graded doping concentration, different portions of the first region110may be implanted to have the doping concentration increase in a step-wise manner. That is, the first region110may include a plurality of concentric ring (or annulus) portions111to116, and the doping concentration of the first region110may increase in a radial direction from a center ring portion111to a perimeter ring portion116, as shown inFIGS.1A and1B. It should be appreciated that the “ring” or “annulus” portions are used herein to describe the general shape of the plurality of concentric ring (or annulus) portions111to116. The “ring” or “annulus”portions may include discontinuities. In an example, thicknesses of the ring portions may be in a range from 0.18 um to 2.5 um and the two adjacent ring portions may be spaced out by a distance in a range from 0.22 um to 3 um. A thickness of a respective ring portion is defined herein as the minimum distance between the inner perimeter and the outer perimeter of the ring portion, for example, the thickness of the ring portion114is denoted as “t” as shown inFIG.1A and1B. A distance of the two consecutively adjacent ring portions including an inner ring portion and an outer ring portion is defined herein as the minimum distance between the inner perimeter of the outer ring portion and the outer perimeter of the inner ring portion, for example, the distance of the ring portion115is denoted as “d” as shown inFIG.1B. A thickness of the ring portion111may be smaller than a thickness of the ring portion112, the thickness of the ring portion112may be smaller than a thickness of the ring portion113, the thickness of the ring portion113may be smaller than a thickness of the ring portion114, the thickness of the ring portion114may be smaller than a thickness of the ring portion115, and the thickness of the ring portion115may be smaller than a thickness of the ring portion116. The first region110may further include a plurality of substrate portions in between the plurality of concentric ring portions111to116. A thickness of the substrate portion in between the ring portion111and the ring portion112may be smaller than or equal to a thickness of the substrate portion in between the ring portion112and the ring portion113, and so forth. While six concentric ring portions have been presented herein, it should be appreciated that the number of concentric ring portions may be more or less than six, and the exemplary number of six is not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. The plurality of the concentric ring portions111to116may be substantially located concentric with the first ring region120and the second ring region140. It should be appreciated that being concentric provides direct and quick current paths between the ring regions; however, the ring regions may not be concentric and instead eccentric with an inner ring region being at least partially enclosed by an outer ring region. As will be discussed further herein, the first region110including the plurality of concentric ring portions111-116may be further annealed to provide a gradual graded doping. The concentric ring portions111to116may not be clearly defined after annealing which may depend on a distance between the adjacent ring portions and/or a thickness of the ring portion. The concentric ring portions111to116illustrated inFIGS.1A-1Billustrate an example of a possible arrangement of the plurality of concentric ring portions111-116prior to annealing relative to the first ring region120. In an example, the first ring region120may include a continuous guardring portion120aas shown inFIG.1Aand in another example, the first ring region120may include a digitated discontinuous guardring portion120bas shown inFIG.1B. The device100amay include the features of the device100bexcept for the feature120awhereas the device100bhas the different feature120bas discussed herein. The digitated discontinuous guardring portion120bmay include a plurality of guardring portions spaced apart by a plurality of gap portions. The plurality of guardring portions may include multiple guardring portions having a same length (denoted as “SW”) and the multiple guardring portions having the same length may be arranged in two parallel lines. One of the multiple guardring portions in one of the parallel lines may be in alignment with another multiple guardring portion in the other of the parallel lines. The plurality of guardring portions may also include two half ring portions arranged at each end of the two parallel lines. The plurality of gap portions may have a same length (denoted as “SS”) that is smaller than or equal to the length SWof the plurality of guardring portions. Greater details will be discussed below. The device100may further include a first isolation region160disposed in the first region110. The first isolation region160may be ring shaped. The isolation regions discussed herein may be shallow trench isolation (STI) or local oxidation of silicon (LOCOS) regions and have a cross-section of a trapezoid or a hexagonal prism. An inner edge of the first isolation region160may be in direct contact with the first ring region120, and an outer edge end of the first isolation region160may be in direct contact with the second terminal region140and the second ring region150. The inner edge of the first isolation region160may be spaced apart with the first terminal region130so as to reduce leakage under the off state. Referring toFIG.2, the first isolation region160, in a cross-sectional view, may include a first portion161and a second portion162of the first isolation region160. The first portion161of the first isolation region160extends between the first portion131of the first terminal region130and the first portion151of the second terminal region150, and the second portion162of the first isolation region160extends between the second portion132of the first terminal region130and the second portion152of the second terminal region150. The device100may further include a first field poly plate170disposed over the first isolation region160. The first field poly plate170may be ring shaped. The first field poly plate170may be connected to the anode101and disconnected with the first and second terminal regions130,150. The first field poly plate170, in a cross-sectional view, may include a first portion171and a second portion172of the first field poly plate170. The first portion171of the first field poly plate170is disposed over the first portion161of the first isolation region160and the second portion172of the first field poly plate170is disposed over the second portion162of the first isolation region160. The first, second terminal regions130,150may include ring regions concentric with the first, second ring regions120,140. The first isolation region160, the first field poly plate170may also include ring regions concentric with the first, second ring regions120,140. The device100may further include a second isolation region180at least partially disposed in the first region110. The second isolation region180may be ring shaped. The second isolation region180may extend laterally from the second ring region140, a first end of the second isolation region180being in direct contact with the second terminal region150and the second region140. In alternative embodiments, the first end of the second isolation region180may be spaced apart from the second terminal region150and the second region140. The device100may further include a deep isolation region190in direct contact with the second isolation region180and extending to the buried oxide layer109. The second isolation region180, in a cross-sectional view, may include a first portion181and a second portion182of the second isolation region180. The second isolation region180and the deep isolation region190may include a square region enclosing the first region110, the first ring region120and the second ring region140, thereby no leakage path through the substrate108. The deep isolation region190, in a cross-sectional view, may include a first portion191and a second portion192of the deep isolation region190, with the first portion191in direct contact with the first portion181of the second isolation region180and the second portion192in direct contact with the second portion182of the second isolation region180. The second isolation region180may be integrated with the deep isolation region190and have the same material composition. The device100may further include a silicide layer103disposed over the first terminal region130, the first ring region120and the first region110, wherein the first terminal region120is connected to the anode101through the silicide layer103. The silicide layer may help guide current flow to the anode101. In various non-limiting embodiments, the substrate108may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, Epitaxial (EPI) Si, silicon-on-sapphire (SOS), silicon-on-insulator (SOI) or silicon-on-replacement insulator (SRI) or silicon germanium substrates and the like. The substrate108may in addition or instead include various isolations, dopings and/or device features. The substrate108may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), aluminium nitride (AlN), indium nitride (InN), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, AlGaN, or GaInAsP, or combinations thereof. FIG.3shows a partial equivalent circuit of the device100. Graded doping concentration of the first region110provides a lower resistance R from the cathode102to the anode101and accordingly lower forwarding voltages and higher reverse breakdown voltages of the device100. Furthermore, the buried oxide layer109disconnects the collector substrate108and therefore prevents a parasitic bipolar junction transistor (BJT) formed by the first terminal region130, the first ring region120, the first region110and the substrate108. Additionally, double reduced-surface-field effect (RESURF) from the field poly plate170and the buried oxide layer109promotes higher reverse breakdown voltages. FIG.4shows simulated total current densities for the device100in technology computer aided design (TCAD). The intensive contours of total current density are present from the cathode102to the anode101, with stronger currents401located at lower doping concentration ring portions of the first region110and weaker currents402located at higher doping concentration ring portions. RESURF can also been seen fromFIG.4. FIG.5shows a cross section view of the device100along the B-B′ line ofFIG.1(B)according to various embodiments of the present disclosure. The B-B′ line comes across the gap portions of the first ring region120and accordingly, the first ring region120including the guardring portion is absent inFIG.5. FIG.6Ashows the forwarding voltages of the device100ofFIG.1AandFIG.6Bshows the breakdown voltages of the device100ofFIG.1A, when the anode length (denoted as “L” inFIG.1AandFIG.2) is 0.5 um, 1 um and 2 um. As it can be seen from Graph601and Graph602when the anode length is 0.5um, the forwarding voltage is 0.64V as the current is 0.1 uA and 0.70V as the current is 1 uA, and the breakdown voltage is 86V. As the anode length increases to 1 um and as seen from Graph603and Graph604, the forwarding voltage is 0.4V as the current is 0.1 uA and 0.53V as the current is 1 uA, and the breakdown voltage is 54V. As the anode length further increases to 2 um and as seen from Graph605and Graph606, the forwarding voltage is 0.33V as the current is 0.1 uA and 0.44V as the current is 1 uA, and the breakdown voltage is 54V. Accordingly, both the forwarding voltage and the breakdown voltage decrease as the anode length increases from 0.5 um to 2 um. Therefore, a suitable and optimum value of the anode length can be achieved from the present disclosure. FIG.7Ashows the forwarding voltages of the device100ofFIG.1Bwhen the anode length is 1.0 um and 1.4 um, and the length SSof plurality of gap portions is 1 um and equal to the length SWof the plurality of guardring portions of the first ring region120b.FIG.7Bshows the breakdown voltages of the device100ofFIG.1Bwhen the anode length is 1 um and 1.4 um, and SSis 1.4 um, smaller than SWwhich is 1.8 um. As it can be seen from Graph701and Graph702when the anode length, SSand SWare at 1 um, the forwarding voltage is 0.34V as the current is 0.1 uA and 0.40V as the current is 1 uA, and the breakdown voltage is 78V. As the anode length and SSincrease to 1.4 um and SWincreases to 1.8 um, Graph703shows that the forwarding voltage is 0.35V as the current is 0.1 uA and 0.42V as the current is 1 uA, and Graph704shows that the breakdown voltage is 50V. Accordingly, the forwarding voltage does not change significantly and the breakdown voltage increases as the anode length and SSdecreases from 1.4 um to 1.0 um and SWdecreases from 1.8 um to 1 um. Therefore, the anode length, SS, SWcan be varied to achieve optimum forwarding voltages and breakdown voltages from the present disclosure. FIGS.8A to8Dshow simplified cross-sectional views that illustrate a method800for fabricating the device100according to various non-limiting embodiments. Referring toFIG.8A, the method800may include providing a buried oxide layer109on a substrate108and providing a first region110on the buried oxide layer109. Providing the first region110may include using a photoresist mask810when doping the first region110as shown inFIG.8Aand annealing the first region110after doping the first region110to allow the activation and diffusion of dopants as shown inFIG.8B. For example, the photoresist mask810may have a pattern including a plurality of concentric ring patterns811,812,813,814for providing a plurality of concentric ring portions111,112,113,114in the first region110, and the sizes of the ring patterns may increase in a radial direction from the center concentric ring patterns811,812, to the perimeter concentric ring pattern814corresponding to the thicknesses of the plurality of concentric ring portions111,112,113,114. It shall be appreciated that the number of the concentric rings shown is just for illustration and provides those skilled in the art with a convenient road map for fabricating the devices. For example, the center ring portion111of the first region110may be formed by doping the region in between the concentric ring patterns811,812. During doping the first region110, the doping material is directed into the specific areas820where no patterns of the plurality of concentric ring patterns811to814exist, as shown by the arrows in820. The plurality of the concentric ring patterns811to814may have sizes in a range from 0.22 um to 3 um and be spaced out by distances in a range of 0.18 um to 2.5 um. As shown inFIG.8C, the method800may further include providing a first isolation region160and a second isolation180disposed in the first region110, and providing a deep isolation region190being in direct contact with the buried oxide layer109. As shown inFIG.8D, the method800may further include providing a first ring region120and a second ring region140in the first region110, providing a first terminal region130disposed in the first ring region120and a second terminal region150disposed in the second ring region140, and providing a first field poly plate170. The first terminal region130may be connected to the anode101and the second terminal region150connected to the cathode102. Now referring toFIG.9, a device200is presented according to other various non-limiting embodiments. The device200may include the features of the device100as described above in connection toFIG.2, and therefore, the common features are labelled with the same reference numerals and need not be discussed. The device200may further include a Laterally Diffused N-type Metal Oxide Semiconductor (LDNMOS) region200a, which includes a second region210, and a third region220disposed in the second region210, the third region220being connected to a drain201and in direct contact with the buried oxide layer109. The second region210may be a draft region and the third region220may be a middle voltage well region. The LDNMOS region200amay further include a third ring region230disposed at least partially in the second region210and the third ring region230may be connected to a source202and in direct contact with the buried oxide layer109. The third ring region230may be a middle voltage well region. The LDNMOS region200amay also include a third isolation region240disposed in the second region210extending between the third region220and the third ring region230. The third isolation region240may be in direct contact with the third region220. A second end of the second isolation region180may be in direct contact with the third ring region230, and the deep isolation region190may be located between the second ring region140and the third ring region230. The second region210and the third region220may have a first conductivity type and the third ring region230may have a second conductivity type. The ring regions in the LDNMOS region200amay be concentric with the ring regions of the device100that is the Schottky diode region. Alternatively, the ring regions in the LDNMOS region200amay be concentric with the ring regions of the device100in accordance with operation voltage ratings. The LDNMOS region200amay further include a second field poly plate250disposed over the third isolation region240, the second region210and the third ring region230. The LDNMOS region200amay also include a fourth isolation region260expanding from the third ring region230and an additional deep isolation region270in direct contact with the fourth isolation region260and the buried oxide layer109. FIGS.10A to10Dshow simplified cross-sectional views that illustrate a method900for fabricating the device200according to various non-limiting embodiments. The method900may include the steps of the method800as described above in connection toFIGS.8A to8D. Referring toFIG.10A, the method900may include providing a buried oxide layer109on a substrate108and providing a first region110on the buried oxide layer109. The method may also include providing a second region210on the buried oxide layer109. Providing the first region110may include using a photoresist mask910when doping the first region110and the second region210as shown inFIG.10Aand annealing after doping as shown inFIG.10B. The photoresist mask910may have a pattern including a plurality of concentric ring patterns911to914configured to provide the plurality of concentric ring portions111to114, and the sizes of the ring patterns may increase in a radial direction from the center ring patterns911,912to the perimeter ring pattern914, in a similar manner as the photoresist mask810. The photoresist mask910may further include an opening919where the second region210is deposited with doping materials. As shown inFIG.10C, the method900may further include providing a first isolation region160and a second isolation180disposed in the first region110, and providing a deep isolation region190being in direct contact with the buried oxide layer109. The method900may also include providing a third isolation region240, a fourth isolation region260and an additional deep isolation region270. As shown inFIG.10D, the method900may further include providing a first ring region120and a second ring region140in the first region110, providing a first terminal region130disposed in the first ring region120and a second terminal region150disposed in the second ring region140, and providing a first field poly plate170. The first terminal region130may be connected to the anode101and the second terminal region150connected to the cathode102. The method900may also include providing a second region210, a third region220, a third ring region230and a second field poly plate250. The third region220may be connected to a drain201and the third ring region230may be connected to a source202. The above described order for the method is only intended to be illustrative, and the method is not limited to the above specifically described order unless otherwise specifically stated. In various non-limiting embodiments, the devices100,200may be conventionally fabricated, for example, using known processes and techniques (e.g., growing epitaxial material and implanting impurities). For example, the p-type material may be or include, but is not limited to boron doped silicon as a material, and/or the n-type material may be or include, but is not limited to doped silicon material including phosphorus dopants, arsenic dopants, or combinations thereof FIG.11shows the doping concentration and electrical field characteristics of the first region110. Graph1101depicts a decreasing doping concentration across the first region110from the cathode side to the anode side. Graph1102depicts substantially uniform electrical field1102across the first region110from the cathode side to the anode side. Various modifications can be made to the device100as described herein. Similar modifications as those described with reference to device100may be made to devices200. For example, the distances between the ring portions111to116of the first region110as shown inFIG.1A and1Bmay be varied. By varying these distances, the lateral graded junction in the first region110is varied and therefore the breakdown voltages of the device100can be adjusted to a desired level. In an example, the distance between any two ring portions of the first region110may be zero, that is, the two ring portions are in direct contact with each other. In an example, two adjacent ring portions may be overlapped, that is, there is no visible boundary between the two adjacent ring portions of the first region110. The variation of the distances varies the breakdown voltages with greater distance between two ring portions resulting in higher breakdown voltage. By reducing the distance between two ring portions, the breakdown voltages can be reduced. The device100provides scalable breakdown voltages for high voltage applications. Further, the thicknesses of the ring portions of the first region110may be varied, and the electrical characteristics and performance of the device100may be varied accordingly. The difference between the thicknesses of two adjacent ring portions can be also varied, whereby the graded doping concentration of the first region110may be varied. InFIG.2and the description set forth, the first region110, the second ring region140, the second terminal region150are indicated as n-doped conductivity; and the substrate108, the first ring region120and the first terminal region130are indicated as p-doped conductivity. It can be understood by a person skilled in the art that the first region110, the second ring region140, the second terminal region150can have a different conductivity or an opposite conductivity, e.g. p-doped conductivity; and that the substrate108, the first ring region120and the first terminal region130can have a different conductivity, e.g. n-doped conductivity. Furthermore, inFIG.9, the second region210and the third region220are shown as n-doped conductivity region, and it can be understood that they can be a different conductivity as discussed herein. Similarly, the third ring region230is shown as p-doped conductivity region, and it can be understood that it can be a different conductivity as discussed herein. The device100may also be modified such that only some regions are replaced with respective regions of an opposite conductivity type. For instance, the substrate108can be replaced with an n-type substrate, while the conductivity type of the rest of the device100remains the same. It would be clear to a person skilled in the art that the directions of current flows will change accordingly when the conductivity types of the various regions are reversed. In various non-limiting embodiments, the first terminal region130and the second terminal region150, may include one or more dopants or combinations thereof and may have the same doping concentrations (i.e. same concentration of dopants) or different doping concentrations (i.e. different concentrations of dopants) from each other. The highest doping concentration of the graded doping concentration of the first region110may be lower than the doping concentration of the second ring region140. That is, the doping concentration of the second ring region140is higher than the highest doping concentration of the graded doping concentration of the first region110. The doping levels of the various regions may be varied, the electrical characteristics and performance of the devices100,200as described herein will be varied accordingly. Furthermore, the positioning of the regions of the device100may be varied and one region may be partially or fully within another region. For instance, the second ring region140may be partially or fully within the first region110. The isolation regions160,180,190, may be positioned differently. The cross- sectional view of the isolation regions160,180,190, may be any shape other than trapezoid. The sizes of the isolation regions160,180,190, may be adjusted to be less or larger in the lateral direction or in the vertical direction. In addition, the surfaces of the devices100,200, are not intended to limit to flat surfaces. In various non-limiting embodiments, the surfaces of the devices100,200, can be curved surfaces. The disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the disclosure described herein. Scope of the disclosure is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein. | 41,097 |
11862674 | REFERENCE SIGNS 100substrate101aactive area101bjunction terminal area102high voltage semiconductor device103RESURF104first biasing field plate105ferroelectric material layer106N type top doping layer107P type berried layer108field oxide layer109gate109agate dielectric layer109bgate polysilicon layer110drain110adrain metal layer110bdrain region111second biasing field plate112emitter113collector113acollector metal layer114drift region115interlayer dielectric layer116anode117cathode117aohmic contact layer118JTE structure120DT2structure121bulk region122cut-off ring123source123asource region124PN junction regionL lateral distanceD thickness of the interlayer dielectric layerS1˜S4steps DESCRIPTION OF EMBODIMENTS OF THE INVENTION Reference is now made to the following concrete examples taken in conjunction with the accompanying drawings to illustrate implementation of the present invention. Persons of ordinary skill in the art having the benefit of the present disclosure will understand other advantages and effects of the present invention. The present invention may be implemented with other examples. For various view or application, details in the present disclosure may be used for variation or change for implementing embodiments within the scope of the present invention. Please refer toFIGS.1to8. Please note that the drawings provided here are only for examples but not limited to the specific number or scale shown therein. When implementing the examples according to the drawings, condition, number and proportion of each element may be changed and arrangement of the elements may be in a more complex way. First Embodiment As shown inFIG.1, the present embodiment provides a high voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material, and the high voltage semiconductor device comprises: an active area101aformed with the high voltage semiconductor device102; a combined junction terminal protection structure having a RESURF (Reduced Surface Field) structure103, the RESURF structure103comprising a first biasing field plate104electrically connecting to the active area101aand a ferroelectric material layer105positioned below the first biasing field plate104and in contact with the first biasing field plate104. Please note that the combined junction terminal protection structure has the same function as that of a current high voltage power device, i.e. preventing from early breakdown at a periphery of a main PN junction of the device to increase voltage withstand ability, and meanwhile preventing from an excessively high surface electric field to promote reliability. The high voltage semiconductor device of the present embodiment may be vertical power device or lateral power device made with any proper semiconductor materials, for example, silicon-based, SiC-based or GaN-based lateral or vertical power device. The combined junction terminal protection structure having the RESURF structure103of the present embodiment may be applied at a junction terminal area of the vertical power device or a drift region of the lateral power device. The vertical power device in the present embodiment may be PiN power device, VDMOS power device, or IGBT power device, and the lateral power device may be LDMOS power device. The combined junction terminal protection structure may comprise the RESURF structure103only, or the RESURF structure103along with a typical junction termination protection structure to form the combined junction termination protection structure, such as junction terminal extension structure (abbreviated as JTE structure), field limiting ring structure (abbreviated as FLR structure), deep trench terminal structure (abbreviated as DT2structure), floating field plate structure, etc. Further, the RESURF structure103may be one single biasing field plate electrically connecting to the active area, such as the first biasing field plate104; may be double biasing field plate electrically connecting to the active area, such as the composed field plate structure of the first biasing field plate104and the second biasing field plate111(not shown inFIG.1for simplicity). For example, the material of the ferroelectric material layer105may be chosen from any current proper ferroelectric material, such as PZT, SBT, etc., and preferably, in the present embodiment, the material of the ferroelectric material layer105may be comprise hafnium dioxide-based ferroelectric material doped with aluminum and/or zirconium, which is an environmental-friendly ferroelectric material used in CMOS process that effectively reduce pollution to the environment. A cross-sectional view of an IGBT power device comprising a combined junction terminal protection structure with a ferroelectric material of according to a first embodiment of the present invention is shown inFIG.1. An IGBT power device102is of a planar gate type, and its structure is mainly identical to that of a current typical IGBT power device, comprising: an emitter112of the IGBT power device102formed both in and on an active area101aof a substrate100, a gate109constructed by a gate dielectric layer109aand a gate polysilicon layer109b, a bulk region121, a collector113and a collector metal layer113a. Please note that inFIG.1, only a basic structure of the current IGBT power device102is shown; however, it is readily to be understood that the IGBT power device102of the planar gate type in the present embodiment may comprise other current design(s) promoting performance of the device, other than the basic structure. The combined junction terminal protection (JTE) structure of the IGBT power device102may comprise JTE structure118formed in a junction termination area101bof the substrate100and a RESURF structure103formed on the JTE structure118, in which the first biasing field plate104in the RESURF structure103electrically connects to the gate109, and the JTE structure118is isolated from the RESURF structure103with an insulating layer. Preferably, the insulating layer may be formed during forming the gate dielectric layer109a, and made with the same material as that of the gate dielectric layer109a; the first biasing field plate104may be formed during forming the gate polysilicon layer109b, and made with the same material as that of the and gate polysilicon layer109b, i.e. polysilicon material. An N type IGBT power device is taken for example to describe an operating principle of the RESURF structure103in the following paragraphs. It is readily to be understood that the operating principle of the RESURF structure103of a P type IGBT power device consists to that of the N type IGBT power device. FIG.2shows the way of polarization of the ferroelectric material layer105of the RESURF structure103when the IGBT power device is in a turn-off status. In a turn-off status, a potential VAof the first biasing field plate104having an equipotential connection to the gate109bis in a low potential, compared with a bulk potential VB, so as to form an external electric field along with a direction which is from VBtoward VA. At this time, in the ferroelectric material layer105in the external electric field, a polarized electric field from VAtoward VBis generated. The closer the ferroelectric material layer105is to the gate109laterally, the stronger an intensity of the polarized electric field is. The polarized electric field may induce more depletion region in the JTE structure118to further increase the breakdown voltage BV of the device. FIG.3shows the way of polarization of the ferroelectric material layer105of the RESURF structure103when the IGBT power device is in a turn-on status. In a turn-on status, the potential VAof the first biasing field plate104having the equipotential connection to the gate109bis in a high potential, compared with the bulk potential VB, so as to form an external electric field along with a direction which is from VAtoward VB. At this time, in the ferroelectric material layer105in the external electric field, a polarized electric field from VBtoward VAis generated. The closer the ferroelectric material layer105is to the gate109laterally, the stronger the intensity of the polarized electric field is. The polarized electric field may induce electrons so as to effectively decrease the on-resistance (Ron) at turn-on state. Thus, the ferroelectric layer can raise the BV in turn-off and also decrease the Ron in turn-on and also to fulfill miniaturization of the device structure. Aforesaid operating principle of the RESURF structure103is illustrated with the IGBT power device for example; however, the operating principle may be applied to other semiconductor high voltage devices which will not be repeated in the following paragraphs. When applying the RESURF structure of the present embodiment, the breakdown voltage BV may be raised in turn-off and the on-resistance Ron may be lowered in turn-on based on the current junction termination protection structure. When implementing the present embodiment, the RESURF structure and current junction termination protection structure with ferroelectric layer may be combined to apply both structures to satisfy the requirement of device performance, for example, inFIG.1, the RESURF structure and the JTE structure with ferroelectric layer are combined into one application. FIG.4shows a cross-sectional view of a VDMOS power device of a planar gate type comprising a combined junction terminal protection structure with a ferroelectric material, and its structure is basically the same as that of a current typical VDMOS power device102of the planar gate type, comprising: a source123formed both in and on an active area101aof a substrate, a source region123a, a gate109(with a gate dielectric underneath not shown here for simplicity), a bulk region121, a drain110and a drain metal layer110a. Please note that only a basic structure of the planar gate VDMOS power device102is shown in, and it is readily to be understood that the VDMOS power device102of the planar gate type in the present embodiment may comprise other current design(s) promoting performance of the device, other than the basic structure. The combined junction terminal protection structure of the VDMOS power device102of the planar gate type may comprise a RESURF structure103formed both in and on a DT2structure120of a junction termination area101bof the substrate, in which, a passivation protection layer (not shown) is generally positioned on a surface of the DT2structure120, and the first biasing field plate104in the RESURF structure103electrically connects to the gate109, the ferroelectric layer105. Is underneath the RESURF structure103. FIG.5shows a cross-sectional view of a high voltage diode device comprising a combined junction terminal protection structure with a ferroelectric material, and its structure is basically the same as that of a current typical high voltage diode device102, comprising: an anode116formed both in and on an active area101aof a substrate, a PN junction region124, an ohmic contact layer117aand a cathode117. Please note that only a basic structure of the high voltage diode device102is shown in, and it is readily to be understood that the high voltage diode device102in the present embodiment may comprise other current design(s) promoting performance of the device, other than the basic structure. The combined junction terminal protection structure of the high voltage diode device102may comprise a RESURF structure103formed both in and on a DT2structure120of a junction terminal area101bof the substrate, in which, a passivation protection layer (not shown) is generally positioned on a surface of the DT2structure120, and the first biasing field plate104in the RESURF structure103electrically connects to the anode116, the ferroelectric layer105is below the RESURF structure103and above the DT2structure120. FIG.6shows a cross-sectional view of a LDMOS power device comprising a combined junction terminal protection structure with a ferroelectric material, and a N type LDMOS power device is taken for example. It is readily to be understood that a P type LDMOS power device may be formed with proper variation of polarization and conductivity type of dopants, as common knowledge of the technology field. The structure of the N type LDMOS power device structure is basically the same as that of a current typical LDMOS power device102, comprising: a source region123aformed in a bulk region121, a gate109constructed by a gate dielectric layer109aand a gate polysilicon layer109b, and a drain region110b. Please note that only a basic structure of the planar gate LDMOS power device102is shown in, and it is readily to be understood that the LDMOS power device102in the present embodiment may comprise other current design(s) promoting performance of the device, other than the basic structure. A RESURF structure103of the combined junction termination protection structure of the LDMOS power device102may comprise, from an upper side to a lower side, a first biasing field plate04formed in a drift region of the LDMOS power device, the ferroelectric material layer105, a field oxide layer108for isolation, a N type top doping layer106and a P type berried layer107. The first biasing field plate104electrically connects to the gate109band the drain region110b, and preferably, the first biasing field plate104and the polysilicon layer109bmay be formed at the same time, and the first biasing field plate104and the polysilicon layer109bmay be made with the same polysilicon material. Please note that either of the N type top doping layer106and the P type berried layer107ofFIG.6may be used along with the first biasing field plate104and the ferroelectric material layer105, both of them may be used along with the first biasing field plate104and the ferroelectric material layer105, and they may be used without the first biasing field plate104and the ferroelectric material layer105, because the combination may depend on actual requirements. Preferably, the RESURF structure may further comprise a second biasing field plate111formed on the first biasing field plate104, and the first and second biasing field plate104,110may be electrically isolated from each other with an interlayer dielectric layer115. The second biasing field plate111may electrically connect to the source region123aand the drain region110bthrough a metal contact123. The same operating principle works in the present embodiment, and therefore when applying the second biasing field plate111, the breakdown voltage (BV) may be further increased at turn-off and the on-resistance (Ron) may be reduced at turn-on. In the manufacturing process, the second biasing field plate111may be formed at same time as a metal layer of the device after forming the contact123of the LDMOS device. The metal layer may be used not only for interconnection but also serving as the second biasing field plate111. To simplify the process, the material of the second biasing field plate111may be metal material. Preferably, a lateral distance L between a free end of the second biasing field plate111and a free end of the first biasing field plate104may be greater than a thickness D of the interlayer dielectric layer115. Second Embodiment The present embodiment provides a method of making a high voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material. With the method, the high voltage semiconductor device comprising the combined junction terminal protection structure with the ferroelectric material of the first embodiment may be made; however, the high voltage semiconductor device of the first embodiment is not limited to the method disclosed in the present embodiment, and therefore, it is readily to be understood that the device of the first embodiment may be made by performing other manufacturing method, i.e. the first embodiment stands for all the implementations with the device structure of the first embodiment. Please refer to the first embodiment for effects of the device structure formed with the manufacturing method of the present embodiment, and they are not repeated here. FIGS.7and8show the method of making the high voltage semiconductor device comprising the combined junction terminal protection structure with the ferroelectric material, comprising: providing a semiconductor wafer for preparation, the semiconductor wafer comprising a substrate100, the substrate100being formed with an active area101a, and the active area101abeing formed with a partial structure of the high voltage semiconductor device102; depositing a ferroelectric material on the substrate100, and performing rapid thermal annealing on the ferroelectric material, so as to crystalize the ferroelectric material; patterning the ferroelectric material to form the ferroelectric material layer105; forming a remaining partial structure of the high voltage semiconductor device102both in and on the active area101a, and at the mean time forming a first biasing field plate104, the first biasing field plate104being positioned on the ferroelectric material layer105and in contact with the ferroelectric material layer105, the first biasing field plate104being electrically connecting to the active area104a, and a RESURF structure103of the combined junction terminal protection structure being comprised of the ferroelectric material layer105and the first biasing voltage104. FIG.8shows a perspective view of a cross-sectional structure of a trench gate type VDMOS power device. Taking the trench gate type VDMOS power device for example, the making method would be illustrated easily. The current trench gate type VDMOS power device102is basic in structure; however, it is readily to be understood that the VDMOS power device102in the present embodiment may comprise other current design(s) promoting performance of the device, other than the basic structure, and steps of making the same may apply a current typical process. Please keep in mind to pay attention to the process steps of the RESURF structure103in the present embodiment. Specifically, at first, a semiconductor wafer for preparation is provided. The semiconductor wafer comprises a substrate100, and an active area101aand a junction terminal area101bare formed in the substrate100. A drift region114formed in the active area101aand the junction terminal area101b, and a gate trench is formed on a surface of the active area101a. Then, the ferroelectric material is deposited on the substrate100, and rapid thermal annealing on the ferroelectric material is performed, so as to crystalize the ferroelectric material; then, the ferroelectric material is patterned to form the ferroelectric material layer105. Then, a gate dielectric layer109aand a gate polysilicon layer109bare formed in the gate trench, and the gate dielectric layer109aand the gate polysilicon layer109bforms the gate109. Then, a bulk region121is formed on the surface of the active area101a, and a source region123ais formed in the bulk region121. Then, a metal contact is formed on the surface of the active area101a. Then, a patterned metal layer electrically connecting to the metal contact is formed, at this time, the patterned metal layer is further served as a first biasing field plate104which electrically connecting to the gate109b. Last, bask-side processing of the substrate100is performed, and a step of forming a drain110and a drain metal layer110aat a bask-side surface of the substrate100is comprised. For example, a physical vapor deposition process or an atomic layer deposition process may be performed to form the ferroelectric material, and a temperature of the rapid thermal annealing for the ferroelectric material may be within 400° C.˜1000° C. to ensure the crystallization of the ferroelectric material. For example, the junction terminal protection structures of the trench gate type VDMOS power device may comprise a current typical structure, such as junction terminal extension structure (JTE), field limiting ring structure (FLR), deep trench terminal structure (DT2), floating field plate structure (FFP), etc., and may comprise the second biasing field plate111shown inFIG.6, and any single one or some of the structures may be but not limited to applied along with the RESURF structure, depending on the requirements. The structure shown inFIG.8comprises current typical DT2structure which may be formed at the same time as forming the gate109. As shown inFIG.6, when the structure comprises a second biasing field plate111, the second biasing field plate111may be formed at the same time as forming a metal layer after forming a metal contact. For example, the first biasing field plate104is a polysilicon field plate, the second biasing field plate111is a metal field plate. For example, the material of the ferroelectric material layer105may be chosen from any current proper ferroelectric material, such as PZT, SBT, etc., and preferably, the material of the ferroelectric material layer105may be hafnium dioxide-based material doped with aluminum and/or zirconium, which is an CMOS technology friendly material. For example, the high voltage semiconductor device102may be vertical power device or lateral power device made with any proper semiconductor materials, such as silicon-based, SiC-based or GaN-based lateral or vertical power device. The combined junction terminal protection structure having the RESURF structure103of the present embodiment may be applied to a junction terminal area of the vertical power device or a drift region of the lateral power device. Preferably, the lateral power device comprises a LDMOS power device, and the vertical power device comprises a PiN power device, a VDMOS power device, an IGBT power device. As mentioned above, according to the high voltage semiconductor device having the combined junction termination protection structure with the ferroelectric material and the method of making the same of the present invention of the present invention, the semiconductor device can further raise the breakdown voltage (BV) at turn-off and reduce on-resistance (Ron) at turn-on based on the current junction termination protection structure. The device can be reduced by shorten the JTE width while keep same BV; further, the manufacturing process is simple by adding steps of deposition and patterning ferroelectric layer into current manufacturing process. Therefore, the present invention effectively overcomes various drawbacks of the current technology and is highly valuable for the industry. It is to be understood that these embodiments are not meant as limitations of the invention but merely exemplary descriptions of the invention with regard to certain specific embodiments. Indeed, different adaptations may be apparent to those skilled in the art without departing from the scope of the annexed claims. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, and such claims accordingly define the invention(s), and their equivalents or variations, that are protected thereby. | 23,227 |
11862675 | DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. An integrated circuit (IC) may, for example, comprise a high side area and a low voltage area. The high side area includes devices that operate at a high voltage level, and the low voltage area includes devices that operate at a comparatively low voltage level. A high voltage junction termination (HVJT) device has a ring-shaped top layout that surrounds and demarcates the high side area. Further, the HVJT device separates the high side area from the low voltage area and a high voltage metal-oxide-semiconductor (HVMOS) device. The HVMOS device partially or wholly defines a level shifter translating an input signal at the low voltage level to an output signal at the high voltage level. Further, the HVMOS device is electrically coupled to a device in the high side area to provide the output signal to the device. Such electrical coupling may, for example, be performed externally by wire bonding, or internally by metal wires of a back-end-of-line (BEOL) interconnect structure. A challenge with using wire bonding to externally electrically couple the HVMOS device to the device in the high side area is that wire bonding has high process costs and low reliability in extreme environments (e.g., environments with high pressure and/or high temperature). A challenge with using metal wires of a BEOL interconnect structure to internally electrically couple the HVMOS device to the device in the high side area is that the metal wires depend upon an opening in the HVJT device. This leads to reliability issues (e.g., a low breakdown voltage), limits the number of HVMOS devices, and increases complexity. In view of the foregoing, various embodiments of the present application are directed towards an IC in which an HVMOS device is integrated with a HVJT device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. The ring-shaped pattern may be circular ring shaped, square ring shaped, rectangular ring shaped, triangular ring shaped, or some other closed path shape. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well. The first drift well, the body well, and the gate electrode partially define the HVMOS device, and the second drift well and the peripheral well partially defined the HVJT device. A high side well is in the substrate and has the second doping type. Further, the high side well overlies the second drift well and is spaced from the peripheral well by the second drift well. Integrating the HVMOS device and the HVJT device results in smaller IC chip area and higher reliability. For example, because the HVMOS device and the HVJT device are integrated, the two devices share a common IC chip area instead of separate IC chip areas. This leads to a reduction in overall IC chip area (e.g., about a 25-60% reduction). As another example, because the HVMOS device and the HVJT device are integrated, the HVMOS device and the HVJT device may be electrically coupled without wire bonding and without an opening in the HVJT device. This leads to enhanced reliability. By surrounding and separating the first and second drift wells, the peripheral well may define an isolation ring separating the HVMOS device from the HVJT device. The isolation ring may be circular ring shaped, square ring shaped, rectangular ring shaped, triangular ring shaped, or some other closed path shape. The isolation ring facilitates efficient integration of the HVMOS device with the HVJT device without increased IC chip area. The efficient integration allows the number of HVMOS device to be increased and/or the size of the high side well to be increased without complex redesigns and increased IC chip area by the HVJT and HVMOS devices. Further, the efficient integration allows a voltage handling capability and/or a current handling capability of the HVMOS device to be varied without complex redesigns. With reference toFIG.1, a top layout100of some embodiments of an IC in which HVMOS devices102are integrated with a HVJT device104is provided. The HVMOS devices102and the HVJT device104border and collectively define a composite structure. The composite structure extends laterally in a closed path along a boundary of a high side area106of the IC to completely surround the high side area106. In some embodiments, the composite structure is square ring shaped, rectangular ring shaped, triangular ring shaped, circular ring shaped, or some other closed path shape. Further, the composite structure is surrounded by a low voltage area108of the IC. The high side area106accommodates semiconductor devices (not shown) operating at a high voltage level, whereas the low voltage area108accommodates semiconductor devices (not shown) operating at a low voltage level. The high voltage level is high relative to the low voltage level and may be or comprise, for example, voltages between about 300-1200 volts, voltages between about 300-750 volts, voltages between about 750-1200 volts, or voltages in excess of about 300 volts. The low voltage level may be or comprise, for example, voltages between about 1-20 volts, voltages between about 1-10 volts, voltages between about 10-20 volts, or voltages less than about 20 volts. The HVJT device104physically and electrically separates the high side area106from the low voltage area108. Further, the HVJT device104is or comprises a diode. The diode is capable of sustained operation at the high voltage level and is configured to operate in a reverse biased state. The HVMOS devices102are transistors or some other switching devices capable of sustained operation at the high voltage level. For example, the HVMOS devices102may be laterally diffused metal-oxide-semiconductor (LDMOS) devices or some other suitable metal-oxide-semiconductor (MOS) devices, and/or may sustain operation while source-drain voltages are at the high voltage level (e.g., about 600 volts). In some embodiments, the HVMOS devices102partially or wholly define a level shifter translating an input signal at the low voltage level to an output signal at the high voltage level. The HVMOS devices102comprise a first HVMOS device102A and a second HVMOS device102B. Each of the HVMOS devices102is on an HVMOS drift well110and an HVMOS body well112, and comprises a first source/drain region114, a second source/drain region116, a body contact region118, and a gate electrode120. The HVMOS drift well110is a semiconductor region with a first doping type and surrounds the HVMOS body well112. The HVMOS body well112is a semiconductor region with a second doping type, opposite the first doping type, and defines a selectively-conductive channel122of the HVMOS device. The first doping type may, for example, be n-type, and the second doping type may, for example, be p-type, or vice versa. Further, the HVMOS body well112underlies the first source/drain region114and the body contact region118when viewed in cross-section (not visible within the top layout100ofFIG.1). The first and second source/drain regions114,116are spaced by the HVMOS drift and body wells110,112, such that the first source/drain region114borders the low voltage area108and the second source/drain region116borders the high side area106. The first and second source/drain regions114,116are semiconductor regions with the first doping type and higher doping concentrations than the HVMOS drift well110. The body contact region118is a semiconductor region with the second doping type and a higher doping concentration than the HVMOS body well112. The gate electrode120(shown in phantom) overlies the HVMOS body well112, such that the gate electrode120borders the first source/drain region114and is mostly between the first and second source/drain regions114,116. The gate electrode120may be or comprise, for example, doped polysilicon, metal, or some other conductive material. The HVMOS devices102are individually surrounded by isolation rings124physically and electrically separating the HVMOS devices102from the high side area106and the HVJT device104. For example, the isolation rings124may define diodes with a drift region of the HVJT device104(discussed hereafter) and/or the HVMOS drift wells110, and the diodes may operate in the blocking or reversed biased state to provide electrical separation. While the isolation rings124may be circular ring shaped, the isolation rings124are not limited to being circular ring shaped. The isolation rings124may, for example, be square ring shaped, rectangular ring shaped, triangular ring shaped, or some other closed path shape. In some embodiments, the isolation rings124are semiconductor regions with an opposite doping type as the HVMOS drift wells110, and/or the same doping type as the HVMOS body well112. The isolation rings124facilitate efficient integration of the HVMOS devices102with the HVJT device104without increased IC chip area. As seen hereafter, the integration allows the number of HVMOS devices to be increased and/or the size of the high side area106to be increased without complex redesigns and without the HVMOS and HVJT devices102,104using more IC chip area. Further, the integration allows voltage handling capabilities and/or current handling capabilities of the HVMOS devices102to be varied without complex redesigns. Further yet, the integration leads to low IC chip area and high reliability. For example, because the HVMOS devices102and the HVJT device104are integrated, the HVMOS and HVJT devices102,104share a common IC chip area instead of separate IC chip areas. This leads to a reduction in overall IC chip area. As another example, because the HVMOS devices102and the HVJT device104are integrated, the HVMOS and HVJT devices102,104may be electrically coupled without wire bonding and without an opening in the HVJT device104. This leads to enhanced reliability. While the IC is illustrated as having two HVMOS devices (i.e., the first HVMOS device102A and the second HVMOS device102B) inFIG.1, the first or the second HVMOS device102A,102B may be omitted in other embodiments. Further, as seen hereafter, the IC may have one or more additional HVMOS devices in other embodiments. In such embodiments, the one or more additional HVMOS devices are each as described above and are each positioned along the boundary of the high side area106. With reference toFIG.2A, a cross-sectional view200A of some more detailed embodiments of the IC ofFIG.1is provided. The cross-sectional view200A may, for example, be taken along line A-A′ inFIG.1. As illustrated, the first HVMOS device102A and the HVJT device104are on a semiconductor substrate202. The semiconductor substrate202may be, for example, a bulk silicon substrate, a group III-V substrate, a silicon-on-insulator (SOI) substrate, or some other semiconductor substrate. A peripheral well204is in the semiconductor substrate202and overlies a bulk semiconductor region202B of the semiconductor substrate202. The peripheral well204comprises a pair of segments between which the first HVMOS device102A and the HVJT device104are sandwiched, and further comprises the isolation ring124. When viewed top down, the isolation ring124extends laterally along a boundary of the first HVMOS device102A to completely enclose the first HVMOS device102A. Note this is not visible within the cross-sectional-sectional view200A ofFIG.2A. In some embodiments, the peripheral well204has an elevated doping concentration at the isolation ring124relative to remainder of the peripheral well204. Further, in some embodiments, the peripheral well204has the same doping type as the bulk semiconductor region202B. An isolation structure206overlies the peripheral well204. The isolation structure206comprises a dielectric material (e.g., silicon oxide), and may be or comprise, for example, a shallow trench isolation (STI) structure, a field oxide (FOX) structure, a local oxidation of silicon (LOCOS) structure, or some other isolation structure. Further, a first peripheral contact region208A and a second peripheral contact region208B overlie the peripheral well204. The first peripheral contact region208A is adjacent to the first HVMOS device102A, and the second peripheral contact region208B is adjacent to the HVJT device104. The first and second peripheral contact regions208A,208B are in the semiconductor substrate202and have the same doping type as, but a higher doping concentration than, the peripheral well204. In some embodiments, the first and second peripheral contact regions208A,208B are electrically coupled to ground and/or or a cathode of a low voltage power supply. The HVMOS drift well110and the HVMOS body well112are in the semiconductor substrate202and overlie the bulk semiconductor region202B. Further, the first HVMOS device102A is on the HVMOS drift well110and the HVMOS body well112. The first HVMOS device102A may be, for example, an LDMOS transistor or some other switching device. The HVMOS drift well110underlies and laterally surrounds the HVMOS body well112, such that the HVMOS drift well110spaces (e.g., completely spaces) the HVMOS body well112from the bulk semiconductor region202B and the peripheral well204. Further, the HVMOS drift well110has an opposite doping type as the peripheral well204and the HVMOS body well112. The HVMOS body well112has the same doping type as the peripheral well204. In some embodiments, the isolation structure206covers a boundary along which the HVMOS drift well110contacts the peripheral well204. The second source/drain region116overlies the HVMOS drift well110, closer to the high side area106than the first source/drain region114. The first source/drain region114and the body contact region118overlie the HVMOS body well112, such that the first source/drain region114is between the body contact region118and the second source/drain region116. The first and second source/drain regions114,116are laterally separated by the HVMOS drift well110, the HVMOS body well112, and the isolation structure206. The first source/drain region114, the second source/drain region116, and the body contact region118are in the semiconductor substrate202. The first and second source/drain regions114,116have the same doping type as, but a higher doping concentration than, the HVMOS drift well110. The body contact region118has the same doping type as, but a higher doping concentration than, the HVMOS body well112. In some embodiments, the first source/drain region114and the body contact region118are electrically shorted together. The selectively-conductive channel122is in the HVMOS body well112. The selectively-conductive channel122extends along a top surface of the semiconductor substrate202, from the first source/drain region114to the HVMOS drift well110. The HVMOS drift well110extends from the selectively-conductive channel122to the second source/drain region116. Further, the isolation structure206overlies the HVMOS drift well110, between the selectively-conductive channel122and the second source/drain region116. In some embodiments, a width W of the isolation structure206on the HVMOS drift well110is about 50-200 micrometers, about 75-125 micrometers, or about 100 micrometers. The gate electrode120overlies the selectively-conductive channel122and the isolation structure206, and further extends along a sidewall of the isolation structure206from overlying the selectively-conductive channel122to overlying the isolation structure206. Further, the gate electrode120is electrically insulated from the selectively-conductive channel122by a gate dielectric layer212. The gate dielectric layer212may be or comprise, for example, silicon oxide, hafnium oxide, or some other dielectric material. In some embodiments, an HVMOS field plate214borders the second source/drain region116. The HVMOS field plate214extends along a sidewall of the isolation structure206and overlies the isolation structure206. In some embodiments, the HVMOS field plate214is electrically shorted to the second source/drain region116. The HVMOS field plate214may be or comprise, for example, doped polysilicon, metal, or some other conductive material. During operation of the first HVMOS device102A, the selectively-conductive channel122selectively conducts depending upon whether a voltage from the gate electrode120to the first source/drain region114exceeds a threshold voltage. Further, while the first HVMOS device102A is in the non-conducting or blocking state, the HVMOS drift well110acts as resistor to absorb high electric fields associated with high source-drain voltages (e.g., voltages in excess of 300 volts). This, in turn, allows the first HVMOS device102A to sustain operation at the high source-drain voltages. In some embodiments, the HVMOS drift well110is widened to increase the separation between the HVMOS body well112and the second source/drain region116, thereby increasing resistance and voltages at which the first HVMOS device102A can sustain operation. In such embodiments, the width W of the isolation structure206on the HVMOS drift well110is increased with the HVMOS drift well110. In some embodiments, the doping concentration of the HVMOS drift well110is reduced, thereby increasing resistance and voltages at which the first HVMOS device102A can sustain operation. A challenge with widening the HVMOS drift well110and/or decreasing the doping concentration of the HVMOS drift well110is that the resistance of the first HVMOS device102A in the conducting or non-blocking state may become high and power efficiency may become low. Further, a challenge with widening the HVMOS drift well110is that IC chip area consumed by the first HVMOS device102A may become high. In some embodiments, the HVMOS body well112comprises a protrusion112P protruding laterally towards the high side area106. The protrusion112P results in an alternating stack of n-type and p-type semiconductor regions that define an HVMOS reduced surface field (RESURF) structure216with multiple PN junctions. The multiple PN junctions comprise: 1) a first PN junction at a boundary between a bottom surface of the protrusion112P and the HVMOS drift well110; and 2) a second PN junction at a boundary between a top surface of the protrusion112P and the HVMOS drift well110. In some embodiments, the multiple PN junctions further comprise a third PN junction at a boundary between the bulk semiconductor region202B and the HVMOS drift well110. The multiple PN junctions may, for example, also be known as a Super Junction. The HVMOS RESURF structure216laterally and vertically distributes the high electric field associated with high source-drain voltages, such that the maximum electric field is low in the blocking or OFF state. For example, the high electric field may be vertically distributed across the multiple PN junctions, and/or may be laterally distributed from the second source/drain region116to the HVMOS body well112. This, in turn, allows the first HVMOS device102A to sustain operation at high voltages. Further, the HVMOS RESURF structure216does not depend upon a high resistance from the second source/drain region116to the HVMOS body well112, such that IC chip area may be low and the resistance of the first HVMOS device102A n the non-blocking state may be low. A HVJT drift well218overlies the bulk semiconductor region202B and is sandwiched between opposing segments of the peripheral well204. Further, the HVJT drift well218underlies and laterally surrounds a high side well220at the high side area106, such that the HVJT drift well218spaces (e.g., completely spaces) the high side well220from the bulk semiconductor region202B and the peripheral well204. The HVJT drift well218and the high side well220are in the semiconductor substrate202and respectively have opposite doping types. In some embodiments, the HVJT drift well218has the same doping type as the HVMOS drift well110, and/or the high side well220has the same doping type as the HVMOS body well112and the peripheral well204. In some embodiments, the peripheral well204, the HVMOS body well112, the high side well220, and the bulk semiconductor region202B are p-type, whereas the HVMOS drift well110and the HVJT drift well218are n-type, or vice versa. In some embodiments, the isolation structure206partially covers the high side well220and/or covers a boundary along which the high side well220contacts the HVJT drift well218. A high side contact region222overlies the high side well220and comprises a pair of segments on opposite sides of the high side well220. In some embodiments, when viewed top down, the high side contact region222extends laterally along a boundary of the high side well220in a closed path and/or has a ring-shape. Note this is not visible within the cross-sectional-sectional view200A ofFIG.2A. The high side contact region222is in the semiconductor substrate202and has the same doping type as, but a higher doping concentration than, the high side well220. A HVJT drift contact region224overlies the HVJT drift well218, adjacent to the high side well220, and comprises a pair of segments between which the high side well220and the high side contact region222are sandwiched. In some embodiments, when viewed top down, the HVJT drift contact region224extends laterally along a boundary of the high side well220in a closed path and/or has a ring-shape. Note this is not visible within the cross-sectional-sectional view200A ofFIG.2A. The HVJT drift contact region224is in the semiconductor substrate202and has the same doping type as, but a higher doping concentration than, the HVJT drift well218. The HVJT device104is or comprises a diode, and is defined in part by the HVJT drift well218, the peripheral well204, the second peripheral contact region208B, and the HVJT drift contact region224. An anode of the diode is defined by the second peripheral contact region208B, and a cathode of the diode is defined by the HVJT drift contact region224, or vice versa. Further, the HVJT drift well218and the peripheral well204define a PN junction of the diode. The isolation structure206overlies the HVJT drift well218, between the second peripheral contact region208B and the HVJT drift contact region224. Further, in some embodiments, the isolation structure206has the same width W between the second peripheral contact region208B and the HVJT drift contact region224as between the first and second source/drain regions114,116. A first HVJT field plate226overlies a PN junction at which the HVJT drift well218contacts the peripheral well204, between the second peripheral contact region208B and the isolation structure206. Further, the first HVJT field plate226extends along a sidewall of the isolation structure206from overlying the PN junction to overlying the isolation structure206. The first HVJT field plate226is electrically insulated from the HVJT drift well218and the peripheral well204by a field plate dielectric layer228. The field plate dielectric layer228may be or comprise, for example, silicon oxide, hafnium oxide, or some other dielectric material. In some embodiments, the first HVJT field plate226is electrically shorted to the second peripheral contact region208B. The first HVJT field plate226may be or comprise, for example, doped polysilicon, metal, or some other conductive material. In some embodiments, a second HVJT field plate230borders the HVJT drift contact region224, between the first HVJT field plate226and the HVJT drift contact region224. The second HVJT field plate230extends along a sidewall of the isolation structure206and overlies the isolation structure206. In some embodiments, the second HVJT field plate230is electrically shorted to the HVJT drift contact region224. The second HVJT field plate230may be or comprise, for example, doped polysilicon, metal, or some other conductive material. During operation of the HVJT device104, the HVJT device104provides electrical separation between the peripheral well204and the high side well220while the high side well220is at a higher voltage than the peripheral well204. Further, while the HVJT device104is in the non-conducting or blocking state, the HVJT drift well218and the peripheral well204act as resistors between the second peripheral contact region208B and the HVJT drift contact region224to absorb high electric fields associated with high voltages (e.g., voltages in excess of 300 volts). This, in turn, allows the HVJT device104to sustain operation at the high voltages. In some embodiments, the HVJT drift well218is widened to increase the separation between the second peripheral contact region208B and the HVJT drift contact region224, thereby increasing resistance and voltages at which the HVJT device104can sustain operation. In such embodiments, the width W of the isolation structure206on the HVJT drift well218is also increased with the HVJT drift well218. In some embodiments, the doping concentration of the HVJT drift well218is reduced, thereby increasing resistance and voltages at which the HVJT device104can sustain operation. A challenge with widening the HVJT drift well218and/or decreasing the doping concentration of the HVJT drift well218is that the resistance of the HVJT device104in the conducting or non-blocking state may become high, and power efficiency may become low. Further, a challenge with widening the HVJT drift well218is that IC chip area consumed by the HVJT device104may become high. In some embodiments, the peripheral well204comprises a protrusion204P protruding towards the high side area106. The protrusion204P results in an alternating stack of n-type and p-type semiconductor regions that define an HVJT RESURF structure232with multiple PN junctions. The multiple PN junctions comprise: 1) a first PN junction at a boundary between a bottom surface of the protrusion204P and the HVJT drift well218; and 2) a second PN junction at a boundary between a top surface of the protrusion204P and the HVJT drift well218. In some embodiments, the multiple PN junctions further comprise a third PN junction at a boundary between the bulk semiconductor region202B and the HVJT drift well218. The HVJT RESURF structure232laterally and vertically distributes the high electric field associated with high voltages, such that the maximum electric field is low in the blocking state. For example, the high electric field may be vertically distributed across the multiple PN junctions, and/or may be laterally distributed from the second peripheral contact region208B and the HVJT drift contact region224. This allows the HVJT device104to sustain operation at high voltages. Further, the HVJT RESURF structure232does not depend upon a high resistance from the second peripheral contact region208B and the HVJT drift contact region224, such that IC chip area may be low and the resistance of the HVJT device104in the non-blocking state may be low. The HVJT RESURF structure232laterally distributes (e.g., from the second peripheral contact region208B and the HVJT drift contact region224) and vertically distributes (e.g., across the multiple PN junctions) the high electric field associated with high voltages, such that the maximum electric field from the second peripheral contact region208B and the HVJT drift contact region224is low in the blocking state. This, in turn, allows the HVJT device104to sustain operation at high voltages while having a low ON resistance and a low IC chip area. In some embodiments, a spiral structure234overlies the isolation structure206on the HVJT drift well218and the HVMOS drift well110. When viewed top down, the spiral structure234extends laterally and continuously in a spiral over the isolation structure206. Note this is not visible within the cross-sectional-sectional view200A ofFIG.2A. The spiral structure234serves as a field plate to manipulate (e.g., increase or decrease) carrier mobility thereunder. In some embodiments, a first end of the spiral structure234is electrically coupled to the first and second peripheral contact regions208A,208B and/or ground. In some embodiments, a second end of the spiral structure, opposite the first end, is electrically coupled to the high side contact region222and/or the HVJT drift contact region224. The spiral structure234may be or comprise, for example, doped polysilicon, metal, or some other conductive material. Conductive wires236and conductive vias238are stacked over the semiconductor substrate202and define conductive paths. For ease of illustration, only some of the conductive wires236are labeled236, and only some of the conductive vias238are labeled238. The conductive paths provide electrically coupling between the various contact regions (e.g., the HVJT drift contact region224), the various fields plates (e.g., the first HVJT field plate226), the gate electrode120, the first and second source/drain regions114,116, and the spiral structure234. For example, one of the conductive paths may electrically couple the first source/drain region114to the body contact region118. The conductive wires236and the conductive vias238may be or comprise, for example, copper, aluminum copper, aluminum, tungsten, some other conductive material, or any combination of the foregoing. WhileFIG.2Aillustrates and describes the first HVMOS device102A, it is to be understand that the second HVMOS device102B ofFIG.1may, for example, be as the first HVMOS device102A is illustrated and described inFIG.2A. More generally, each HVMOS device described herein may, for example, be as the first HVMOS device102A is illustrated and described inFIG.2A. With reference toFIG.15, a cross-sectional view1500of some alternative embodiments of the IC ofFIG.2Ais provided in which constituents of the IC are varied. For example, the protrusion204P of the peripheral well204protrudes to a sidewall directly under the HVJT drift contact region224. With reference toFIG.2B, a cross-sectional view200B of some more detailed embodiments of the IC ofFIG.1is provided. The cross-sectional view200B may, for example, be taken along line B-B′ inFIG.1. As illustrated, the HVJT device104is on opposite sides of the high side area106. Further, the first HVMOS device102A ofFIG.2Aand the isolation ring124ofFIG.2Aare not visible (i.e., are outside the cross-sectional view200B). With reference toFIG.3A, a top layout300A of some more detailed embodiments of the IC ofFIG.1is provided. The cross-sectional view200A ofFIG.2Amay, for example, be taken along line A-A′ inFIG.3A, and the cross-sectional view200B ofFIG.2Bmay, for example, be taken along line B-B′ inFIG.3A. In some embodiments, HVMOS drift wells110of the first and second HVMOS devices102A,102B and/or HVMOS body wells112of the first and second HVMOS devices102A,102B may also be known as switching device wells. In some embodiments, the HVJT drift well218of the HVJT device104may also be known as a termination device well. As illustrated byFIG.3A, the high side contact region222and the HVJT drift contact region224are ring shaped, and conform to the isolation rings124of the first and second HVMOS devices102A,102B. In some embodiments, the high side contact region222and the HVJT drift contact region224serve as guard rings or pickup rings. In some embodiments, the high side contact region222is connected to the lowest voltage level in a circuit within which the IC is applied, and the HVJT drift contact region224is connected to highest voltage level in the circuit, to safeguard devices on the high side well220(seeFIGS.2A and2B) against parasitic latching up and turning on. As should be appreciated, while the high side contact region222and the HVJT drift contact region224may be circular ring shaped, the high side contact region222and the HVJT drift contact region224are not limited to circular ring shaped and may be square ring shaped, rectangular ring shaped, triangular ring shaped, or some other closed path shape. Also illustrated byFIG.3A, the spiral structure234extends continuously over the isolation structure206. In some embodiments, a first end of the spiral structure234is electrically coupled to the first and second peripheral contact regions208A,208B and/or ground. In some embodiments, a second end of the spiral structure, opposite the first end, is electrically coupled to the high side contact region222and/or the HVJT drift contact region224. With reference toFIG.3B, a top layout300B of some more detailed embodiments of the IC ofFIG.1is provided.FIG.3Bis a variant ofFIG.3Ain which the isolation structure206, the gate electrode120, the various field plates (e.g., the first HVJT field plate226), and the spiral structure234have been removed to show underlying structure. As illustrated byFIG.3B, the peripheral well204completely surrounds the HVJT drift well218, and is completely spaced from the HVMOS body wells112by the HVMOS drift wells110. Absent such spacing, the HVMOS body wells112would be at the same voltage as the peripheral well204, which may be undesirable for certain applications of the first and second HVMOS devices102A,102B. Also illustrated byFIG.3B, the HVJT drift well218is ring shaped, and conforms to the isolation rings124of the first and second HVMOS devices102A,102B. As should be appreciated, while the HVJT drift well218may be circular ring shaped, the HVJT drift well218is not limited to circular ring shaped and may be square ring shaped, rectangular ring shaped, triangular ring shaped, or some other closed path shape. The isolation ring124facilitates the integration of the first and second HVMOS devices102A,102B with the HVJT device104by allowing the first and second HVMOS devices102A,102B to be sandwiched between the HVJT drift well218and the peripheral well204without breaking a continuity of the HVJT drift well218and the peripheral well204. As described above, the HVJT device104is or comprises a diode, and the HVJT drift well218and the peripheral well204define a PN junction of the diode. Such integration leads to low IC chip area (e.g., a 25-60% reduction in IC chip area), high reliability, and simplified design iterations. For example, because of the integration, the first HVMOS device102A is not remote from the HVJT device104and IC chip area is low. As another example, because of the integration, the first HVMOS device102A may be electrically coupled to the HVJT device104locally and without the use of remote wire bonding or complex interconnect structures. This, in turn, increases the reliability of the IC and reduces manufacturing costs. As noted above, the isolation rings124may define diodes that operate in the blocking or reversed biased state to provide electrical separation between the HVJT device104and the first and second HVMOS devices102A,102B. The isolation rings124define ring-shaped PN junctions with the HVMOS drift wells110. These ring-shaped PN junctions respectively surround the first and second HVMOS devices102A,102B and, where the HVMOS drift wells110are n-type, may prevent current from flowing from the first and second HVMOS devices102A,102B to the HVJT device104. The isolation rings124(and a remainder of the peripheral well204) define a ring-shaped PN junction with the HVJT drift well218. This ring-shaped PN junction defines the HVJT device104and, where the HVMOS drift well110is n-type, may prevent current from flowing from the HVJT device104to the first and second HVMOS devices102A,102B. In some embodiments, the isolation rings124define NPN junctions with the HVJT drift well218the HVMOS drift wells110. With reference toFIGS.4A and4B, top layouts400A,400B of various other embodiments of the IC ofFIG.1are provided in which a geometry of a high side area106is scaled in the X dimension and/or the Y dimension to vary the size of the high side area106. For example, the geometry of the high side area106may be scaled to accommodate more or less devices. Because the isolation rings124facilitate efficient integration between the HVJT device104and the HVMOS devices102, the geometry of the high side area106may be readily scaled without complex redesigns. With reference toFIGS.5A-5D, top layouts500A-500D of various other embodiments of the IC ofFIG.1are provided in which geometries of the HVMOS devices102are varied according to current handling requirements and voltage handling requirements. As illustrated byFIGS.5A and5B, the HVMOS devices102ofFIG.5Ahave a first width W1, whereas the HVMOS devices102ofFIG.5Bhave a second width W2less than the first width W1. Increasing a width of the HVMOS devices102increases a width of the first and second source/drain regions114,116, which widens selectively-conductive channels of the HVMOS devices102and widens the HVMOS drift wells110. This increases the source-drain current at which the HVMOS device102can sustain operation. Further, decreasing a width of the HVMOS devices102decreases a width of the first and second source/drain regions114,116, which narrows selectively-conductive channels of the HVMOS devices102and narrows the HVMOS drift wells110. This decreases the source-drain current at which the HVMOS devices102can sustain operation. Therefore, because the first width W1is greater than the second width W2, the HVMOS devices102ofFIG.5Acan sustain operation at a higher source-drain current than the HVMOS devices102ofFIG.5B. As illustrated byFIG.5C, the first and second HVMOS devices102A,102B respectively have a third width W3and a fourth width W4, where the fourth width W4is less than the third width W3. Therefore, the first HVMOS device102A ofFIG.5Ccan sustain operation at a higher source-drain current than the second HVMOS device102B ofFIG.5C. As illustrated byFIGS.5A-5D, the HVMOS devices102ofFIGS.5A-5Cand the HVJT device104ofFIGS.5A-5Chave a first thickness T1, whereas the HVMOS devices102ofFIG.5Dand the HVJT device104ofFIG.5Dhave a second thickness T2greater than the first thickness T1. Increasing a thickness of the HVMOS devices102lengthens the HVMOS drift wells110of the HVMOS devices102, which increases the voltages at which the HVMOS devices102can sustain operation. Similarly, increasing a thickness of the HVJT device104lengthens the HVJT drift well (not shown), which increases the voltage at which the HVJT device104can sustain operation. Decreasing a thickness of an HVMOS devices102shortens the HVMOS drift wells110, which decreases the voltages at which the HVMOS devices102can sustain operation. Similarly, decreasing a thickness of the HVJT device104shortens the HVJT drift well, which decreases the voltage at which the HVJT device104can sustain operation. Therefore, since the first thickness T1is less than the second thickness T2, the HVMOS devices102ofFIG.5Dcan sustain operation at higher voltages than the HVMOS devices102of theFIGS.5A-5C. Further, the HVJT device104ofFIG.5Dcan sustain operation at a higher voltage than the HVJT device104ofFIGS.5A-5C. Because the isolation rings124facilitate efficient integration between the HVJT device104and the HVMOS devices102, the geometries of the HVMOS devices102and the HVJT device104may be readily scaled without complex redesigns by adjusting the size of the isolation rings124. With reference toFIGS.6A and6B, top layouts600A,600B of various other embodiments of the IC ofFIG.1are provided in which more than two HVMOS devices are integrated with the HVJT device104. As illustrated byFIG.6A, the HVMOS devices102further comprise a third HVMOS device102C. As illustrated byFIG.6B, the HVMOS devices102further comprise the third HVMOS device102C and a fourth HVMOS device102D. Each of the HVMOS devices102is as described inFIG.1and may, for example, be as the first HVMOS device102A is illustrated and described in any one ofFIGS.2A,2B,3A, and3B. Because the isolation rings124facilitate efficient integration between the HVJT device104and the HVMOS devices102, the number of HVMOS devices integrated with the HVJT device104may be varied without complex redesigns. Further, because the HVJT device104and the HVMOS devices102are integrated together, the number of HVMOS devices integrated with the HVJT device104may be increased without increasing IC chip area. With reference toFIG.7, a block diagram700of some embodiments of a circuit in which the IC ofFIG.1finds application. The circuit may, for example, be or comprise a high-side gate driver circuit. As illustrated, a level shifter702comprises the first HVMOS device102A and the second HVMOS device102B, and further comprises a first resistor704A and a second resistor704B. In some embodiments, the first and second HVMOS devices102A,102B are n-channel LDMOS transistors. The first HVMOS device102A and the first resistor704A are electrically coupled in series from a high side supply node706(e.g., HS_Vdd) to a low voltage return node708(e.g., LV_Vss), such that the first HVMOS device102A is separated from the high side supply node706by the first resistor704A. Similarly, the second HVMOS device102B and the second resistor704B are electrically coupled in series from the high side supply node706to the low voltage return node708, such that the second HVMOS device102B is separated from the high side supply node706by the second resistor704B. In some embodiments, the low voltage return node708is electrically coupled to ground710. An edge pulse generator712is powered by a low voltage power supply714, and controls gates of the first and second HVMOS devices102A,102B based on a high side input signal716. The high side input signal716is a binary signal varying between 0 volts and a voltage of the low voltage power supply714. The low voltage power supply714has an anode electrically coupled to a low voltage supply node718(e.g., LV_Vdd), and a cathode electrically coupled to the low voltage return node708. The low voltage power supply714may be, for example, a direct current (DC) power supply, and/or may, for example, supply a low voltage between about 1-20 volts, between about 1-10 volts, between about 10-20 volts, or less than about 20 volts. The edge pulse generator712detects rising edges of the high side input signal716, and further detects falling edges of the high side input signal716. Further, the edge pulse generator712generates a rising-edge signal720A and a falling-edge signal720B. The rising-edge signal720A has a pulse at each of the detected rising edges and gates the first HVMOS device102A. The falling-edge signal710B has a pulse at each of the detected falling edges and gates the second HVMOS device102B. A set-reset (S-R) latch722is set by a set signal724A at a shared node of the first HVMOS device102A and the first resistor704A, and is further reset by a reset signal724B at a shared node of the second HVMOS device102B and the second resistor704B. In some embodiments, the set and reset signals724A,724B pass through a noise filter (not shown) before passing to the S-R latch722. An inverted output (e.g.,Q) of the S-R latch722controls a gate driver726to selectively switch the gate driver726between an ON state and an OFF state. For example, the gate driver726may be in an ON state when the inverted output of the S-R latch722indicates a binary “0” and may be in an OFF state when the inverted output of the S-R latch722indicates a binary “1”. In some embodiments, the gate driver726is or comprises a complementary metal-oxide-semiconductor (CMOS) inverter. In some embodiments, the gate driver726comprises a p-channel MOS field-effect transistor (MOSFET)728P and an n-channel MOSFET728N connected in series from the high side supply node706to a high side return (e.g., HS_Vss) node730, such that the p-channel MOSFET728P separates the n-channel MOSFET728N from the high side supply node706. The HVJT device104and the first and second HVMOS devices102A,102B collectively define a composite structure extending laterally along a boundary of a high side area106of an IC die732to surround the high side area106. In some embodiments, the composite structure is square ring shaped, rectangular ring shaped, triangular ring shaped, circular ring shaped, or some other closed path shape. Further, the composite structure is surrounded by a low voltage area108of the IC die732. The high side area106accommodates the S-R latch722, the gate driver726, the first resistor704A, and the second resistor704B, whereas the low voltage area108accommodates the edge pulse generator712. The HVJT device104is or comprises a diode104dand electrically separates the low voltage area108from the high side area106. In some embodiments, a cathode of the diode104dis electrically coupled to the high side supply node706, and/or an anode of the diode104dis electrically coupled to the low voltage return node708. A bootstrap capacitor734is electrically coupled from the high side supply node706to the high side return node730. The bootstrap capacitor734is charged by the low voltage power supply714, through a bootstrap diode736, while the gate driver726is in the OFF state. Further, the bootstrap capacitor734powers devices (e.g., the S-R latch722) at the high side area106to change the gate driver726to the ON state. A high side power supply738is electrically coupled to the low voltage return node708, and is selectively electrically coupled to the high side return node730by a first power MOSFET740. Note that an insulated-gate bipolar transistor (IGBT) or some other switching device may alternatively be used in place of the first power MOSFET740. The high side power supply738may be, for example, a DC power supply, and/or may, for example, supply a high voltage between about 300-1200 volts, between about 300-750 volts, between about 750-1200 volts, between about 550-650 volts, or in excess of 300 volts. The first power MOSFET740is gated by an output of the gate driver726and may be, for example, an n-channel power MOSFET. In some embodiments, the output of the gate driver726is at a node shared by the p-channel MOSFET728P and the n-channel MOSFET728N. The bootstrap diode736limits the flow of current between the low voltage supply node714and the high side supply node706. The bootstrap diode736allows current to flow from the low voltage supply node718to the high side supply node706while the high side supply node706is at a lower voltage level than the low voltage supply node718. This may occur while the gate driver726is in the OFF state and allows the bootstrap capacitor734to be charged. Further, the bootstrap diode736blocks current from flowing between the low voltage supply node718and the high side supply node706while the high side supply node706is at a higher voltage level than the low voltage supply node718. This may occur while the gate driver726is in the ON state and prevents devices at the low voltage area108from being damaged by high voltages of the high side power supply738. In operation, to disable the first power MOSFET740, the high side input signal716is changed from a binary “1” to a binary “0”, thereby resetting the S-R latch722. After resetting the S-R latch722, the S-R latch722outputs a binary “1” at the inverted output, which disables the p-channel MOSFET728P and enables the n-channel MOSFET728N. This electrically shorts the gate of the first power MOSFET740and the source of the first power MOSFET740, thereby disabling the first power MOSFET740. Additionally, the high side return node730is electrically coupled to the low voltage return node708. In some embodiments, this electrical coupling is performed by a second power MOSFET742or some other switching device. The second power MOSFET742is gated by a low-side input signal744, which may, for example, be generated by a low-side gate driver circuit. Since the bootstrap capacitor734has largely been discharged and the high side return node730is electrically coupled to the low voltage return node708, the voltage at the high side supply node706is low compared to the voltage of the low voltage supply node718. Therefore, the bootstrap diode736is operating in a forward biased state and allows the flow of current between the low voltage supply node718and the high side supply node706. This, in turn, charges the bootstrap capacitor734from the low voltage power supply714. To enable the first power MOSFET740, the high side return node730is electrically separated from the low voltage return node708, such that the high side return node730is floating. In some embodiments, this electrical separation is performed by the second power MOSFET742. The high side return node730floats upward, whereby the bootstrap diode736moves to a reverse biased state. Further, the high side input signal716is changed from a binary “0” to a binary “1”. This change sets the S-R latch722, such that the inverted output of the S-R latch722is at a binary “0”. The inverted output enables the p-channel MOSFET728P and enables the n-channel MOSFET728N, which electrically couples the bootstrap capacitor734from the gate of the first power MOSFET740to the source of the first power MOSFET740. Charge accumulated in the bootstrap capacitor734enables the first power MOSFET740, which electrically couples the high side power supply738to the high side return node730. This changes a voltage at the high side supply node706to the voltage of the high side power supply738plus the voltage across the bootstrap capacitor734. With reference toFIGS.8-13, a series of cross-sectional views800-1300of some embodiments of a method for forming an IC in which a HVMOS device is integrated with a HVJT device is provided. The IC may, for example, be as illustrated and described with respect toFIGS.1,2A,2B,3A, and3B, and/or the cross-sectional views800-1300may, for example, be taken along line A-A′ inFIGS.1,3A, and3B. As illustrated by the cross-sectional view800ofFIG.8, a series of doping processes are performed to form a high side well220, a peripheral well204, an HVJT drift well218, an HVMOS drift well110, and an HVMOS body well112in a semiconductor substrate202. The semiconductor substrate202may be, for example, a bulk silicon substrate, a group III-V substrate, a SOI substrate, or some other semiconductor substrate. The peripheral well204overlies a bulk semiconductor region202B of the semiconductor substrate202, and comprises a pair of segments between which the high side well220, the HVJT drift well218, the HVMOS drift well110, and the HVMOS body well112are sandwiched. Further, the peripheral well204comprises an isolation ring124and a protrusion204P. The isolation ring124provides electrical and physical separation between the HVJT drift well218and the HVMOS drift well110. When viewed top down, the isolation ring124may be square ring shaped, rectangular ring shaped, triangular ring shaped, circular ring shaped, or some other closed path shape. The protrusion204P protrudes laterally into the HVJT drift well218, towards the high side well220, thereby leading to an HVJT RESURF structure232. The HVJT RESURF structure232enables the HVJT device under manufacture to sustain operation at high voltages. In some embodiments, the peripheral well204and the bulk semiconductor region202B have the same doping type, such as, for example, p-type. In some embodiments, the peripheral well204is continuous. For example, the various segments of the peripheral well204may be connected outside the cross-sectional view800ofFIG.8. See, for example,FIG.3B. The HVJT drift well218underlies and laterally surrounds the high side well220to completely separate the high side well220from the peripheral well204and the bulk semiconductor region202B. The HVJT drift well218and the peripheral well204have opposite doping types and partially define the HVJT device under manufacture. Namely, the HVJT device under manufacture is or comprises a diode, and the HVJT drift well218and the peripheral well204define a PN junction of the diode. In some embodiments, the HVJT drift well also has an opposite doping type as the high side well220, and/or has the same doping type as the HVMOS drift well110. The HVMOS drift well110underlies and laterally surrounds the HVMOS body well112to completely separate the HVMOS body well112from the peripheral well204and the bulk semiconductor region202B. The HVMOS drift well110has an opposite doping type as the peripheral well204and the HVMOS body well112. Further, in some embodiments, the HVMOS drift well110has the same doping type as the HVJT drift well218. The HVMOS drift well110and the HVMOS body well112support the HVMOS device under manufacture. The HVMOS body well112comprises a protrusion112P protruding laterally into the HVMOS drift well110, towards the high side well220, thereby leading to an HVMOS RESURF structure216. The HVMOS RESURF structure216enables the HVMOS device under manufacture to sustain operation at high voltages. The doping processes ofFIG.8may, for example, be performed by ion implantation and/or some other doping processes. In some embodiments, the doping processes comprise n-type doping processes and p-type doping processes. The n-type doping processes are performed to form n-type wells, and the p-type doping processes are performed to form p-type wells. The p-type wells may, for example, include the peripheral well204, the high side well220, and the HVMOS body well112, and the n-type wells may, for example, include the HVJT drift well218and the HVMOS drift well110, or vice versa. In some embodiments, some or all of the n-type and p-type doping processes is/are each performed by forming a mask with a pattern over the semiconductor substrate202, performing ion implantation into the semiconductor substrate202with the mask in place, and removing the mask. The mask may, for example, have a pattern of the one or more wells being formed by the ion implantation, and may, for example, be photoresist, silicon nitride, or some other material. As illustrated by the cross-sectional view900ofFIG.9, an isolation structure206is formed over the semiconductor substrate202, demarcating boundaries for doped regions (e.g., contact regions and/or source/drain regions) to be formed hereafter. The isolation structure206comprises a dielectric material (e.g., silicon oxide), and may be or comprise, for example, a STI structure, a FOX structure, a LOCOS structure, or some other isolation structure. Overlying the high side well220, the isolation structure206defines a high side opening902. The high side opening902is on opposite sides of the high side well220and may, for example, have a ring-shaped top layout. Overlying a boundary at which the peripheral well204contacts the HVJT drift well218, the isolation structure206defines a low-side HVJT opening904. Overlying the HVJT drift well218and adjacent to the high side well220, the isolation structure206defines a high-side HVJT opening906. The high-side HVJT opening906is on opposite sides of the high side well220and may, for example, have a ring-shaped top layout. As used herein with respect to the high side opening902and the high-side HVJT opening906, ring-shaped may be circular ring shaped, square ring shaped, rectangular ring shaped, triangular ring shaped, or some other closed path shape. Overlying a boundary at which the HVMOS body well112contacts the HVMOS drift well110, the isolation structure206defines a low-side HVMOS opening908. Overlying the HVMOS drift well110and adjacent to the isolation ring124, the isolation structure206defines a high-side HVMOS opening910. Overlying the peripheral well204and adjacent to the HVMOS drift well110, the isolation structure206defines a peripheral opening912. In some embodiments, a process for forming the isolation structure206comprises forming a mask (not shown) covering the semiconductor substrate202and having a layout of the isolation structure206. The mask may, for example, be silicon nitride, photoresist, or some other suitable mask material. An oxidation process is then performed with mask in place to form the isolation structure206, and the mask is subsequently removed. As illustrated by the cross-sectional view1000ofFIG.10, a dielectric layer1002and a conductive layer1004are formed stacked over the semiconductor substrate202and the isolation structure206. The dielectric layer1002may be or comprise, for example, silicon oxide, hafnium oxide, or some other dielectric, and/or the conductive layer1004may be or comprise, for example, doped polysilicon, metal, or some other conductive material. In some embodiments, the dielectric layer1002is formed by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), some other deposition or oxidation process, or any combination of the foregoing. In some embodiments, the conductive layer1004is formed by CVD, PVD, electroless plating, electroplating, some other deposition or plating process, or any combination of the foregoing. As illustrated by the cross-sectional view1100ofFIG.11, the dielectric layer1002(seeFIG.10) and the conductive layer1004(seeFIG.10) are patterned. Overlying the HVMOS drift well110, the patterning forms a gate electrode120and a gate dielectric layer212stacked in the low-side HVMOS opening908and lining a sidewall of the isolation structure206. Further, the patterning forms an HVMOS field plate214in the high-side HVMOS opening910and lining a sidewall of the isolation structure206. Overlying the HVJT drift well218, the patterning forms a first HVJT field plate226and a field plate dielectric layer228stacked in the low-side HVJT opening904and lining a sidewall of the isolation structure206. Further, the patterning forms a second HVJT field plate230in the high-side HVJT opening906and lining a sidewall of the isolation structure206. In some embodiments, a process for performing the patterning comprises forming a mask overlying the conductive layer1004, and subsequently performing an etch into the conductive layer1004and the dielectric layer1002with the mask in place. The mask is thereafter be removed and may, for example, be or comprise photoresist, silicon nitride, some other mask material, or any combination of the foregoing. In some embodiments, the patterning of the conductive layer1004also forms a spiral structure234overlying both the HVMOS drift well110and the HVMOS drift well218. In other embodiments, the spiral structure234is formed independent of the conductive layer1004and/or the patterning of the conductive layer1004. For example, a second conductive layer (not shown) may be formed and subsequently patterned into the spiral structure234. The second conductive layer may, for example, be a different material than the conductive layer1004and/or may, for example, be metal, doped polysilicon, or some other conductive material. Further, the second conductive layer may, for example, be formed by CVD, PVD, electroless plating, electroplating, some other deposition or plating process, or any combination of the foregoing. The patterning of the second conductive layer may, for example, be performed by photolithography and/or as the patterning of the conductive layer1004is described above. As illustrated by the cross-sectional view1200ofFIG.12, a series of doping processes is performed to form contact regions and source/drain regions in the semiconductor substrate202. A first peripheral contact region208A is formed overlying the peripheral well204, through the peripheral opening912. The first peripheral contact region208A has the same doping type as, but a higher doping concentration than, the peripheral well204. A high side contact region222is formed overlying the high side well220, through the high side opening902. The high side contact region222has the same doping type as, but a higher doping concentration than, the high side well220. A first source/drain region114and a body contact region118are formed overlying the HVMOS body well112, through the low-side HVMOS opening908. A second source/drain region116is formed overlying the HVMOS drift well110, through the high-side HVMOS opening910. The first and second source/drain regions114,116, the body contact region118, the gate electrode120, and the HVMOS field plate214at least partially define an HVMOS device102A on the HVMOS body well112and the HVMOS drift well110. A second peripheral contact region208B is formed overlying the peripheral well204, through the low-side HVJT opening904. A HVJT drift contact region224is formed overlying the HVJT drift well218, through the high-side HVJT opening906. The peripheral well204, the HVJT drift well218, the first and second HVJT field plates226,228, the second peripheral contact region208B, and the HVJT drift contact region224at least partially define an HVJT device104. In some embodiments, the spiral structure234overlies both the HVJT device104and the HVMOS device102and serves as a field plate for both of the HVJT device104and the HVMOS device102. The doping processes ofFIG.12may, for example, be performed by ion implantation and/or some other doping processes. In some embodiments, the doping processes comprise an n-type doping process and a p-type doping process. In some embodiments, each of the doping processes is performed by forming a mask with a pattern over the semiconductor substrate202, performing ion implantation into the semiconductor substrate202with the mask in place, and removing the mask. The mask may, for example, have a pattern of the one or more contact and/or source/drain regions being formed by the ion implantation, and may, for example, be photoresist, silicon nitride, or some other material. As illustrated by the cross-sectional view1300ofFIG.13, a back-end-of-line (BEOL) metallization process is performed to form a plurality of conductive wires236and a plurality of conductive vias238stacked over the semiconductor substrate202. For ease of illustration, only some of the conductive wires236are labeled236, and only some of the conductive vias238are labeled238. The conductive wires236and the conducive vias238define conductive paths interconnecting the first and second source/drain regions114,116, the various contact regions (e.g., the high side contact region222), the various field plates (e.g., the second HVJT field plate230), the gate electrode120, and the spiral structure234. The conductive wires236and the conductive vias238may be or comprise, for example, copper, aluminum copper, aluminum, tungsten, some other conductive material, or any combination of the foregoing. In some embodiments, the conductive vias238are formed by forming an interlayer dielectric (ILD) layer (not shown) covering the structure ofFIG.12, performing a planarization into a top surface of the ILD layer, and patterning the ILD layer to define via openings corresponding to the conductive vias238. The ILD layer is covered with a conductive layer (not shown) and the via openings are filled with the conductive layer. A planarization is performed into a top surface of the conductive layer until the top surface of the conductive layer is about even with the top surface of the ILD layer, thereby forming the conductive vias238from the conductive layer. The above described process for forming the conductive vias238is then repeated for the conductive wires236. With reference toFIG.14, a flowchart1400of some embodiments of the method ofFIGS.8-13is provided. At step1402, a series of doping processes are performed to form a high side well, a HVJT drift well surrounding the high side well, a HVMOS body well, a HVMOS drift well surrounding the HVMOS body well, and a peripheral well surrounding the HVJT drift well and the HVMOS drift well, where the HVJT and HVMOS drift wells border in a ring-shaped pattern, and where the peripheral well comprises an isolation ring separating the HVMOS drift well from the HVJT drift well. See, for example,FIG.8. At step1404, an isolation structure is formed over the semiconductor substrate, demarcating boundaries for doped regions to be formed hereafter. See, for example,FIG.9. The doped regions include, for example, contact regions and source/drain regions. At step1406, a dielectric layer and a conductive layer are deposited on the semiconductor substrate and the isolation structure. See, for example,FIG.10. At step1408, the dielectric layer and the conductive layer are patterned into a gate electrode, field plates, and a spiral structure, wherein the gate electrode overlies a PN junction between the HVMOS body and drift wells, and where the spiral structure is shared by HVMOS and HVJT devices under manufacture. See, for example,FIG.11. At step1410, a series of doping processes is performed to form source/drain regions and contact regions, where the source/drain regions and a body contact region are formed on the HVMOS body well and the HVMOS drift well, and where a peripheral contact region and a HVJT drift contact region are respectively formed on the peripheral well and the HVJT drift well. See, for example,FIG.12. The source/drain regions, the body contact region and the gate electrode at least partially define an HVMOS device on the HVMOS drift well and the HVMOS body well. The peripheral contact region, the HVJT drift contact region, the HVJT drift well, and the peripheral well at least partially define an HVJT device. At step1412, a BEOL metallization process is performed to form a plurality of conductive wires and a plurality of conductive vias interconnecting the source/drain regions, the contact regions, the gate electrodes, the field plates, and the spiral structure. See, for example,FIG.13. While the flowchart1400ofFIG.14is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. In some embodiments, the present application provides an integrated circuit including: a substrate; a first drift well and a second drift well in the substrate, wherein the first and second drift wells border in a ring-shaped pattern and have a first doping type; a peripheral well in the substrate and having a second doping type, wherein the peripheral well surrounds and separates the first and second drift wells, and wherein the second doping type is opposite the first doping type; a body well in the substrate and having the second doping type, wherein the body well overlies the first drift well and is spaced from the peripheral well by the first drift well; and a gate electrode overlying a junction between the first drift well and the body well. In some embodiments, the integrated circuit further includes a high side well in the substrate and having the second doping type, wherein the high side well overlies the second drift well and is spaced from the peripheral well by the second drift well. In some embodiments, the integrated circuit further includes a high side contact region overlying the high side well, wherein the high side contact region extends laterally along a periphery of the high side well in a closed path, and wherein the high side contact region has the same doping type as, but a higher doping concentration than, the high side well. In some embodiments, the integrated circuit further includes a drift contact region overlying the second drift well, wherein the drift extends laterally along a periphery of the high side well in a closed path to completely enclose the high side well, wherein the drift contact region has the same doping type as, but a higher doping concentration than, the second drift well, and wherein the drift contact region separates the high side well from the first drift well. In some embodiments, the substrate includes a bulk semiconductor region having the second doping type, wherein the first and second drift wells and the peripheral well overlie the bulk semiconductor region. In some embodiments, the integrated circuit further includes a first source/drain region and a second source/drain region, wherein the first and second source/drain regions respectively overlie the body well and the first drift well, and wherein the first and second source/drain regions are separated by the body well and the first drift well. In some embodiments, the integrated circuit the body well protrudes laterally into the first drift well towards the second drift well, such that the substrate has an alternating stack of p-type and n-type regions defining a RESURF structure. In some embodiments, the peripheral well protrudes laterally into the second drift well towards the first drift well, such that the substrate has an alternating stack of p-type and n-type regions defining a RESURF structure. In some embodiments, the integrated circuit further includes a spiral structure overlying both the first and second drift wells, wherein the spiral structure is conductive and has a continuous, spiral-shaped top layout. In some embodiments, the integrated circuit further includes: a diode including a PN junction defined by the peripheral well and the second drift well; and a LDMOS device on the body well and the first drift well, wherein the LDMOS device includes the gate electrode. In some embodiments, the present application provides another integrated circuit including: a semiconductor substrate; a drift well in the semiconductor substrate, wherein the drift well has a first doping type and has a ring-shaped top layout; a high side well in the semiconductor substrate and having a second doping type opposite the first doping type, wherein the high side well overlies the drift well and is surrounded by the drift well; a switching device on the semiconductor substrate, at an indent in the drift well, wherein the drift well separates the switching device from the high side well; and a peripheral well in the semiconductor substrate and having the second doping type, wherein the peripheral well surrounds the drift well and the switching device, and wherein the peripheral well separates the switching device from the drift well. In some embodiments, the integrated circuit further includes: a second drift well in the semiconductor substrate, wherein the second drift well borders the drift well and has the first doping type; and a body well in the semiconductor substrate and having the second doping type, wherein the body well overlies the second drift well and is spaced from the peripheral well by the second drift well, and wherein the switching device is on the second drift well and the body well. In some embodiments, the integrated circuit further includes: a high side contact region overlying the high side well; and a drift contact region overlying the drift well, wherein the drift contact region extends along a periphery of the high side well in a closed path to enclose the high side well and the high side contact region, and wherein the high side contact region and the drift contact region have ring-shaped top layouts and respectively have opposite doping types. In some embodiments, the high side well has an indentation adjacent to the switching device, and wherein the high side contact region and the drift contact region conform to the indent. In some embodiments, the integrated circuit further includes: a second drift well bordering the drift well in the semiconductor substrate and having the first doping type; a body well in the semiconductor substrate and having the second doping type, wherein the body well overlies the second drift well and is completely spaced from the peripheral well by the second drift well; and a gate electrode overlying an NP junction at which the second drift well and the body well directly contact, wherein the second drift well, the body well, and the gate electrode are independent of the switching device. In some embodiments, the drift well directly contacts the peripheral well at a PN junction, and wherein the PN junction has a continuous, ring-shaped top layout. In some embodiments, the peripheral well protrudes into the drift well towards the high side well, such that the semiconductor substrate has an alternating stack of p-type and n-type regions defining a RESURF structure. In some embodiments, the integrated circuit further includes a spiral structure overlying both the drift well and the switching device, wherein the spiral structure is conductive and has a continuous, spiral-shaped top layout that completely encloses the high side well. In some embodiments, the present application provides a method for manufacturing an integrated circuit, the method including: performing a series of doping processes into a substrate to form: a first drift well and a second drift well bordering and having a first doping type, wherein the second drift well has a ring-shaped top layout, and wherein the first drift well is at an indent in the ring-shaped top layout; a peripheral well having a second doping type opposite the first doping type, wherein the peripheral well surrounds and separates the first and second drift wells; and a body well having the second doping type, wherein the body well overlies the first drift well and is spaced from the peripheral well by the first drift well; forming an isolation structure overlying the first and second drift wells; and forming a gate electrode overlying a junction between the first drift well and the body well, and extending from the junction, along a sidewall of the isolation structure, to a top surface of the isolation structure. In some embodiments, the method further includes: depositing a conductive layer over the substrate and the isolation structure; and patterning the conductive layer to form the gate electrode, and to further form a spiral structure overlying the first and second drift wells on the top surface of the isolations structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 76,678 |
11862676 | REFERENCE NUMERALS 100drift region;110body region;111first doped region;112second doped region;121first trench gate;122second trench gate;130dielectric layer;141first conductive structure;142second conductive structure;143third conductive structure;150extension region;160second electrode lead-out region;171first trench;172second trench;173contact hole;200interlayer dielectric layer;310first electrode;320second electrode. DETAILED DESCRIPTION In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the related drawings. Preferred embodiments of the present application are shown in the accompanying drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be more thorough and complete. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification are for the purpose of describing specific embodiments only, and are not intended to limit the present application. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. The semiconductor device in the present application will be described below with reference toFIG.1. The semiconductor device includes:A drift region100, with a first conductivity type, and the drift region100can specifically be an epitaxial layer formed by epitaxial growth on a semiconductor substrate;A body region110, with a second conductivity type, is formed in the drift region100, and is specifically formed on the upper surface layer of the drift region100;A first doped region111and a second doped region112, both are formed in the body region110, where the first doped region111has the first conductivity type, the second doped region112has the second conductivity type, and the doping concentration of the second doped region112is higher than the doping concentration of the body region110;A first trench gate121and an extension region150, the first trench gate121is formed by filling a first trench. The first trench penetrates the first doped region111and the body region110and extends into the drift region100, i.e. the bottom of the first trench is located in the drift region100. The extension region150with the second conductivity type is formed in the drift region100under the first trench and surrounds the bottom wall of the first trench. The first trench is filled with a first conductive structure141located at the bottom of the first trench and a second conductive structure142located at the top of the first trench, and the first conductive structure141and the second conductive structure142are isolated from each other. Specifically, a dielectric layer can be formed between the first conductive structure141and the second conductive structure142, so that the conductive structures on the upper and lower sides are separated by the dielectric layer; for example, a dielectric layer130is formed between the second conductive structure142and the inner wall of the first trench, and the dielectric layer130is also formed between the first conductive structure141and the inner wall of the first trench not surrounded by the extension region150. It can be understood that the depth of the second conductive structure142is greater than or equal to the depth of the body regions110on both sides to ensure that conduction channels can be formed in the body regions110on both sides;A second trench gate122, is formed by filling a second trench. The second trench penetrates the first doped region111and the body region110, and can further extend into the drift region100. The second trench is filled with a third conductive structure143and the dielectric layer130which is between the third conductive structure143and the inner wall of the second trench;A gate (not shown in the figure), is electrically connected to the second conductive structure142and the third conductive structure143, where the second conductive structure142and the dielectric layers130on both sides of the second conductive structure142form a gate structure, the third conductive structure143and the dielectric layers130on both sides of the third conductive structure143also form a gate structure, and the gate structures are connected to the gate. After a potential is obtained from the gate, conduction channels are formed inside the body region110on both sides of the gate structures;A first electrode310, is electrically connected to the first doped region111and the second doped region112, and a second electrode lead-out region160is in contact with the drift region100and leads out a second electrode320. It can be understood that an interlayer dielectric layer200is further formed on each trench gate and doped region, and the first electrode310is electrically connected to the first doped region111and the second doped region112through a contact hole. After the gate is applied with a potential to form a conduction channel in the body region110, a current path can be formed between the first electrode310and the second electrode320. Specifically, the first conductive structure141, the second conductive structure142and the third conductive structure143may be polysilicon, and the dielectric layer may be an oxide layer. The first conductivity type is P type and the second conductivity type is N type, or, the first conductivity type is N type and the second conductivity type is P type. A trench gate structure of the semiconductor device described above is divided into the first trench gate121and the second trench gate122, where the second conductive structure142and the dielectric layer130in the upper half of the first trench gate121form the gate structure, while the first conductive structure141and the dielectric layer130in the lower half of the first trench gate121are used as an inner field plate, through which the electric field of the drift region can be adjusted to enhance the depletion of the drift region. The bottom of the first trench gate121is surrounded by the extension region150, and the conductivity type of the extension region150is opposite to that of the drift region100, which can further enhance the depletion of the drift region100. Under the combined action of the above-mentioned inner field plate and the extension region150, the depletion of the drift region can be enhanced, thereby increasing the breakdown voltage of the drift region. Therefore, under the condition of having a same breakdown voltage, the doping concentration of the drift region100of the semiconductor device in the present application can be increased, thereby reducing the on-resistance, that is, under the condition of having a same breakdown voltage, the semiconductor device in the present application can have a lower on-resistance and on-voltage drop. On the other hand, the extension region150surrounds the bottom of the first trench, which can transfer the breakdown position from the trench gate to the interface between the extension region150and the drift region100, thereby allowing the breakdown more stable. Meanwhile, the combined use of the first trench gate121and the second trench gate122can enhance the depletion of the drift region and reduce the process cost as much as possible. In one embodiment, as shown inFIG.1, the first trench gates121and the second trench gates122are alternately distributed side by side, and further, the interval between adjacent trench gates is equal, so that the distribution of the inner field plate and the extension regions is uniform, the depletion regions in the drift region100are uniformly distributed, and the withstand voltage of the device is further improved. In one embodiment, as shown inFIG.1, the depth of the second trench is smaller than that of the first trench, i.e. the depth of the second trench gate122is smaller than that of the first trench gate121. Further, the bottom of the second trench is flush with the top of the first conductive structure141. In this embodiment, since the second trench gate122is only used as a gate structure, it does not participate in the adjustment of the drift region100, the extension length of the second trench gate122in the drift region100can be reduced on the premise of ensuring that the second trench gate122penetrates the body region110, which can not only reduce the process cost, but also reduce the space occupied by the second trench gate122in the drift region100to avoid current crowding in the drift region100from affecting the current intensity. In the present application, the distribution of the first doped region111and the second doped region112may have various forms. In one embodiment, the first doped region111and the second doped region112may be formed side by side on the upper surface layer of the body region110, and are respectively led out through different contact holes and are electrically connected to the first electrode310. In another embodiment, as shown inFIG.1, the first doped region111is formed on the upper surface layer of the body region110, and the second doped region112is formed in the body region110below the first doped region111and is connected with the first doped region111. The first doped region111is provided with a contact hole penetrating the first doped region111and exposing the second doped region112. At this time, the first electrode310can be electrically connected to the first doped region111and the second doped region112through the contact hole, respectively. In the present application, the first conductive structure141may be a floating structure (no potential is connected), or may obtain the potential of the first electrode310by being electrically connected to the first electrode310. For the case where the first conductive structure141and the first electrode310are electrically connected, specifically, the first conductive structure141can be led out from one end of the first trench, and then directly electrically connected to the first electrode310through the contact hole, or a dielectric layer can be provided between the first conductive structure141and the first electrode310with a thickness that enable the first conductive structure141to obtain the induced potential from the first electrode310. When the first conductive structure141and the first electrode310are electrically connected in an inductive manner, the first conductive structure141can obtain an induced potential, and the leakage path between the first electrode310and the first conductive structure141can be cut off to avoid electrical leakage of the first electrode310. In one embodiment, when the first conductive structure141is electrically connected to the first electrode310, the parasitic capacitance between the gate and the second electrode320can be reduced. In the present application, the specific designs of the first trench gate121and the extension region150may have various forms. In one embodiment, the dielectric layer130is formed between the first conductive structure141and the inner wall of the first trench not surrounded by the extension region150, and at least part of the bottom wall of the first trench surrounded by the extension region150is not covered by the dielectric layer, i.e. the extension region150is in contact with the first conductive structure141. At this case, the extension region150and the first conductive structure141have the same potential. If the first conductive structure141is a floating structure, then the extension region150is also a floating structure; if the first conductive structure141is electrically connected to the first electrode310, then the extension region150is also electrically connected to the first electrode310through the first conductive structure141to have a certain potential, so that the depletion of the drift region100can be further enhanced. As shown inFIG.2, in one embodiment, the dielectric layer130is formed between the first conductive structure141and the inner wall of the first trench not surrounded by the extension region150, and the bottom wall of the first trench surrounded by the extension region150is also covered by the dielectric layer, i.e. the dielectric layer130is formed on the entire inner wall of the first trench, and the extension region150is isolated from the first conductive structure141by the dielectric layer130. At this case, regardless of whether the first conductive structure141is charged or not, the extension region150has a floating structure, thereby further avoiding electrical leakage of the electrode. In one embodiment, as shown inFIGS.1and2, the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor), where the first electrode310is used as an emitter, and the second electrode lead-out region160includes an collector region162and a buffer region161located between the collector region162and the drift region100; the buffer region161has the first conductivity type and the doping concentration of the buffer region161is greater than that of the drift region100; the collector region162has the second conductivity type, and the second electrode320is used as a collector electrode. Specifically, the second electrode lead-out region160is formed on the side of the drift region100which is away from the body region110. In this embodiment, in the case of the semiconductor device is an IGBT, the first trench gate121extends into the drift region100and the extension region150surrounds the bottom of the first trench gate121, which can not only adjust the electric field in the drift region, but also accelerate a recombination of the remaining charge carriers in the drift region100when the IGBT is turned off, thereby increasing the switching speed of the IGBT, and adjusting the switching characteristics of the device to optimize the device performance. In one embodiment, as shown inFIGS.3and4, the semiconductor device may also be a MOS transistor, whereFIG.3is a schematic structural diagram showing the contact between the first conductive structure141and the extension region150;FIG.4is a schematic structural diagram showing that the isolation of the first conductive structure141and the extension region150. The first electrode310is a source electrode, the second electrode lead-out region160has the first conductivity type, specifically may be a semiconductor substrate having the first conductivity type, and the second electrode320is a drain electrode. It should be noted that “N” and “P” inFIGS.1to4represent the conductivity types of the corresponding regions. InFIGS.1to4, as an example, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type type. The present application further provides a method for preparing semiconductor device, as shown inFIG.5, the method includes the following steps: Step S510: forming a drift region with a first conductivity type, forming a first trench in the drift region, and forming a dielectric layer on the inner wall of the first trench. As shown inFIG.6a, the drift region100with the first conductivity type can be formed on a semiconductor substrate (not shown in the figure) by epitaxial growth, the first trench171is formed in the drift region100, and the dielectric layer130is formed on the inner wall of the first trench171. The dielectric layer130may be an oxide layer, and specifically the oxide layer may grow on the inner wall of the first trench171by a thermal oxidation process. Step S520: doping the drift region at the bottom of the first trench with dopants with the second conductivity type through the first trench to form an extension region surrounding the bottom wall of the first trench. As shown inFIG.6b, dopants with the second conductivity type are doped into the drift region100through the first trench171to form an extension region150surrounding and contacting with the bottom wall of the first trench171. Step S530: filling the first trench with a first conductive structure. As shown inFIG.6c, the first conductive structure141is filled into the first trench171. Specifically, the first conductive structure141may be polysilicon. In one embodiment, between step S520and step S530, the method may further include: Etching at least part of the dielectric layer on the bottom wall of the first trench surrounded by the extension region to expose the extension region. Specifically, the dielectric layer130on the bottom wall of the first trench171may be dry-etched to form an opening exposing the extension region150. in this case, in step S530, after the first conductive structure141is filled, the first conductive structure141is in contact with the extension region150. Step S540: Simultaneously etching the first conductive structure in the first trench and the drift regions on both sides of the first trench, removing the first conductive structure at the top of the first trench and retaining the first conductive structure at the bottom of the first trench; at the same time, forming second trenches on both sides of the first trench. As shown inFIG.6d, the first conductive structure141in the first trench171and the drift regions100on both sides of the first trench are etched simultaneously, the first conductive structure on the top of the first trench171is removed and the first conductive structure141at the bottom of the first trench171is retained, and the second trenches172are formed on both sides of the first trench171. Since the etching of the first conductive structure141and the etching of the drift region100are performed simultaneously, the etching depth of the first conductive structure141and that of the drift region100are the same in the etching process, i.e. the bottom of the second trench172is flush with the top of the remaining first conductive structure141. Step S550: filling the first trench and the second trench with the dielectric layer at the same time. As shown inFIG.6e, the first trench171and the second trench172are filled with the dielectric layer130at the same time. Specifically, a relatively thick dielectric layer130can be deposited by a deposition process to fill the first trench171and the second trench172, and then the excess dielectric layer outside the trenches can be removed by a grinding process. Step S560: Simultaneously etching and removing part of the dielectric layer in the top of the first trench and the top of the second trench, retaining part of the dielectric layer on the first conductive structure and at the bottom of the second trench. As shown inFIG.6f, part of the dielectric layer on the top of the first trench171and the top of the second trench172is etched at the same time, and part of the dielectric layer on the first conductive structure141and at the bottom of the second trench172is retained. Step S570: forming the dielectric layer on the exposed sidewalls of the first trench and the second trench at the same time, and then filling the first trench and the second trench with a conductive material at the same time to form a second conductive structure at the upper part of the first trench and a third conductive structure inside the second trench. As shown inFIG.6g, the dielectric layer is formed on the exposed sidewalls of the first trench and the second trench at the same time, and then the conductive material is filled into the first trench and the second trench at the same time, where the conductive material filled on the top of the first trench forms the second conductive structure142, and the conductive material filled in the second trench forms the third conductive structure143. Specifically, the above-mentioned conductive material can also be polysilicon. At this case, the structure filled in the first trench forms a first trench gate121, the structure filled in the second trench forms a second trench gate122. The bottom of the first trench gate121is surrounded by the extension region150, and the depth of the first trench gate121is greater than that of the second trench gate122. Step S580: doping the drift region with dopants with the second conductivity type, forming body regions on both sides of the first trench and the second trench, and doping the body regions with dopants with the first conductivity type and dopants with the second conductivity type to form a first doped region and a second doped region, respectively. The doping concentration of the second doped region is greater than that of the body region, and the second doped region is spaced apart from the first trench and the second trench. In one embodiment, between step S570and step S580, the following steps are further included: Forming a dielectric layer covering the second conductive structure and the third conductive structure on the top of the first trench and the top of the second trench, respectively. Specifically, as shown inFIG.6e, a portion of the second conductive structure142and the third conductive structure143located at the top of the trenches may be etched away, and then a oxide layer grows on top of the second conductive structure142and the top of the third conductive structure143by thermal oxidation. In this embodiment, the oxide layer grows on the top of the second conductive structure142and the third conductive structure143, which can prevent dopants from being doped into the second conductive structure142and the third conductive structure143of the trenches during the doping process in step S580. As shown inFIG.6h, after the first trench gate121and the second trench gate122are formed, the upper surface layer of the drift region100is doped with dopants with the second conductivity type. The body regions110contacting the sidewalls of the first trench121and the second trench122are formed on both sides of the trenches. It can be understood that the depth of the body region110is less than or equal to the depth of the second trench gate122. In one embodiment, the process of forming the body region110is specifically a drive-in process at high temperature, where the temperature and time of the drive-in process can be adjusted according to the doping depth and doping concentration of the body region, specifically, the temperature of the drive-in process can be controlled within the range of 900° C.-1200° C., and the time of the drive-in process can be controlled within the range of 10 min-180 min. During the formation of body region110by the drive-in process, the dopant ions of the extension region150diffuses outward, so that the extension region150is expanded outward, thereby increasing the volume of the extension region150. Specifically, the distributions of a first doped region111and a second doped region112may have various forms, and correspondingly, the processes for forming the first doped region111and the second doped region112may also have various options. In one embodiment, as shown inFIGS.6hand6i, the first doped region111is stacked on the second doped region112, and the corresponding process may include: A step S581, doping dopants with the first conductivity type on the upper surface layer of the body region110to form the first doped region111in contact with the first trench and the second trench. A step S582, forming a contact hole173penetrating the first doped region111and exposing the body region110, and doping the exposed body region110with dopants with the second conductivity type through the contact hole to form the second doped region112located under the first doped region111. Further, the contact hole173may extend into the body region110. A step S583, doping the body region110exposed through the contact hole173with dopants with the second conductivity type to form the second doped region112. After that, a first electrode310can be electrically connected to the first doped region111and the second doped region112through the contact hole173, respectively. Further, between step S581and step S582, the following step is also included: Forming an interlayer dielectric layer200on the first trench gate121, the second trench gate122and the first doped region111. In step S582, before etching the first doped region111, the interlayer dielectric layer200is etched so that the contact hole173can penetrate the interlayer dielectric layer200. Step S590: forming a gate electrically connected to the second conductive structure and the third conductive structure, a first electrode electrically connected to the first doped region and the second doped region, and leading out a second electrode through a second electrode lead-out region in contact with the drift region. In one embodiment, as shown inFIG.6j, the first electrode310and the gate (not shown in the figure) are formed, and the second electrode320is led out through the second electrode lead-out region160. In one embodiment, the first doped region111and the second doped region112are formed through the above-mentioned steps S581to S583, and the contact holes penetrating the first doped region111and extending into the second doped region112are simultaneously formed, the first doped region111and the second doped region112are exposed through the contact holes. Therefore, the first electrode310can be electrically connected to the first doped region111and the second doped region112only through depositing one metal layer and filling the contact hole with the metal layer. In one embodiment, as shown inFIG.6j, the above-mentioned semiconductor device is specifically an IGBT, the first electrode310is used as an emitter, and the second electrode lead-out region160includes a collector region162and a buffer region161located between the collector region162and the drift region100, and the second electrode lead-out region160may be formed in step S590. The buffer region161has the first conductivity type and the doping concentration of the buffer region161is greater than that of the drift region100, the collector region162has the second conductivity type, and the second electrode320is used as a collector electrode. Specifically, the second electrode lead-out region160is formed on the side of the drift region100away from the body region110. In an embodiment, as shown inFIG.3andFIG.4, the semiconductor device may also be a MOS transistor. The first electrode310is a source electrode, the second electrode lead-out region160has the first conductivity type, specifically can be a semiconductor substrate having the first conductivity type, and the second electrode320is a drain electrode. In the above-mentioned method for preparing semiconductor device, the first trench gate121and the second trench gate122are formed in the cellular region, where the upper part of the first trench gate121forms a gate structure, and the lower part of the first trench121is used as an inner field plate. Meanwhile, the bottom of the first trench gate121is surrounded by the extension region150, and the conductivity type of the extension region150is opposite to that of the drift region100. Therefore, under the combined action of the above-mentioned inner field plate and the extension region, the depletion of the drift region can be enhanced, thereby increasing the breakdown voltage of the drift region. On the other hand, the extension region150surrounding the bottom of the first trench can transfer the breakdown position from the trench gate to the interface between the extension region150and the drift region100, thereby making the breakdown more stable. At the same time, since the second trench gate122and the upper part of the first trench are both used as gate structures, in the preparing process, after the first conductive structure141is formed and the dielectric layer is filled in the first trench, the second trench gate122and the structure located on the first conductive structure141inside the first trench can be simultaneously formed, thereby saving process cost. The above embodiments are only used to illustrate several implementations of the present application, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the present invention. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims. | 28,751 |
11862677 | DETAILED DESCRIPTION According to an embodiment, a semiconductor device includes a semiconductor part, a first electrode and a plurality of control electrodes. The semiconductor part includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type. The plurality of trenches are provided at a front side of the semiconductor part. The first electrode is provided at the front side of the semiconductor part. The plurality of control electrodes are provided in the plurality of trenches, respectively. The plurality of control electrodes each are electrically insulated from the semiconductor part via an insulating film. The plurality of control electrodes include a first control electrode, and a second control electrode next to the first control electrode. The second semiconductor layer is provided between the first semiconductor layer and the first electrode. The second semiconductor layer is provided between the first and second control electrodes. The second semiconductor layer faces the first and second control electrodes via the insulating film. The third and fourth semiconductor layers are provided between the second semiconductor layer and the first electrode. The third and fourth semiconductor layers are electrically connected to the first electrode and arranged along a front surface of the second semiconductor layer facing the first electrode. The semiconductor part further includes a first region partially provided between the first semiconductor layer and the second semiconductor layer. The first region is provided between the first semiconductor layer and the third semiconductor layer, the first region including a material having a lower thermal conductivity than the first semiconductor layer. Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated. There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward. FIG.1is a perspective view schematically showing a semiconductor device1according to an embodiment. The semiconductor device1is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device1includes, for example, a semiconductor part10, a first electrode, a second electrode, and multiple control electrodes GE1to GE3. The first electrode is provided on the front surface of the semiconductor part10; and the second electrode is provided on the back surface of the semiconductor part10(referring toFIGS.2A and2B). The first electrode and the second electrode are not illustrated inFIG.1. As shown inFIG.1, the semiconductor device1includes the multiple control electrodes GE1to GE3. The control electrodes GE1to GE3are provided respectively inside trenches TR that are provided in the semiconductor part10. The control electrodes GE1to GE3are electrically insulated from the semiconductor part10respectively by a gate insulating film GI. The control electrodes GE1and GE2are, for example, gate electrodes. The control electrode GE3is controlled, for example, independently of the control electrodes GE1and GE2. The control electrode GE2is next to the control electrode GE1. The control electrode GE2is provided between the control electrode GE1and the control electrode GE3. The control electrode GE3is next to the control electrode GE2. The semiconductor part10includes, for example, a first semiconductor layer11of a first conductivity type, a second semiconductor layer13of a second conductivity type, a third semiconductor layer15of the first conductivity type, and a fourth semiconductor layer17of the second conductivity type. The semiconductor part10includes, for example, silicon. Hereinbelow, the first conductivity type is described as an n-type, and the second conductivity type is described as a p-type. The first semiconductor layer11is, for example, an n-type drift layer or an n-type base layer. The control electrodes GE1to GE3extend from the front side of the semiconductor part10into the first semiconductor layer11. The second semiconductor layer13is, for example, a p-type diffusion layer or a p-type base layer. The second semiconductor layer13, for example, is provided on the first semiconductor layer11between the control electrode GE1and the control electrode GE2and between the control electrode GE2and the control electrode GE3. The second semiconductor layer13faces the control electrodes GE1to GE3via the gate insulating film GI. The third semiconductor layer15is, for example, an n-type source layer or an n-type emitter layer. The third semiconductor layer15is provided on the second semiconductor layer13between the control electrode GE1and the control electrode GE2. For example, the third semiconductor layer15contacts the gate insulating film GI at a side of the control electrode GE1. The fourth semiconductor layer17is, for example, a p-type contact layer. The fourth semiconductor layer17is provided on the second semiconductor layer13between the control electrode GE1and the control electrode GE2and between the control electrode GE2and the control electrode GE3. The third semiconductor layer15and the fourth semiconductor layer17are arranged on the second semiconductor layer13between the control electrode GE1and the control electrode GE2. The fourth semiconductor layer17includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second semiconductor layer13. As shown inFIG.1, the semiconductor part10further includes a guard region GR. The guard region GR is partially provided between the first semiconductor layer11and the second semiconductor layer13. The guard region GR is located between the control electrodes GE1and GE2. Also, the guard region GR is positioned between the first semiconductor layer11and the third semiconductor layer15. The guard region GR includes a material that has a lower thermal conductivity than the first semiconductor layer11. In other words, the guard region GR suppresses the thermal conduction from the first semiconductor layer11into the second semiconductor layer13. That is, the Joule heat generated in the first semiconductor layer11is suppressed to conduct into the region of the second semiconductor layer13under the third semiconductor layer15. The guard region GR may include, for example, an insulating body. The guard region GR includes the same material as the gate insulating film GI, e.g., silicon oxide. The guard region GR may include a semiconductor that has an amorphous structure, e.g., amorphous silicon. FIG.2Ais a schematic cross-sectional view showing the semiconductor device1according to the embodiment.FIG.2Ais a schematic view illustrating a cross section parallel to the Y-Z plane between the control electrode GE1and the control electrode GE2. The semiconductor device1is a MOSFET. As shown inFIG.2A, the semiconductor device1includes a first electrode SE and a second electrode DE. The first electrode SE is, for example, a source electrode. The second electrode DE is, for example, a drain electrode. The semiconductor part10is provided between the first electrode SE and the second electrode DE. The control electrodes GE1to GE3extend into the first semiconductor layer11from the front surface of the semiconductor part10that faces the first electrode SE (referring toFIG.1). The first semiconductor layer11extends between the first electrode SE and the second electrode DE. The first semiconductor layer11is, for example, an n-type drift layer. The second semiconductor layer13is provided between the first semiconductor layer11and the first electrode SE. The second semiconductor layer13is, for example, a p-type diffusion layer. The third semiconductor layer15and the fourth semiconductor layer17are provided between the second semiconductor layer13and the first electrode SE. The third semiconductor layer15is, for example, an n-type source layer. The third semiconductor layer15and the fourth semiconductor layer17are arranged along the surface of the second semiconductor layer13that faces the first electrode SE. The third semiconductor layer15and the fourth semiconductor layer17are in contact with the first electrode SE and electrically connected thereto. The second semiconductor layer13is electrically connected to the first electrode SE via the fourth semiconductor layer17. The control electrodes GE1to GE3(referring toFIG.1) extend in a direction (e.g., a Y-direction) along the front surface of the semiconductor part10. The second semiconductor layer13and the fourth semiconductor layer17extend along the extension direction of the control electrodes GE1to GE3(i.e., the Y-direction). For example, the third semiconductor layer15and the fourth semiconductor layer17are arranged in the extension direction of the control electrodes GE1and GE2(i.e., the Y-direction). The width in the Y-direction of the fourth semiconductor layer17is greater than the width in the Y-direction of the third semiconductor layer15. The guard region GR is partially provided between the first semiconductor layer11and the second semiconductor layer13. The guard region GR is positioned between the first semiconductor layer11and the third semiconductor layer15. A width WR of the guard region GR is greater than a width WS of the third semiconductor layer15in a direction (e.g., the Y-direction) along the boundary between the first semiconductor layer11and the second semiconductor layer13. The second semiconductor layer13includes a portion that is positioned between the guard region GR and the fourth semiconductor layer17. The semiconductor part10further includes a fifth semiconductor layer19of the first conductivity type. The fifth semiconductor layer19is, for example, a drain layer. The fifth semiconductor layer19is provided between the first semiconductor layer11and the second electrode DE. The fifth semiconductor layer19includes a first-conductivity-type impurity with a higher concentration than a first-conductivity-type impurity of the first semiconductor layer11. For example, the fifth semiconductor layer19is in contact with the second electrode DE and electrically connected thereto. The second electrode DE is electrically connected to the first semiconductor layer11via the fifth semiconductor layer19. FIG.2Bis a schematic cross-sectional view showing a semiconductor device2according to the embodiment.FIG.2Bis a schematic view illustrating a cross section parallel to the Y-Z plane between the control electrode GE1and the control electrode GE2. The semiconductor device2is, for example, an IGBT. As shown inFIG.2B, the semiconductor device2includes a first electrode EE and a second electrode CE. The first electrode EE is, for example, an emitter electrode. The second electrode CE is, for example, a collector electrode. The semiconductor part10is provided between the first electrode EE and the second electrode CE. The first semiconductor layer11is, for example, an n-type base layer. The second semiconductor layer13is, for example, a p-type base layer. The third semiconductor layer15is, for example, an n-type emitter layer. The fifth semiconductor layer19is, for example, an n-type buffer layer. The semiconductor part10further includes a sixth semiconductor layer21of the second conductivity type. The sixth semiconductor layer21is provided between the fifth semiconductor layer19and the second electrode CE. The sixth semiconductor layer21is, for example, a p-type collector layer. The sixth semiconductor layer21is in contact with the second electrode CE and electrically connected thereto. Also, in the example, the semiconductor part10includes the guard region GR. The guard region GR is partially provided between the first semiconductor layer11and the second semiconductor layer13. Also, the guard region GR is provided between the first semiconductor layer11and the third semiconductor layer15. The semiconductor device1or the semiconductor device2according to the embodiment is used in, for example, a power conversion device such as an inverter, etc., and is connected in series with another semiconductor device between power lines. When a short-circuit fault occurs in, for example, the other semiconductor device, a short-circuit current (an overcurrent) flows in the semiconductor device1or2. By providing the guard region GR in the semiconductor devices1and2, the thermal conduction from the first semiconductor layer11into the second semiconductor layer13is suppressed, and the Joule heat generated by such an overcurrent can be prevented from conducting in the second semiconductor layer13. Thus, it is possible in the second semiconductor layer13to prevent the temperature increase. Therefore, the n-p-n parasitic transistor that includes the first semiconductor layer11, the second semiconductor layer13and the third semiconductor layer15can be prevented from the turn-on. As a result, a further increase of the overcurrent and the resulting heat generation, i.e., so-called thermal runaway, can be suppressed, and the element breakdown can be avoided. The guard region GR can be formed by partially forming an insulating body of, for example, silicon oxide or the like in the first semiconductor layer11; subsequently, another semiconductor layer that is to be the second semiconductor layer13, the third semiconductor layer15, and the fourth semiconductor layer17is epitaxially grown. Alternatively, the portion of the first semiconductor layer11that becomes the guard region GR may be amorphized by ion-implanting hydrogen atoms thereinto. FIG.3is a perspective view schematically showing a semiconductor device3according to a first modification of the embodiment. The semiconductor device3is, for example, a MOSFET. The first electrode SE, the second electrode DE, and the control electrodes GE1to GE3are not illustrated inFIG.3. Alternately, the semiconductor device3may be an IGBT. This is also similar for the following examples. In the semiconductor device3, a first-conductivity-type inversion layer is induced by the control electrodes GE1and GE2at the interfaces between the second semiconductor layer13and the gate insulating film GI. During the turn-on period in the semiconductor device3, an electron current flows from the third semiconductor layer15toward the first semiconductor layer11via the inversion layer. This is the same in the semiconductor devices according to the other examples. According to the embodiment, the guard region GR is provided between the first semiconductor layer11and the second semiconductor layer13, and thus, the electron current Ie flows toward the first semiconductor layer11from the third semiconductor layer15via a detour around the guard region GR. Therefore, the channel length from the third semiconductor layer15to the first semiconductor layer11is increased and makes the on-resistance increase. According to the embodiment, the advantage of suppressing thermal runaway is prioritized over the on-resistance. As shown inFIG.3, the fourth semiconductor layer17is apart from the third semiconductor layer15. The second semiconductor layer13includes a portion that extends between the third semiconductor layer15and the fourth semiconductor layer17. The width in a Z-direction of the first-conductivity-type inversion layer that is induced at the interface between the second semiconductor layer13and the gate insulating film GI can be increased thereby. As a result, in the semiconductor device3, the path of the electron current that flows from the third semiconductor layer15to the first semiconductor layer11via the inversion layer can be widened, and the on-resistance can be reduced. FIGS.4A and4Bare schematic cross-sectional views showing a semiconductor device4according to a second modification of the embodiment. FIG.4Ais a schematic view illustrating a cross section along line A-A shown inFIG.4B. FIG.4Bis a schematic view illustrating a cross section along line B-B shown inFIG.4A. As shown inFIG.4A, the semiconductor device4includes a planar control portion PG that links the control electrode GE1and the control electrode GE2. The planar control portion PG is provided on the front surface of the semiconductor part10. The planar control portion PG is provided between the second semiconductor layer13and the first electrode SE and faces the second semiconductor layer13via the gate insulating film GI. The planar control portion PG is electrically insulated from the first electrode SE by an inter-layer insulating film LI. The guard region GR that is provided between the control electrode GE1and the control electrode GE2is positioned between the first semiconductor layer11and the planar control portion PG. The third semiconductor layer15is not provided between the guard region GR and the planar control portion PG. As shown inFIG.4B, the planar control portion PG is provided on a region where the third semiconductor layer15and the fourth semiconductor layer17are apart from each other. The planar control portion PG is provided on a portion of the second semiconductor layer13that extends between the third semiconductor layer15and the fourth semiconductor layer17. In the semiconductor device4, a first-conductivity-type inversion layer is also induced between the second semiconductor layer13and the planar control portion PG in addition to between the second semiconductor layer13and the control electrode GE1and between the second semiconductor layer13and the control electrode GE2. The path of the electron current from the third semiconductor layer15to the first semiconductor layer11via the first-conductivity-type inversion layer can be enlarged thereby, and the on-resistance can be reduced. FIG.5is a perspective view schematically showing a semiconductor device5according to a third modification of the embodiment.FIG.5shows the semiconductor part10of the semiconductor device5. The first electrode SE, the second electrode DE, and the control electrodes GE1to GE3, for example, are not illustrated inFIG.5. As shown inFIG.5, the semiconductor part10further includes a seventh semiconductor layer23of the second conductivity type. The seventh semiconductor layer23is partially provided between the first semiconductor layer11and the fourth semiconductor layer17. The seventh semiconductor layer23extends through the second semiconductor layer13and contacts the first and fourth semiconductor layers11and17. The seventh semiconductor layer23includes a second-conductivity-type impurity with a higher concentration than the concentration of the second-conductivity-type impurity of the second semiconductor layer13. By providing the seventh semiconductor layer23, a path of a hole current Ih from the first semiconductor layer11to the fourth semiconductor layer17is formed. The seventh semiconductor layer23serves as a hole ejection path from the first semiconductor layer11to the first electrode SE or the first electrode EE. When the semiconductor device4is turned off, the hole ejection from the first semiconductor layer11can be promoted thereby, and the switching loss can be reduced. The seventh semiconductor layer23is not limited to the example and is applicable also to the other semiconductor devices herein. FIG.6is a perspective view schematically showing a semiconductor device6according to a fourth modification of the embodiment.FIG.6is a schematic view showing the semiconductor part10of the semiconductor device6. The first electrode SE and the second electrode DE, for example, are not illustrated inFIG.6. In the semiconductor device6, the guard region GR is also provided between the control electrode GE2and the control electrode GE3. The guard region GR is partially provided between the first semiconductor layer11and the second semiconductor layer13(referring toFIG.2B). The control electrode GE3is biased, for example, to have the same potential as the first electrode SE or the first electrode EE. As shown inFIG.6, the third semiconductor layer15is not provided between the control electrode GE2and the control electrode GE3. Therefore, the electron current does not flow in the region of the semiconductor part10provided between the control electrode GE2and the control electrode GE3; and this region serves as an ejection path of holes. When the trench gate structure is downscaled, for example, it is difficult to provide the guard region GR only between the control electrode GE1and the control electrode GE2. In such a case, the guard region GR is also provided between the control electrode GE2and the control electrode GE3. The ejection path of the holes between the control electrode GE2and the control electrode GE3is narrowed thereby, but the ejection of the holes can be promoted by providing the seventh semiconductor layer23(referring toFIG.5). It should be noted that configurations that illustrate features of the semiconductor devices are not limited to each example, and are also applicable to other examples when technically feasible. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. | 22,700 |
11862678 | DETAILED DESCRIPTION OF THE EMBODIMENTS FIG.1depicts a camera101imaging a scene. Camera101includes an image sensor190, which includes a pixel-array substrate100. Constituent elements of pixel-array substrate100may include at least one of silicon and germanium. Pixel-array substrate100includes a pixel array192. Image sensor190may part of a chip-scale package or a chip-on-board package. FIG.2andFIG.3illustrates respective cross-sectional views of an image sensor290with pixel-array substrate200, which are examples of image sensor190and pixel-array substrate100, respectively.FIG.2andFIG.3are best viewed together. The location of the cross-section illustrated inFIG.2is equivalent to the section line A-A inFIG.1. The cross section illustrated inFIG.2is parallel to a plane, hereinafter the x-z plane, formed by orthogonal axes298X and298Z, which are each orthogonal to an axis298Y. The cross section illustrated inFIG.3is parallel to a plane, hereinafter the x-y plane, formed by orthogonal axes298X and298Y, and planes parallel to the x-y plane are referred to as horizontal planes. Unless otherwise specified, heights of objects herein refer to the object's extent along axis298Z. Herein, a reference to an axis x, y, or z refers to axes298X,298Y, and298Z respectively. Also, herein, a width refers to an object's extent along the y axis, and vertical refers to a direction along the z axis. Also, herein, above refers to a relative position a distance away along the axis298Z in the positive direction and below refers to a relative position a distance away along the axis298Z in the negative direction The pixel-array substrate200includes electrical isolation including guard ring220, second guard ring224, third guard ring228, trench230, and second trench234to resist a of leakage currents (240(1) and240(2)) across the pixel-array substrate200, according to an embodiment. The image sensor290also includes a pixel array292and an optics layer294. The pixel-array substrate200includes a front surface206, a back surface208, and a periphery region204that surrounds the pixel array292in the horizontal plane. The front surface206is opposite the back surface208and the two are separated by a substrate thickness210. The pixel-array substrate200is formed in a semiconductor substrate202, which may include silicon, silicon-germanium, germanium, gallium arsenide, and combinations thereof. A guard ring220is formed of a doped semiconductor, extends into the semiconductor substrate202from the front surface206, and encloses the pixel array292in the horizontal plane. The guard ring220increases the electrical resistance of a charge carrier (not shown) through the guard ring220. In the embodiment illustrated inFIG.2, the guard ring220resists the flow of electrical current through the guard ring220in the direction along the x axis for the portion of the pixel-array substrate200shown. In general, the guard ring220illustrated inFIG.2resists the flow of electrical current through the guard ring220along directions included in the horizontal plane. By enclosing the pixel array292, guard ring220resists the flow of electrical current between the pixel array292and the periphery region204. Formed into the back surface208of the semiconductor substrate202is a trench230. In some embodiments, the trench230is coated with a high-κ passivation layer (not shown) and filled with an oxide (not shown) that both serve to further resist the flow of electric current across the trench230. The trench230overlaps the guard ring220in the horizontal plane. The trench230limits the flow of electrical current through the semiconductor along directions included in the horizontal plane by removing material of the semiconductor substrate202through which charge carriers could otherwise flow. The trench230extends into the semiconductor substrate202to a trench depth232and the guard ring220extends into the semiconductor substrate to a ring depth222. In the embodiment illustrated inFIG.2, the trench depth232and the ring depth222combined are greater than the substrate thickness210, which causes the trench230and the guard ring220to overlap along the z axis. In the embodiment illustrated inFIG.2, electrical current is resisted across the guard ring220and trench230through the semiconductor along directions included in the horizontal plane at all vertical extents within the semiconductor substrate202, either by the guard ring220, the trench230, or a combination of both. Ring depth222and trench depth232may be increased or decreased and the combined length of the two may also be increased or decreased without departing from the scope hereof. In an embodiment, the guard ring220is formed of a p-doped semiconductor, as is known in the art. In an embodiment, the pixel-array substrate200further includes a second guard ring224that is formed of a doped semiconductor, extends into the semiconductor substrate202from the front surface206, and encloses the guard ring220in the horizontal plane. The second guard ring224increases the electrical resistance of the charge carrier (not shown) through the second guard ring224. In the embodiment illustrated inFIG.2, the second guard ring224resists the flow of electrical current through the second guard ring224in the direction along the x axis for the portion of the pixel-array substrate200shown. Formed into the back surface208of the semiconductor substrate202is a second trench234. In some embodiments, the second trench234is coated with a high-κ passivation layer (not shown) and filled with an oxide (not shown) that both serve to further resist the flow of electric current across the trench230. The second trench234overlaps the second guard ring224in the horizontal plane. The second trench234limits the flow of electrical current through the semiconductor along directions included in the horizontal plane by removing material of the semiconductor substrate202through which charge carriers could otherwise flow. The second trench234extends into the semiconductor substrate202to a second trench depth236and the second guard ring224extends into the semiconductor substrate to a second ring depth226. In the embodiment illustrated inFIG.2, the second trench depth236and the second ring depth226combined are greater than the substrate thickness210, which causes the second trench234and the second guard ring224to overlap along the z axis. In the embodiment illustrated inFIG.2, electrical current is reduced across the second guard ring224and second trench234through the semiconductor along directions included in the horizontal plane at all vertical extents within the semiconductor substrate202, either by the second guard ring224, the second trench234, or a combination of both. The second ring depth226and second trench depth236may be increased or decreased and the combined length of the two may also be increased or decreased without departing from the scope herein. In an embodiment, the second guard ring224is formed of a p-doped semiconductor, as is known in the art. In an embodiment, the pixel-array substrate200further includes a third guard ring228that is formed of a doped semiconductor, extends into the semiconductor substrate202from the front surface206, encloses the guard ring220in the horizontal plane, and excludes the second guard ring224in the horizontal plane. The combination of the guard ring220, the second guard ring224and the third guard ring228effectively prevent the flow of electric current through the semiconductor substrate202. In an embodiment, the third guard ring228is formed by doping the semiconductor substrate202to form a n-doped semiconductor material, as is known in the art. In an embodiment, the third guard ring228is supplied a voltage that further serves to prevent the flow of current across the third guard ring228. FIG.4illustrates one pixel-array substrate400with a back surface408of a semiconductor substrate402that is coated with a high-κ passivation layer436that lines a trench430. The pixel-array substrate400is an example of the pixel-array substrate200including only certain components from the description ofFIG.2. The back surface408, the semiconductor substrate402, and the trench430are examples of the back surface208, semiconductor substrate202and trench230/second trench234ofFIG.2, respectively, and the descriptions of each respective element apply between the two figures. FIG.5illustrates one pixel-array substrate500with a back surface508of a semiconductor substrate502that is coated with a high-κ passivation layer536that lines a trench530and with an oxide538that fills the trench530. Inside the trench530is the oxide538that further resists the flow of electric current (not shown) through the trench530. The pixel-array substrate500is an example of the pixel-array substrate200including only certain components from the description ofFIG.2. The back surface508, semiconductor substrate502, and trench530are examples of the back surface208, the semiconductor substrate202and the trench230/second trench234ofFIG.2, respectively, and the descriptions of each respective element apply between the two figures. FIG.6is a flowchart illustrating a method600for reducing leakage current between a pixel-array and a periphery region of a pixel-array substrate. Method600may be used in conjunction with any of pixel-array substrates200,400, or500. Method600includes blocks610and620. In embodiments, method600also includes at least one of blocks624and626. In block610of method600, a semiconductor substrate is doped to form a guard ring that extends into the semiconductor substrate from a front surface, encloses a pixel array, excludes a periphery region, and resists a flow of electric current. In one example of block610, the semiconductors substrate202is doped to form a guard ring220. In block620of method600, into a back surface of the semiconductor substrate, a trench is formed that penetrates into the back surface and overlaps the guard ring, the back surface opposite the front surface, the guard ring and the trench are configured to resist the flow of electric current between the pixel array and the periphery region. In one example of block620, the trench230is formed into the back surface208of the semiconductor substrate. In one example of block620, the trench430/530is formed into the back surface408/508. FIG.7shows cross-sectional views of semiconductor substrate702, the views illustrating blocks of the method600. Using block610, semiconductor substrate702of pixel-array substrate700is doped to form a guard ring720that extends into the semiconductor substrate702from a front surface706, encloses a pixel array792, and excludes a periphery region704. Using block620, the back surface708of the semiconductor substrate702is etched to form a trench730that penetrates into the back surface708and overlaps the guard ring720in the horizontal plane. The back surface708is opposite the front surface706and the guard ring720combined with the trench730are configured to resist the flow of electric current740between the pixel array792and the periphery region704. In certain embodiments, the method600includes one or more additional blocks of the flowchart inFIG.6. In block614of method600, the semiconductor substrate is doped with a p-type dopant when forming the guard ring. In one example of block614, guard ring220is formed by doping the semiconductor substrate202with a p-type dopant (not shown). FIG.7illustrates one example of block614of method600. In this example, the semiconductor substrate702of a pixel-array substrate700is doped with a p-type dopant to form the guard ring720, as is known in the art. In certain embodiments, the method600includes one or more additional blocks of the flowchart inFIG.6. In block622of method600, the back surface of the semiconductor is etched until the trench extends into the guard ring. In one example of block622, the back surface208of the semiconductor substrate202is etched until the trench230extends into the guard ring220. In one example of block622, the back surface408/508is etched until the trench430/530respectively extends into the guard ring (not shown). FIG.7illustrates one example of block622of method600. In this example, the back surface708is etched until the trench730extends into the guard ring720. In certain embodiments, the method600includes one or more additional blocks of the flowchart inFIG.6that serve to further resist the flow of unwanted electric current though the semiconductor substrate. In block624of method600, the trench is coated with a high-κ passivation layer and in block626, the trench is filled with an oxide. In one example of block624, trench230is coated with a high-κ passivation layer (not shown). In one example of block624, the trench430/530is coated with high-κ passivation layer436/536, respectively. In one example of block626and the trench230is filled with an oxide (not shown). In one example of block626, trench530is filled with an oxide538. FIG.8shows cross-sectional views of semiconductor substrate802, the views illustrating blocks of the method600. The semiconductor substrate802of pixel-array substrate800has a trench830. Block624coats the trench830with a high-κ passivation layer836. Block626fills the trench830with an oxide838. Since the method600may be used in pixel-array substrates described previously, the description of respective components of pixel-array substrates discussed above with respect toFIGS.1-5applies to those elements of method600with like names. Furthermore, method600is not limited, unless otherwise specified or understood by those of ordinary skill in the art, to the order shown inFIG.6. FIG.9is a flowchart illustrating a method900for reducing leakage current across a pixel-array substrate between a first region and a second region. Method900may be used in conjunction with any of pixel-array substrates200,400,500,700or800. Method900includes blocks910and920. In embodiments, method900also includes at least one of blocks924and926. In block910of method900, a semiconductor substrate is doped to form a guard ring that extends into the semiconductor substrate from a front surface, encloses a first region, excludes a second region, and resists a flow of electric current when the first region is supplied with a first voltage and the second region is supplied with a second voltage. In one example of block910, the semiconductor substrate202is doped to form the second guard ring224. In block920of method900, a trench is formed into a back surface of the semiconductor substrate. The trench penetrates into the back surface and overlaps the guard ring. The guard ring and the trench are configured to resist the flow of electric current between the first region and the second region. In one example of block920, the back surface208forms the second trench234. In one example of block920, the back surface408/508forms the trench430/530. In one example of block920, back surface808forms the trench830. FIG.10shows cross-sectional views of semiconductor substrate1002, the views illustrating blocks of the method900. Using block910, the semiconductor substrate1002of pixel-array substrate1000is doped to form a guard ring1024that extends into the semiconductor substrate1002from a front surface1006, encloses a first region1012, and excludes a second region1014. Using block920, the back surface1008of the semiconductor substrate1002is etched to form a trench1034that penetrates into the back surface1008and overlaps the guard ring1024in the horizontal plane. The back surface1008is opposite the front surface1006and the guard ring1024combined with the trench1034are configured to resist the flow of electric current1040between the first region1012and the second region1014. In certain embodiments, the method900includes one or more additional blocks of the flowchart inFIG.9. In block912of method900, the guard ring is formed in a periphery region of the semiconductor substrate that encloses a pixel array. In one example of block912, second guard ring224is formed in the periphery region204of the pixel-array substrate200that encloses the pixel array292in the horizontal plane. FIG.10illustrates one example of block912of method900. In this example, guard ring1024is formed in the periphery region1004of the pixel-array substrate1000that encloses the pixel array1092in the horizontal plane. In certain embodiments, the method900includes one or more additional blocks of the flowchart inFIG.9. In block914of method900, the semiconductor substrate is doped with a p-type dopant when forming the guard ring. In one example of block914, the semiconductor substrate202is doped with a p-type dopant (not shown) to form the second guard ring224. FIG.10illustrates one example of block914of method900. In this example, the semiconductor substrate1002of pixel-array substrate1000is doped with a p-type dopant to form the guard ring1024, as is known in the art. In certain embodiments, the method900includes one or more additional blocks of the flowchart inFIG.9. In block922of method900, the back surface of the semiconductor is etched until the trench extends into the guard ring. In one example of block922, the back surface208of the semiconductor substrate202is etched until the second trench234extends into the second guard ring224. In one example of block922, the back surface408/508is etched until the trench430/530respectively extends into the guard ring (not shown). In one example of block922, the back surface808of semiconductor substrate802is etched until the trench830extends into the guard ring (not shown). FIG.10illustrates one example of block922of method900. In this example, the back surface1008is etched until the trench1034extends into the guard ring1024. In certain embodiments, the method900includes one or more additional blocks of the flowchart inFIG.9that serve to further resist the flow of unwanted electric current though the semiconductor substrate. In block924of method900, the trench is coated with a high-κ passivation layer and in block926, the trench is filled with an oxide. In one example of block924, second trench234is coated with a high-κ passivation layer (not shown). In one example of block924, the trench430/530is coated with high-κ passivation layer436/536, respectively. In one example of block924, trench730is coated with a high-κ passivation layer (not shown). In one example of block924, the trench830is coated with high-κ passivation layer836. In one example of block926and the second trench234is filled with an oxide (not shown). In one example of block926, trench530is filled with an oxide538. In one example of block926and the trench730is filled with an oxide (not shown). In one example of block926, trench830is filled with an oxide838. FIG.11illustrates one example of block924and block926of method900. In this example, the semiconductor substrate1102of pixel-array substrate1100has a trench1130. Block924cotes the trench1130with a high-κ passivation layer1136. Block926fills the trench1130with an oxide1138. Since the method900may be used in pixel-array substrates described previously, the description of respective components of pixel-array substrates discussed above with respect toFIGS.1-8applies to those elements of method900with like names. Furthermore, method900is not limited, unless otherwise specified or understood by those of ordinary skill in the art, to the order shown inFIG.9. Combinations of Features Features described above, as well as those claimed below, may be combined in various ways without departing from the scope hereof. The following enumerated examples illustrate some possible, non-limiting combinations: (A1) In a first aspect, a pixel-array substrate includes: a semiconductor substrate that includes a pixel array, a back surface, and a front surface opposite the back surface; a guard ring formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the front surface; and the back surface forming a trench extending into the semiconductor substrate, the trench overlapping the guard ring. (A2) In an embodiment of A1, the trench extends into the semiconductor substrate to a trench depth, the guard ring extends into the semiconductor substrate to a ring depth, the trench depth plus the ring depth being sufficiently long to exceed a substrate thickness of the semiconductor substrate. (A3) In an embodiment of either one of A1 and A2, the guard ring is formed of a p-doped semiconductor. (A4) An embodiment of any one of A1 through A3 further includes a second guard ring formed of a p-doped semiconductor that encloses the guard ring and extends into the semiconductor substrate from the front surface. (A5) An embodiment of A4 further includes a second trench formed by the back surface that overlaps the second guard ring. (A6) In an embodiment of A5, the second trench extends into the semiconductor substrate to a second trench depth, the second guard ring extends into the semiconductor substrate to a second ring depth, the second trench depth plus the second ring depth is sufficiently long to span the substrate thickness of the semiconductor substrate. (A7) An embodiment of A6 further includes a third guard ring that encloses the guard ring and is enclosed by the second guard ring, the third guard ring extends into the semiconductor substrate from the front surface and is formed of an n-doped semiconductor material. (A8) An embodiment of any one of A6 and A7 further includes a high-κ passivation layer on the back surface that lines the trench and the second trench. (A9) An embodiment of any one of A6 through A8, the trench and the second trench being filled with an oxide. (B1) In a second aspect, a method for reducing leakage current into a pixel-array of a pixel-array substrate including: doping a semiconductor substrate to form a guard ring that extends into the semiconductor substrate from a front surface, encloses a pixel array, excludes a periphery region, and resists a flow of electric current; and forming, into a back surface of the semiconductor substrate, a trench that penetrates into the back surface and overlaps the guard ring, the back surface is opposite to the front surface, the guard ring and the trench are configured to resist the flow of electric current between the pixel array and the periphery region. (B2) In an embodiment of B1, forming the trench includes etching the back surface until the trench extends into the guard ring. (B3) An embodiment of either one of B1 and B2 further includes coating the trench with a high-κ passivation layer. (B4) An embodiment of any one of B1 through B3 further includes filling the trench with an oxide. (B5) In an embodiment of any one of B1 through B4, said doping includes doping the semiconductor substrate with a p-type dopant. (C1) In a third aspect, a method for reducing leakage current across a pixel-array substrate including: doping a semiconductor substrate to form a guard ring that extends into the semiconductor substrate from a front surface, encloses a first region of the semiconductor substrate, excludes a second region of the semiconductor substrate, and resists a flow of electric current when the first region is supplied with a first voltage and the second region is supplied with a second voltage; and forming, into a back surface of the semiconductor substrate, a trench that penetrates into the back surface and overlaps the guard ring, the back surface is the front surface, the guard ring and the trench configured to resist the flow of electric current between the first region and the second region. (C2) In an embodiment of C1, doping includes forming the guard ring in a periphery region of the semiconductor substrate that surrounds a pixel-array. (C3) In an embodiment of either one of C1 and C2, forming the trench includes etching the back surface until the trench extends into the guard ring. (C4) An embodiment of any one of C1 through C3 further includes coating the trench with a high-κ passivation layer. (C5) An embodiment of any of C1 through C4 further includes filling the trench with an oxide. (C6) In an embodiment of any one of C1 through C5, said doping including doping the semiconductor substrate with a p-type dopant. Any feature of the first, second, and third aspects described above are interchangeable with other of the described aspects, unless otherwise specified or understood by those of ordinary skill in the art. Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween. | 25,022 |
11862679 | DETAILED DESCRIPTION FIG.1illustrates a plan view of a semiconductor device according to some example embodiments.FIGS.2A,2B, and2Cillustrate cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′ ofFIG.1. Referring toFIGS.1and2A to2C, a substrate100may be provided to include a memory cell region. For example, the memory cell region of the substrate100may be provided thereon with memory cell transistors that constitute a plurality of SRAM cells. A device isolation layer ST may be provided on the substrate100. The device isolation layer ST may define first and second active patterns AP1and AP2. The substrate100may include a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, silicon-germanium, or the like. The device isolation layer ST may include a dielectric material, such as a silicon oxide layer. The first and second active patterns AP1and AP2may be portions of the substrate100. The first and second active patterns AP1and AP2may extend in parallel along a second direction D2. A first trench TR1may be defined between a pair of neighboring active patterns AP1and AP2. The device isolation layer ST may (e.g., at least partially) fill the first trench TR1. The first and second active patterns AP1and AP2may have their upper portions that vertically protrude beyond the device isolation layer ST. Each of the upper portions of the first and second active patterns AP1and AP2may have a fin shape that vertically protrudes above the device isolation layer ST. First channels CH1and first source/drain patterns SD1may be provided on the upper portion of each of the first active patterns AP1. For example, the first source/drain pattern SD1may fill a recess RS formed on the upper portion of the first active pattern AP1. Second channels CH2and second source/drain patterns SD2may be provided on the upper portion of each of the second active patterns AP2. The first source/drain patterns SD1may be p-type impurity regions. The second source/drain patterns SD2may be n-type impurity regions. Each of the first channels CH1may be between a pair of the first source/drain patterns SD1, and each of the second channels CH2may be between a pair of the second source/drain patterns SD2. The first and second source/drain patterns SD1and SD2may be epitaxial patterns formed by a selective epitaxial growth process. The first and second source/drain patterns SD1and SD2may have their top surfaces at a higher level (e.g., farther from the substrate100) than that of top surfaces of the first and second channels CH1and CH2. The first and second source/drain patterns SD1and SD2may include a semiconductor element that is the same as or different from that of the substrate100. The first source/drain patterns SD1may include a semiconductor element whose lattice constant is greater than that of the semiconductor element of the substrate100. The first source/drain patterns SD1may therefore provide the first channel region CH1with compressive stress. The first source/drain patterns SD1may include, e.g., silicon-germanium (SiGe). The second source/drain patterns SD2may include the same semiconductor element as that of the substrate100. The second source/drain pattern SD2may include, e.g., silicon (Si). Gate electrodes GE may be provided to extend in a first direction D1, while running across the first and second active patterns AP1and AP2. The gate electrodes GE may vertically overlap the first and second channels CH1and CH2. For example, the gate electrodes GE may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). A dielectric pattern IL may be between the gate electrodes GE adjacent to each other in the first direction D1. The dielectric pattern IL may separate adjacent gate electrodes GE from each other. A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D1along the gate electrodes GE. The gate spacers GS may have top surfaces that are higher than those of the gate electrodes GE. The top surfaces of the gate spacers GS may be coplanar with that of a first interlayer dielectric layer110, which will be discussed below. The gate spacers GS may include one or more of SiO2, SiCN, SiCON, and SiN. In an implementation, the gate spacers GS may include a multiple layer that consists of two or more of SiO2, SiCN, SiCON, and SiN. Gate dielectric patterns GI may be between the gate electrode GE and the first active pattern AP1and between the gate electrode GE and the second active pattern AP2. Each of the gate dielectric patterns GI may extend along a bottom surface of one of the gate electrode GE. Each of the gate dielectric patterns GI may cover the top surface and opposite sidewalls of one of the first and second channels CH1and CH2. The gate dielectric patterns GI may include a high-k dielectric material. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. A gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping patterns GP may extend in the first direction D1along the gate electrodes GE. The gate capping pattern GP may be between a pair of the gate spacers GS. The gate capping patterns GP may include a material having an etch selectivity with respect to first, second, third, and fourth interlayer dielectric layers110,120,130, and140, which will be discussed below. For example, the gate capping patterns GP may include one or more of SiON, SiCN, SiCON, and SiN. A first interlayer dielectric layer110may be provided on the substrate100. The first interlayer dielectric layer110may cover the gate spacers GS and the first and second source/drain patterns SD1and SD2. The first interlayer dielectric layer110may have a top surface that is substantially coplanar with those of the gate capping patterns GP and those of the gate spacers GS. The first interlayer dielectric layer110may be provided thereon with a second interlayer dielectric layer120that covers the top surfaces of the gate capping patterns GP and the top surfaces of the gate spacers GS. Active contacts AC may be provided between the gate electrodes GE. The active contacts AC may penetrate the second interlayer dielectric layer120and the first interlayer dielectric layer110, and may then be coupled to the first and second source/drain patterns SD1and SD2. The active contacts AC may have top surfaces coplanar with that of the second interlayer dielectric layer120. Each of the active contacts AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The barrier pattern BM may cover sidewalls and a bottom surface of the conductive pattern FM. The conductive pattern FM may include metal, e.g., one or more of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include one or more of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include one or more of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer. A silicide layer SC may be between each of the first and second source/drain patterns SD1and SD2and the active contact AC corresponding to the each of the first and second source/drain patterns SD1and SD2. The active contact AC may be electrically connected through the silicide layer SC either to the first source/drain pattern SD1or to the second source/drain pattern SD2. The silicide layer SC may include metal silicide, e.g., one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. Gate contacts GC may be provided on the gate electrodes GE. Each of the gate contacts GC may be coupled to the gate electrode GE, while penetrating the second interlayer dielectric layer120, the first interlayer dielectric layer110, and the gate capping pattern GP. The gate contacts GC may have top surfaces coplanar with that of the second interlayer dielectric layer120. The gate contacts GC may have bottom surfaces higher than those of the active contacts AC. Each of the gate contacts GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM and the barrier pattern BM of the gate contact CG may be substantially the same respectively as the conductive pattern FM and the barrier pattern BM of the active contact AC discussed above. For example, the gate contact GC and its connected active contact AC may constitute a single conductive structure. The first source/drain pattern SD1will be further discussed in detail with reference back toFIGS.2A and2B. The first source/drain pattern SD1may include a body part BP and a capping pattern CAP on the body pat BP. The body part BP may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4. The first semiconductor pattern SP1may cover an inner wall of the recess RS. The first semiconductor pattern SP1may have a U shape when viewed in cross-section taken along the second direction D2(seeFIG.2A). For example, the first semiconductor pattern SP1may be conformally formed to have a uniform thickness on the inner wall of the recess RS. The first semiconductor pattern SP1may be provided thereon with the second semiconductor pattern SP2that covers an inner wall of the first semiconductor pattern SP1. The second semiconductor pattern SP2may have a U shape when viewed in cross-section taken along the second direction D2. The second semiconductor pattern SP2may be provided thereon with the third semiconductor pattern SP3that covers an inner wall of the second semiconductor pattern SP2. The second semiconductor pattern SP2may be between the first semiconductor pattern SP1and the third semiconductor pattern SP3. The first, second, and third semiconductor patterns SP1, SP2, and SP3may completely fill the recess RS. Each of the first, second, and third semiconductor patterns SP1, SP2, and SP3may include a semiconductor element whose lattice constant is greater than that of a semiconductor element included in the substrate100. For example, when the substrate100includes silicon (Si), the first, second, and third semiconductor patterns SP1, SP2, and SP3may include silicon-germanium (SiGe). Germanium (Ge) may have a greater lattice constant than that of silicon (Si). The first semiconductor pattern SP1may serve as a buffer layer between the substrate100and the second semiconductor pattern SP2. The first semiconductor pattern SP1may contain germanium (Ge) whose concentration is relatively low. For example, the first semiconductor pattern SP1may contain germanium (Ge) in an amount of about 10 at % to about 30 at %. The second semiconductor pattern SP2may contain germanium (Ge) in an amount that is greater than that of germanium (Ge) contained in the first semiconductor pattern SP1. For example, the second semiconductor pattern SP2may have a germanium (Ge) content of about 25 at % to about 50 at %. The third semiconductor pattern SP3may contain germanium (Ge) in an amount that is greater than that of germanium (Ge) contained in the second semiconductor pattern SP2. For example, the third semiconductor pattern SP3may have a germanium (Ge) content of about 40 at % to about 75 at %. The first, second, and third semiconductor patterns SP1, SP2, and SP3may include impurities (e.g., boron) that cause the first source/drain pattern SD1to have p-type conductivity. The third semiconductor pattern SP3may have an impurity concentration (e.g., at %) that is greater than that of the second semiconductor pattern SP2. The impurity concentration of the second semiconductor pattern SP2may be greater than that of the first semiconductor pattern SP1. The fourth semiconductor pattern SP4may be provided on the third semiconductor pattern SP3. The fourth semiconductor pattern SP4may cover an exposed surface of the third semiconductor pattern SP3. The fourth semiconductor pattern SP4may act as a capping layer that protects the third semiconductor pattern SP3. The fourth semiconductor pattern SP4may include the same semiconductor element as that of the substrate100. For example, the fourth semiconductor pattern SP4may include single crystalline silicon (Si). The fourth semiconductor pattern SP4may include silicon (Si) in an amount of about 95 at % to about 100 at %. The following will discuss a cross-section in the first direction D1of the first source/drain pattern SD1with reference back toFIG.2B. The body part BP may include a first facet FA1, a second facet FA2, a third facet FA3, and a fourth facet FA4. The first to fourth facets FA1to FA4may be surfaces of the fourth semiconductor pattern SP4. The first to fourth facets FA1to FA4may be substantially the same crystal plane. The first to fourth facets FA1to FA4may be (111) planes. A first corner edge SE1may be defined by (e.g., formed at an interface between) the first and second facets FA1and FA2or by the third and fourth facets FA3and FA4. The first corner edge SE1may horizontally protrude in a direction away from a central line CEN of the first active pattern AP1. For example, the first corner edge SE1may protrude in the first direction D1or in a reverse direction to the first direction D1. A second corner edge SE2may be defined by the second and third facets FA2and FA3. The second corner edge SE2may be aligned with the central line CEN of the first active pattern AP1. The second corner edge SE2may vertically protrude along the central line CEN. For example, the second corner edge SE2may protrude in a third direction D3. The capping pattern CAP may be provided on the body part BP. The capping pattern CAP may selectively cover the second and third facets FA2and FA3of the body part BP. The capping pattern CAP may not cover the first and second corner edges SE1and SE2of the body part BP. The capping pattern CAP may expose the first and second corner edges SE1and SE2of the body part BP. The first and fourth facets FA1and FA4of the body part BP may not be covered with the capping pattern CAP, and may be exposed. The capping pattern CAP may have a rounded surface. The capping pattern CAP may have a thickness that increases and then decreases approaching the second corner edge SE2from the first corner edge SE1. The capping pattern CAP may include germanium (Ge) or silicon-germanium (SiGe). The capping pattern CAP may contain germanium (Ge) in an amount that is greater than that of germanium (Ge) in the third semiconductor pattern SP3. The capping pattern CAP may have a germanium (Ge) content of about 5 at % to about 100 at %. In an implementation, the germanium (Ge) content of the capping pattern CAP may be about 95 at % to about 100 at %. The first source/drain pattern SD1may have a maximum width MW in the first direction D1at a level at which the first corner edge SE1of the body part BP is located. The maximum width MW of the first source/drain pattern SD1may be substantially the same as that of the body part BP. This may be because that the capping pattern CAP does not cover the first corner edge SE1but selectively covers the second facet FA2and the third facet FA3. When the active contact AC is provided on the first source/drain pattern SD1, the capping pattern CAP may increase a contact area between the first source/drain pattern SD1and the active contact AC (or the silicide layer SC). This may be because that the body part BP, the capping pattern CAP, and the active contact AC have therebetween a contact area greater than that between the body part BP and the active contact AC. Because the first source/drain pattern SD1maintains its maximum width MW even when the capping pattern CAP is additionally provided on the body part BP, a spacing margin may be securely obtained between the first source/drain patterns SD1adjacent to each other. In such cases, an increase in contact area between the first source/drain pattern SD1and the active contact AC may help improve electrical characteristics of a semiconductor device according to some example embodiments. Furthermore, an electrical short between neighboring first source/drain patterns SD1may be reduced or prevented to enhance reliability of a semiconductor device according to some example embodiments. FIGS.3,5,7,9,11, and13illustrate plan views of stages in a method of manufacturing a semiconductor device according to some example embodiments.FIGS.4,6A,8A,10A,12A, and14Aillustrate cross-sectional views taken along line A-A′ ofFIGS.3,5,7,9,11, and13, respectively.FIGS.6B,8B,10B,12B, and14Billustrate cross-sectional views taken along line B-B′ ofFIGS.5,7,9,11, and13, respectively.FIGS.6C,8C,10C,12C, and14Cillustrate cross-sectional views taken along line C-C′ ofFIGS.5,7,9,11, and13, respectively. Referring toFIGS.3and4, a substrate100may be patterned to form first and second active patterns AP1and AP2. For example, the formation of the first and second active patterns AP1and AP2may include forming mask patterns on the substrate100, and using the mask patterns as an etching mask to anisotropically etch the substrate100. A first trench TR1may be formed between a pair of neighboring active patterns AP1and AP2. A device isolation layer ST may be formed on the substrate100, filling the first trench TR1. For example, a dielectric layer (e.g., a silicon oxide layer) may be formed on the substrate100, covering the first and second active patterns AP1and AP2. The dielectric layer may be recessed until upper portions of the first and second active patterns AP1and AP2are exposed. Referring toFIGS.5and6A to6C, sacrificial patterns PP may be formed to run across the first and second active patterns AP1and AP2. Each of the sacrificial patterns PP may have a linear shape that extends in a first direction D1. For example, the formation of the sacrificial patterns PP may include forming a sacrificial layer on an entire surface of the substrate100, forming mask patterns MA on the sacrificial layer, and using the mask patterns MA as an etching mask to pattern the sacrificial layer. The sacrificial layer may include a polysilicon layer. A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. The gate spacers GS may also be formed on opposite sidewalls of the upper portion of each of the first and second active patterns AP1and AP2. The formation of the gate spacers GS may include conformally forming a spacer layer on the entire surface of the substrate100and anisotropically etching the spacer layer. The spacer layer may include one or more of SiO2, SiCN, SiCON, and SiN. In an implementation, the spacer layer may include a multiple layer that consists of two or more of SiO2, SiCN, SiCON, and SiN. Referring toFIGS.7and8A to8C, recesses RS may be formed on the upper portion of each of the first and second active patterns AP1and AP2. A pair of the recesses RS may be formed on opposite sides of each of the sacrificial patterns PP. The formation of the recesses RS may include performing an etching process in which the mask patterns MA and the gate spacers GS are used as an etching mask to etch the upper portions of the first and second active patterns AP1and AP2. The etching process may remove the gate spacers GS on the opposite sidewalls of the upper portion of each of the first and second active patterns AP1and AP2. An exposed device isolation layer ST may be recessed during the etching process. Referring toFIGS.9and10A to10C, a first hardmask pattern MP may be formed to selectively cover the second active patterns AP2. The first hardmask pattern MP may include an opening OP that exposes the first active patterns AP1. First source/drain patterns SD1may be formed to fill the recesses RS of the first active patterns AP1exposed to the opening OP. For example, the formation of the first source/drain patterns SD1may include performing a selective epitaxial growth process in which exposed inner walls of the recesses RS are used as seed layers. A first channel CH1may be defined between a pair of the first source/drain patterns SD1. For example, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. Each of the first source/drain patterns SD1may include a second semiconductor element whose lattice constant is greater than that of a first semiconductor element included in the substrate100. For example, the first semiconductor element may be silicon, and the second semiconductor element may be germanium. Each of the first source/drain patterns SD1may be formed to have a plurality of semiconductor layers. Each of the first source/drain patterns SD1may include first to fourth semiconductor patterns SP1to SP4and a capping pattern CAP that are sequentially formed. The first to fourth semiconductor patterns SP1to SP4may constitute a body part BP, and the capping pattern CAP may be formed on the body part BP. The first semiconductor pattern SP1may be formed by a first selective epitaxial growth process in which the inner wall of the recess RS of the first active pattern AP1is used as a seed layer. The first semiconductor pattern SP1may contain the second semiconductor element whose concentration is low. The first semiconductor pattern SP1may be doped to include low concentration impurities. For example, the first semiconductor pattern SP1may include silicon-germanium (SiGe) in which boron (B) is doped. The first semiconductor pattern SP1may contain germanium (Ge) in an amount of about 10 at % to about 30 at %. The second semiconductor pattern SP2may be formed by a second selective epitaxial growth process in which the first semiconductor pattern SP1is used as a seed layer. The second semiconductor pattern SP2may contain the second semiconductor element at a concentration that is is greater than that of the second semiconductor element contained in the first semiconductor pattern SP1. The second semiconductor pattern SP2may be doped to include impurities at a concentration that is greater than that of impurities included in the first semiconductor pattern SP1. For example, the second semiconductor pattern SP2may include silicon-germanium (SiGe) in which boron (B) is doped. The second semiconductor pattern SP2may contain germanium (Ge) in an amount of about 25 at % to about 50 at %. The third semiconductor pattern SP3may be formed by a third selective epitaxial growth process in which the second semiconductor pattern SP2is used as a seed layer. The third semiconductor pattern SP3may contain the second semiconductor element at a concentration that is greater than that of the second semiconductor element contained in the second semiconductor pattern SP2. The third semiconductor pattern SP3may be doped to include impurities at a concentration that is greater than that of impurities included in the second semiconductor pattern SP2. For example, the third semiconductor pattern SP3may include silicon-germanium (SiGe) in which boron (B) is doped. The third semiconductor pattern SP3may contain germanium (Ge) in an amount of about 40 at % to about 75 at %. The fourth semiconductor pattern SP4may be formed by a fourth selective epitaxial growth process in which the third semiconductor pattern SP3is used as a seed layer. The fourth semiconductor pattern SP4may conformally cover a surface of the third semiconductor pattern SP3. The fourth semiconductor pattern SP4may contain the first semiconductor element that is the same as that of the substrate100. For example, the fourth semiconductor pattern SP4may include single crystalline silicon (Si). The fourth semiconductor pattern SP4may contain silicon (Si) in an amount of about 95 at % to about 100 at %. The fourth semiconductor pattern SP4may include a first facet FA1, a second facet FA2, a third facet FA3, and a fourth facet FA4. For example, the body part BP may include the first facet FA1, the second facet FA2, the third facet FA3, and the fourth facet FA4. The first and second facets FA1and FA2or the third and fourth facets FA3and FA4may define a first corner edge SE1that horizontally protrudes. The second and third facets FA2and FA3may define a second corner edge SE2that vertically protrudes. The capping pattern CAP may be selectively formed on the second and third facets FA2and FA3of the body part BP. The capping pattern CAP may not be formed on the first and fourth facets FA1and FA4of the body part BP. The capping pattern CAP may not cover the first corner edge SE1. The capping pattern CAP may be formed by a fifth selective epitaxial growth process in which the fourth semiconductor pattern SP4is used as a seed layer. For example, the capping pattern CAP may include germanium (Ge) or silicon-germanium (SiGe). The capping pattern CAP may contain germanium (Ge) in an amount of about 5 at % to about 100 at %. In an implementation, the capping pattern CAP may have a germanium (Ge) content of about 95 at % to about 100 at %. The fifth selective epitaxial growth process may be performed at a temperature similar to or less than those of the first to fourth selective epitaxial growth processes. The fifth epitaxial growth process may use a process gas including an etching gas that contains HCl, Cl2, or a combination thereof. When the fifth selective epitaxial growth process is adjusted on its process conditions (e.g., temperature, pressure, and etching gas amount), it may be possible to control selective growth of the capping pattern CAP only on the second facet FA2and the third facet FA3. Referring toFIGS.11and12A to12C, the first hardmask pattern MP may be removed, and a second hardmask pattern may be formed to selectively cover the first active patterns AP1. Second source/drain patterns SD2may be formed to fill the recesses RS of the second active patterns AP2exposed to the second hardmask pattern. For example, the formation of the second source/drain patterns SD2may include performing a selective epitaxial growth process in which exposed inner walls of the recesses RS are used as seed layers. The second source/drain patterns SD2may include the same first semiconductor element, such as silicon, as that of the substrate100. Afterwards, the second hardmask pattern may be removed. A first interlayer dielectric layer110may be formed to cover the first and second source/drain patterns SD1and SD2, the gate spacers GS, and the mask patterns MA. For example, the first interlayer dielectric layer110may include a silicon oxide layer. The first interlayer dielectric layer110may be planarized until top surfaces of the sacrificial patterns PP are exposed. An etch-back or chemical mechanical polishing (CMP) process may be performed to planarize the first interlayer dielectric layer110. As a result, the first interlayer dielectric layer110may have a top surface substantially coplanar with those of the sacrificial patterns PP and those of the gate spacers GS. The sacrificial patterns PP may be replaced with gate electrodes GE and a dielectric pattern IL. For example, an anisotropic etching process may be performed on the exposed sacrificial patterns PP. The anisotropic etching process may selectively etch the sacrificial patterns PP. The dielectric pattern IL may be formed in empty spaces where the sacrificial patterns PP are removed. Gate dielectric patterns GI and the gate electrodes GE may be formed in remaining empty spaces where the dielectric pattern IL is not formed. The gate dielectric patterns GI may be conformally formed by an atomic layer deposition (ALD) process or a chemical oxidation process. For example, the gate dielectric pattern GI may include a high-k dielectric material. The formation of the gate electrodes GE may include forming a gate electrode layer on the gate dielectric patterns GI and performing a planarization process on the gate electrode layer. For example, the gate electrode layer may include one or more of metal and conductive metal nitride. The gate electrodes GE may be recessed by selectively etching upper portions thereof. The recessed gate electrodes GE may have their top surfaces lower than that of the first interlayer dielectric layer110and those of the gate spacers GS. Gate capping patterns GP may be formed on the recessed gate electrodes GE. The formation of the gate capping patterns GP may include forming a gate capping layer to cover the recessed gate electrodes GE and performing a planarization process on the gate capping layer until the top surface of the first interlayer dielectric layer110is exposed. For example, the gate capping layer may include one or more of SiON, SiCN, SiCON, and SiN. Referring toFIGS.13and14A to14C, a second interlayer dielectric layer120may be formed on the first interlayer dielectric layer110, covering the gate capping patterns GP. First contact holes CNH1may be formed to penetrate the second interlayer dielectric layer120and the first interlayer dielectric layer110, exposing the first and second source/drain patterns SD1and SD2. Second contact holes CNH2may be formed to penetrate the second interlayer dielectric layer120, the first interlayer dielectric layer110, and the gate capping patterns GP, exposing the gate electrodes GE. When an etching process is performed to form the first contact holes CNH1, the etching process may etch upper portions of the first and second source/drain patterns SD1and SD2. Silicide layers SC may be formed by performing a silicidation process on the first and second source/drain patterns SD1and SD2exposed to the first contact holes CNH1. For example, the silicide layers SC may include one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. Referring back toFIGS.1and2A to2C, active contacts AC may be formed in the first contact holes CNH1, contacting the first and second source/drain patterns SD1and SD2. Gate contacts GC may be formed in the second contact holes CNH2, contacting the gate electrodes GE. The formation of the active contacts AC and the gate contacts GC may include forming a barrier pattern BM to partially fill each of the first and second contact holes CNH1and CNH2, and forming a conductive pattern FM on the barrier pattern BM. FIGS.15,16, and17illustrate cross-sectional views taken along line D-D′ ofFIG.1, showing a semiconductor device according to some example embodiments. In the embodiment that follows, a repeated detailed description of technical features relative to those of the semiconductor device discussed above with reference toFIGS.1and2A to2Cmay be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.1,2A,2C, and15, the silicide layer SC may have a surface that conforms to a surface profile of the first source/drain pattern SD1or the second source/drain pattern SD2beneath the silicide layer SC. For example, a shape of the first source/drain pattern SD1and its overlying silicide layer SC may be similar to that of the first source/drain pattern SD1having no silicide layer SC thereon. The silicide layer SC on the first source/drain pattern SD1may have a top end at a level substantially the same as that of a top end (e.g., the second corner edge SE2) of the first source/drain pattern SD1having no silicide layer SC thereon. Referring back toFIGS.13and14A to14C, the formation of the silicide layer SC and the active contact AC may include forming the first contact holes CNH1by performing a selective etching process that selectively etches the first and second interlayer dielectric layers110and120except for the first and second source/drain patterns SD1and SD2. The first and second source/drain patterns SD1and SD2may be exposed by the selective etching process, but may maintain their shapes even after the first contact holes CNH1are formed. When a silicidation process is performed on the exposed first and second source/drain patterns SD1and SD2, the exposed first and second source/drain patterns SD1and SD2may be converted into the silicide layers SC. Referring toFIGS.1,2A,2C, and16, the capping pattern CAP may include a first segment P1and a second segment P2. The first segment P1may cover the second and third facets FA2and FA3of the body part BP, and the second segment P2may cover the first and fourth facets FA1and FA4of the body part BP. The first and second segments P1and P2may not cover the first and second corner edges SE1and SE2of the body part BP. The second segment P2may have a maximum thickness less than that of the first segment P1. Referring toFIGS.1,2A,2C, and17, the capping pattern CAP may not cover the first corner edge SE1of the body part BP, and may cover the second corner edge SE2of the body part BP. For example, the capping pattern CAP may have a top end at a higher level than that of the second corner edge SE2. FIG.18illustrates a plan view showing a semiconductor device according to some example embodiments.FIGS.19A,19B, and19Cillustrate cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′ ofFIG.16. In the embodiment that follows, a repeated detailed description of technical features relative to those discussed above with reference toFIGS.1and2A to2Cmay be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.18and19A to19C, at least one logic cell may be provided on a substrate100. The logic cell may include logic transistors that constitute a logic circuit of a semiconductor device. For example, the logic cell of the substrate100may include logic transistors constituting a processor core or an I/O terminal. The substrate100may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2formed on an upper portion of the substrate100. For example, the second trench TR2may be formed between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart in a first direction D1from each other across the second trench TR2. The PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2intersecting the first direction D1. The PMOSFET region PR and the NMOSFET region NR may be provided thereon with a plurality of active patterns AP1and AP2that extend in the second direction D2. The active patterns AP1and AP2may include first active patterns AP1on the PMOSFET region PR and second active patterns AP2on the NMOSFET region NR. The first and second active patterns AP1and AP2may be vertically protruding portions of the substrate100. A first trench TR1may be defined between neighboring first active patterns AP1and between neighboring second active patterns AP2. The second trench TR2may be deeper than the first trench TR1. A device isolation layer ST may fill the first and second trenches TR1and TR2. The first and second active patterns AP1and AP2may have their upper portions that vertically protrude beyond the device isolation layer ST. First channels CH1and first source/drain patterns SD1may be provided on the upper portions of the first active patterns AP1. Second channels CH2and second source/drain patterns SD2may be provided on the upper portions of the second active patterns AP2. The first source/drain patterns SD1may be p-type impurity regions. The second source/drain patterns SD2may be n-type impurity regions. The first and second source/drain patterns SD1and SD2may be epitaxial patterns formed by a selective epitaxial growth process. Gate electrodes GE may be provided to extend in the second direction D2, while running across the first and second active patterns AP1and AP2. The gate electrodes GE may be spaced apart from each other in the first direction D1. For example, the gate electrodes GE may include one or more of metal and conductive metal nitride. A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. Gate dielectric patterns GI may be between the gate electrode GE and the first active pattern AP1and between the gate electrode GE and the second active pattern AP2. A gate capping pattern GP may be provided on each of the gate electrodes GE. A first interlayer dielectric layer110may be provided on the substrate100. The first interlayer dielectric layer110may cover the gate spacers GS and the first and second source/drain patterns SD1and SD2. The first interlayer dielectric layer110may be provided thereon with a second interlayer dielectric layer120that covers top surfaces of the gate capping patterns GP and top surfaces of the gate spacers GS. Active contacts AC may be provided between the gate electrodes GE. The active contacts AC may penetrate the second interlayer dielectric layer120and the first interlayer dielectric layer110, and may be coupled to the first and second source/drain patterns SD1and SD2. The first source/drain pattern SD1may be provided on three first active patterns AP1adjacent to each other in the first direction D1. For example, the first source/drain patterns SD1on adjacent first active patterns AP1may be merged with other to constitute a single source/drain pattern. The first source/drain pattern SD1may include a body part BP and a capping pattern CAP on the body pat BP. The body part BP may include first to fourth semiconductor patterns SP1to SP4, and may further include a fifth semiconductor pattern SP5. The fifth semiconductor pattern SP5may be provided on the third semiconductor pattern SP3. The fifth semiconductor pattern SP5may be between the third semiconductor pattern SP3and a silicide layer SC. The third semiconductor pattern SP3may include valleys VAL. The third semiconductor pattern SP3may have a top surface a portion of which is recessed toward the substrate100, and the valley VAL may be the recessed portion of the top surface of the third semiconductor pattern SP3. For example, the valley VAL may be a recess formed on the top surface of the third semiconductor pattern SP3. The valley VAL may be on a space between a pair of neighboring first active patterns AP1. The fifth semiconductor pattern SP5may fill the valley VAL of the third semiconductor pattern SP3. The valley VAL may be defined by connecting adjacent (111) planes of the top surface of the third semiconductor pattern SP3(see TS1and TS2ofFIG.25B). The fifth semiconductor pattern SP5may selectively cover the (111) planes that define the valley VAL of the third semiconductor pattern SP3. The fourth semiconductor pattern SP4may cover other planes of the third semiconductor pattern SP3, which other planes are not covered with the fifth semiconductor pattern SP5. The fifth semiconductor pattern SP5may include silicon-germanium (SiGe). The fifth semiconductor pattern SP5may contain germanium (Ge) in an amount that is is greater than that of germanium (Ge) in the second semiconductor pattern SP2. The fifth semiconductor pattern SP5may have a germanium (Ge) content equal to or less than that of the third semiconductor pattern SP3. For example, the germanium (Ge) content of the fifth semiconductor pattern SP5may be about 40 at % to about 75 at %. The body part BP of the first source/drain pattern SD1may include a first facet FA1and a second facet FA2. The first facet FA1and the second facet FA2may face an adjacent second source/drain pattern SD2. The first facet FA1and the second facet FA2may be (111) planes. The first facet FA1and the second facet FA2may define a first corner edge SE1. The first corner edge SE1may horizontally protrude toward the adjacent second source/drain pattern SD2. The capping pattern CAP may be provided on the body part BP. For example, the capping pattern CAP may not cover the first facet FA1and may selectively cover the second facet FA2. The capping pattern CAP may not cover, but expose the first corner edge SE1. The first source/drain pattern SD1may have a maximum width MW in the first direction D1at a level at which the first corner edge SE1is located. The maximum width MW of the first source/drain pattern SD1may be substantially the same as that of the body part BP. This may be because that the capping pattern CAP does not cover the first corner edge SE1and selectively covers the second facet FA2. The silicide layer SC may be between the first source/drain pattern SD1and the active contact AC. The silicide layer SC may cover the third, fourth, and fifth semiconductor patterns SP3, SP4, and SP5. The silicide layer SC may cover the capping pattern CAP. The capping pattern CAP may help increase a contact area between the first source/drain pattern SD1and the active contact AC (or the silicide layer SC). FIGS.20,22,24,26, and28illustrate plan views of a method of manufacturing a semiconductor device according to some example embodiments.FIGS.21,23A,25A,27A, and29Aillustrate cross-sectional views taken along line A-A′ ofFIGS.20,22,24,26, and28, respectively.FIGS.23B,25B,27B, and29Billustrate cross-sectional views taken along line B-B′ ofFIGS.22,24,26, and28, respectively.FIGS.23C,25C,27C, and29C illustrate cross-sectional views taken along line C-C′ ofFIGS.22,24,26, and28, respectively. In the embodiment that follows, a repeated detailed description of technical features relative to those discussed with reference toFIGS.1to14may be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.20and21, a substrate100may be patterned to form active patterns AP1and AP2. The active patterns AP1and AP2may be formed to have at a regular interval (or pitch). A first trench TR1may be formed between a pair of neighboring active patterns AP1and AP2. The first trenches TR1may have substantially the same depth. The substrate100may be patterned to form a second trench TR2that defines a PMOSFET region PR and a NMOSFET region NR. The second trench TR2may be formed deeper than the first trench TR1. One or more of the active patterns AP1and AP2may be removed when the substrate100is patterned, and thus first active patterns AP1may remain on the PMOSFET region PR and second active patterns AP2may remain on the NMOSFET region NR. A device isolation layer ST may be formed to fill the first and second trenches TR1and TR2. The formation of the device isolation layer ST may include forming on the substrate100a dielectric layer (e.g., a silicon oxide layer) to cover the first and second active patterns AP1and AP2, and recessing the dielectric layer until upper portions of the first and second active patterns AP1and AP2are exposed. Referring toFIGS.22and23A to23C, sacrificial patterns PP may be formed to run across the first and second active patterns AP1and AP2. A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. The gate spacers GS may also be formed on opposite sidewalls of the upper portion of each of the first and second active patterns AP1and AP2. Referring toFIGS.24and25A to25C, recesses RS may be formed on the upper portion of each of the first and second active patterns AP1and AP2. A first hardmask pattern MP may be formed to selectively cover the second active patterns AP2. The first hardmask pattern MP may expose the first active patterns AP1. First source/drain patterns SD1may be formed to fill the recesses RS of the exposed first active patterns AP1. For example, a first semiconductor pattern SP1may be formed in each of the recesses RS. A second semiconductor pattern SP2may be formed on each of the first semiconductor patterns SP1. A third semiconductor pattern SP3may be formed on the second semiconductor patterns SP2adjacent to each other in a second direction D2. The formation of the third semiconductor pattern SP3may include growing epitaxial patterns using the second semiconductor patterns SP2as seed layers, and then merging the epitaxial patterns into a single piece. A fourth semiconductor pattern SP4may be formed on the third semiconductor pattern SP3. Except for that mentioned above, the formation of the first to fourth semiconductor patterns SP1to SP4may be substantially the same as that discussed above with reference toFIGS.9and10A to10C. In an implementation, the formation of the first source/drain pattern SD1may further include forming a fifth semiconductor pattern SP5on the third semiconductor pattern SP3before forming the fourth semiconductor pattern SP4. The first to fifth semiconductor patterns SP1to SP5may constitute a body part BP of the first source/drain pattern SD1. The third semiconductor pattern SP3may be formed to include valleys VAL. For example, the third semiconductor pattern SP3may have a top surface including a first surface TS1and a second surface TS2adjacent to each other. Each of the first and second surfaces TS1and TS2may be a (111) plane. The first surface TS1and the second surface TS2may define the valley VAL on the top surface of the third semiconductor pattern SP3. The fifth semiconductor pattern SP5may be formed by a selective epitaxial growth process in which the first and second surfaces TS1and TS2constituting the valley VAL are used as a seed layer. The fifth semiconductor pattern SP5may be formed to fill the valley VAL, and may not be formed on different surfaces other than the first and second surfaces TS1and TS2of the third semiconductor pattern SP3. When the selective epitaxial growth process is adjusted on its process conditions (e.g., temperature, pressure, and etching gas amount), it may be possible to control selective growth of the fifth semiconductor pattern SP5only on the first surface TS1and the second surface TS2. The body part BP may be formed to have a first facet FA1and a second facet FA2. The first facet FA1and the second facet FA2may define a first corner edge SE1. A capping pattern CAP may be selectively formed on the second facet FA2of the body part BP. The capping pattern CAP may not be formed on the first facet FA1of the body part BP. The capping pattern CAP may not cover the first corner edge SE1. Referring toFIGS.26and27A to27C, second source/drain patterns SD2may be formed to fill the recesses RS of the second active patterns AP2. A first interlayer dielectric layer110may be formed on the substrate100. Each of the sacrificial patterns PP may be replaced with a gate dielectric pattern GI, a gate electrode GE, and a gate capping pattern GP. Referring toFIGS.28and29A to29C, a second interlayer dielectric layer120may be formed on the first interlayer dielectric layer110. Contact holes CNH may be formed to penetrate the second interlayer dielectric layer120and the first interlayer dielectric layer110, exposing the first and second source/drain patterns SD1and SD2. Silicide layers SC may be formed by performing a silicidation process on the first and second source/drain patterns SD1and SD2exposed to the contact holes CNH. Referring back toFIGS.18and19A to19C, active contacts AC may be formed in the contact holes CNH, contacting the first and second source/drain patterns SD1and SD2. By way of summation and review, semiconductor devices may have high integration with the advanced development of electronic industry. For example, semiconductor devices with high reliability, high speed, and/or multi-functionality may be desirable. Semiconductor devices may be gradually complicated and integrated to meet these characteristics. According to an embodiment, a semiconductor device may be configured such that a contact area between a source/drain pattern and an active contact (or a silicide layer) is increased while the source/drain pattern maintains its maximum width. A resistance between the source/drain pattern and the active contact may be reduced to help improve electrical characteristics of the semiconductor device. According to an embodiment, this may be realized by providing a capping layer. One or more embodiments may provide a semiconductor device having increased integrated and reliability. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 49,420 |
11862680 | DETAILED DESCRIPTION Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics. An electrostatic discharge (ESD) protection structure of this disclosure may be incorporated into various electronic devices for releasing static electricity that is generated during manufacturing thereof. In this disclosure, the ESD protection structure is applied to a nitride-based device, such as high electron mobility transistor (HEMT), but is not limited thereto. Embodiment 1 Referring toFIGS.1to3, a first embodiment of the nitride-based device having the ESD protection structure is illustrated. The nitride-based device includes an epitaxial structure, an isolation trench (C), a first p-type nitride layer61, a source electrode (S), a drain electrode (D), a gate electrode (G), a field plate1, and a metal layer7. The epitaxial structure includes a substrate2, and an epitaxial layer having a buffer layer3, a channel layer4, and a barrier layer5that are disposed on the substrate2in such order. The isolation trench (C) is formed in the epitaxial structure, so as to divide the epitaxial structure into an active region (A) and an ESD protection region (B) outside the active region (A). The source electrode (S), the drain electrode (D) and the gate electrode (G) are disposed on the active region (A) of the epitaxial structure and spaced apart from each other. The field plate1is disposed on the active region (A) of the epitaxial structure and spaced apart from the source electrode (S), the drain electrode (D) and the gate electrode (G). The ESD protection structure includes the channel layer4of the ESD protection region (B), and the barrier layer5of the ESD protection region (B), the first p-type nitride layer61and the metal layer7formed on the channel layer4of the ESD protection region (B) of the epitaxial structure in such order. The metal layer7of the ESD protection structure is electrically connected to the field plate1. A p-n junction is formed when the first p-type nitride layer61is in contact with the barrier layer5. In this embodiment, the nitride-based device further includes a dielectric layer8that is interposed between the field plate1and the active region (A) of the epitaxial structure exposed from the source electrode (S), the drain electrode (D) and the gate electrode (G). Preferably, the nitride-based device further includes a second p-type nitride layer62that is interposed between the active region (A) of the epitaxial structure and the gate electrode (G). The dielectric layer8is interposed between the field plate1and the active region (A) of the epitaxial structure exposed from the source electrode (S), the drain electrode (D), the gate electrode (G) and the second p-type nitride layer62. The dielectric layer8has openings aligned with the first p-type nitride layer61and the second p-type nitride layer62for deposition of the metal layer7and the gate electrode (G), respectively. In the nitride-based device, such as a HEMT, the substrate2may be made of one of silicon, silicon carbide, and gallium, nitride (GaN), but is not limited thereto. The buffer layer3may be made of GaN, but is not limited thereto. The channel layer4may be made of one of GaN, indium nitride (InN), and indium gallium nitride (InGaN), but is not limited thereto. The barrier layer5may be made of one of aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium aluminum nitride (InAlN), aluminum scandium nitride (AlScN), and indium aluminum gallium nitride (InAlGaN), but is not limited thereto. In this embodiment, the substrate2is made of silicon, the buffer layer3is made of GaN, the channel layer4is made of GaN, and the barrier layer5is made of AlGaN. The first p-type nitride layer61and the second p-type nitride layer62are made from the same p-type nitride layer that is made of p-type group III nitride, such as p-type GaN, p-type AlGaN and p-type InAlGaN. Preferably, both the first and second p-type nitride layers61,62have a p-type doping concentration ranging from 1017cm−3to 1021cm−3. In this embodiment, the metal layer7and the field plate1are made from the same metallic material layer that is made of a material selected from the group consisting of nickel, palladium, gold, titanium, aluminum, tungsten, and alloys and compounds thereof. In the case that the metal layer7is made of a material selected from the group consisting of nickel, palladium, gold, and alloys and compounds thereof, an ohmic contact is formed at an interface between the metal layer7and the first p-type nitride layer61. In the case that the metal layer7is made of a material selected from the group consisting of titanium, aluminum, tungsten, and alloys and compounds thereof, a Schottky contact is formed at the interface between the metal layer7and the first p-type nitride layer61. In the conventional nitride-based device, lots of electric charges are accumulated on field plates and could not be released. That is because each of the field plates is disposed on a dielectric layer that is insulated, i.e., in a floating state, so that the electric charges could not be released through the dielectric layer, and thus might lead to ESD. In contrast, in the nitride-based device having the ESD protection structure of this disclosure, two-dimensional electron gas (2DEG) is generated at the channel layer4when a heterojunction is formed at an interface of the channel layer4(i.e., the GaN layer) and the barrier layer5(i.e., the AlGaN layer), where self-polarization or piezoelectric polarization occurs. Further, the p-n junction is formed at an interface of the barrier layer5and the first p-type nitride layer61. When electric charges generated during manufacturing of the nitride-based device accumulates on the field plate1to an extent that the field plate1has a voltage relative to ground (i.e., the substrate2) higher than 3.4 V, the p-n junction is forward-biased and allows the electric charges to flow from the first p-type nitride layer61to the substrate2. As a result, charge release and effective reduction of risks of damage by ESD during manufacturing of the nitride-based device can be achieved. FIG.1is a top view illustrating a positional relationship of the source electrode (S), the drain electrode (S), the gate electrode (G) and the field plate1. The dielectric layer8and other interconnect structures, etc., are omitted. It is noted that the source electrode (S), the drain electrode (D), the gate electrode (G) and the field plate1may be located at different altitude and are disjoint spatially, as is known to those skilled in the art of semiconductor fabrication. In this embodiment, the field plate1is classified as a source-field plate, which is positioned between the drain electrode (D) and the gate electrode (G) so as to effectively reduce a strength of an electric field near the drain electrode (D). In this embodiment, the nitride-based device includes a plurality of the field plates1spaced apart from each other. The metal layer7and the first p-type nitride layer61of the electrostatic discharge protection structure are respectively formed into spaced-apart islands. Each of the islands of the metal layer7is disposed on a corresponding one of the islands of the first p-type nitride layer61. Each of the field plates1is electrically connected to a corresponding one of the islands of the metal layer7. Referring toFIGS.4A to4GandFIGS.5A to5G, a method for manufacturing the first embodiment of the nitride-based device is illustrated based on two cross-sectional views taken along line a-a′ ofFIG.1and line b-b′ inFIG.1that is perpendicular to line a-a′. The method includes consecutive steps from steps S1to S9. In step S1, the epitaxial structure including the substrate2and the epitaxial layer having the buffer layer3, the channel layer4, the barrier layer5, and a p-type nitride unit6that are disposed on the substrate2in such order is provided, as shown inFIGS.4A and5A. The epitaxial layer is made of nitride-based materials suitable for forming a HEMT. In this embodiment, the buffer layer3is made of GaN and the channel layer4is made of GaN. The barrier layer5has a chemical formula of Alx1Ga(1-x1)N, where x1 may range from 0.01 to 1, and a thickness that may range from 1 nm to 50 nm. The p-type nitride unit6may has a thickness ranging from 50 nm to 300 nm, and a p-type doping concentration ranging from 1017cm−3to 1021cm−3. Moreover, the epitaxial structure has the ESD protection region (B), a source region, a drain region, and a gate region. In step S2, the p-type nitride unit6is etched during a photolithography process to form the first p-type nitride layer61on the electrostatic discharge protection region (B) of the epitaxial structure and the second p-type nitride layer62on the gate region (G) of the epitaxial structure, as shown inFIGS.4B and5B. The first p-type nitride layer61is formed into spaced-apart islands. Examples of the etching technique include inductively coupled plasma (ICP) etching and reactive-ion etching (RIE). In step S3, the source electrode (S) and the drain electrode (D) are formed on the source region and the drain region, respectively, as shown inFIGS.4C and5C. To be specific, the source electrode (S) and the drain electrode (D) are formed by depositing a material, which may be selected from the group consisting of titanium, aluminum, nickel, gold, tantalum, and alloys and compounds thereof, on the source region and the drain region using one of evaporative physical vapor deposition (PVD) and sputtering PVD. Then, the deposited material is patterned using photolithography process to form the source electrode (S) and the drain electrode (D). In step S4, the isolation trench (C) is formed in the epitaxial structure to isolate the active region (A) including the source, drain, and gate regions from the ESD protection region (B), as shown inFIGS.4Dand5D. The isolation trench (C) may be formed by ion implantation to be a region with high resistance. The isolation trench (C) may also be formed by photolithography and then filling an insulation material therein. In step S5, the dielectric layer8is disposed to cover the active region (A), the source electrode (S), the drain electrode (D), and the ESD protection region (B), as shown inFIGS.4E and5E. In step S6, the dielectric layer8in the ESD protection region (B) is partially removed to form an opening so as to expose the first p-type nitride layer61. In step S7, a first metallic material is deposited on the dielectric layer8in the active region (A) to form the field plates1spaced apart from each other using photolithography, and is also deposited on the first p-type nitride layer61in the ESD protection region (B) to form the metal layer7. The metal layer7thus formed is in contact with the first p-type nitride layer61through the opening of the dielectric layer8. The metal layer7is formed into the spaced-apart islands using photolithography, and each of the islands of the metal layer7is electrically connected to a corresponding one of the field plates1. Deposition of the first metallic material is performed using one of evaporative PVD and sputtering PVD, as shown in FIGS.4F and5F. The first metallic material may be selected from the group consisting of nickel, palladium, gold, titanium, aluminum, tungsten, and alloys and compounds thereof. In step S8, the dielectric layer8is formed with an opening that is aligned with the second p-type nitride layer62in the gate region. In step S9, a second metallic material is filled into the opening in the gate region to form the gate electrode (G) on the second p-type nitride layer62using one of evaporative PVD and sputtering PVD, as shown inFIGS.4G and5G. Examples of the second metallic material may include nickel, palladium, gold, titanium, aluminum, tungsten, and alloys and compounds thereof. The gate electrode (G) is in contact with the second p-type nitride layer62through the opening in the gate region. Next, conventional processes for manufacturing the nitride-based device are subsequently performed, such as formation of metal interconnect layers in a back-end-of-the-line section and formation of electrical connections between the metal interconnect layers and the source, drain, and gate electrodes (S, D, G) in a middle-of-the-line section for manufacturing the nitride-based device. Since such processes are not the essential features of the disclosure, detailed description thereof is omitted herein. Referring toFIGS.6to8, in a variant of this embodiment, the metal layer7of the electrostatic discharge protection structure is likewise disposed on the first p-type nitride layer61. The first p-type nitride layer61and the metal layer7are plate-shaped. The field plates1are electrically connected to the metal layer7of the electrostatic discharge protection structure. That is to say, the metal layer7has a length larger than a pitch of the field plates1, so that the field plates1are able to be electrically connected to the same metal layer7of the electrostatic discharge protection structure, as shown inFIGS.6to8. The method for manufacturing the variant of the nitride-based device is similar to the abovementioned method for manufacturing the first embodiment, except that each of the first p-type nitride layer61and the metal layer7is formed into a plate, and the plate of the metal layer7is electrically connected to the field plates1. Embodiment 2 Referring toFIGS.9to11, a second embodiment of the nitride-based device has a structure similar to that of the first embodiment. However, the second p-type nitride layer62is omitted so that the gate electrode (G) is in contact with the barrier layer5. In this embodiment, the nitride-based device includes the dielectric layer8interposed between the field plate1and the active region (A) of the epitaxial structure exposed from the source electrode (S), the drain electrode (D), and the gate electrode (G). Referring toFIGS.12A to12GandFIGS.13A to13G, a method for manufacturing the second embodiment of the nitride-based device is illustrated based on two cross-sectional schematic views taken along line a-a′ ofFIG.9and line b-b′ ofFIG.9that is perpendicular to line a-a′. The method for manufacturing the second embodiment of the nitride-based device having the ESD protection structure includes consecutive steps S1to S9. In step S1, the epitaxial structure including the substrate2, and the epitaxial layer that has the buffer layer3, the channel layer4, and the barrier layer5disposed on the substrate2in such order is provided, as shown inFIGS.12A and13A. The epitaxial layer is made of nitride-based materials suitable for forming the HEMT. In this embodiment, the buffer layer3is made of GaN, the channel layer4is made of GaN, and the barrier layer5is made of AlGaN. The epitaxial structure has the ESD protection region (B), the source region and the drain region. In step S2, the first p-type nitride layer61is formed on the ESD protection region (B) of the epitaxial structure through selective-area secondary epitaxial growth, as shown inFIGS.12B and13B. To be specific, a mask layer that is made of a material such as silicon nitride or silicon dioxide is formed on the epitaxial layer. The epitaxial structure of the ESD protection region (B) is then exposed from the mask layer by photolithography based on a predetermined shape of the first p-type nitride layer61. Subsequently, the first p-type nitride layer61is formed on the barrier layer5(i.e., AlGaN layer) of the ESD protection region (B) through selective-area secondary epitaxial growth, and is formed into spaced-apart islands. Finally, the mask layer is removed by one of wet etching and dry etching, such as ICP etching or RIE. The first p-type nitride layer61has a thickness ranging from 50 nm to 300 nm, and a p-type doping concentration ranging from 1017cm−3to 1021cm−3. An example of p-type dopant in the first p-type nitride layer61includes magnesium (Mg). In step S3, the source electrode (S) and the drain electrode (D) are formed on the source region and the drain region, respectively, as shown inFIGS.12C and13C. Details regarding the formation of the source electrode (S) and the drain electrode (D) are similar to those described above with reference toFIGS.4C and5C. In step S4, the isolation trench (C) is formed in the epitaxial structure to isolate the active region (A) including the source and drain regions from the ESD protection region (B), as shown inFIGS.12D and13D. Details regarding the formation of the isolation trench (C) are similar to those described above with reference toFIGS.4D and5D. In step S5, the dielectric layer8is disposed to cover the active region (A), the source electrode (S), the drain electrode (D), and the ESD protection region (B), as shown inFIGS.12E and13E. In step S6, the dielectric layer8is removed from the ESD protection region (B) to expose the first p-type nitride layer61. In step S7, the first metallic material is deposited on the dielectric layer8in the active region (A) to form the field plates1spaced apart from each other, and on the first p-type nitride layer61in the ESD protection region (B) to form the metal layer7into the spaced-apart islands, such that the spaced-apart islands of the metal layer7can be respectively and electrically connected to the field plates1, as shown inFIGS.12F and13F. Details regarding the formation of the field plate1and the metal layer7are similar to those described above with reference toFIGS.4F and5F. In step S8, the dielectric layer8is formed with an opening in the gate region. In step S9, the second metallic material is filled into the opening in the gate region to form the gate electrode (G), as shown inFIGS.12G and12G. The gate electrode (G) is in contact with the barrier layer5(i.e., the AlGaN layer) through the opening. Details regarding the formation of the gate electrode (G) are similar to those described above with reference toFIGS.4G and5G. Next, conventional processes for manufacturing the nitride-based device are performed, such as formation of metal interconnect layers in a back-end-of-the-line section and formation of electrical connections between the metal interconnect layers and the source, drain, and gate electrodes (S, D, G) in a middle-of-the-line section. Such processes are not the essential features of the disclosure, and thus, detailed description thereof is omitted herein. Embodiment 3 Referring toFIGS.14to16, a third embodiment of the nitride-based device has a structure similar to that of the second embodiment of the nitride-based device having the ESD protection structure. However, the first p-type nitride layer61is formed in an upper region of the barrier layer5of the ESD protection region (B) of the epitaxial structure, and is exposed from an upper surface of the barrier layer5to be in contact with the metal layer7disposed thereon. A method for manufacturing the third embodiment of the nitride-based device is similar to that of the second embodiment, except that the first p-type nitride layer61is formed through ion implantation, or ion diffusion in step S2, rather than through selective-area secondary epitaxial growth. To be specific, a mask layer that is made of a material such as silicon nitride or silicon dioxide is formed on the epitaxial layer. The epitaxial structure of the ESD protection region (B) is then exposed from the mask layer by photolithography based on a predetermined shape of the first p-type nitride layer61. Subsequently, the first p-type nitride layer61is formed in the upper region of the barrier layer5of the ESD protection region (B) through ion implantation or ion diffusion, and then dopants for ion implantation or ion diffusion, such as Mg, are activated at high temperature. Finally, the mask layer is removed by one of wet etching and dry etching, such as ICP etching or RIE. The p-type doping concentration of the first p-type nitride layer61ranges from 1017cm−3to 1021cm−3. In summary, the electrostatic discharge protection structure of this disclosure achieves the purpose of charge release and effectively reduces risks of damage by ESD during manufacturing of the nitride-based device. Furthermore, the electrostatic discharge protection structure of this disclosure is applicable to the nitride-based device with different configurations of the gate electrode (G) by taking advantage of a region of the epitaxial structure that is positioned outside the active region (A) of the same without occupying additional chip area. In addition, the method for manufacturing the electrostatic discharge protection structure of this disclosure can be included in the method for manufacturing the nitride-based device. Hence, the method of manufacturing the nitride-based device having the electrostatic discharge protection structure is simple, low cost, and is suitable for actual mass production. In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure. While the disclosure has been described in connection with what are considered the exemplary embodiments, it is understood that this disclosure is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements. | 22,668 |
11862681 | Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. As used herein, the term “etch selectivity” refers to the ratio of the etch rates of two different materials under the same etching conditions. As used herein, the term “deposition selectivity” refers to the ratio of the deposition rates on two different materials or surfaces under the same deposition conditions. As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO2(e.g., greater than 3.9). As used herein, the term “p-type” defines a structure, layer, and/or region as being doped with p-type dopants, such as boron. As used herein, the term “n-type” defines a structure, layer, and/or region as being doped with n-type dopants, such as phosphorus. As used herein, the term “nanostructured” defines a structure, layer, and/or region as having a horizontal dimension (e.g., along an X- and/or Y-axis) and/or a vertical dimension (e.g., along a Z-axis) less than, for example, 100 nm. As used herein, the term “n-type work function metal (nWFM)” defines a metal or a metal-containing material with a work function value closer to a conduction band energy than a valence band energy of a material of a FET channel region. In some embodiments, the term “n-type work function metal (nWFM)” defines a metal or a metal-containing material with a work function value less than 4.5 eV. As used herein, the term “p-type work function metal (pWFM)” defines a metal or a metal-containing material with a work function value closer to a valence band energy than a conduction band energy of a material of a FET channel region. In some embodiments, the term “p-type work function metal (pWFM)” defines a metal or a metal-containing material with a work function value equal to or greater than 4.5 eV. In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures. The required gate voltage—the threshold voltage Vt—to turn on a field effect transistor (FET) can depend on the semiconductor material of the FET channel region and the work function values of the stack of layers (also referred to as a “gate stack”) included in a gate structure of the FET. For example, for an n-type FET (NFET), reducing the difference between the work function value of the NFET gate stack and the conduction band energy of the material (e.g., 4.1 eV for Si or 3.8 eV for SiGe) of the NFET channel region can reduce the NFET threshold voltage. For a p-type FET (PFET), reducing the difference between the work function value of the PFET gate stack and the valence band energy of the material (e.g., 5.2 eV for Si or 4.8 eV for SiGe) of the PFET channel region can reduce the PFET threshold voltage. The work function values of the FET gate stacks can depend on the thickness and/or material composition of each of the layers of the FET gate stacks. As such, FETs can be manufactured with different threshold voltages by adjusting the thickness and/or material composition of the gate stack layers. Due to the increasing demand for low power portable devices, there is an increasing demand for FETs with low threshold voltages, such as threshold voltages lower than 100 mV (also referred to as “ultra-low threshold voltage”). One way to achieve such ultra-low threshold voltage in FETs can be by using work function metal (WFM) layer(s) with thickness greater than about 4 nm (e.g., about 5 nm to about 10 nm) in the gate stacks. However, the thickness of the WFM layer(s) in the gate stacks can be constrained by the gate stack geometries of the FETs. For example, in gate-all-around (GAA) FETs, the thickness of the WFM layer(s) can be constrained by the spacing between the nanostructured channel regions of the GAA FETs. Also, depositing such thick WFM layer(s) can become increasingly challenging with the continuous scaling down of FETs (e.g., GAA FETs). The present disclosure provides example structures of FETs (e.g., finFETs or GAA FETs) with different gate structures configured to provide ultra-low threshold voltages and example methods of forming such FETs on a same substrate. The example methods form FETs of different conductivity types with different work function values, and as a result, with different and/or ultra-low threshold voltages on the same substrate. These example methods can be less complicated and more cost-effective in manufacturing reliable gate structures in FETs with nanostructured channel regions and with ultra-low threshold voltages than other methods of forming FETs with similar channel dimensions and threshold voltages on the same substrate. In addition, these example methods can form FET gate structures with smaller dimensions (e.g., thinner gate stacks) than other methods of forming FETs with similar threshold voltages. For example, using these example methods, the thicknesses of gate stack layers can be reduced by about 50% to about 75% compared to the thicknesses of gate stack layers formed using the other methods. In some embodiments, NFETs and PFETs with different gate stack layer configurations can be selectively formed on the same substrate. To achieve NFETs and PFETs with ultra-low threshold voltages, NFETs and PFETs can include Al-based NFET gate stacks and substantially Al-free (e.g., with no Al) PFET gate stacks, respectively. The NFET and PFET gate stacks can have n-type WFM (nWFM) layer(s) and p-type WFM (pWFM) layer(s) in physical contact with gate dielectric layers of the NFETs and PFETs, respectively. The NFET gate stacks can include Al-based nWFM layers (e.g., Al-based titanium (Ti) or tantalum (Ta) alloys) and the PFET gate stacks can include substantially Al-free (e.g., with no Al) pWFM bi-layers (e.g., Al-free Ti and Ta nitrides or alloys) with thicknesses smaller than 3 nm (e.g., about 0.5 nm to about 3 nm) to achieve ultra-low threshold voltages. In some embodiments, TaN of the pWFM bi-layers can prevent underlying layers from being etched during subsequent processing (e.g., deposition of fluorine-free tungsten (FFW) layer) and protect the integrity of the pWFM layer(s), thus improving the reliability of PFET gate structures. In some embodiments, the reliability of the NFET gate structures can be improved with the selective formation of Si capping layers on the Al-based nWFM layers. The Si capping layers can prevent the oxidation of the Al-based nWFM layers and as a result, prevent an increase in work function values of the Al-based nWFM layers. A semiconductor device100having FETs102A-102B is described with reference toFIGS.1A-1D, according to some embodiments.FIG.1Aillustrates an isometric view of semiconductor device100, according to some embodiments.FIGS.1B-1Dillustrate cross-sectional views along lines B-B, C-C, and D-D of semiconductor device100ofFIG.1A, respectively, according to some embodiments. In some embodiments, FETs102A-102B can be NFET and PFET, respectively. Even though two FETs are discussed with reference toFIGS.1A-1D, semiconductor device100can have any number of FETs. The discussion of elements of FETs102A-102B with the same annotations applies to each other, unless mentioned otherwise. The isometric view and cross-sectional views of semiconductor device100are shown for illustration purposes and may not be drawn to scale. Referring toFIGS.1A-1D, FETs102A-102B can be formed on a substrate106. Substrate106can be a semiconductor material such as, but not limited to, silicon. In some embodiments, substrate106can include a crystalline silicon substrate (e.g., wafer). In some embodiments, substrate106can include (i) an elementary semiconductor, such as germanium (Ge); (ii) a compound semiconductor including silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and/or a III-V semiconductor material; (iii) an alloy semiconductor including silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium stannum (GeSn), silicon germanium stannum (SiGeSn), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GaInP), gallium indium arsenide (GaInAs), gallium indium arsenic phosphide (GaInAsP), aluminum indium arsenide (AlAs), and/or aluminum gallium arsenide (AlGaAs); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon germanium (SiGe)-on insulator structure (SiGeOI); (vi) germanium-on-insulator (GeOI) structure; or (vii) a combination thereof. Further, substrate106can be doped depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, substrate106can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). FETs102A-102B can include fin structures108A-108B, passivation layers109A-109B, epitaxial fin regions110A-110B, gate structures112A-112B (also referred to as “gate-all-around (GAA) structures112A-112B”), inner spacers113A-113B, and outer spacers114A-114B, respectively. As shown inFIGS.1B-1D, fin structure108A can include a fin base portion119A and a stack of first semiconductor layers120disposed on fin base portion119A and fin structure108B can include a fin base portion119B and a stack of second semiconductor layers122. In some embodiments, fin base portions119A-119B can include material similar to substrate106. Fin base portions119A-119B can be formed from photolithographic patterning and etching of substrate106. First and second semiconductor layers120and122can include semiconductor materials different from each other. In some embodiments, first and second semiconductor layers120and122can include semiconductor materials with oxidation rates and/or etch selectivity different from each other. In some embodiments, first and second semiconductor layers120and122can include semiconductor materials similar to or different from substrate106. First and second semiconductor layers120and122can include (i) an elementary semiconductor, such as silicon or germanium; (ii) a compound semiconductor including a III-V semiconductor material; (iii) an alloy semiconductor including SiGe, germanium stannum, or silicon germanium stannum; or (iv) a combination thereof. In some embodiments, first and second semiconductor layers120and122can include SiGe with Ge in a range from about 25 atomic percent to about 50 atomic percent with any remaining atomic percent being Si or can include Si without any substantial amount of Ge (e.g., with no Ge). The semiconductor materials of first and/or second semiconductor layers120and122can be undoped or can be in-situ doped during their epitaxial growth process using: (i) p-type dopants, such as boron, indium, or gallium; and/or (ii) n-type dopants, such as phosphorus or arsenic. In some embodiments, first semiconductor layers120can include Si, SiAs, silicon phosphide (SiP), SiC, or silicon carbon phosphide (SiCP) for n-type FET102A and second semiconductor layers122can include SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium stannum boron (SiGeSnB), or a III-V semiconductor compound for p-type FET102A. In some embodiments, both first and semiconductor layers120and122can include Si, SiAs, SiP, SiC, or SiCP for n-type FETs102A-102B or SiGe, SiGeB, GeB, SiGeSnB or a III-V semiconductor compound for p-type FETs102A-102B. In some embodiments, first and second semiconductor layers120and122can include materials similar to each other for NFET and PFET102A-102B. Each of first semiconductor layers120can have (i) nanostructured regions120A wrapped around by epitaxial fin regions110A and underlying inner and outer spacers113A-114A (FIGS.1A and1D), and (ii) nanostructured channel regions120B wrapped around by gate structure112A (FIGS.1B and1D). Similarly, each of second semiconductor layers122can have (i) nanostructured regions122A wrapped around by epitaxial fin regions110B and underlying inner and outer spacers113B-114B (FIGS.1A and1C), and (ii) nanostructured channel regions122B wrapped around by gate structure112B (FIGS.1B and1C). Referring toFIG.1B, nanostructured channel regions120B and122B can have respective vertical dimensions H1and H2(e.g., thickness or diameter) along a Z-axis ranging from about 5 nm to about 12 nm and respective horizontal dimensions W1and W2(e.g., width or diameter) along a Y-axis ranging from about 5 nm to about 30 nm. The ratios of H1/W1and H2/W2can each range from about 0.2 to about 5. Though rectangular cross-sections of nanostructured channel regions120B and122B are shown inFIG.1B, nanostructured channel regions120B and122B can have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). Further, nanostructured channel regions120B and122B can have respective horizontal dimensions L1(FIG.1D) and L2(FIG.1C) along an X-axis ranging from about 10 nm to about 100 nm. The ratios of L1/H1and L2/H2can range from about 2 to about 20. In some embodiments, dimensions H1and H2, W1and W2, and L1and L2can be equal to or different from each other, respectively. In some embodiments, the ratios of H1/W1and H2/W2, and L1/H1and L2/H2can be equal to or different from each other, respectively. Referring toFIGS.1A-1B, passivation layers109A-109B can be disposed on sidewalls of nanostructured channel regions120B and122B and on sidewalls of fin base portions119A and119B, respectively. In some embodiments, passivation layer109A can be disposed on top surface of the top most nanostructured channel region120B, as shown inFIG.1D. In some embodiments, passivation layers109A-109B can be a nitride, oxide, fluoride, chloride, and/or sulfide film. Referring toFIGS.1A and1C-1D, epitaxial fin regions110A can be grown wrapped around nanostructured regions120A that are not under inner or outer spacers113A-114A. Similarly, epitaxial fin regions110B can be grown wrapped around nanostructured regions122A that are not under inner or outer spacers113B-114B. In some embodiment, as shown inFIGS.2A-2B, epitaxial fin regions110B-110A can be grown on fin base portions119B-119A, instead of being wrapped around nanostructured regions122A and120A, respectively. Epitaxial fin regions110A-110B can include epitaxially-grown semiconductor materials similar to or different from each other. In some embodiments, the epitaxially-grown semiconductor material can include the same material or a different material from the material of substrate106. Epitaxial fin regions110A-110B can each have a thickness along sidewalls of respective nanostructured regions120A and122A ranging from about 3 nm to about 6 nm. Though triangular cross-sections of epitaxial fin regions110A-110B are shown inFIGS.1C-1D, epitaxial fin regions110A-110B can have cross-sections of other geometric shapes (e.g., rectangular, semicircular, or polygonal). Epitaxial fin regions110A-110B can be n- and p-type, respectively. P-type epitaxial fin regions110B can include SiGe, SiGeB, GeB, SiGeSnB, a III-V semiconductor compound, or a combination thereof and a dopant concentration ranging from about 1×1020atoms/cm3to about 1×1021atoms/cm3. In some embodiments, each of p-type epitaxial fin regions110B can have a plurality of sub-regions (not shown) that can include SiGe and can differ from each other based on, for example, doping concentration, epitaxial growth process conditions and/or relative concentration of Ge with respect to Si. Each of the sub-regions can have thicknesses similar to or different from each other and thicknesses can range from about 0.5 nm to about 5 nm. In some embodiments, the atomic percent Ge in a first sub-region can be smaller than the atomic percent Ge in a second sub-region. In some embodiments, the first sub-region can include Ge in a range from about 15 atomic percent to about 35 atomic percent, while the second sub-region can include Ge in a range from about 25 atomic percent to about 50 atomic percent with any remaining atomic percent being Si in the sub-regions. The plurality of sub-regions of p-type epitaxial fin regions110B can have varying p-type dopant concentrations with respect to each other, according to some embodiments. For example, the first sub-region can be undoped or can have a dopant concentration lower (e.g., dopant concentration less than about 8×102atoms/cm3) than the dopant concentration (e.g., dopant concentration in a range from about 1×1020to about 3×1022atoms/cm3) of the second sub-region. In some embodiments, n-type epitaxial fin regions110A can have a plurality of n-type sub-regions (not shown). First n-type sub-regions can have materials with SiAs, SiC, or SiCP, a dopant concentration ranging from about 1×1020atoms/cm3to about 1×1021atoms/cm3and a thickness ranging from about 1 nm to about 3 nm. Second n-type sub-regions disposed on the first n-type sub-regions can have materials with SiP and a dopant concentration ranging from about 1×1020atoms/cm3to about 1×1022atoms/cm3. Third n-type sub-regions disposed on the second n-type sub-regions can have materials with material compositions and thicknesses similar to the first n-type sub-regions. Epitaxial fin regions110A-110B along with their underlying nanostructured regions120A and122A can form source/drain (S/D) regions126A-126B, respectively. In some embodiments, epitaxial fin regions110A-110B as shown inFIGS.2B-2Acan form S/D regions126A-126B, respectively. Nanostructured channel regions120B and122B can be interposed between a pair of S/D regions126A-126B, respectively, as shown inFIGS.1C-1D and2A-2B. Gate structures112A-112B can be multi-layered structures and can be wrapped around nanostructured channel regions120B and122B, respectively, for which gate structures112A-112B can be referred to as “gate-all-around (GAA) structures” or “horizontal gate-all-around (HGAA) structures,” and FETs102A-102B can be referred to as “GAA FETs102A-102B” or “GAA NFET and PFET102A-102B,” respectively. Gate structures112A-112B can include interfacial oxide layers127A-127B, gate dielectric layers128A-128B, gate WFM layers130A-130B, fluorine blocking layers134A-134B, and gate metal fill layers135A-135B, respectively. Gate structure112A can further include capping layers131-132. Even thoughFIG.1Bshows that all the layers of gate structures112A-112B are wrapped around nanostructured channel regions120B and122B, respectively, nanostructured channel regions120B and122B can be wrapped around by at least interfacial oxide layers127A-127B and gate dielectric layers128A-128B to fill the spaces between adjacent nanostructured channel regions120B and122B, and thus electrically isolate nanostructured channel regions120B and122B from each other, respectively, to prevent shorting between gate structures112A-112B and S/D regions126A-126B during operation of FETs102A-102B, respectively. In some embodiments, instead of all the layers of gate structures112A-112B being wrapped around nanostructured channel regions120B and122B, respectively, nanostructured channel regions120B and122B can be wrapped around by at least interfacial oxide layers127A-127B, gate dielectric layers128A-128B, gate WFM layers130A-130B to fill the spaces between adjacent nanostructured channel regions120B and122B to achieve ultra-low threshold voltage for FETs102A-102B, respectively. Each of interfacial oxide layers127A-127B can be disposed on respective nanostructured channel regions120B and122B and can include silicon oxide and a thickness ranging from about 0.5 nm to about 1.5 nm. Each of gate dielectric layers128A-128B can have a thickness (e.g., about 1 nm to about 3 nm) that is about 2 to 3 times the thickness of interfacial oxide layers127A-127B and can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), (iii) a high-k dielectric material having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu), or (iv) a combination thereof. Referring toFIGS.1B-1D, in some embodiments, WFM layers130A-130B can be disposed on and in physical contact with gate dielectric layers128A-128B and can include nWFM and pWFM layers for NFET102A and PFET102B, respectively. The nWFM layers can include a metallic material with a work function value closer to a conduction band energy than a valence band energy of a material of nanostructured channel regions120B. For example, the nWFM layers can include an Al-based or Al-doped metallic material with a work function value less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which can be closer to the conduction band energy (e.g., 4.1 eV of Si or 3.8 eV of SiGe) than the valence band energy (e.g., 5.2 eV of Si or 4.8 eV of SiGe) of Si-based or SiGe-based nanostructured channel regions120B, respectively. In some embodiments, the nWFM layers can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or a combination thereof. In some embodiments, each of the nWFM layers can include a thickness ranging from about 1 nm to about 3 nm. The thickness within this range can allow the nWFM layers to be wrapped around nanostructured channel regions120B for ultra-low threshold voltage of NFET102A without being constrained by the spacing between adjacent nanostructured channel regions120B. Each of WFM layers130B can include bi-layers of pWFM layers130B1-130B2, which are different from each other in material and/or structural composition. Either or both of pWFM layers130B1-130B2can include a metallic material with a work function value closer to a valence band-edge energy than a conduction band-edge energy of a material of nanostructured channel regions122B. For example, either or both of pWFM layers130B1-130B2can include a substantially Al-free (e.g., with no Al) metallic material with a work function value equal to or greater than 4.5 eV (e.g., about 4.5 eV to about 5.5 eV), which can be closer to the valence band-edge energy (e.g., 5.2 eV of Si or 4.8 eV of SiGe) than the conduction band-edge energy (e.g., 4.1 eV of Si or 3.8 eV of SiGe) of Si-based or SiGe-based nanostructured channel regions122B, respectively. In some embodiments, pWFM layers130B1can include substantially Al-free (e.g., with no Al) (i) Ti-based nitrides or alloys, such as TiN, TiSiN, titanium gold (Ti—Au) alloy, titanium copper (Ti—Cu) alloy, titanium chromium (Ti—Cr) alloy, titanium cobalt (Ti—Co) alloy, titanium molybdenum (Ti—Mo) alloy, or titanium nickel (Ti—Ni) alloy; (ii) Ta-based nitrides or alloys, such as TaN, TaSiN, Ta—Au alloy, Ta—Cu alloy, Ta—W alloy, tantalum platinum (Ta—Pt) alloy, Ta—Mo alloy, Ta—Ti alloy, or Ta—Ni alloy; or (iii) a combination thereof. In some embodiments, pWFM layers130B2can be configured to prevent etching of pWFM layers130B1by precursors (e.g., tungsten chloride) used during deposition of overlying fluorine blocking layers134B (e.g., FFW). In some embodiments, pWFM layers130B2can include substantially Al-free (e.g., with no Al) (i) Ta-based nitrides, such as TaN or TaSiN; (ii) W-based nitrides, such as WN or WCN; or (iii) a combination thereof. In some embodiments, each of pWFM layers130B1-130B2can include a thickness ranging from about 1 nm to about 3 nm. The thickness within this range can allow pWFM layers130B1-130B2to be wrapped around nanostructured channel regions120B for ultra-low threshold voltage of PFET102B without being constrained by the spacing between adjacent nanostructured channel regions122B. Referring toFIGS.1B-1D, capping layers131-132can be selectively formed on WFM layers130A and not on WFM layers130B. In some embodiments, capping layers131can include Si-based layers and capping layers132can include bi-layers of Ti— and/or Ta-based capping layers132A and Ta— and/or W-based capping layers132B. Either or both capping layers131and132A can be configured to prevent the oxidation of WFM layers130A (e.g., Al-based or Al-doped layers) during the processing of gate structures112A-112B. WFM layers130A are prevented from being oxidized because oxidized WFM layers130A (e.g., aluminum oxide-based layers) can have work function values closer to the valence band-edge energy (e.g., 5.2 eV of Si or 4.8 eV of SiGe) than the conduction band-edge energy (e.g., 4.1 eV of Si or 3.8 eV of SiGe) of Si-based or SiGe-based nanostructured channel regions120B, respectively, and as a result, increase the threshold voltage of NFET102A. Similar to pWFM layers130B2, capping layers132B can be configured to prevent etching of underlying capping layers132A by precursors (e.g., tungsten chloride) used during deposition of overlying fluorine blocking layers134B (e.g., FFW). In some embodiments, the material and/or structural composition of capping layers132A-132B can be similar to that of pWFM layers130B1-130B2and can be simultaneously formed with pWFM layers130B1-130B2. In some embodiments, fluorine blocking layers134A-134B can be disposed between gate metal fill layers135A and capping layers132and between gate metal fill layers135B and WFM layers130B, respectively. Fluorine blocking layers134A-134B can prevent any substantial diffusion of fluorine (e.g., no fluorine diffusion) from fluorine-based precursors used during the deposition of overlying gate metal fill layers135A-135B to underlying layers capping layers132and WFM layers130B, respectively. In some embodiments, fluorine blocking layers134A-134B can include substantially fluorine-free metal layers (e.g., FFW layers). The substantially fluorine-free metal layers can include an amount of fluorine contaminants less than about 5 atomic percent in the form of ions, atoms, and/or molecules. In some embodiments, fluorine blocking layers134A-134B can each have a thickness ranging from about 2 nm to about 4 nm for effective blocking of fluorine diffusion from gate metal fill layers135A-135B to capping layers132and WFM layers130B, respectively. Each of gate metal fill layers135A-135B can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals different from each other. In some embodiments, each of gate metal fill layers135A-135B can include a suitable conductive material, such as W, Ti, Ag, ruthenium (Ru), Mo, Cu, cobalt (Co), Ni, metal alloys, and/or combinations thereof. Though gate structures112A-112B are shown to have GAA structures, other gate structures (e.g., vertical GAA structures or gate structures without GAA structures) are within the scope and spirit of this disclosure. Each of inner spacers113A can be disposed between a sub-region110As of epitaxial regions110A and a sub-region112As of gate structure112A and each of inner spacers113B can be disposed between a sub-region110Bs of epitaxial regions110B and a sub-region112Bs of gate structure112B. Each of inner spacers113A-113B can prevent capacitive coupling between sub-regions110As and112As and between sub-regions110Bs and112Bs, respectively. Preventing capacitive coupling between these sub-regions can reduce parasitic capacitance between S/D regions126A-126B and gate structures112A-112B and improve device performance of FETs102A-102B. In some embodiments, inner spacers113A-113B can include a low-k dielectric material with a dielectric constant less than about 3.9 and/or between about 1 to about 3.5. In some embodiments, the low-k dielectric material can include silicon oxycarbonitride (SiOCN), silicon carbon nitride (SiCN), silicon oxide carbide (SiOC), polymides, carbon-doped oxides, fluorine-doped oxides, hydrogen-doped oxides, or a combination thereof. In some embodiments, inner spacers113A-113B can have material similar to or different from each other. In some embodiments, both FETs102A-102B can have inner spacers, such as inner spacers113A-113B or one of FETs102A-102B can have inner spacers, such as inner spacers113A or113B. Though rectangular cross-sections of inner spacers113A-113B are shown inFIGS.1C-1D, inner spacers113A-113B can have cross-sections of other geometric shapes (e.g., semicircular, triangular, or polygonal). In some embodiments, each of inner spacers113A-113B can have a horizontal dimension along an X-axis ranging from about 3 nm to about 15 nm. Outer spacers114A-114B can be disposed on sidewalls of respective gate structures112A-112B and be in physical contact with respective gate dielectric layers128A-128B, according to some embodiments. Outer spacers114A-114B can include an insulating material, such as silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), a low-k material, or a combination thereof. Outer spacers114A-114B can have a low-k material with a dielectric constant less than about 3.9 and/or between about 1 to about 3.5. In some embodiments, each of outer spacers114A-114B can have a thickness ranging from about 2 nm to about 10 nm. In some embodiments, a horizontal distance between outer spacers114A along an X-axis is greater than a horizontal distance between inner spacers113A along an X-axis. Similarly, a horizontal distance between outer spacers114B along an X-axis is greater than a horizontal distance between inner spacers113B along an X-axis. FETs102A-102B can be incorporated into an integrated circuit through the use of other structural components, such as gate contact structures, S/D contact structures, conductive vias, conductive lines, interconnect metal layers, etc., which are not shown herein for the sake of clarity. Referring toFIGS.1A-1D, semiconductor device100can further include etch stop layer (ESL)116, interlayer dielectric (ILD) layer118, and shallow trench isolation (STI) regions138. ESL116can be disposed on sidewalls of outer spacers114A-114B and on epitaxial regions110A-110B. ESL116can be configured to protect gate structures112A-112B and/or S/D regions126A-126B. This protection can be provided, for example, during the formation of ILD layer118and/or S/D contact structures (not shown). In some embodiments, ESL116can include, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbo-nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), or a combination thereof. In some embodiments, ESL116can have a thickness ranging from about 3 nm to about 30 nm. ILD layer118can be disposed on ESL116and can include a dielectric material deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). In some embodiments, the dielectric material is silicon oxide. In some embodiments, ILD layer118can have a thickness in a range from about 50 nm to about 200 nm. STI regions138can be configured to provide electrical isolation between FETs102A-102B and neighboring FETs (not shown) on substrate106and/or neighboring active and passive elements (not shown) integrated with or deposited on substrate106. In some embodiments, STI regions138can include a plurality of layers, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating materials. In some embodiments, STI regions138can have a vertical dimension along a Z-axis ranging from about 40 nm to about 200 nm. The cross-sectional shapes of semiconductor device100and its elements (e.g., fin structure108A-108B, gate structures112A-112B, epitaxial fin regions110A-110B, inner spacers113-113B, outer spacers114A-114B, and/or STI regions138) are illustrative and are not intended to be limiting. FIG.3is a flow diagram of an example method300for fabricating semiconductor device100, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.300will be described with reference to the example fabrication process for fabricating semiconductor device300as illustrated inFIGS.4A-17A,4B-17B,7C-12C, and7D-12D.FIGS.4A-12Aare isometric views of semiconductor device100at various stages of its fabrication.FIGS.4B-12Bare cross-sectional views along lines B-B of structures ofFIGS.4A-12A, respectively, according to some embodiments.FIGS.7C-12C and7D-12Dare cross-sectional views along lines C-C and D-D of structures ofFIGS.7A-12A, respectively, according to some embodiments.FIGS.13A-17A and13B-17Bare cross-sectional views along lines C-C and D-D, respectively, of semiconductor device100at various stages of fabrication of gate structures112A-112B following the formation of the structure ofFIG.12A, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method300may not produce a complete semiconductor device100. Accordingly, it is understood that additional processes can be provided before, during, and after method300, and that some other processes may only be briefly described herein. Elements inFIGS.4A-17A,4B-17B,7C-12C, and7D-12Dwith the same annotations as elements inFIGS.1A-1Dare described above. In operation305, fin structures of an NFET and a PFET are formed on a substrate. For example, fin structures108A*-108B* (shown inFIGS.5A-5B) with fin base portions119A-119B and stacks of first and second semiconductor layers120and122arranged in alternating configurations can be formed on substrate106as described with reference toFIGS.4A-5B. In subsequent processing, fin structures108A*-108B* can form fin structures108A-108B (shown inFIGS.1A-1D) after the removal of second and first semiconductor layers122and120from fin structures108A*-108B*, respectively. The process for forming fin structures108A*-108B* can include forming a stacked layer108* on substrate106as shown inFIGS.4A-4B. Stacked layer108* can include first and second semiconductor layers120* and122* stacked in an alternating configuration. First and second semiconductor layers120* and122* can have respective vertical dimensions H1and H2along a Z-axis ranging from about 5 nm to about 30 nm. Each of first and second semiconductor layers120* and122* can be epitaxially grown on its underlying layer and can include semiconductor materials different from each other. In some embodiments, first and second semiconductor layers120* and122* can include semiconductor materials with oxidation rates and/or etch selectivity different from each other. In some embodiments, first and second semiconductor layers120* and122* can include semiconductor materials similar to or different from substrate106. First and second semiconductor layers120* and122* can include (i) an elementary semiconductor, such as silicon or germanium; (ii) a compound semiconductor including a III-V semiconductor material; (iii) an alloy semiconductor including SiGe, germanium stannum, or silicon germanium stannum; or (iv) a combination thereof. In some embodiments, first semiconductor layers120* can include Si and second semiconductor layers122* can include SiGe. In some embodiments, first and second semiconductor layers120* and122* can include SiGe with Ge in a range from about 25 atomic percent to about 50 atomic percent with any remaining atomic percent being Si or can include Si without any substantial amount of Ge (e.g., with no Ge). First and/or second semiconductor layers120* and122* can be undoped or can be in-situ doped during their epitaxial growth process using (i) p-type dopants, such as boron, indium, or gallium; and/or (ii) n-type dopants, such as phosphorus or arsenic. For p-type in-situ doping, p-type doping precursors, such as diborane (B2H6), boron trifluoride (BF3), and/or other p-type doping precursors can be used. For n-type in-situ doping, n-type doping precursors, such as phosphine (PH3), arsine (AsH3), and/or other n-type doping precursor can be used. The process for forming fin structures108A*-108B* can further include etching the structure ofFIG.4Athrough patterned hard mask layers (not shown) formed on stacked layer108* ofFIG.4A. In some embodiments, hard mask layers can include layers of silicon oxide formed, for example, using a thermal oxidation process and/or layers of silicon nitride formed using, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD). The etching of the structure ofFIG.4Acan include a dry etch, a wet etch process, or a combination thereof. The dry etch process can include using etchants having an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, NF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, HCl, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), ammonia gas (NH3), an iodine-containing gas, other suitable etching gases and/or plasmas, or combinations thereof. The dry etch process can be carried out at high bias voltage ranging from about 150 V to about 350 V, at a radio frequency power ranging from about 10 W to about 50 W, at a pressure of about 5 Torr to about 50 Torr, at a temperature ranging from about 25° C. to about 40° C., and for a time period ranging from about 10 sec to about 40 sec. The wet etch process can include etching in diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia (NH3), a solution containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), or combinations thereof. After the etching of stacked layer108*, fin structures108A*-108B* with fin base portions119A-119B having respective vertical dimensions along a Z-axis ranging from about 40 nm to about 60 nm can be formed, as shown inFIGS.5A-5B. Stacks of first and second semiconductor layers120and122formed on fin base portions119A-119B can have respective vertical dimensions H3and H4along a Z-axis ranging from about 5 nm to about 30 nm and respective horizontal dimensions W3and W4along a Y-axis ranging from about 5 nm to about 50 nm. The ratios of H3/W3and H4/W4can each range from about 0.2 to about 5. In some embodiments, dimensions H3-H4and W3-W4can be equal to or different from each other, respectively. In some embodiments, the ratios of H3/W3and H4/W4can be equal to or different from each other, respectively. Following the formation of fin structures108A*-108B*, passivation layers109A-109B can be formed on fin structures108A*-108B*, respectively, and STI regions138can be formed on passivation layers109A-109B, as shown inFIGS.6A-6B. The process for forming passivation layers109A-109B on fin structures108A*-108B* can include blanket depositing a passivation layer109on the structure ofFIG.5Ausing one or more precursor gases having fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, NH3, and/or hydrogen sulfide (H2S) in an ALD or CVD process. The portions of blanket deposited passivation layer109on fin structures108A*-108B* can be referred to as “passivation layers109A-109B,” respectively. The formation of STI regions138can include (i) depositing a layer of nitride material (not shown) on passivation layer109using ALD or CVD, (ii) depositing a layer of oxide material (not shown) on the layer of nitride material using ALD or CVD, (iii) depositing a layer of insulating material (not shown) on the layer of oxide material, (iv) annealing the layer of insulating material, (v) chemical mechanical polishing (CMP) the layers of nitride and oxide materials and the annealed layer of insulating material, and (vi) etching back the polished structure by a dry etch process, a wet etch process, or a combination thereof to form STI regions138ofFIGS.6A-6B. Referring toFIG.3, in operation310, polysilicon structures are formed on the fin structures. For example, as shown inFIGS.6A-6B, polysilicon structures112A*-112B* can be formed on fin structures108A*-108B* and outer spacers114A-114B can be formed on sidewalls polysilicon structures112A*-112B*. In some embodiments, prior to the formation of polysilicon structures112A*-112B*, protective oxide layers640A-640B can be formed on respective passivation layers109A-109B and polysilicon structures112A*-112B* can be formed on respective protective oxide layer640A-640B and STI regions138, as described with reference toFIGS.6A-6B. The process for forming protective oxide layers640A-640B can include (i) blanket depositing a layer of oxide material (not shown) on the partial semiconductor device100(not shown) formed after the formation of STI regions138, (ii) a high temperature annealing process, and (iii) an etching process. The layer of oxide material can include silicon oxide and can be blanket deposited using a suitable deposition process, such as CVD, ALD, plasma enhanced ALD (PEALD), physical vapor deposition (PVD), or e-beam evaporation. In some embodiments, the layer of oxide material can be blanket deposited using PEALD at an energy ranging from about 400 W to about 500 W and at a temperature ranging from about 300° C. to about 500° C. The blanket deposition of the layer of oxide material can be followed by a dry annealing process under oxygen gas flow at a temperature ranging from about 800° C. to about 1050° C. The oxygen precursor concentration can be in a range of about 0.5% to about 5% of the total gas flow rate. In some embodiments, the annealing process can be a flash process where the annealing time can be between about 0.5 s to about 5 s. The etching process to form protective oxide layers640A-640B may not follow the annealing process and can be carried out during the formation of polysilicon structures112A*-112B* described below or as a separate etching process after the formation of polysilicon structures112A*-112B*. The annealing of the blanket deposited layer of oxide material for protective oxide layers640A-640B can be followed by the formation of polysilicon structures112A*-112B*. During subsequent processing, polysilicon structures112A*-112B* can be replaced in a gate replacement process to form gate structures112A-112B, respectively. In some embodiments, the process for forming polysilicon structures112A*-112B* can include blanket depositing a layer of polysilicon material on the annealed layer of oxide material for protective oxide layers640A-640B and etching the blanket deposited layer of polysilicon material through patterned hard mask layers642A-642B formed on the layer of polysilicon material. In some embodiments, the polysilicon material can be undoped and hard mask layers642A-642B can include an oxide layer and/or a nitride layer. The oxide layer can be formed using a thermal oxidation process and the nitride layer can be formed by LPCVD or PECVD. Hard mask layers642A-642B can protect polysilicon structures112A*-112B* from subsequent processing steps (e.g., during formation of inner spacers113A-113B, outer spacers114A-114B, epitaxial fin regions110A-110B, ILD layer118, and/or ESL116). The blanket deposition of the layer of polysilicon material can include CVD, PVD, ALD, or other suitable deposition processes. In some embodiments, the etching of the blanket deposited layer of polysilicon material can include a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching of the blanket deposited layer of polysilicon material can include four etching steps. The first polysilicon etch step can include using a gas mixture having hydrogen bromide (HBr), oxygen (O2), fluoroform (CHF3), and chlorine (Cl2). The second polysilicon etch step can include using a gas mixture having HBr, O2, Cl2, and nitrogen (N2) at a pressure of about 45 mTorr to about 60 mTorr. The third polysilicon etch step can include using a gas mixture having HBr, O2, Cl2, N2, and argon (Ar) at a pressure of about 45 mTorr to about 60 mTorr. The fourth polysilicon etch step can include using a gas mixture having HBr, O2, Cl2, and N2at a pressure of about 45 mTorr to about 60 mTorr. Along with the polysilicon material, the fourth polysilicon etch step can remove portions of the annealed blanket deposited layer of oxide material for protective oxide layers640A-640B that are not covered by polysilicon structures112A*-112B*, according to some embodiments. The first polysilicon etch step can have a higher polysilicon etch rate than the second, third, and/or fourth polysilicon etch steps. The first polysilicon etch step can be used to etch unwanted portions of the blanket deposited layer of polysilicon material above fin structures108A*-108B*. The second, third, and fourth polysilicon etch steps can be used to etch unwanted portions of the blanket deposited layer of polysilicon material within high aspect ratio spaces643. In some embodiments, vertical dimensions of polysilicon structures112A*-112B* along a Z-axis on top surfaces of fin structures108A*-108B* can be in a range from about 40 nm to about 60 nm. Polysilicon structures112A*-112B* can have an aspect ratio equal to or greater than about 9, where aspect ratio is a ratio of a vertical dimension along a Z-axis to a horizontal dimension along a Y-axis of polysilicon structures112A*-112B*. In some embodiments, horizontal dimensions between center lines of adjacent polysilicon structures112A*-112B* along a Y-axis (e.g., spacing) can be in a range from about 30 nm to about 70 nm. Following the formation of polysilicon structures112A*-112B*, the portions of the blanket deposited layer of oxide that are not covered by polysilicon structures112A*-112B* can be removed by a dry or a wet etch process if they are not removed during the fourth polysilicon etch step to form the structure ofFIGS.6A-6B. The structure ofFIGS.6A-6Bhas polysilicon structures112A*-112B* and protective oxide layers640A-640B disposed on stacks of nanostructured regions120B and122B (FIG.6B), respectively, and has stacks of nanostructured regions120A and122A (FIG.6A) extending out from either sides of polysilicon structures112A*-112B*, respectively, along an X-axis. In some embodiments, protective oxide layers640A-640B can have vertical dimensions (e.g., thickness on top surface of fin structures108A*-108B*) along a Z-axis and horizontal dimensions (e.g., thickness on sidewalls of fin structures108A*-108B*) along a Y-axis ranging from about 1 nm to about 3 nm. In some embodiments, the vertical dimensions can be equal to or greater than the horizontal dimensions. The presence of protective oxide layers640A-640B allow etching polysilicon material from high aspect ratio spaces643(e.g., aspect ratio greater than 1:15, 1:18, or 1:20) without substantially etching and/or damaging fin structures108A*-108B* during the formation of polysilicon structures112A*-112B*. Following the formation of polysilicon structures112A*-112B*, outer spacers114A-114B can be formed on sidewalls of polysilicon structures112A*-112B* and on portions of passivation layers109A-109B not covered by polysilicon structures112A*-112B*, as shown inFIGS.6A-6B. Referring toFIG.3, in operation315, n- and p-type epitaxial fin regions are selectively formed on the fin structures. For example, n- and p-type epitaxial fin regions110A-110B can be selectively formed on portions of fin structures108A*-108B* (e.g., nanostructured regions120A and122A, respectively) that are not underlying polysilicon structures112A*-112B*, respectively, as described with reference toFIGS.7A-8D. In some embodiments, prior to the selective formation of epitaxial fin regions110A-110B, inner spacers113A-113B can be selectively formed on portions of nanostructured regions120A and122B that are not wrapped around by epitaxial fin regions110A-110B, respectively, in subsequent processing. In some embodiments, the selective formation of inner spacers113A can be followed by the selective formation of epitaxial fin regions110A, which can be followed by the selective formation of inner spacers113B and subsequently, the selective formation of epitaxial fin regions110B, as described with reference toFIGS.7A-8D. Prior to the formation of inner spacers113A and epitaxial regions110A of FET102A, FET102B can be protected by patterning a photoresist layer746on FET102B as shown inFIGS.7B-7C. Photoresist layer746is not shown inFIG.7Afor the sake of clarity. The process for forming inner spacers113A can include sequential steps of (i) etching portions of outer spacers114A from the stack of nanostructured regions120A and122A extending out from either sides of polysilicon structure112A* along an X-axis, (ii) etching nanostructured regions122A from the stack of nanostructured regions120A and122A to form suspended nanostructured regions120A with openings (not shown) between them, (iii) blanket depositing a layer of low-k dielectric material (not shown) until the openings are filled or partially filled with the layer of low-k dielectric material, and (iv) etching the blanket deposited layer of low-k dielectric material to etch back the layer of low-k dielectric material within the openings to form inner spacers113A as shown inFIG.7D. The etching of outer spacers114A can include a dry etch process with etchant gases, such as CH4, O2, and CH3F. The flow rate ratio of CH4:O2:CH3F can range from about 1:1:1 to about 1:2:4. The etching of nanostructured regions122A can include using a dry etching process or a wet etching process with higher selectivity towards SiGe than Si. For example, the wet etching process can include using a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) and/or a mixture of ammonia hydroxide (NH4OH) with H2O2and deionized (DI) water (APM). As a result of the etching of nanostructured regions122A, suspended nanostructured regions120A can be formed with openings between them. The etching process can be controlled such that the openings extend along an X-axis at least under outer spacers114A and the sidewalls of nanostructured regions122B are substantially aligned with interfaces between outer spacers114A and polysilicon structure112A*. In some embodiments, the openings can further extend along an X-axis under polysilicon structure112A* to prevent the formation of gate structure112A under outer spacers114A during the replacement of nanostructured regions122B and polysilicon structure112A* with gate structure112A in subsequent processing. The blanket deposition of the layer of low-k dielectric material can include using an ALD process or a CVD process. In some embodiments, the blanket deposition process can include a plurality of cycles of deposition and etch processes. In some embodiments, the low-k dielectric material can include silicon oxycarbonitride (SiOCN), silicon carbon nitride (SiCN), silicon oxide carbide (SiOC), polymides, carbon-doped oxides, fluorine-doped oxides, hydrogen-doped oxides, or a combination thereof. The etching of the blanket deposited layer of low-k dielectric material can include a dry etch process using a gas mixture of HF and NF3. The gas ratio of HF to NF3can range from about 1 to about 20. Epitaxial fin regions110A can be grown around the suspended nanostructured regions120A after the formation of inner spacers113A. In some embodiments, epitaxial fin regions110A can be grown by (i) CVD, such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), remote plasma CVD (RPCVD), or any suitable CVD; (ii) molecular beam epitaxy (MBE) processes; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, epitaxial fin regions110A can be grown by an epitaxial deposition/partial etch process, which repeats the epitaxial deposition/partial etch process at least once. N-type epitaxial fin regions110A can include Si without any substantial amount of Ge (e.g., with no Ge) and can be in-situ doped during the epitaxial growth process using n-type dopants, such as phosphorus or arsenic. For n-type in-situ doping, n-type doping precursors such as, but not limited to, phosphine (PH3), arsine (AsH3), and/or other n-type doping precursor, can be used. After the formation of inner spacers113A and epitaxial regions110A of FET102A, photoresist layer746can be removed from FET102B and another photoresist layer846can be patterned on FET102A (shown inFIGS.8B and8D) to protect FET102A during the subsequent processing steps to form inner spacers113B and epitaxial regions110B of FET102B as described with reference toFIGS.8A-8D. Photoresist layer846is not shown inFIG.8Afor the sake of clarity. The process for forming inner spacers113B can include sequential steps of (i) etching portions of outer spacers114B from the stack of nanostructured regions120A and122A extending out from either sides of polysilicon structure112B* along an X-axis, (ii) etching nanostructured regions120A from the stack of nanostructured regions120A and122A to form suspended nanostructured regions122A with openings (not shown) between them, (iii) blanket depositing a layer of low-k dielectric material (not shown) until the openings are filled or partially filled with the layer of low-k dielectric material, and (iv) etching the blanket deposited layer of low-k dielectric material to etch back the layer of low-k dielectric material within the openings to form inner spacers113B as shown inFIG.8C. The process for etching the portions of outer spacers114B can be similar to the etching process of outer spacers114A. The etching of nanostructured regions120A can include using a wet etching process with higher selectivity towards Si than SiGe. For example, the wet etching process can include using a mixture (NH4OH) with HCl. The process for etching nanostructured regions120A can be controlled such that the openings extend along an X-axis at least under outer spacers114B and the sidewalls of nanostructured regions120B are substantially aligned with interface between outer spacers114B and polysilicon structure112B*. In some embodiments, the openings can further extend along an X-axis under polysilicon structure112B* to prevent the formation of gate structure112B under outer spacers114B during the replacement of nanostructured regions120B and polysilicon structure112B* with gate structure112B in subsequent processing. The blanket deposition and the etching of the layer of low-k dielectric material can be similar to that used to deposit and etch back the layer of low-k dielectric material for forming inner spacers113A. Epitaxial fin regions110B can be grown around the suspended nanostructured regions122A after the formation of inner spacers113B. Epitaxial fin regions110B can be grown similarly as epitaxial fin regions110A described with reference toFIG.7A-7D, except p-type epitaxial fin regions110B with SiGe can be in-situ doped during the epitaxial growth process using p-type dopants, such as boron, indium, or gallium. For p-type in-situ doping, p-type doping precursors such as, but not limited to, diborane (B2H6), boron trifluoride (BF3), and/or other p-type doping precursors can be used. After the formation of inner spacers113B and epitaxial regions110B, photoresist layer846can be removed from FET102A. In some embodiments, the processing steps for forming inner spacers113A-113B can be simultaneously performed without using photoresist layers746and846if both FETs102A-102B are of the same conductivity type (e.g., n-type or p-type). Similarly, the processing steps for forming epitaxial fin regions110A-11B can be simultaneously performed without using photoresist layers746and846after simultaneously forming inner spacers113A-113B if both FETs102A-102B are of similar conductivity type. Referring toFIG.3, in operation320, nanostructured channel regions are formed between the n-type epitaxial fin regions and between the p-type epitaxial fin regions. For example, nanostructured channel regions120B and122B can be formed sequentially in regions of fin structures108A*-108B* underlying polysilicon structures112A*-112B*, as described with reference toFIGS.9A-12D. Prior to the formation of nanostructured channel regions120B and122B, ESL116can be deposited on the structure ofFIG.8Aand ILD118can be deposited on ESL116. In some embodiments, ESL116can be formed of materials including SiNx, SiOx, SiON, SiC, SiCN, BN, SiBN, SiCBN, or a combination thereof. The formation of ESL116can include blanket depositing a layer of material for ESL116on the structure ofFIG.8Ausing PECVD, sub atmospheric chemical vapor deposition (SACVD), LPCVD, ALD, high-density plasma (HDP), plasma enhanced atomic layer deposition (PEALD), molecular layer deposition (MLD), plasma impulse chemical vapor deposition (PICVD), or other suitable deposition methods. The blanket deposition of the layer of material for ESL116can be followed by a blanket deposition of a layer of dielectric material for ILD118. In some embodiments, the dielectric material can be silicon oxide. The layer of dielectric material can be deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). For example, flowable silicon oxide can be deposited using a FCVD process. The blanket deposition process can be followed by a thermal annealing of the deposited layer of dielectric material in steam at a temperature ranging from about 200° C. to about 700° C. for a period ranging from about 30 minutes to about 120 minutes. The thermal annealing can be followed by a CMP process to coplanarize top surfaces of ESL116, ILD118, outer spacers114A-114B, and polysilicon structures112A*-112B* with each other as shown inFIG.9A. During the CMP process, hard mask layers642A-642B can be removed. Following the CMP process, nanostructured channel regions120B of FET102A can be formed as described with reference toFIGS.9A-10D. The process for forming nanostructured channel regions120B can include sequential steps of (i) forming a photoresist layer950on FET102B as shown inFIGS.9A-9C, (ii) etching polysilicon structure112A* and protective oxide layer640A from the structure ofFIG.9A, and (iii) etching nanostructured regions122B of FET102A from the structure ofFIG.9A. In some embodiments, polysilicon structure112A* and protective oxide layer640A can be etched using the first, second, third, and/or fourth polysilicon etch steps described in operation310. In some embodiments, nanostructured regions122B can be etched using a wet etch process similar to that used for etching nanostructured regions122A described with reference toFIGS.7A-7D. As a result of the etching of nanostructured regions122B, nanostructured channel regions120B are formed with gate openings1052A around them as shown inFIGS.10B and10D. Following the etching of nanostructured regions122B of FET102A, nanostructured channel regions122B of FET102B can be formed as described with reference toFIGS.11A-12D. The process for forming nanostructured channel regions122B can include sequential steps of (i) removing photoresist layer950, (ii) forming a photoresist layer1150within gate openings1052A (shown inFIGS.10B and10D) to protect nanostructured channel regions120A as shown inFIGS.11B and11D, (iii) etching polysilicon structure112B* and protective oxide layer640B, and (iv) etching nanostructured regions120B of FET102B from the structure ofFIG.10A. Similar to the etching of polysilicon structure112A* and protective oxide layer640A, polysilicon structure112B* and protective oxide layer640B can be etched using the first, second, third, and/or fourth polysilicon etch steps described in operation310. In some embodiments, nanostructured regions120B can be etched using a wet etch process similar to that used for etching nanostructured regions120A described with reference toFIGS.8A-8D. As a result of the etching of nanostructured regions120B, nanostructured channel regions122B are formed with gate openings1052B around them as shown inFIGS.11B and11D. Following the formation of nanostructured channel regions122B of FET102B, photoresist layer1150can be removed from gate openings1052A to form the structure ofFIGS.12A-12D. The vertical dimensions (e.g., spacing) of gate openings1052A-1052B along a Z-axis can be adjusted based on the thickness of nanostructured regions122B and120B removed from FETs102A-102B and/or by additional etching of nanostructured channel regions120B and122B after the formation of gate openings1052A-1052B, respectively. The vertical dimensions can be a value (e.g., from about 8 nm to about 12 nm) such that nanostructured channel regions120B and122B can be wrapped around by at least interfacial oxide layers127A-127B and gate dielectric layers128A-128B to fill gate openings1052A-1052B to prevent shorting between gate structures112A-112B and S/D regions126A-126B during operation of FETs102A-102B, respectively. In some embodiments, the vertical dimensions can be a value (e.g., from about 8 nm to about 12 nm) such that nanostructured channel regions120B and122B can be wrapped around by at least interfacial oxide layers127A-127B, gate dielectric layers128A-128B, gate WFM layers130A-130B to fill gate openings1052A-1052B to achieve ultra-low threshold voltage for FETs102A-102B, respectively. Referring toFIG.3, in operations325-345, gate-all-around (GAA) structures are formed on the nanostructured channel regions. For example, using the steps described in operations325-345, gate structures112A-112B can be formed wrapped around nanostructured channel regions120B and122B, respectively, as described with reference toFIGS.13A-17D and1A-1D. In operation325, interfacial oxide layers and a gate dielectric layer are deposited and annealed on the nanostructured channel regions. For example, interfacial oxide layers127A-127B and a gate dielectric layer128can be deposited and annealed on nanostructured channel regions120B and122B, respectively, as described with reference toFIGS.13A-14B. During subsequent processing, gate dielectric layer128can form gate dielectric layers128A-128B as shown inFIGS.1A-1D. Interfacial oxide layers127A-127B can be formed on exposed surfaces of nanostructured channel regions120B and122B within gate openings1052A-1052B, respectively. In some embodiments, interfacial oxide layers127A-127B can be formed by exposing nanostructured channel regions120B and122B to an oxidizing ambient. For example, the oxidizing ambient can include a combination of ozone (O3), a mixture of ammonia hydroxide, hydrogen peroxide, and water (SC1 solution), and/or a mixture of hydrochloric acid, hydrogen peroxide, water (SC2 solution). As a result of the oxidation process, oxide layers ranging from about 0.5 nm to about 1.5 nm can be formed on the exposed surfaces of nanostructured channel regions120B and122B. The deposition of gate dielectric layer128can include blanket depositing gate dielectric layer128on the partial semiconductor device100(not shown) formed after the formation of interfacial oxide layers127A-127B. The blanket deposited gate dielectric layer128can be substantially conformally deposited on interfacial oxide layers127A-127B and the exposed surfaces of the partial semiconductor device100(e.g., sidewalls of gate openings1052A-1052B and top surfaces of ILD118), as shown inFIGS.13A-13B. In some embodiments, gate dielectric layer128can include a dielectric material with a dielectric constant (k-value) higher than about 3.9. In some embodiments, gate dielectric layer128can include (i) silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, (iii) a high-k dielectric material having oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu, or (iv) a combination thereof. Gate dielectric layer128with high-k dielectric layer (e.g., HfO2) can be formed by ALD and/or other suitable methods. In some embodiments, gate dielectric layer128can be formed with ALD using hafnium chloride (HfCl4) as a precursor at a temperature ranging from about 250° C. to about 350° C. In some embodiments, gate dielectric layer128can have a thickness ranging from about 1 nm to about 3 nm in order to wrap around nanostructures channel regions120B and122B without being constrained by spacing between adjacent nanostructured channel regions120B and between adjacent nanostructured channel regions122B. The formation of interfacial oxide layers127A-127B and gate dielectric layer128can be followed by a three-stage annealing process to barrier layer (not shown) on gate dielectric layer128and to improve the electrical characteristics and/or reliability of interfacial oxide layers127A-127B and/or gate dielectric layer128. The first-stage annealing process can include sequential steps of (i) blanket depositing a metal nitride capping layer1354(FIGS.13A-13B) on gate dielectric layer128, (ii) in-situ blanket depositing a Si capping layer1356on metal nitride capping layer1354, and (iii) performing a first spike annealing process on the partial semiconductor device100(not shown) formed after the in-situ blanket deposition of Si capping layer1356. In some embodiments, metal nitride capping layer1354can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl4), silane (SiH4), and ammonia (NH3) as precursors at a temperature ranging from about 400° C. to about 500° C. Metal nitride capping layer1354can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer128during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer128. In some embodiments, the barrier layer can include hafnium titanium silicate (HfTiSiOx) with a thickness ranging from about 1 nm to about 3 nm. The barrier layer can be configured to prevent diffusion of elements (e.g., metals and oxygen) into interfacial oxide layers127A-127B and/or gate dielectric layer128from overlying layers during subsequent processing. The in-situ blanket deposition of Si capping layer1356can include an ALD, a CVD, or a PVD process. In some embodiments, the in-situ blanket deposition of Si capping layer1356can include a soaking process with TiCl4and SiH4gases at a temperature ranging from about 400° C. to about 500° C. The soaking process can include flowing TiCl4gas for a time period ranging from about 80 seconds to about 100 seconds and then flowing SiH4gas for a time period ranging from about 100 seconds to about 200 seconds on the surfaces of metal nitride capping layer1354. In some embodiments, Si capping layer1356can include Si or its compound and/or can include amorphous or polycrystalline Si. Si capping layer1356can prevent oxidation of interfacial oxide layers127A-127B and/or gate dielectric layer128and as a result, prevent additional growth of interfacial oxide layers127A-127B and/or gate dielectric layer128during subsequent annealing processes and/or ex-situ processes. The first spike annealing process can include performing an annealing process on the partial semiconductor device100(not shown) formed after the deposition of Si capping layer1356in a nitrogen ambient at an annealing temperature ranging from about 850° C. to about 900° C. for a time period ranging from about 1 second to about 5 seconds. According to some embodiments, the first spike annealing process can strengthen the chemical bonds at the interface between interfacial oxide layers127A-127B and gate dielectric layer128to improve the reliability of interfacial oxide layers127A-127B and/or gate dielectric layer128, and consequently, improve the reliability of gate structures112A-112B. The second-stage annealing process can include sequential steps of (i) ex-situ blanket depositing a Si capping layer1358(FIGS.13A-13B) on Si capping layer1356after the first spike annealing process and (ii) performing a second spike annealing process on the partial semiconductor device100(not shown) formed after the ex-situ blanket deposition of Si capping layer1358. The ex-situ blanket deposition of Si capping layer1358can include an ALD, a CVD, or a PVD process. In some embodiments, the ex-situ blanket deposition of Si capping layer1358can include depositing a silicon-based layer on Si capping layer1356by a CVD process using SiH4, disaline (Si2H6), and hydrogen at a temperature ranging from about 350° C. to about 450° C. Si capping layer1358can be deposited with a thickness (e.g., about 2 nm to about 5 nm) about 2 to about 5 times greater than the thickness of Si capping layer1356. The thicker Si capping layer1358can prevent oxidation of interfacial oxide layers127A-127B and/or gate dielectric layer128during the subsequent second annealing process, which is performed at a temperature higher than that of the first spike annealing process. The second spike annealing process can be performed in a nitrogen ambient at an annealing temperature ranging from about 900° C. to about 950° C. for a time period ranging from about 1 second to about 10 seconds. The third-stage annealing process can include sequential steps of (i) removing metal nitride layer1354, in-situ Si capping layer1356, and ex-situ Si capping layer1358after the second spike annealing process (FIGS.14A-14B) and (ii) performing a third spike annealing process on the structures ofFIGS.14A-14B. Metal nitride layer1354, in-situ Si capping layer1356, and ex-situ Si capping layer1358can be removed by a wet etching process. In some embodiments, the wet etching process can include etching in DHF, KOH solution, SC solution, or a combinations thereof. The third spike annealing process can be performed in an NH3ambient at an annealing temperature ranging from about 850° C. to about 950° C. The third spike annealing process can incorporate nitrogen into gate dielectric layer128to remove defects, such as oxygen vacancies from gate dielectric layer128and as a result, improve the reliability of gate structures112A-112B (shown inFIG.1A). In some embodiments, the annealing temperatures of the first and third spike annealing processes can be similar to or different from each other. In some embodiments, the annealing temperature of the second spike annealing process can be higher than the annealing temperatures of the first and third spike annealing processes. Referring toFIG.3, in operation330, an nWFM layer and a Si capping layer are selectively formed on the nanostructured channel regions of the NFET. For example, an nWFM layer130A* and Si capping layer131* can be selectively formed on nanostructured channel regions120B of FET102A, as described with reference toFIGS.15A-16B. During subsequent processing, nWFM layer130A* and Si capping layer131* can form nWFM layer130A and Si capping layer131as shown inFIGS.1A-1B and1D. The process for selectively forming nWFM layer130A* and Si capping layer131* on nanostructured channel regions120B can include sequential steps of (i) blanket depositing nWFM layer130A* (FIGS.15A-15B) on the structures ofFIGS.14A-14Bafter the third spike annealing process, (ii) blanket depositing Si capping layer131* (FIGS.15A-15B) on nWFM layer130A*, (iii) selectively forming a masking layer1560(e.g., a photoresist layer or a nitride layer) on the portion of Si capping131* of FET102A as shown inFIG.15B, (iv) selectively removing portions of nWFM layer130A* and Si capping131* of FET102B to form the structure ofFIG.16A, and (v) removing masking layer1560to form the structure ofFIG.16B. The blanket deposition of nWFM layer130A* can include blanket depositing about 1 nm to about 3 nm thick Al-based nWFM layer on gate dielectric layer128with an ALD or a CVD process using titanium tetrachloride (TiCl4) and titanium ethylene aluminum (TEAl) or tantalum chloride (TaCl5) and trimethylaluminium (TMA) as precursors at a temperature ranging from about 350° C. to about 450° C. In some embodiments, the Al-based nWFM layer can be deposited in an ALD process of about 4 cycles to about 12 cycles, where one cycle can include sequential periods of: (i) first precursor gas (e.g., TiCl4or TaCl5) flow, (ii) a first gas purging process, (iii) a second precursor gas (e.g., TEAl or TMA) gas flow, and (iv) a second gas purging process. In some embodiments, the Al-based nWFM layer can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), or a combination thereof. The blanket deposited nWFM layer130A* can be substantially conformally deposited (e.g., step coverage of about 99%) on gate dielectric layer128as shown inFIGS.15A-15B. In some embodiments, instead of blanket depositing the Al-based nWFM layer, a metallic layer (e.g., TiN, TiC, TaN, TaC) can be blanket deposited on gate dielectric layer128followed by a doping process with Al dopants to form nWFM layer130A*. The blanket deposition of Si capping layer131* can include blanket depositing about 0.5 nm to about 2 nm thick Si-based layer on nWFM layer130A* with a soaking process in an ALD or a CVD chamber using TiCl4and SiH4gases at a temperature ranging from about 300° C. to about 500° C. and pressure ranging from about 3 torr to about 30 torr. The soaking process can include flowing TiCl4gas for a time period ranging from about 80 seconds to about 100 seconds and then flowing SiH4gas for a time period ranging from about 100 seconds to about 200 seconds on the surfaces of nWFM layer130A*. In some embodiments, the Si-based layer can include Si or its compound and/or can include amorphous or polycrystalline Si. The blanket deposited Si capping layer131* can be substantially conformally deposited (e.g., step coverage of about 99%) on nWFM layer130A* as shown inFIGS.15A-15B. The selective formation of masking layer1560can include depositing and patterning a layer of photoresist or nitride on Si capping layer131* to form the structures ofFIGS.15A-15B. The selective removal of the portions of nWFM layer130A* and Si capping131* not protected by masking layer1560can include a wet etching process using etchants with a higher etch selectivity for nWFM layer130A* and Si capping131* than masking layer1560. In some embodiments, the etchants can include a mixture of ammonia hydroxide, hydrogen peroxide, and water (SC1 solution), and/or a mixture of hydrochloric acid, hydrogen peroxide, water (SC2 solution) and the etching time period can be about 2 min to about 5 min. Masking layer1560can be removed after the wet etching process to form the structure ofFIG.16B. Referring toFIG.3, in operation335, a bi-layer of pWFM layers are deposited on a portion of the gate dielectric layer of the PFET and on the Si capping layer of the NFET. For example, a bi-layer of pWFM layer130B1*-130B2* can be deposited partly on the portion of gate dielectric layer128of FET102B (FIG.17A) and partly on Si capping layer131* (FIG.17B) as described with reference toFIGS.17A-17B. During subsequent processing, the portions of pWFM layer130B1*-130B2* on gate dielectric layer128of FET102B can form pWFM layers130B1-130B2, respectively, as shown inFIGS.1A-1B and1Cand the portions of pWFM layer130B1*-130B2* on Si capping layer131* can form capping layers132A-132B, respectively, as shown inFIGS.1A-1B and1D. The deposition of the bi-layer of pWFM layer130B1*-130B2* can include sequential steps of (i) blanket depositing pWFM layer130B1* on the structures ofFIGS.16A-16Band (ii) blanket depositing pWFM layer130B2* on pWFM layer130B1*. The blanket deposition of pWFM layer130B1* can include blanket depositing about 1 nm to about 3 nm thick Al-free pWFM layer with an ALD or a CVD process using titanium tetrachloride (TiCl4) and NH3as precursors at a temperature ranging from about 350° C. to about 475° C. In some embodiments, the Al-free pWFM layer can be deposited in an ALD process of about 30 cycles to about 90 cycles, where one cycle can include sequential periods of: (i) first precursor gas (e.g., TiCl4) flow, (ii) a first gas purging process, (iii) a second precursor gas (e.g., NH3) gas flow, and (iv) a second gas purging process. In some embodiments, the Al-free pWFM layer can include substantially Al-free (e.g., with no Al) Ti-based nitrides or alloys. The blanket deposited pWFM layer130B1* can be substantially conformally deposited (e.g., step coverage of about 99%) on the structures ofFIGS.16A-16B. The blanket deposition of pWFM layer130B2* can include in-situ blanket depositing about 1 nm to about 3 nm thick Al-free pWFM layer with an ALD or a CVD process using pentakis-dimethylamino tantalum (PDMAT) and NH3as precursors at a temperature ranging from about 200° C. to about 300° C. The in-situ blanket deposition of pWFM layer130B2* can include performing the deposition in the same deposition chamber as pWFM layer130B1* and/or in the same integration module as pWFM layer130B1* without a vacuum break between the deposition of pWFM layers130B1* and130B2*. In some embodiments, the Al-free pWFM layer for pWFM layer130B2* can be deposited in an ALD process of about 20 cycles to about 50 cycles, where one cycle can include sequential periods of: (i) first precursor gas (e.g., PDMAT) flow, (ii) a first gas purging process, (iii) a second precursor gas (e.g., NH3) gas flow, and (iv) a second gas purging process. In some embodiments, the Al-free pWFM layer for pWFM layer130B2* can include substantially Al-free (e.g., with no Al) Ta-based nitrides or alloys. The blanket deposited pWFM layer130B2* can be substantially conformally deposited (e.g., step coverage of about 99%) on pWFM layer130B1* as shown inFIGS.16A-16B. Referring toFIG.3, in operation340, a fluorine blocking layer and a gate metal fill layer are deposited on the bi-layer of pWFM layers. For example, a fluorine blocking layer134can be deposited on pWFM layer130B2* and a gate metal fill layer135can be deposited on fluorine blocking layer134as described with reference toFIGS.17A-17B. During subsequent processing, fluorine blocking layer134and gate metal fill layer135can form fluorine blocking layers134A-134B and gate metal fill layers135A-135B, respectively, as shown inFIGS.1A-1B. The deposition of fluorine blocking layer134can include blanket depositing a fluorine-free metal layer (e.g., a FFW layer) on pWFM layer130B2*. The blanket deposition of fluorine-free metal layer can include blanket depositing about 2 nm to about 4 nm thick fluorine-free metal layer with an ALD or a CVD process using WCl5or WCl6and H2as precursors at a temperature ranging from about 400° C. to about 470° C. In some embodiments, the fluorine-free metal layer can be deposited in an ALD process of about 160 cycles to about 320 cycles, where one cycle can include sequential periods of: (i) first precursor gas (e.g., WCl5or WCl6) flow, (ii) a first gas purging process, (iii) a second precursor gas (e.g., H2) gas flow, and (iv) a second gas purging process. The blanket deposited fluorine blocking layer134can be substantially conformally deposited (e.g., step coverage of about 99%) on pWFM layer130B2*. The deposition of fluorine blocking layer134can be followed by the deposition of gate metal fill layer135on fluorine blocking layer134until gate openings1052A-1052B are filled as shown inFIGS.17A-17B. The deposition of gate metal fill layer135can include blanket depositing about 150 nm to about 200 nm thick metal layer with a CVD process using WCl5or WCl6and H2as precursors at a temperature ranging from about 300° C. to about 400° C. Referring toFIG.3, in operation345, the gate dielectric layer, nWFM layer, Si capping layer, pWFM layers, fluorine blocking layer, and gate metal fill layer are polished. For example, gate dielectric layer128, nWFM layer130A*, Si capping layer131*, pWFM layers130B1*-130B2*, fluorine blocking layer134, and gate metal fill layer135can be polished by a chemical mechanical polishing process to substantially coplanarize top surfaces of gate dielectric layer128, nWFM layer130A*, Si capping layer131*, pWFM layers130B1*-130B2*, fluorine blocking layer134, and gate metal fill layer135with top surface of ILD layer118as shown inFIGS.1A-1D. As a result of the polishing process, gate structures112A-112B can be formed as shown inFIGS.1A-1D. Thus, as described in operations325-345, gate structures112A-112B can be formed using an nWFM-first scheme in which Al-based nWFM layer (e.g., nWFM layer130A*) can be formed prior to the formation of Al-free pWFM layers (e.g., pWFM layers130B1*-130B2*) to prevent or substantially reduce contamination of the Al-free pWFM layers with Al from the Al-based nWFM layer. The formation of gate structures112A-112B can be followed by formation of other elements such as S/D contacts, gate contacts, vias, interconnect metal layers, dielectric layers, passivation layers, etc., which are not shown for the sake of clarity. The present disclosure provides example structures of FETs (e.g., FETs102A-102B) with different gate structures (e.g., gate structures112A-112B) configured to provide ultra-low threshold voltages and example methods of forming such FETs on a same substrate (e.g., substrate106). The example methods form FETs of different conductivity types with different work function values, and as a result, with different and/or ultra-low threshold voltages on the same substrate. These example methods can be less complicated and more cost-effective in manufacturing reliable gate structures in FETs with nanostructured channel regions and with ultra-low threshold voltages than other methods of forming FETs with similar channel dimensions and threshold voltages on the same substrate. In addition, these example methods can form FET gate structures with smaller dimensions (e.g., thinner gate stacks) than other methods of forming FETs with similar threshold voltages. For example, using these example methods, the thicknesses of gate stack layers can be reduced by about 50% to about 75% compared to the thicknesses of gate stack layers formed using the other methods. In some embodiments, NFETs (e.g., FET102A) and PFETs (e.g., FET102B) with different gate stack layer configurations can be selectively formed on the same substrate. To achieve NFETs and PFETs with ultra-low threshold voltages, NFETs and PFETs can include Al-based NFET gate stacks and substantially Al-free (e.g., with no Al) PFET gate stacks, respectively. The NFET and PFET gate stacks can have nWFM layers (e.g., nWFM layer130A) and pWFM layers (e.g., pWFM layers130B1-130B2) in physical contact with gate dielectric layers (e.g., gate dielectric layers128A-128B) of the NFETs and PFETs, respectively. The NFET gate stacks can include Al-based nWFM layers (e.g., Al-based titanium (Ti) or tantalum (Ta) alloys) and the PFET gate stacks can include substantially Al-free (e.g., with no Al) pWFM bi-layers (e.g., Al-free Ti and Ta nitrides or alloys) with thicknesses smaller than about 3 nm (e.g., about 0.5 nm to about 3 nm) to achieve ultra-low threshold voltages. In some embodiments, TaN of the pWFM bi-layers can prevent underlying layers from being etched during subsequent processing (e.g., deposition of fluorine-free tungsten (FFW) layer) and protect the integrity of the pWFM layers, thus improving the reliability of PFET gate structures. In some embodiments, the reliability of the NFET gate structures can be improved with the selective formation of Si capping layers on the Al-based nWFM layers. The Si capping layers can prevent the oxidation of the Al-based nWFM layers and as a result, prevent an increase in work function values of the Al-based nWFM layers. In some embodiments, a method of fabricating a semiconductor device includes forming first and second stacks of first and second nanostructured layers arranged in an alternating configuration on a substrate, growing first and second epitaxial regions of opposite conductivity type on the first and second stacks, respectively, forming first and second nanostructured channel regions in the first and second nanostructured layers of the first and second stacks, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes depositing a gate dielectric layer surrounding the first and second nanostructured channel regions, selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer. In some embodiments, a method of fabricating a semiconductor device includes forming first and second stacks of first and second nanostructured layers arranged in an alternating configuration on a substrate, growing first and second epitaxial regions of opposite conductivity type on the first and second stacks, respectively, forming first and second nanostructured channel regions in the first and second nanostructured layers of the first and second stacks, respectively, depositing a gate dielectric layer on the first and second nanostructured channel regions, forming a barrier layer on the gate dielectric layer, selectively forming an n-type work function metal layer and a capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, and depositing a gate metal fill layer on the bi-layer of Al-free p-type work function layers. In some embodiments, a semiconductor device includes a substrate, first and second stacks of first and second nanostructured layers arranged in an alternating configuration on the substrate, first and second nanostructured channel regions in the first and second nanostructured layers of the first and second stacks, respectively, and first and second gate dielectric layers wrapped around the first and second nanostructured channel regions, respectively, an Al-based n-type work function metal layer in physical contact with the first gate dielectric layer, a Si-based capping layer on the Al-based n-type work function metal layer, first and second bi-layers of Al-free p-type work function metal layers in physical contact with the second gate dielectric layer and the Si-based capping layer, respectively, first and second fluorine blocking layers on the first and second bi-layers of p-type work function layers, and first and second gate metal fill layers on the first and second fluorine blocking layers. The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 92,012 |
11862682 | DETAILED DESCRIPTION Hereinafter, example embodiments of inventive concepts will be described as follows with reference to the accompanying drawings. FIG.1is a plan view illustrating a semiconductor device according to an example embodiment of inventive concepts,FIG.2is a cross-sectional view taken along line I-I′ of the semiconductor device ofFIG.1, andFIG.3is an enlarged view illustrating region A of the semiconductor device illustrated inFIG.2. Referring toFIGS.1and2, a semiconductor device100according to an example embodiment of inventive concepts may include a protruding portion104defining an active region on the substrate101, and a plurality of gate electrodes130disposed to cross the protruding portion104. The protruding portion104may extend in a first direction (e.g., X direction). The plurality of gate electrodes130may extend in a second direction (e.g., Y direction) crossing the first direction. Embedded source/drain regions107may be disposed on both sides of the plurality of gate electrodes130. The source/drain regions107may be referred to as source/drain structures107. A plurality of channel layers120penetrating through the plurality of gate electrodes130in the first direction may be disposed between the source/drain regions107. The plurality of gate electrodes130may be formed to respectively surround the plurality of channel layers120. Referring toFIGS.2and4, the semiconductor device100according to an example embodiment of inventive concepts may include a substrate101, an isolation insulating layer103, a source/drain region107, a gate insulating film110, a gate electrode130, a gate spacer140, a gate cap layer150, and an interlayer insulating layer165. The substrate101may be a semiconductor substrate. The semiconductor substrate may include a group IV semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. The substrate101may be a semiconductor on insulator (SOI) substrate (e.g., silicon on insulator). The substrate101may include a protruding portion104having a fin shape extending in the first direction. The isolation insulating layer103may be disposed on the substrate101to cover a side surface of the protruding portion104of the substrate101. An upper surface of the isolation insulating layer103may be lower than the upper surface of the protruding portion104. An upper portion of the protruding portion104may protrude further than the upper surface of the isolation insulating layer103. The protruding portion104may also be referred to as an “active region.” The plurality of channel layers120extending in the first direction on the protruding portion104may be disposed to be spaced apart in a third direction (e.g., Z direction) perpendicular to the upper surface of the substrate101. In the example embodiment, the channel layers120are illustrated as three, but the number thereof is not particularly limited. The channel layers120may be formed of semiconductor patterns. For example, the semiconductor patterns may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The source/drain region107may be disposed in regions of protruding portion104located on both sides of the gate electrodes130. The source/drain regions107may be respectively connected to the channel layers120. The gate electrode130may surround the plurality of channel layers120, and may extend in a second direction (e.g., Y direction) crossing the first direction (e.g., X direction). A gate insulating film110is disposed between the gate electrode130and the plurality of channel layers120. Specifically, as illustrated inFIG.4, the gate electrode130may be formed to surround the channel layers120, and may also be disposed on the upper surface of the protruding portion104and on the upper surface of the isolation insulating layer103in the second direction. In addition, a gate cap layer150may be disposed on the upper surface of the gate electrode130, and gate spacers140may be disposed on side surfaces of the gate electrode130. The gate insulating film110may be interposed between each of the channel layers120and the gate electrode130, and may surround outer surfaces of each of the channel layers120. The gate insulating film110and the gate electrode130may be disposed between the channel layers120to isolate the channel layers120from each other, and the channel layers120may be surrounded by the gate insulating film110and the gate electrode130. The channel layers120may have a sheet shape that is wider than the thickness thereof. In the example embodiment, edges of the plurality of channel layers120are illustrated as having an angular shape, but are not limited thereto. The edges of the plurality of channel layers120may have a curvature. In some other example embodiments, the plurality of channel layers120may have a wire structure having a circular cross-section or an elliptical cross-section. The gate insulating film110may extend along a bottom surface of the gate electrode130, and may be interposed between the gate electrode130and the protruding portion104(the active region) and between the gate electrode130and the isolation insulating layer103, respectively. As described above, the gate electrode130, the channel layers120, and the source/drain region107may constitute a gate-all-around type electric field transistor. The gate electrode130may include a doped semiconductor, a conductive metal nitride, and/or a metal. For example, the gate electrode130may include metal nitrides such as TiN, WN, and TaN and/or metals such as Ti, W, and Ta. The high dielectric film may include a material having a higher dielectric constant than the silicon oxide film, such as a hafnium oxide (HfO) film, an aluminum oxide (AlO) film, or a tantalum oxide (TaO) film. Each of the gate spacer140and the gate cap layer150may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In a cross-section illustrated inFIG.2, the gate electrode130has portions130A and130B located on an uppermost channel layer120T of the plurality of channel layers120and a portion130C disposed between the plurality of channel layers120. The portions130A and130B located on the uppermost channel layer120T have the portion130B overlapping the source/drain region107in the first direction. FIG.3is an enlarged view illustrating portion A ofFIG.2. Referring toFIG.3, an upper surface of the source/drain region107may be located at a level LSD, higher than a level LGof a surface in which the gate electrode130contacts an upper surface of an uppermost channel layer120T. The overlapped portion130B of the gate electrode130has a side surface130S inclined toward the upper surface of the substrate101. In some embodiments, an inclined angle θ of the inclined side surface130S may be in a range of 50° to 80° based on the upper surface of the substrate101. For example, the gate electrode130has a cross-section shape in which a width (Wa) of a surface, in contact with the upper surface of the uppermost channel layer120T is smaller than a width (Wb) at the same level as the upper surface of the source/drain region107. Meanwhile, a side surface of the second portion130B of the gate electrode130may have an inclined plane or a curved surface. In addition, as illustrated inFIG.3, the gate insulating film110may extend to a point between the second portion130B located on the uppermost channel layer120T of the gate electrode130and the source/drain region107. As described above, the gate electrode130according to the present embodiment has an innate cross-sectional shape (e.g., inclined plane or curved surface at the second portion130B) when viewed in the cross-section in the first direction. As a result, deviations between the channel length (or a width) of the uppermost channel layer120T and the channel length (or a width) of another adjacent channel layer120may be greatly reduced. Referring toFIG.2, although the plurality of channel layers120are shown to have substantially similar lengths, some channel layers120may actually have different lengths according to their positions. For example, in the recess formation (or expansion) process for the source/drain region107(see.FIG.11), since an undercut C is formed in an upper region of the nanosheet structure, the uppermost channel layer thereof may have a relatively large width with an adjacent channel layer when the channel layer is disposed as an uppermost layer. As described above, when the deviation in the channel length is large, the deviation in strain due to the source/drain region107and deviation in the degree of dopant diffusion in the source/drain region107occur more, which may cause deterioration of the device performance. However, according to the example embodiment, since the uppermost channel layer120T is not located on an uppermost portion of the nanosheet structure, and the second portion130B of the gate electrode130is formed at the position thereof, deviation in the channel length may be reduced, and uniform performance of the channel layers120may be guaranteed. For example, in the cross-section in the first direction, the width of the uppermost channel layer120T according to the present embodiment may have deviation of 20% or less from the width of another adjacent channel layer120, and the performance deviation according to the channel length may be greatly reduced. In another aspect, the source/drain region107may have a side surface that is inclined to be in contact with the second portion130B of the gate electrode. In some example embodiments, side surfaces of the source/drain regions107may also have inclined planes or curved surfaces similar to the side surfaces of the second portion130B of the gate electrode130. The source/drain region107may include first and second epitaxial regions107aand107bhaving different compositions from each other. For example, the first and second epitaxial regions107aand107binclude SiGe having different germanium (Ge) contents, and the Ge content of the second epitaxial region107bmay be higher than the Ge content of the first epitaxial region107a. In another example embodiment, it may be divided into three or more epitaxial regions, and may be deposited to gradually increase the germanium content. Although the upper surfaces of the source/drain regions107are illustrated as being formed at a higher level than the second portion of the gate electrode, inventive concepts is not limited thereto. The upper surfaces of the source/drain regions107may be formed to be higher than the upper surface of the uppermost channel layer120T such that the source/drain regions107are respectively connected to all the channel layers120. The upper surface of the source/drain region107may be formed to have a convex curved surface, but is not limited thereto. The gate electrode130may be disposed between the source/drain regions107, and may extend in a second direction (e.g., Y axis direction) crossing the first direction on the substrate101. The gate electrode130and the source/drain regions107may be insulated by the gate insulating film110. The gate electrode130may be formed to surround the channel layers120. The gate insulating film110may be disposed between the gate electrode130and the channel layers120and between the gate electrodes130and the gate spacers140. The gate electrode130may also be formed on the isolation insulating film103. The gate insulating film110may also be disposed between the gate electrode130and the isolation insulating layer103. Gate spacers140extending in the same direction as the gate electrode130may be disposed on both sidewalls of the gate electrode130. The gate spacers140may be formed of silicon oxynitride (SiON), silicon nitride (SiN), SiOC, SiOCN, SiBCN, or a combination thereof. A gate cap layer150for protecting the gate electrode may be disposed on the gate electrode130. The gate cap layer150may include silicon nitride. Referring toFIG.3, the gate insulating film110may include a plurality of layers. In an example embodiment, the gate insulating film110may include a first insulating layer111and a second insulating layer112. The first insulating layer111and the second insulating layer112may have different dielectric constants, and the dielectric constant of the second insulating layer112may be greater than the dielectric constant of the first insulating layer111. In this case, the second insulating layer112may be disposed closer to the channel layer120than the first insulating layer111. That is, the first insulating layer111may be disposed closer to the gate electrode130than the second insulating layer112. Meanwhile, the second insulating layer112having a relatively higher dielectric constant may have a larger thickness than the first insulating layer111. The second insulating layer112having a relatively high dielectric constant may include a high dielectric constant dielectric material. The high dielectric constant dielectric material may be aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), It may be any one of hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), praseodymium oxide (Pr2O3), or a combination thereof. All of the plurality of metal layers included in the gate electrode130may be disposed between the channel layers120. A barrier metal layer131may be disposed adjacent to the gate insulating film110, a work function metal layer132may be disposed on the barrier metal layer131, and a gate metal layer133may be disposed on the work function metal layer132. In some example embodiments, some layers may be omitted or added. For example, a space between the channel layers120may only be filled with the barrier metal layer131and the work function metal layer132together with the gate insulating film110. The barrier metal layer131may include metal nitrides such as TiN, TaN, TaSiN, TiSiN, and the like. The work function metal layer132may determine a threshold voltage of the semiconductor device100. In some embodiments, the work function metal layer132may include a plurality of metal layers stacked to each other. For example, the work function metal layer132may include ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof. The gate metal layer133may be formed of a metal material such as tungsten. An interlayer insulating layer165may cover embedded source/drain regions107. An upper surface of the interlayer insulating layer165may form a coplanar surface with an upper surface of the gate cap layer150. The interlayer insulating layer165may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low dielectric film. The upper surface of the gate cap layer150may be substantially coplanar with an upper surface of the interlayer insulating layer165. The gate spacers140may be interposed between the gate cap layer150and the interlayer insulating layer165. Contact plugs175respectively connected to the source/drain regions107may be provided through the interlayer insulating layer165. The contact plugs175may be in contact with the source/drain regions107. A conductive barrier171may be formed on surfaces of the contact plugs175. The contact plugs175may be recessed in the source/drain region107to overlap the uppermost channel layer120T of the plurality of channel layers120in the first direction. For example, the conductive barrier171may be formed of a metal nitride such as TiN, TaN, or WN. The contact plug175may be formed of tungsten (W), cobalt (Co), titanium (Ti), an alloy thereof, or a combination thereof. FIG.5is a plan view illustrating a semiconductor device according to an example embodiment. Referring toFIG.5, it may be understood that a semiconductor device100A according to an example embodiment is similar to the semiconductor device100illustrated inFIGS.1to4, except that internal spacers106are formed on both sides of the channel layers CH. In addition, the components of the example embodiment may be understood with reference to the descriptions of the same or similar components of the semiconductor device100illustrated inFIGS.1and2unless specifically described otherwise. In the semiconductor device100A according to the example embodiment, internal spacers106disposed on both sides of the gate electrode130in the first direction (e.g., X direction) between the plurality of channel layers120may be further included. The internal spacers106may be disposed between the gate electrode130and source/drain region107. For example, the internal spacers106may include at least one selected from a group consisting of SiN, SiCN, SiON, SiBN, SiOCN, SiBCN, and SiOC. The internal spacers106may be formed after the recess formation (the process ofFIG.10) and before the epitaxial growth (the process ofFIG.12) in the process of forming the source/drain region107among processes to be described later. Specifically, the internal spacers106may be formed by partially etching sacrificial patterns160after the recess formation and before the epitaxial growth, and depositing an insulator in the etched space. In this process, both sides of the portion of the gate electrode130located on the uppermost channel layer120T may also be exposed by the recess and etched to form internal spacers106T, as illustrated inFIG.5. Since the internal spacers106T are formed along the inclined surface, the internal spacers106T may have a shape different from that of the internal spacers106of the other channel layers120. FIGS.6to15are cross-sectional views illustrating processes for manufacturing the semiconductor device ofFIG.1. Specifically,FIGS.6,8,10to15are cross-sectional views taken along line I-I′ ofFIG.1, andFIGS.7and9are cross-sectional views taken along line II-II′ ofFIG.1. Referring toFIG.6, a plurality of sacrificial layers160′ and a plurality of semiconductor layers120′ may be alternately stacked on the substrate101. A stacked structure in which the plurality of sacrificial layers160′ and the plurality of semiconductor layers120′ are alternately disposed may be formed on the substrate101such that the sacrificial layer160is located on the uppermost portion thereof. The stacked structure employed in the example embodiment is illustrated as including four sacrificial layers160′ and three semiconductor layers120′, but is not limited thereto. The plurality of semiconductor layers120′ may include a semiconductor material, and the plurality of sacrificial layers160′ may include a semiconductor material having etch selectivity with the plurality of semiconductor layers120′. For example, the plurality of semiconductor layers120′ may include silicon (Si), and the plurality of sacrificial layers160′ may include silicon-germanium (SiGe). The plurality of sacrificial layers160′ may be silicon-germanium having a germanium content of 30% or more and less than 100%. Thicknesses of the plurality of semiconductor layers120′ and the plurality of sacrificial layers160′ may be variously changed according to example embodiments. The thicknesses of the plurality of semiconductor layers120′ and the thicknesses of the plurality of sacrificial layers160′ may be several nm to several tens of nm, respectively. For example, the thicknesses of the plurality of sacrificial layers160′ may be greater than the thicknesses of the plurality of semiconductor layers120′. Subsequently, referring toFIG.7, a fin structure FS may be formed by selectively removing portions of the plurality of semiconductor layers120′ and the plurality of sacrificial layers160′ on the substrate101. The fin structure FS may extend in a first direction (e.g., X direction) on the substrate101. The fin structure FS may be formed by applying an anisotropic etching process using a mask pattern to the stacked structures of the plurality of semiconductor layers120′ and the plurality of sacrificial layers160′. In a process of forming the fin structure FS, a portion of the substrate101may be removed to form a protruding portion104on the substrate101. The protruding portion104of the substrate101may form the fin structure FS together with the plurality of semiconductor layers120′ and the plurality of sacrificial layers160′. An isolation insulating layer103may be formed in a region in which a portion of the substrate101is removed. The isolation insulating layer103may partially cover a side surface of the protruding portion104. An upper surface of the isolation insulating layer103may be formed to be lower than the upper surface of the protruding portion104on the substrate101. That is, the protruding portion104on the substrate101may protrude above the isolation insulating layer103. After the fin structure FS and the isolation insulating layer103are formed, the mask pattern may be removed. Next, referring toFIGS.8and9, a dummy gate pattern DG crossing the fin structure FS may be formed. A cap layer135may be further formed on the dummy gate pattern DG. Gate spacers140and sacrificial spacers142may be formed on both sidewalls of the dummy gate pattern DG. An etch stop layer128may be disposed between the dummy gate pattern DG and the fin structure FS. The dummy gate pattern DG may extend in a second direction (e.g., Y direction). The etch stop layer128, the gate spacers140, and the sacrificial spacers142may extend in the same direction as the dummy gate pattern DG. The dummy gate pattern DG and the etch stop layer128may cover the fin structure FS protruding onto the isolation insulating layer103. The dummy gate pattern DG may be formed of a semiconductor material such as polysilicon. The gate spacers140may be formed of silicon oxynitride (SiON), silicon nitride (SiN), SiOC, SiOCN, SiBCN, or a combination thereof. The etch stop layer128may be formed of at least one layer selected from silicon oxide, silicon nitride, and silicon oxynitride. Subsequently, referring toFIG.10, first recesses R1may be formed in some regions of the fin structure FS located on both sides of the dummy gates DG. The present process may be performed by applying an anisotropic dry etching process using the capping layer135, the dummy gate pattern DG, and the gate spacers140as an etching mask. Some exposed regions of the fin structure FS may be selectively removed to form first recesses R1. A plurality of channel layers120may be formed below the dummy gate pattern DG by the anisotropic dry etching process. Further, a plurality of sacrificial patterns160may be formed between the plurality of channel layers120. A portion of the upper surface of the substrate101may be exposed by the first recesses R1. A portion of the upper surface of the substrate101may be etched by the anisotropic dry etching process. Next, referring toFIG.11, the first recesses R1may be expanded using an isotropic dry etching process. The first recesses R1located on both sides of the dummy gate pattern DG may be expanded below the gate spacer140and the sacrificial spacer142by an isotropic etching process to form second recesses R2. In addition, the second recesses R2may be obtained by additionally etching the upper surface of the exposed substrate101. In the present process, an upper region C of the fin structure FS, that is, an uppermost sacrificial pattern160T may have inclined side surfaces. On the other hand, the uppermost channel layer120T of the plurality of channel layers120is not located in the inclined upper region C, and thus the uppermost channel layer120T may be formed to have a relatively flat side surface and/or to have a length similar to the length of another adjacent another channel layer120. Subsequently, referring toFIG.12, source/drain regions107may be formed from the upper surface of the substrate101using a selective epitaxial growth (SEG) process in the expanded second recess R2. Sacrificial spacers142may be removed by a precleaning process. Before forming embedded source/drain regions107, source/drain regions107may be formed through selective epitaxial growth in the second recesses R2. The source drain regions107may include a plurality of epitaxial regions having different compositions. For example, in the source/drain regions107, the first and second epitaxials107aand107bmay include SiGe having different Ge contents, and the Ge content of the second epitaxial107bmay be higher than the Ge content of the first epitaxial107a. In some example embodiments, the source/drain regions107may be configured to provide tensile strain in the channel layers CH. For example, when the channel layers CH include silicon Si, the source/drain region SD may include silicon (Si) and/or silicon carbide (SiC). In other example embodiments, the source/drain region SD may be configured to provide compressive strain to the channel layers CH. For example, when the channel layers CH include silicon (Si), the source/drain region SD may include silicon germanium (SiGe). The source/drain region SD may further include a dopant. The dopant may be employed to improve electrical characteristics of the transistor including the source/drain region SD. When the transistor TR is an N-MOSFET, an example of the dopant may be phosphorus (P). When the transistor TR is a P-MOSFET, an example of the dopant may be boron (B). It may be doped with a particular conductive-type dopant. For example, when doped with a p-type dopant, the p-type dopant may be implanted in situ during the selective epitaxial growth process or by a subsequent ion implantation process. Next, referring toFIG.13, a dummy gate pattern DG and an etch stop layer128may be removed to form a first opening OPa. Before forming the first opening OPa, an interlayer insulating layer165covering the dummy gate pattern DG may be formed. The interlayer insulating layer165may be formed outside of the gate spacer140to cover the source/drain regions107. The interlayer insulating layer165may be formed by a process of applying an insulating material and a planarization process. The capping layer135may be removed by the planarization process, and the dummy gate pattern DG may be exposed. The dummy gate pattern DG and the etch stop layer128may be sequentially removed by selective etching. Subsequently, referring toFIG.14, a plurality of sacrificial patterns160may be selectively removed to form second and third openings OPb and OPc. The second opening OPb is a region from which an uppermost sacrificial pattern160T is removed, and the third opening OPc is a region from which the sacrificial patterns160located between the plurality of channel layers120are removed. Since the second opening OPb corresponds to an inclined upper region, the second opening OPb has a width greater than a width of the third opening OPc while having the inclined side surface. The second and third openings OPb and OPc may be connected to the first opening OPa to form one opening OP. For example, a plurality of channel layers120may include Si, and a plurality of sacrificial patterns160may include SiGe. In order to selectively remove the plurality of sacrificial patterns160, an etchant having a greater etching rate of SiGe than Si may be used. For example, an etchant containing hydrogen peroxide (H2O2), hydrofluoric acid (HF) and acetic acid (CH3COOH), an etchant containing ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and deionized water (H2O), and an etchant containing peracetic acid, or a combination thereof may be used. Next, referring toFIG.15, a gate insulating film110and a gate electrode130are formed in the opening OP. As described above, the opening OP may include a first opening OPa positioned between the gate spacers140, a second opening OPb positioned on an uppermost channel layer120T below the first opening OPa, and a third opening OPc positioned between the plurality of channel layers. In the present process, the gate insulating film110may be conformally formed on the exposed surfaces of the opening OP. A gate insulating film110may be formed to surround each of the channel layers120. In addition, it may be conformally formed on both sidewalls of the gate spacer140exposed to the first opening OPa, a portion of surfaces of the source/drain region107exposed to the second opening OPb and an upper surface of the uppermost channel layer120T. The exposed surface of the source/drain region107has an inclined surface. Subsequently, the gate electrode130is formed on the gate insulating film110to extend in the second direction (e.g., Y direction). Specifically, the gate electrode130may be formed to fill the first and second openings OPa and OPb and the third opening OPc between the plurality of channel layers120. The gate insulating film110may include a high dielectric material having a higher dielectric constant than that of the silicon oxide film. For example, the gate insulating film110may include one or more of a hafnium oxide, a hafnium silicon oxide, a lanthanum oxide, a lanthanum aluminum oxide, a zirconium oxide, a zirconium silicon oxide, a tantalum oxide, a titanium oxide, a barium strontium titanium oxide, a barium titanium oxide, a strontium titanium oxide, a yttrium oxide, an aluminum oxide, a lead scandium tantalum oxide, or a lead zinc niobate, but are not limited thereto. The gate electrode130may include a conductive material. For example, the gate electrode130may include at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, and Al. The gate electrode130is illustrated as a single layer, but is not limited thereto. For example, as described above, the gate electrode130may include a work function conductive layer for adjusting a work function and a conductive layer filling a spaced formed by the work function conductive layer for adjusting a work function. FIG.16is a plan view illustrating a semiconductor device according to an example embodiment of inventive concepts. Referring toFIG.16, it can be understood that a semiconductor device100B according to the example embodiment is similar to the semiconductor device100illustrated inFIGS.1to4except that a silicon cap layer125is interposed in upper regions130A and130B of the gate electrode130. In addition, the components of the example embodiment may be understood with reference to the descriptions of the same or similar components of the semiconductor device100illustrated inFIGS.1and2unless specifically described otherwise. The gate electrode130has first and second portions130A and130B positioned on the uppermost channel layer120T of the plurality of channel layers120, similarly to the previous example embodiment. The second portion130B is defined as a portion overlapping the source/drain region107in the first direction (e.g., X direction), and the first portion130A may be disposed on the second portion130B. The semiconductor device100B according to the example embodiment may further include a semiconductor cap layer125disposed between the first portion130A and the second portion130B of the gate electrode130. The semiconductor cap layer125may be obtained by forming the semiconductor cap layer similar to the semiconductor layer120′ on the sacrificial layer160′ as a protective layer in the process ofFIG.6. For example, the semiconductor cap layer125may include the same silicon as the semiconductor layer120′, but in a final structure, the semiconductor cap layer125may be formed to have a relatively thin thickness to serve as a protective layer for protecting the sacrificial layer without serving as a channel layer. A thickness t1of the semiconductor cap layer125may be formed to be thinner than a thickness t2of the semiconductor layer120. For example, the thickness t1of the semiconductor cap layer125may be formed to be 50% or less of the thickness t2of the semiconductor layer120. As illustrated inFIG.16, in the cross-section along the first direction (e.g., X direction), the second portion130bof the gate electrode130has an inclined side surface toward the upper surface of the substrate101. In addition, the gate insulating film110may be disposed between the gate electrode130and the channel layers120, as well as between the gate electrode130and the semiconductor cap layer125. The upper surface of the source/drain region107may be formed to have a level of or lower than the upper surface of the second portion130bof the gate electrode130. Therefore, the semiconductor cap layer125may not be connected to the source/drain region107, and as a result, it may not act as a channel layer. As set forth above, according to an embodiment of inventive concepts, by reducing a difference in channel lengths of channel layers, it is possible to reduce strain variation and/or dopant diffusion variation due to an epitaxial of the source/drain region. Various and advantageous advantages and effects of inventive concepts is not limited to the above description, it will be more readily understood in the process of describing the specific embodiments of inventive concepts. While the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of inventive concepts as defined by the appended claims. | 33,427 |
11862683 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are disposed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The term “nominal” as used herein refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes and/or tolerances. In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. It is to be understood that the terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein. . Ultra-thin fin structures—e.g., with an average width between about 5 nm and about 15 nm—used in fin field-effect transistors (finFETs) provide improved gate control over the channel region and alleviate issues related to short-channel effects. For these reasons, ultra-thin fin structures are attractive for finFETs. However, the aforementioned benefits of the ultra-thin fin structures are compromised by their limited saturation current—e.g., due to their reduced width—and lack of structural rigidity compared to thicker fin structures (e.g., thicker than about 20 nm). For example, ultra-thin fin structures can be susceptible to bending or collapsing under mechanical stress originating from the surrounding layers (e.g., dielectrics) and/or subsequent fabrication operations—e.g., densification processes that cause stress build up near the ultra-thin structures. To address the aforementioned challenges, this disclosure is directed to a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity while maintaining desirable gate control characteristics. In some embodiments, silicon and silicon-germanium (SiGe) ultra-thin fins can be fabricated using the methods described herein. Further, SiGe fins with a Ge variable concentration and a tapered bottom profile can be formed in p-type finFETs for improved gate control over the channel and interface quality between the ultra-thin fin structure and the gate dielectric stack. According to some embodiments,FIG.1Ais a partial isometric view of ultra-thin fin structures100(fin structures100) having a bottom tapered profile105which substantially improves the structural stiffness of fin structures100. In some embodiments, fin structures100are formed on pedestal structures110of substrate115prior to the formation of a gate stack not shown inFIG.1. Fin structures100have a top width W between about 5 nm and about 15 nm and a total height H between about 40 nm and about 70 nm. Height H of each fin structure100is measured from the interface between fin structure100and pedestal structure110of substrate115and includes height B, which corresponds to the total height of bottom tapered profile105, and height A—the height of fin structure100above bottom tapered profile105. In some embodiments, height H is substantially equal to the sum of heights A and B (e.g., H=A+B) as shown inFIG.1A. In some embodiments, height A is between about 80% and about 90% of height H (e.g., 80% H≤A≤90% H) and height B is between about 10% and about 20% of height H (e.g., 10% H≤B≤20% H). For example, if H is between about 40 nm and about 70 nm, height A is between about 32 nm and about 63 nm and height B (e.g., the height of bottom tapered profile105) is between about 4 nm and about 14 nm. In some embodiments, if height B is less than about 10% of height H, bottom tapered profile105may not be sufficiently thick to structurally support fin structure100. For example, if height B is less than about 10% of height H, fin structure100may become susceptible to bending or collapsing. On the other hand, if height B is larger than about 20% of height H (e.g., if bottom tapered profile105occupies a larger portion of fin structure100), then the channel control in the vicinity of bottom tapered profile105may be limited. Therefore, the size of bottom tapered profile105in fin structure100(e.g., height B), needs to be tailored so that fin structures100exhibit an optimal balance between mechanical stiffness and electrical performance. As shown inFIG.1A, fin structures100are isolated by an isolation material120which includes a dielectric material such as silicon oxide, carbon containing silicon oxide, hydrogen and nitrogen containing silicon oxide, or any other suitable dielectric material or layers. Pedestal structures110can be formed from substrate115and can include one or more doped regions not shown inFIG.1A. For example, a top portion of pedestal structure110(e.g., below bottom tapered profile105) can be doped with n-type or p-type dopants to prevent leakage current between fin structures100and substrate115during the finFET operation. In some embodiments, substrate115is a bulk semiconductor wafer or a top layer of a semiconductor on insulator (SOI) wafer such as, for example, silicon on insulator. Further, substrate115can be made of silicon or another elementary semiconductor such as, for example, (i) germanium (Ge); (ii) a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); (iii) an alloy semiconductor including gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP); or (iv) combinations thereof. In some embodiments, substrate115has a crystalline microstructure—e.g., it is not amorphous or polycrystalline. For example purposes, substrate115and pedestal structures110will be described in the context of crystalline silicon (Si) with their top surface parallel to the (100) crystal plane. Based on the disclosure herein, other materials, as discussed above, or crystalline orientations can be used. These materials are within the spirit and scope of this disclosure. According to some embodiments, bottom tapered profile105of fin structures100is formed above the top surface of isolation material120as shown inFIG.1A In some embodiments, fin structures100can include a single epitaxial layer or a stack of epitaxial layers. For example, fin structures100can include a single Si epitaxial layer125as shown inFIG.1A, a single SiGe epitaxial layer130as shown inFIG.1B, or a stack of SiGe epitaxial layers135,140, and145shown inFIG.1C. In some embodiments, fin structures100with single silicon epitaxial layer125shown inFIG.1Aare suitable for n-type finFETs (e.g., nFETs). Fin structures100with single SiGe epitaxial layer130or a stack of SiGe epitaxial layers135,140, and145shown inFIGS.1B and1Care suitable for p-type finFETs (pFETs). In some embodiments, fin structures100for both nFETs and pFETs as shown inFIGS.1A-Ccan be formed on the same substrate (e.g., substrate115) with the methods described herein. In some embodiments, fin structures100are pFET fin structures made from single SiGe epitaxial layer130, as shown inFIG.1B, have a Ge atomic concentration (at. %) that varies as a function of height H. For example, in referring toFIG.1B, single SiGe epitaxial layer130has a Ge concentration that varies from about 10 atomic % (at. %) to about 25 at. % along height A of fin structure100, and a Ge concentration that varies from about 25 at. % to about 35 at. % along height B of bottom tapered profile105. In some embodiments, the Ge “peak” concentration within an area defined by height A is located towards the bottom of height A—for example, within an area of fin structure100defined by a height HG, above bottom tapered profile105. In some embodiments, height HGranges between about ⅓ and ⅔ of height H of fin structure100. For example, if the total fin height H is about 60 nm, height HGcan range between about 20 nm and about 40 nm. In some embodiments,FIG.1Dshows the Ge at. % as a function of height H of fin structure100shown inFIG.1B. As discussed above with respect toFIG.1B, within the “boundaries” of height A, the peak Ge at. % can be found within an area of the fin structure100defined by height HG, which extends between about ⅓ and ⅔ of height H of fin structure100. Additionally, the Ge at. % can be even higher within bottom tapered profile105(e.g., along height B) as described above and shown inFIG.1D. The Ge at. % profile shown inFIG.1Dcan be achieved during the growth of the SiGe epitaxial layer by tuning the deposition process conditions as will be discussed later. In some embodiments, a similar Ge profile to that shown inFIG.1Dcan be achieved for fin structures100shown inFIG.1C, which includes SiGe epitaxial layers135,140, and145. For example, SiGe epitaxial layers135,140, and145can be grown with different Ge concentrations that replicate the Ge profile shown inFIG.1D. By way of example and not limitation, epitaxial layer145can be grown with the lowest Ge concentration, epitaxial layer140can be grown with a Ge concentration greater than that of epitaxial layer145and with a thickness equal to about height HG, and epitaxial layer135can be grown to form bottom tapered profile105with a Ge concentration greater than that of epitaxial layer140and a thickness equal to about height B. The above description of SiGe epitaxial layers135,140, and145is not limiting and a stack with two layers instead of three can be formed. For example, SiGe epitaxial layers135and140can be combined to a single SiGe epitaxial layer. Additional SiGe epitaxial layers are also possible and are within the spirit and the scope of this disclosure. In some embodiments,FIGS.2and3are magnified cross-sectional views of structural elements included in rectangular150ofFIG.1A. The features shown inFIGS.2and3apply equally to fin structures100shown inFIGS.1B and1C. In referring toFIG.2, bottom tapered profile105has a top width Wt between about 5 nm and about 15 nm, a middle width Wm between about 8 nm and about 20 nm, and a bottom width Wb between about 7 nm and about 18 nm. In some embodiments, width Wb is larger than width Wt, and width Wm is larger than both widths Wt and Wb. For example, Wm>Wb>Wt. In some embodiments, ratio Wt/Wm is between about 0.25 and about 0.75 (e.g., 0.25≤Wt/Wm≤0.75); and ratio Wb/Wm is between about 0.35 and about 0.90 (e.g., 0.35≤Wb/Wm≤0.90). In some embodiments, ratios Wt/Wm and Wb/Wm less than about 0.25 and 0.35, respectively, can produce exaggerated tapered profiles with limited channel control in the tapered area of fin structure100. In some embodiments, ratios Wt/Wm and Wb/Wm greater than about 0.75 and 0.90, respectively, can produce tapered profiles incapable of providing adequate structural support for fin structures100. In some embodiments, width Wt of bottom tapered profile105is substantially equal to or larger than top width W of fin structure100shown inFIG.1(e.g., Wt≥W). Therefore, it is possible that fin structures100are narrow at the top of fin structure100and increase in width along height A (e.g., W<Wt). In some embodiments, the width of fin structures100along height A is constant (e.g., W=Wt) and increases within height B of bottom tapered profile105. In some embodiments, width Wm of bottom tapered profile105is spaced from the interface between pedestal structure110and fin structure100by a vertical distance C that ranges between about 1 nm and about 3 nm. In some embodiments, vertical distance C is between about ⅓ and about ½ of height B (e.g., the entire height of bottom tapered profile105). In some embodiments, a C/B ratio below about ⅓ will “move” Wm closer to Wb. This will produce a challenging geometry for the deposition of gate layers. For example, it would be challenging to conformally deposit the gate layers (e.g., high-k dielectric layer, work function layers, etc.) on portions of bottom tapered profile105between Wm and Wb, which can result in an undesirable threshold voltage variation between the FETs. On the other hand, a C/B ratio above about ½ will “move” Wm closer to Wt, which will weaken the structural integrity of fin structure100. In some embodiments, the interface between pedestal structure110and fin structure100is positioned above the top surface of isolation material120by a vertical distance D that ranges between about 4 nm and about 15 nm. As discussed above, fin structures100, have wide and narrow portions along height H to improve their structural stiffness. However, under the same gate biasing conditions, the gate control on wider portions of fin structures100(e.g., at the locations of Wt, Wm, and Wb) can be challenging. According to some embodiments, the Ge concentration can be used to “locally” reduce the Vt over the wider portions of fin structures100and improve the gate control. This is because Ge has a narrower bandgap than Si; therefore, areas with a higher concentration in Ge (e.g., within the area defined by height HGand bottom tapered profile105) can have a lower Vt compared to areas with a lower concentration of Ge (e.g., at the top of fin structure100). Consequently, increasing the Ge concentration in wider portions of fin structures100, effectively reduces the Vt in the wider portions and improves the gate control over the channel. According to some embodiments, tailoring the Ge concentration in the fin structures can be beneficial for the operation of the finFET and ensures a substantially constant saturation current along height H of fin structure100. In some embodiments, the Ge concentration in the Ge-rich areas of fin structure100can reach to about 50%. According to some embodiments, width Wm of bottom tapered profile105shown inFIG.2is a critical structural parameter used to tailor the structural stiffness of fin structure100. As discussed above, width Wm can range from about 8 nm to about 20 nm. If width Wm is less than about 8 nm, bottom tapered profile105is not wide enough to adequately provide structural support for fin structure100. Conversely, if width Wm is greater than about 20 nm, channel control within bottom tapered profile105becomes challenging even with a higher Ge concentration. In some embodiments, control of width Wm is provided via angles θ1and θ2on each side of bottom tapered profile105shown inFIG.3. In some embodiments, angles θ1and θ2between about 10° and about 30° provide a width Wm between about 8 nm and about 20 nm. Therefore, angles θ1and θ2below about 10° result in a width Wm below about 8 nm and angles θ1and θ2wider than about 30° result in a width Wm greater than about 20 nm. In some embodiments, middle width Wm and angles θ1and θ2are controlled via etching and annealing conditions used during and after the formation of fin structures100. In some embodiments, angle03ranges between about 120° and about 160°. In some embodiments, angles θ1and θ2prevent sidewall portions of bottom tapered profile105from being co-planar with sidewall portions of fin structure100above and below bottom tapered profile105. Further, angles θ1and θ2prevent sidewall portions of bottom tapered profile105from being co-planar with sidewall portions of pedestal structures110as shown inFIG.3. FIG.4is a flowchart of fabrication method400for the formation of fin structures100shown inFIG.1A. Other fabrication operations may be performed between the various operations of method400and may be omitted merely for clarity and ease of description. These various operations are within the spirit and the scope of this disclosure. Additionally, not all operations may be required to perform the disclosure provided herein. Some of the operations may be performed simultaneously, or in a different order than the ones shown inFIG.4. In some embodiments, one or more other operations may be performed in addition to or in place of the presently described operations. Method400will be described in reference toFIGS.5-10. The figures provided to describe method400are for illustrative purposes only and may not be to scale. In addition, the figures may not reflect the actual geometry of the real structures, features, or films. Some structures, films, or geometries may have been deliberately augmented or omitted for illustrative purposes. In referring toFIG.4, method400begins with operation405and the process of depositing a Si epitaxial layer on a p-type region of a substrate, such as substrate115shown inFIG.1A. By way of example and not limitation, and according to operation405of method400, Si epitaxial layer125can be grown directly on a p-type region500of substrate115as shown inFIG.5. P-type region500can be formed, for example, with an ion implant process using a p-type dopant such as boron (B) and having a dopant concentration that ranges from about 5×1016atoms/cm3to about 1×1019atoms/cm3. Si epitaxial layer125can be grown to a thickness between about 30 nm and about 100 nm using a chemical vapor deposition (CVD) process. Source gases for the silicon epitaxial formation can include silane (SiH4), silicon tetrachloride (SiCl4), trichlorosilane (TCS), or dichlorosilane (SiH2Cl2or DSC). Hydrogen (H2) can be used as a reactant gas that reduces the aforementioned source gases. The deposition temperature during the epitaxial layer growth can range from about 700° C. to about 1250° C. depending on the gases used. For example, source gases with fewer chlorine atoms (e.g., DSC) may require lower formation temperatures than source gases with more chlorine atoms, such as SiCl4or TCS. The aforementioned ranges and type of gases are provided as examples and are not limiting. In referring toFIG.4, method400continues with operation410and the process of patterning Si epitaxial layer125and p-type region500to form fin structures on substrate115. In some embodiments, patterning of Si epitaxial layer125and p-type region500is achieved with photolithography and etching operations using hard mask structures505shown inFIG.5. In some embodiments, hard mask structures505function as an etch mask and can include one or more layers such as silicon oxide and silicon nitride. Fin structures may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes can combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. In some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures. According to some embodiments,FIG.5shows the final patterning operation for the formation of the fin structures where hard mask structures505can be the remaining spacers disposed on Si epitaxial layer125. According to some embodiments,FIG.6shows the resulting fin structures100formed according to operation410described above. Additional fin structures100can be formed on substrate115according to operation410by using additional hard mask structures. In some embodiments, the width and length of hard mask structures505along the y-axis and x-axis defines the width and length of fin structures100shown inFIG.6. Further, the spacing between hard mask structures505defines the spacing between fin structures100. Therefore, by controlling the dimensions of hard mask structure505, the dimensions of fin structure100can be defined. In some embodiments, width W′ of fin structures100after operation410is between about 7 nm and about 18 nm, which can be similar or thicker than Wb shown inFIG.2. In referring toFIG.4, method400continues with operation415and the process of depositing an isolation material between fin structures100. Depositing the isolation material includes the deposition of a liner layer600over fin structures100as shown inFIG.6. By way of example and not limitation, liner layer600functions as an adhesion layer for the isolation material. By way of example and not limitation, liner layer600can be deposited with a conformal deposition process, such as plasma-enhanced atomic layer deposition (PEALD), at a thickness between about 2 nm and 4 nm. By way of example and not limitation, liner layer600can be a silicon oxide or a silicon oxide-based dielectric material. Subsequently, an isolation material120is deposited to surround fin structures100as shown inFIG.6. In some embodiments, isolation material120is deposited at a thickness about 3 times height H of fin structures100shown inFIG.1A. According to some embodiments, isolation material120is deposited with a flowable chemical vapor deposition process (e.g., flowable CVD) to ensure that isolation material120fills the space between fin structures100without forming seams or voids. In some embodiments, isolation material120is a silicon oxide based dielectric material that includes, for example, nitrogen and hydrogen. To further improve its dielectric and structural properties, isolation material120may be subjected to a wet steam anneal (e.g., 100% water molecules) at a temperature between about 600° C. and 1200° C. During the wet steam anneal, isolation material120densifies and its oxygen content increases. Subsequently, a chemical mechanical planarization (CMP) process polishes isolation material120until top surfaces of fin structures100are exposed. During the aforementioned CMP process, the portions of liner layer600on the top surfaces of fin structures100are removed. A dry etching process “pulls back” (e.g., selectively etches) liner layer600and isolation material120to expose top portions of fin structures100as shown inFIG.7. This is because the gas chemistry used in the etch process of isolation material120is also selective towards liner layer600. In some embodiments, the etch process includes, but is not limited to, fluorocarbon chemistry. As a result of the aforementioned etch process, the top portions of fin structures100are exposed while the bottom portions remain embedded in isolation material120. In some embodiments, isolation material120is etched so that the top surface of recessed isolation material120is spaced from the interface between pedestal structure110and Si epitaxial layer125by a vertical distance R. In some embodiments, vertical distance R is substantially equal to vertical distance C shown inFIG.2(e.g., between about 1 nm and 3 nm). In other words, isolation material120is etched approximately to the level of width Wm shown inFIG.2. In referring toFIG.4, method400continues with operation420and the process of “trimming” (e.g., etching) the sidewalls of silicon epitaxial layer125of fin structures100not covered by isolation material120—for example, by trimming the exposed portions of fin structures100. In some embodiments, trimming (e.g., etching) the sidewalls of silicon epitaxial layer125includes selectively depositing a silicon-based layer on silicon epitaxial layer125, re-flowing the silicon-based layer so that the silicon-based layer becomes thinner on the top of fin structures100and thicker towards the bottom of fin structures100, and subsequently etching the silicon-based layer and the silicon epitaxial layer125to form an initial or first tapered profile. In some embodiments, the silicon-based layer is a silicon epitaxial layer selectively deposited on top and sidewall surfaces of fin structures100in a conformal manner at a thickness between about 1 nm and about 2 nm. As a result, the silicon-based material does not grow on isolation material120. In some embodiments, the two-stage annealing process includes a pre-soak at a temperature between about 600° C. and about 700° C. for about 10 s to about 30 s, followed by a spike anneal at a temperature between about 800° C. and about 1000° C. for about 1 ms. The re-flow process is configured to redistribute the silicon-based material on fin structures100. In some embodiments, about 0.5 nm to about 1 nm of the silicon-based material is redistributed between the top and the bottom of fin structures100. For example, after the re-flow process, the thickness of silicon-based layer can be about 3 nm at the bottom of fin structures100and about 1 nm at the top of fin structures100.FIG.7shows silicon-based layer700after the aforementioned deposition and reflow processes. A subsequent etching process, selective to silicon-based layer700and silicon epitaxial layer125, begins to remove silicon-based layer700. Due to the non-conformal distribution of silicon-based layer700after the reflow process, silicon epitaxial layer125at the top of fin structures100is exposed sooner to the etching chemistry than silicon epitaxial layer125at the bottom of fin structures100where silicon-based layer700is thicker. Consequently, the top portion of fin structures100is exposed for a longer period of time to the etching chemistry than the bottom portion. This intentional exposure time difference to the etching chemistry is responsible for the formation of an initial or first tapered profile in fin structures100. The resulting fin structures100are shown inFIG.8. By way of example and not limitation, fin structures100develop rounding top corners after the etching process as shown inFIG.8. Further, after the etching process, top width W″ has been reduced compared to the initial top width W′ shown inFIG.6(e.g., W″<W). In some embodiments, W″ can be substantially equal to or greater than about W shown inFIG.1A(e.g., W″≥W). In some embodiments, thicker silicon-based layers (e.g., thicker than about 2 nm) and longer reflow times can be used to generate more pronounced tapered profiles (e.g., bottom tapered profiles with a larger width Wm). However, such conditions may substantially increase the overall processing time and fabrication cost. On the other hand, thinner silicon-based layers (e.g., thinner than about 2 nm) may not produce the desired tapered profile (e.g., the desired difference between the top and bottom widths). In some embodiments, the thickness of the silicon-based layer and the reflow conditions (e.g., annealing duration and temperature) can be used to tune the thickness difference between the top and bottom sidewall coverage on fin structures100and to produce the desired tapered profile. More specifically, the aforementioned processes can be used to define angle θ1shown inFIG.3. Further, in some embodiments, operation420may be repeated to fine tune the desired initial tapered profile and top width for fin structures100. In some embodiments, the aforementioned etching process includes a combination of a wet etching and a dry etching. In some embodiments, the wet etching process is used for the main etch (e.g., to trim fin structures100) and the dry etching process is used to remove byproducts formed during the main etch. In some embodiments, the etching process removes between about 10% and 20% of silicon epitaxial material from fin structures100(e.g., between about 4 nm and about 7 nm). By way of example and not limitation, the wet etching chemistry can include diluted hydrochloric acid (dHF), ammonia hydroxide (NH4OH), and water. The dry etching process can include, for example, ozone (O3) plasma. In some embodiments, the wet etching process is isotropic to ensure etching uniformity from all directions during the main etch. In referring toFIG.4, method400continues with operation425and the deposition of an oxide layer on the trimmed fin structures100. For example, and in referring toFIG.9, oxide layer900can be deposited to cover top and sidewall surfaces of trimmed fin structures100and top surfaces of isolation material120. By way of example and not limitation, oxide layer900can be a sacrificial gate oxide layer, such as a silicon oxide layer or a silicon oxy-nitride layer with a thickness between about 2 nm and about 5 nm. Oxide layer900is replaced in a subsequent operation by a gate dielectric stack that includes a material with a high dielectric constant (e.g., with a dielectric constant greater than about 3.9). In referring toFIG.4, method400continues with operation430and the process of performing an annealing process to form a second tapered profile shown inFIG.10. More specifically, the annealing process of operation430defines angles θ2and θ3shown inFIG.3. This is because, during the annealing process of operation430, fin structures100are partially oxidized due to the availability of oxygen from oxide layer900, liner layer600, and isolation material120as indicated by short black arrows905and long black arrows910inFIG.9. Since, the combined thickness of liner layer600and isolation material120is larger than the thickness of oxide layer900, more oxygen is available for oxidation for the portions of fin structures100covered by liner layer600and isolation material120than for the portions of fin structures100covered by oxide layer900. Therefore, portions of fin structures100covered by liner layer600and isolation material120will be oxidized more than portions of fin structures100covered by oxide layer900. Therefore, more silicon material from fin structures100will be consumed for the formation of thicker oxide on portions of fin structures100covered by liner layer600and isolation material120than on portions of fin structures100covered by oxide layer900. At the same time, during the aforementioned annealing process, isolation material120shrinks as indicated by white arrows915. Hence, the height of isolation material120is reduced and isolation material120is effectively recessed to reveal bottom tapered profile105shown inFIG.10. In some embodiments, the annealing process is similar to the annealing process discussed with respect to the reflow of silicon-based layer700in operation420. However, there are differences. For example, in operation430, the temperature range for the spike anneal can be greater—e.g., between about 700° C. and about 1100° C. according to some embodiments. Additionally, the oxygen concentration during the annealing process in operation430is higher than that of the annealing process described in operation420. In some embodiments, partial oxidation of fin structures100covered by liner layer600and isolation material120may also occur during the annealing process as discussed above with respect to the reflow of silicon-based layer700in operation420. Similarly, isolation material120may be also recessed during the annealing process in operation430. Based on the aforementioned oxidation process described in operation430, portions of oxide layer900on lower portions of bottom tapered profile105, as indicated by dashed circles1000inFIG.10, are grown thicker than portions of oxide layer900above bottom tapered profile105. This is due to the presence of additional oxygen in the vicinity of liner layer600and isolation material120that enhances the oxidation reaction in this region. At the same time, as isolation material120shrinks and recesses with respect to fin structures100, the growth of oxide layer900slows down since the oxygen source is removed by the recess action of isolation material120. Therefore, bottom tapered profile105is formed by a combination of the etching and oxidation processes as discussed above. According to some embodiments, angle θ2shown inFIG.3can be modulated through the annealing conditions of operation430. For example, increasing the annealing temperature (e.g., setting the annealing temperature closer to about 1100° C.) and/or the anneal time, allows oxide layer900to continue growing at the bottom of fin structures100as discussed above. A thicker oxide layer900means that there is a greater consumption of Si epitaxial layer125from fin structures100, which results in a larger θ2and width Wm and a narrower θ3. Conversely, an annealing temperature closer to about 700° C. and/or shorter annealing times will produce a thinner oxide layer and a lower consumption of Si epitaxial layer125, which results in a smaller θ2and width Wm and a wider θ3. Oxide layer900and liner layer600are not shown inFIGS.1A-1C,2, and3for ease of description. In some embodiments, after operation430, a sacrificial gate electrode1005is deposited on fin structures100as shown inFIG.10. In some embodiments, sacrificial gate electrode1005does not cover the entire length of fin structures100along the x-direction. For example, sacrificial gate electrode1005covers a middle section of fin structures100, leaving the rest of fin structures100exposed. Further, after operation430, width W of fin structures100does not substantially change. In some embodiments, during operations420and425, the height of fin structures100is successively reduced from operation410due to the etching and annealing processes described above. In some embodiments, exposed sections of fin structures100(e.g., portions of fin structures100not covered by sacrificial gate electrode1005) are stripped from oxide layer900(e.g., with an etching process preferentially selective towards oxide layer900), and a source/drain epitaxial structure1100is grown thereon as shown inFIG.11. In some embodiments, source/drain epitaxial structure1100is a merged source/drain epitaxial structure formed by two or more epitaxial layers grown from each fin structure100. During the final stages of the growth, the two or more epitaxial layers are allowed to merge and form source/drain epitaxial structure1100shown inFIG.11. In some embodiments, source/drain epitaxial structure1100includes SiGe for p-type finFETs and carbon doped Si (Si:C) for n-type finFETs. Method400can also be used to form SiGe fin structures shown inFIGS.1B and1C. For example, in operation405, a single SiGe epitaxial layer or a SiGe epitaxial stack can be formed on n-type regions of substrate115to form fin structures100shown inFIGS.1B and1C—which, as discussed above, are suitable for p-type finFETs. In some embodiments, the SiGe epitaxial layer(s) is grown with a heteroepitaxial process using, for example, a CVD process. By way of example and not limitation, precursor gases used for the single SiGe epitaxial layer or the SiGe epitaxial stack growth may include a combination of (i) SiH4, disaline (Si2H6), SiH2Cl2, germane (GeH4), or hydrochloric acid (HCl), and (ii) hydrogen (H2), nitrogen (N2), or argon (Ar). In some embodiments, a buffer layer (not shown) may be deposited prior to the growth of SiGe epitaxial layer(s) to suppress growth defects due to the lattice mismatch between the grown SiGe and underlying substrate115. Further, substrate115may be pre-treated prior to the growth of SiGe epitaxial layer(s) to remove native oxide layers formed thereon. By way of example and not limitation, the Ge concentration during growth can be modulated via the partial pressure of GeH4and the partial pressure of other gases, such as SiH4, Si2H6, and SiH2Cl2, during growth. For example, higher partial pressure of GeH4or lower partial pressure of SiH4, Si2H6, or SiH2Cl2during growth favor SiGe layers with higher Ge concentration. Lower partial pressure of GeH4or higher partial pressure of SiH4, Si2H6, or SiH2Cl2favor SiGe layers with a lower Ge concentration. Various embodiments in accordance with this disclosure describe a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and desirable gate control characteristics. In some embodiments, Si and SiGe ultra-thin fins can be fabricated using the methods described herein. Further, SiGe fins with a Ge variable concentration and a tapered bottom profile can be formed in p-type finFETs for improved gate control over the channel. In some embodiments, the variable Ge concentration of the SiGe fin structures ranges from about 10% to about 35% with higher Ge concentration towards the bottom of the fin structures. In some embodiments, the top width of the ultra-thin fin structures ranges between about 5 nm and about 15 nm and the width of the bottom tapered profile ranges between about 8 nm and about 20 nm. In some embodiments, a first tapered profile is achieved via depositing and reflowing a silicon-based layer on the patterned fin structure, followed by trimming the fin structure with a combination of wet etching and dry etching processes. In some embodiments, the second tapered profile is formed by depositing an oxide layer on the trimmed portions of the fin and subjecting the fin structure to an annealing process that oxidizes the bottom portion of the fin structure more than the top portion of the fin structure. In some embodiments, a semiconductor structure includes a substrate comprising pedestal structures formed thereon and fin structures formed on the pedestal structures. The fin structure further includes a bottom tapered portion having a bottom width, a middle width, and a top width with the middle width being larger than the bottom width and the top width. The fin structure also includes an upper portion having a width substantially equal to or narrower than the top width of the bottom tapered portion. Further the semiconductor structure includes an isolation material disposed between the pedestal structures. In some embodiments, a semiconductor structure includes a substrate comprising pedestal structures formed thereon and fin structures formed on the pedestal structures. The fin structures further include a top portion and a tapered bottom portion wider than the top portion where each sidewall of the tapered bottom portion is not coplanar with sidewall surfaces of the top portion of the fin structure and sidewall surfaces of the pedestal structures. Further the semiconductor structure includes an isolation material disposed between the pedestal structures. In some embodiments, a method includes depositing an epitaxial layer on a doped region of a substrate; patterning the epitaxial layer and the doped region to form a fin structure that includes an epitaxial layer portion and a doped region portion. The method also includes forming an isolation region on the substrate so that a top section of the epitaxial layer portion is above the isolation region; depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region; annealing the silicon-based layer to reflow the silicon-based layer; and etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region. The method further includes annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region so that the first and second bottom tapered profiles collectively form a bottom profile with a top width, a middle width, and a bottom width where the middle width is greater than each of the top and bottom widths. It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all exemplary embodiments contemplated and thus, are not intended to be limiting to the subjoined claims. The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the subjoined claims. | 41,767 |
11862684 | DETAILED DESCRIPTION Problem to be Solved by the Present Disclosure An object of the present disclosure is to provide a recycle wafer of silicon carbide and a method for manufacturing a silicon carbide semiconductor device that can reduce the absolute value of the amount of change in warpage before and after epitaxial growth. Advantageous Effect of the Present Disclosure According to the above description, a recycle wafer of silicon carbide and a method for manufacturing a silicon carbide semiconductor device that can reduce the absolute value of the amount of change in warpage before and after epitaxial growth can be provided. Summary of Embodiment of the Present Disclosure First, a summary of an embodiment of the present disclosure will be described. Regarding crystallographic indications in the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, an individual plane is represented by ( ), and a group plane is represented by { }. Generally, a negative index is supposed to be crystallographically indicated by putting “-” (bar) above a numeral, but is indicated by putting the negative sign before the numeral in the present specification. (1) A recycle wafer100of silicon carbide in accordance with one aspect of the present disclosure includes a silicon carbide substrate10and a first silicon carbide layer21. Silicon carbide substrate10has a first main surface1and a second main surface2opposite to first main surface1. First silicon carbide layer21is in contact with first main surface1. Silicon carbide substrate10includes a substrate region11that is within 10 μm from first main surface1toward second main surface2. In a direction perpendicular to first main surface1, a value obtained by subtracting a value that is three times a standard deviation of a nitrogen concentration in substrate region11from an average value of the nitrogen concentration in substrate region11is greater than a minimum value of a nitrogen concentration in first silicon carbide layer21. (2) In recycle wafer100of silicon carbide in accordance with (1) described above, the minimum value may be greater than a value obtained by dividing the average value by 1000. (3) In recycle wafer100of silicon carbide in accordance with (1) or (2) described above, silicon carbide substrate10may further have an outer peripheral surface7, a first inclined surface4, and a second inclined surface6, first inclined surface4being continuous to each of first main surface1and outer peripheral surface7and being inclined toward second main surface2as first inclined surface4extends from first main surface1to outer peripheral surface7, second inclined surface6being continuous to each of second main surface2and outer peripheral surface7and being inclined toward first main surface1as second inclined surface6extends from second main surface2to outer peripheral surface7. First silicon carbide layer21may be in contact with first inclined surface4. First silicon carbide layer21may have a third inclined surface5opposite to first inclined surface4. A length of third inclined surface5in a direction parallel to first main surface1may be greater than a length of second inclined surface6in a direction parallel to second main surface2. A length of third inclined surface5in the direction perpendicular to first main surface1may be greater than a length of second inclined surface6in a direction perpendicular to second main surface2. (4) Recycle wafer100of silicon carbide in accordance with any of (1) to (3) described above may further include a second silicon carbide layer22in contact with second main surface2. (5) In recycle wafer100of silicon carbide in accordance with (4) described above, a thickness of second silicon carbide layer22may be greater than a thickness of first silicon carbide layer21. (6) A method for manufacturing a silicon carbide semiconductor device in accordance with one aspect of the present disclosure includes preparing recycle wafer100of silicon carbide according to any of (1) to (5) described above, and processing recycle wafer100of silicon carbide. Details of Embodiment of the Present Disclosure Next, the details of the embodiment of the present disclosure will be described with reference to the drawings. It should be noted that, in the drawings below, identical or corresponding parts will be designated by identical reference numerals, and an overlapping description will not be repeated. (Recycle Wafer of Silicon Carbide) FIG.1is a schematic cross sectional view showing a configuration of a recycle wafer of silicon carbide in accordance with the present embodiment. As shown inFIG.1, recycle wafer100of silicon carbide in accordance with the present embodiment has silicon carbide substrate10and first silicon carbide layer21. Silicon carbide substrate10has first main surface1and second main surface2. Second main surface2is a surface opposite to first main surface1. Silicon carbide substrate10has a first substrate region11and a second substrate region12. First substrate region11is a region that is within 10 μm from first main surface1toward second main surface2. First substrate region11constitutes first main surface1. The thickness of first substrate region11(a first thickness T1) is 10 μm. The thickness of silicon carbide substrate10(a second thickness T2) is not particularly limited, and is more than or equal to 350 μm and less than or equal to 500 μm, for example. Silicon carbide substrate10has a substantially disk shape. The diameter of silicon carbide substrate10is more than or equal to 150 mm, for example. Silicon carbide substrate10is constituted by a silicon carbide single crystal, for example. The silicon carbide constituting silicon carbide substrate10has a polytype of 4H, for example. Second main surface2is, for example, a {0001} plane or a plane inclined at an off-angle of more than or equal to 2° and less than or equal to 6° relative to the {0001} plane. Specifically, second main surface2is a (0001) plane or a plane inclined at an off-angle of more than or equal to 2° and less than or equal to 6° relative to the (0001) plane, for example. Alternatively, second main surface2may be a (000-1) plane or a plane inclined at an off-angle of more than or equal to 2° and less than or equal to 6° relative to the (000-1) plane, for example. When first main surface1is inclined relative to the {0001} plane, the direction of inclination (off direction) of first main surface1is a <11-20> direction, for example. First silicon carbide layer21is located on the first main surface1side of silicon carbide substrate10. First silicon carbide layer21is in contact with first main surface1. First silicon carbide layer21is in contact with first substrate region11at first main surface1. First main surface1is a back surface. The back surface is a surface on which a back-surface electrode (for example, a drain electrode) of a vertical semiconductor device is to be formed. Second main surface2is a front surface. The front surface is a surface on which a front-surface electrode (for example, a source electrode) of the vertical semiconductor device is to be formed. The thickness of first silicon carbide layer21(a third thickness T3) is not particularly limited, and is 3 μm, for example. Third thickness T3may be more than or equal to 0.5 μm and less than or equal to 10 μm, for example. The thickness of first silicon carbide layer21(third thickness T3) is smaller than the thickness of silicon carbide substrate10(second thickness T2). First silicon carbide layer21is a layer formed by epitaxial growth, for example. The silicon carbide constituting first silicon carbide layer21has a polytype of 4H, for example. First silicon carbide layer21has a third main surface3opposite to first main surface1. Third main surface3is a {0001} plane or a plane inclined at an off-angle of more than or equal to 2° and less than or equal to 6° relative to the {0001} plane, for example. FIG.2is an enlarged schematic cross sectional view showing a configuration of a region II inFIG.1. As shown inFIG.2, chamfering is performed on an outer peripheral portion of silicon carbide substrate10. Specifically, silicon carbide substrate10has outer peripheral surface7, first inclined surface4, and second inclined surface6. Outer peripheral surface7is an annular surface exposed to the outer periphery of silicon carbide substrate10. First inclined surface4is continuous to each of first main surface1and outer peripheral surface7. First inclined surface4is inclined toward second main surface2as first inclined surface4extends from first main surface1to outer peripheral surface7. The angle formed between first inclined surface4and first main surface1(a first angle θ1) is more than 90° and less than 180°. The angle formed between first inclined surface4and outer peripheral surface7(a second angle θ2) is more than 90° and less than 180°. First inclined surface4is constituted by first substrate region11. As shown inFIG.2, second inclined surface6is continuous to each of second main surface2and outer peripheral surface7. Second inclined surface6is inclined toward first main surface1as second inclined surface6extends from second main surface2to outer peripheral surface7. The angle formed between second inclined surface6and second main surface2(a third angle θ3) is more than 90° and less than 180°. The angle formed between second inclined surface6and outer peripheral surface7(a fourth angle θ4) is more than 90° and less than 180°. Second inclined surface6is constituted by second substrate region12. First silicon carbide layer21is in contact with first inclined surface4. First silicon carbide layer21has third inclined surface5opposite to first inclined surface4. Third inclined surface5is substantially parallel to first inclined surface4. Third inclined surface5is located on an outer peripheral side of third main surface3. Third inclined surface5is continuous to third main surface3. The length of third inclined surface5in a direction parallel to first main surface1(a third horizontal length a3) may be greater than the length of second inclined surface6in a direction parallel to second main surface2(a second horizontal length a2). The length of third inclined surface5in a direction perpendicular to first main surface1(a third vertical length b3) may be greater than the length of second inclined surface6in a direction perpendicular to second main surface2(a second vertical length b2). Each of silicon carbide substrate10and first silicon carbide layer21contains nitrogen (N) as an n type impurity. Each of silicon carbide substrate10and first silicon carbide layer21has an n type conductivity type.FIG.3is a schematic view showing a nitrogen concentration profile in the thickness direction of recycle wafer100of silicon carbide. The axis of abscissas inFIG.3represents the position in the thickness direction of recycle wafer100of silicon carbide. The axis of ordinates inFIG.3represents the nitrogen concentration in recycle wafer100of silicon carbide. As shown inFIG.3, the nitrogen concentration in silicon carbide substrate10exhibits a substantially constant value in the thickness direction. The average value of the nitrogen concentration in first substrate region11(N1_ave) of silicon carbide substrate10is more than or equal to 1×1018cm−3and less than or equal to 1×1019cm−3, for example. First silicon carbide layer21has a region where the nitrogen concentration decreases from a boundary surface between first silicon carbide layer21and silicon carbide substrate10(first main surface1) toward third main surface3. The nitrogen concentration in first silicon carbide layer21exhibits a minimum value (N2_min) at a position P1in first silicon carbide layer21. Position P1is located between third main surface3and first main surface1in the direction perpendicular to first main surface1. In the direction perpendicular to first main surface1, the nitrogen concentration in first silicon carbide layer21may increase monotonically from position P1to first main surface1. From another viewpoint, first silicon carbide layer21may have a region where the nitrogen concentration increases monotonically from position P1at which the nitrogen concentration exhibits the minimum value to first main surface1. Similarly, in the direction perpendicular to first main surface1, the nitrogen concentration in first silicon carbide layer21may increase monotonically from position P1to third main surface3. From another viewpoint, first silicon carbide layer21may have a region where the nitrogen concentration increases monotonically from position P1at which the nitrogen concentration exhibits the minimum value to third main surface3. As shown inFIG.3, the average value of the nitrogen concentration in first substrate region11(N1_ave) is greater than the minimum value of the nitrogen concentration in first silicon carbide layer21(N2_min). Specifically, in the direction perpendicular to first main surface1, a value obtained by subtracting a value that is three times a standard deviation of the nitrogen concentration in first substrate region11from the average value of the nitrogen concentration in first substrate region11(N1_ave) is greater than the minimum value of the nitrogen concentration in first silicon carbide layer21(N2_min). The minimum value of the nitrogen concentration in first silicon carbide layer21(N2_min) may be greater than a value obtained by dividing the average value of the nitrogen concentration in first substrate region11(N1_ave) by 1000. The minimum value of the nitrogen concentration in first silicon carbide layer21(N2_min) may be greater than a value obtained by dividing the average value of the nitrogen concentration in first substrate region11(N1_ave) by 800, or may be greater than a value obtained by dividing the average value of the nitrogen concentration in first substrate region11(N1_ave) by 500. The minimum value of the nitrogen concentration in first silicon carbide layer21(N2_min) may be smaller than a value obtained by dividing the average value of the nitrogen concentration in first substrate region11(N1_ave) by 10. Next, a method for measuring the nitrogen concentration will be described. The nitrogen concentration in recycle wafer100of silicon carbide can be measured using secondary ion mass spectroscopy (SIMS). The measurement device is a secondary ion mass spectrometry device manufactured by Cameca, for example. The measuring pitch is 0.01 μm, for example. The primary ion beam is cesium (Cs). The primary ion energy is 14.5 eV. The secondary ion polarity is negative. Next, a configuration of a variation of the recycle wafer of silicon carbide in accordance with the present embodiment will be described. FIG.4is a schematic cross sectional view showing a configuration of a variation of the recycle wafer of silicon carbide in accordance with the present embodiment. As shown inFIG.4, the variation of recycle wafer100of silicon carbide in accordance with the embodiment further has second silicon carbide layer22, in addition to the configuration inFIG.1. That is, recycle wafer100of silicon carbide may be constituted by silicon carbide substrate10, first silicon carbide layer21, and second silicon carbide layer22. Second silicon carbide layer22is in contact with second main surface2. From another viewpoint, second silicon carbide layer22is in contact with second substrate region12at second main surface2. The thickness of second silicon carbide layer22(a fourth thickness T4) may be greater than the thickness of first silicon carbide layer21(third thickness T3). Fourth thickness T4may be twice or more third thickness T3, for example. Fourth thickness T4is more than or equal to 5 μm and less than or equal to 100 μm, for example. Second silicon carbide layer22contains nitrogen (N) as an n type impurity. Second silicon carbide layer22has the n type conductivity type. The average value of the nitrogen concentration in second silicon carbide layer22may be smaller than the average value of the nitrogen concentration in first substrate region11(N1_ave) of silicon carbide substrate10. The average value of the nitrogen concentration in second silicon carbide layer22may be greater than the minimum value of the nitrogen concentration in first silicon carbide layer21(N2_min). FIG.5is an enlarged schematic cross sectional view showing a configuration of a region V inFIG.4. As shown inFIG.5, second silicon carbide layer22has a fourth main surface8and a fourth inclined surface9. Fourth main surface8is opposite to second main surface2. Fourth inclined surface9is opposite to second inclined surface6. Fourth inclined surface9is located on an outer peripheral side of fourth main surface8. Fourth inclined surface9is continuous to fourth main surface8. Fourth inclined surface9is substantially parallel to second inclined surface6. The length of third inclined surface5in the direction parallel to first main surface1(third horizontal length a3) may be greater than the length of fourth inclined surface9in the direction parallel to second main surface2(a fourth horizontal length a4). The length of third inclined surface5in the direction perpendicular to first main surface1(third vertical length b3) may be greater than the length of fourth inclined surface9in the direction perpendicular to second main surface2(a fourth vertical length b4). (Method for Manufacturing Recycle Wafer of Silicon Carbide) Next, a method for manufacturing the recycle wafer of silicon carbide in accordance with the present embodiment will be described. FIG.6is a process chart showing a method for manufacturing the recycle wafer of silicon carbide in accordance with the present embodiment. As shown inFIG.6, the method for manufacturing the recycle wafer of silicon carbide in accordance with the present embodiment mainly has a substrate receiving step (S1:FIG.6), an epitaxial growth step (S2:FIG.6), a grinding step (S3:FIG.6), a mechanical polishing step (S4:FIG.6), and a chemical mechanical polishing step (S5:FIG.6). First, the substrate receiving step (S1:FIG.6) is performed. In the substrate receiving step, silicon carbide substrate10is prepared.FIG.7is a schematic cross sectional view showing the substrate receiving step of the method for manufacturing recycle wafer100of silicon carbide in accordance with the present embodiment. Silicon carbide substrate10is formed of a silicon carbide single crystal. Silicon carbide substrate10is formed of a hexagonal silicon carbide single crystal having a polytype of 4H, for example. Silicon carbide substrate10has first main surface1, first inclined surface4, second main surface2, second inclined surface6, and outer peripheral surface7. First inclined surface4is continuous to both of first main surface1and outer peripheral surface7. First inclined surface4is inclined upward (toward second main surface2) as first inclined surface4extends from first main surface1to outer peripheral surface7. As shown inFIG.7, second main surface2is a surface opposite to first main surface1. Second inclined surface6is continuous to both of second main surface2and outer peripheral surface7. Second inclined surface6is inclined downward (toward first main surface1) as second inclined surface6extends from second main surface2to outer peripheral surface7. The length of first inclined surface4in the direction parallel to first main surface1(a first horizontal length a1) may be greater than the length of second inclined surface6in the direction parallel to second main surface2(second horizontal length a2). The length of first inclined surface4in the direction perpendicular to first main surface1(a first vertical length b1) may be greater than the length of second inclined surface6in the direction perpendicular to second main surface2(second vertical length b2). Then, the epitaxial growth step (S2:FIG.6) is performed. In the epitaxial growth step, a silicon carbide layer is formed by epitaxial growth, using a CVD (Chemical Vapor Deposition) method, for example. A mixed gas containing silane, propane, nitrogen, and hydrogen, for example, is introduced into a chamber of a CVD apparatus. On that occasion, the temperature within the chamber is maintained at about 1630° C., for example. Ammonia gas may be used instead of nitrogen gas. Although the epitaxial growth is mainly performed on the front surface side, the mixed gas also reaches the back surface side of silicon carbide substrate10. In particular, when silicon carbide substrate10is warped, a gap is formed between the back surface of silicon carbide substrate10and a susceptor, and thus the mixed gas enters the back surface side. In addition, also when first horizontal length a1and first vertical length b1of first inclined surface4are long, the mixed gas is likely to enter the back surface side of silicon carbide substrate10. In such a case, deposition or sublimation of silicon carbide occurs not only on the front surface side but also on the back surface side of silicon carbide substrate10. FIG.8is a schematic cross sectional view showing a state after the epitaxial growth step of the method for manufacturing the recycle wafer of silicon carbide in accordance with the present embodiment. As shown inFIG.8, in the epitaxial growth step, a third silicon carbide layer23is formed on the front surface (second main surface2and second inclined surface6) of silicon carbide substrate10. The thickness of third silicon carbide layer23is 10 μm, for example. At the same time, first silicon carbide layer21is formed on the back surface (first main surface1and first inclined surface4) of silicon carbide substrate10. The thickness of first silicon carbide layer21is 3 μm, for example. As shown inFIG.8, third silicon carbide layer23has a fifth main surface31and a fifth inclined surface32. Fifth main surface31is opposite to second main surface2. Fifth inclined surface32is opposite to second inclined surface6. Fifth inclined surface32is located on an outer peripheral side of fifth main surface31. Fifth inclined surface32is continuous to fifth main surface31. Fifth inclined surface32is substantially parallel to second inclined surface6. The length of third inclined surface5in the direction parallel to first main surface1(third horizontal length a3) may be greater than the length of fifth inclined surface32in the direction parallel to second main surface2(a fifth horizontal length a5). The length of third inclined surface5in the direction perpendicular to first main surface1(third vertical length b3) may be greater than the length of fifth inclined surface32in the direction perpendicular to second main surface2(a fifth vertical length b5). Then, evaluation of third silicon carbide layer23is performed. Specifically, it is determined whether third silicon carbide layer23has a failure. More specifically, it is determined whether the impurity concentration and the defect density in third silicon carbide layer23satisfy predetermined criteria. When it is determined that third silicon carbide layer23has a failure, third silicon carbide layer23is removed. In the following, a method for removing third silicon carbide layer23will be described. First, the grinding step (S3.FIG.6) is performed. In the grinding step, grinding is performed on the fifth main surface31side. The grinding device is DAG-810 manufactured by DISCO, for example. The grindstone is a diamond grindstone, for example. The grindstone has a mesh size of #2000. The number of revolutions of a spindle is 4000 rpm, for example. The number of revolutions of a table is 50 rpm, for example. The feed rate is 0.2 μm/second, for example. Thus, at least a portion of third silicon carbide layer23is removed by the grinding. Then, the mechanical polishing step (S4:FIG.6) is performed. In the mechanical polishing step, mechanical polishing is performed on the second main surface2side of silicon carbide substrate10. Specifically, silicon carbide substrate10is held by a polishing head such that second main surface2of silicon carbide substrate10faces a surface plate. The mechanical polishing device is LGP-612 manufactured by Lapmaster, for example. A slurry containing abrasive grains is supplied between the surface plate and second main surface2. The abrasive grains are diamond abrasive grains, for example. The abrasive grains have a grain size of 1 μm, for example. The number of revolutions of the surface plate is 60 rpm, for example. Thereby, third silicon carbide layer23is removed from silicon carbide substrate10. FIG.9is a schematic cross sectional view showing a state after the mechanical polishing step of the method for manufacturing the recycle wafer of silicon carbide in accordance with the present embodiment. As shown inFIG.9, third silicon carbide layer23on second main surface2has been removed, and second main surface2is exposed. A portion of third silicon carbide layer23may be left on second inclined surface6. First silicon carbide layer21is maintained in contact with each of first main surface1and first inclined surface4. Then, the chemical mechanical polishing step (S5.FIG.6) is performed. In the chemical mechanical polishing step, chemical mechanical polishing is performed on the second main surface2side of silicon carbide substrate10. Specifically, silicon carbide substrate10is held by the polishing head such that second main surface2faces a polishing cloth. A slurry is supplied between the polishing cloth and second main surface2. The slurry is a colloidal silica slurry, for example. The slurry is DSC-0902 manufactured by Fujimi Incorporated, for example. The polishing cloth is made of suede, for example. The number of revolutions of the surface plate is 60 rpm, for example. In the chemical mechanical polishing step, the portion of third silicon carbide layer23left on second inclined surface6is removed. Thereby, recycle wafer100of silicon carbide in accordance with the present embodiment is manufactured (seeFIG.1). It should be noted that, in the grinding step (S3:FIG.6), the mechanical polishing step (S4:FIG.6), and the chemical mechanical polishing step (S5:FIG.6) described above, only one side (the second main surface2side) of silicon carbide substrate10is processed. Thereby, third silicon carbide layer23is removed. That is, in the grinding step (S3:FIG.6), the mechanical polishing step (S4:FIG.6), and the chemical mechanical polishing step (S5:FIG.6) described above, processing is not performed on third main surface3. Accordingly, first silicon carbide layer21is left without being removed. (Method for Manufacturing Silicon Carbide Semiconductor Device) Next, a method for manufacturing a silicon carbide semiconductor device300in accordance with the present embodiment will be described. The method for manufacturing the silicon carbide semiconductor device in accordance with the present embodiment mainly has a recycle wafer100of silicon carbide preparing step (S10:FIG.10) and a substrate processing step (S20:FIG.10). First, the recycle wafer of silicon carbide preparing step (S10:FIG.10) is performed. Specifically, recycle wafer100of silicon carbide shown inFIG.1is prepared using the method for manufacturing recycle wafer100of silicon carbide described above. Then, epitaxial growth is performed on recycle wafer100of silicon carbide. Specifically, second silicon carbide layer22is formed by epitaxial growth, using the CVD (Chemical Vapor Deposition) method. The epitaxial growth conditions for second silicon carbide layer22may be the same as the epitaxial growth conditions for third silicon carbide layer23described above. Thus, recycle wafer100of silicon carbide having first silicon carbide layer21, second silicon carbide layer22, and silicon carbide substrate10is prepared (seeFIG.11). Then, the substrate processing step (S20:FIG.10) is performed. Specifically, the silicon carbide semiconductor device is manufactured by processing recycle wafer100of silicon carbide. The “processing” includes various types of processing such as ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing, for example. That is, the substrate processing step may include at least one processing of ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing. In the following, a method for manufacturing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of the silicon carbide semiconductor device will be described. The substrate processing step (S20:FIG.10) includes an ion implantation step (S21:FIG.10), an oxide film forming step (S22:FIG.10), an electrode forming step (S23:FIG.10), and a dicing step (S24:FIG.10), for example. First, the ion implantation step (S21:FIG.10) is performed. A p type impurity such as aluminum (Al), for example, is implanted into fourth main surface8on which a mask (not shown) having openings is formed. Thereby, a body region132having a p type conductivity type is formed. Then, an n type impurity such as phosphorus (P), for example, is implanted into a predetermined position within body region132. Thereby, a source region133having the n type conductivity type is formed. Then, a p type impurity such as aluminum is implanted into a predetermined position within source region133. Thereby, a contact region134having the p type conductivity type is formed (seeFIG.12). In second silicon carbide layer22, the portion other than body region132, source region133, and contact region134serves as a drift region131. Source region133is separated from drift region131by body region132. Ion implantation may be performed with recycle wafer100of silicon carbide being heated to about 300° C. or more and 600° C. or less. After the ion implantation, activation annealing is performed on recycle wafer100of silicon carbide. By the activation annealing, the impurities implanted into second silicon carbide layer22are activated, and carriers are generated in each region. The atmosphere for the activation annealing is an argon (Ar) atmosphere, for example. The temperature for the activation annealing is about 1800° C., for example. The time for the activation annealing is about 30 minutes, for example. Then, the oxide film forming step (S22:FIG.10) is performed. By heating recycle wafer100of silicon carbide in an atmosphere containing oxygen, for example, an oxide film136is formed on fourth main surface8(seeFIG.13). Oxide film136is composed of silicon dioxide or the like, for example. Oxide film136functions as a gate insulating film. The temperature for thermal oxidation treatment is about 1300° C., for example. The time for the thermal oxidation treatment is about 30 minutes, for example. After oxide film136is formed, heat treatment may further be performed in a nitrogen atmosphere. For example, the heat treatment is performed in an atmosphere of nitric oxide, at about 1100° C., for about one hour. Thereafter, heat treatment is further performed in an argon atmosphere. For example, the heat treatment is performed in the argon atmosphere, at about 1100° C. or more and 1500° C. or less, for about one hour. Then, the electrode forming step (S23:FIG.10) is performed. Specifically, a gate electrode141is formed on oxide film136. Gate electrode141is formed by the CVD (Chemical Vapor Deposition) method, for example. Gate electrode141is composed of polysilicon or the like having electrical conductivity, for example. Gate electrode141is formed at a position facing source region133and body region132. Subsequently, an interlayer insulating film137covering gate electrode141is formed. Interlayer insulating film137is formed by the CVD method, for example. Interlayer insulating film137is composed of silicon dioxide or the like, for example. Interlayer insulating film137is formed to come into contact with gate electrode141and oxide film136. Then, portions of oxide film136and interlayer insulating film137are removed by etching. Thereby, source region133and contact region134are exposed from oxide film136. Subsequently, a source electrode142is formed at the exposed portion by a sputtering method, for example. Source electrode142is composed of titanium, aluminum, silicon, or the like, for example. After source electrode142is formed, source electrode142and recycle wafer100of silicon carbide are heated at a temperature of about 900° C. or more and 1100° C. or less, for example. Thereby, source electrode142and recycle wafer100of silicon carbide come into ohmic contact with each other. Then, an interconnection layer138is formed to come into contact with source electrode142(seeFIG.14). Interconnection layer138is composed of a material containing aluminum, for example. Subsequently, a back surface polishing step is performed. In the back surface polishing step, first silicon carbide layer21is removed. After first silicon carbide layer21is removed, a portion of silicon carbide substrate10is further removed. Thereby, the thickness of silicon carbide substrate10is reduced. Then, a drain electrode143is formed on first main surface1of silicon carbide substrate10. Drain electrode143is composed of an alloy containing nickel and silicon (for example, NiSi or the like), for example. Drain electrode143is formed to come into contact with silicon carbide substrate10at first main surface1. Then, the dicing step (S24:FIG.10) is performed. For example, recycle wafer100of silicon carbide is divided into a plurality of semiconductor chips by being diced along dicing lines. Thus, silicon carbide semiconductor device300is manufactured (seeFIG.15). It should be noted that, although the method for manufacturing the silicon carbide semiconductor device in accordance with the present disclosure has been described above by taking a planar MOSFET as an example, the manufacturing method in accordance with the present disclosure is not limited thereto. The manufacturing method in accordance with the present disclosure is applicable to silicon carbide semiconductor devices such as a trench MOSFET, an IGBT (Insulated Gate Bipolar Transistor), an SBD (Schottky Barrier Diode), a thyristor, a GTO (Gate Turn Off thyristor), a PN diode, and the like, for example. Next, the function and effect of the recycle wafer of silicon carbide and the method for manufacturing the silicon carbide semiconductor device in accordance with the present embodiment will be described. Recycle wafer100of silicon carbide in accordance with the present embodiment has silicon carbide substrate10and first silicon carbide layer21. Silicon carbide substrate10has first main surface1and second main surface2opposite to first main surface1. First silicon carbide layer21is in contact with first main surface1. In the case where first silicon carbide layer21is provided on the first main surface1side, when second silicon carbide layer22is formed on second main surface2by epitaxial growth, silicon carbide substrate10is sandwiched between first silicon carbide layer21and second silicon carbide layer22. Accordingly, in the thickness direction of silicon carbide substrate10, a stress acts in a direction in which it is balanced. This results in a reduction of the absolute value of the amount of change in warpage before and after second silicon carbide layer22is formed on second main surface2by epitaxial growth. In addition, recycle wafer100of silicon carbide in accordance with the present embodiment is manufactured by performing grinding and mechanical polishing on second main surface2with first silicon carbide layer21being in contact with first main surface1of silicon carbide substrate10. Since first main surface1is protected by first silicon carbide layer21, it is possible to suppress damage to first main surface1of silicon carbide substrate10. Further, according to the method for manufacturing silicon carbide semiconductor device300in accordance with the present embodiment, the transfer failure rate of recycle wafers100of silicon carbide in a transfer step can be reduced. Furthermore, according to the method for manufacturing the silicon carbide semiconductor device in accordance with the present embodiment, the suction failure rate of recycle wafers100of silicon carbide of wafers in an exposure step can be reduced. First Example (Preparation of Samples) First, recycle wafers100of silicon carbide in accordance with samples 1 and 2 were prepared. Recycle wafer100of silicon carbide in accordance with sample 1 served as an example. Recycle wafer100of silicon carbide in accordance with sample 2 served as a comparative example. Recycle wafer100of silicon carbide in accordance with sample 1 had silicon carbide substrate10and first silicon carbide layer21. Recycle wafer100of silicon carbide in accordance with sample 2 had silicon carbide substrate10but did not have first silicon carbide layer21. Recycle wafers100of silicon carbide in accordance with samples 1 and 2 were manufactured according to the method for manufacturing recycle wafer100of silicon carbide described above, except for the following point. Specifically, recycle wafer100of silicon carbide in accordance with sample 1 was manufactured by processing only one side (the second main surface2side) in the grinding step (S3:FIG.6), the mechanical polishing step (S4:FIG.6), and the chemical mechanical polishing step (S5:FIG.6) described above. Accordingly, first silicon carbide layer21was left without being removed. On the other hand, recycle wafer100of silicon carbide in accordance with sample 2 was manufactured by processing both sides (the first main surface1side and the second main surface2side) in the grinding step (S3:FIG.6), the mechanical polishing step (S4.FIG.6), and the chemical mechanical polishing step (S5:FIG.6) described above. Accordingly, first silicon carbide layer21was removed. Then, the nitrogen concentration in each recycle wafer100of silicon carbide was measured using secondary ion mass spectroscopy (SIMS). The measurement device was a secondary ion mass spectrometry device manufactured by Cameca. The measuring pitch was 0.01 μm. The nitrogen concentration was measured by penetrating recycle wafer100of silicon carbide from the back surface side toward the front surface side of recycle wafer100of silicon carbide. In recycle wafer100of silicon carbide in accordance with sample 1, a region 3 μm from the back surface was the region of first silicon carbide layer21. In recycle wafer100of silicon carbide in accordance with sample 2, a region 3 μm from the back surface was the region of silicon carbide substrate10. A minimum value of the nitrogen concentration in the region 3 μm from the back surface was defined as N2_min. In recycle wafer100of silicon carbide in accordance with sample 1, a position 3 μm away from the back surface toward the front surface is a boundary between first silicon carbide layer21and silicon carbide substrate10. In recycle wafer100of silicon carbide in accordance with sample 2, a position 3 μm away from the back surface toward the front surface is the region of silicon carbide substrate10. The average value and the standard deviation of the nitrogen concentration in a region from the position 3 μm away from the back surface toward the front surface to a position 13 μm away from the back surface toward the front surface were defined as N1_aveand σ(N1), respectively. As shown in Table 1, N1_ave, σ(N1) and N2_minof recycle wafer100of silicon carbide in accordance with sample 1 were 6.81×1018cm−3, 7.74×1016cm−3, and 2.31×1016cm−3, respectively. N1_ave, σ(N1), and N2_minof recycle wafer100of silicon carbide in accordance with sample 2 were 3.53×1018cm−3, 8.46×1016cm−3, and 3.36×1018cm−3, respectively. TABLE 1Sample No.Sample 1Sample 2First Silicon Carbide LayerPresentAbsentN1—ave(cm−3)6.81 × 10183.53 × 1018σ(N1) (cm−3)7.74 × 10168.46 × 1016N2—min(cm−3)2.31 × 10163.36 × 1018N1—ave-3 × σ(N1) (cm−3)6.58 × 10183.28 × 1018WARP before Epitaxial Growth (μm)41.622.2WARP after Epitaxial Growth (μm)32.759.1Amount of Change in WARP (μm)−8.9+36.9 (Evaluation Method) Next, warpage was measured before and after second silicon carbide layer22was formed on second main surface2of recycle wafer100of silicon carbide. First, warpage of recycle wafer100of silicon carbide before forming second silicon carbide layer22on second main surface2of recycle wafer100of silicon carbide was measured. Specifically, a WARP of recycle wafer100of silicon carbide before forming second silicon carbide layer22was measured. Subsequently, second silicon carbide layer22was formed on second main surface2of recycle wafer100of silicon carbide in accordance with each of samples 1 and 2 by epitaxial growth. Specifically, first, recycle wafer100of silicon carbide in accordance with each of samples 1 and 2 was placed within a chamber of a CVD apparatus, with second main surface2being exposed. Subsequently, a mixed gas containing silane, propane, nitrogen, and hydrogen was introduced into the chamber. On that occasion, the temperature within the chamber was maintained at about 1630° C. The thickness of second silicon carbide layer22was 10 μm. Subsequently, a WARP of recycle wafer100of silicon carbide after forming second silicon carbide layer22was measured. It should be noted that a WARP is one of the indicators of the magnitude of warpage, and is a value calculated as the sum of the distance from a three-point reference plane to the largest displacement value on one side with respect to the three-point reference plane and the distance from the three-point reference plane to the largest displacement value on the other side with respect to the three-point reference plane. The three-point reference plane is a plane passing through three measurement points inside a measurement region. The three measurement points are positions located inside by 3% of the diameter of the measurement region and located at 0°, 120°, and 240°. The measurement of the WARP was performed with Flatmaster manufactured by Tropel. (Evaluation Result) As shown in Table 1, the WARPs before and after forming second silicon carbide layer22on second main surface2of recycle wafer100of silicon carbide in accordance with sample 1 were 41.6 μm and 32.7 μm, respectively. The amount of change in WARP was −8.9 μm. On the other hand, the WARPs before and after forming second silicon carbide layer22on second main surface2of recycle wafer100of silicon carbide in accordance with sample 2 were 22.2 μm and 59.1 μm, respectively. The amount of change in WARP was +36.9 μm. According to the above results, it was confirmed that recycle wafer100of silicon carbide in accordance with sample 1 can reduce the absolute value of the amount of change in warpage before and after epitaxial growth, when compared with recycle wafer100of silicon carbide in accordance with sample 2. Second Example (Preparation of Samples) First, recycle wafers100of silicon carbide in accordance with samples 1 and 2 were prepared. Recycle wafers100of silicon carbide in accordance with samples 1 and 2 were the same as those described in the first example. Then, second silicon carbide layer22was formed on second main surface2of each recycle wafer100of silicon carbide. (Evaluation Method) The influence of first silicon carbide layer21during transfer of recycle wafer100of silicon carbide having second silicon carbide layer22formed on second main surface2was evaluated. Specifically, the transfer failure rate during manufacture of silicon carbide semiconductor devices was evaluated. The case where recycle wafer100of silicon carbide fell within a facility, and the case where recycle wafer100of silicon carbide was unable to be recognized, during transfer of recycle wafer100of silicon carbide, were regarded as transfer failures. A value obtained by dividing the number of recycle wafers100of silicon carbide having transfer failures by the number of all recycle wafers100of silicon carbide attempted to be transferred was defined as the transfer failure rate. In addition, the influence of first silicon carbide layer21during suction of recycle wafer100of silicon carbide having second silicon carbide layer22formed on second main surface2onto a chuck in an exposure step was evaluated. Specifically, the suction failure rate during manufacture of silicon carbide semiconductor devices was evaluated. The case where a suction pressure was less than a predetermined value during suction of recycle wafer100of silicon carbide was regarded as a suction failure. A value obtained by dividing the number of recycle wafers100of silicon carbide having suction failures by the number of all recycle wafers100of silicon carbide attempted to be suctioned was defined as the suction failure rate. (Evaluation Result) TABLE 2Sample No.Sample 1Sample 2First Silicon Carbide LayerPresentAbsentN1—ave(cm−3)6.81 × 10183.53 × 1018σ(N1) (cm−3)7.74 × 10168.46 × 1016N2—mm(cm−3)2.31 × 10163.36 × 1018N1—ave-3 × σ(N1) (cm−3)6.58 × 10183.28 × 1018Transfer Failure Rate (%)024Suction Failure Rate (%)213 As shown in Table 2, the transfer failure rates of recycle wafers100of silicon carbide in accordance with samples 1 and 2 were 0% and 24%, respectively. In addition, the suction failure rates of recycle wafers100of silicon carbide in accordance with samples 1 and 2 were 2% and 13%, respectively. According to the above results, it was confirmed that recycle wafer100of silicon carbide in accordance with sample 1 can reduce the transfer failure rate and the suction failure rate, when compared with recycle wafer100of silicon carbide in accordance with sample 2. It should be understood that the embodiment and the examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the scope of the claims, rather than the above description, and is intended to include any modifications within the scope and meaning equivalent to the scope of the claims. REFERENCE SIGNS LIST 1: first main surface;2: second main surface;3: third main surface;4: first inclined surface;5: third inclined surface;6: second inclined surface;7: outer peripheral surface;8: fourth main surface;9: fourth inclined surface;10: silicon carbide substrate;11: substrate region (first substrate region);12: second substrate region;21: first silicon carbide layer;22: second silicon carbide layer;23: third silicon carbide layer;31: fifth main surface;32: fifth inclined surface;100: recycle wafer of silicon carbide;131: drift region;132: body region;133: source region;134: contact region;136: oxide film;137: interlayer insulating film;138: interconnection layer;141: gate electrode;142: source electrode;143: drain electrode;300: silicon carbide semiconductor device; P1: position; S1: substrate receiving step; S2: epitaxial growth step; S3: polishing step; S4: mechanical polishing step; S5: chemical mechanical polishing step; T1: first thickness; T2: second thickness; T3: third thickness; T4: fourth thickness; a1: first horizontal length; a2: second horizontal length; a3: third horizontal length; a4: fourth horizontal length; a5: fifth horizontal length; b1: first vertical length; b2: second vertical length; b3: third vertical length; b4: fourth vertical length; b5: fifth vertical length; θ1: first angle; θ2: second angle; θ3: third angle; θ4: fourth angle. | 47,501 |
11862685 | Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of this disclosure. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of this disclosure, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness. The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of this disclosure. Hereinafter, while embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, it is noted that examples are not limited to the same. Throughout the present disclosure, the phrase that a certain element “comprises” or “includes” another element means that the certain element may further include one or more other elements but does not preclude the presence or addition of one or more other elements, unless stated to the contrary. Throughout the present disclosure, it will be understood that when an element is referred to as being “connected” to another element, it can be directly connected to the other element or intervening elements may be present. In this disclosure, “B being placed on A” means that B is placed in direct contact with A or placed over A with another layer or structure interposed therebetween and thus should not be interpreted as being limited to B being placed in direct contact with A, unless the description clearly dictates. In this disclosure, the phrase “combination(s) thereof” included in a Markush-type expression denotes one or more mixtures or combinations selected from the group consisting of components stated in the Markush-type expression, that is, denotes that one or more components selected from the group consisting of the components are included. In this disclosure, the description “A and/or B” means “A or B, or A and B.” In this disclosure, terms such as “first,” “second,” “A,” or “B” are used to distinguish the same terms from each other. The singular forms “a,” “an,” and “the” include the plural form unless the context clearly dictates otherwise. In this disclosure, a singular form is contextually interpreted as including a plural form as well as a singular form unless specially stated otherwise. Hereinafter, the present disclosure will be described in further detail. One object of the present disclosure is to provide a silicon carbide ingot and a wafer having a low retardation in a polarized light during a visible light irradiation, by controlling a value such as a density of an insulating material during a manufacturing process of the silicon carbide ingot and the wafer. Another object of the present disclosure is to provide a silicon carbide ingot and a wafer, whose defect value such as dislocation density is decreased and having excellent quality. The wafer according to the present disclosure has advantages of having a low retardation value, not including distortion or twist of a crystal, and showing a good crystal quality. Furthermore, the method of manufacturing the wafer according to the present disclosure can manufacture a silicon carbide ingot, which can secure a certain degree of retardation value, and whose defect density value is decreased, by applying an insulating material having certain density. Various factors such as a raw material, an atmosphere, and a condition applied in a manufacturing process affect a quality of an ingot and a wafer obtained from the process. A crystal quality, a degree of defect occurrence, a residual stress, and so on of an ingot and a wafer can affect a performance, properties, and a manufacturing process of devices, which are manufactured into a wafer. Accordingly, though the crystal quality, the residual stress, and the defect may be evaluated as separate factors, they may also be comprehensively evaluated quantitatively by measuring retardation. The inventors have conducted research on a method of manufacturing a silicon carbide ingot and a wafer having a better retardation distribution characteristic, reduced defects, and excellent crystal quality. The inventors have confirmed that among various factors, a temperature gradation and properties of an insulating material is important in growth of a silicon carbide when applying a physical vapor transport (PVT), and a silicon carbide ingot and a wafer with an excellent quality can be manufactured by controlling these conditions, and thus completed this invention. Wafer10 In one general aspect, the wafer10according to the present disclosure may have a retardation distribution measured with a light having a wavelength of 520 nm, and an average value of the retardation is 38 nm or less. The wafer10may have the average value of retardation measured with a light having a center wavelength of 520 nm entering the wafer in a thickness direction, and the average value of the retardation may be 38 nm or less. Referring toFIG.1, the wafer10may include one side11and the other side12, which are opposite to each other. The thickness direction may be a direction from the one side11to the other side12. The one side11of the wafer10is so-called Si surface, where silicon atoms mainly distributed on the surface, and the other side12as an opposite side of the one side11is so-called C surface, where carbon atoms mainly distributed on the surface. When cutting the wafer10, the wafer10may be easily cut in an interface between the layer of carbon atoms and the layer of silicon atoms, or in a direction parallel to the interface. Accordingly, a surface, where carbon atoms are mainly exposed, and another surface, where silicon atoms are mainly exposed, tend to exist on the cross section. Polishing of one side and/or the other side of a wafer may be performed during a process of manufacturing a wafer from an ingot. The wafer used for measuring retardation distribution may be a wafer, where both of the surfaces of the wafer are polished. Retardation distribution within a certain area may be measured by being visualized or quantified through a device such as WPA-200 or WPA-micro available from PHOTONIC LATTICE, INC. Example embodiments are based on the results measured with a light having a wavelength of 520 nm by applying WPA-200 available from PHOTONIC LATTICE, INC. The retardation refers to a value showing a difference of phases between before and after transmitting a polarized visible ray in a thickness direction of a target. When the target has residual stress, distortion, defects, or damage, variation occurs in the retardation distribution. Even though in a clear target not having a birefringence characteristic, the birefringence may be observed when a certain stress and distortion are applied to the target. Accordingly, evaluating a birefringence is one convenient method for evaluating residual stress and distortion quantitatively. Retardation distribution is a parameter related to a phase retardation value of a target, which may be generated when polarized light is transmitted through the target in a thickness direction thereof. Occurrence of a phase difference means that a polarized state is changed. Additionally, the phase difference may be generated by various causes. Birefringence is generally in proportion to retardation, such that retardation can be used as a parameter showing a degree of residual stress. Accordingly, when retardation distribution is within a certain range in an entire area, it means that the target has a stress regulated in the area. Particularly, when a target is formed with the substantially same material in a thickness direction, and the thickness of the target is substantially equal, the result can be more credible. However, retardation distribution may be affected by other factors besides residual stress. For example, retardation distribution may be changed by defects such as distortion and dislocation, and may also be affected by a degree of crystallinity in a case of a crystalline substance. Also, retardation distribution may be changed by defects such as a fine crack generated in a target. That is, evaluation of retardation distribution of a wafer may be considered to be a method for simultaneously evaluating a degree of residual stress, a presence of distortion and defects, excellence of crystal, presence of existing damage or a possible damage from an external impact, and may be used as a criteria for confirming whether various characteristics required for the wafer manufactured by the present disclosure are all excellent. The average value of the retardation of the wafer10may be 38 nm or less. The average value of the retardation of the wafer may be 30 nm or less, or 20 nm or less. The average value of the retardation of the wafer may be 15 nm or less. The average value of the retardation of the wafer may be 0.1 nm or more. The average value of the retardation of the wafer may be 5 nm or more. When the wafer has such a retardation value, distortion or defects of the inner crystal can be minimized, and the wafer has improved properties when applied as a semiconductor device. The maximum value of the retardation of the wafer10may be 60 nm or less, 45 nm or less, or 42.8 nm or less. The minimum value of the retardation of the wafer10may be less than 0.10 mm, 0.08 mm or less, or 0.02 mm or less. The standard deviation of the retardation of the wafer10in the direction of the thickness of the wafer may be 30 nm or less, 20 nm or less, or 12 nm or less. The deviation of retardation may be 1 nm or more. When the wafer has these maximum, minimum, and standard deviation of retardation, an inner lattice of the wafer has minimum distortion or defects, and the wafer can have constant distribution of the inner lattice. The wafer10may be prepared by cutting a silicon carbide ingot as described below. The wafer may have a rocking angle of −1.5° to 1.5°, −1.0° to 1.0°, −0.5° to 0.5°, or −0.3° to 0.3°. The wafer having such a characteristic can have an excellent crystalline characteristic. The rocking angle may be measured by a high-resolution X-ray diffraction analysis system (HR-XRD system) according to the following method. The [11-20] direction of the wafer is set to an X-ray route, the angles of X-ray source optic and X-ray detector optic are set to 2 θ (35° to 36°), omega (ω, or θ as an X-ray detector optic) angle is set to an off angle of the wafer to measure a rocking curve, and a differences between a peak angle as a reference angle and two full width at half maximum (FWHM) values are respectively set as the rocking angles to evaluate crystallinity. In the present disclosure, off angle is X° means having an off angle evaluated as X° within the margin of error generally permitted, and for example, includes an off angle in a range of (X°−0.05°) to (X°+0.05°). In addition, “a rocking angle is −1° to 1° compared to a reference angle” means that a full width at half maximum value is within a range of (peak angle−1°) to (peak angle+1°) based on the peak angle as a reference angle. Moreover, for the rocking angle, a surface except for a center and portions within 5 mm from the edges to the center are trisected to be substantially equal, and the results of measuring three times or more in respective portions were averaged to be considered as the above rocking angle. In detail, among wafers applied with an off angle, which is an angle selected in a range of 0° to 10° against (0001) surface of a silicon carbide ingot, when the off angle is 0°, the omega angle is 17.8111°, when the off angle is 4°, the omega angle is 13.811°, and when the off angle is 8°, the omega angle is 9.8111°. The wafer10may have a full width at half maximum value (FWHM) of rocking curve of 30 arcsec or less, or 27.4 arcsec or less according to XRD analysis. The wafer10may have FWHM of rocking curve of 3.5 arcsec or more according to XRD analysis. When a defect is present in a crystal of a wafer, a strength of a diffracting X-Ray shows gaussian distribution and this is referred to as a rocking curve. The FWHM of a rocking curve has a unit of arcsec, and when the FWHM is large, it may be considered as having many crystal defects. The wafer having above ranges of the FWHM may exhibit excellent crystallinity and improve properties of devices manufactured from the same. The wafer10may have a micropipe (MP) density of 1.5/cm2or less, or 1/cm2or less. The wafer10may have a threading edge dislocation (TED) density of 10,000/cm2or less, or 8,000/cm2. The wafer10may have a basal plane dislocation (BPD) density of 5,000/cm2or less, or 3,000/cm2or less. The thickness of the wafer10may be 150 μm to 900 μm, or 200 μm to 600 μm, but not limited thereto, and any proper thickness applicable to a semiconductor device can be applied. The wafer10may be a silicon carbide wafer, and may be a wafer substantially including a 4H silicon carbide, which is a single crystal. The diameter of the wafer10may be 4 inch or more, 5 inch or more, or 6 inch or more. The diameter of the wafer may be 12 inch or less, or 10 inch or less. The entire Ra average roughness of one side11of the wafer10may be less than 0.3 nm, or 0.2 nm or less. The entire Ra average roughness of the one side11may be 0.01 nm or more. A wafer having these ranges of roughness can improve electric properties, when manufactured into a device through subsequent processes. The wafer10may be manufactured by the method of manufacturing the wafer described below. Method of Manufacturing the Wafer In another general aspect, the method of manufacturing the wafer according to example embodiments includes, a preparation step of disposing a raw material300and a silicon carbide seed crystal to face each other in an inner space of a reactor200; a growing step of adjusting a temperature, a pressure, and an atmosphere of the inner space to sublimate the raw material, and thereby preparing a silicon carbide ingot grown from the seed crystal; a cooling step of cooling the reactor200and retrieving the silicon carbide ingot; a cutting step of cutting the retrieved silicon carbide ingot thereby preparing a wafer; and a processing step of flattening a thickness of the prepared wafer and polishing a surface of the wafer, wherein the reactor includes an insulating material surrounding an external surface of the reactor200and a heater for adjusting a temperature of the reactor or the temperature of the inner space, and a density of the insulating material is 0.14 g/cc to 0.28 g/cc. The preparation step is for disposing the raw material300and the silicon carbide seed crystal to face each other in the reactor200having the inner space. The silicon carbide seed crystal in the preparation step may be one with a proper size depending on a desired wafer, and a C surface ((000-1) surface) of the silicon carbide seed crystal can be toward a direction of the raw material300. The raw material300in the preparation step may be a powder form having carbon sources and silicon sources, and the powder may be a material treated by necking from each other or a silicon carbide powder, whose surface is treated with carbonization. The reactor200in the preparation step may be any container, which is proper for growing reaction of a silicon carbide ingot, and for example, a graphite crucible may be applied. Specifically, the reactor200may include a body210including an inner space and an opening part, and a cover220corresponding the opening part and thereby closing the inner space. The crucible cover may further comprise a seed crystal holder in one body or separated with the crucible cover, and can fix a silicon carbide seed crystal to allow a silicon carbide seed crystal and a material to face each other through the seed crystal holder. The reactor200in the preparation step may be surrounded and fixed by an insulating material400, the insulating material400surrounding the reactor may be placed inside a reaction chamber500like a quartz tube, and the temperature of the inner space of the reactor200may be controlled by a heater600disposed outside of the insulating material400and the reaction chamber200. The insulating material400in the preparation step may have a coefficient of thermal expansion of 2.65×10−6/° C. to 3.05×10−6/° C., 2.7×10−6/° C. to 3×10−6/° C., or 2.75×10−6/° C. to 2.9×10−6/° C. at 1000° C. The coefficient of thermal expansion may be an average of coefficients of thermal expansion in a first direction, which is one direction of the insulating material, a second direction perpendicular to the first direction, and a third direction perpendicular to the first direction and the second direction. By applying an insulating material having such a coefficient of thermal expansion, a proper distribution of residual stress can be obtained through establishing even distribution of temperature gradient, and retardation distribution measured with a visible ray in a thickness direction of the wafer can have a good value. The coefficient of thermal expansion can be obtained by measuring length variation depending on a unit temperature. In detail, it can be obtained by cutting the insulating material as a measuring target in a size of 5×5×5 mm3for preparing a measuring sample, and measuring length variation against the unit temperature by using TMA Q400 available from TA INSTRUMENTS INC, and the coefficient of thermal expansion may be a value at 1000° C. The insulating material400in the preparation step may have a porosity of 72% to 95%, 75% to 93%, or 80% to 91%. When applying the insulating material satisfying the above porosity, it is possible to decrease crack occurrence of the silicon carbide ingot to be grown. The insulating material400in the preparation step may have a compressive strength of 0.2 MPa or more, 0.48 MPa or more, or 0.8 MPa or more. Also, the insulating material400may have a compressive strength of 3 MPa or less, or 2.5 MPa or less. When the insulating material has such a compressive strength, it is possible to manufacture a silicon carbide ingot excellent in thermal/mechanical stability and having a more excellent quality due to a decreased possibility of generating ash. The insulating material400in the preparation step may include a carbon-based felt, and in detail, may include a graphite felt, a rayon-based graphite felt, or a pitch-based graphite felt. The insulating material400in the preparation step may have a density of 0.14 g/cc or more, 0.16 g/cc or more, or 0.17 g/cc or more. The insulating material may have a density of 0.28 g/cc or less, 0.24 g/cc or less, or 0.20 g/cc or less. With the insulating material having the above density ranges, a bend and a twist can be prevented in an ingot to be manufactured, and a good retardation value can be obtained in a wafer manufactured from the ingot. The reaction chamber500in the preparation step may include a vacuum exhauster700connected to the internal space of the reaction chamber500, which regulates a vacuum degree of the internal space of the reaction chamber500, a pipe810connected to the internal of the reaction chamber500and allowing an inert gas to flow into the internal space of the reaction chamber500, and a mass flow controller800for controlling the flow of the inert gas. Through them, the flow rate of an inert gas can be regulated in subsequent growing step or cooling step. The growing step is for adjusting the temperature, the pressure, and the air atmosphere of the inner space of the reactor200to sublime the raw material and thereby preparing a silicon carbide ingot grown from the seed crystal. The growing step can proceed by the heater600heating the reactor200and the inner space of the reactor200, and can induce growing of a silicon carbide crystal by depressurizing the inner space simultaneously or separately from the heating to adjust a vacuum degree of the inner space and by introducing an inert gas into the inner space. The growing step may proceed in a condition of a temperature of 2000° C. to 2600° C. and a pressure of 1 torr to 200 torr, and it is possible to manufacture a silicon carbide ingot more efficiently in the above ranges of temperature and pressure. In detail, the growing step may proceed in a condition, in which temperatures at surfaces of an upper and a lower portions of the reactor200are 2100° C. to 2500° C., and a pressure of the inner space of the reactor200is 1 torr to 50 torr, and in further detail, in a condition in which the temperatures at the surfaces of the upper and the lower portion of the reactor200are 2150° C. to 2450° C., and a pressure of the inner space of the reactor200is 1 torr to 40 torr, and more specifically, in a condition, in which the temperatures at the surfaces of the upper and the lower portion of the reactor200are 2150° C. to 2350° C., and the pressure of the inner space of the reactor200is 1 torr to 30 torr. When the condition of temperature and pressure above is applied to the growing step, a silicon carbide ingot in a higher quality can be manufactured. The growing step may allow heating to proceed at a heating rate of 1° C./min to 10° C./min, or 5° C./min to 10° C./min until reaching the above temperature range. In the growing step, an inert gas may be added in a fixed flow rate to an outside of the reactor200. The inert gas may flow in the inner space of the reactor200, and may flow in a direction from the raw material300to the silicon carbide seed crystal. Accordingly, a stable temperature gradient can be formed in the reactor200and the inner space of the reactor200. The flow rate of the inert gas in the growing step may be 70 sccm or more, or 330 sccm or less. In this range for the flow rate of the inert gas, defect occurrence of the ingot manufactured can be minimized, and a desired retardation value can be achieved by forming effective temperature gradient of the reactor and the inner space. Specifically, the inert gas in the growing step may be an argon, a helium, or a mixture thereof. The cooling step is for cooling the grown silicon carbide ingot at a specific cooling rate and a flow rate of the inert gas. The cooling step may allow cooling to proceed in a rate of 1° C./min to 10° C./min, or 1° C./min to 5° C./min. The cooling step may simultaneously regulate the pressure of the inner space of the reactor200, or the pressure may be regulated separately from the cooling step. The pressure may be regulated to have maximum 760 torr for the inner space. The flow rate of the inert gas in the cooling step may be 1 sccm or more, or 300 sccm or less. Crack occurrence can be prevented, and the quality degradation can be minimized in an ingot manufactured in this range of the flow rate. In the cooling step, an inert gas may be added in a fixed flow rate to the outside of the reactor200like in the growing step. The inert gas may flow in the inner space of the reactor200, and may flow in a direction from the raw material300to the silicon carbide seed crystal. The cutting step is for cutting the silicon carbide ingot retrieved after the cooling step and thereby preparing a wafer. Through the cutting step, the silicon carbide ingot can be cut in a fixed off angle with the (0001) surface of the silicon carbide ingot or a surface, where growing has started in the silicon carbide ingot. The off angle in the cutting step may be 0° to 10°. The cutting step may allow the thickness of the wafer to be 150 μm to 900 μm, or 200 μm to 600 μm, but the present disclosure is not limited thereto. The processing step is for flattening the thickness of the wafer prepared through the cutting step and polishing the surface of the wafer. The process for flattening the thickness may be accomplished by applying wheel grinding to both sides of the wafer one by one. A polishing material used for the wheel grinding may be a diamond polishing material. Through the process of flattening the thickness in the processing step, damage and stress added to the wafer in the cutting step are reduced and the wafer is made to be flat. The process of polishing the surfaces in the processing step may further include a chemical mechanical polishing (CMP). The chemical mechanical polishing process may be performed by adding slurry of polished particles on a rotating plate and contacting the fixed wafer with a rotating polishing head at a certain pressure. A washing step using a general RCA chemical washing solution may be further performed after the processing step. Silicon Carbide Ingot100 In still another general aspect, the silicon carbide ingot100according to the present disclosure may include, a first surface110and a second surface120opposite to the first surface, wherein the first surface is defined as an upper portion of the silicon carbide ingot and may be a flat surface or a convex surface, wherein a wafer may be prepared in a portion below the first surface, and wherein the wafer may have retardation distribution measured with a light having a wavelength of 520 nm and an average value of the retardation may be 35 nm or less. The silicon carbide ingot100is grown from a raw material inside a reactor, which is sublimed and recrystallized on a silicon carbide seed crystal. Referring toFIG.3, a surface facing the raw material among surfaces of the silicon carbide ingot after being completion of the growing may be the first surface110, and the first surface110may have a curved convex surface or a flat surface. The silicon carbide ingot100may include a body121and a convex part111extended from the body and having a convex surface. When the convex surface of the silicon carbide ingot is designated as an upper portion, a portion below the convex surface may correspond to the body. That is, when the first surface110of the silicon carbide ingot is designated as an upper portion, a bottom surface, where the growing of the silicon carbide ingot has started, may be designated as the second surface120and be designated as a lower portion, and a portion below the first surface may be cut in a fixed thickness to prepare a wafer. At this time, a certain off angle may be applied with the second surface120or (0001) surface of the silicon carbide ingot. In addition, the process of preparing the wafer may include, trimming an outer diameter of the silicon carbide ingot100in a direction from the outer diameter to an inner diameter using a grinding device, cutting the silicon carbide ingot in a certain thickness and with a fixed off angle against the second surface120or (0001) surface of the silicon carbide ingot, grinding the edges, grinding the surface, and a processing such as polishing. The silicon carbide ingot100may be grown from a C surface ((000-1) surface) of a silicon carbide seed crystal. The silicon carbide ingot100may be manufactured through a crucible satisfying a certain thermal conductivity in a growing step and a cooling step during the manufacture. Hereinafter, the present disclosure will be described in further detail by specific embodiments. The below embodiments are for illustration only and the scope of the present application is not limited thereto. Example 1—Manufacture of Wafer As being illustrated inFIG.2, a silicon carbide powder as a material was charged in a lower portion of an inner space of a reactor200, and a silicon carbide seed crystal was disposed in an upper portion thereof. At this time, a silicon carbide seed crystal consisting of a 4H—SiC crystal with 6 inch was used, and C surface ((000-1) surface) of the silicon carbide seed crystal was faced toward the silicon carbide raw material in a lower portion of the inner space using a conventional method. Similar process was applied to the examples and the comparative examples described below. A reactor200was sealed up, the outside thereof was surrounded with an insulating material400having a density of 0.15 g/cc and a coefficient of thermal expansion of 2.80×10−6/° C., and after that the reactor was disposed inside a quartz tube500, which is equipped with a heating coil as the heater600at the outside of the quartz tube500. The inner space of the reactor200was depressurized to a vacuum atmosphere, argon gas was introduced to the inner space to reach 760 torr, and the inner space was depressurized again. At the same time, the temperature of the inner space was heated to 2300° C. at a heating rate of 5° C./min, and the flow rate of argon gas inside a quartz tube was adjusted through a pipe and a vacuum degassing device700connected to the quartz tube500. A silicon carbide ingot was allowed to be grown on a surface of a silicon carbide seed crystal opposite to a silicon carbide raw material for 100 hours under a temperature of 2300° C. and a pressure of 20 torr. After growing of the silicon carbide ingot, the temperature of the inner space was cooled to 25° C. at a rate of 5° C./min, and at the same time, the pressure of the inner space was set to be 760 torr. A wafer sample, which was cut to have an off angle of 4° against (0001) surface of the cooled silicon carbide ingot and had a thickness of 360 μm, was prepared, the edge of this wafer was ground by 5% against the maximum outer diameter, and subsequently chemical mechanical polishing and RCA washing was performed. Example 2—Manufacture of Wafer A wafer was manufactured by the same method as the Example 1, except that the density of the insulating material was 0.16 g/cc and the coefficient of thermal expansion was 2.75×10−6/° C. Example 3—Manufacture of Wafer A wafer was manufactured by the same method as the Example 1, except that the density of the insulating material was 0.17 g/cc and the coefficient of thermal expansion was 2.9×10−6/° C. Comparative Example 1—Manufacture of Wafer A wafer was manufactured by the same method as the Example 1, except that the density of the insulating material was 0.13 g/cc and the coefficient of thermal expansion was 2.6×10−6/° C. Comparative Example 2—Manufacture of Wafer A wafer was manufactured by the same method as the Example 1, except that the density of the insulating material was 0.29 g/cc and the coefficient of thermal expansion was 3.1×10−6/° C. Experimental Example—Measurement of Retardation and the Full Width at Half Maximum Value of Wafer The prepared wafer samples were measured for the average value, the minimum value, and the maximum value of retardation in a thickness direction of a wafer by using WPA-200 device (available from PHOTONIC LATTICE, INC) with a light having wavelength of 520 nm, and the results were shown in Table 1 and Table 4. And then, the FWHMs of the rocking curve of the wafer samples were measured through a XRD analyzing device (SmartLab X-ray Diffractometer available from RIGAKU), and the results were shown in Table 1. TABLE 1TheAverageof the FullDensityCoefficientTheTheWidth atofof ThermalTheMinimumMaximumHalfInsulatingExpansionAverage ofValue ofValue ofMaximumMaterial(×10−6)/° C.RetardationRetardationRetardationValue(g/cc)(@1000° C.)(nm)(nm)(nm)(arcsec)Example 10.152.80200.0125.06—Example 20.162.75190.0842.7427.4Example 30.172.9150.0242.7226.7Comparative0.132.6400.1269.2765.3Example 1Comparative0.293.1410.1080.66—Example 2 Referring to Table 1, it was confirmed that the Examples having the density of the insulating material within a range of 0.14 g/cc to 0.28 g/cc, and the coefficient of thermal expansion within a range of 2.65×10−6/° C. to 3.05×10−6/° C. had a retardation value of 35 nm or less and the FWHM of the X-Ray rocking curve of 30 arcsec or less, such that the Examples show excellent crystal quality, whose residual stress distribution was good and whose distortion occurrence, defects, and so on were reduced, compared to the Comparative examples having a density of insulating material and a coefficient of thermal expansion outside these ranges. While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure. | 33,898 |
11862686 | DETAILED DESCRIPTION OF EMBODIMENTS Various embodiments of the present invention will be described below. In the drawings and descriptions below, same or similar elements or parts are labeled by same or similar referend characters. The drawings are for illustration purposes only, and various dimensional ratios, such as relationships between the thickness and horizontal dimensions and the ratios of various dimensions of respective devices or parts, may differ from actual devices or constructions. Specific dimensions, such as thickness, etc., should be understood by referring to the corresponding descriptions below. Also, even among the drawings, the ratios of the dimensions of various parts may differ from each other. In the descriptions below, the positive direction along the Z-axis may be referred to as “up” and the negative direction thereof may be referred to as “down.” Further, “up” and “down” may not necessarily mean directions along a vertical direction with respect to the ground. That is, the directions of “up” and “down” may not be limited relative to the direction of the gravity. The expressions “up” and “down” are merely used for convenience in order to specify relative positional relationship among regions, layers, films, and substrates, etc., and do not unduly limit the scope of the present invention. For example, if a sheet is rotated 180 degrees, “top” becomes “bottom, and “bottom” becomes “top” needless to say. Furthermore, in the below descriptions, “+” or “−” attached to p or n indicate relatively higher or lower impurity concentration as compared with p or n without these symbols. However, even if two layers have the same letter p assigned thereto, for example, that does not mean that these two layers have the exact same impurity concentrations. First Embodiment FIG.1is a plan view of a GaN semiconductor device100according to a first embodiment of the present invention.FIG.1is a X-Y plane plan view. Here, the X-axis and Y-axis directions are parallel to a first primary surface10aof a GaN substrate10, which will be described below. The Z-axis direction is perpendicular to the first primary surface10aand is a direction along which a depth of GaN semiconductor device100is defined. The Z-axis direction is also a direction in which the depth of a gallium nitride layer20(GaN layer) is defined. The X-axis, the Y-axis, and the Z-axis are perpendicular to each other. The GaN semiconductor device100is an example of a nitride semiconductor device of the present invention. As shown inFIG.1, the GaN semiconductor device100has an active region110and an edge termination region130. The active region110is a region in which current flows in the depth direction of the GaN semiconductor device100where vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is arranged. The active region110has a gate pad112and a source pad114. The gate pad112and the source pad114are electrode pads that are connected to a gate electrode62and a source electrode68, respectively, which are described below with reference toFIG.2. In a plan view, as seen in the negative Z-axis direction, the edge termination region130surrounds the periphery of the active region110and has a guard ring structure in which a plurality of thin p-type regions40(seeFIG.2described below) surround the active region110in a ring-shaped manner. The edge termination region130provides a function of preventing electric field concentration (i.e., field relaxation) in the active region110by expanding the depletion region generated in the active region110to the edge termination region130. FIG.2is a cross-sectional view of the GaN semiconductor device100according to the first embodiment of the present invention.FIG.2is a cross section taken along the line A-A′ ofFIG.1. As shown inFIG.2, the GaN semiconductor device100has a gallium nitride substrate10(GaN substrate), a GaN layer20provided on a first primary surface10aof the GaN substrate10, a gate insulating film60provided on the GaN layer20, a gate electrode62provided on the gate insulating film60, an interlayer insulating film64on the GaN layer20, covering the gate electrode62, a source electrode68provided on the interlayer insulating film64, and a drain electrode70provided on a second primary surface10bof the GaN substrate10. The GaN substrate10is a GaN single crystalline substrate. The GaN substrate10is an n-type substrate. It may be an n+ substrate, for example. The GaN substrate10has the first primary surface10aand the second primary substrate10bthat is opposite to the first primary substrate10a. For example, the GaN substrate10is a self-supporting, low dislocation density substrate having a dislocation density less than 1.0×107cm−2. Due to the low dislocation density of the GaN substrate10, the dislocation density of the GaN layer20formed on the GaN substrate10becomes low as well. By using the GaN substrate10having such a low dislocation density, even when a large area power device is formed on the GaN substrate10, the device has a small leakage current. Because of this, the power devices can be manufactured at a high yield. Moreover, a thermal treatment can prevent undesirable deep diffusion of ion-implanted impurities along dislocations. The GaN layer20is epitaxially formed on the first primary surface10aof the GaN substrate10. The GaN layer20is an n type layer, and may be an n+ layer, for example. The n-type impurities in the GaN layer20may be silicon (Si), germanium (Ge) or oxygen (O) or their combinations. In this embodiment, Si is used as an example of the n-type impurity. In the GaN layer20, the donor concentration Nd obtained by offsetting the n-type impurity concentration with compensating impurity concentrations is equal to or greater than 1.0×1015cm−3and less than or equal to 5.0×1016cm−3, for example. It may be 1.0×1016cm−3, for example. The compensating impurity may be carbon (C), for example. The thickness of the GaN layer20(i.e., the distance from the primary surface10aof the GaN substrate10to the surface20aof the GaN layer20) is equal to or greater than 1 μm and less than or equal to 50 μm, for example. It may be 10 μm, for example. The surface20aof the GaN layer20is an example of the “first primary surface) of the present disclosure. The gate insulating film60is made of silicon oxide (SiO2film), for example. The gate electrode62is made of polysilicon (Poly-Si) doped with impurities. The interlayer insulating film64is made of SiO2, for example. The thickness of the interlayer insulating film64is equal to or greater than 0.5 μm and less than or equal to 1 μm, for example. The source electrode68is in contact with a source region24and a contact region26through the contact hole64H formed in the interlayer insulating film64. The source electrode68is made of a Ti layer at the contacting surface and Al or Al alloy (for example, Al—Si, which is an alloy of Al and Si) at the other portions. The source electrode68may also function as the source pad114(FIG.1). The drain electrode70is in contact with the second primary surface10bof the GaN substrate10. The drain electrode70is made of a Ti layer at the contacting surface and Al or Al alloy (for example, Al—Si, which is an alloy of Al and Si) at the other portions. In the GaN layer20in the active region110, a p−well region22, an n+source region24, and a p+contact region26are provided. The well region22is formed on a surface side of the GaN layer20. A channel of the MOSFET is formed in a region at and adjacent to the surface of the well region22that is directly under the gate electrode62through the gate insulating film60. The source region24and the contact region26are arranged inside of the well region22. The source region24and the contact region26contact with each other. In the GaN layer20in the edge termination region130, an N injected region30(“defect region” or “element high density region”) and p-type regions40within the N injected region30are provided. The p-type region40includes an Mg injected region41(“first p-type region”) and an Mg diffused region42(“second p-type region”) at the periphery of the Mg injected region41. The N injected region30is a region in which nitrogen (N) atoms are injected by ion implantation. The concentration of nitrogen in the N injected region30is higher than that in a region surrounding the N injected region30. The nitrogen concentration in the N injected region30is equal to or greater than 1.0×1018cm−3and less than or equal to 1.0×1019cm−3, for example. The nitrogen here is an example of “an impurity other than p-type impurities and n-type impurities.” The Mg injected region41is a region in which magnesium (Mg) is injected by ion implantation. The Mg concentration in the Mg injected region41is higher than that in a region surrounding the Mg injected region41. The Mg diffused region is a region in which Mg injected in the Mg injected region41is thermally diffused. The Mg concentration in the Mg diffused region is higher than that in the N injected region and is lower than that in the Mg injected region41. FIG.3is an exemplary depth profile of the Mg concentration in the GaN semiconductor device100according to the first embodiment of the present invention. InFIG.3, the horizontal axis shows a depth from the surface20aof the GaN layer20in the unite of nm, and the vertical axis shows concentrations of elements contained in the GaN layer20in the unit of cm−3.FIG.3shows Mg concentrations along the line B-B′ ofFIG.2As shown inFIG.3, the Mg concentration in the Mg diffused region42is roughly constant in the depth direction; in this example, it is roughly constant in a range equal to or greater than 1.0×1018cm−3and less than or equal to 1.0×1019cm−3. Furthermore, in the depth direction of the GaN layer20, the Mg concentration drastically changes at the boundary between the Mg injected region41and the Mg diffused region42and at the boundary between the Mg diffused region42and the N injected region30. Here, inFIG.3, the broken line indicates the Mg concentration immediately after the ion implantation, and the dash-dot line indicates the N concentration immediately after the ion implantation. The Mg concentration indicated by the broken line and the N concentration indicated by the dash-dot line will be explained below. FIG.4is an exemplary Mg concentration distribution in the vicinity of the surface20aof the GaN layer20in the horizontal direction in the GaN semiconductor device100according to the first embodiment of the present invention. InFIG.4, the horizontal axis shows horizontal positions in the GaN layer20, and the vertical axis shows the Mg concentration (cm−3). As shown inFIG.4, the Mg concentration in the Mg diffused region42is roughly constant along the horizontal direction of the GaN layer20. The Mg concentration drastically changes at the boundaries between the Mg injected region41and the Mg diffused region42and at the boundaries between the Mg diffused region42and the N injected region30. The distance d1shown inFIG.2, which is the distance from the surface20aof the GaN layer20to the bottom of the Mg injected region41(i.e., the thickness of the Mg injected region41), is equal to or greater than 10 nm and less than or equal to 100 nm, for example. The distance d2, which is the distance from the bottom of the Mg injected region41to the bottom of the Mg diffused region42(i.e., the thickness of the Mg diffused region directly under the Mg injected region41) is equal to or greater than 100 nm and less than or equal to 1000 nm, for example. The distance d3, which is the distance from the bottom of the Mg diffused region42to the bottom of the N injected region30(i.e., the thickness of the N injected region30directly under the Mg diffused region42) is equal to or greater than 50 nm and less than or equal to 500 nm, for example. The length L1shown inFIG.2, which is the length of the Mg diffused region42at the surface20aof the GaN layer20(i.e., the diffusion length of Mg in the Mg injected region41in the horizontal direction) is equal to or greater than 100 nm and less than or equal to 1000 nm, for example. The horizontal direction here is a direction in the X-Y plane and perpendicular to the Z-axis. The interval L2, which is the spacing between the adjacent two Mg diffused regions42at the surface20aof the GaN layer20, is equal to or greater than 0.2 μm and less than or equal to 1 μm, for example. The guard ring structure in the edge termination region130includes a plurality of p-type regions40each having the Mg injected region41and the Mg diffused region42. With the plurality of p-type regions40surrounding the active region110in ring shapes, the electric field at the periphery of the active region110is relaxed, thereby ensuring the high withstand voltage of the GaN semiconductor device100. To enhance the field relaxation function by the guard ring structure, the Mg injected region41and the Mg diffused region42, which constitute the p-type region40, are preferably designed as follows. The Mg concentration in the Mg injected region41in the vicinity of the surface20apreferably is equal to or greater than 1.0×1019cm−3. The Mg concentration in the Mg diffused region42preferably is equal to or greater than 1.0×1017cm−3and less than or equal to 1.0×1019cm−3, and more preferably is equal to or greater than 1.0×1018cm−3and less than or equal to 1.0×1019cm−3. The Mg diffused region42preferably has a width of 100 nm or greater in the depth and horizontal directions at the periphery of the Mg diffused region41. That is, the above-mentioned distances d2and L1are both preferably equal to or greater than 100 nm. Further, the width of a region between the Mg diffused region42and the N injected region30, in which the Mg concentration changes from greater than or equal to 1.0×1018cm−3to equal to or less than 1.0×1017cm−3(i.e., the Mg concentration decreases to 1/10thor less), is preferably equal to or less than 100 nm, and more preferably is equal to or less than 50 nm. The p-type region40, which is constructed of the Mg injected region41and the Mg diffused region42, is preferably provided in a plurality and repeatedly arranged in the horizontal direction. The interval L2between the Mg diffused regions42is preferably 1 μm or less, and more preferably 0.5 μm or less. The number of the p-type regions40and the distance L2may be appropriately designed in accordance with the target withstand voltage required for the guard ring structure. <Manufacturing Method for GaN Semiconductor Device> A manufacturing method for the GaN semiconductor device100according to an embodiment of the present invention will be described.FIGS.5to10are cross-sectional views for explaining various steps in the manufacturing method of the GaN semiconductor device100of the first embodiment in the order they are performed. The GaN semiconductor device100is manufactured by various manufacturing apparatus, such as film formation apparatus, exposure apparatus, etching apparatus, ion-implantation apparatus, and thermal treatment apparatus. As shown inFIG.5, the GaN layer20is formed on the GaN substrate10. For example, an n GaN layer20is epitaxially grown on an n+GaN substrate10using an apparatus for Metal Organic Chemical Vapor Deposition (MOCVD), Halide Vapor Phase Epitaxy (HVPE) or the like. Next, Mg and Si are locally injected into the GaN layer20in the active region110(seeFIG.2) by photolithography and ion-implantation. For example, Mg is ion-implanted into a region22′, which will become the p−well region22(seeFIG.2). Si is ion-implanted into a region24′, which will become the n+source region24(seeFIG.2). Mg is ion-implanted into a region26′, which will become the p+contact region26(seeFIG.2). The order for the respective ion-implantation processes for the respective ions for the regions22′,24′ and26′ is not particularly limited, and these ion-implantation processes may be performed in any order. Next, as shown inFIG.6, nitrogen (N) is locally ion-implanted into the GaN layer20in the edge termination region130(seeFIG.2) by photolithography and ion implantation. Here, the N atoms are ion-implanted into a region30′(an example of the “first region”), which becomes the N injected region30. In the N ion implantation process, multiple ion implantations with varying implantation energies and injection amounts may be performed so that the injected N concentration is roughly constant from the surface20aof the GaN layer20up to a depth of 300 nm, for example, as shown in the dash-dot line inFIG.3. By the N ion implantation, crystal defects are introduced into the region30′. Next, as shown inFIG.7, Mg is locally injected into the GaN layer20in the edge termination region130(seeFIG.2) by photolithography and ion implantation. Here, Mg is injected in to a region(s)41′ (an example of the “second region”), which will become the Mg injected region(s)41. In the Mg ion implantation process, as indicated by the dotted line in FIG.3, the implantation energy is set such that the injection peak of Mg is located sufficiently shallower than the injection depth of N atoms (which is, for example, a depth of 300 nm from the surface20aof the GaN layer20). The injection peak of Mg is formed between the surface20aof the GaN layer20and the deepest injection peak of N atoms. That is, the Mg implantation energy is set such that the Mg injection peak is located within the N injected region. Also, it is preferable to set the Mg implantation energy such that the Mg injection peak is located at a position close to the surface20aof the GaN layer20. This way, the distance d2shown inFIG.2can be made large. Here, the order of the above-mentioned N ion implantation process for the region30′ and the above-mentioned Mg ion implantation process for the region41′ is not limited and they may be performed in any order. The Mg ion implantation may be performed after the N ion implantation, or the N ion implantation may be performed after the Mg ion implantation. Next, as shown inFIG.8, a passivation film50is formed on the GaN layer20. The passivation film50prevents Si, Mg, and N atoms from discharging from the GaN layer20. At sites from which N atoms are discharged will form nitrogen vacancies. Because the nitrogen vacancies could function as donor defects, the realization of p-type property may be inhibited by them. To prevent this, the passivation film50is formed on the GaN layer20. Here, the passivation film50may be formed on an insulating film (not shown in the figure) previously formed on the GaN layer20. Furthermore, the passivation film50may be formed not only on the GaN layer20, but also on a side of the second primary surface10bof the GaN substrate10. The passivation film50preferably has properties of a high thermal resistance and a high adhesiveness with an insulating film, and should not allow its impurities to diffuse into the GaN layer20side. The passivation film50in the GaN layer20also preferably has an etching selectivity with respect to the GaN layer20. The passivation film50may be an aluminum nitride (AlN) film, an SiO2film, or a silicon nitride (SiN) film. For example, it is an AlN film with a thickness of 300 nm. Next, a thermal treatment is performed on a multilayered boy that includes the GaN substrate10and the GaN layer20. The conditions for the terminal treatment are, for example, in a nitrogen atmosphere, at 1300° C., for 5 minutes. Due to this thermal treatment, Si and Mg that have been ion-implanted into the GaN layer20are activated. As a result, as shown inFIG.9, the p−well region22, the n+source region24, the p+contact region26, the N injected region30, the Mg injected regions41, and the Mg diffused regions42are formed in the GaN layer20. The Mg diffused regions42are formed by activation of Mg that has been thermally diffused from the Mg injected region41into the region30′ that have crystal defects due to the N ion implantation. Next, the passivation film50is removed from the GaN layer20, as shown inFIG.9. As shown inFIG.10, next, a gate insulating film60, a gate electrode62, an interlayer insulating film64, and a contact hole64H are formed on the GaN layer20. Next, a source electrode68(seeFIG.2) is formed to fill in the contact hole64H. Through these manufacturing steps, the GaN semiconductor device100, as shown inFIG.2, is completed. As explained above, the manufacturing method for the GaN semiconductor device100according to the first embodiment includes: ion-implanting nitrogen atoms (N) in a region30′ that is locally positioned on a side of the surface20aof the GaN layer20; ion-implanting magnesium (Mg), which is an example of p-type impurities, into a region41′ that is locally positioned in the region30′ that has been N ion-implanted; and performing a thermal treatment on the GaN layer20, which has been N and Mg ion-implanted. In the thermal treatment process, Mg is thermally diffused from the region41′ that has been ion implanted with Mg into a region42′, which is within the N ion-implanted region30′ and which surrounds the region41′. According to the manufacturing method of the first embodiment, the region30′, which is locally positioned on the side of the surface20aof the GaN layer20, contains a high concentration of crystal defects due to the N ion implantation, as compared with other regions of the GaN layer20. Mg is ion-implanted into this high defect density region and the ion-implanted Mg is thermally diffused by a thermal treatment. Mg diffuses more in GaN having crystal defects than in GaN having no or less crystal defects. Because of this, Mg that has been introduced into the region41′ thermally diffuses into the region42′ in a relative short amount of time at a relatively low temperature. As a result, the p+Mg injected region41and the p Mg diffused region42are formed in the n−GaN layer20with ease. Further, according to the manufacturing method of the first embodiment, the p-type region40(the p+Mg injected region41and the p Mg diffused region42) is locally formed without using etching steps. Because there is no need to perform etching on the GaN layer20in the formation of the p-type region40, the pn junction between the n−GaN layer20and the p-type region40does not suffer etching damages. Due to this, in the guard ring structure that includes the p-type regions40, instabilities on various properties, such as the withstand voltage, due to etching damages can be prevented. Further, according to the manufacturing method of the first embodiment, the p-type regions40can be locally formed in the n−GaN layer20without re-growing p−GaN on the n GaN. Because there is no need to re-grow p−GaN in the formation of the p-type region40, silicon (Si) and oxygen (O) do not exist at high concentrations at the pn junction between the n−GaN layer20and the p-type region40. Silicon (Si) and Oxygen (O) function as n-type impurities in GaN. Because a high-density n-type impurity region is not formed at the above-mentioned pn junction, the guard ring structure that includes the p-type regions40can effectively prevent instabilities on various properties, such as the withstand voltage, due to high-density n-type impurities. In the manufacturing method of the first embodiment, the Mg concentrations in the p-type region40can be adjusted by appropriately setting the Mg ion implantation conditions (the Mg dosage and Mg ion implantation energy, for example), the thermal treatment conditions (the thermal treatment temperature and duration, for example), and the N ion implantation conditions (the N dosage and N ion implantation energy, for example). For example, in the p-type region40, the Mg injected region41having an Mg concentration of equal to or greater than 1.0×1019cm−3and less than or equal to 1.0×1020cm−3and the Mg diffused region42having an Mg concentration of equal to or greater than 1.0×1017cm−3and less than or equal to 1.0×1019cm−3may be formed. Furthermore, as shown inFIG.3, the Mg concentration in the Mg diffused region42may be made constant at about 1×1018cm−3along the depth direction and may be made to change drastically along the depth direction at and near the boundary with the n−GaN layer20. For example, in the depth direction of GaN layer20(Z-axis direction), the width of a region within which the Mg concentration decreases by 1/10th(to about 1.0×1017cm−3) of the Mg concentration in the Mg diffused region42, as moving farther away from the Mg diffused region42in the depth direction, may be made equal to or less than 100 nm. FIG.11is a depth profile of the Mg concentrations in a comparison example. InFIG.11, the horizontal axis shows the depth (nm) from the surface of GaN, and the vertical axis shows the Mg concentration contained in GaN in cm−3. In this comparison example, nitrogen atoms are not ion-implanted in GaN. In this comparison example shown inFIG.11, Mg was ion-implanted into GaN and the thermal treatment was conducted under the same conditions as those for the first embodiment for which data forFIG.3were taken, but the N ion implantation was not conducted.FIG.11shows that in the comparison example, the Mg concentration in the Mg diffused region cannot be made constant at around 1×1018cm−3. The GaN semiconductor device100according to the first embodiment of the present invention includes: the N injected region30provided locally on a side of the surfaced20aof the GaN layer20and the p-type region40provided locally within the N injected region30. The N injected region30contains a higher concentration of nitrogen atoms than in other regions within the GaN layer20and contains crystal defects that are generated due to the nitrogen atoms ion implantation. The p-type region40includes the Mg injected region41that contains Mg and the Mg diffused region42that surrounds the Mg injected region41and contains Mg at a lesser concentration than in the Mg injected region41. For example, the Mg diffused region42is in contact with the sides of the Mg injected region41in the X and Y directions and also in contact with the bottom of the Mg injected region41in the Z direction. The manufacturing method of the first embodiment therefore can manufacture the GaN semiconductor device100having this structure. Modified Example FIG.12is a depth profile of the Mg concentrations in a GaN semiconductor device according to a modified example of the first embodiment of the present invention. InFIG.12, the horizontal axis shows the depth (nm) from the surface20aof the GaN layer20, and the vertical axis shows the concentrations of elements contained in the GaN layer20in cm−3. InFIG.12, the broken line indicates the Mg concentration profile immediately after the ion implantation, and the dash-dot line indicates the N concentration profile immediately after the ion implantation. The Mg ion implantation performed inFIG.7for the first embodiment may be performed multiple times by varying the Mg implantation energy. By doing so, the Mg concentration profile immediately after the ion implantation may differ from the profile shown inFIG.3. For example, the Mg concentration immediately after the ion implantation may be made roughly constant in the depth range of 100 nm to 250 nm from the surface20aof the GaN layer20. In this case, as shown by the solid line inFIG.12, the Mg concentration after the thermal treatment takes a shape different from the shape inFIG.3. For example, the Mg concentration after the thermal treatment may be made roughly constant in the depth range of 100 nm to 250 nm from the surface20aof the GaN layer20. Similar to the first embodiment above, the p+Mg injected region41and the p Mg diffused region42having this profile may be formed in the n−Gan layer20with ease. Here, the p-type region40having the concentration profile ofFIG.3and the p-type region40having the concentration profile ofFIG.12may be formed in the same substrate. In such a case, both types of the p-type regions may be formed via the same thermal treatment process. In the embodiments above, as the “element other than p-type impurities and n-type impurities,” nitrogen (N) atoms are used. However, the present invention is not limited thereto. For example, elements other than N, such as phosphorous (P) and arsenic (As), may be used as the “element other than p-type impurities and n-type impurities,” to introduce crystal defects in the GaN layer20. Second Embodiment FIG.13is a cross-sectional view of a GaN semiconductor device100A according to a second embodiment of the present invention (another example of the “nitride semiconductor device” of the present invention). As shown inFIG.13, the GaN semiconductor device100A has electrodes71connected to the Mg injected regions41. The electrodes71are independent electrodes electrically isolated from the gate electrode62, the source electrode68, the gate pad112, and the source pad114, provided in the active region110. This structure also provides the same effects as the first embodiment. Further, in the GaN semiconductor device100A, voltages may be applied to the p-type regions40through the electrodes71. Because of this, the depletion region can further expand from the p-type regions40towards the n−GaN layer20, thereby improving the withstand voltage of the GaN semiconductor device100A. Third Embodiment FIG.14is a cross-sectional view of a GaN semiconductor device100B according to a third embodiment of the present invention. The GaN semiconductor device100B is an example of the “nitride semiconductor device” of the present invention. As shown inFIG.14, in the GaN semiconductor device100B, the horizontal intervals L2of a plurality of p-type regions40that constitute a guard ring structure are progressively widened from the active region110side towards the periphery of the edge termination region130. For example, the interval L2near the active region110is 1 μm or less, and L2becomes progressively larger than 1 μm as moving towards the periphery of the edge termination region130. This structure has the same effects as the first embodiment. Further, in the GaN semiconductor device100B, the lengths of the intervals L2and their variations may be adjusted according to the required withstand voltage. This will further contribute to an improvement of the withstand voltage of the GaN semiconductor device100B. Fourth Embodiment FIG.15is a cross-sectional view of a GaN semiconductor device100C according to a fourth embodiment of the present invention. The GaN semiconductor device100C is an example of the “nitride semiconductor device” of the present invention, and has vertical MOSFET having a planar gate structure. As shown inFIG.15, in the semiconductor device100C, an N injected region30A is formed in the active region110. The p well regions22, the n+source regions24, and the p+contact regions26are formed within the N injected region30A in the active region110. Similar to the N injected region30in the first embodiment, the N injected region30A is formed by ion-implanting nitrogen (N) into the surface20aof the GaN layer20. Similar to the Mg injected region41in the first embodiment, the p+contact region26is formed by ion implantation of Mg into the N injected region30A and a subsequent thermal treatment. Similar to the Mg diffused region42in the first embodiment, the p−well region22is formed by thermal diffusion of Mg contained in the p+contact region26into the periphery of the contact region26during the above-mentioned thermal treatment. With this structure, the p−well region22and the p+contact region26may be formed in the p−well region22with ease. Also, because the gate structure is formed in the diffusion region, channels are formed in portions having good p-type properties, and the channel properties can be enhanced as a result. This results in a reduction in the ON resistance of the vertical MOSFET. Further, because the p-type region that is formed by Mg diffusion is used in the pn junction in the active area, depletion in the p−well region22in the active region is relaxed, thereby improving the junction breakdown voltage. Therefore, it is possible to realize a device having a low ON resistance and a high withstand voltage. Here, similar to the first through third embodiments, the Mg injected regions41and the Mg diffused regions42may be formed in the edge termination region130in the fourth embodiment. In such a case, the N ion implantation conditions for the active region110and for the edge termination region130may be set as the same so that the N ion implantation is performed in both regions at once. Alternatively, the N ion implantation conditions for these regions may differ, and separate N ion implantation processes may be performed for these regions. If separate N ion implantation processes are performed for the active region110and the edge termination region130, respectively, the Mg concentration in the p−well region22in the active region110and the Mg concentration in the Mg diffused region42in the edge termination region130will have different profiles with each other. By adjusting the respective N ion implantation conditions, the respective Mg concentrations after the thermal treatment may be designed as desired. Fifth Embodiment FIG.16is a cross-sectional view of a GaN semiconductor device100D according to a fifth embodiment of the present invention. The GaN semiconductor device100D is an example of the “nitride semiconductor device” of the present invention, and has MOSFETs having a trench gate structure. As shown inFIG.16, in the GaN semiconductor device100D, an N injected region30A is formed in the active region110. The p−well regions22, the n+source regions24, and the p+contact regions26are formed within the N injected region30A in the active region110. Further, in the GaN semiconductor device100D, trenches are formed in the N injected region30A in the active region110, and a gate electrode62is formed in each trench with a gate insulating film60interposed therebetween. Similar to the fourth embodiment, the N injected region30A is formed by ion-implanting nitrogen (N) into the surface20aof the GaN layer20. The p+contact region26is formed by ion implantation of Mg into the N injected region30A and a subsequent thermal treatment. The p−well region22is formed by thermal diffusion of Mg contained in the p+contact region26into the periphery of the contact region26during the above-mentioned thermal treatment. In the fifth embodiment, a plurality of p−well regions22are arranged in the horizontal direction. The trenches are formed between the well regions. Each trench penetrates the well region22and is bottomed within the N injected region30A. The gate insulating film60is formed so as to cover the bottom and side walls of the trench. The gate electrode62is formed so as to be embedded into the trench with the gate insulating film60interposed therebetween. In the fifth embodiment, because the gate structure is formed in the diffusion region, channels are formed in portions having good p-type properties, and the channel properties can be enhanced as a result. This results in a reduction in the ON resistance of the vertical MOSFET. Furthermore, because the p-type region that is formed of Mg diffusion is used in the pn junction in the active area, depletion in the p−well region22in the active region can be relaxed, thereby improving the junction withstand voltage. Therefore, it is possible to realize a device having a low ON resistance and a high withstand voltage. Other Embodiments Various embodiments and their modifications have been described above. However, the descriptions and drawings explained above do not unduly limit the scope of the present invention. The present disclosure includes various other embodiments and modifications that can be understood by those having ordinary skill in the art based on the disclosure herein. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention. For example, the gate insulating film60may be made of silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO), or silicon nitride (Si3N4). Also, the gate insulating film60may be a multilayer film by laminating multiple single layer insulating films. When an insulating film other than SiO2is used, such a vertical MOSFET may also be referred to as a vertical MISFET. The term “MISFET” broadly means an insulating gate type transistor that includes MOSFET. | 36,936 |
11862687 | DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinbelow, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention disclosed in claims. In addition, not all combinations of features described in the embodiments necessarily have to be essential to solving means of the invention. In this specification, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as “upper”, and the other side is referred to as “lower”. One surface of the two main surfaces of a substrate, layer, or other members is referred to as a front surface, and the other surface is referred to as a back surface. The “upper”, “lower”, “front”, and “back” directions are not limited to the gravitational direction or the direction of attachment to a substrate or the like at the time of mounting of a semiconductor device. In this specification, “N” or “P” attached on a layer or region means that the main dopant therein is electron and hole, respectively. The sign “+” or “−” given to the character “N” or “P” means having a higher or lower doping concentration than layers or regions without it, respectively. FIG.1Ashows one example of the configuration of a nitride semiconductor device100according to example 1. The nitride semiconductor device100is one example of the MOSFET structure, and is not limited to the present embodiment. The nitride semiconductor device100of the present example includes a first nitride semiconductor layer10, an epitaxial layer20, a second nitride semiconductor layer30, a junction region40, a source region50, an insulating layer60, an electrode70, and an electrode72. A front surface101indicates the upper surface of the nitride semiconductor layer included in the nitride semiconductor device100. Aback surface102indicates the lower surface of the nitride semiconductor layer included in the nitride semiconductor device100. In the present example, the front surface101corresponds to the upper surface of the second nitride semiconductor layer30, and the back surface102corresponds to the lower surface of the first nitride semiconductor layer10. In one example, the first nitride semiconductor layer10is an N-type free-standing substrate GaN substrate. The first nitride semiconductor layer10may be provided by using any method such as a vapor deposition method including an HVPE, or a liquid deposition method. The first nitride semiconductor layer10may be cut out of a GaN layer which is epitaxially deposited. The epitaxial layer20is a layer epitaxially deposited on the first nitride semiconductor layer10. In one example, the epitaxial layer20is an N-type GaN layer. The thickness of the epitaxial layer20is not particularly limited. The second nitride semiconductor layer30is provided on the epitaxial layer20. The second nitride semiconductor layer30may be provided by ion-implanting P-type dopants into a layer of the same material as the epitaxial layer20being N-type. For example, the P-type dopant of the second nitride semiconductor layer30is magnesium (Mg). In one example, the film thickness D2-NSLof the second nitride semiconductor layer30is 300 nm or more. More preferably, the film thickness meets the following condition: 500 nm≤D2-NSL≤1.5 μm. The junction region40is provided above the epitaxial layer20. The junction region40of the present example is provided to extend through the second nitride semiconductor layer30into the epitaxial layer20. The junction region40is formed by ion-implanting N-type dopants from the side of the front surface101of the second nitride semiconductor layer30. In one example, the dopant of the junction region40includes at least one of oxygen (O) and silicon (Si). For example, the depth DJFETof the junction region40meets the following condition: DJFET≥D2-NSL. Also, the depth DJFETof the junction region40may meet the following condition: 200 nm≤DJFET≤2 μm. More preferably, the depth may meet the following condition: 500 nm≤DJFET≤1.5 μm. The source region50is provided on the side of the front surface101of the second nitride semiconductor layer30. The source region50is provided more shallowly than the junction region40. In one example, the depth of the source region50is 10 nm or more and 100 nm or less. The source region50of the present example is provided by ion-implanting N-type dopants into the second nitride semiconductor layer30. The doping concentration of the source region50may be higher than that of the junction region40. For example, the dopant of the source region50includes at least one of silicon (Si) and germanium (Ge). In one example, the dose DoseSof the source region50meets the following condition: 5×1014cm−2≤DoseS≤1×1016cm−2. The dopant of the source region50is an element with an atomic weight higher than that of the dopant of the junction region40. For example, the dopant of the junction region40is oxygen (O), and the dopant of the source region50includes any one of silicon (Si) and germanium (Ge). Also, the dopant of the junction region40may be silicon (Si), and the dopant of the source region50may be germanium (Ge). The insulating layer60is provided on the front surface101of the second nitride semiconductor layer30. In addition, the insulating layer60is also provided above the junction region40and the source region50. The insulating layer60may have an opening to electrically connect an electrode72with the source region50. The insulating layer60prevents the electrode72provided above the second nitride semiconductor layer30from being electrically shorted with the second nitride semiconductor layer30and the junction region40. For example, the insulating layer60is the oxide film of silicon dioxide (SiO2) and the like. The insulating layer60may be a nitride film of silicon nitride (SiN) and the like. The electrode70is provided on the back surface102of the first nitride semiconductor layer10. The electrode70of the present example serves as a drain electrode (D). The electrode72is provided above the front surface101. The electrode72of the present example has a gate electrode (G) provided above the junction region40and the insulating layer60. The electrode72may have a source electrode (S) provided on the source region50. For example, the electrode72is a nickel (Ni)/gold (Au) electrode. In the nitride semiconductor device100of the present example, a dopant with an atomic weight lower than that of the dopant of the source region50is ion-implanted into the shallow junction region40, and a dopant with an atomic weight higher than that of the dopant of the junction region40is ion-implanted into the deep source region50. The nitride semiconductor device100in which a damage due to ion-implantation is reduced can be provided by selecting a dopant with an appropriate atomic weight depending on the depth of the N-type region. Also, an ultra-high energy ion implantation apparatus can be unnecessary for the fabrication of the nitride semiconductor device100. It is noted that the junction region40may include a plurality of dopants which is ion-implanted with various depths. Also, in the junction region40, an element with a high atomic weight may be ion-implanted into a shallow region, and an element with a low atomic weight may be ion-implanted into a deep region. For example, in the junction region40, oxygen (O) and silicon (Si) is ion-implanted as a dopant. Moreover, the junction region40may have a region in which silicon (Si) is doped and a region in which oxygen (O) is doped deeper than silicon (Si). Thereby, the hysteresis of the nitride semiconductor device100is improved. In the junction region40, a dopant with an atomic weight similar to that of the Ga element may be ion-implanted into the a shallow region, and dopant with an atomic weight far from that of the Ga element may be ion-implanted into a deep region. In other words, ion-implantation of a dopant with an atomic weight similar to Ga element into a region near the insulating layer60serving as a gate oxide film reduces a distortion which degrades the electrical characteristics around a gate structure, resulting in the improvement of characteristics of the nitride semiconductor device100. The epitaxial layer20in the nitride semiconductor device100of the present example may be an n-type GaN layer with a low concentration formed on an n-type substrate with a high concentration. In this case, the n-type GaN layer with a low concentration may be provided by using a vapor deposition method such as HVPE and MOCVD, a liquid deposition method, an ion-implantation, and any other method. The nitride semiconductor device100of the present example includes epitaxial layer20, but it may not include the epitaxial layer20in another example. In this case, the nitride semiconductor device100includes the first nitride semiconductor layer10, the second nitride semiconductor layer30, the junction region40, the source region50, the insulating layer60, the electrode70, and the electrode72. The second nitride semiconductor layer30is provided on the first nitride semiconductor layer10. Also, the junction region40is provided to extend through the second nitride semiconductor layer30into the first nitride semiconductor layer10. Other features are similar to those in example 1. For the nitride semiconductor device100, a type of the N-type dopant may be selected according to the depth of the N-type region and the application. For example, for the deep junction region40such as the counter doping into JFET, an element with a low atomic weight such as oxygen (O) and silicon (Si) is selected. For the shallow source region50such as a source contact portion, an element with a high atomic weight such as silicon (Si) and germanium (Ge) is selected. Thereby, the damage to the junction region40is reduced, and the controllability at a low doping concentration is improved. The distortion of the source region50can be reduced by appropriately selecting the size of the atomic weight. It is noted that, example 1 describes the case in which two types of N-type dopant are used, but three or more types of N-type dopant may be used. Likewise, three or more types of N-type dopant may be used in other examples. Herein, the doping concentration NM of the junction region40in example 1 meets the following condition: 5×1015cm−3NJFET≤2×1018cm−3. It is noted that the range of doping concentration NJFETis one example, and is not limited thereto. The dopant of the junction region40may be oxygen (O). The width WJFETof the junction region40may meet the following condition: 0.5 μm≤WJFET≤3 μm. Also, the doping concentration NJFETmay meet the following condition: 5×1015cm−3≤NJFET≤2×1018cm−3. FIG.1Bshows one example of the method for fabricating the nitride semiconductor device100according to example 1. The method for fabricating the nitride semiconductor device100shown in the present example is one example and is not limited thereto. The epitaxial layer20is formed on the first nitride semiconductor layer10(S100). The epitaxial layer20in the present example is an N-type GaN layer epitaxially deposited on the first nitride semiconductor layer10by using any method such as the MOCVD method. In one example, the doping concentration of the epitaxial layer20is 1.0×1015cm−3or more and 1.0×1017cm−3or less. However, the doping concentration of the epitaxial layer20is not limited to the present example. A mask110ais formed on the epitaxial layer20(S102). The mask110arestricts ion-implantation into the epitaxial layer20. The mask110ahas a pattern corresponding to a region where the second nitride semiconductor layer30is formed. By using the mask110a, a P-type dopant is selectively ion-implanted into a region where the second nitride semiconductor layer30is provided (S104). In one example, providing the second nitride semiconductor layer30includes ion-implanting any one of magnesium (Mg), zinc (Zn), cadmium (Cd), beryllium (Be), and the like. The second nitride semiconductor layer30in the present example is formed by ion-implanting magnesium (Mg). Ion-implanting dopants may include ion-implanting with multiple stages. Ion-implanting with multiple stages can facilitate adjustment of the doping concentration of the second nitride semiconductor layer30for each depth. In this specification, the term “multiple stages” means ion-implanting dopants with various implanting conditions such as accelerating voltage. The mask110ais then removed, and a mask110bto form the N-type junction region40is formed on the epitaxial layer20(S106). Then, by using the mask110b, a dopant is selectively ion-implanted into a region where the N-type junction region40is provided. A selective ion-implantation on the second nitride semiconductor layer30and the junction region40prevents a P-type dopant to form the second nitride semiconductor layer30from being ion-implanted into the junction region40. After the ion-implantation on the junction region40, the nitride semiconductor device100may be annealed at a predetermined first temperature. Thereby, the dopants ion-implanted into the junction region40are activated. The first temperature may be 1200° C. or more, 1300° C. or more, 1400° C. or more, and 1500° C. or more. Then, the mask110bis removed, and a mask110cto form the source region50is formed on the epitaxial layer20(S108). Then, by using the mask110c, dopants are selectively ion-implanted into a region where an N+type source region50is provided. The source region50in the present example is formed by ion-implanting any one of silicon (Si) and germanium (Ge). After the ion-implantation on the source region50, the nitride semiconductor device100may be annealed at a predetermined second temperature. Thereby, the dopants ion-implanted into the source region50are activated. The second temperature may be 1200° C. or more, 1300° C. or more, 1400° C. or more, and 1500° C. or more. The second temperature may be different from the first temperature. The insulating layer60and the electrode72are formed above the front surface101(S110). For example, the insulating layer60is silicon oxide film (SiO2) whose film thickness is 400 nm. The electrode72may be stacked film of nickel (Ni) and gold (Au), and the film thickness may be 50 nm and 150 nm, respectively. The insulating layer60and the electrode72are patterned with a pattern according to the structure of the nitride semiconductor device100. Then, the electrode70is formed on the back surface102of the first nitride semiconductor layer10. For the nitride semiconductor device100in the present example, ion-implanting steps on three regions, that is, the second nitride semiconductor layer30, the junction region40, and the source region50, are included. After ion-implanting steps on the three regions, an annealing step which corresponds to each ion-implanting step may be included. Specifically, after ion-implanting magnesium (Mg) for the second nitride semiconductor layer30, and before ion-implanting oxygen (O) or silicon (Si) for the junction region40, an annealing step may be included. After ion-implanting oxygen (O) or silicon (Si) for the junction region40, and before ion-implanting silicon (Si) or germanium (Ge) for the source region50, an annealing step may be included. Moreover, after ion-implanting silicon (Si) or germanium (Ge) for the source region50, an annealing step may be included. In addition, the order of ion-implanting steps to form the second nitride semiconductor layer30, the junction region40, and the source region50is not limited to the present example. Furthermore, the annealing steps may be performed together after a plurality of ion-implanting steps. By annealing together, the fabrication time of the nitride semiconductor device100can be reduced. In one example, after the ion-implanting step on the junction region40, an annealing step at the first temperature is included. After the ion-implanting step on the source region50, an annealing step at a second temperature different from the first temperature of the junction region40may be included. For example, the first temperature is higher than the second temperature. It is noted that, when the second temperature is higher than the first temperature, the source region50may be formed before the junction region40is formed. By performing a process at a high annealing temperature (for example, second temperature) before performing a process at a low annealing temperature (for example, first temperature), a thermal history at the second temperature higher than the first temperature is not remained in the junction region40. For example, by annealing at a second temperature after forming the source region50with the ion-implantation of silicon (Si), and then forming the junction region40with the ion-implantation of oxygen (O) and annealing at a first temperature lower than the second temperature, the anneal can be performed without exposing the junction region40after the implantation of oxygen (O) to a high temperature. FIG.2shows one example of the doping concentration of oxygen (O) implanted into the junction region40according to example 1 and the increase in the carrier concentration Nddue to oxygen (O) of the junction region40. As the doping concentration of implanted oxygen (O) increases, the carrier concentration Ndincreases. In the present example, the nitride semiconductor device100is fabricated through an annealing step at 1300° C. which is the first temperature after the junction region40and the source region50are formed, but is not limited thereto. It is noted that the range of doping concentration of oxygen (O) can be adapted to the width WJFETof the junction region40according to the correlation between NJFETand the concentration of oxygen (O) at 1300° C. FIG.3AandFIG.3Bshow the relationship between the JFET resistance being the resistance of the junction region40, the breakdown voltage of the junction region40, and the doping concentration of the implanted oxygen (O).FIG.3Ashows a result in a case where the width WJFETof the junction region40according to example 1 is 3 μm.FIG.3Bshows a result in a case where the width WJFETof the junction region40according to example 1 is 1 μm. The present example shows the tendency that the JFET resistance and the breakdown voltage decrease as the doping concentration of oxygen (O) increases. It is noted that, in the present example, the JFET resistance and the breakdown voltage in a case where the doping concentration of oxygen (O) is 0 cm−3, 3.6×1017cm−3, and 9.0×1017cm−3are each plotted. In the junction region40, the JFET resistance of the junction region40is 0.4 mΩcm2or less when the element breakdown voltage is 1200 V. It is noted that this numerical value is one example and is not limited to the present embodiment. In reference toFIG.3A, the JFET resistance is approximately 0 mΩcm2when the doping concentration of oxygen (O) is 3.6×1017cm−3. On the other hand, the breakdown voltage decreases to 1200 V or less. This result suggests that, in the present embodiment, the upper limit of the doping concentration of oxygen (O) is 3.6×1017cm−3when the width WJFETis 3 μm. The JFET resistance when no oxygen (O) is doped, that is, the original JFET resistance is approximately 0.65 mΩcm2. In addition, the original breakdown voltage is approximately 1350 V. From this, it can be seen that, when each of the plots of the JFET resistance and the breakdown voltage inFIG.3Ais connected with a curved line, the lower limit of the doping concentration of oxygen (O) at which the JFET resistance is 0.4 mΩcm2or less and the breakdown voltage is 1200 V or more is approximately 5.0×15 cm−3. In reference toFIG.3B, the case in which the doping concentration of oxygen (O) is 0 is not shown. This is because, when the width WJFETis 1 μm, the original JFET resistance is 100 mΩcm2or more, and the nitride semiconductor device100in the present embodiment cannot operate. In a case where the doping concentration of oxygen (O) is 3.6×1017cm−3, the JET resistance is approximately 0.2 mΩcm2and the breakdown voltage is approximately 1400 V. In addition, in a case where the doping concentration of oxygen (O) is 9.0×1017cm−3, the JET resistance is approximately 0 mΩcm2and the breakdown voltage is approximately 1300 V. Because the JFET resistance is preferably close to 0 mΩcm2, in the present embodiment, it can be seen that when the width WJFETis 1 μm, the upper limit of the doping concentration of oxygen (O) is 9.0×1017cm−3. In addition, when the plots of JFET resistance inFIG.3Bare connected with a curved line, it can be seen that the WET resistance is 0.4 mΩcm2or less when the doping concentration of oxygen (O) is 1.0×1017cm−3or more. Therefore, it can be seen that the lower limit of the doping concentration of oxygen (O) is 1.0×1017cm−3. FIG.4shows one example in which the relationship between the width WJFETand the doping concentration of the implanted oxygen (O) is calculated from the result inFIG.3AandFIG.3B. InFIG.4, the upper limit and the lower limit of the doping concentration of oxygen (O) are indicated with a solid line and a dashed line, respectively.FIG.4shows the relationship according to example 1, and it is not limited to the present embodiment. The doping concentration range (cm−3) of oxygen (O) and the width WJFET(μm) meets the following Equation 1. 2×1017×exp(−1.15×WJFET)≤NJFET≤2×1018×exp(−0.75×WJFET) [Equation 1] Herein, the unit of width WJFETis μm. For example, when the width WJFETis 1 μm, the upper limit value and the lower limit value of the doping concentration NJFETof oxygen (O) (cm−3) can be derived by substituting 1 in Equation 1. In addition, based on the calculation result of Equation 1, the dose range of dose DoseJFETof oxygen (O)(cm−2) and the width WJFET(μm) meet the following Equation 2. 1.3×1013×exp(−1.15×WJFET)≤DoseJFET≤1.3×1014×exp(−0.75×WJFET) [Equation 2] Herein, the unit of width WJFETis μm as with Equation 1. For example, when the width WJFETis 1 μm, the upper limit value and the lower limit value of the dose DoseJFETof oxygen (O) (cm−2) can be derived by substituting 1 in Equation 2. Based on Equation 1 and Equation 2, the appropriate range of the doping concentration in the counter doping of oxygen (O) for the junction region40may be specified. Thereby, the ultra-high energy ion implantation apparatus of 1 MeV or more can be unnecessary for the fabrication of the nitride semiconductor device100. Therefore, the fabrication cost can be reduced. FIG.5Ashows one example of the configuration of the schottky barrier diode150using the junction region40according to example 1. The schottky barrier diode150is one example of the diode structure, and is not limited to the present embodiment. The schottky barrier diode150includes the N-type first nitride semiconductor layer10, the N-type epitaxial layer20, the N-type junction region40, the electrode70, and the electrode72. For the schottky barrier diode150, the electrode70and72are formed after the oxygen (O) is implanted with the same condition as the junction region40of the nitride semiconductor device100according to example 1 and the heat process is performed at 1100° C. or 1300° C. Each of the electrodes70and72serves as the anode or cathode. FIG.5Bshows one example of a profile of SIMS (Secondary Ion Mass Spectrometry) in the schottky barrier diode150. Thereby, the depth DJFETof the junction region40can be estimated. In one example, the depth DJFETis 0.7 μm. FIG.5Cshows one example of the current J-voltage V characteristics of the schottky barrier diode150in a case where the annealing is performed at the first temperature 1100° C. InFIG.5C, the current reaches approximately 1.5×101, A/cm2. FIG.5Dshows one example of the current J-voltage V characteristics of the schottky barrier diode150in a case where the annealing is performed at the first temperature 1300° C. InFIG.5D, the current reaches 1×103A/cm2unlike in a case with 1100° C. Therefore, in present embodiment, it can be seen that the activation ratio is improved by increasing the temperature from the first annealing temperature 1100° C., at which the maximum current value is lower by approximately two degrees of magnitude, to 1300° C. It is noted that the first annealing temperature may be 1300° C. or more, in which case the activation ratio is further increased. FIG.6Ashows one example of the configuration of the nitride semiconductor device100according to example 2. The basic structure of the nitride semiconductor device100in the present example is the same as that of the nitride semiconductor device100according to example 1. However, the nitride semiconductor device100in the present example is different from the nitride semiconductor device100according to example 1 in that it has the second nitride semiconductor layer35which is epitaxially deposited. The present example particularly describes the difference from the example 1. The second nitride semiconductor layer35is provided on the epitaxial layer20. The second nitride semiconductor layer35may be formed by using the MOCVD method as with the epitaxial layer20. The second nitride semiconductor layer35may be provided continuously after the epitaxial layer20is epitaxially deposited. In this case, the second nitride semiconductor layer35is continuously deposited by the influx of dopant gas different from that during the deposition of the epitaxial layer20. The nitride semiconductor device100in example 2 does not include a step of P-type ion-implantation. This possibly reduces the crystal defect of the GaN layer, which is caused by ion-implantation and degrades the electrical characteristics of the nitride semiconductor device100. In the present example, the doping concentration NJFETin the junction region40meets the following condition in which the dopant concentration NEpiof the second nitride semiconductor layer35is used: NEpi+5×1015cm−3≤NJFET≤NEpi+2×1018cm−3. Thereby, the JFET resistance and breakdown voltage of the nitride semiconductor device100can become appropriate values. It is noted that the range of doping concentration NJFETin the present example is one example, and is not limited thereto. FIG.6Bshows one example of the method for fabricating the nitride semiconductor device100according to example 2. The method for fabricating the nitride semiconductor device100shown in the present example is one example and is not limited thereto. The epitaxial layer20is formed on the first nitride semiconductor layer10(S200). The epitaxial layer20in the present example is an N-type GaN layer epitaxially deposited on the first nitride semiconductor layer10by using any method such as the MOCVD method. In one example, the dopant concentration of the epitaxial layer20is 1.0×1015cm−3or more and 1.0×1017cm−3or less. However, the dopant concentration of the epitaxial layer20is not limited to the present example. On the epitaxial layer20, a second nitride semiconductor layer35is epitaxially deposited (S202). Then, on the second nitride semiconductor layer35, the mask110bis formed (S204). The mask110brestricts the ion-implantation on the second nitride semiconductor layer35. The mask110bhas a pattern corresponding to the region where the junction region40is formed. N-type dopants are selectively ion-implanted into a region provided in the junction region40by using the mask110b(S206). Because the second nitride semiconductor layer35is epitaxially deposited, the junction region40includes magnesium (Mg) to make the P-type second nitride semiconductor layer35. In one example, providing the junction region40includes ion-implanting at least one of oxygen (O) and silicon (Si). The junction region40in the present example is formed by ion-implanting oxygen (O). Ion-implanting dopants may include ion-implanting with multiple stages. Ion-implanting with multiple stages can facilitate adjustment of the doping concentration of the second nitride semiconductor layer35for each depth. Then, the mask110bis removed, and a mask110cto form the source region50is formed on the second nitride semiconductor layer35(S208). Then, by using the mask110c, N-type dopants are selectively ion-implanted into a region where the source region50is provided. The source region50in the present example is formed by ion-implanting any one of silicon (Si) and germanium (Ge). Then, the mask110cis removed, and the insulating layer60and the electrode72are formed above the second nitride semiconductor layer35(S210). For example, the insulating layer60is silicon oxide film (SiO2) whose film thickness is 400 nm. The electrode72may be stacked film of nickel (Ni) and gold (Au), and the film thickness may be 50 nm and 150 nm, respectively. The insulating layer60and the electrode72are patterned with a pattern according to the structure of the nitride semiconductor device100. Then, the electrode70is formed on the back surface102of the first nitride semiconductor layer10. FIG.7Ashows one example of the configuration of the nitride semiconductor device100according to example 3. The nitride semiconductor device100in the present example is one example of a trench MOSFET. The present example is different from the nitride semiconductor device100according to example 2 in that the nitride semiconductor device100includes the trench portion80. In the present example, the difference from example 2 is particularly described. The trench portion80is provided on the upper surface of the epitaxial layer20. The trench portion80is provided such that it extends from the upper surface of the second nitride semiconductor layer35to the inside. The depth and width of the trench portion80are not particularly limited. It is noted that the nitride semiconductor device100in the present example has the second nitride semiconductor layer35on the epitaxial layer20. However, the second nitride semiconductor layer30may be provided instead of the second nitride semiconductor layer35as with example 2. The junction region45is provided on the lower surface of the trench portion80. The junction region45is formed by ion-implanting N-type dopants into the bottom surface of the trench portion80. In one example, the dopant includes at least one of oxygen (O) and silicon (Si). For example, the depth DJFETof the junction region45is 200 nm or more and 2000 nm or less from the front surface101. More preferably, it is 500 nm or more and 1500 nm or less. The source region55is provided on the side of the front surface101of the second nitride semiconductor layer35. The source region55is provided more shallowly than the junction region45. In one example, the depth of the source region55is 10 nm or more and 100 nm or less. FIG.7Bshows one example of the method for fabricating the nitride semiconductor device100according to example 3. The method for fabricating the nitride semiconductor device100shown in the present example is one example and is not limited thereto. On the first nitride semiconductor layer10, the epitaxial layer20is formed (S300). The epitaxial layer20in the present example is an N-type GaN layer epitaxially deposited on the first nitride semiconductor layer10by using any method such as the MOCVD method. In one example, the dopant concentration of the epitaxial layer20is 1.0×1015cm−3or more and 1.0×1017cm−3or less. However, the dopant concentration of the epitaxial layer20is not limited to the present example. On the epitaxial layer20, the second nitride semiconductor layer35is epitaxially deposited (S302). Then, on the second nitride semiconductor layer35, the mask110bis formed (S304). The mask110brestricts the etching on apart of the second nitride semiconductor layer35. In addition, the mask110bin the present example is used to restrict the ion-implantation to provide the junction region45. The mask110bin the present example has a pattern corresponding to the region where the trench portion80is formed. The region where the trench portion80is to be provided is selectively etched by using the mask110b(S306). The second nitride semiconductor layer35is etched by using chlorine gas as one example. After the second nitride semiconductor layer35is etched, the junction region45is provided. In one example, providing the junction region45includes ion-implanting any one of oxygen (O) and silicon (Si) (S306). The junction region45in the present example is formed by ion-implanting oxygen (O). Ion-implanting dopants may include ion-implanting with multiple stages. Ion-implanting with multiple stages can facilitate adjustment of the doping concentration of the junction region45for each depth. Then, the mask110bis removed, and the mask110cto form the source region55is formed (S308). Then, by using the mask110c, N-type dopants are selectively ion-implanted into a region where the source region55is provided. Providing the source region55includes ion-implanting any one of silicon (Si) and germanium (Ge). The source region55in the present example is formed by ion-implanting silicon (Si). Then, the mask110cis removed, and the insulating layer60and the electrode72are formed (S310). For example, the insulating layer60is silicon oxide film (SiO2) whose film thickness is 400 nm. The electrode72may be stacked film of nickel (Ni) and gold (Au), and the film thickness may be 50 nm and 150 nm, respectively. The insulating layer60and the electrode72are patterned with a pattern according to the structure of the nitride semiconductor device100. Then, the electrode70is formed on the back surface102of the first nitride semiconductor layer10. For the nitride semiconductor device100in example 3, the junction region45is formed after the trench portion80is provided through etching. Thereby, the ion-implantation to form the junction region45can be shallower by the depth of the trench portion80. However, for the nitride semiconductor device100, etching to form the trench portion80may be performed after ion-implanting dopants to form the junction region45. FIG.8shows one example of the doping concentration in the junction region40and the source region50in example 1. In addition,FIG.8is a diagram to describe the tail of the doping concentration in the N-type region at depth D from the front surface101.FIG.8shows tail length Lt in a case where the N-type region is formed through ion-implantation in example 1. FIG.8(A)shows the tail length LtJ-40of the N-type dopant which is ion-implanted to form the junction region40. The tail length LtJ-40is the tail length Lt from the peak P of the doping concentration in the junction region40to the lower end of the junction region40. When the junction region40is formed through ion-implantation with multiple stages, the peak P of the doping concentration in the junction region40refers to the peak of the deepest ion-implantation. FIG.8(B)shows the tail length LtS-50of the N-type dopant ion-implanted to form the source region50. The tail length LtS-50is the tail length Lt from the doping concentration peak of the source region50to the lower end of the source region50. When the source region50is formed through ion-implantation with multiple stages, the peak P of the doping concentration in the source region50refers to the peak of the deepest ion-implantation. The tail length LtJ-40in the present example is less than the tail length LtS-50. The tail length LtJ-40can be reduced to be shorter than the tail length LtS-50by selecting a dopant which possibly causes the tail length LtJ-40to be small. For example, the tail length LtJ-40is reduced to be shorter than the tail length LtS-50by ion-implanting oxygen (O) into the junction region40and ion-implanting silicon (Si) or germanium (Ge) into the source region50. For example, the implantation depth of the peak P in the junction region40is 800 nm, and the tail length LtJ-40is smaller than 500 nm. In this case, for example, the implantation depth of the peak P in the source region50is 20 nm, and the tail length LtS-50is 500 nm. However, the doping concentration distribution of the junction region40and the source region50is not limited to the present example. In addition, the description about the doping concentration in the junction region40and the source region50in the present example is similarly applied to the description about the doping concentration according to all examples. The tail length LtJ-40may have approximately the same size as the tail length LtS-50. In one example, the tail length LtJ-40is within a range of ±10% of the tail length LtS-50. For example, the implantation depth of the peak P in the junction region40is 800 nm, and the tail length LtJ-40is 500 nm. In this case, for example, the implantation depth of the peak P in the source region50is 20 nm, and the tail length LtS-50is 500 nm. However, the doping concentration distribution of the junction region40and the source region50is not limited to the present example. In addition, the description about the doping concentration in the junction region40and the source region50in the present example is similarly applied to the description about the doping concentration according to all examples. While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention. The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams can be performed in any order as long as the order is not indicated by “prior to,” “before,” or the like and as long as the output from a previous process is not used in a later process. Even if the process flow is described using phrases such as “first” or “next” in the claims, embodiments, or diagrams, it does not necessarily mean that the process must be performed in this order. | 38,178 |
11862688 | Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale or proportion unless specifically stated to be of scale or proportion. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes. In the figures, similar components and/or features may have the same numerical reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components and/or features. If only the first numerical reference label is used in the specification, the description is applicable to any one of the similar components and/or features having the same first numerical reference label irrespective of the letter suffix. DETAILED DESCRIPTION Integrated power modules provide packaged semiconductor devices delivering higher power density than many standalone configurations. As power demands are increasing for a host of devices and machines, improved power modules are being developed. For systems requiring increased power levels, integration of the semiconductor devices may determine the overall power density of the power module. As increased demand and faster switching speeds are sought, materials characterized by a wider bandgap are being used. For example, power modules are attempting to incorporate switches or diodes including silicon carbide or gallium nitride. However, these faster switching materials may produce increased heat that can inhibit performance if not properly dissipated from the system. Many conventional power modules attempting to incorporate silicon carbide or gallium nitride have been limited in operational ability due to lower heat dissipation, which is often a result of the module configuration. A potential solution may be to improve a conduction path from the semiconductor devices to an associated heat sink, such as a cold plate, which may be performed by reducing component spacing and layer separation. However, due to component mismatches, these reductions may have been frustrated or prevented. For example, producing a planar power module including a planar heat-rejection surface may improve conductive contact with a cold plate or other heat sink. Similarly, increasing coupling between the circuitry, semiconductor switches, and baseplate, which may then be coupled with a heat sink, may improve heat dissipation during operation. Producing these closer couplings may be frustrated in conventional designs due to mismatches between components. For example, a circuit board on which the circuitry is disposed may be characterized by a different coefficient of thermal expansion compared to the baseplate. Were the semiconductor switches directly coupled with each of the circuit board and the baseplate, at least one of the components may warp during soldering operations. For example, the baseplate may warp during soldering operations, which can cause a number of issues. The circuit board may be fiberglass and copper, while the baseplate, such as direct bonded copper, may include ceramics characterized by different thermal properties that will cause the baseplate to warp. During cooling subsequent to the soldering, connections may fracture, which may limit performance, if not lead to yield loss. Additionally, a warped or non-planar baseplate may frustrate coupling with the heat sink, requiring increased coupling material, such as thermal paste, which may increase the thermal resistance between the components and limit performance due to lower heat dissipation. Consequently, many conventional designs are limited to separating the circuit board from the switches and including an additional gate drive board and board-to-board connectors, or producing a structure that will necessarily include a warped baseplate when the switches are soldered to each of the circuit board and the baseplate. Alternatively, some conventional technologies may include a gap pad between the semiconductor devices and the baseplate, which may greatly reduce thermal dissipation to the heat sink, limiting operational capabilities of the module. The present technology overcomes these issues by utilizing additional baseplate materials or designs, which may accommodate thermal expansion differences between the materials, and may allow closer coupling. By providing a direct coupling solution with the semiconductor device, gate drivers and other components may be positioned in closer proximity to the switches, which may be or include gallium nitride. With this closer connection, the decoupling loop for the capacitor and the gate drive loop may be greatly reduced, improving switching speeds. Consequently, dv/dt and di/dt related losses may be minimized in the present technology, which may allow devices according to some embodiments of the present technology to be operated over wider current and voltage ranges. Improved heat rejection may also be afforded, which may allow the gallium nitride switches to operate faster and more efficiently, further improving device performance. Although the remaining portions of the description will reference power modules including gallium nitride switches, it will be readily understood by the skilled artisan that the technology is not so limited. The present materials and techniques may be employed with any number of power module topologies and components, including other semiconductor materials such as silicon carbide, or other materials. Moreover, the present technology may be applicable to power modules used in any number of technologies that may include, without limitation, power conversion equipment including motor drives, power supplies, AC-DC power converters, high-voltage to low-voltage converters, or uninterruptable power supplies. The devices may be implementable in power grid applications, green technology such as including solar panels, home appliances, or any other system or device that may benefit from aspects of the present technology. FIG.1shows a schematic cross-sectional view of an integrated power module100according to some embodiments of the present technology. The figure may illustrate components and configurations that may be incorporated in any number of power modules according to some embodiments of the present technology. The figure illustrates top-side cooled devices in a configuration that may maintain a substantially consistent gap between the circuit board and the baseplate. Although some embodiments of the present technology may utilize direct-bonded copper as a baseplate or heat-transfer substrate as will be described further below, in some embodiments as illustrated, the baseplate or heat-transfer substrate may be or include an insulated metal substrate as the heat-transfer substrate105.FIG.1illustrates a power module that has been coupled with a cooling plate103or heat sink, which may be a gas or liquid-flowed heat sink. It is to be understood that the heat sink is illustrated for understanding of coupling according to some embodiments of the present technology, and may not be included in integrated power modules according to some embodiments of the present technology, including integrated power module100, such as where the heat sink may be incorporated with the system or device in which the power module is installed. The heat-transfer substrate105(e.g., the insulated metal substrate or IMS board) may include a metal substrate106as well as one or more layers illustrated as layer108. Layer108may represent one or more layers of insulation material and/or copper foil, as would be understood as being included in an IMS board. In some embodiments, a single insulation layer and a single copper foil layer may be included, although in other embodiments additional layers may be included. For example, by including multiple layers, one or more layers may be utilized as a grounding layer or an electromagnetic compatibility shielding, as well as current and/or thermal distribution layers. Accordingly, it is to be understood that layer108may include one or more layers of each of insulation and/or foil in embodiments of the present technology. Additionally, metal substrate106may be or include any number of metals, such as aluminum, copper, or other metals, although in some embodiments the metal may be copper. Although aluminum is utilized in some IMS boards, aluminum may be characterized by a coefficient of thermal expansion that may limit or otherwise impact coupling between the layers in configurations as illustrated. By utilizing copper as the metal substrate106in some embodiments, a planar substrate and more complete coupling during soldering processes may be maintained. Accordingly, such as in comparison to a direct-bonded copper substrate, although the integrated metal substrate may increase local thermal resistance at the insulation layer or layers, the substrate may afford a substantially planar profile at the base surface to be coupled with a cold plate or other device. This may maintain an overall increased heat dissipation potential compared to a direct-bonded carbon, which may be warped if soldering is included as described above, and which may be characterized by a greater overall resistance between the power module and a cold plate. By substantially planar is meant to encompass machine tolerances that may prevent perfect planarity, as well as natural surface roughness, but which may maintain a surface profile that may maintain a consistent surface that may provide contact with a cold plate or other component at greater than or about 90% of the base of the integrated metal substrate, and may maintain contact at greater than or about 95%, greater than or about 97%, greater than or about 99%, or more. Similarly, where a thermal grease or paste may be disposed between the integrated metal substrate and the cold plate, a thickness of the thermal paste may be consistent in thickness to +/−1%, +/−0.5%, +/−0.1% or less across greater than or about 90% of the area of contact, and may be maintained across greater than or about 95% of the area of contact, greater than or about 97% of the area of contact, greater than or about 99% of the area of contact, or more. Integrated power module100may include a circuit board110, which may be any type of printed circuit board, such as an FR4 board in non-limiting embodiments of the present technology. It is to be understood that the circuit board110may be any board that may be or include one or more fiberglass and/or copper layers, as well as any other circuit board materials. Any substrate that may operate to maintain auxiliary circuits or components may be encompassed in embodiments of the present technology, and may be used as circuit board110. Circuit board110may be characterized by a first surface112, and a second surface114, which may be opposite first surface112as illustrated. Mounted along, or coupled with, first surface112may be one or more components of a power module, such as surface-mounted components. Illustrated component115and component117may be or include any number of components in any configuration. It is to be understood that the present technology may be utilized for power modules characterized by any number of topologies, and any number of components may be included. For example, the components may be or include capacitors, gate drivers, diodes, switches, thermistors, connectors, such as including for a transformer, or sensors, which may be included to produce any topology such as may include switches, bride rectifiers, power converters, neutral-point-clamped configurations, inverters, or other topologies that may include any number of components to produce circuits of various structures. Accordingly, the figure and following figures are not intended to limit any aspect of the present technology. As illustrated, component115and component117may be soldered to the circuit board110, although any other coupling may be encompassed by the present technology. In some embodiments, integrated power module100optionally may include a dam120or other structure that may be coupled with the circuit board110about a periphery of an active region of the first surface112of the circuit board110. The dam may be plastic, rubber, or some polymeric material, which may be glued or otherwise adhered to the first surface112of the circuit board110as illustrated. Within dam120optionally may be included a potting122extending across the first surface112of the circuit board110, and which may further extend about the one or more surface mounted components, as illustrated. Potting122may be any number of materials, such as any rubber material, epoxy, silicone gel, or any other encapsulation material that may be used in semiconductor or electronic technologies. Additionally, potting122may be characterized by an increased thermal conductivity, which may afford improved heat dissipation from components, such as capacitors. Coupled with the second surface114of circuit board110may be one or more components, which may also be coupled with the insulated metal substrate. As illustrated, in some embodiments circuit board110may be separated from the heat-transfer substrate by the one or more components, although in some embodiments the circuit board may include certain components embedded, and may extend to contact the heat-transfer substrate. The components disposed between the circuit board110and the heat-transfer substrate105may include one or more gallium nitride components125, such as switches or transistors, used in power modules. Although the remaining description will identify the components as including gallium nitride, it is to be understood that in some embodiments additional semiconductor materials may be used, such as silicon-containing materials, including silicon or silicon carbide. Additionally, although two gallium nitride components125are illustrated, it is to be understood that integrated power modules according to some embodiments of the present technology may include any number of gallium nitride components125, including greater than or about 2, greater than or about 4, greater than or about 6, greater than or about 8, greater than or about 10, or more, depending on the topology, device size, and component configurations, for example. The gallium nitride components125may be coupled between the circuit board110and the heat-transfer substrate105as previously noted, and may be in contact with each component, such as being directly soldered to each of the second surface114of the circuit board110and the heat-transfer substrate105as illustrated. Additionally, to improve coupling and maintain location during the soldering process, in some embodiments an underfill126may be included along either surface of the gallium nitride components125, such as between the solder contacts along the second surface114of the circuit board110, as illustrated. Underfill126may be any number of materials used in solder underfilling, and may include an epoxy or other polymeric material along with any number of fillers, flow agents, or other materials. In some embodiments, integrated power modules according to the present technology may include one or more spacers130, which may be positioned at one or more positions between the circuit board110and the heat-transfer substrate105. Similar to gallium nitride components125, spacers130may be coupled between the circuit board110and the heat-transfer substrate105, and may be soldered to each of the circuit board110and the heat-transfer substrate105. Spacers130may include a metal material, such as copper, or some other material, which may provide one or more benefits to the power module, and the metal material may be plated with solder or other conductive coupling materials. For example, spacers130may be incorporated to maintain a specific gap distance between circuit board110and heat-transfer substrate105during reflow operations where solder on each side of the gallium nitride components125and/or spacers130may be melted to engage with the corresponding surfaces of the circuit board and the heat-transfer substrate. Spacers130may be positioned about a periphery of the boards, as well as within an internal area, and may be used to facilitate heat transfer from the circuit board in some embodiments. For example, in some embodiments one or more vias132may be formed at locations proximate one or more spacers, which may more readily draw heat from surface-mounted components to the spacers and underlying heat-transfer substrate. Vias132may extend at least partially through the circuit board110, and may extend fully through the circuit board110in some embodiments. The vias may couple with wire tracing or other heat sinks within the circuit board, as well as coupling proximate or with one or more surface-mounted components in embodiments of the present technology. Spacers130may similarly afford current sharing between the circuit board and the heat-transfer substrate based on coupling with layers of the components. Additionally, the spacers may be incorporated to provide electromagnetic compatibility shielding connection locations about the power module. The spacers may couple with foil layers of the heat-transfer substrate, as well as with the base metal layer, in some embodiments. Regardless, the spacers may provide access to the heat-transfer substrate, which may then provide lateral and vertical distribution and dissipation of heat. In some embodiments a molding140may be incorporated between and extend along and/or contact each of the circuit board110and the heat-transfer substrate105. Molding140may be any number of encapsulating materials used in semiconductor packaging, for example, and may include any of the materials noted previously for potting as well as other epoxy resins, hardeners, fillers, catalysts, or other agents that may be incorporated in molding or overmolding. Molding140may extend about the gallium nitride components125, as well as the spacers130, in some embodiments, and may provide additional rigidity to the power module and components. Additionally, the molding140may provide environmental protection, which may facilitate lower creepage and clearance requirements, and which may allow closer coupling of components, for example. This may increase the module density, while providing a stable package that can further distribute heat for improved heat transfer. Although shown at a similar lateral dimension as each of the circuit board110and the heat-transfer substrate105, in some embodiments the components may not be similarly sized. For example, in some embodiments the circuit board110may be characterized by longer lateral dimensions than the heat-transfer substrate. In some embodiments, the molding may then extend about the heat-transfer substrate and increase the lateral dimensions in order to provide conformity of dimensions about the power module. During dicing, the molding and/or the circuit board may be trimmed to provide vertical sidewalls for each material, for example. Integrated power modules according to embodiments of the present technology may also include one or more modifications to the structure illustrated inFIG.1, and which may provide additional flexibility to the module for a variety of environments and configuration capabilities. It is to be understood that any of the designs illustrated may show additional features of power module100, or may include any feature or aspect of power module100described above. Turning toFIG.2is shown a schematic cross-sectional view of an integrated power module200according to some embodiments of the present technology, and which may include more than one heat-transfer substrate. Integrated power module200may include any feature, aspect, component, or material from integrated power module100, and may illustrate additional features of integrated power module100in some embodiments. For example, integrated power module200may include any number of components as previously described, and which may be included in power module200. Integrated power module200may include multiple heat-transfer substrates, such as a first heat-transfer substrate205aand a second heat-transfer substrate205b,which may include any aspect of heat-transfer substrates discussed previously, and which may be an insulated metal substrate as previously described. The module may include a circuit board210, which may include one or more surface-mounted components215on a first surface of the circuit board, and which may be any of the materials and components previously described. The power module may include one or more gallium nitride components as previously described, and may include a number of heat-transfer substrates that is less than or equal to the number of gallium nitride components. For example, each gallium nitride component may include a corresponding heat-transfer substrate, or multiple gallium nitride components may share a heat-transfer substrate. Although any number of transistors or switches may be included in embodiments according to the present technology, in some embodiments the power module may include at least a first gallium nitride component225aand a second gallium nitride component225b.Each of the components may be coupled between and soldered to the second surface of the circuit board210. Additionally, the components may be soldered to a corresponding heat-transfer substrate. For example, as illustrated, first gallium nitride component225amay be coupled with first heat-transfer substrate205a,and second gallium nitride component225bmay be coupled with second heat-transfer substrate205b.As shown, the power module may also include a third heat-transfer substrate coupled with a third gallium nitride component, and a fourth heat-transfer substrate coupled with a fourth gallium nitride component. Consequently, any number of transistors and heat-transfer substrates may be incorporated in power modules according to embodiments of the present technology. In some embodiments potting optionally may be included as previously discussed, and a molding240may be included to support the power module and provide rigidity to the individual heat-transfer substrates and transistors. Molding240may extend along the second surface of the circuit board210, and may extend about and between the heat-transfer substrates and gallium nitride components. As explained previously, bonding the gallium nitride components to the circuit board and heat-transfer substrates may cause an amount of deformation of one of the substrates. By limiting the size of the substrate to be similar to the size of the component, stress produced due to mismatch may be accommodated. Additionally, subsequent the reflow operation and/or the molding formation, a planarization operation may be performed along a base of the power module to ensure a substantially planar surface across and along each of the heat-transfer substrates for coupling with a cold plate, for example. Although heat transfer may be reduced relative to a larger heat-transfer substrate as illustrated elsewhere in this disclosure, in some embodiments the individual heat-transfer substrates or the planarization operations may allow more flexibility of heat-transfer substrates, which may afford reduced packaging sizing as will be described further below. FIG.3shows a schematic cross-sectional view of an integrated power module300according to some embodiments of the present technology, and which may include a direct-bonded copper substrate as the heat-transfer substrate. Integrated power module300may include any feature, aspect, component, or material from integrated power module100, and may illustrate additional features of integrated power module100in some embodiments. For example, integrated power module300may include a heat-transfer substrate305characterized by a reduced thickness, such as a direct-bonded copper substrate, for example. The power module may include any number of other components as discussed previously for any other power module. For example, the module may include circuit board310, which may include one or more surface-mounted components315on a first surface of the circuit board, and which may be any of the materials and components previously described. The integrated power module300may include any number of gallium nitride components325as well as spacers330, which may be or include any of the components or configurations as discussed above. The module also optionally may include potting and/or molding as discussed above. As discussed previously, the soldering process for coupling the gallium nitride components with the circuit board and the heat-transfer substrate will cause the direct-bonded copper substrate to warp due to differences in the coefficient of thermal expansion of the substrate relative to the circuit board. Solder plated on each of the components may be used to accommodate the flexing that will occur in order to protect the coupling from fracturing during cooling. For example, the thickness of solder, or the size of solder bumps, may be adjusted across the substrate where an increased amount of solder may be utilized proximate edge regions or other locations where more deflection may occur. When the heat-transfer substrate305is a direct-bonded copper substrate, the substrate305may include a first layer of copper301and a second layer of copper303on opposite surfaces of a layer of a ceramic base302, where the first layer of copper301may be coupled with the components. The cooling process after soldering may cause the heat-transfer substrate to warp in any number of ways, and an arcuate profile may be produced. As explained previously, conventional technologies would be limited to increasing a thermal coupling layer, such as thermal paste, which may reduce heat transfer between the heat-transfer substrate and the cold plate, for example. The present technology may include modifications to the substrate as well as the soldering process. For example, during the reflow process where the solder may be heated, as well as during subsequent cooling, pressure may be applied across the power module, either upwards on the heat-transfer substrate, and/or downwards on the circuit board, which may reduce an amount of deflection during cooling. Again, the amount of solder may be adjusted to accommodate stress caused by the process. Accordingly, the amount of deflection may be reduced or minimized. Additionally, in some embodiments a subsequent planarization operation may be performed along the backside of the heat-transfer substrate. For example, as illustrated inFIG.3, a portion of the second copper layer303may be removed, as well as a portion of the ceramic layer302that may be exposed during the removal and depending on the extent of deflection, such as by grinding or other removal operations. This removal may produce a substantially planar profile across a backside of the heat-transfer substrate. Consequently, during a subsequent coupling with a cold plate, for example, similar contact or thermal paste thicknesses may be afforded as previously described. Despite the potential loss of copper on edge regions as illustrated, the improved thermal conductivity of the direct-bonded substrate may improve overall performance. Additionally, a subsequent operation may be performed to ensure copper along the base of the surface. For example, copper foil may be applied across the backside of the heat-transfer substrate subsequent the removal operation, for example, or copper may be applied or sputtered across the backside to improve a heat transfer profile. Hence, in some embodiments of the present technology, direct-bonded copper substrates may be employed as the heat-transfer substrate by accommodating the deformation that may occur during bonding. Additionally, direct-bonded copper substrates may be used in similar configurations as discussed previously with regard toFIG.2, where individual heat-transfer substrates are coupled with each of the gallium nitride switches.FIG.4shows a schematic cross-sectional view of an integrated power module400according to some embodiments of the present technology, and which may illustrate incorporation of direct-bonded copper substrates as individual heat-transfer substrates. Integrated power module400may include any feature, aspect, component, or material from integrated power module100, and may illustrate additional features of integrated power module100in some embodiments. Additionally, integrated power module400may include any of the features or aspects of integrated power module200discussed above, and which may include a similar design. For example, integrated power module400may include any number of components as previously described, and which may be included in power module400. Integrated power module400may include multiple heat-transfer substrates, such as a first heat-transfer substrate405aand a second heat-transfer substrate405b,which may include any aspect of heat-transfer substrates discussed previously, and which may be direct-bonded copper substrates as previously described. The first heat-transfer substrate405amay include a first layer of copper401aand a second layer of copper403aon opposite surfaces of a layer of a ceramic base402a.The second heat-transfer substrate405bmay include a first layer of copper401band a second layer of copper403bon opposite surfaces of a layer of a ceramic base402a.The first layers of copper401a,401bmay be corresponding coupled with components (e.g., gallium nitride components425a,425b). The module may include a circuit board410, which may include one or more surface-mounted components415on a first surface of the circuit board, and which may be any of the materials and components previously described. The power module may include one or more gallium nitride components as previously described, and may include a number of heat-transfer substrates that is less than or equal to the number of gallium nitride components. For example, each gallium nitride component may include a corresponding heat-transfer substrate. Although any number of transistors or switches may be included in embodiments according to the present technology, in some embodiments the power module may include at least a first gallium nitride component425aand a second gallium nitride component425b.Each of the components may be coupled between and soldered to the second surface of the circuit board410. Additionally, the components may be soldered to a corresponding heat-transfer substrate. For example, as illustrated, first gallium nitride component425amay be coupled with first heat-transfer substrate405a,and second gallium nitride component425bmay be coupled with second heat-transfer substrate405b.Again, it is to be understood that any number of transistors and heat-transfer substrates may be incorporated in power modules according to embodiments of the present technology. In some embodiments, potting optionally may be included as previously discussed, and a molding440may be included to support the power module and provide rigidity to the individual heat-transfer substrates and transistors. Molding240may extend along the second surface of the circuit board210, and may extend about and between the heat-transfer substrates and gallium nitride components. As explained above, direct-bonded copper substrates may be more likely to warp during cooling subsequent to a soldering process. By utilizing heat-transfer substrates that are sized similarly to, or slightly larger than, the switches, deformation may be limited or prevented during cooling. Additionally, as discussed previously, a subsequent planarization may be performed along the backside of the power module. However, with reduced sizing for the heat-transfer substrates, planarization may be limited, and may substantially maintain the copper on the backside of the direct-bonded copper substrate, which may improve heat transfer from the devices. FIG.5shows a schematic cross-sectional view of an integrated power module500according to some embodiments of the present technology, and which may show a power converter having incorporated transformer coils. Integrated power module500may include any feature, aspect, component, or material from any of the integrated power modules as discussed above, and may illustrate additional features of any integrated power module previously described, in some embodiments. For example, integrated power module500may be a power converter including multiple power modules on a single circuit board. For example the power converter may include an AC-to-DC converter including each module and the associated transformers, a high-voltage-to-low-voltage converter including each module and the associated transformers, or any other structure. As illustrated, the structure may include any number of components as previously described, and which may be included in power module500. Integrated power module500may include multiple heat-transfer substrates, such as a first heat-transfer substrate505aand a second heat-transfer substrate505b,which may include any aspect of heat-transfer substrates discussed previously, and which may be any of the substrates as previously described. The module may include a circuit board510, which may include one or more surface-mounted components515on a first surface of the circuit board, and which may be any of the materials and components previously described. Additionally, the components mounted across the circuit board may be separated into a first subset of components and a second subset of components, which may be on either side of a transformer coil520, which may separate the two modules of the converter. It is to be understood that the transformer is illustrated schematically to facilitate understanding of the device, and may be considerably larger than shown relative to other components of the converter or modules. The transformer coil520may be coupled with the first surface of the circuit board, and a second transformer coil may be coupled with the second surface of the circuit board between the two modules formed. Such a design may eliminate the need for transformer connectors, where the transformer may be characterized by embedded coils in the circuit board. This configuration may also provide a lower profile converter. Additionally, potting included on the top side, when used, may be included about the transformer coil as well, which may support and protect the components of the entire module. The heat-transfer substrates may be separated to support the incorporated modules, where heat-transfer substrate505amay support a first module of the converter, and heat-transfer substrate505bmay support a second module of the converter. For example, the heat-transfer substrate505amay be coupled with a first subset of gallium nitride components525aand optional spacers530a,and which may be coupled with a first region of the circuit board510, and associated with components on the circuit board for a first module. Similarly, the heat-transfer substrate505bmay be coupled with a second subset of gallium nitride components525band optional spacers530b,and which may be coupled with a second region of the circuit board510, and associated with components on the circuit board for a second module. The components and couplings may include any aspects of similarly-named components as described previously. By utilizing components and configurations according to embodiments of the present technology, improved power modules may be produced, which may overcome limitations in conventional configurations, and improve efficiency and heat transfer within the device. In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details. Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. Where multiple values are provided in a list, any range encompassing or based on any of those values is similarly specifically disclosed. As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a material” includes a plurality of such materials, and reference to “the spacer” includes reference to one or more spacers and equivalents thereof known to those skilled in the art, and so forth. Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups. | 38,593 |
11862689 | DESCRIPTION OF THE EMBODIMENTS When the expression “weight” is used herein, the expression may be replaced with “mass” that is commonly used as an SI unit representing a weight. A Group-III element nitride semiconductor substrate according to an embodiment of the present invention is typically a freestanding substrate formed of a Group-III element nitride crystal. In the description of the present invention, the term “freestanding substrate” means a substrate that is not deformed or broken by its own weight at the time of its handling, and hence can be handled as a solid. The freestanding substrate may be used as each of the substrates of various semiconductor devices, such as a light-emitting device and a power-controlling device. The Group-III element nitride semiconductor substrate according to the embodiment of the present invention is typically a wafer shape (substantially complete round shape). When the Group-III element nitride semiconductor substrate according to the embodiment of the present invention is a wafer shape, its size is as follows: its diameter is preferably from mm to 310 mm, and is typically, for example, 25 mm (about 1 inch), from 45 mm to 55 mm (about 2 inches), from 95 mm to 105 mm (about 4 inches), from 145 mm to 155 mm (about 6 inches), from 195 mm to 205 mm (about 8 inches), or from 295 mm to 305 mm (about 12 inches). Such size facilitates the application of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention to a production process for a semiconductor package. The substrate may be processed into any other shape such as a rectangular shape as required. The thickness of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention (when the thickness is not constant, the thickness of a site having the largest thickness) is preferably from 300 μm to 1,000 μm. Typical examples of the Group-III element nitride include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and a mixed crystal thereof. Those nitrides may be used alone or in combination thereof. The Group-III element nitride is specifically GaN, AlN, InN, GaxAl1-xN (1>x>0), GaxIn1-xN (1>x>0), AlxIn1-xN (1>x>0), or GaxAlyInzN (1>x>0, 1>y>0, x+y+z=1). Those nitrides may be doped with various n-type dopants or p-type dopants. Typical examples of the p-type dopant include beryllium (Be), magnesium (Mg), strontium (Sr), and cadmium (Cd). Those dopants may be used alone or in combination thereof. Typical examples of the n-type dopant include silicon (Si), germanium (Ge), tin (Sn), and oxygen (O). Those dopants may be used alone or in combination thereof. The plane direction of the Group-III element nitride semiconductor substrate may be set to any one of a c-plane, an m-plane, an a-plane, and a specific crystal plane tilted from each of the c-plane, the a-plane, and the m-plane, and particularly when the plane direction is set to the c-plane, the effects of the present invention are expressed to a larger extent. Examples of the specific crystal plane tilted from each of the c-plane, the a-plane, and the m-plane may include so-called semipolar planes, such as a {11-22} plane and a {20-21} plane. In addition, the plane direction is permitted to include not only a so-called just plane vertical to the c-plane, the a-plane, the m-plane, or the specific crystal plane tilted from each of the planes but also an off angle in the range of ±5°. The Group-III element nitride semiconductor substrate according to the embodiment of the present invention is a Group-III element nitride semiconductor substrate including a first surface and a second surface, wherein the first surface is a mirror surface, wherein the second surface has a second-surface central region and a second-surface outer peripheral region, wherein the second-surface central region is a mirror surface, and wherein the second-surface outer peripheral region is a non-mirror surface. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, when the first surface is defined as a main surface, and the second surface is defined as a back surface, as long as the plane direction of the Group-III element nitride semiconductor substrate is the c-plane, the main surface is typically a Group-III element polar surface, and the back surface is typically a nitrogen polar surface. However, various devices may be produced on the nitrogen polar surface depending on applications, and hence the main surface may be set to the nitrogen polar surface, and the back surface may be set to the Group-III element polar surface. The various devices may be implemented on the main surface, and an epitaxial crystal may be grown thereon. The back surface may be held with a susceptor or the like to transfer the Group-III element nitride semiconductor substrate according to the embodiment of the present invention. In the description of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the first surface is described as the main surface, and the second surface is described as the back surface. Accordingly, in this description, the term “main surface” may be replaced with “first surface,” the term “first surface” may be replaced with “main surface,” the term “back surface” may be replaced with “second surface,” and the term “second surface” may be replaced with “back surface.” FIG.1is a typical schematic sectional view of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention. As illustrated inFIG.1, a Group-III element nitride semiconductor substrate100according to the embodiment of the present invention typically includes a main surface10and a back surface20that are in a two-sided relationship, and a side surface30, the main surface10has a main-surface central region10aand a main-surface outer peripheral region10b, and the back surface20has a back-surface central region20aand a back-surface outer peripheral region20b. Although the main surface10has the main-surface central region10aand the main-surface outer peripheral region inFIG.1, the main surface may be free of any main-surface central region and any main-surface outer peripheral region unlike this example. Any appropriate form may be adopted as the end portion of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention to the extent that the effects of the present invention are not impaired. That is, the end-portion sectional shape of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention is not limited to such a rectangular shape as illustrated inFIG.1, and for example, the shape may be a shape in which both of the main surface side and back surface side of the end portion are chamfered so as to be flat surfaces (FIG.2A), may be a shape chamfered in an R-shape (FIG.2B), may be a shape in which only the main surface side of the end portion is chamfered so as to be a flat surface (FIG.2C), or may be a shape in which only the back surface side of the end portion is chamfered so as to be a flat surface (FIG.2D). In the Group-III element nitride semiconductor substrate100according to an embodiment of the present invention illustrated inFIG.2A, the main surface side and back surface side of its end portion are chamfered to arrange a main surface-side chamfered portion11and a back surface-side chamfered portion21. In the Group-III element nitride semiconductor substrate100according to an embodiment of the present invention illustrated inFIG.2B, the main surface-side chamfered portion11and the back surface-side chamfered portion21each become a curved surface chamfered in an R-shape, and the respective curved surfaces assemble on the outer peripheral edge of the substrate, and hence no flat side surface remains. In the Group-III element nitride semiconductor substrate100according to an embodiment of the present invention illustrated inFIG.2C, the main surface has the main surface-side chamfered portion11, the back surface is free of any back surface-side chamfered portion, the main surface-side chamfered portion11becomes a flat surface, the flat surface is tilted with respect to the main surface10, the back surface20, and the side surface30, and the side surface30is a flat surface. In the Group-III element nitride semiconductor substrate100according to an embodiment of the present invention illustrated inFIG.2D, the back surface has the back surface-side chamfered portion21, the main surface is free of any main surface-side chamfered portion, the back surface-side chamfered portion21becomes a flat surface, the flat surface is tilted with respect to the main surface10, the back surface20, and the side surface30, and the side surface30is a flat surface. The end portion of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention is of course not limited to the forms illustrated inFIG.2AtoFIG.2D. The main surface-side chamfered portion11may be arranged over the entirety (one entire round) of the main-surface outer peripheral region10b, or may be arranged only in part of the main-surface outer peripheral region10b. From, for example, the viewpoint of suppressing the chipping of the semiconductor substrate, the main surface-side chamfered portion11is preferably arranged over the entirety (one entire round) of the main-surface outer peripheral region10b. The back surface-side chamfered portion21may be arranged over the entirety (one entire round) of the back-surface outer peripheral region20b, or may be arranged only in part of the back-surface outer peripheral region20b. From, for example, the viewpoint of suppressing the chipping of the semiconductor substrate, the back surface-side chamfered portion21is preferably arranged over the entirety (one entire round) of the back-surface outer peripheral region20b. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the main surface is a mirror surface. That is, when the main surface10has the main-surface central region10aand the main-surface outer peripheral region10bas illustrated inFIG.1, both of the main-surface central region10aand the main-surface outer peripheral region10bbecome mirror surfaces. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the back surface has the back-surface central region and the back-surface outer peripheral region, the back-surface central region is a mirror surface, and the back-surface outer peripheral region is a non-mirror surface. That is, inFIG.1, the back-surface central region20ais a mirror surface, and the back-surface outer peripheral region20bis a non-mirror surface. In the case where the Group-III element nitride semiconductor substrate according to the embodiment of the present invention has a shape in which the back surface side is chamfered so as to be a flat surface as illustrated in, for example,FIG.2A,FIG.2B, orFIG.2D, the back surface-side chamfered portion may coincide with the back-surface outer peripheral region of the back surface. That is, inFIG.2A,FIG.2B, orFIG.2D, the back surface-side chamfered portion21may coincide with the back-surface outer peripheral region20b. Also in this case, the back-surface outer peripheral region20bis a non-mirror surface, and hence the back surface-side chamfered portion21is also a non-mirror surface. As described above, in the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the main surface is a mirror surface, the back-surface central region is a mirror surface, and the back-surface outer peripheral region is a non-mirror surface. That is, in the main surface and back surface of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, only the back-surface outer peripheral region is a non-mirror surface, and the other regions are mirror surfaces. The Group-III element nitride semiconductor substrate according to the embodiment of the present invention is a Group-III element nitride semiconductor substrate of such a type that both of its front and back surfaces are mirror surfaces in which only the back-surface outer peripheral region is subjected to non-mirror finish as described above. Accordingly, it is easy to visually distinguish the main surface and the back surface from each other, the end portion of the substrate is easily detected with an optical sensor, and the warping of the entirety of the substrate is reduced. In addition, it becomes easy to visually distinguish the main surface and the back surface from each other, and hence there is no need to form a secondary orientation flat. Thus, a large effective area (area that can be used in device production) of the semiconductor substrate can be secured. The term “mirror surface” refers to a surface subjected to mirror processing, the surface being brought into a state in which the roughness and waviness of the surface are reduced to such an extent that light is reflected after the mirror processing, and hence the fact that an object is reflected on the surface subjected to the mirror processing can be visually observed. In other words, the term refers to a surface in a state in which the magnitude of each of the roughness and waviness of the surface after the mirror processing is reduced to such an extent as to be sufficiently negligible with respect to the wavelength of visible light. An epitaxial crystal can be sufficiently grown on the surface subjected to the mirror processing. Any appropriate method may be adopted as a method for the mirror processing to the extent that the effects of the present invention are not impaired. An example of such method is a method including performing the mirror processing through use of one, or a combination of two or more, of the following apparatus: a polishing apparatus using a tape; a lapping apparatus using diamond abrasive grains; and a chemical mechanical polish (CMP) apparatus using a slurry such as colloidal silica and a polishing pad made of a nonwoven fabric. The term “non-mirror surface” refers to a surface that is not subjected to mirror processing, and a typical example thereof is a rough surface obtained by surface-roughening treatment. Any appropriate method may be adopted as a method for the surface-roughening treatment to the extent that the effects of the present invention are not impaired. Examples of such method include: laser texture processing; etching treatment including using various chemicals and gases; physical or chemical coating treatment; and texturing by machining. The surface roughness Ra of the back-surface outer peripheral region is preferably 100 nm or more, more preferably from 200 nm to 1,500 nm, still more preferably from 500 nm to 1,000 nm. When the surface roughness Ra of the back-surface outer peripheral region is adjusted within the ranges, it becomes easier to visually distinguish the main surface and back surface of the semiconductor substrate from each other, and the end portion thereof is more easily detected with the optical sensor. However, a case in which the surface roughness Ra of the back-surface outer peripheral region becomes excessively large is not preferred because damage to the semiconductor substrate becomes larger to be responsible for a crack. The surface roughness Ra of the back-surface central region is preferably 10 nm or less, more preferably from 0.1 nm to 2 nm, still more preferably from 0.1 nm to 1 nm, particularly preferably from 0.1 nm to 0.5 nm. When the surface roughness Ra of the back-surface central region is adjusted within the ranges, it becomes easier to visually distinguish the main surface and the back surface from each other, the end portion is more easily detected with the optical sensor, and the warping of the semiconductor substrate can be suppressed. The surface roughness Ra of the main surface is preferably 2 nm or less, more preferably 1 nm or less, still more preferably from 0.1 nm to 0.5 nm, particularly preferably from 0.1 nm to 0.2 nm. When the surface roughness Ra of the main surface is adjusted within the ranges, it becomes easier to visually distinguish the main surface and the back surface from each other, and the end portion is more easily detected with the optical sensor. The physical surface states of the main surface and back surface of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention are close to each other, and hence the warping of the substrate is small, preferably 50 μm or less, more preferably 40 μm or less, still more preferably 30 μm or less. When the warping of the substrate is more than 50 μm, at the time of the production of various devices through use of the semiconductor substrate, a production failure due to the thickness variation of a film-forming device or the focus shift of an exposing device for a semiconductor circuit may occur. The physical surface states of the main surface and back surface of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention are close to each other. Accordingly, the warping of the substrate is small, and the radius of curvature thereof is preferably 30 m or more, more preferably 50 m or more, still more preferably 70 m or more, particularly preferably 100 m or more. When the radius of curvature is less than 30 m, at the time of the production of various devices through use of the semiconductor substrate, the substrate cannot be fixed by adsorption in a process apparatus or on a conveying device, and hence a production failure due to, for example, the falling of the substrate may occur. It is easy to visually distinguish the main surface and the back surface from each other in the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, and hence there is no need to form a secondary orientation flat. Thus, a large effective area (area that can be used in device production) of the semiconductor substrate can be secured. That is, the Group-III element nitride semiconductor substrate according to the embodiment of the present invention is preferably free of any secondary orientation flat. FIG.3is a schematic plan view viewed from the main surface direction of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention. As illustrated inFIG.3, the main surface-side chamfered portion11may be arranged in the main surface. The main surface-side chamfered portion11is typically a region arranged in the main-surface outer peripheral region10b, the region ranging from an outer peripheral end portion12to a distance corresponding to a width D1 toward the inner direction of the main surface10over the entire periphery of the main-surface outer peripheral region. The width D1 of the main surface-side chamfered portion is a distance starting from the outer peripheral end portion12, the distance being in a normal direction with respect to a tangent in the outer peripheral end portion12toward the inner direction of the main surface10. The width D1 of the main surface-side chamfered portion is preferably constant in the entirety of the main surface-side chamfered portion11. FIG.4is a schematic plan view viewed from the back surface direction of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention. As illustrated inFIG.4, the back surface-side chamfered portion21may be arranged in the back surface. The back surface-side chamfered portion21is typically a region arranged in the back-surface outer peripheral region20b, the region ranging from an outer peripheral end portion22to a distance corresponding to a width D2 toward the inner direction of the back surface20over the entire periphery of the back-surface outer peripheral region. The width D2 of the back surface-side chamfered portion is a distance starting from the outer peripheral end portion22, the distance being in a normal direction with respect to a tangent in the outer peripheral end portion22toward the inner direction of the back surface20. The width D2 of the back surface-side chamfered portion is preferably constant in the entirety of the back surface-side chamfered portion21. As illustrated inFIG.4, the back-surface outer peripheral region20bis typically a region from the outer peripheral end portion22to a distance corresponding to a width d2 toward the inner direction of the back surface20when the back surface20is viewed from a surface direction. As illustrated inFIG.4, the width d2 of the back-surface outer peripheral region is a distance starting from the outer peripheral end portion22, the distance being in a normal direction with respect to a tangent in the outer peripheral end portion22toward the inner direction of the back surface20. The width d2 of the back-surface outer peripheral region is preferably constant over the entirety of the back-surface outer peripheral region20b. Any appropriate size may be adopted as the width d2 of the back-surface outer peripheral region in accordance with, for example, the size of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention to the extent that the effects of the present invention are not impaired. The width d2 of the back-surface outer peripheral region is preferably 5 mm or less, more preferably 3 mm or less, still more preferably 1 mm or less because the effect of the present invention can be expressed to a larger extent. The lower limit value of the width d2 of the back-surface outer peripheral region is preferably 0.2 mm or more, more preferably 0.5 mm or more because the effect of the present invention can be expressed to a larger extent. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the back surface-side chamfered portion may coincide with the back-surface outer peripheral region of the back surface. For example, inFIG.4, the back surface-side chamfered portion21may coincide with the back-surface outer peripheral region20b. In this case, inFIG.4, the width D2 of the back surface-side chamfered portion coincides with the width d2 of the back-surface outer peripheral region. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the back-surface outer peripheral region20bis preferably a light-shielding region configured to attenuate laser light having a wavelength of from 450 nm to 1,100 nm. When the back-surface outer peripheral region20bis a light-shielding region configured to attenuate the laser light having a wavelength of from 450 nm to 1,100 nm, it may become easy to visually distinguish the main surface and back surface of the substrate from each other, and the end portion thereof can be easily detected with an optical sensor. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the back-surface outer peripheral region20bis more preferably a light-shielding region configured to attenuate laser light having a wavelength of 650 nm by 10% or more. The warping of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention is preferably 50 μm or less. The measurement of the warping is described later. The radius of curvature of the Group-III element nitride semiconductor substrate according to the embodiment of the present invention is preferably 30 m or more, more preferably 40 m or more, still more preferably 50 m or more. The measurement of the radius of curvature is described later. The Group-III element nitride semiconductor substrate according to the embodiment of the present invention may be produced by any appropriate method to the extent that the effects of the present invention are not impaired. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, typically, as illustrated inFIG.5(A), a seed crystal film2is formed on the main surface1aof a base substrate1, and a Group-III element nitride layer3is formed on the Group-III element polar surface2aof the seed crystal film2. Next, a Group-III element nitride layer (seed crystal film2+Group-III element nitride layer3) serving as a freestanding substrate is separated from the base substrate1to provide a freestanding substrate100′ having a main surface10′ and a back surface20′. The freestanding substrate100′ may be obtained as illustrated inFIG.5(B)through the separation of the Group-III element nitride layer by a laser lift-off method including applying laser light from the back surface1bside of the base substrate1as indicated by the arrows A, or the freestanding substrate100′ may be obtained by a spontaneous separation method including utilizing a thermal shrinkage difference at the time of a temperature decrease after the formation of the Group-III element nitride layer3, or by slicing the Group-III element nitride layer3with a wire saw or the like. Any appropriate material may be adopted as a material for the base substrate to the extent that the effects of the present invention are not impaired. Examples of such material include sapphire, crystal-oriented alumina, gallium oxide, AlxGa1-xN (0≤x≤1), GaAs, and SiC. Any appropriate material may be adopted as a material for the seed crystal film to the extent that the effects of the present invention are not impaired. Examples of such material include AlxGa1-xN (0≤x≤1) and InxGa1-xN (0≤x≤1). Of those, gallium nitride is preferred. The material for the seed crystal film is more preferably gallium nitride that is recognized to show a yellow luminescence effect when observed with a fluorescence microscope. The term “yellow luminescence” refers to a peak (yellow luminescence (YL) or a yellow band (YB)) appearing in the range of from 2.2 eV to 2.5 eV in addition to an exciton transition (UV) from a band to another band. Any appropriate formation method may be adopted as a method of forming the seed crystal film to the extent that the effects of the present invention are not impaired. Such formation method is, for example, a vapor growth method, and preferred examples thereof include a metal organic chemical vapor deposition (MOCVD) method, a hydride vapor phase epitaxy (HVPE) method, a pulsed excitation deposition (PXD) method, a molecular beam epitaxy (MBE) method, and a sublimation method. Of those, a metal organic chemical vapor deposition (MOCVD) method is more preferred as the method of forming the seed crystal film. A growth temperature is preferably from 950° C. to 1,200° C. Any appropriate growth direction may be adopted as the growth direction of the Group-III element nitride crystal to the extent that the effects of the present invention are not impaired. Examples of such growth direction include: the normal direction of the c-plane of a wurtzite structure; the normal direction of each of the a-plane and m-plane thereof; and the normal direction of a plane tilted from each of the c-plane, the a-plane, and the m-plane. Any appropriate production method may be adopted as a method of producing the Group-III element nitride layer to the extent that the effects of the present invention are not impaired. Examples of such production method include: gas phase methods, such as a metal organic chemical vapor deposition (MOCVD) method, a hydride vapor phase epitaxy (HVPE) method, a pulsed excitation deposition (PXD) method, a molecular beam epitaxy (MBE) method, and a sublimation method; and liquid phase methods, such as an ammonothermal method and a flux method. Next, the freestanding substrate is shaped into a circular shape having a desired diameter by grinding its outer peripheral portion. Any appropriate size may be adopted as the size of the freestanding substrate to the extent that the effects of the present invention are not impaired. Such size is, for example, 25 mm (about 1 inch), from 45 mm to 55 mm (about 2 inches), from 95 mm to 105 mm (about 4 inches), from 145 mm to 155 mm (about 6 inches), from 195 mm to 205 mm (about 8 inches), or from 295 mm to 305 mm (about 12 inches). Next, the nitrogen polar surface of the circular freestanding substrate is bonded to a surface plate for processing. At the time of the bonding, the surface shape of the freestanding substrate is changed by changing the thickness of a wax through the adjustment of a load to be applied to the freestanding substrate, or by interposing a jig between the freestanding substrate and the surface plate for processing. Next, the freestanding substrate is turned into a thin plate having a desired thickness, and the surface of the Group-III element polar surface is flattened, through the removal processing of the Group-III element polar surface by grinding, lapping, polishing, or the like. Thus, a freestanding substrate in which the Group-III element polar surface is turned into a mirror surface is obtained. Next, the Group-III element polar surface of the freestanding substrate in which the Group-III element polar surface is turned into a mirror surface is bonded to a surface plate for processing. At the time of the bonding, the surface shape of the freestanding substrate is changed by changing the thickness of a wax through the adjustment of a load to be applied to the freestanding substrate, or by interposing a jig between the freestanding substrate and the surface plate for processing. Next, the freestanding substrate is turned into a thin plate having a desired thickness, and the surface of the nitrogen polar surface is flattened, through the removal processing of the nitrogen polar surface by grinding, lapping, polishing, or the like. Thus, a freestanding substrate in which the nitrogen polar surface is turned into a mirror surface is obtained. In this embodiment, the nitrogen polar surface is subjected to mirror finish after the Group-III element polar surface has been subjected to mirror finish. However, the order may be reverse to the foregoing. The thickness of the freestanding substrate after the polishing (when the thickness is not constant, the thickness of a site having the largest thickness) is preferably from 300 μm to 1,000 μm. Next, the outer peripheral edge of the freestanding substrate is chamfered by grinding. Finally, the Group-III element nitride semiconductor substrate100according to the embodiment of the present invention is obtained. In the Group-III element nitride semiconductor substrate according to the embodiment of the present invention, the chamfering may be performed by any appropriate chamfering method to the extent that the effects of the present invention are not impaired. Examples of such chamfering method include: grinding with diamond abrasive grains; polishing with a tape; and chemical mechanical polish (CMP) with a slurry such as colloidal silica and a polishing pad made of a nonwoven fabric. Next, the outer peripheral portion of the nitrogen polar surface is subjected to surface-roughening processing. Finally, the Group-III element nitride semiconductor substrate100according to the embodiment of the present invention is obtained. Any appropriate method may be adopted as a method for the surface-roughening processing to the extent that the effects of the present invention are not impaired. Examples of such method include: laser texture processing; etching treatment including using various chemicals and gases; physical or chemical coating treatment; and texturing by machining. A crystal can be epitaxially grown on the main surface (Group-III element polar surface)10of the Group-III element nitride semiconductor substrate100to be obtained, and the formation of a functional layer4as illustrated inFIG.5(C)provides a functional element5. Reference numeral20represents the back surface (nitrogen polar surface) of the substrate. When the warping of the main surface (Group-III element polar surface) and the warping of the back surface (nitrogen polar surface) differ from each other, the total thickness variation (TTV) of the freestanding substrate occurs. However, even when the total thickness variation of the freestanding substrate occurs, no large variation occurs on the main surface (Group-III element polar surface) at the time of the epitaxial growth of the functional layer on the freestanding substrate. This is because the following property is utilized: the thermal conductivity of the Group-III element nitride crystal for constituting the freestanding substrate is high. As a result, morphology abnormality at the time of the formation of the functional layer does not occur, and hence the shift of the luminous wavelength of the layer and variations in voltage-current characteristics thereof can be sufficiently suppressed. The epitaxial crystal to be grown on the Group-III element nitride semiconductor substrate to be obtained may be, for example, gallium nitride, aluminum nitride, indium nitride, or a mixed crystal thereof. Specific examples of such epitaxial crystal include GaN, AlN, InN, (1>x>0), GaxIn1-xN (1>x>0), AlxIn1-xN (1>x>0), and GaxAlyInzN (1>x>0, 1>y>0, x+y+z=1). In addition, examples of the functional layer to be arranged on the Group-III element nitride semiconductor substrate to be obtained include a rectifying element layer, a switching element, and a power semiconductor layer in addition to a light-emitting layer. In addition, the thickness and total thickness variation of the freestanding substrate may be reduced by subjecting the nitrogen polar surface to processing, such as grinding or polishing, after the arrangement of the functional layer on the Group-III element polar surface of the Group-III element nitride semiconductor substrate to be obtained. EXAMPLES The present invention is specifically described below by way of Examples. However, the present invention is by no means limited to Examples. Test and evaluation methods in Examples and the like are as described below. The term “part(s)” in the following description means “part(s) by weight” unless otherwise specified, and the term “%” in the following description means “wt %” unless otherwise specified. <Measurement of Surface Roughness Ra> The surface roughness (arithmetic average roughness) Ra of the surface of a Group-III element nitride semiconductor freestanding substrate was calculated with a non-contact surface shape-measuring machine (manufactured by Zygo Corporation, New View 7000, objective lens: ×5, software: MetroPro 9.0.10) in an observation field of view measuring 1.4 mm by 1.05 mm. The Ra of each of the main surface and back-surface central region of the substrate was measured at the central portion of the substrate, and when the width of the back-surface outer peripheral region thereof was represented by d2, the Ra of the back-surface outer peripheral region was measured at a position corresponding to a distance of d2/2 from a boundary between the back-surface central region and the back-surface outer peripheral region. When the width d2 of the back-surface outer peripheral region was narrower than the observation field of view measuring 1.4 mm by 1.05 mm, the measurement was performed while the observation field of view was appropriately narrowed. <Evaluation Criteria of Visual Distinction Between Main Surface and Back Surface> The main surface and back surface of a wafer were visually distinguished from each other by using a white fluorescent lamp as a light source in a room having an illuminance of from 817 LX to 893 LX. YOKOGAWA 510LUX METER was used as an illuminometer. A surface whose entirety was uniformly a mirror surface was defined as the main surface, and a surface whose outer peripheral portion was not a mirror surface was defined as the back surface. A case in which the distinction was able to be performed without any particular gaze was judged to be to “easy”, a case in which the distinction was able to be performed with a gaze was judged to be to “possible”, and a case in which clear distinction could not be performed even with a gaze was judged to be to “difficult”. The phrase “with a gaze” as used herein means that the main surface and the back surface are observed over a time period of 10 seconds or more while an observation angle is changed. <Evaluation Criteria of Detection of End Portion with Optical Sensor> A test for the detection of the end portion of a substrate was performed with a transmission photoelectric sensor. ZX-GT28S (wavelength: 650 nm) manufactured by OMRON Corporation was used as a light source and a detector, and an attenuation ratio at a wavelength of 650 nm was evaluated while the binarization level of a measured value was set to 50%. A laser intensity enabling the transmission photoelectric sensor to detect an edge was identified with a laser power sensor (manufactured by Ophir Optronics Solutions, Inc., 3A).o: Laser light having a wavelength of 650 nm can be attenuated by 10% or more (sensor judgment: acceptable).x: Laser light having a wavelength of 650 nm cannot be attenuated by 10% or more (sensor judgment: unacceptable). <Measurement of Warping> The warping of the main surface of a substrate was measured, and the radius of curvature thereof was calculated from the warping. The warping may be measured with a laser displacement meter. The term “laser displacement meter” refers to an apparatus for measuring the displacement of each surface by irradiating the surface with laser light. The wavelength of the laser light is set to 655 nm, and a confocal system, a triangular ranging system, or an optical interference system may be used as a measurement system in accordance with the surface roughness of the substrate. A waveform was obtained except for a range having a width of 3 mm from the end of the substrate. Next, a curve approximate to the waveform was obtained by a least-squares method including using a quadratic function. A difference between the maximum value and minimum value of the approximate curve was measured on each of two axes perpendicular to each other on the surface of the substrate, and the average of the two values was defined as a warping S. In addition, a radius of curvature R was calculated from the warping value through use of the following equation. The diameter of the substrate is represented by D. R=D2/(8·S) where the radius of curvature R, the substrate diameter D, and the warping S are represented in the unit of [m]. Example 1 A gallium nitride film having a thickness of 2 μm was formed on a 6-inch c-plane sapphire wafer by a MOCVD method to produce a seed crystal substrate. The seed crystal substrate was arranged in an alumina crucible having a diameter of 200 mm in a glove box under a nitrogen atmosphere. Next, metal gallium and metal sodium were loaded into the crucible so that the following ratio was obtained, followed by the lidding of the crucible with an alumina plate: Ga/Ga+Na (mol %)=15 mol %. The crucible was loaded into a stainless steel-made inner vessel, and the vessel was further loaded into a stainless steel-made outer vessel capable of storing the vessel, followed by the closing of the outer vessel with a vessel lid mounted with a nitrogen-introducing pipe. The outer vessel was arranged on a rotary table placed in a heating portion in a crystal-producing apparatus that had been baked in a vacuum in advance, and the pressure-resistant vessel of the apparatus was lidded and hermetically sealed. Next, the inside of the pressure-resistant vessel was evacuated to a vacuum of 0.1 Pa or less with a vacuum pump. Subsequently, while an upper heater, a middle heater, and a lower heater were regulated to heat a heating space so that its temperature became 870° C., a nitrogen gas was introduced from a nitrogen gas bomb into the pressure-resistant vessel until a pressure therein became 4.0 MPa, and the outer vessel was rotated about its central axis at a speed of 20 rpm clockwise and counterclockwise at a certain period. Then, the outer vessel was held under the state for 40 hours. After that, the temperature was naturally cooled to room temperature, and the pressure was reduced to atmospheric pressure. After that, the lid of the pressure-resistant vessel was opened, and the crucible was removed from its inside. Solidified metal sodium in the crucible was removed, and a gallium nitride crystal grown on the seed crystal substrate was recovered. UV laser light was applied from a sapphire wafer side to decompose the gallium nitride crystal on the seed crystal substrate. Thus, the grown gallium nitride crystal was separated from the sapphire wafer. The warping of the gallium nitride crystal obtained by the separation was 50 μm. The outer peripheral portion of the gallium nitride crystal was ground with diamond abrasive grains so that the diameter thereof was adjusted to 150 mm. Next, the gallium nitride crystal was bonded to a ceramic-made surface plate for processing, and the Ga polar surface thereof was ground and polished with a grinder and a lapping apparatus. The resultant surface was subjected to mirror finish serving as final finish with diamond abrasive grains each having a grain diameter of 0.1 μm. The gallium nitride crystal was reversed and fixed to the ceramic-made surface plate for processing, and the nitrogen polar surface thereof was similarly ground and polished. The resultant surface was subjected to mirror finish serving as final finish with diamond abrasive grains each having a grain diameter of 0.1 μm. A protective material was applied to each of the front and back surfaces of the gallium nitride crystal, and the outer peripheral portion of the wafer was molded with a beveling apparatus. The Ga polar surface was chamfered with tilted abrasive grains (tilt angle: 20°). The chamfering width D1 of the plane was set to 150 μm. The nitrogen polar surface was subjected to outer periphery surface-roughening processing by laser texture processing. An uneven shape was formed in the outer peripheral portion of the nitrogen polar surface with a UV laser having a wavelength of 355 nm and an output of 3 W by applying laser light condensed into a diameter of 70 μm to the portion while scanning the light. The range d2 of the surface-roughening processing was set to 3 mm from the outer periphery of the nitrogen polar surface. The front and back surfaces of the resultant Group-III element nitride semiconductor wafer were able to be visually distinguished from each other with ease. In addition, the warping of the wafer was 40 μm. The results are shown in Table 1. Example 2 A Group-III element nitride semiconductor wafer was produced in the same manner as in Example 1 except that the range d2 of the back surface-roughening processing was set to mm from the outer periphery. The front and back surfaces of the resultant Group-III element nitride semiconductor wafer were able to be visually distinguished from each other with ease. In addition, the warping of the wafer was 48 μm. The results are shown in Table 1. Example 3 A Group-III element nitride semiconductor wafer was produced in the same manner as in Example 1 except that the range d2 of the back surface-roughening processing was set to 1 mm from the outer periphery. The front and back surfaces of the resultant Group-III element nitride semiconductor wafer were able to be visually distinguished from each other. In addition, the warping of the wafer was 28 μm. The results are shown in Table 1. Comparative Example 1 A Group-III element nitride semiconductor wafer was produced in the same manner as in Example 1 except that the entire surface of the back surface was subjected to rough finish. The front and back surfaces of the resultant Group-III element nitride semiconductor wafer were able to be visually distinguished from each other with ease. In addition, the warping of the wafer was 105 μm. The results are shown in Table 1. Comparative Example 2 A Group-III element nitride semiconductor wafer was produced in the same manner as in Example 1 except that the range d2 of the back surface-roughening processing was set to 10 mm from the outer periphery. The front and back surfaces of the resultant Group-III element nitride semiconductor wafer were able to be visually distinguished from each other with ease. In addition, the warping of the wafer was 59 μm. The results are shown in Table 1. Comparative Example 3 A Group-III element nitride semiconductor wafer was produced in the same manner as in Example 1 except that the entire surface of the back surface was subjected to mirror surface finish. The front and back surfaces of the resultant Group-III element nitride semiconductor wafer could not be visually distinguished from each other. In addition, the warping of the wafer was 21 μm. The results are shown in Table 1. TABLE 1Width ofVisualouterdistinctionDetectionperipheralbetweenof endregionmainportionof backsurfacewithRadius ofsurfaceand backopticalWarpingcurvature(mm)surfacesensor(μm)(m)Example 13Easy○4070Example 25Easy○4859Example 31Possible○28100ComparativeNoneEasy○10527Example 1Comparative10Easy○5948Example 2ComparativeNoneDifficultx21134Example 3 The Group-III element nitride semiconductor substrate according to the embodiment of the present invention may be utilized as each of the substrates of various semiconductor devices. According to the present invention, such Group-III element nitride semiconductor substrate including the first surface and the second surface that it is easy to visually distinguish the first surface and the second surface from each other, that an end portion is easily detected with an optical sensor, that a large effective area can be secured, and that the warping of the entirety of the substrate is reduced can be provided. Many other modifications will be apparent to and be readily practiced by those skilled in the art without departing from the scope and spirit of the invention. It should therefore be understood that the scope of the appended claims is not intended to be limited by the details of the description but should rather be broadly construed. | 46,627 |
11862690 | DETAILED DESCRIPTION It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, there may be one or more additional operations in/between the described operations, and the order of operations may be changed. In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. Materials, configurations, dimensions, processes and/or operations same as or similar to those described with one embodiment may be employed in the other embodiments and the detailed explanation may be omitted. FIG.1shows a cross sectional view along the X direction of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device includes transistors disposed over a substrate10, having a gate electrode84disposed over a channel region20and a source region and a drain region (source/drain region50). The semiconductor device further includes one or more conductive wiring layers120formed in one or more interlayer dielectric layers95. In some embodiments, the channel region is a part of a fin structure protruding from an isolation insulating layer. A source/drain contact layer100, which may also be referred to as a local interconnect or a diffusion contact, is a conductive (e.g., metal or metallic) layer disposed on a source/drain region50(e.g., source/drain epitaxial layer) below the first (lowest) metal wiring layer. The source/drain contact layer100is also used to increase the height of the source/drain regions electrically connected to the first metal wirings. In such a case, the source/drain contact layer100does not necessarily connect two or more source/drain regions, and is disposed on one source/drain region. A via110is further disposed on the source/drain contact layer and embedded an etch stop layer96and multiple dielectric layers90,92and95. A gate contact layer130is also disposed on the gate electrode84. In some embodiments, plurality of line-shaped conductive layers are formed between adjacent gate electrodes and a cutting operation is performed to cut the line-shaped conductive layers into multiple source/drain contact layers, by removing part of the line-shaped conductive layers. In other embodiments, a plurality of grooves corresponding to the source/drain contact layers are formed between adjacent gate electrodes, and the grooves are filled with conductive material. FIGS.2A to13Cshow various views illustrating a sequential fabrication process for the source/drain contact layer100according to an embodiment of the present disclosure. In these figures, some layers/features are omitted for simplification. It is understood that additional operations can be provided before, during, and after processes shown by these figures, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIGS.2A-2Cshow one of the stages of a sequential fabrication process of a semiconductor device according to an embodiment of the present disclosure.FIG.2Ashows a plan (top) view,FIG.2Bshows a cross sectional view along line X1-X1ofFIG.2AandFIG.2Cshows a cross sectional view along Y1-Y1ofFIG.2A. As shown inFIGS.2A-2C, fin structures20, as active regions, are disposed over a substrate10, and separated by an isolation insulating layer (shallow trench isolation (STI))30. In some embodiments, the fin structures20include one or more fin structures for n-type fin field effect transistor transistors (Fin FETs) and one or more fin structures for p-type Fin FETs. The substrate10is, for example, a p-type silicon substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1018cm−3. In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1018cm3. Alternatively, the substrate may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group IV-IV compound semiconductors, such as SiC and SiGe; Group III-V compound semiconductors, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon-on insulator) substrate. In some embodiments, the fin structures20are patterned by any suitable method. For example, the fin structures20can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin structures. The isolation insulating layer30includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide are deposited. Flowable dielectric materials, as their name suggests, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), a mixture of MSQ and HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. The flowable film may be doped with boron and/or phosphorous. The isolation insulating layer30may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN and/or fluoride-doped silicate glass (FSG) in some embodiments. After forming a thick isolation insulating layer over the fin structures20, a planarization operation is performed so as to remove part of the isolation insulating layer. The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process. Then, the isolation insulating layer is further removed so that an upper part of the fin structure20, which is to become a channel layer, is exposed, as shown inFIG.2C. In certain embodiments, the partial removing of the isolation insulating layer30is performed using a wet etching process, for example, by dipping the substrate in hydrofluoric acid (HF). In another embodiment, the partial removing of the isolation insulating layer30is performed using a dry etching process. For example, a dry etching process using CHF3or BF3as etching gases is used. After forming the isolation insulating layer30, a thermal process, for example, an anneal process, is performed to improve the quality of the isolation insulating layer30. In certain embodiments, the thermal process is performed by using rapid thermal annealing (RTA) at a temperature in a range of about 900° C. to about 1050° C. for about 1.5 seconds to about 10 seconds in an inert gas ambient, such as an N2, Ar or He ambient. Then, a dummy gate structure40is formed over part of the fin structures20as shown inFIGS.2A-2C. A dielectric layer and a poly silicon layer are formed over the isolation insulating layer30and the exposed fin structures20, and then patterning operations are performed so as to obtain a dummy gate structure including a dummy gate electrode layer made of poly silicon and a dummy gate dielectric layer. The patterning of the poly silicon layer is performed by using a hard mask including a silicon nitride layer and an oxide layer in some embodiments. The dummy gate dielectric layer can be silicon oxide formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), e-beam evaporation, or other suitable process. In some embodiments, the dummy gate dielectric layer includes one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. In some embodiments, a thickness of the dummy gate dielectric layer is in a range of about 1 nm to about 5 nm. In some embodiments, the dummy gate electrode layer is doped poly-silicon with uniform or non-uniform doping. In the present embodiment, the width of the dummy gate electrode layer is in the range of about 30 nm to about 60 nm. In some embodiments, a thickness of the dummy gate electrode layer is in a range of about 30 nm to about 50 nm. In addition, one or more dummy gate structures may be disposed adjacent to both sides of the dummy gate structure40to improve pattern fidelity in patterning processes. The width of the dummy gate structure40is in a range of about 5 nm to about 40 nm in some embodiments, and is in a range of about 7 nm to about 15 nm in certain embodiments. Further, as shown inFIGS.2A-2C, sidewall spacers48are formed on opposite side faces of the dummy gate structures40. An insulating material layer for sidewall spacers48is formed over the dummy gate structure40. The insulating material layer is deposited in a conformal manner so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the dummy gate structure40, respectively. In some embodiments, the insulating material layer has a thickness in a range from about 5 nm to about 20 nm. The insulating material layer includes one or more of SiN, SiON and SiCN or any other suitable dielectric material. The insulating material layer can be formed by ALD or CVD, or any other suitable method. Next, bottom portions of the insulating material layer are removed by anisotropic etching, thereby forming sidewall spacers48. In some embodiments, the sidewall spacers46include two to four layers of different insulating materials. In some embodiments, part of the dummy gate dielectric layer is disposed between the sidewall spacers48and the isolation insulating layer30. In other embodiments, no part of the dummy gate dielectric layer is disposed between the sidewall spacers46and the isolation insulating layer30. InFIGS.2A-2C, four fin structures20and four dummy gate structures are shown. However, the numbers of the fin structures20and the dummy gate structures are not limited to four, respectively. FIGS.3A-3Cshow one of the stages of a sequential fabrication process of a semiconductor device according to an embodiment of the present disclosure.FIG.3Ashows a plan (top) view,FIG.3Bshows a cross sectional view along line X1-X1ofFIG.3AandFIG.3Cshows a cross sectional view along Y2-Y2ofFIG.3A. InFIG.3A, the isolation insulating layer30is omitted (transparent). Subsequently, a source/drain region of the fin structure20not covered by the dummy gate structure40is etched down (recessed) to form a source/drain recess25in some embodiments. In other embodiments, no recess is formed and the epitaxial layers are formed over the fin structure. FIGS.4A-4Cshow one of the stages of a sequential fabrication process of a semiconductor device according to an embodiment of the present disclosure.FIG.4Ashows a plan (top) view,FIG.4Bshows a cross sectional view along line X1-X1ofFIG.4AandFIG.4Cshows a cross sectional view along Y2-Y2ofFIG.4A. InFIG.4A, the isolation insulating layer30is omitted (transparent). After the source/drain recess25is formed, one or more source/drain epitaxial layers50are formed in and over the source/drain recess25. In some embodiments, two or more epitaxial layers having different compositions are formed as the source/drain epitaxial layer50. In some embodiments, the source/drain epitaxial layer50includes SiP or SiCP for an n-type FinFET, and SiGe doped with B for a p-type FinFET. In at least one embodiment, the source/drain epitaxial layers50are epitaxially-grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition or any other suitable method. The LPCVD process is performed at a temperature of about 400 to 850° C. and under a pressure of about 1 Torr to 200 Torr, using silicon source gas such as SiH4, Si2H6, or Si3H8; germanium source gas such as GeH4, or G2H6; carbon source gas such as CH4or SiH3CH3and phosphorus source gas such as PH3. In some embodiments, a silicide layer is further formed over the source/drain epitaxial layers50. FIGS.5A-5Cshow one of the stages of a sequential fabrication process of a semiconductor device according to an embodiment of the present disclosure.FIG.5Ashows a plan (top) view,FIG.5Bshows a cross sectional view along line X1-X1ofFIG.5AandFIG.5Cshows a cross sectional view along Y2-Y2ofFIG.5A. InFIG.5A, some of the layers over the sacrificial gate structures and source/drain epitaxial layers are omitted. Then, as shown inFIGS.5A-5C, an etch stop layer60is formed over the source/drain epitaxial layer50and the dummy gate structures40, and then a first interlayer dielectric (ILD) layer70is formed over the etch stop layer60. In some embodiments, the etch stop layer60is made of a silicon nitride based material, such as silicon nitride or SiON. The materials for the first ILD layer70include compounds comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the first ILD layer70. FIGS.6A-6Cshow one of the stages of a sequential fabrication process of a semiconductor device according to an embodiment of the present disclosure.FIG.6Ashows a plan (top) view,FIG.6Bshows a cross sectional view along line X1-X1ofFIG.6AandFIG.6Cshows a cross sectional view along Y2-Y2ofFIG.6A. InFIG.6A, some of the layers over the sacrificial gate structures and source/drain epitaxial layers are omitted. After the first ILD layer70is formed, a planarization operation, such as CMP, is performed, so that the top portion of the dummy gate structures40is exposed. Then, the dummy gate structures40including the dummy gate electrode layer and the dummy gate dielectric layer are removed, thereby forming gate spaces. The dummy gate structures can be removed using plasma dry etching and/or wet etching. When the dummy gate electrode layer is polysilicon and the first ILD layer70is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the dummy gate electrode layer. The dummy gate dielectric layer is thereafter removed using plasma dry etching and/or wet etching. In the gate spaces, a metal gate structure is formed. The metal gate structure includes a gate dielectric layer82and a metal gate electrode84as shown inFIG.6B. In some embodiments, an interfacial layer is formed on the fin structure20and a gate dielectric layer82is formed on the interfacial layer. In some embodiments, the interfacial layer is formed by chemical oxidation. In some embodiments, the interfacial layer includes one of silicon oxide, silicon nitride and mixed silicon-germanium oxide. The thickness of the interfacial layer is in a range from about 0.2 nm to about 6 nm in some embodiments. In some embodiments, the gate dielectric layer82includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, La2O3, HfO2—La2O3, Y2O3or other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer82may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer82is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layer. The thickness of the gate dielectric layer82is in a range from about 1 nm to about 100 nm in one embodiment. The metal gate electrode84includes one or more conductive layers disposed on the gate dielectric layer82. In some embodiments, the metal gate electrode layer includes one or more work function adjustment layers. In some embodiments, the work function adjustment layers are made of a conductive material such as a single layer of TiN, WN, TaAlC, TiC, TaAl, TaC, Co, Al, TiAl, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, an aluminum containing layer, such as TiAl, TiAlC, TaAl and/or TaAlC is used as an n-type WFM layer, and for the p-channel FET, one or more of TaN, TiN, WN, TiC and/or Co is used as a p-type WFM layer, in some embodiments. The metal gate electrode layer includes one or more body gate electrode layers formed on the work function adjustment layer. In some embodiments, the body gate electrode layer includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. FIGS.7A and7Bshow a perspective view and a plan view (a top view), respectively, illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure. As shown inFIG.7A, multiple layers are formed over the gate electrodes84and the first ILD layer70. In some embodiments, a first layer210is formed over the gate electrodes84and the first ILD layer70. In some embodiments, the first layer210is a dielectric layer such as silicon nitride, SiON, SiCN or SiOCN or other suitable material. In some embodiments, a thickness of the first layer210is in a range from about 2 nm to about 4 nm. In some embodiments, the first layer210functions as an etch stop layer. In some embodiments, a second layer220is formed over the first layer210. In some embodiments, the second layer220is a dielectric layer different from the first layer210and includes silicon oxide, SiOC, SiOCN or other suitable material. In some embodiments, a thickness of the second layer220is in a range from about 40 nm to about 80 nm. In some embodiments, the second layer220functions as a second ILD layer. In some embodiments, a third layer230is formed over the second layer220. In some embodiments, the third layer210is made of a different material than the second layer220. In some embodiments, the third layer230includes a metal alloy such as WC, WN, TiN, TaN or other suitable material. In other embodiments, the third layer230is made of a dielectric material, such as AlO, AlON, AlN, hafnium oxide, or other dielectric material. In some embodiments, a thickness of the third layer230is in a range from about 15 nm to about 30 nm. In some embodiments, the third layer230functions as a first hard mask layer. In some embodiments, a fourth layer240is formed over the third layer230. In some embodiments, the fourth layer240is a dielectric layer different from the third layer230and includes silicon oxide, SiOC, SiOCN or other suitable material. In some embodiments, a thickness of the fourth layer240is in a range from about 40 nm to about 50 nm. In some embodiments, the fourth layer240functions as a second hard mask layer. In some embodiments, a fifth layer250is formed over the fourth layer240. In some embodiments, the fifth layer250is made of a different material than the fourth layer240and includes amorphous silicon or polysilicon, or other suitable material. In other embodiments, the fifth layer250is made of a dielectric material, such as AlO, AlON, AlN, hafnium oxide, or other dielectric material. In some embodiments, a thickness of the fifth layer250is in a range from about 20 nm to about 40 nm. In some embodiments, the fifth layer250functions as a third hard mask layer. The first to fifth layers are formed by CVD, ALD or any suitable method. Then, as shown inFIG.7A, a tri-layer resist system is formed over the fifth layer250. The tri-layer resist system includes a bottom layer260as a sixth layer, a middle layer270as a seventh layer and a photo resist layer (pattern)280. In some embodiments, the bottom layer260is made of an organic material. The organic material may include a plurality of monomers or polymers that are not cross-linked. The bottom layer260contains a material that is patternable and/or have a composition tuned to provide anti-reflection properties in some embodiments. Exemplary materials for the bottom layer30include carbon backbone polymers, such as polyhydroxystyrene (PHS), poly methyl methacrylate (PMMA), polyether, and combinations thereof, and other organic polymers containing aromatic rings. In some embodiments, the bottom layer260is formed by a spin coating process. In other embodiments, the bottom layer260is formed by another suitable deposition process. The thickness of the bottom layer260is in a range from about 50 nm to about 100 nm in some embodiments. In some embodiments, after the bottom layer260is formed, an annealing operation is performed. The middle layer270includes a silicon containing polymer, such as polysiloxane in some embodiments. The thickness of the middle layer270is in a range from about 10 nm to about 30 nm in some embodiments. In the tri-layer resist patterning system, the photo resist layer280is patterned using one or more lithography operations, as shownFIG.7A. The photo resist pattern280corresponds to areas where no source/drain contact layer is formed. FIG.7Cshows a cross sectional view illustrating one of the stages of a sequential semiconductor device fabrication process, andFIGS.8A and8Bshow a perspective view and a plan view (a top view), respectively, illustrating one of the stages of a sequential semiconductor device fabrication process, according to an embodiment of the present disclosure. In some embodiments, the middle layer270is etched by using the photo resist pattern280as an etching mask, and the bottom layer260is etched by using the patterned middle layer as an etching mask, as shown inFIG.7C. Then, the fifth layer250is etched by using the patterned middle layer270and/or bottom layer260as etching mask, as shown inFIGS.8A and8B. In some embodiments, the middle layer270and the bottom layer260are subsequently removed. FIGS.9A and9Bshow a perspective view and a plan view (a top view), respectively, illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure. Then, as shown inFIGS.9A and9B, a tri-layer resist system is formed over the patterned fifth layer250. The tri-layer resist system includes a bottom layer310, a middle layer320and a photo resist layer (pattern)330. The materials and configurations of the tri-layer resist system are explained as set forth above. The photo resist pattern330includes line-and-space patterns extending in the Y direction (gate extending direction). FIGS.10A-10Dshow cross sectional views illustrating various stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure. As shown inFIG.10A, the middle layer320is patterned by using the photo resist pattern330as an etching mask. Then, in some embodiments, as shown inFIG.10B, another photo resist pattern having line-and-space patterns is formed over the patterned middle layer320, and the patterned middle layer320is further patterned by using the photo resist pattern340as an etching mask. The remaining middle layers320disposed above the gate electrode and the spaces formed by the middle layers320correspond to the source/drain contact layers. After the middle layer320is patterned as shown inFIG.10C, the bottom layer310is patterned by using the patterned middle layer320as an etching mask. Then, the fourth layer240and the third layer230are patterned into line-and-space patterns by using the pattered bottom layer310as an etching mask. In this etching operation, the patterned fifth layer250having island shapes is not patterned. Accordingly, part of the fourth layer240and the third layer230under the patterned fifth layer250remains as shown inFIG.10D. In some embodiments, the fifth layer250, the fourth layer240and the third layer230are made of different materials from each other. FIGS.11A and11Bshow a perspective view and a plan view (a top view), respectively, illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure. After the fourth layer240and the third layer230are patterned, the middle layer320and the bottom layer310are removed, and the fifth layer250is removed, as shown inFIGS.11A and11B. The patterned fourth layer240corresponds to the photo resist pattern280, which has been extended to the fifth layer250. The spaces between the patterned middle layer320extend the Y direction, and a portion where no fifth pattern250is formed is etched to remove the fourth layer and the third layer, and a portion where the fifth pattern250is formed is protected from the etching, thereby leaving the fourth layer and the third layer. As shown inFIG.11B, the spaces not covered by the patterned third layer230and the patterned fourth layer240correspond to the source/drain contact layers. In other words, the spaces formed by the patterned third layer230are cut by the patterned fourth layer240. FIGS.12A and12Bshow a perspective view and a plan view (a top view), respectively, illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure. Subsequently, the second layer220, the first layer210and the first ILD layer70are patterned by using the combination of the patterned third layer230and the patterned fourth layer240as an etching mask, and thereby forming spaces72. Then, the patterned third layer230and the patterned fourth layer240are removed, as shown inFIGS.12A and12B. FIGS.13A,13B and13Cshow a perspective view, a plan view (a top view) and a cross sectional view, respectively, illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure. The spaces72are filled by a conductive material, thereby forming a source/drain contact layer100, as shown inFIGS.13A-13C.FIG.13Cshows a cross sectional view along the line X2-X2ofFIG.13A. One or more layers of conductive material, such as tungsten, titanium, cobalt, molybdenum and nickel, or silicide thereof, an alloy thereof or other suitable materials, are formed in the spaces72and the second layer210, and a planarization operation, such as CMP, is performed. FIG.14shows an application of the foregoing technique to a standard cell structure of a semiconductor device. In some embodiments, CMOS circuits are disposed in cell regions between two power rail regions in which power supply wirings for Vdd and Vss are disposed. The gate electrodes extend in the Y direction and are arranged in the X direction, and active regions extend in the X direction and are arranged in the Y direction. In a case of a fin field effect transistor (FinFET), each of the active regions includes one or more fin structures extending in the X direction and arranged in the Y direction. In some embodiments, source/drain contact layers are disposed on and/or connecting source/drain regions of the active regions (fin structures). As shown inFIG.14, the pattern of the source/drain contact layer is generated by a subtractive operation of general line patterns and cut patterns. The manufacturing operation, as set forth above, achieves this subtractive operation. FIG.15is an enlarged layout view of a power rail region of a standard cell structure according to an embodiment of the disclosure. In some embodiments, one or more vias (110) connect the source/drain contact layers (the remaining general patterns cut by the cut patterns) and the power supply wiring. When the device size shrinks, margins between the vias and the cut patterns and/or margins between adjacent cut patterns decrease. In some embodiments, the adjacent cut patterns merge with each other. In such a case, when the cut patterns are formed as a photo resist pattern280as shown inFIG.7A, a wavy line pattern would be formed. In other cases, island shapes of the cut patterns are rounded in the photo resist patterns. Such deformation of the cut patterns in the photo resist patterns may cause insufficient landing of the vias to the source/drain contact layer. The embodiments disclosed herein solve this problem. FIG.16shows a top view illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure.FIG.16shows a photo resist pattern280of a part of the cut pattern shown inFIG.15, as explained with respect toFIGS.7A and7B. In some embodiments, in the original layout shown inFIG.15, the width W1of the cut pattern is set in a range from about 15 nm to about 20 nm. As shown inFIG.16, the width W2of the photo resist pattern280corresponding to the cut pattern is about 25% to about 45% greater than W1. The width W2can be adjusted by adjusting one or more parameters in the photo lithography operation and/or by adjusting a mask bias of a photo mask for the cut patterns. Then, as shown inFIGS.17A and17B, a directional process is performed to reduce the width of the photo resist pattern280along the Y direction. In some embodiments the directional process is a directional ion implantation process. In some embodiments, the ions (energetic species) are mainly implanted to the side faces of the photo resist pattern280. In some embodiments, the ions are Ar ions. In other embodiments, the ions are one or more of As, P, B, C, Si, He, Ne or any other suitable elements. The ion implantation dose is in a range of about 1×1014cm−2to about 5×1016cm−2with an implantation energy of about 0.5 keV to about 100 keV, or about 30 keV to about 50 keV. In some embodiments, the ions are implanted with an angle of about 0° to about 300° or about 30° to about 65° relative to the horizontal surface in the x-y plane (the horizontal surface of the substrate). In some embodiments, the angle is more than 0 degrees and equal to or less than about 20°. By the directional ion implantation process, the width W3of the photo resist pattern280is about 10% to about 30% smaller than the width W2. In some embodiments, the connected photo resist patterns280are separated by the directional ion implantation process as shown inFIG.17C. In some embodiments, the directional ion implantation is performed only along the Y directions (+Y and −Y directions), and no directional ion implantation is performed along other directions (+X or −X directions). In other embodiments, the directional process is a directional etching process. The directional etching can be characterized as horizontal or surface anisotropic or selective etching, in which a target layer or pattern is etched substantially only one direction (e.g., Y direction) within a plane (X-Y plane) parallel to a substrate, substantially without etching another direction (e.g., X direction). A directional etching can be performed by tuning various etching parameters to generate etching species (free radicals) that travel in a substantially horizontal direction or are incident on the substrate with a large incident angle of more than about 30-90 degrees (where the angle of 90 degrees is horizontal). The etching parameters to be tuned include, but are not limited to, etchant (gas) composition, etching temperature, etching time, etching pressure, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, wafer tilting, other suitable etching parameters, or combinations thereof. FIG.18Ashows a schematic view of a directional patterning apparatus, andFIGS.18B,18C and18Dshow schematic views of directional patterning in accordance with an embodiment of the present disclosure. As shown inFIG.18A, the directional patterning apparatus, for example, a directional etching apparatus1000includes a main chamber1010in which a wafer stage1030for a wafer to be processed is disposed, and a plasma generation chamber1020for generating plasma. In some embodiments, the plasma is RF (radio frequency) generated plasma, using a high frequency power supply at 13.56 MHz and/or 2.45 GHz. Other frequency ranges may be used. A separation plate1026is disposed between the main chamber1010and the plasma chamber1020. The separation plate1026includes a slit1022from which plasma beams1100are introduced into the main chamber. In some embodiments, an adjustable meniscus1024is provided over the slit1022in the plasma chamber side. One or more vacuum systems1040including, for example, a turbo molecular pump, is coupled to the main chamber and to the plasma chamber (not shown) to maintain reduced pressure states in the chambers. In some embodiments, during the etching process, the pressure in the main chamber is lower than the pressure in the plasma chamber. In certain embodiments, the pressure in the main chamber is in the order to 1×10−5Torr, and the pressure in the plasma chamber is in the order to 1×10−3Torr. In some embodiments, the separation plate1026and the wafer stage1030are biased by DC voltage, respectively, to extract and control the plasma beams1100. Further, the wafer stage1030is movable by a moving mechanism1035to scan the wafer relative to the plasma beams1100. In some embodiments, at least one of RF and DC bias voltages is tuned to achieve an electric field that causes etching species to flow substantially horizontally along an in-plane direction (for example, in the X direction) relative to a surface over the substrate, or to provide a large incident angle. In some embodiments, the etching species are tuned to have a profile of momenta of the energetic species such that the momenta of the etching species or energetic species along a frontline are not the same, i.e., the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species on the bottom path. In some embodiments, the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species in the middle path above the bottom path, and the momentum of the etching or energetic species on the top path is the same as or different from the momentum of an etching or energetic species on the bottom path. Any combinations can be achieved by adjustment of the electromagnetic control to tune the energies of the etching or energetic species alone the etching front. In some embodiments, the etching gas includes oxygen, fluorine, carbon, argon, hydrogen, hydrocarbon, and/or nitrogen or any other suitable species. In some embodiments, as shown inFIGS.18B and18C, a position of the meniscus1024is adjusted to change the incident angle θi of the plasma beams1100. As shown inFIG.18D, by scanning the wafer along the Y direction, a groove pattern can be formed without substantially expanding the groove in the X direction. In some embodiments, a ratio of an amount of etching in the Y direction to an amount of etching in the X direction is about 2 or more, and is about 5 or more in other embodiments. In certain embodiments, the ratio is about 10 or more. Ideally, the ratio is as high as possible, but it can be up to about 100 in some embodiments and up to about 50 in other embodiments. Further, an amount of etching along the Z direction (vertical direction) is smaller than the amount of etching in the Y direction. In some embodiments, a ratio of an amount of etching in the Y direction to an amount of etching in the Z direction is about 2 or more, and is about 5 or more in other embodiments. In certain embodiments, the ratio is about 10 or more. Ideally, the ratio is as high as possible, but it can be up to about 100 in some embodiments and up to about 50 in other embodiments. By the directional etching process, the width W3of the photo resist pattern280is about 10% to about 30% smaller than the width W2. In some embodiments, the connected photo resist patterns280are separated by the directional etching process as shown inFIG.17C. In some embodiments, the directional etching process is performed only along the Y directions (+Y and −Y directions), and no directional etching process is performed along other directions (+X or −X directions). FIGS.19A and19Bshow top views illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure.FIGS.19A and19Bshow a patterned fifth layer250patterned by the process explained above with respect toFIGS.7A-8B. As shown inFIG.19A, the patterned fifth layer250is further reduced from the photo resist patterns280as shown inFIG.17A. In some embodiments, the width W4of the patterned fifth layer250along the Y direction is about 20% to about 30% smaller than the width W3. In some embodiments, a residual piece remains between the corners of the cut patterns of the fifth layer250as shown inFIG.19A. When the photo resist pattern280is separated by the direction process as shown inFIG.17C, no residual pieces remains and the continuous patterns is divided into island patterns as shown inFIG.19Bin some embodiments. FIG.20shows a top view illustrating one of the stages of a sequential semiconductor device fabrication process according to an embodiment of the present disclosure.FIG.20shows a patterned fourth layer240patterned by the process explained above with respect toFIGS.9A-11B. As shown inFIG.20, the cut pattern240includes island patterns similar to the designed patterns as shown inFIG.15. In some embodiments, the width X5of the patterned fourth layer240along the Y direction is about ±20% of the width W4. In some embodiments, no residual pieces remains. After the fourth layer240is patterned, the operation explained with respect toFIGS.12A-13Care performed to form the source/drain contact layers100. The various embodiments or examples described herein offer several advantages over the existing art. For example, in the present disclosure, since a directional process is employed to adjust a width of a first resist pattern, an influence of a deformation in the first photo resist pattern is eliminated or suppressed in the hard mask pattern. The technology as disclosed can increase the margin between vias and source/drain contact layers. It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages. According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern. In one or more of the foregoing and the following embodiments, the adjusting the width of the first photo resist pattern comprises a directional etching process or a directional ion implantation process. In one or more of the foregoing and the following embodiments, the first photo resist pattern includes a continuous pattern, and the first hard mask pattern includes a corresponding continuous pattern, and the corresponding continuous pattern is divided into island patterns in the second hard mask pattern. In one or more of the foregoing and the following embodiments, the first photo resist pattern includes a continuous pattern, and the first hard mask pattern includes a corresponding continuous pattern, and the corresponding continuous pattern is divided into island patterns connected by a residual pattern or with a residual pattern therebetween, in the second hard mask pattern. In one or more of the foregoing and the following embodiments, the hard mask layer includes amorphous silicon or polysilicon. In one or more of the foregoing and the following embodiments, one or more second resist layers are further formed over the second hard mask pattern, a third hard mask pattern is formed by patterning the one or more second resist layers, and the one or more layers are patterned by using the third hard mask pattern and the second hard mask pattern as an etching mask, thereby forming a fourth hard mask pattern. In one or more of the foregoing and the following embodiments, the underling structure further comprises a first interlayer dielectric (ILD) layer disposed over the source/drain epitaxial layers and a second ILD layer disposed over the first ILD layer and gate electrodes. Further, the second ILD layer and the first ILD layer are patterned by using the fourth hard mask pattern as an etching mask, thereby forming trench patterns, and source/drain contact patterns are formed by filling the trench patterns with a conductive material. In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, an underlying structure is formed. The underlying structure includes fin structures disposed over a substrate, gate structures disposed over upper portions of the fin structures, source/drain epitaxial layers over source/drain regions of the fin structures, and an interlayer dielectric (ILD) layer over the source/drain epitaxial layer. A first layer is formed over the underlying structure, a second layer is formed over the first layer, a third layer is formed over the second layer, a fourth layer is formed over the third layer, and a fifth layer is formed over the fourth layer. A first resist layer is formed over the fifth layer and a dimension of the first photo resist layer is adjusted. The first resist layer is patterned by using a first photo resist pattern as an etching mask, and the fifth layer is patterned by using the patterned first resist layer as an etching mask. A second resist layer is formed over the patterned fifth layer, the second resist layer is patterned by using one or more second photo resist patterns as an etching mask, the fourth and third layers are patterned by using the patterned second resist layer and the patterned fifth layer as an etching mask, the second layer, the first layer and the ILD layer are patterned by using the patterned fourth and third layers as an etching mask, thereby forming trench patterns over the source/drain epitaxial layers, and source/drain contact patterns are formed by filling the trench patterns with a conductive material. In one or more of the foregoing and the following embodiments, the adjusting the width of the first photo resist pattern comprises a directional etching process. In one or more of the foregoing and the following embodiments, in the directional etching process, an etching rate of the first photo resist pattern along a first axis is twice or more an etching rate of the first photo resist pattern along a second axis perpendicular to the first axis. In one or more of the foregoing and the following embodiments, the adjusting the width of the first photo resist pattern comprises a directional ion implantation process which implant ions in a direction having an angle of more than 0 degrees and equal to or less than 20 degrees with respect to an upper surface of the first resist layer. In one or more of the foregoing and the following embodiments, in the directional ion implantation process, argon ions are implanted into the first photo resist pattern. In one or more of the foregoing and the following embodiments, the fifth layer includes amorphous silicon or polysilicon. In one or more of the foregoing and the following embodiments, the third layer includes at least one of WC, WN, TiN or TaN. In one or more of the foregoing and the following embodiments, at least one of the second layer or the fourth layer includes silicon oxide. In one or more of the foregoing and the following embodiments, each of the first and second resist layer includes a bottom layer including an organic material and a middle layer including a silicon containing polymer. In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern. The first photo resist pattern includes a continuous pattern located in a power rail region where a power supply wiring is to be formed, and a corresponding second hard mask pattern includes divided island patterns in the power rail region. In one or more of the foregoing and the following embodiments, the continuous pattern is formed by multiple patterns arranged along a first direction, and the width of the first photo resist pattern along a second direction crossing the first direction is reduced. In one or more of the foregoing and the following embodiments, the width of the first photo resist pattern along the second direction is reduced by 10% to 30%. In one or more of the foregoing and the following embodiments, a width of the divided island pattern along the second direction is 10% to 20% smaller than the width of the first photo resist pattern after the width is reduced. The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 49,601 |
11862691 | Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION Referring now toFIGS.1A and1B, a mesa structure10is shown having a substrate12, here for example, a semiconductor substrate such as gallium arsenide (GaAs), gallium nitride (GaN), silicon (Si), gallium oxide (Ga2O3), or silicon carbide (SiC); a gallium nitride (GaN) buffer layer14on the substrate12and an aluminum gallium nitride (AlGaN) layer16on, and forming a heterojunction with, the GaN layer14. A source electrode18and a drain electrode20are in ohmic contact with the AlGaN layer16and a gate electrode22, disposed between the source electrode18and drain electrode20is here in Schottky contact with the AlGaN layer16, the gate electrode being used for controlling a flow of carriers between the source electrode18and the drain electrode20through a two-dimensional electron gas (2DEG) channel formed by the heterojunction. Referring now toFIGS.2A and2B, a layer of dielectric material, here silicon nitride (SiNx), SiO2, Al2O3, or Ta2O5, for example, is formed over the surface of the structure by plasma enhanced chemical vapor deposition (PECVD), Low Pressure Chemical Vapor Deposition, for example, and patterned using conventional photolithography and etching processes to form a dielectric layer24over the surface as shown inFIG.2B. The layer24extends from a portion of the drain electrode20, over the surface of the AlGaN layer16between the drain electrode20and the gate electrode22, over the top and sides of the gate electrode22and then over the surface of the AlGaN layer16between the gate electrode22and the source electrode18and then over a portion of the source electrode18as shown. It should be noted that if the dielectric layer24is not of sufficient quality, a second dielectric layer24′, can be deposited over the layer24for this purpose as will be described below in connection withFIG.4B′. Continuing withFIGS.3A and3B, a mask28having a window30therein is disposed over the upper surface of the structures as shown. Ions41, (here negative charge indicated by the symbol (−) from a source29external to the semiconductor structure10, here the source29is an ion implanter, are implanted via ion implantation into the portions of the dielectric layer24exposed by the window30. Here, the distribution is uniform along the direction parallel to the surface of dielectric layer24and has a predetermined distribution in the depth of dielectric layer24; here, for example, a Gaussian distribution having a peak at a predetermined depth into upper surface of dielectric layer24. More particularly, ions are deposited into the region between drain and gate utilizing ion implantation of proper species (heavy ion to reduce diffusion in subsequent processing steps), charge (negative for n-channel transistors and positive for p-channel transistors, energy (low energy to create shallow layer in dielectric layer24), and dose (sufficient dose to create the correct electrical potential of the self-biased field plate). This charge (ions) is deposited utilizing mask28, here a photolithographically defined mask, to restrict the region of implantation to the region between drain20and gate22without extending into the region between gate22and source18so as to eliminate any possible increase of the parasitic gate to source capacitance. The window30need not be merely a simple open window to deposit the charge uniformly into layer24, but may be modified to tailor the charge (ion) distribution and resultant semiconductor field such as a stipple of dots30′ or stripes30″ as shown for masks28′ and28″ inFIGS.6A and6BandFIGS.7A and7B, respectively to create a diffraction-like grating pattern to tailor the charge distribution and resultant semiconductor field. For example, the apertures30′ and30″ may be arranged in size and spacing to provide a graded charge distribution. Thus, the charge41is deposited non-uniformly into the dielectric layer24. Thus, the masks28′ or28″ provide a predetermined, non-uniform, distribution of ions along the surface of the dielectric layers24or24′. The correct ions to implant should be relatively large (slow thermal diffusion), such as negative ions Sr−, Ba−, Ra−, and Ca−, or positive ion of Cs+, and also be electrically stable to modify the semiconductor field over the expected device lifetime. The correct energy would be somewhat low to create a shallow, well defined sheet charge; for example, in a range of 10-40 keV. The correct dose would be determined through simulations and experiments and would depend on the masking method (rectangular or stippled); however, that dose would be on the order of 1e13 ions/cm2to 1e15 ions/cm2. Referring toFIGS.4A and4B, once the ions41are in place and the photolithographically defined mask30is removed, semiconductor processing is completed with the ion charge un-annealed and remaining in place to distribute the electric field in the gate to drain region. It should be noted that the electric field produced by the field plate structure41is provided solely by the electric ions41in the dielectric layer24. It should also be noted that the process described above with regard to the ion implantation is not semiconductor doping, but rather charge implantation with the resulting implanted charge41creating an implanted dielectric field plate. When operating bias is applied to the resulting semiconductor device, the peak electric field at the drain side of the gate electrode is smaller than it would be if the device had been fabricated without the implanted ions. In this regard, the device is now capable of operating at higher voltages without its peak electric field exceeding an excessive or critical value. Referring now toFIG.5, the Field Effect Transistor40structure shown inFIGS.4A and4Bhas a ground plane conductor42formed on the bottom of the substrate12. The source electrode18is connected to a ground plane conductor42through a conductive via44. The drain electrode20is connected to a positive voltage source +V through a resistor R and gate electrode22is connected to an RF input signal, as shown, to form a common source amplifier48. It is noted that here, the ion-implanted region extends over a portion of the gate electrode22towards the drain electrode20; it being noted that the ion-implanted region does not extend all the way to the drain electrode20. It is noted that there is no annealing performed to neutralize the charge of the ions in the dielectric so that they remain charged in a floating configuration in the dielectric. It is noted that the ion implanted region is localized only in a region between the gate and drain in this common source transistor example, to eliminate source electrode side capacitance increase. EXAMPLES Single Dielectric StructureFIG.4B: Dielectric layer24thickness: 60 to 150 nmCharge is implanted with a Gaussian-like distribution to a maximum depth: 30 to 50 nm in layer24The implanted charge peak depth: 5 to 20 nm into the upper surface of layer24 Double Dielectric StructureFIG.4B′:Dielectric layer24′ thickness: 45 to 150 nmDielectric layer24would be thinner than layer24′ in the double dielectric configuration for device reasons other than the implanted field plate, such as device passivationCharge is implanted with a Gaussian-like distribution layer to a maximum depth: 30 to 50 nm in layer24′The implanted charge peak depth: 5 to 20 nm into the upper surface of layer24′ A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims. | 7,719 |
11862692 | DETAILED DESCRIPTION The embodiments described herein provide a power semiconductor device having semiconductor mesa and field plate contacts that are interrupted along the length of the gate trenches. By interrupting the semiconductor mesa and field plate contacts along the length of the gate trenches, movement of the insulating layer which surrounds the contact layer is reduced during wire bonding. Less movement by the insulating layer which underlies the final (power) metallization reduces the likelihood of cracks forming in the final metallization layer during the wire bonding process. With fewer cracks in the final metallization layer, contaminants introduced by a treatment for improving mold compound adhesion are less likely to diffuse beyond the final metallization layer. In the case of a power transistor device, the source (emitter) implantation also may be interrupted or omitted in areas without a mesa contact, to avoid latch up during avalanche. Described next is an embodiment of the power semiconductor device. FIG.1illustrates a plan view of a power semiconductor device100.FIG.2illustrates a plan view of the region of the power transistor device100included in the dashed box102inFIG.1, with the final (power) metallization layer being hidden from view so that the underlying filed plate and semiconductor mesa contact structure is visible.FIGS.3through7illustrate cross-sectional views taken along the lines labelled A-A′ through E-E′ inFIG.2, respectively. The power semiconductor device100is explained in the context of a power MOSFET (metal-oxide-semiconductor field-effect transistor) in that reference is made to source, body and drain regions. However, the power semiconductor device100may instead be an IGBT (insulated gate bipolar transistor) or other type of power transistor device. Accordingly, details relating to the type of device are discussed only briefly. Emphasis instead is placed on a contact structure which increases the mechanical stability of the insulating layer just below the final (top) metallization layer of the device. The power semiconductor device100includes a semiconductor substrate104. The semiconductor substrate104may comprise any type of semiconductor material suitable for power devices such as power transistors and power diodes. For example, the semiconductor substrate104may comprise Si, SiC, GaN, etc. The semiconductor substrate104may include a base semiconductor and one or more epitaxial layers grown on the base semiconductor. The power semiconductor device100also includes trenches106formed in the semiconductor substrate104, e.g., by etching. The trenches106extend lengthwise in parallel with one another in a direction (x-direction inFIGS.1and2) that is parallel to a main surface108of the semiconductor substrate104in which the trenches106are formed, such that each pair of adjacent trenches106confines a semiconductor mesa110. Directions ‘x’ and ‘y’ inFIGS.1and2are lateral (horizontal) directions which run perpendicular to one another and parallel to the main surface108of the semiconductor substrate104, whereas direction ‘z’ inFIGS.3through7is a vertical direction which runs perpendicular to the main surface108of the semiconductor substrate104. A field electrode112and one or more gate electrodes114are disposed in each of the trenches106. Each gate electrode114is insulated from the surrounding semiconductor material by a gate dielectric116. Each field electrode112is insulated from the gate electrode(s) in the same trench106and from the surrounding semiconductor material by a field dielectric118which may be of the same material as the gate dielectric116or a different insulative material. The field electrodes112may be biased at source potential, another potential, or floating. A final (power) metallization layer120is formed above the semiconductor substrate104. A passivation layer122such as silicon nitride may be formed on the final metallization layer120. The passivation layer122may comprise silicon nitride and/or imide and/or silicon oxide. The final metallization layer120, which may be a Cu layer, Al layer, AlCu, layer, etc., is segmented into a plurality of contact pads124. The segmented final metallization layer120is covered by the passivation layer122and therefore illustrated as dashed rectangles inFIG.1. The contact pads124are defined by openings125in the passivation layer122. A gate pad127also may be defined by one of the openings125in the passivation layer122. The contact pads124may extend lengthwise in parallel with one another in the same direction (x-direction inFIGS.1and2) as the trenches106, e.g., as shown inFIG.1. The contact pads124may instead extend lengthwise in parallel with one another in a direction transverse to the trenches106, e.g., as shown inFIG.1. Still other contact pad configurations are possible. In the case of a power transistor device as shown inFIGS.1through7, the contact pads124provide a power (e.g. source or emitter) terminal connection to the power semiconductor device100. Electrical conductors (not shown) such as bond wires, metal ribbons, a metal clip, etc. are attached to the contact pads124to provide external electrical connection to the power semiconductor device100. The final metallization layer120of the power semiconductor device100is disposed on an insulating layer126that comprises an electrically insulative material such as BPSG. The power semiconductor device100may include more than one metallization layer with an interlayer dielectric separating the metallization layers, with the metallization layer120shown inFIGS.1through7being the uppermost one. Field plate contacts128extend lengthwise in parallel with one another in the same direction (x-direction inFIGS.1and2) as the trenches106, e.g., as shown inFIG.2. The field plate contacts128also extend in the vertical direction (z-direction inFIGS.3through7) and electrically connect the overlying contact pads124of the final metallization layer120to the underlying field electrodes112disposed in the trenches106. The field plate contacts128are each divided along the length of the trenches106into a plurality of field plate contact segments128′ that are separated from one another. Mesa contacts130which form part of the same vertical interconnect layer that includes the field plate contacts128extend lengthwise in parallel with one another in the same direction (x-direction inFIGS.1and2) as the trenches106, e.g., as shown inFIG.2. The mesa contacts130also extend in the vertical direction (z-direction inFIGS.3through7) and electrically connect the overlying contact pads124of the final metallization layer120to the underlying semiconductor mesas110. The mesa contacts130are each divided along the length of the trenches106into a plurality of mesa contact segments130′ that are separated from one another. In one embodiment, the field plate contacts128and the mesa contacts130comprise polysilicon. In another embodiment, the field plate contacts128and the mesa contacts130comprise one or more metals or metal alloys. In one embodiment, the field plate contact segments128′ of the same field plate contact128are separated from one another by first bridging regions126′ of the uppermost insulating layer126and the mesa contact segments130′ of the same mesa contact130are separated from one another by second bridging regions126″ of the uppermost insulating layer126. The first bridging regions126′ of the uppermost insulating layer126(between adjacent field plate contact segments128′ of the same field plate contact128) are wider than the second bridging regions126″ of the uppermost insulating layer126(between adjacent mesa contact segments130′ of the same mesa contact130). Accordingly, the field plate contact segments128′ of the same field plate contact128are separated from one another by a first distance d1measured along the length (x-direction inFIGS.1and2) of the trenches106. The mesa contact segments130′ of the same mesa contact130are separated from one another by a second distance d2which is measured in the same direction as the first distance d1and smaller than d1. According to one embodiment of segmenting the field plate contacts128and the mesa contacts130, the uppermost insulating layer126(e.g. BPSG) is deposited over the main surface108of the semiconductor substrate104after formation of the trenches106and device regions in the semiconductor mesas110confined by the trenches106. A lithography mask (not shown) is then formed on the uppermost insulating layer126. The lithography mask defines locations of each field plate contact128and each mesa contact130and also locations where each contact128,130is to be etched and thus divided into multiple spaced-apart segments128′,130′ along the length of the trenches106. The uppermost insulating layer126is then patterned, e.g., by etching using the lithography mask to define the locations of the field plate contacts128and the mesa contacts130(where the uppermost insulating layer126has been removed), and also the locations of the bridging regions126′,126″ of the uppermost insulating layer126where the uppermost insulating layer126has not been etched. An electrically conductive material such as polysilicon or a metal/metal alloy is deposited on the patterned uppermost insulating layer126and then etched or planarized to form the segmented field plate contacts128and the segmented mesa contacts130. For example, a Ti/TiN/W layer stack may be deposited and then etched or planarized to form the segmented field plate contacts128and the segmented mesa contacts130. As shown inFIG.2, the first bridging regions126′ of the uppermost insulating layer126separate adjacent field plate contact segments128′ of the same field plate contact128along the length (x-direction inFIGS.1and2) of the trenches106and the second bridging regions126″ of the uppermost insulating layer126separate adjacent mesa contact segments130′ of the same mesa contact130along the length of the trenches106. As shown inFIGS.2and7, the insulative bridging regions126′,126″ also interconnect the uppermost insulating layer126between adjacent ones of the contacts128,130at several locations along the length of the trenches106. In one embodiment, the field plate contacts128are each divided along the length of the trenches106into at least 10 field plate contact segments128′ that are separated from one another by first bridging regions126′ of the uppermost insulating layer126and the mesa contacts130are each similarly divided along the length of the trenches106into at least 10 mesa contact segments130′ that are separated from one another by second bridging regions126″ of the uppermost insulating layer126. The field plate contacts128may be divided into the field plate contact segments128′ at the same locations (aligned in y-direction inFIGS.1and2) along the length (x-direction inFIGS.1and2) of the trenches106. In a similar manner, the mesa contacts130may be divided into the mesa contact segments130′ at the same locations (aligned in y-direction inFIGS.1and2) along the length (x-direction inFIGS.1and2) of the trenches106. As shown inFIG.2, the field plate contacts128and the mesa contacts130may be divided at the same locations (aligned in y-direction inFIGS.1and2) along the length (x-direction inFIGS.1and2) of the trenches106, although the width of separation for the different types of contact segments128′,130′ may be different (d1versus d2) as previously explained herein. In another embodiment, the field plate contacts128are divided into the field plate contact segments128′ at first locations along the length of the trenches106and the mesa contacts130are divided into the mesa contact segments130′ at second locations along the length of the trenches106, wherein the first locations are different than the second locations. That is, the first and second locations may not be aligned in the y-direction inFIGS.1and2. In a first area132adjacent to an end134of the trenches106, a first line (e.g. corresponding to cross-section line A-A′ inFIG.2) that runs perpendicular to the trenches106intersects the field plate contact segment128′ of each field plate contact128and the mesa contact segment130′ of each mesa contact130disposed closest to the end134of the trenches106. In a second area136spaced inward from the first area132, a second line (e.g. corresponding to cross-section line B-B′ inFIG.2) that runs perpendicular to the trenches106intersects a field plate contact segment128′ of each field plate contact128and a mesa contact segment130′ of each mesa contact130. The semiconductor mesas110confined by the trenches106include a source region138of a first conductivity type in the second area136. The semiconductor mesas110may be devoid of the source region138in the first area132. The mesa contact segments130′ located in the second area136contact the source region138of the semiconductor mesas138. The mesa contact segments130′ located in the first area132extend from the first area132into the second area136and contact the source region138of the semiconductor mesas110in the second area136but not in the first area132. In one embodiment, the source region138of the semiconductor mesas110has gaps140in the second area136that are filled with semiconductor material142of a second conductivity type, e.g., a body region of the power transistor device100. That is, the source region138may be interrupted or omitted in areas without a mesa contact130, to avoid latch up during avalanche. For each mesa contact130divided into two or more mesa contact segments130′ over the length of the mesa contact130, the gaps140in the source region130may be realized by blocking the implantation of a dopant used to form the source region138from a region of the semiconductor mesa110vertically aligned with a gap (represented by distance d2inFIG.2) between the mesa contact segments130′ of each mesa contact130. The gaps140in the source region130may be realized by appropriate patterning of a lithography mask (not show) used during the source implantation, i.e., the source implantation is blocked by corresponding intact/blocking regions of the lithography mask. The gaps140in the source region138may slightly increase the on resistance (RON) of the power transistor device100. However, if the distance d2between the mesa contact segments130′ is smaller than the distance d1between the field plate contact segments128′, no RON disadvantage is expected. With the interruption of the contacts128,130, mechanical stability is increased. The separation between the mesa contact segments130′ of the mesa contacts130may be vertically aligned with the gaps140in the source region138of the semiconductor mesas110, e.g., as shown inFIGS.2and7. The outline of the source region138is illustrated by as a single large dashed rectangle inFIG.2since the source region138would otherwise not be visible in this plan view. The gaps140in the source region138are similarly illustrated by smaller dashed rectangles inFIG.2. As shown inFIGS.3through7, the trenches106extend depth-wise in a second direction (z-direction inFIGS.3through7) perpendicular to the main surface108of the semiconductor substrate104and into a drift region144of the first conductivity type. The body region142of the second conductivity type separates the source region138from the drift region144. A drain region146of the first conductivity type is disposed below the drift region144at the opposite side of the semiconductor substrate104as the source region138. The first conductivity type is n-type and the second conductivity type is p-type in the case of an n-channel device. In the case of a p-channel device, the first conductivity type is p-type and the second conductivity type is n-type. As previously explained herein, the source region138may be omitted from the semiconductor mesas110in the first area132of the power semiconductor device100such that the mesa contact segments130′ closest to the corresponding end134of the trenches106extend from the first area132of the device100into the second area136. A first part130a′ of the mesa contact segments130′ closest to the end134of the trenches106contact the body region142but not the source region138in the first area132of the power semiconductor device100. A second part130b′ of the mesa contact segments130′ closest to the end134of the trenches106contact both the body region142and the source region138in the second area136of the power semiconductor device100. In one embodiment, an aspect ratio of the field plate contacts128is in a range between 5 and 30, wherein the aspect ratio being defined as a ratio of contact height to a bottom width of the field plate contacts128. With such a high aspect ratio for the field plate contacts128, and since the contacts128,130extend over the length of the trenches106, the forces on the uppermost insulating layer126would be very high during wire bonding unless the field plate contacts128and the mesa contacts130are divided into multiple spaced-apart segments128′,130′ along the length of the trenches106, as described herein. The segmented contact array structure described herein increases the mechanical stability of the insulating layer126below the final (top) metallization layer120which includes the contact pads124. By making the uppermost insulating layer126more stable, the final metallization layer120is also stabilized. The interruption length may vary as well as the interruption of the source implantation. Also, the location of the interruption of the contacts128,130relative to each other may also vary. In one embodiment, only the field plate contacts128are interrupted. According to this embodiment, no RON disadvantage is expected but the improvement of the mechanical stability is less. Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure. Example 1. A transistor device, comprising: a semiconductor substrate having a first surface; a plurality of trenches in the semiconductor substrate and extending lengthwise in parallel with one another in a first direction parallel to the first surface such that each pair of adjacent trenches confines a semiconductor mesa; a field electrode and a gate electrode disposed in each of the trenches; a final metallization layer above the semiconductor substrate and segmented into a plurality of contact pads; a plurality of field plate contacts extending lengthwise in parallel with one another in the first direction and electrically connecting the contact pads to the field electrodes; and a plurality of mesa contacts extending lengthwise in parallel with one another in the first direction and electrically connecting the contact pads to the semiconductor mesas, wherein the field plate contacts are each divided along the length of the trenches into a plurality of field plate contact segments that are separated from one another, wherein the mesa contacts are each divided along the length of the trenches into a plurality of mesa contact segments that are separated from one another, wherein in a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts, wherein in a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts. Example 2. The transistor device of example 1, wherein the semiconductor mesas include a source region of a first conductivity type in the second area and are devoid of the source region in the first area, and wherein the second mesa contact segments contact the source region of the semiconductor mesas in the second area. Example 3. The transistor device of example 2, wherein the first mesa contact segments extend from the first area into the second area, and wherein the first mesa contact segments contact the source region of the semiconductor mesas in the second area but not in the first area. Example 4. The transistor device of example 2 or 3, wherein the source region of the semiconductor mesas has gaps in the second area that are filled with semiconductor material of a second conductivity type, and wherein the separation between the mesa contact segments of the mesa contacts are vertically aligned with the gaps in the source region of the semiconductor mesas. Example 5. The transistor device of any of examples 1 through 4, wherein the field plate contacts are each divided along the length of the trenches into at least 10 field plate contact segments that are separated from one another, and wherein the mesa contacts are each divided along the length of the trenches into at least 10 mesa contact segments that are separated from one another. Example 6. The transistor device of any of examples 1 through 5, wherein the field plate contacts are divided into the field plate contact segments at the same locations along the length of the trenches. Example 7. The transistor device of any of examples 1 through 6, wherein the mesa contacts are divided into the mesa contact segments at the same locations along the length of the trenches. Example 8. The transistor device of any of examples 1 through 7, wherein the field plate contacts are divided into the field plate contact segments at first locations along the length of the trenches, wherein the mesa contacts are divided into the mesa contact segments at second locations along the length of the trenches, and wherein the first locations are different than the second locations. Example 9. The transistor device of any of examples 1 through 8, wherein the plurality of trenches extends depth-wise in a second direction perpendicular to the first surface into a drift region of a first conductivity type, wherein each semiconductor mesa includes a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift region, and wherein the mesa contacts are in contact with the source regions. Example 10. The transistor device of example 9, wherein the source region is omitted from the semiconductor mesas in the first area, wherein the mesa contact segments closest to the end of the trenches extend from the first area into the second area, and wherein a first part of the mesa contact segments closest to the end of the trenches contact the body region but not the source region in the first area and a second part of the mesa contact segments closest to the end of the trenches contact both the body region and the source region in the second area. Example 11. The transistor device of any of examples 1 through 10, wherein the field plate contact segments of the same field plate contact are separated from one another by first regions of an electrically insulative material, wherein the mesa contact segments of the same mesa contact are separated from one another by second regions of the electrically insulative material, and wherein the first regions of the electrically insulative material are wider than the second regions of the electrically insulative material. Example 12. The transistor device of any of examples 1 through 11, wherein the field plate contact segments of the same field plate contact are separated from one another by a first distance, and wherein the mesa contact segments of the same mesa contact are separated from one another by a second distance smaller than the first distance. Example 13. The transistor device of any of examples 1 through 12, wherein an aspect ratio of the field plate contacts is in a range between 5 and 30, and wherein the aspect ratio is defined as a ratio of contact height to a bottom width of the field plate contacts. Example 14. A method of producing a transistor device, the method comprising: forming a plurality of trenches in a semiconductor substrate and extending lengthwise in parallel with one another in a first direction parallel to a first surface of the semiconductor substrate such that each pair of adjacent trenches confines a semiconductor mesa; forming a field electrode and a gate electrode in each of the trenches; forming a final metallization layer above the semiconductor substrate and segmented into a plurality of contact pads; forming a plurality of field plate contacts that extend lengthwise in parallel with one another in the first direction and electrically connect the contact pads to the field electrodes; and forming a plurality of mesa contacts that extend lengthwise in parallel with one another in the first direction and electrically connect the contact pads to the semiconductor mesas, wherein forming the plurality of field plate contacts comprises dividing each field plate contact along the length of the trenches into a plurality of field plate contact segments that are separated from one another, wherein forming the plurality of mesa contacts comprises dividing each mesa contact along the length of the trenches into a plurality of mesa contact segments that are separated from one another, wherein in a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts, wherein in a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts. Example 15. The method of example 14, wherein the semiconductor mesas include a source region of a first conductivity type in the second area and are devoid of the source region in the first area, and wherein the second mesa contact segments contact the source region of the semiconductor mesas in the second area. Example 16. The method of example 15, wherein the first mesa contact segments extend from the first area into the second area, and wherein the first mesa contact segments contact the source region of the semiconductor mesas in the second area but not in the first area. Example 17. The method of example 15 or 16, wherein the source region of the semiconductor mesas has gaps in the second area that are filled with semiconductor material of a second conductivity type, the method further comprising: vertically aligning the separation between the mesa contact segments of the mesa contacts with the gaps in the source region of the semiconductor mesas. Example 18. The method of any of examples 14 through 17, wherein the plurality of trenches extends depth-wise in a second direction perpendicular to the first surface into a drift region of a first conductivity type, the method further comprising: forming a source region of the first conductivity type and a body region of a second conductivity type in each semiconductor mesa, the body region separating the source region from the drift region, the mesa contacts being in contact with the source regions; omitting the source region from the semiconductor mesas in the first area; and for the mesa contact segments closest to the end of the trenches and extending from the first area into the second area, contacting a first part of the mesa contact segments to the body region but not the source region in the first area and contacting a second part of the mesa contact segments to both the body region and the source region in the second area. Example 19. The method of any of examples 14 through 18, further comprising: separating the field plate contact segments of the same field plate contact from one another by first regions of an electrically insulative material; and separating the mesa contact segments of the same mesa contact from one another by second regions of the electrically insulative material, wherein the first regions of the electrically insulative material are wider than the second regions of the electrically insulative material. Example 20. The method of any of examples 14 through 19, further comprising: separating the field plate contact segments of the same field plate contact from one another by a first distance; and separating the mesa contact segments of the same mesa contact from one another by a second distance smaller than the first distance. Example 21. A transistor device, comprising: a semiconductor substrate having a first surface; a plurality of trenches in the semiconductor substrate and extending lengthwise in parallel with one another in a first direction parallel to the first surface such that each pair of adjacent trenches confines a semiconductor mesa; a field electrode and a gate electrode disposed in each of the trenches; a final metallization layer above the semiconductor substrate and segmented into a plurality of contact pads; a plurality of field plate contacts extending lengthwise in parallel with one another in the first direction and electrically connecting the contact pads to the field electrodes; and a plurality of mesa contacts extending lengthwise in parallel with one another in the first direction and electrically connecting the contact pads to the semiconductor mesas, wherein the field plate contacts are each divided along the length of the trenches into a plurality of field plate contact segments that are separated from one another, wherein in a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts, wherein in a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts. Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description. As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof. | 31,185 |
11862693 | DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the embodiments may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed. As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements. As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.” Embodiments of the present disclosure generally relate to semiconductor devices or integrated circuits (ICs). More particularly, some embodiments relate to transistor devices having a high switching performance. The transistor devices may be metal oxide semiconductor field effect transistors, such as EDMOS (extended drain metal oxide semiconductor) transistors. Other suitable transistor devices may also be useful. Such devices may be incorporated into or used with, for example, RF switches and power amplifiers. FIG.1Ashows a cross-sectional view of an embodiment of a semiconductor device100. The device, for example, may be an IC. Other types of devices may also be useful. As shown, the device includes a substrate105. The substrate105may be a semiconductor substrate, such as a silicon substrate. Other types of substrates, such as silicon germanium, germanium, gallium arsenide, or crystal-on-insulator (COI) such as silicon-on-insulator (SOI), may also be used. The substrate105may include a device well107. The device well107, for example, may be a high voltage (HV) device well. The device well107may be provided for devices operating in high voltage ranges, for example, at a voltage ranging of about 5V to about 20V. Other suitable voltage values may also be useful. A drain region113and a source region115may be disposed in the substrate105. The drain region may be an extended drain region. The drain region113and the source region115may be doped with first polarity type dopants for a first polarity type transistor. For example, the first polarity type dopants may be p-type dopants for a PMOS. Alternatively, the first polarity type dopants may be n-type dopants for an NMOS. In a non-limiting example, p-type dopants may include boron (B), aluminum (Al), indium (In) or a combination thereof, while n-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. The drain region113and the source region115may be heavily doped regions. A (first) gate122may be arranged over the substrate. The gate122may be arranged between the drain region113and the source region115. The gate122may include a first sidewall122aand a second sidewall122b. The gate122may include a gate electrode over a gate dielectric. The gate dielectric may be formed of an oxide layer, such as silicon oxide while the gate electrode may be formed of polysilicon, in a non-limiting example. Providing other types of material for the gate electrode and the gate dielectric may also be useful. The gate122may further include gate spacers on sidewalls of the gate electrode (not shown). The gate spacers may be dielectric spacers, such as silicon oxide spacers, in a non-limiting example. Other suitable types of dielectric materials may also be useful, such as silicon nitride or a combination of dielectric materials or layers. According to various embodiments, the drain region113may be arranged spaced apart from the first sidewall122aof the gate. The source region115may be disposed adjacent to the second sidewall122bof the gate. In some embodiments, a silicide block layer1601may be arranged over the substrate between the gate122and the drain region113. For example, the silicide block layer1601may extend from the first sidewall122aof the gate122to the drain region113. In some embodiments, the silicide block layer1601may extend over at least a portion of the gate122. A body well1401may be disposed in the substrate105. The body well1401may be disposed adjacent to the second sidewall122bof the gate122and extends at least partially under a first portion of the gate122. For example, the body well1401may extend beyond the source region115and may underlap a first side of the gate122. As shown, the body well1401may surround the source region115. For example, the body well1401may be lightly or intermediately doped with second polarity dopants for a first polarity type transistor. The second polarity type is different or opposite to the first polarity type. For example, in the case the first polarity type dopants are n-type dopants, the second polarity type dopants are p-type dopants. Alternatively, in the case the first polarity type dopants are p-type dopants, the second polarity type dopants are n-type dopants. For example, the body well1401comprises p-type dopants for an n-type transistor or n-type dopants for a p-type transistor. A well tap145may be disposed within the body well1401in the substrate and in communication with the body well1401. The body well1401may surround the well tap145. The well tap145may serve to bias the body well1401. The well tap145may be disposed adjacent to the source region115. In some embodiments, the well tap145may abut the source region115. In other embodiments, the well tap145may be spaced apart from the source region115. The well tap145may have the same polarity type as the body well1401. For example, the well tap145may be doped with second polarity type dopants for a first polarity type transistor. For example, the well tap145be doped with p-type dopants for an n-type transistor. Alternatively, the well tap145may be doped with n-type dopants for a p-type transistor. In a non-limiting embodiment, the well tap145may be a heavily doped region, similar to the source and drain regions. According to various embodiments, the substrate105may further include a second source region117. A second gate124may be further arranged over the substrate between the second source region117and the drain region113. The drain region113may be common to the gate122and the second gate124. The second source region117, for example, may be heavily doped with first polarity type dopants. The second gate124may include a first sidewall124aand a second sidewall124b. Similar to the gate122, the second gate124may include a gate electrode over a gate dielectric, and gate spacers on sidewalls of the gate electrode (not shown). The drain region113may be arranged spaced apart from the first sidewall124aof the gate. The second source region117may be disposed adjacent to the second sidewall124bof the gate. In some embodiments, a silicide block layer1602may be arranged over the substrate between the second gate124and the drain region113. For example, the silicide block layer1602may extend from the first sidewall124aof the gate124to the drain region113. In some embodiments, the silicide block layer1602may extend over at least a portion of the second gate124. Similarly, a second body well1402may be disposed adjacent to the second sidewall124bof the second gate124and extends at least partially under a first portion of the second gate124. For example, the second body well1402may extend beyond the second source region117and may underlap a first side of the second gate124. As shown, the second body well1402may surround the second source region117. A second well tap147may be disposed within the second body well1402in the substrate. The second body well1402may surround the second well tap147. The second well tap147may be disposed adjacent to the second source region117. For example, the second well tap147may be heavily doped with second polarity type dopants. In some embodiments, metal silicide contacts may be provided over the gate electrode, source regions, drain region, and well tap (not shown). The silicide contacts, for example, may be or include, but are not limited to a nickel-based silicide, a cobalt silicide (CoSi), and combinations thereof. Other suitable types of metal silicide contacts may also be useful. The silicide contacts may be employed to reduce contact resistance and facilitate contact to back-end-of-line (BEOL) interconnects. A drift well or region150may be disposed in the substrate105. The drift well150may surround the drain region113and extends at least partially under a second portion of the gate122(and the second gate124). The depth or bottom of the drift well150may be deeper than the body well1401and the second body well1402from the substrate surface. The depth, for example, may depend on the design voltage of the device. The substrate portion under the gate122disposed between the source region115and drift well150may form a channel region. Similarly, the substrate portion under the second gate124disposed between the second source region117and drift well150may form a channel region. The drift well150may include first polarity type dopants for a first polarity type transistor. For example, the drift well150may include n-type dopants for an n-type transistor or p-type dopants for a p-type transistor. The dopant concentration of the drift well150may be lower than the dopant concentration of the drain region113. For example, the drift well150may be lightly doped. For example, the dopant concentration of the drift well150may depend on device requirement such as breakdown voltage and/or RONperformance. According to various embodiments, the inner edge of the body well140(body well1401and the second body well1402) under the gate122and the second gate124may be contiguous with the edge of the drift well150. Other configurations of the body well140and the drift well150may also be useful. In some embodiments, the device well107may surround or may encompass the body well140, the drift well150, source region115, second source region117and drain region113. The depth or bottom of the device well107may be below the body well140and the drift well150. For example, the device well107may include second polarity type dopants for a first polarity type device. For example, the device well107may include p-type dopants for an n-type transistor. Alternatively, the device well107may include n-type dopants for a p-type transistor. The device well107may be lightly doped. An interlevel dielectric (ILD) may be arranged over the substrate105. The ILD may include ILD layers comprising interconnects. As illustrated inFIG.1A, a first ILD layer160may be arranged over the substrate105. The dielectric layer may be formed in a BEOL processing in a non-limiting example. The first ILD layer160may be formed of a dielectric material, such as silicon oxide in a non-limiting example. Other suitable types of dielectric materials are also useful. An etch stop layer161, such as silicon nitride, may be arranged between the substrate105and the first ILD layer160. The first ILD layer160may include at least one drain contact162coupled to drain region113, and body contacts164and166coupled to the well tap145and second well tap147, respectively. The at least one drain contact162may extend through the first ILD layer160over the drain region113and may be coupled to a conductive field plate177. The body contacts164and166may extend through the first ILD layer160over the well tap145and second well tap147, respectively, and may be coupled to the conductive field plate177. In other embodiments, the first ILD layer160may further include source contacts coupled to the source region115and the second source region117(not shown). The body contacts and the source contacts may have the same or different biasing. In the case where the body contacts and the source contacts are biased differently, the source region115and the well tap145may be separated by an isolation region, similarly the second source region117and the second well tap147may be separated by a further isolation region. For example, the drain contact162and body contacts164and166(and source contacts) may be formed of a conductive material such as copper (Cu), aluminum (Al), etc. Other suitable types of conductive material may also be useful. As illustrated, the conductive field plate177may be arranged over the first ILD layer160. The conductive field plate177may include a plate opening179. The conductive field plate177may have a first plate portion177aand a second plate portion177b. The first plate portion177aand the second plate portion177bmay be separated by the plate opening179. The plate opening179may provide a relatively small spacing between the first plate portion177aand the second plate portion177b. The plate opening179may have a width w ranging from about 150 nm to about 200 nm, in a non-limiting example. According to various embodiments, a drain captive structure180may be disposed in the first ILD layer160and adjacent to the drain region113. The drain captive structure180may have a trench182comprising or consisting of an air gap183in the first ILD layer160. The drain region113may partially underlap the drain captive structure180. As shown inFIG.1A, the drain captive structure180may be laterally spaced apart from sidewalls122aand122bof the gate122. For example, the drain captive structure180may be displaced from the first sidewall122aof the gate122by a predetermined distance. Similarly, the drain captive structure180may be laterally spaced apart from sidewalls124aand124bof the second gate124. For example, the drain captive structure180may be displaced from the first sidewall124aof the second gate124by a predetermined distance. According to various embodiments, the air gap183of the drain captive structure180may be configured to surround the drain contact162. The drain captive structure180may include a first ring-type barrier184and a second ring-type barrier186which defines the trench182. The first ring-type barrier184and the second ring-type barrier186may each surround the drain contact162. The first ring-type barrier184may be separated from the drain contact by dielectric material. For example, each of the first ring-type barrier184and the second ring-type barrier186may be a rectangular shaped ring barrier. However, it is understood that other shapes such circular, or a polygon may also be used. Each of the first ring-type barrier184and the second ring-type barrier186may be continuous and may have a closed configuration (e.g., a closed loop). The first ring-type barrier184and the second ring-type barrier186may serve as a dummy or shield to prevent portions of dielectric material of the first ILD layer160from being etched during formation of the air gap in the first ILD layer160. According to various embodiments, the first ring-type barrier184and the second ring-type barrier186and the drain contact162(and the body contacts164and166) may be formed of a same conductive material. In some embodiments, the conductive field plate177may also be formed of the same conductive material as the first ring-type barrier184and the second ring-type barrier186and the drain contact162. The conductive material, for example, may be a metal such as Cu or Al. In other embodiments, the conductive field plate177, the first ring-type barrier184, the second ring-type barrier186and the drain contact162may be formed of different materials. FIG.1Billustrates a top view of an embodiment of the semiconductor device100ofFIG.1A. The well tap, source region, drain region, drift well, second source region and second well tap may be formed within an active region190in the substrate. For purpose of illustration, the conductive field plate177is depicted with a solid line, while the plate opening179in the conductive field plate177is depicted with dashed lines. The plate opening179may be relatively small and having a width sufficient to enable dielectric material in the trench of the drain captive structure to be removed. According to various embodiments, the conductive field plate177may extend to substantially cover the active area195of the device. The conductive field plate177may be an extended field plate. For example, the conductive field plate177may extend from the source side to the drain side of the device. The first plate portion177amay cover a top surface of body contacts164and166and the second ring-type barrier186. The second plate portion177bmay cover a top surface of the drain contact162and the first ring-type barrier184. Providing the extended field plate increases the breakdown voltage of the device without increasing the on-state resistance. For example, providing the field plate which extend from the source region (and second source region) to the drain region helps to increase the breakdown voltage of a transistor by depleting the charge carriers in the drift region and reducing the surface electric field of the transistor. Referring toFIG.1C, a second ILD layer192may be arranged over the first ILD layer160. As illustrated, the second ILD layer192may be arranged over the conductive field plate177. The second ILD layer192may be formed of a dielectric material, such as oxide, nitride, or combinations thereof. Other suitable types of dielectric materials are also useful. According to various embodiments, the plate opening179of the conductive field plate177pinches off dielectric material of the second ILD layer192to seal the air gap of the drain captive structure180. For example, the plate opening179may have a relatively small width, ranging from about 150 nm to about 200 nm, in a non-limiting example, such that dielectric material of the second ILD layer192deposited over the conductive field plate177does not extend beyond the plate opening179. As shown, a sealed off or pinched off dielectric portion197is formed in the plate opening179. The sealed off dielectric portion197partially fills the plate opening179to seal the air gap183, and does not extend beyond the plate opening179. The sealed off dielectric portion197may be formed by depositing dielectric material of the second ILD layer192using a high density plasma (HDP) process. For example, the second ILD layer192may be formed over the conductive field plate177using a HDP chemical vapor deposition (CVD) process. In the case the second ILD layer192is formed of a combination of nitride and oxide, the second ILD layer192may be formed by deposition of nitride (e.g., plasma enhanced CVD with high pressure), followed by deposition of oxide using the HDP process. Deposition of dielectric material using HDP process (e.g., deposition of the oxide) seals the plate opening179while forming an air gap or void183in the trench182and in the space of the plate opening179under the sealed off dielectric portion197. During deposition of the dielectric material (e.g., oxide) of the second ILD layer192using the HDP process, the air gap183may be formed based on a deposition to sputtering (D/S) ratio of the HDP process, width of the plate opening179(e.g., critical dimension of the spacing of the conductive field plate177), and thickness of the conductive field plate177. The D/S ratio of the HDP process, width of the plate opening179, and thickness of the conductive field plate177may be chosen such that the dielectric material of the second ILD layer192does not enter into the trench182of first dielectric layer160during deposition, forming the air gap183in the trench182and in the space of the plate opening179under the sealed off dielectric portion197. In other words, the dielectric material of the second ILD layer192does not “fall” into the trench182of first dielectric layer160based on the process condition for the deposition, i.e., the HDP process for the deposition with a higher D/S ratio, a small width of the plate opening179and thickness of the conductive field plate177. The deposition of the dielectric material of the second ILD layer192using the HDP process may be performed with a relatively higher D/S ratio to ensure the air gap183is formed in the trench182, and the dielectric material of the second ILD layer192does not “fall” into the trench182during the deposition. The D/S ratio of the HDP process may depend on the width of the plate opening179(e.g., critical dimension of the spacing of the conductive field plate177), and thickness of the conductive field plate177. In a non-limiting example, in the case the conductive field plate177has a thickness of about Sum, the D/S ratio of the HDP process for the deposition of the dielectric material of the second ILD layer192may be about 4 or greater. In cases where the dielectric material of the second ILD layer192does fall into the trench182during deposition over the plate opening179, it is of a small amount and may be left in the trench182as the air gap183is formed in the trench182.FIG.1Dshows an exemplary SEM image of the device100having the air gap183in the drain captive structure180. According to various embodiments, an etch back process may be performed after the deposition of the oxide over the conductive field plate177. The deposition of oxide using HDP process and the etch back may be performed alternately over the conductive field plate177having the small or narrow plate opening179. When the duration of deposition (deposition time) is increased and the duration of etch (etch time) is reduced, the dielectric material (oxide) of the second ILD layer192does not fill the trench182, and the air gap183may be formed in the trench182and in the plate opening179under the sealed off dielectric portion197. In other words, the air gap183may be formed by controlling the deposition and etching in the geometrically narrow plate opening179of the conductive field plate177. The second ILD layer192may further include via contacts and conductive lines which interconnect to the conductive field plate177. According to various embodiments, the drain captive structure having the trench filled with air to form the air gap in the first ILD layer (or ILD) may lower or reduce the gate-drain capacitance Cgdand gate charge Qg. Providing the transistor devices with low gate-drain capacitance improves the switching speed of the transistor devices. Further, a low gate charge may be required to operate the transistor device. Additionally, providing the conductive field plate increases the breakdown voltage of the device without increasing the on-state resistance. Accordingly, the transistor device according to various embodiments may advantageously have a high breakdown voltage, low forward voltage drop, and fast switching speed. FIGS.2A-2Dshow cross-sectional views of an embodiment of a process200for forming a semiconductor device. The device, for example, is similar to that described inFIGS.1A-1C. As such, common elements may not be described or described in detail. Referring toFIG.2A, a substrate105is provided. The substrate105may be a semiconductor substrate, such as a silicon substrate in a non-limiting embodiment. The substrate may be at least partially processed. The substrate, as shown, is at the stage of processing where at least a portion of an ILD has been formed over the substrate in a BEOL processing. For example, the first ILD layer160has been formed over the substrate, covering the gate122and the second gate124. The first ILD layer160may be formed by chemical vapor deposition (CVD). Other techniques for forming the first ILD layer160may also be useful. The drain contact(s)162and body contacts164and166may be formed in the first ILD layer160. For example, via openings may be formed in the first ILD layer160by mask and etch techniques to expose the well taps145and147and the drain region113. After the via openings are formed, a conductive material may be deposited to fill the via openings. The conductive material may be formed by, for example, plating, such as electro or electro-less plating. Other types of conductive layers or forming techniques may also be useful. A planarization process, such as chemical mechanical polishing (CMP), may be performed to remove excess conductive material, forming the drain contact162and body contacts164and166in the first ILD layer160. According to various embodiments, a first ring-type barrier184and a second ring-type barrier186may be formed in the first ILD layer160. The first ring-type barrier184and a second ring-type barrier186may be formed to define a trench182of the drain captive structure. For example, openings corresponding to the first ring-type barrier184and the second ring-type barrier186may be formed in the first ILD layer160by mask and etch techniques, and a conductive material may be deposited to fill the openings. A planarization process, such as CMP, may be performed to remove excess conductive material, forming the first ring-type barrier184and the second ring-type barrier186in the first ILD layer160. In some embodiments, the first ring-type barrier184and the second ring-type barrier186may be formed in the same process step as the drain contact162and body contacts164and166. A conductive field plate177may be formed over the first ILD layer160. The conductive field plate177may be formed by depositing a conductive material over the first ILD layer160. A plate opening179may be formed in the conductive field plate177, for example, by mask and etch techniques. The plate opening may be formed to expose dielectric material in the trench182. Referring toFIG.2B, a patterned mask210such as a photoresist layer may be formed over the conductive field plate177to cover the conductive field plate177, while exposing the plate opening179and portion of dielectric material in the first ILD layer160. For example, a photoresist may be patterned by exposing it with an exposure source using a reticle with the desired pattern. After exposure, the photoresist may be developed, transferring the pattern of the reticle to the photoresist. The patterned photoresist may then be used as an etch mask to remove the dielectric material of the first ILD layer160in the trench182. According to various embodiments, the dielectric material in the trench182may be removed through the plate opening179. An etch, for example, using vapor hydrofluoric acid (VHF) may be performed to remove the dielectric material in the trench182through the plate opening179. As illustrated inFIG.2C, the trench182may be filled with air. The patterned mask may be removed, for example, by ashing in the case of a photoresist layer, after removing the dielectric material in the trench182. A second ILD layer192may be formed over the conductive field plate177, forming a sealed off or pinched off dielectric portion197in the plate opening179to seal the air gap183of the drain captive structure in the first ILD layer160. The plate opening179pinches off dielectric material of the second ILD layer192to form the sealed off dielectric portion197. The second ILD layer192, for example, may be deposited by plasma-enhanced CVD using high density plasma (HDP) process. The HDP process is a plasma CVD process that includes simultaneous deposition and sputtering components and may employs a plasma having an ion density on the order of 1011 ions/cm3 or greater, in a non-limiting example. The relative levels of the combined deposition and sputtering characteristics of the high-density plasma may depend on such factors as the flow rates used to provide the gaseous mixture, the source power levels applied to maintain the plasma, the bias power applied to the substrate, in a non-limiting example. The combination of such factors may be quantified with the D/S to characterize the process: DS=(netdepositionrate)+(blanketsputteringrate)(blanketsputteringrate) The D/S ratio increases with increased deposition and decreases with increased sputtering. As used in the definition of D/S, the “net deposition rate” refers to the deposition rate that is measured when deposition and sputtering are occurring simultaneously. The “blanket sputter rate” is the sputter rate measured when the process recipe is run without deposition gases; the pressure within the process chamber is adjusted to the pressure during deposition and the sputter rate measured on a blanket thermal oxide. The sealed off dielectric portion197may be formed by depositing dielectric material of the second ILD layer192over the conductive field plate179using the HDP process with a higher D/S ratio. In the case the second ILD layer192is formed of a combination of nitride and oxide, the second ILD layer192may be formed by deposition of nitride, followed by deposition of oxide using the HDP process. The deposition of nitride, for example, may be performed by plasma enhanced CVD with high pressure such that the nitride material lines the sidewalls of the plate opening179and/or trench182, but does not fill the trench182and space in the plate opening179. The deposition of oxide, for example, may be then performed using the HDP process with a higher D/S ratio. According to various embodiments, an etch back process may be performed after the deposition of the oxide over the conductive field plate177. The deposition of oxide using HDP process and the etch back may be performed alternately over the conductive field plate177having the small or narrow plate opening179. When the duration for the deposition (deposition time) is increased and the duration for the etch (etch time) is reduced, the dielectric material of the second ILD layer192does not fill the trench182, and the air gap183may be formed in the trench182and in the plate opening179under the sealed off dielectric portion197. In other words, the air gap183may be formed by controlling the deposition and etching of the dielectric material of the second ILD layer192over the geometrically narrow plate opening179of the conductive field plate177. The second ILD layer may then be planarized by, for example, using a CMP process. In addition, conductive vias and conductive lines (not shown) may be formed in the second ILD layer192. An optional thermal treatment may be performed after deposition of the second ILD layer192. Additional processes may be performed to complete the device. Such processes may include forming additional interconnect metal levels, final passivation, dicing, packaging, testing, etc. The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein. | 34,307 |
11862694 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various embodiments provide a method for improving interfaces between dielectric layers and contacts and semiconductor devices formed by said methods. The method includes forming an opening in a dielectric layer, depositing a first contact material in the opening, depositing a second contact material over the first contact material to form the contact, and performing an ion implantation process on the dielectric layer. The dielectric layer may include silicon oxide, silicon nitride, or the like; the first contact material may include cobalt or the like; and the second contact material may include tungsten, ruthenium, or the like. Ions implanted by the ion implantation process may include germanium, xenon, argon, silicon, arsenic, nitrogen, combinations thereof, or the like. Implanting the ions into the dielectric layer may cause the volume of the dielectric layer to expand, which forms a seal between the dielectric layer and the second contact material. A planarization process such as a chemical mechanical polish (CMP) planarizes the dielectric layer and the second contact material. The seal prevents chemicals used in the planarization process, such as CMP slurry, from penetrating between the second contact material and the dielectric layer and removing material of the first contact material. This reduces crack formation between the contact and the dielectric layer, reduces device defects and improves device performance. FIG.1illustrates an example of FinFETs, in accordance with some embodiments. The FinFETs comprise fins55on a substrate50(e.g., a semiconductor substrate). Shallow trench isolation (STI) regions58are disposed in the substrate50and the fins55protrude above and from between neighboring STI regions58. Although the STI regions58are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of STI regions. Additionally, although the fins55are illustrated as single, continuous materials with the substrate50, the fins55and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fins55refer to the portions extending between the neighboring STI regions58. Gate dielectric layers100are along sidewalls and over a top surface of the fins55, and gate electrodes102are over the gate dielectric layers100. Epitaxial source/drain regions92are disposed on opposite sides of the fins55, the gate dielectric layers100, and the gate electrodes102.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode102and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions92of the FinFETs. Cross-section B-B′ is perpendicular to cross-section A-A′ and is along a longitudinal axis of a fin55and in a direction of, for example, the current flow between the epitaxial source/drain regions92of the FinFETs. Cross-section C-C′ is parallel to cross-section A-A′ and extends through the epitaxial source/drain regions92of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity. Some embodiments discussed herein are discussed in the context of fin field effect transistors (FinFETs) formed using gate-last processes. In some embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices (e.g., planar field effect transistors), nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like. FIGS.2through22Bare cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2through5,6A,7A,8A,9A,10A,11A,12A,13A,14A,15A,16A,17A,18A,19A,20A,21A, and22Aare illustrated along reference cross-section A-A′ illustrated inFIG.1.FIGS.6B,7B,8B,9B,10B,11B,12B,13B,14B,14C,15B,16B,17B,18B,18D,19B,19D,20B,20D,21B, and22Bare illustrated along a similar cross-section B-B′ illustrated inFIG.1.FIGS.7C,8C,9C,10C, and10Dare illustrated along reference cross-section C-C′ illustrated inFIG.1.FIGS.15C,16C,17C,18C,19C,19E,19F, and20Care top-down views. InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. The substrate50has a region50N and a region50P. The region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The region50N may be physically separated from the region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region50N and the region50P. InFIG.3, fins55are formed in the substrate50. The fins55are semiconductor strips. In some embodiments, the fins55may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), a neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. The fins55may be patterned by any suitable method. For example, the fins55may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins55. In some embodiments, the mask (or other layer) may remain on the fins55. InFIG.4, shallow trench isolation (STI) regions58are formed adjacent the fins55. The STI regions58may be formed by forming an insulation material (not separately illustrated) over the substrate50and between neighboring fins55. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system with post curing to convert the deposited material to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In some embodiments, the insulation material is formed such that excess insulation material covers the fins55. The insulation material may comprise a single layer or may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along surfaces of the substrate50and the fins55. Thereafter, a fill material, such as those discussed above may be formed over the liner. A removal process is then applied to the insulation material to remove excess insulation material over the fins55. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may planarize the insulation material and the fins55. The planarization process exposes the fins55such that top surfaces of the fins55and the insulation material are level after the planarization process is complete. The insulation material is then recessed to form the STI regions58as illustrated inFIG.4. The insulation material is recessed such that upper portions of the fins55and the substrate50protrude from between neighboring STI regions58. Further, the top surfaces of the STI regions58may have flat surfaces as illustrated, convex surfaces, concave surfaces (such as dishing), or a combination thereof. The top surfaces of the STI regions58may be formed flat, convex, and/or concave by an appropriate etch. The STI regions58may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins55and the substrate50). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. The process described with respect toFIGS.2-4is just one example of how the fins55may be formed. In some embodiments, the fins55may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins55. For example, the fins55inFIG.4can be recessed, and a material different from the fins55may be epitaxially grown over the recessed fins55. In such embodiments, the fins55comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In some embodiments, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins55. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in region50N (e.g., an NMOS region) different from the material in region50P (e.g., a PMOS region). In some embodiments, upper portions of the fins55may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like. Further inFIG.4, appropriate wells (not separately illustrated) may be formed in the fins55and/or the substrate50. In some embodiments, a P well may be formed in the region50N, and an N well may be formed in the region50P. In some embodiments, a P well or an N well are formed in both the region50N and the region50P. In the embodiments with different well types, the different implant steps for the region50N and the region50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins55and the STI regions58in the region50N. The photoresist is patterned to expose the region50P of the substrate50, such as a PMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the region50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1×1018atoms/cm3, such as between about 1×1016atoms/cm3and about 1×1018atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process. Following the implanting of the region50P, a photoresist is formed over the fins55and the STI regions58in the region50P. The photoresist is patterned to expose the region50N of the substrate50, such as the NMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the region50P, such as the PMOS region. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1×1018atoms/cm3, such as between about 1×1016atoms/cm3and about 1×1018atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. After the implants of the region50N and the region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. InFIG.5, dummy dielectric layers60are formed on the fins55and the substrate50. The dummy dielectric layers60may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer62is formed over the dummy dielectric layers60, and a mask layer64is formed over the dummy gate layer62. The dummy gate layer62may be deposited over the dummy dielectric layers60and then planarized by a process such as CMP. The mask layer64may be deposited over the dummy gate layer62. The dummy gate layer62may be conductive or non-conductive materials and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing the selected material. The dummy gate layer62may be made of other materials that have a high etching selectivity from the material of the STI regions58. The mask layer64may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer62and a single mask layer64are formed across the region50N and the region50P. It is noted that the dummy dielectric layers60are shown covering only the fins55and the substrate50for illustrative purposes only. In some embodiments, the dummy dielectric layers60may be deposited such that the dummy dielectric layers60cover the STI regions58, extending between the dummy gate layer62and the STI regions58. FIGS.6A through22Billustrate various additional steps in the manufacturing of embodiment devices.FIGS.6A through22Billustrate features in either of the region50N or the region50P. For example, the structures illustrated inFIGS.6A through22Bmay be applicable to both the region50N and the region50P. Differences (if any) in the structures of the region50N and the region50P are described in the text accompanying each figure. InFIGS.6A and6B, the mask layer64(seeFIG.5) may be patterned using acceptable photolithography and etching techniques to form masks74. An acceptable etching technique may be used to transfer the pattern of the masks74to the dummy gate layer62to form dummy gates72. In some embodiments, the pattern of the masks74may also be transferred to the dummy dielectric layers60. The dummy gates72cover respective channel regions68of the fins55. The pattern of the masks74may be used to physically separate each of the dummy gates72from adjacent dummy gates72. The dummy gates72may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins55. The dummy dielectric layers60, the dummy gates72, and the masks74may be collectively referred to as “dummy gate stacks.” InFIGS.7A through7C, a first spacer layer80and a second spacer layer82are formed over the structures illustrated inFIGS.6A and6B. InFIGS.7A through7C, the first spacer layer80is formed on top surfaces of the STI regions58, top surfaces and sidewalls of the fins55and the masks74, and sidewalls of the dummy gates72and the dummy dielectric layers60. The second spacer layer82is deposited over the first spacer layer80. The first spacer layer80may be formed by thermal oxidation or deposited by CVD, ALD, or the like. The first spacer layer80may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer82may be deposited by CVD, ALD, or the like. The second spacer layer82may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. InFIGS.8A through8C, the first spacer layer80and the second spacer layer82are etched to form first spacers81and second spacers83. The first spacer layer80and the second spacer layer82may be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. The first spacers81and the second spacers83may be disposed on sidewalls of the fins55, the dummy dielectric layers60, the dummy gates72, and the masks74. The first spacers81and the second spacers83may have different heights adjacent the fins55and the dummy gate stacks due to the etching processes used to etch the first spacer layer80and the second spacer layer82, as well as different heights between the fins55and the dummy gate stacks. Specifically, as illustrated inFIGS.8B and8C, in some embodiments, the first spacers81and the second spacers83may extend partially up sidewalls of the fins55and the dummy gate stacks. In some embodiments, the first spacers81and the second spacers83may extend to top surfaces of the dummy gate stacks. After the first spacers81and the second spacers83are formed, implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above inFIG.4, a mask, such as a photoresist, may be formed over the region50N, while exposing the region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins55and the substrate50in the region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region50P while exposing the region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins55and the substrate50in the region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities of from about 1×1015atoms/cm3to about 1×1019atoms/cm3. An anneal may be used to repair implant damage and to activate the implanted impurities. It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers81may be formed prior to forming the second spacers83, additional spacers may be formed and removed, and/or the like). Furthermore, the n-type and p-type devices may be formed using a different structures and steps. InFIGS.9A through9C, the substrate50and the fins55are etched to form first recesses86. As illustrated inFIG.9C, top surfaces of the STI regions58may be level with top surfaces of the fins55. In some embodiments, bottom surfaces of the first recesses86are disposed above or below the top surfaces of the STI regions58. The substrate50/fins55are etched using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers81, the second spacers83, and the masks74mask portions of the substrate50/fins55during the etching processes used to form the first recesses86. A single etch process or multiple etch processes may be used to form the first recesses86. Timed etch processes may be used to stop the etching of the first recesses86after the first recesses86reach a desired depth. InFIGS.10A through10D, epitaxial source/drain regions92are formed in the first recesses86to exert stress on the channel regions68of the fins55, thereby improving performance. As illustrated inFIG.10B, the epitaxial source/drain regions92are formed in the first recesses86such that each dummy gate72is disposed between respective neighboring pairs of the epitaxial source/drain regions92. In some embodiments, the first spacers81and second spacers83are used to separate the epitaxial source/drain regions92from the dummy gates72by an appropriate lateral distance so that the epitaxial source/drain regions92do not short out subsequently formed gates of the resulting FinFETs. The epitaxial source/drain regions92in the region50N, e.g., the NMOS region, may be formed by masking the region50P, e.g., the PMOS region. Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86. The epitaxial source/drain regions92may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fins55are silicon, the epitaxial source/drain regions92may include materials exerting a tensile strain on the fins55, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions92may have surfaces raised from respective surfaces of the fins55and may have facets. The epitaxial source/drain regions92in the region50P, e.g., the PMOS region, may be formed by masking the region50N, e.g., the NMOS region. Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86. The epitaxial source/drain regions92may include any acceptable material, such as appropriate for p-type NSFETs. For example, if the fins55are silicon, the epitaxial source/drain regions92may comprise materials exerting a compressive strain on the fins55, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions92may also have surfaces raised from respective surfaces of the fins55and may have facets. The epitaxial source/drain regions92, the fins55, and/or the substrate50may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1019atoms/cm3and about 1×1021atoms/cm3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions92may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions92in the region50N and the region50P, upper surfaces of the epitaxial source/drain regions92have facets which expand laterally outward beyond sidewalls of the fins55. In some embodiments, these facets cause adjacent epitaxial source/drain regions92of a same FinFET to merge as illustrated byFIG.10C. In some embodiments, adjacent epitaxial source/drain regions92remain separated after the epitaxy process is completed as illustrated byFIG.10D. In the embodiments illustrated inFIGS.10C and10D, the first spacers81may be formed covering portions of the sidewalls of the fins55that extend above the STI regions58thereby blocking the epitaxial growth. In some embodiments, the spacer etch used to form the first spacers81may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region58. The epitaxial source/drain regions92may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions92may comprise a first semiconductor material layer92A, a second semiconductor material layer92B, and a third semiconductor material layer92C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions92. Each of the first semiconductor material layer92A, the second semiconductor material layer92B, and the third semiconductor material layer92C may be formed of different semiconductor materials and/or may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer92A may have a dopant concentration less than the second semiconductor material layer92B and greater than the third semiconductor material layer92C. In embodiments in which the epitaxial source/drain regions92comprise three semiconductor material layers, the first semiconductor material layer92A may be deposited, the second semiconductor material layer92B may be deposited over the first semiconductor material layer92A, and the third semiconductor material layer92C may be deposited over the second semiconductor material layer92B. InFIGS.11A and11B, a first interlayer dielectric (ILD)96is deposited over the structure illustrated inFIGS.10A and10B, respectively. The first ILD96may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the dielectric materials for the first ILD96may include silicon oxide, silicon nitride, silicon oxynitride, or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)94is disposed between the first ILD96and the epitaxial source/drain regions92, the masks74, the first spacers81, and the second spacers83. The CESL94may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD96. In some embodiments, the first ILD96may be formed of silicon oxide or silicon nitride and the CESL94may be formed of silicon oxide or silicon nitride. InFIGS.12A and12B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD96with the top surfaces of the dummy gates72or the masks74. The planarization process may also remove the masks74on the dummy gates72, and portions of the first spacers8iand the second spacers83along sidewalls of the masks74. After the planarization process, top surfaces of the dummy gates72, the first spacers81, and the first ILD96are level. Accordingly, the top surfaces of the dummy gates72are exposed through the first ILD96. In some embodiments, the masks74may remain, in which case the planarization process levels the top surface of the first ILD96with top surface of the masks74and the first spacers8i. InFIGS.13A and13B, the dummy gates72, and the masks74if present, are removed in an etching step(s), so that second recesses98are formed. Portions of the dummy dielectric layers60in the second recesses98may also be removed. In some embodiments, only the dummy gates72are removed and the dummy dielectric layers60remain and are exposed by the second recesses98. In some embodiments, the dummy dielectric layers60are removed from second recesses98in a first region of a die (e.g., a core logic region) and remain in second recesses98in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates72are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates72at a faster rate than the first ILD96or the first spacers81. Each second recess98exposes and/or overlies a channel region68of a respective fin55. Each channel region68is disposed between neighboring pairs of the epitaxial source/drain regions92. During the removal, the dummy dielectric layer60may be used as an etch stop layer when the dummy gates72are etched. The dummy dielectric layer60may be optionally removed after removing the dummy gates72. InFIGS.14A and14B, gate dielectric layers100and gate electrodes102are formed for replacement gates.FIG.14Cillustrates a detailed view of region103ofFIG.14B. The gate dielectric layers100may be formed by depositing one or more layers in the second recesses98, such as on top surfaces and sidewalls of the fins55and the first spacers81and on top surfaces of the STI regions58, the first ILD96, the CESL94, and the second spacers83. The gate dielectric layers100may comprise one or more layers of silicon oxide, silicon nitride, metal oxides, metal silicates, or the like. For example, in some embodiments, the gate dielectric layers100include an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, a combination thereof, or the like. The gate dielectric layers100may include a dielectric layer having a k-value greater than about 7.0. The gate dielectric layers100may be deposited by molecular-beam deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layer60remain in the second recesses98, the gate dielectric layers100may include a material of the dummy dielectric layer60(e.g., SiO2). The gate electrodes102are deposited over the gate dielectric layers100and fill remaining portions of the second recesses98. The gate electrodes102may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode102is illustrated inFIG.14B, the gate electrodes102may comprise any number of liner layers102A, any number of work function tuning layers102B, and a fill material102C as illustrated byFIG.14C. After the filling of the second recesses98, a planarization process, such as a CMP, is performed to remove excess portions of the gate dielectric layers100and the gate electrodes102, which excess portions are over top surfaces of the first ILD96. The remaining portions of the gate electrodes102and the gate dielectric layers100form replacement gates of the resulting FinFETs. The gate electrodes102and the gate dielectric layers100may be collectively referred to as “gate stacks.” The gate stacks may extend along sidewalls of the channel regions68of the fins55. The formation of the gate dielectric layers100in the region50N and the region50P may occur simultaneously such that the gate dielectric layers100in each region are formed from the same materials. The formation of the gate electrodes102may occur simultaneously such that the gate electrodes102in each region are formed from the same materials. In some embodiments, the gate dielectric layers100in each region may be formed by distinct processes, such that the gate dielectric layers100may be different materials. The gate electrodes102in each region may be formed by distinct processes, such that the gate electrodes102may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. InFIGS.15A through15C, the first ILD96and the CESL94are etched to form third recesses104exposing surfaces of the epitaxial source/drain regions92. The third recesses104may be formed using acceptable photolithography and etching techniques. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. InFIGS.16A through16C, a liner106, such as a diffusion barrier layer, an adhesion layer, or the like, is formed in the third recesses104. The liner106may include titanium, titanium nitride, tantalum, tantalum nitride, silicon nitride, or the like. The liner106may be deposited by a conformal process, such as CVD, ALD, or the like. The liner106may be deposited along top surfaces of the gate electrodes102, the gate dielectric layers100, the first spacers81, the second spacers83, and the epitaxial source/drain regions92; and along top surfaces and sidewalls of the first ILD96and the CESL94. The liner106may then be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like to remove lateral portions of the liner106and expose surfaces of the epitaxial source/drain regions92. Etching the liner106may further remove portions of the liner106from above the top surfaces of the gate electrodes102, the gate dielectric layers100, the first spacers81, the second spacers83, the first ILD96, and the CESL94. The liner106may have a thickness ranging from about 1 nm to about 2 nm. InFIGS.17A through17C, a first contact material108is formed in the third recesses104over the epitaxial source/drain regions92and the liner106. The first contact material108may be a conductive material, such as cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), combinations thereof, or the like. The first contact material108may be deposited using a deposition process such as sputtering, chemical vapor deposition, atomic layer deposition, electroplating, electroless plating, or the like. In some embodiments, the first contact material108may be deposited to fill or overfill the third recesses104. The first contact material108may be planarized with top surfaces of the first ILD96, the CESL94, the liner106, the gate electrodes102, the gate dielectric layers100, the first spacers81, and the second spacers83. The first contact material108may then be recessed to a level below the top surfaces of the first ILD96, the CESL94, the liner106, the gate electrodes102, the gate dielectric layers100, the first spacers81, and the second spacers83. In an embodiment the first contact material108is recessed using a wet or dry etching process that uses one or more etchants that are selective to the material of the first contact material108(e.g., cobalt or the like) without significantly removing the material of the first ILD96, the CESL94, the liner106, the gate electrodes102, the gate dielectric layers100, the first spacers81, and the second spacers83. The first contact material108may be recessed a first distance D1of between about 18 nm and about 25 nm. However, any suitable distance may be utilized. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions92and the first contact material108. The first contact material108is physically and electrically coupled to the epitaxial source/drain regions92. InFIGS.18A through18D, a second contact material110is formed in the third recesses104over the first contact material108. The second contact material110may be a conductive material, such as tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), molybdenum (Mo), combinations thereof, or the like. The second contact material110may be deposited using a deposition process such as sputtering, chemical vapor deposition, atomic layer deposition, electroplating, electroless plating, or the like. In some embodiments, the second contact material110may be deposited to fill or overfill the third recesses104. In the embodiment illustrated inFIG.18B, the second contact material110may be deposited by a plating process or the like and, following the deposition, top surfaces of the second contact material110may be disposed above top surfaces of the first ILD96, the CESL94, the liner106, the gate electrodes102, the gate dielectric layers100, the first spacers81, and the second spacers83. In some embodiments, the second contact material110may be formed of a material different from a material of the first contact material108. Using different materials for the second contact material110and the first contact material108lowers contact resistance, which improves device performance. FIG.18Dillustrates an embodiment in which top surfaces of the first contact material108and the second contact material110are non-planar. As illustrated inFIG.18D, top surfaces of the first contact material108and the second contact material110may be W-shaped or M-shaped in a cross-sectional view. The top surfaces of the first contact material108and the second contact material110may have one or more dimples. However, any suitable shapes are possible for the first contact material108and the second contact material110, depending on the deposition and etch processes used to form the first contact material108and the second contact material110. In some embodiments, the first contact material108and the second contact material110may be deposited by CVD at a temperature ranging from about 300° C. to about 500° C., by PVD at room temperature, or the like. The deposition process may be followed by an anneal process at a temperature ranging from about 300° C. to about 600° C. Dry etching processes, such as halogen-based processes, may be used to define the first contact material108and the second contact material110. In some embodiments, the second contact material110may be deposited by a plating process or the like. Following the deposition, top surfaces of the second contact material110may be disposed above top surfaces of the first ILD96, the CESL94, the liner106, the gate electrodes102, the gate dielectric layers100, the first spacers81, and the second spacers83. Materials of the second contact material110and the liner106may not have good adhesion with one another, such that cracks or other defects may be formed between the second contact material110and the liner106during subsequent processes. For example, cracks may be formed between the second contact material110and the liner106during a subsequent process used to planarize the second contact material110(discussed below with respect toFIGS.20A through20D). The cracks may allow process fluids, such as a CMP slurry, to penetrate between the second contact material110and the liner106and the process fluids may remove material of the second contact material110and the first contact material108, creating further device defects and reducing device performance. InFIGS.19A through19E, doped contact portions110aare formed in the second contact material110, doped liner portions106aare formed in the liner106, doped ILD portions96aare formed in the first ILD96, and doped CESL portions94aare formed in the CESL94.FIGS.19E and19Fillustrate detailed views of a region111ofFIG.19C. Doping the liner106, the first ILD96, and the CESL94to form the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a, respectively, may cause materials of the liner106, the first ILD96, and the CESL94to expand, improving sealing between the doped contact portions110athe doped liner portions106a. The improved sealing between doped liner portions106aand the doped contact portions110aprevents process fluids, such as a CMP slurry, from penetrating between the doped liner portions106aand the doped contact portions110a. This prevents materials of the doped contact portions110a, the second contact material110, and the first contact material108from being undesirably removed by the process fluids or the like, which reduces device defects and improves device performance. Outer surfaces of each of the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94amay expand outwards a distance ranging from about 1 nm to about 10 nm or from about 1 nm to about 5 nm. Expansion of the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94aby at least this amount improves the sealing between the doped contact portions110aand each of the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a, which prevents process fluids from penetrating between the doped contact portions110a, the second contact materials110, and the first contact materials108and each of the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a. This prevents undesired removal of material from each of the doped contact portions110a, the second contact material110, and the first contact material108, reduces device defects, and improves device performance. The dopants in each of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a, may extend to a depth ranging from about 1 nm to about 15 nm or from about 1 nm to about 10 nm. Although bottom extents of each of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94aare illustrated as being aligned with one another at the same depth, any of the bottom surfaces of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94amay be misaligned with one another and may extend to different depths. In the embodiment illustrated inFIGS.19A through19D, the first contact material108is free from the dopants. However, in some embodiments, the dopants may extend throughout a partial thickness or the entire thickness of the second contact material110and the dopants may extend into the first contact material108. In some embodiments, the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94amay include the same dopants, which may include germanium (Ge), silicon (Si), argon (Ar), xenon (Xe), arsenic (As), nitrogen (N), combinations thereof, or the like. In some embodiments, the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94amay further include hydrogen (H), which may be implanted from ambient air or the like along with the dopants. The doped contact portions110a, the doped CESL portions94a, the doped liner portions106a, and the doped ILD portions96amay be formed by an ion implantation. A dosage for the ion implantation may range from about 1×1014atoms/cm2to about 1×1016atoms/cm2and a tilt angle for the ion implantation may range from about 0 degrees to about 60 degrees. The ion implantation may be performed at a temperature ranging from about −100° C. to about 500° C. with an applied energy ranging from about 2 keV to about 50 keV. In some embodiments, performing the ion implantation at a temperature ranging from about −100° C. to about 25° C. may provide for greater expansion of the doped liner portions106a, the doped ILD portions96a, and/or the doped CESL portions94a, which may further improve sealing between the doped contact portions110aand the doped liner portions106a. In some embodiments, concentrations of the dopants in each of the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94amay range from about 1×1020atoms/cm3to about 2×1022atoms/cm3. In some embodiments, concentrations of the dopants in the doped contact portions110amay range from about 1×1018atoms/cm3to about 1×1021atoms/cm3. The distribution of dopants may vary throughout each of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a. A distribution of the dopants in the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94ais depicted as the curve109illustrated inFIGS.19B and19D. In some embodiments, a peak of the distribution curve109can be near the middle of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94ain a direction perpendicular to a major surface of the substrate50, but the disclosure is not limited thereto. In some embodiments, the peak of the distribution curve109may be near top surfaces of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a. FIGS.19E and19Fillustrate stress applied to the doped contact portions110aby the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a, in accordance with some embodiments. In the embodiment illustrated inFIG.19E, the first contact material108(not separately illustrated), the second contact material110(not separately illustrated), and the doped contact portions110amay have rectangular shapes in a top-down view. The stress Sx1applied to the doped contact portions110ain a first direction may be proportional to a width b1of the doped contact portions110ain the first direction and the stress Sy1applied to the doped contact portions110ain a second direction perpendicular to the first direction may be proportional to a width a1of the doped contact portions110ain the second direction. The stress Sx1and the stress Sy1may also depend on the materials of the CESL94and the first ILD96. The width a1and the width b1may range from about 5 nm to about 200 nm and a ratio of the width a1to the width b1may range from about 1 to about 40. In embodiments in which the CESL94and the first ILD96are formed of the same materials (e.g., silicon oxide, silicon nitride, or the like), the stress Sx1and the stress Sy1may be equal when the width a1and the width b1are equal, the stress Sx1may be greater than the stress Sy1when a1is less than b1, and the stress Sx1may be less than the stress Sy1when a1is greater than b1. In embodiments in which the CESL94and the first ILD96are formed of different materials, the stress Sx1and the stress Sy1may be equal when either of the widths a1or b1are greater and either of the stress Sx1or the stress Sy1may be greater when the widths a1and b1are equal or when either of the widths a1or b1are greater. In the embodiment illustrated inFIG.19F, the first contact material108(not separately illustrated), the second contact material110(not separately illustrated), and the doped contact portions110amay have round shapes (e.g., elliptical shapes) in a top-down view. The stress Sx2applied to the doped contact portions110ain a first direction may be proportional to a width b2of the doped contact portions110ain the first direction and the stress Sy2applied to the doped contact portions110ain a second direction perpendicular to the first direction may be proportional to a width a2of the doped contact portions110ain the second direction. The stress Sx2and the stress Sy2may also depend on the materials of the CESL94and the first ILD96. The width a2and the width b2may range from about 5 nm to about 200 nm and a ratio of the width a2to the width b2may range from about 1 to about 40. In embodiments in which the CESL94and the first ILD96are formed of the same materials (e.g., silicon oxide, silicon nitride, or the like), the stress Sx2and the stress Sy2may be equal when the width a2and the width b2are equal, the stress Sx2may be greater than the stress Sy2when a2is less than b2, and the stress Sx2may be less than the stress Sy2when a2is greater than b2. In embodiments in which the CESL94and the first ILD96are formed of different materials, the stress Sx2and the stress Sy2may be equal when either of the widths a2or b2are greater and either of the stress Sx2or the stress Sy2may be greater when the widths a2and b2are equal or when either of the widths a2or b2are greater. Although the dopants have been described as only being implanted in the second contact material110, the liner106, the first ILD96, and the CESL94, in some embodiments, the dopants may also be implanted in the first spacers81, the second spacers83, the gate dielectric layers100, and the gate electrodes102. Implanting the dopants in any of the first spacers81, the second spacers83, the gate dielectric layers100, and the gate electrodes102may cause additional stress to be applied to the doped contact portions110a, which may improve sealing between the doped contact portions110aand the doped liner portions106a. Moreover, in some embodiments, the dopants may be implanted throughout the thickness of the second contact material110and into the first contact material108. InFIGS.20A through20D, a planarization process, such as a CMP, may be performed to level top surfaces of the doped contact portions110awith top surfaces of the doped liner portions106a, the doped ILD portions96a, the doped CESL portions94a, the first spacers81, the second spacers83, the gate dielectric layers100, and the gate electrodes102. The planarization process may use process fluids, such as a CMP slurry and the like, which may remove materials of the first contact material108, the second contact material110, and the doped contact portions110awhen the process fluids come into contact with the first contact material108, the second contact material110, and the doped contact portions110a. Performing the ion implant process to form the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94aimproves sealing between the doped contact portions110aand the doped liner portions106a, which prevents the process fluids from penetration between the doped liner portions106aand each of the doped contact portions110a, the second contact material110, and the first contact material108. This prevents undesired removal of material from the doped contact portions110a, the second contact material110, and the first contact material108, reduces device defects, and improves device performance. Following the planarization, a peak of the distribution of the dopants in the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94acan be near the middle of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94ain a direction perpendicular to a major surface of the substrate50. In some embodiments, the peak of the distribution of the dopants in the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94amay be near top surfaces of the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a. InFIGS.21A and21B, a second ILD114is deposited over the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, the doped CESL portions94a, the first spacers81, the second spacers83, the gate dielectric layers100, and the gate electrodes102. In some embodiments, the second ILD114is a flowable film formed by FCVD. In some embodiments, the second ILD114is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, the dielectric materials for the second ILD114may include silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, before the formation of the second ILD114, the gate stack (including the gate dielectric layers100and the corresponding overlying gate electrodes102) is recessed, so that a recess is formed directly over the gate stack and between opposing portions of first spacers81. A gate mask112comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the doped contact portions110a, the doped liner portions106a, the doped ILD portions96a, the doped CESL portions94a, the first spacers81, and the second spacers83. Subsequently formed gate contacts (such as the gate contacts116, discussed below with respect toFIGS.22A and22B) penetrate through the gate mask112to contact the top surface of the recessed gate electrodes102. InFIGS.22A and22B, gate contacts116are formed through the second ILD114and the gate masks112and source/drain contacts118are formed through the second ILD114. Openings for the source/drain contacts118are formed through the second ILD114and openings for the gate contacts116are formed through the second ILD114and the gate mask112. The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD114. The remaining liner and conductive material form the source/drain contacts118and the gate contacts116in the openings. The source/drain contacts118are physically and electrically coupled to the epitaxial source/drain regions92through the first contact material108, the second contact material, and the doped contact portions110a, and the gate contacts116are physically and electrically coupled to the gate electrodes102. The source/drain contacts118and the gate contacts116may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts118and the gate contacts116may be formed in different cross-sections, which may avoid shorting of the contacts. Embodiments may achieve various advantages. For example, doping the liner106, the first ILD96, and the CESL94to form the doped liner portions106a, the doped ILD portions96a, and the doped CESL portions94a, respectively, may cause materials of the liner106, the first ILD96, and the CESL94to expand, improving sealing between the doped contact portions110athe doped liner portions106a. The improved sealing between doped liner portions106aand the doped contact portions110aprevents process fluids, such as a CMP slurry, from penetrating between the doped liner portions106aand the doped contact portions110a. This prevents materials of the doped contact portions110a, the second contact material110, and the first contact material108from being undesirably removed by the process fluids or the like, which reduces device defects and improves device performance. The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. A nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016/0365414, which is incorporated herein by reference in its entirety. In accordance with an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant. In an embodiment, the first dopant includes germanium (Ge). In an embodiment, the first contact material includes cobalt (Co) and the second contact material includes tungsten (W). In an embodiment, the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner each extend to depths ranging from 1 nm to 15 nm. In an embodiment, top surfaces of the first dielectric layer, the metal feature, and the dielectric liner are level with one another. In an embodiment, the semiconductor device further includes a second dielectric layer over the conductive feature, a first portion of the second dielectric layer is doped with the first dopant, the first dielectric layer and the second dielectric layer each contact sidewalls of the dielectric liner, and the first dielectric layer and the second dielectric layer each include different materials. In an embodiment, the first dielectric layer includes silicon oxide and the second dielectric layer includes silicon nitride. In an embodiment, a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner is at a top surface of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner, respectively. In an embodiment, a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the first dielectric layer is below a top surface of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the first dielectric layer, respectively. In accordance with another embodiment, a semiconductor device includes a first dielectric layer over a substrate and a conductive feature; a first doped dielectric layer over the first dielectric layer; a first metal portion in the first dielectric layer and electrically coupled to the conductive feature; a doped metal portion over the first metal portion, the first metal portion and the doped metal portion including a same metal material; a dielectric liner between the first dielectric layer and the first metal portion; and a doped liner over the dielectric liner and between the first doped dielectric layer and the doped metal portion, the first doped dielectric layer, the doped liner, and the doped metal portion each including first dopants. In an embodiment, the first dopants include xenon (Xe). In an embodiment, the semiconductor device further includes a second metal portion between the first metal portion and the conductive feature, the second metal portion electrically coupling the first metal portion to the conductive feature, the second metal portion including a different metal than the first metal portion. In an embodiment, the second metal portion includes cobalt (Co) and the first metal portion includes ruthenium (Ru). In an embodiment, the dielectric liner contacts sidewalls of the first metal portion and the second metal portion, and the doped liner contacts sidewalls of the first metal portion. In an embodiment, bottom extents of the first doped dielectric layer, the doped metal portion, and the doped liner are aligned with one another. In accordance with yet another embodiment, a method includes depositing a first dielectric layer over a conductive feature; etching the first dielectric layer to form an opening exposing the conductive feature; forming a dielectric liner in the opening, the dielectric liner lining sidewalls of the first dielectric layer; forming a first metal portion in the opening over the conductive feature; forming a second metal portion over the first metal portion and filling the opening, the second metal portion including a material different from the first metal portion; and performing an ion implantation on the first dielectric layer, the dielectric liner, and the second metal portion, the ion implantation causing the material of the first dielectric layer and the dielectric liner to expand in a direction towards the second metal portion. In an embodiment, forming the first metal portion includes depositing a first metal material in the opening; and etching back the first metal material, the first metal material including cobalt. In an embodiment, the ion implantation is performed at a temperature from −100° C. to 25° C. In an embodiment, the ion implantation is performed with germanium dopants at a dosage from 1×1014atoms/cm2to 1×1016atoms/cm2, and the ion implantation causes the material of the first dielectric layer and the dielectric liner to expand in the direction towards the second metal portion by at least 1 nm. In an embodiment, the method further includes planarizing the second metal portion, the dielectric liner, and the first dielectric layer after performing the ion implantation. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 65,830 |
11862695 | Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness. The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application. Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween. As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items. Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples. Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly. The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof. Due to manufacturing techniques and/or tolerances, variations of the shapes shown in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing. The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application. The identification codes (e.g., a, b, c, etc.) in each operation are used for convenience of description and do not describe the order of each operation. Unless specific orders are explicitly specified by the context, each operation may be performed in a different order from the specified order. That is, each operation may be performed in the same order as the specified order, may be performed substantially at the same time, or may be performed in a reverse order to the specified order. Additionally, the terms “first type” and “second type” may refer to opposite conductive types such as P-type or N-type. Each of the embodiments described and shown herein may include a complementary embodiment thereof. The examples described below will be described by exemplifying examples in which the first type is a P-type and the second type is an N-type. Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the examples belong. Commonly used terms defined in the dictionary are to be construed to have exactly the same meaning as that of related technology in the context. As long as terms are not clearly defined in the examples, the terms should not be ideally or excessively construed as formal meaning. Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. FIGS.1A and1Billustrate examples of structures of a trench power MOSFET which are to be compared, and in particular, a structure of an example split gate trench power metal-oxide semiconductor field-effect transistor (MOSFET). In an example, the split gate power MOSFET may have a low capacitance between a gate electrode and a source electrode. One or more examples provide a split gate trench power MOSFET structure which has a low capacitance between a gate electrode and a source electrode, obtains uniformity of the thickness of an insulating layer formed on the source electrode, and can be manufactured by an easy manufacturing process. In one or more examples, the efficiency of a power semiconductor device may be increased by reducing a capacitance between the gate electrode and the source electrode based on the example structure. In one or more examples, the difference in characteristics according to the example process may be minimized by obtaining uniformity of the thickness of the insulating layer formed on the source electrode based on the example manufacturing process. The first structure of the split gate trench power MOSFET shown inFIG.1Amay have a long middle source electrode140and gate electrodes150on both sides of the source electrode140. The first structure, as illustrated inFIG.1Amay be formed by implementing an easy manufacturing process and may have a problem of a high capacitance between the gate electrode150and the source electrode140. The second structure of the split gate trench power MOSFET illustrated inFIG.1Bmay have a source electrode140within the structure, and a gate electrode150positioned above the source electrode140. The structure illustrated inFIG.1Bmay have an advantage of having a low capacitance between the source electrode140and the gate electrode150. However, it may be difficult to control and maintain a thickness of a first inter-electrode insulating layer430disposed between the source electrode140and the gate electrode150. Other annotation numbers besides the source electrode140and the gate electrode150are explained in the followedFIGS.2A and2B. FIG.2Aillustrates a structure of a split gate trench MOSFET structure, in accordance with one or more embodiments. WhileFIG.2Aillustrates a structure of an N-type split gate trench MOSFET, it can be understood that a structure of a P-type split gate trench MOSFET is the same except for a difference in doping. Referring toFIG.2A, at least one split gate trench MOSFET includes a high concentration N-type drain region110formed in a semiconductor substrate105, and includes a low concentration N-type epitaxial layer120provided on the high concentration N-type drain region110. In an example, the high concentration N-type drain region110may have a higher doping concentration than a doping concentration of the low concentration N-type epitaxial layer120. The low concentration N-type epitaxial layer120can be used as a drift region of the trench MOSFET. Additionally, drain metal may be further provided below the high concentration N-type drain region110. In order to form the split gate trench MOSFET, a gate trench130may be formed such that it starts from the top surface of the low concentration N-type epitaxial layer120and extends to an inner region of the low concentration N-type epitaxial layer120. In an example, the lower portion of the gate trench130may be formed to be spaced apart from the high concentration N-type drain region110by a predetermined distance or more. A sidewall insulating layer410and a source electrode140may be provided within the gate trench130. According to the embodiment, the source electrode140may be located within the gate trench130, and the sidewall insulating layer410may be provided on both sides of the source electrode140, and may fill the inside region of the gate trench130. The width of the sidewall insulating layer410may be greater than the width of the source electrode140. The source electrode140may be formed in order to reduce parasitic capacitance between a gate and a drain. The source electrode140may be electrically connected to source metal190. Additionally, since the source metal190may be electrically connected to a P-type body region170, the source electrode140may also be electrically connected to the P-type body region170. In one or more examples, the source electrode140may be referred to as a lower electrode, a shield electrode, a field plate electrode, or the like. In one or more examples, the split gate trench MOSFET includes a gate insulating layer440formed on an upper sidewall of the gate trench130. Each of two gate electrodes (or gate poly)150may be formed on the gate insulating layer440, or may be formed adjacent to the gate insulating layer440. Floating poly-Si (or floating gate poly)145may be formed between the two gate electrodes (or gate poly)150. The floating poly-Si (or floating gate poly)145may also be implemented as a gate electrode. Hereinafter, the two gate electrodes (or gate poly)150may be referred to as a second upper electrode. The floating poly-Si (or floating gate poly)145may be referred to as a first upper electrode. A plurality of upper electrodes, for example, the floating poly-Si145and the two gate electrodes150, may be formed in an upper inner portion of the gate trench130. The plurality of upper electrodes145and150may be divided into a first upper electrode145and a second upper electrode150. The first upper electrode145may be formed directly above, and spaced apart from, the source electrode140. Thus, a first inter-electrode insulating layer430may be formed between the source electrode140and the first upper electrode145. In a non-limiting example, the two second upper electrodes150may be formed in a same shape. However, this is only an example, and the two second upper electrodes150may be formed in respectively different shapes. In a plan view (not shown), the two second upper electrodes150are connected together. A second inter-electrode insulating layer450may also be formed between the first upper electrode145and the second upper electrode150, or the second upper electrodes150. The second inter-electrode insulating layer450may be formed by oxidizing the first upper electrode145. The second inter-electrode insulating layer450, which is disposed between the first upper electrode145and the second upper electrode150, may have a thickness that is thicker than a thickness of the gate insulating layer440formed on the upper sidewall of the gate trench130. This is because the first upper electrode145made of doped polysilicon may have a more rapid oxidation rate than an oxidation rate of the sidewall of the gate trench130. The sidewall of the gate trench130may be made of single crystal silicon (Si). Since the first upper electrode145may use the doped polysilicon, the first upper electrode145may have a much higher impurity concentration than an impurity concentration of the single crystal silicon (Si) region, and the second inter-electrode insulating layer450may be formed thicker due to the higher impurity concentration, or the like. FIG.2Bis an enlarged view of the upper portion ofFIG.2A. Referring toFIG.2B, there are several characteristics between the first upper electrode145and the second upper electrode or electrodes150. First, the first upper electrode145and the second upper electrode or electrodes150may be formed adjacent to each other, and in a non-limiting example, the second upper electrodes150may surround the first upper electrodes145. A width “a” of an upper region of the first upper electrode145may be less than a width “c” of an upper portion of the second upper electrodes150. However, this is only an example. A width of at least one of the second upper electrodes150may be different from a width of another of the second upper electrodes150, and a width “a” of an upper region of the first upper electrode145may be equal to or greater than a width “c” of one or more of the second upper electrodes150. On the basis of a surface of the substrate105, a depth of the first upper electrode145may be greater than a depth of the second upper electrodes150. The first upper electrode145may include a first region145-1and a second region145-2, and the first region145-1may be formed to overlap the second upper electrodes150in a horizontal direction. The second region145-2may be formed under the first region145-1, and may be formed to be disposed closer to the lower electrode or source electrode140than the first region145-1. A width “b” of the second region145-2may be greater than the width “a” of the first region145-1. However, this is only an example, and the width “b” may be less than, or equal to, the width “a” of the first region145-1. The width “a” of the first region145-1may be less than a width of the source electrode140. The cross-sectional area of the second upper electrodes150may be formed to be generally larger than the cross-sectional area of the first upper electrode145. The depth of the first upper electrode145may be formed to be greater than the depth of the P-type body region170based on the surface of the substrate105. On the other hand, the depth of the P-type body region170may be less than the depth of the first upper electrode145, and may be the same as the depth of the second upper electrode150. In an example, three electrodes145and150may be formed. The first upper electrode145may also be implemented as a gate electrode or may be floating to be a floating electrode without being connected to any terminal. The second upper electrodes150are provided at opposite ends of the upper region of the gate trench130. Additionally, the gate insulating layer440may be provided to surround each of the three electrodes145and150formed in the upper inner portion of the gate trench130. Accordingly, within the gate trench130, the source electrode140may be positioned below the first upper electrode145. In an example, the first upper electrode145may be coupled to both second upper electrodes150and may operate as a gate electrode. The source electrode140, the second upper electrodes150and the first upper electrode145may be spaced apart from each other by the sidewall insulating layer410, the first inter-electrode insulating layer430, the gate insulating layer440, and the second inter-electrode insulating layer450. The sidewall insulating layer410, the first inter-electrode insulating layer430, the gate insulating layer440, and the second inter-electrode insulating layer450may be connected to each other. In an example, the source electrode140, the second upper electrodes150, and first upper electrode145may be formed of doped polysilicon. The P-type body region170may be formed between, or adjacent to, the gate trenches130in a region adjacent to the second upper electrodes150. The P-type body region170may become a channel region. A pair of high concentration N-type source regions185may be formed in the P-type body region170. Further, a high concentration P-type region or a body contact region180may be formed in the P-type body region170. The body contact region180may be in contact with the source metal190and may have higher doping concentration than that of the p-type body region170. The body contact region180may reduce the contact resistance between the P-type body region170and the source metal190. In an example, drain metal (not shown) may be formed on the bottom surface of the substrate105. Thus, a current path may be formed in a vertical direction. When electrons are supplied through the source metal170, the electrons can pass through the N-type source region185and the P-type body region170, pass through the drift region120, and move to the drain metal through the drain region110. An interlayer insulating layer470may be formed on the first upper electrode145and the second upper electrodes150, and may be formed on the pair of high concentration N-type source regions185. The first upper electrode145and the second upper electrodes150may be electrically isolated from the source metal170by the interlayer insulating layer470. The sidewall insulating layer410, the first inter-electrode insulating layer430, the gate insulating layer440, the second inter-electrode insulating layer450, and the interlayer insulating layer470can be connected to each other. Compared to a structure in which the source electrode140is, as illustrated inFIG.1A, positioned between the gate electrodes150, or a structure in which the source electrode is positioned below a large gate electrode150, as illustrated inFIG.1B, the split gate trench MOSFET structure illustrated inFIGS.2A and2B, in accordance with an example, may have an advantage of reducing capacitance between the gate and the source. Generally, capacitance between two planar metals increases in proportion to the facing area of the metals, and decreases in inverse proportion to a distance between them. That is, when the distance between two planar metals is large and the facing area is small, the capacitance can be smaller (C=εS/d). The following Table 1 below illustrates the results of comparing the structure according to the one or more examples with the structure illustrated inFIGS.1A and1Bthrough simulation. TABLE 1DisclosedExamplesParameters(FIG. 2A)FIG. 1AFIG. 1BGate Charge Qg6.8 nC9.0 nC7.2 nCCapacitance Qgs between2.2 nC3.8 nC2.5 nCgate and sourceCapacitance Qgd between1.2 nC0.9 nC0.9 nCgate and drain Referring toFIGS.1A and1B, it can be seen that, in the example of the MOSFET which has a structure in accordance with one or more examples, a gate charge Qg is similar to a gate charge ofFIG.1Band is reduced to about 75% ofFIG.1A, and the capacitance Qgs between the gate and the source is similar to that ofFIG.1Band is significantly reduced to 58% ofFIG.1A. On the other hand, it can be seen that the capacitance Qgd between the gate and the drain increases by about 30%. FIG.3is a flowchart illustrating a method for forming the split gate trench MOSFET structure according to an example.FIGS.4A to4Killustrate schematically a shape of the split gate trench MOSFET formed in each operation of a manufacturing process thereof. Referring toFIGS.3and4A, an operation310forms the gate trench in the substrate. A semiconductor substrate105including the high concentration N-type drain region110is provided. The low concentration N-type epitaxial layer120is formed on the high concentration N-type drain region110. The low concentration N-type epitaxial layer120may be used as a drift region. According to various examples, the gate trench130may be formed in the low concentration N-type epitaxial layer120provided on the high concentration N-type drain region110. According to the example, the gate trench130may be formed by masking and etching portions other than a portion where the trench is to be formed on the top surface of the low concentration N-type epitaxial layer120. The depth of the trench may vary depending on a voltage implemented in the trench MOSFET. In a non-limiting example, the depth of the trench may be 5 um to 20 um, and the width of the trench may be 1 um to 4 um. The voltage implemented in the trench MOSFET may vary from 50 V to 1000V. Referring toFIGS.3and4B, an operation315forms the sidewall insulating layer410within the gate trench130, and deposits a first conductive layer420above the sidewall insulating layer410. The sidewall insulating layer410may be formed within the gate trench130, and the first conductive layer420may be deposited above and/or between the sidewall insulating layer410. In an example, the sidewall insulating layer410may be very thick, and may have a thickness of 100 nm to 1000 nm. The sidewall insulating layer410is deposited in a U-shape. The sidewall insulating layer410may be formed to have a sufficient thickness because the sidewall insulating layer410may become a space in which a gate electrode is formed later. In an example, the sidewall insulating layer410may be formed by a thermal oxidation method or a Low Pressure Chemical Vapor Deposition (LPCVD) method. Alternatively, first, a thermal oxide layer may be formed by processing the thermal oxidation method and additional deposition may be performed by the LPCVD method, so that the sidewall insulating layer410can be formed. After the sidewall insulating layer410is formed, the first conductive layer420may be deposited on/or between and the sidewall insulating layer410. In a non-limiting example, the first conductive layer420may be formed of doped polysilicon or a metal layer. Examples of the metal layer include, but are not limited to, W, Ti, Pt, Ta, Al, and Cu. Referring toFIGS.3and4C, an operation320forms the source electrode140in a lower portion of the gate trench130. The first conductive layer420deposited on and/or between the sidewall insulating layers410is etched to leave only a portion to be used as the source electrode140within the gate trench130. Referring toFIGS.3and4D, an operation325forms the inter-electrode insulating layer430over the source electrode140. Polysilicon implemented as the source electrode140may be oxidized to form the first inter-electrode insulating layer430over the source electrode140. The first inter-electrode insulating layer430may be referred to as an inter-poly insulating layer, an inter-poly oxide layer, an Inter-electrode oxide layer, or the like. In an example, the first inter-electrode insulating layer430may be formed by thermal oxidation in which a high temperature is applied to a semiconductor device. In an example, since the remaining portion of the gate trench130, other than the source electrode140, has been already covered with the insulating layer, additional oxidation does not proceed. However, the first inter-electrode insulating layer430can be formed only on the source electrode140. In an example, the thickness of the first inter-electrode insulating layer430may be between 100 nm and 500 nm, and preferably between 200 nm and 300 nm. Referring toFIGS.3and4E, an operation330forms the first upper electrode145. A second conductive layer (not shown) may be deposited on the sidewall insulating layer410and etched to form the first upper electrode145in the gate trench130. In an example, the second conductive layer may be formed of doped polysilicon or metal film, similarly to the first conductive layer. Examples of the metal layer include, but are not limited to, W, Ti, Pt, Ta, Al, and Cu. Thus, the first upper electrode145may be formed on the first inter-electrode insulating layer430over the source electrode140within the gate trench130. The height of the first upper electrode145may be almost similar to the height of the surface of the substrate. Referring toFIGS.3and4F, an operation335removes the sidewall insulating layer such that the sidewall of the gate trench130is exposed. The sidewall insulating layer410around the first upper electrode145formed within the gate trench130may be removed by performing wet etching. Accordingly, the sidewall of the gate trench130may be exposed. The wet etching may be a method of etching through a chemical reaction using a solution. In an example, a depth to which the insulating layer is removed may be less than or equal to the depth of the first upper electrode145. An empty space415may be formed by removing the sidewall insulating layer410in an area adjacent to the first upper electrode145, and the second upper electrodes150may be formed in the empty space415during a later operation. As a result of removing the sidewall insulating layer410on the upper portion of the gate trench130, a portion of the side surface of the first upper electrode145is exposed, and the remaining portion of the side surface of the first upper electrode is surrounded by the sidewall insulating layer410. A length “d” of the exposed portion of the first upper electrode145may be greater than a length of the unexposed portion of the first upper electrode145. The length “d” of the exposed portion of the first upper electrode145may be at least twice greater than the length of the unexposed portion of the first upper electrode145. In order not to collapse the first upper electrode, the remaining portion of the side surface of the first upper electrode145is surrounded by the sidewall insulation layer410. When the entire side surface of the first upper electrode145is exposed, the first upper electrode pattern may be collapsed down. Referring toFIGS.3and4G, an operation340forms the gate insulating layer440on the sidewall of the gate trench130. The thin gate insulating layer440can be formed by thermally oxidizing the exposed side surface of the first upper electrode145. As a result of operation340, as illustrated inFIG.4G, the gate insulating layer440may be formed on the sidewall of the gate trench130. Additionally, the thick second inter-electrode insulating layer450may be formed on the exposed surface of the first upper electrode145. The gate insulating layer440and the second inter-electrode insulating layer450may be formed simultaneously in the same operation. In the example of the first upper electrode145, the portion of the first upper electrode145originally surrounded by the sidewall insulating layer410may not be oxidized. However, the portion of the first upper electrode145that is not surrounded by the sidewall insulating layer410is thermally oxidized, so that the second inter-electrode insulating layer450is formed on the side surface and the top surface of the first upper electrode145. The exposed surface of the first upper electrode145is thermally oxidized to form the second inter-electrode insulating layer450. The surface of the first region145-1of the first upper electrode145is oxidized. On the other hand, the second region145-2of the first upper electrode145remains as it is. Thus, the thickness or width of the upper portion of the first upper electrode145is reduced overall. In an example, if the first upper electrode145is divided into the first region145-1that is an upper region thereof and the second region145-2that is a lower region thereof, the second region145-2is formed under the first region145-1. Additionally, the second region145-2may be formed closer to the lower electrode140than the first region145-1. The second region145-2may be formed to have a width that is larger than a width of the first region145-1. The first region145-1may be a region in which the surface of the first upper electrode145has been oxidized, while the second region145-2may be a region in which the surface of the first upper electrode145is not oxidized. Therefore, while the width of the second region145-2is maintained, the width of first region145-1is reduced by the surface oxidation. The width of the second region145-2of the first upper electrode145may be similar to the width of the lower electrode140. On the other hand, the width of the first region145-1of the first upper electrode145may be less than the width of the lower electrode140. Referring toFIGS.3and4H, an operation345deposits a third conductive layer on the gate insulating layer440and etches the third conductive layer, so that the second upper electrodes150are formed in parallel with the side of the first upper electrode145. In order to form the second upper electrodes150, the third conductive layer (not shown) is deposited on the gate insulating layer440and the second inter-electrode insulating layer450. Doped polysilicon or metal layer can be deposited on the third conductive layer. An empty space415(seeFIG.4G) may be formed in a region adjacent to the first upper electrode145within the gate trench130by the above operations. The empty space415is filled by the third polysilicon and then, performing an etch-back process. The second upper electrodes150may be formed on the gate insulating layer440and the second inter-electrode insulating layer450. The etch-back process can be replaced by chemical-mechanical processing (CMP). In an example, the second upper electrodes150and the first upper electrode145may be insulated from each other by the second inter-electrode insulating layer450formed in operation340. Regarding the structural characteristics of the first upper electrode145and the second upper electrodes150, the width of the first upper electrode145may be less than the width of each of the second upper electrodes150. On the basis of the surface of the substrate, the depth of the first upper electrode145may be greater than the depth of the second upper electrodes150. The second upper electrodes150may be formed adjacent to the side surface of the first upper electrodes150, and may surround the first upper electrode145. The first upper electrode145may be electrically connected to the second upper electrodes150and can be used as a gate electrode. The cross-sectional area of the second upper electrodes150may be formed to be larger than the cross-sectional area of the first upper electrode145. The formation of a gate module having the split gate structure within the gate trench130can be completed by the above-described operations. Then, an operation of connecting the source metal may additionally be carried out. Referring toFIGS.3and4I, an operation350forms the body region, the source region, and the interlayer insulating layer on the substrate. First, before forming the interlayer insulating layer, the P-type body region170and the high concentration N-type source region185may be formed between the gate trench130in which the gate module has been formed. For this purpose, the P-type body region170may be formed deep by implanting a P-type dopant into the substrate. Then, the high concentration N-type source region185may be formed by implanting an N-type dopant into the P-type body region170. Then, the interlayer insulating layer470may be formed over the entire top surface. The interlayer insulating layer470may be implemented for subsequent isolation between the gate module and the source metal. The interlayer insulating layer470may be formed on the respective first and second upper electrodes145and150. The source metal190and the first and second upper electrodes145and150may be electrically isolated by the interlayer insulating layer470. Referring toFIGS.3and4J, an operation355etches the interlayer insulating layer470to form a contact hole480. A contact hole480, which reaches the P-type body region170, may be formed by etching the interlayer insulating layer470and the high concentration N-type source region185. Further, the high concentration P-type region180which has a higher concentration than a concentration of the p-type body region170, may be formed at the end of the contact hole480. The high concentration P-type region180may become the body contact region. As a result of operation355, the high concentration P-type region180may be formed in a portion of the P-type body region170, which is in contact with the contact hole. Additionally, the high concentration N-type source region185may be cut by the contact hole, so that only the tops of both end surfaces of the P-type body region170remain, and as a result, a pair of high concentration N-type source regions185can be formed. On the basis of the surface of the substrate, a position of the high concentration N-type source region185may be higher than a position of the high concentration P-type region180. Referring toFIGS.3and4K, an operation360forms the source metal190on the interlayer insulating layer470. The source metal190may be formed on the interlayer insulating layer470and within the contact hole480by depositing a metallic material. The metallic material may include, but is not limited to, Al, W, Cu or the like. The source metal190may be in contact with the high concentration P-type region180and the high concentration N-type source region185through the contact hole. The source metal190may be electrically connected to the source electrode140. Additionally, the source metal190may be in direct physical contact with the P-type body region170, the body contact region180, and the high concentration N-type source region185. On the other hand, drain metal (not shown) may be formed on the bottom surface of the substrate. Thus, a current path may be formed in a vertical direction. When electrons are supplied through the source metal170, the electrons can pass through the N-type source region185and the P-type body region170, pass through the drift region120, and move to the drain metal through the drain region110. The foregoing description can be summarized as follows. Additionally, it will be understood by those skilled in the art that various changes and modifications of the following description can be made therein without departing from the spirit and scope of the examples. According to various examples, the trench MOSFET manufacturing method includes forming a gate trench in a substrate, forming a sidewall insulating layer within the gate trench, forming a source electrode in a lower portion of the gate trench by depositing a first conductive layer on the sidewall insulating layer and etching, forming a first inter-electrode insulating layer over the source electrode, forming a first upper electrode by depositing a second conductive layer on the first inter-electrode insulating layer and etching, removing the sidewall insulating layer so as to expose a sidewall of the gate trench, forming a gate insulating layer between the sidewall of the gate trench and the first upper electrode, and forming, by depositing a third conductive layer on the gate insulating layer and etching, a second upper electrode which is formed in parallel to a side of the first upper electrode. According to various examples, the method may further include forming a body region on the substrate and forming a source region on the body region, forming an interlayer insulating layer on the source region and on the gate trench, and forming source metal on the interlayer insulating layer. According to various examples, the removing of the sidewall insulating layer so as to expose the sidewall of the gate trench includes removing the sidewall insulating layer such that a portion of the sidewall of the gate trench and a portion of a side of the first upper electrode are exposed and the remaining side of the first upper electrode is surrounded by the sidewall insulating layer. According to various examples, a width of the first upper electrode is less than a width of the second upper electrode, and a depth of the first upper electrode from a surface of the substrate is greater than a depth of the second upper electrode from the surface of the substrate. According to various examples, the first upper electrode includes a first region and a second region. The first region is formed to overlap the second upper electrode in a horizontal direction. The second region is formed under the first region and is formed closer to the source electrode than the first region. A width of the second region is greater than a width of the first region. According to various examples, the method may further include forming a second inter-electrode insulating layer on a surface of the first upper electrode. A thickness of the second inter-electrode insulating layer is larger than a thickness of the gate insulating layer. According to various examples, the trench MOSFET may include a substrate, a gate trench formed on the substrate, a sidewall insulating layer formed on a sidewall of the gate trench, a source electrode which is surrounded by the sidewall insulating layer, a first upper electrode which is provided above the source electrode, a first inter-electrode insulating layer which is formed between the source electrode and the first upper electrode, a second upper electrode which is formed adjacent to a side of the first upper electrode and surrounds the first upper electrode, and an interlayer insulating layer which is formed on the first upper electrode and the second upper electrode. According to various examples, the trench MOSFET may further include a body region which is formed on the substrate, a high concentration source region and a high concentration contact region which are formed in the body region, and a source metal which is provided on the interlayer insulating layer and is in contact with the body region. According to various examples, the first upper electrode is electrically connected to the second upper electrode and is used as a gate electrode. According to various examples, the trench MOSFET may further include a gate insulating layer formed on an upper sidewall of the gate trench. The sidewall insulating layer, the first inter-electrode insulating layer, the gate insulating layer, and the interlayer insulating layer are connected to each other. According to various examples, a width of the first upper electrode is less than a width of the second upper electrode and a depth of the first upper electrode from a surface of the substrate is greater than a depth of the second upper electrode from the surface of the substrate. According to various examples, the first upper electrode includes a first region and a second region. The first region is formed to overlap the second upper electrode in a horizontal direction. The second region is formed under the first region and is formed closer to a lower electrode than the first region. A width of the second region is greater than a width of the first region. According to various examples, the trench MOSFET may include a substrate; a body region which is formed on the substrate; a source region in the body region; a gate trench formed on the substrate; one lower electrode formed in a lower portion of the gate trench; a plurality of upper electrodes formed above the one lower electrode. The plurality of upper electrodes includes: a first upper electrode which is formed to overlap the lower electrode; and a second upper electrode which surrounds the first upper electrode, a first inter-electrode insulating layer which is formed between the lower electrode and the first upper electrode; a gate insulating layer formed on a sidewall of the gate trench; an interlayer insulating layer formed on the plurality of upper electrodes; and a source metal which is provided on the interlayer insulating layer and is in contact with the body region. According to various examples, the first upper electrode and the second upper electrode may be implemented as a gate electrode. According to various examples, a cross-sectional area of the second upper electrode is greater than a cross-sectional area of the first upper electrode. According to various examples, the trench MOSFET may further include a sidewall insulating layer which surrounds the lower electrode. A width of the sidewall insulating layer is larger than a width of a source electrode. According to various examples, a depth of the first upper electrode from a surface of the substrate is greater than a depth of the body region from the surface of the substrate. According to various examples, the trench MOSFET may further include a second inter-electrode insulating layer formed between the first upper electrode and the second upper electrode. A thickness of the second inter-electrode insulating layer is larger than a thickness of the gate insulating layer. According to various examples, the first upper electrode includes a first region and a second region. The first region is formed to overlap the second upper electrode in a horizontal direction. The second region is formed under the first region and is formed closer to the lower electrode than the first region. A width of the first region of the first upper electrode is less than a width of the lower electrode. As described above, the example structure may be formed by implementing operations325and330as illustrated inFIG.3in the compared manufacturing process. Accordingly, the example structure simplifies the manufacturing process, and reduces the capacitance formed between the gate electrode and the source electrode than typical structures. | 42,273 |
11862696 | DETAILED DESCRIPTION Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. A semiconductor storage device relating to one embodiment includes: a stacked body in which electrode films and insulating films are alternately stacked in a first direction; a first and a second charge storage films that are arranged away from each other in the first direction inside the stacked body and each face one of the electrode films; and a tunnel insulating film that extends in the first direction inside the stacked body and is in contact with the first and the second charge storage films. The first and the second charge storage films each include a first film that is in contact with the electrode film and contains a High-k material, and a second film that is provided between the first film and the tunnel insulating film and contains silicon nitride. First Embodiment FIG.1is a perspective view illustrating a structure of a main part of the semiconductor storage device relating to the first embodiment. A semiconductor storage device1illustrated inFIG.1includes a substrate10, a laminated (stacked) body20, and a plurality of semiconductor films30. In the following description, two directions that are the direction parallel to the substrate10and are orthogonal to each other are defined as an X direction and a Y direction. In addition, the direction that is vertical to the substrate10and are orthogonal to the X direction and the Y direction is defined as a Z direction. The Z direction is also the first direction of the laminated body20. The substrate10is a silicon substrate for example. On the substrate10, the laminated body20is provided. Note that, between the substrate10and the laminated body20, a layer including a drive element such as a transistor used to drive the semiconductor films30or a layer where wiring used to drive the semiconductor films30is formed may be formed. The laminated body20includes an SGD21, a cell22and an SGS23. The SGD21is positioned in a top layer of the laminated body20, and includes a plurality of drain side selection gate electrodes. The SGS23is positioned in a bottom layer of the laminated body20, and includes a plurality of source side selection gate electrodes. The cell22is positioned between the SGD21and the SGS23, and includes a plurality of word lines. The plurality of semiconductor films30are arranged zigzag in the X direction and the Y direction. In addition, each semiconductor film30extends in the Z direction inside the laminated body20. FIG.2is a drawing illustrating part of a cross section along a cutting line A-A illustrated inFIG.1. Here, structures of the cell22and the semiconductor film30will be described with reference toFIG.2. First, the structure of the cell22will be described. As illustrated inFIG.2, in the cell22, a plurality of electrode films201in a planar shape and a plurality of interlayer insulating films202are alternately laminated in the Z direction. The electrode film201includes a metal film211, a barrier metal film212, a block insulating film213, and a block insulating film214. The metal film211contains a metal such as tungsten (W), and functions as the word line. The barrier metal film212contains titanium nitride (TiN) for example, and covers the metal film211in order to prevent diffusion of the metal contained in the metal film211. The block insulating film213contains aluminum oxide (Al2O3) for example, and covers the barrier metal film212. The block insulating film214contains silicon oxide (SiO2) for example, and covers the block insulating film213. On the other hand, the interlayer insulating film202contains the silicon oxide. By the interlayer insulating films202, the plurality of electrode films201are electrically insulated from each other. Note that the SGD21is provided with the drain side selection gate electrodes having the structure similar to the electrode film201. In addition, the SGS23is also provided with the source side selection gate electrodes having the structure similar to the electrode film201. Next, the structure of the semiconductor film30will be described. The semiconductor film30illustrated inFIG.2includes a block insulating film31, charge storage films32a, charge storage films32b, a tunnel insulating film33, a channel film34, and a core film35. The block insulating film31, the charge storage films32a, the charge storage films32band the tunnel insulating film33are examples of a memory film. The block insulating film31is a cylindrical film containing the silicon oxide for example, and is alternately laminated with the charge storage films32bin the Z direction in the cell22. By the laminated structure, the block insulating film31is interposed between the charge storage films32b. Therefore, the individual charge storage films32bare arranged apart holding the block insulating film31therebetween. Each charge storage film32ais an example of the cylindrical first film containing the High-k material. The charge storage films32aare arranged apart in the Z direction holding the interlayer insulating films202therebetween and face the electrode films201. The charge storage film32bis an example of the cylindrical second film containing the silicon nitride (SiN). The charge storage film32bis provided between the charge storage film32aand the tunnel insulating film33. In addition, a width (length) in the Z direction of the charge storage film32aand the charge storage film32bis greater than a width (length) in the Z direction of the metal film211. The tunnel insulating film33is a cylindrical film in contact with the block insulating film31and the charge storage films32b. The tunnel insulating film33contains silicon oxide for example. The channel film34is a cylindrical film provided between the tunnel insulating film33and the core film35. The channel film34contains polysilicon. The core film35is a columnar film containing the silicon oxide for example. In the semiconductor storage device1relating to the present embodiment, an intersection of the semiconductor film30and each electrode film201is a vertical transistor. Of the vertical transistor, an intersection of the metal film211(word line) of the cell22and the semiconductor film30is a memory cell. Note that an intersection of the drain side selection gate electrode of the SGD21and the semiconductor film30is a drain side selection transistor. In addition, an intersection of the source side selection gate electrode of the SGS23and the semiconductor film30is a source side selection transistor. The drain side selection transistor, the memory cell and the source side selection transistor are connected in series. Hereinafter, with reference toFIGS.3-9, a manufacturing process of the semiconductor storage device relating to the present embodiment will be described. Here, the manufacturing process of the cell22will be described in detail. First, as illustrated inFIG.3, a laminated body22ais formed on the substrate10(not illustrated inFIG.3). In the laminated body22a, a plurality of sacrifice films201ain the planar shape and the plurality of interlayer insulating films202are alternately laminated in the Z direction. The sacrifice films201acontain the silicon nitride for example. The laminated body22acan be formed by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) for example. Next, as illustrated inFIG.4, a hole300penetrating the laminated body22ain the Z direction is formed. The hole300is formed at an arrangement location of the semiconductor film30described above. The hole300can be formed by RIE (Reactive Ion Etching) for example. Then, as illustrated inFIG.5, a semiconductor film30ais formed inside the hole300. Specifically, the block insulating film31, a dummy film36, the tunnel insulating film33, the channel film34and the core film35are consecutively formed in the order. The dummy film36contains the polysilicon, for example. For the dummy film36and the channel film34, for example, an amorphous silicon film is formed under a low temperature condition of about 500° C. and then heat treatment of 800° C. or higher is executed. Thus, silicon contained in the dummy film36and the channel film34is polycrystallized. Note that the heat treatment of the dummy film36may be performed simultaneously with the heat treatment of the channel film34. Next, as illustrated inFIG.6, the sacrifice films201aare removed, and an exposed part of the block insulating film31exposed by removing the sacrifice films201ais removed. The sacrifice films201acan be removed by wet etching using a liquid chemical containing phosphoric acid for example. On the other hand, the block insulating film31can be removed by wet etching using a liquid chemical containing hydrofluoric acid for example. By removing part of the block insulating film31in this way, a part of the dummy film36is exposed. Then, as illustrated inFIG.7, the charge storage films32bare formed at the exposed parts of the dummy film36. Specifically, first of all, the polysilicon contained in the dummy film36is subjected to radical nitriding or thermal nitriding. Therefore, the exposed parts of the dummy film36are changed into a silicon nitride film. Consecutively, the silicon nitride film is increased by a thickness of the block insulating film31. Thus, the charge storage films32bare completed. As a method of selectively increasing the silicon nitride film, for example, low pressure vapor phase growth (LPCVD) or the ALD is used, and an incubation time difference or a selective growth method can be utilized. Next, as illustrated inFIG.8, metal films37are selectively formed on the charge storage films32busing sputtering for example. The metal films37contain, for example, metallic elements of hafnium (Hf), aluminum (Al), titanium (Ti), barium (Ba), ruthenium (Ru), lanthanum (La), zirconium (Zr), iodine (Y), magnesium (Mg), tantalum (Ta), strontium (Sr), and niobium (Nb), or a metal compound configured from two or more of the metallic elements. Then, as illustrated inFIG.9, by subjecting the metal films37to radical oxidation, the charge storage films32aare formed. At the time, the polysilicon remaining in the dummy film36without being nitrided when forming the charge storage films32bis oxidized and silicon oxide films36aare also formed. The silicon oxide films36aare integrated with the block insulating film31containing the silicon oxide. By formation of the silicon oxide films36a, a route through which electric charges move in the Z direction between the charge storage films32bthrough the dummy film36can be divided. The charge storage films32acontain the High-k material in which the metallic element contained in the metal films37is oxidized. The High-k material is, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), barium oxide (BaO), ruthenium tetroxide (RuO4), lanthanum oxide (La2O3), zirconium oxide (ZrO2), iodine oxide (Y2O3), magnesium oxide (MgO), tantalum oxide (Ta2O5), strontium oxide (SrO) or niobium oxide (Nb2O5). In order to make the electric charges retained in the charge storage films32adifficult to move, for the charge storage films32a, a material of a barrier height lower than that of the material of the charge storage films32b, that is the silicon nitride, is preferably used. As such a material, specifically, the hafnium oxide, the zirconium oxide, the iodine oxide, the tantalum oxide and strontium titanate (SrTiO3) are relevant. Note that the High-k material may be oxynitride such as aluminum oxynitride (AlON), hafnium oxynitride (HfON), titanium oxynitride (TiON) or zirconium oxynitride (ZrON). In addition, the High-k material may be a mixture of metal oxides of different valences like the aluminum, the iodine and the lanthanum added to the metal oxide such as the titanium oxide, the hafnium oxide or the zirconium oxide or the titanium, the hafnium and the zirconium added to the metal oxide such as the tantalum oxide or the niobium oxide. After the charge storage films32aare formed as described above, at removed parts of the sacrifice films201a, the block insulating film214, the block insulating film213, the barrier metal film212and the metal film211are formed in the order. The films can be formed by the CVD or the ALD for example. As a result, the cell22illustrated inFIG.2is completed. According to the present embodiment described above, the moving route of the electric charges in the Z direction between the charge storage films32ais divided by the interlayer insulating films202. In addition, the moving route of the electric charges in the Z direction between the charge storage films32bis also divided by the block insulating films31(and the silicon oxide films36a). Thus, movement of the electric charges retained in the charge storage films32aand the charge storage films32bis limited so that a charge retention characteristic can be improved. In addition, in the present embodiment, since the High-k material is contained in the charge storage films32a, a charge trap performance is improved. Thus, a data write characteristic can be also improved. Further, the width in the Z direction of the charge storage film32aand the charge storage film32bis greater than the width in the Z direction of the metal film211. Thus, compared to a case where the widths in the Z direction of the charge storage films and the metal film are about the same, reduction of a tunnel current can be suppressed and an erasing characteristic can be improved. (Modification 1) FIG.10is a cross sectional view of a cell of a semiconductor storage device relating to the modification of the first embodiment. Same signs are attached to components similar to that of the first embodiment described above, and detailed description is omitted. In a semiconductor storage device1aillustrated inFIG.10, part of the dummy film36remains inside the block insulating film31. The part is a polysilicon film remaining without being oxidized when forming the charge storage films32a(seeFIGS.8and9). In the present modification, the dummy film36remaining without being oxidized is covered with the block insulating film31as illustrated inFIG.10, thereby being away from the charge storage films32b. Therefore, the charge storage films32bfacing each other in the Z direction are not connected through the dummy film36so that the movement in the Z direction of the electric charges retained in the charge storage films32bcan be limited. Thus, the charge retention characteristic can be improved also in the present modification. In addition, in the present modification, since there is no need to completely oxidize the dummy film36, oxidation time of the dummy film36can be shortened. Second Embodiment FIG.11is a cross sectional view of a cell of a semiconductor storage device relating to the second embodiment. The same signs are attached to the components similar to that of the first embodiment described above, and the detailed description is omitted. A semiconductor storage device2relating to the present embodiment is different from the first embodiment at a point of further including an oxide film32cbetween the charge storage film32aand the charge storage film32b. The oxide film32ccontains the silicon oxide. In addition, the width in the Z direction of the charge storage film32a, the charge storage film32band the oxide film32cis greater than the width in the Z direction of the metal film211. Hereinafter, with reference toFIGS.12-14, the manufacturing process of the semiconductor storage device2relating to the present embodiment will be described. However, since the process from formation of the laminated body22ato formation of the charge storage films32bis similar to the first embodiment, the description is omitted. After forming the charge storage films32b, a surface of the charge storage films32bis subjected to the radical oxidation. As a result, as illustrated inFIG.12, the oxide films32care formed on the charge storage films32b. At the time, the polysilicon remaining in the dummy film36without being nitrided when forming the charge storage films32bis also oxidized and silicon oxide films36aare formed. Next, as illustrated inFIG.13, the metal films37are selectively formed on the oxide films32c. Since a forming method of the metal films37and the material of the metal films37are similar to the first embodiment, the description is omitted. Then, as illustrated inFIG.14, by subjecting the metal films37to the radical oxidation, the charge storage films32aare formed. Since the material of the charge storage films32ais similar to the first embodiment, the description is omitted. Note that, the dummy film36is oxidized simultaneously with the formation of the oxide films32cin the present embodiment, but may be oxidized simultaneously with the formation of the charge storage films32a(the radical oxidation of the metal films37). Thereafter, similarly to the first embodiment, at the removed parts of the sacrifice films201a, the block insulating film214, the block insulating film213, the barrier metal film212and the metal film211are formed in the order. As a result, the cell22illustrated inFIG.11is completed. According to the present embodiment described above, the oxide film32cis provided between the charge storage film32aand the charge storage film32b. Therefore, the movement to the side of the charge storage film32bof the electric charges retained in the charge storage film32acan be limited by the oxide film32c. Thus, the charge retention characteristic can be further improved. Third Embodiment FIG.15is a cross sectional view of a cell of a semiconductor storage device relating to the third embodiment. The same signs are attached to the components similar to that of the first embodiment described above, and the detailed description is omitted. In a semiconductor storage device3relating to the present embodiment, the charge storage films32acover the electrode films201. That is, the charge storage films32aare provided not only between the electrode films201and the charge storage films32bbut also between the electrode films201and the interlayer insulating films202. In addition, similarly to the first embodiment, the width in the Z direction of the charge storage film32aand the charge storage film32bis greater than the width in the Z direction of the metal film211. Hereinafter, with reference toFIG.16andFIG.17, the manufacturing process of the semiconductor storage device3relating to the present embodiment will be described. However, since the process from the formation of the laminated body22ato the formation of the charge storage films32bis similar to the first embodiment, the description is omitted. In the present embodiment, after forming the charge storage films32b, as illustrated inFIG.16, the metal films37are formed by the CVD or the ALD for example. At the time, the metal films37are formed not only on the charge storage films32bbut also on the interlayer insulating films202. That is, the metal films37are formed entirely on the surfaces exposed by removing the sacrifice films201a. Next, as illustrated inFIG.17, by subjecting the metal films37to the radical oxidation similarly to the first embodiment, the charge storage films32aare formed. In this way, the charge storage films32aare formed both on the charge storage films32band on the interlayer insulating films202. In addition, similarly to the first embodiment, when forming the charge storage films32a, the polysilicon remaining in the dummy film36is oxidized and the silicon oxide films36aare also formed. Thereafter, similarly to the first embodiment, at the removed parts of the sacrifice films201a, the block insulating film214, the block insulating film213, the barrier metal film212and the metal film211are formed in the order. As a result, the cell22illustrated inFIG.15is completed. According to the present embodiment described above, since the charge storage films32aare formed entirely at the removed parts of the sacrifice films201a, the need of selectively forming the charge storage films32a(the metal films37) on the charge storage films32bis eliminated. In addition, the charge storage films32aprovided on an upper surface and a lower surface of the electrode films201are divided from the other charge storage films32afacing in the Z direction by the interlayer insulating films202. Thus, the charge retention characteristic can be improved by an easy film formation process. Fourth Embodiment FIG.18is a cross sectional view of a cell of a semiconductor storage device relating to the fourth embodiment. The same signs are attached to the components similar to that of the first embodiment described above, and the detailed description is omitted. In the first embodiment-the third embodiment described above, a film that retains the electric charges has a two-layer structure including the charge storage film32aand the charge storage film32b. On the other hand, in the semiconductor storage device4relating to the present embodiment, the film that retains the electric charges has a single-layer structure of only the charge storage film32a. In the present embodiment, while an outer surface of the charge storage film32ais in contact with the electrode film201, an inner surface of the charge storage film32ais in contact with the block insulating film31. That is, part of the block insulating film31is interposed between the charge storage film32aand the tunnel insulating film33. In addition, the width in the Z direction of the charge storage film32ais greater than the width in the Z direction of the metal film211. Hereinafter, with reference toFIG.19andFIG.20, the manufacturing process of the semiconductor storage device4relating to the present embodiment will be described. However, since the process from the formation of the laminated body22ato removal of the sacrifice films201aand the exposed part of the block insulating film31is similar to the first embodiment, the description is omitted. In the present embodiment, as illustrated inFIG.19, the metal films37are selectively formed at the removed part of the block insulating film31, which is on the dummy film36, by sputtering for example. Next, as illustrated inFIG.20, by subjecting the metal films37to the radical oxidation similarly to the first embodiment, the charge storage films32aare formed. At the time, the polysilicon contained in the dummy film36is also oxidized and the silicon oxide films36aare formed. Part of the silicon oxide films36ais interposed between the charge storage film32aand the tunnel insulating film33. Thereafter, at the removed parts of the sacrifice films201a, the block insulating film214, the block insulating film213, the barrier metal film212and the metal film211are formed in the order. Thus, the cell22illustrated inFIG.18is completed. In the cell22, the block insulating film31is provided between the charge storage films32afacing each other in the Z direction. Therefore, the movement in the first direction of the electric charges retained in the charge storage films32acan be limited. In addition, according to the present embodiment, since the charge storage films32ahave a monolayer structure, film formation time of the charge storage films can be shortened compared to the two-layer structure. Fifth Embodiment FIG.21is a cross sectional view of a cell of a semiconductor storage device relating to the fifth embodiment. The same signs are attached to the components similar to that of the first embodiment described above, and the detailed description is omitted. While the film that retains the electric charges is only the charge storage film32ain the fourth embodiment described above, the film that retains the electric charges is only the charge storage film32bin a semiconductor storage device5relating to the present embodiment. In the present embodiment, the charge storage film32bis provided between the block insulating film214and the tunnel insulating film33. In addition, between the charge storage films32bfacing each other in the Z direction, the block insulating film31is provided. Further, the width in the Z direction of the charge storage film32bis greater than the width in the Z direction of the metal film211. Hereinafter, with reference toFIG.22andFIG.23, the manufacturing process of the semiconductor storage device5relating to the present embodiment will be described. However, since the process from the formation of the laminated body22ato the formation of the charge storage films32bis similar to the first embodiment, the description is omitted. Note that, the charge storage films32bcan be formed by increasing the silicon nitride film in which the polysilicon contained in the dummy film36is subjected to the radical nitriding or thermal nitriding, by the thickness of the block insulating film31. Note that, to the charge storage films32b, impurities may be introduced. The impurities include, for example, one element or two or more elements of hafnium, aluminum, titanium, barium, ruthenium, lanthanum, zirconium, iodine, magnesium, tungsten, strontium, niobium, oxygen, carbon, boron, and fluorine. For example, when a gas containing the impurities described above is introduced at the time of nitriding the polysilicon or at the time of increasing the silicon nitride film, the impurities can be contained in the charge storage films32b. Next, the surface of the charge storage film32bis subjected to the radical oxidation. As a result, as illustrated inFIG.23, the oxide films38are formed on the charge storage films32b. The oxide films38correspond to part of the block insulating film214. In addition, when forming the oxide films38, the polysilicon of the dummy film36not nitrided when forming the charge storage films32bis oxidized and the silicon oxide films36aare also formed. The silicon oxide films36aare integrated with the block insulating film31containing the silicon oxide. Thereafter, at the removed parts of the sacrifice films201a, the block insulating film214, the block insulating film213, the barrier metal film212and the metal film211are formed in the order. Thus, the cell22illustrated inFIG.21is completed. In the cell22, the charge storage films32bfacing each other in the Z direction are separated by the block insulating film31. Therefore, the movement in the first direction of the electric charges retained in the charge storage films32bcan be limited. In addition, according to the present embodiment, since the charge storage film32bhas the monolayer structure, the film formation time of the charge storage film can be shortened compared to the two-layer structure. (Modification 2) FIG.24is a cross sectional view of a cell of a semiconductor storage device relating to the modification of the fifth embodiment. The same signs are attached to the components similar to that of the fifth embodiment described above, and the detailed description is omitted. In a semiconductor storage device5aillustrated inFIG.24, part of the dummy film36remains inside the block insulating film31. The part is the polysilicon film remaining without being oxidized when forming the oxide films38(seeFIG.23). In the present modification, the dummy film36remaining without being oxidized is covered with the block insulating film31as illustrated inFIG.24, thereby being away from the charge storage films32b. Therefore, the charge storage films32bfacing each other in the Z direction are not connected through the dummy film36so that the movement in the Z direction of the electric charges retained in the charge storage films32bcan be limited. Thus, the charge retention characteristic can be improved also in the present modification. In addition, in the present modification, since there is no need to completely oxidize the dummy film36, the oxidation time of the dummy film36can be shortened. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 28,547 |
11862697 | REFERENCE SIGNS OF THE ELEMENTS Substrate:100; active region: AA; trench:101; isolation structure:110; first isolation layer:111; second isolation layer:112; third isolation layer:113; protective layer:130; isolation layer:140; gate structure:120; dielectric layer:121; metal nitride layer:122; first conductive layer:123; polysilicon layer:124; epitaxial layer:102; height of the gate conductive layer: H1; width of the gate conductive layer: W1; and width of the active region on a side of the trench: W2. DETAILED DESCRIPTION When the width of the trench is reduced to a certain extent, it is hard to fill the gate structure in the trench. Meanwhile, while the width of the trench is reduced, the width of the gate structure is reduced, which results in that the resistance of the gate conductive layer is increased and the electrical performance of the transistor is decreased. For the ease of understanding the disclosure, the disclosure is described more completely with reference to related accompanying drawings. Preferred examples of the disclosure are given in the accompanying drawings. However, the disclosure may be implemented in many different forms and is not limited to the examples described herein. Conversely, these examples are provided to make the disclosures of the disclosure more thoroughly and completely. Unless otherwise defined, all technical and scientific terms used in the specification have a same meaning generally understood by a person skilled in the art to which the disclosure belongs. The terms used in the specification of the disclosure are merely to describe the specific examples, rather than to limit the disclosure. The term “and/or” used herein includes one or any or all possible combinations of multiple associated items that are listed. In the conventional art, as shown inFIG.1, the process for forming the buried gate on the substrate100′ includes that: a trench is provided on the substrate100′, a gate structure110′ is filled in a bottom of the trench, and then an isolation layer140′ is directly deposited to fully fill the trench above the gate structure110′. For the buried gate formed in the conventional art, the gate conductive layer has a width of W1′, and a height of H1′. According to the resistance formula R=ρ*L/(W*H), the resistance of the gate conductive layer is inversely proportional to the width of the gate conductive layer. Therefore, the narrower the opening of the trench, and the narrower the gate conductive layer, thereby the larger the resistance. In view of this, the disclosure relates to a method for manufacturing a buried gate. The method for manufacturing the buried gate may at least include the following several steps. A trench is provided on an active region of a substrate. A gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed. An epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, which does not close the trench. An isolation layer is filled in the trench. According to the method for manufacturing the buried gate, the trench is provided on the substrate, the trench may be divided into a bottom trench and a top trench that are communicated to each other, and the gate structure is filled in the bottom groove but not in the top groove, such that the top trench sidewall is exposed, and the epitaxial layer is grown on the top trench sidewall with an epitaxial growth technique. In the disclosure, the trench having an opening with a large width may be first provided on the substrate, in which the gate structure is filled; and after the gate structure is filled, the epitaxial layer is grown on the top trench sidewall with the epitaxial growth technique. The width of the active region at each of two sides of the gate structure is increased by the epitaxial layer. In the disclosure, the trench having the large opening is first provided in which the gate structure is filled, and then the width of the opening of the trench above the gate structure is reduced by the epitaxial growth technique. Compared with the conventional art in which the trench having a small opening is directly provided, when area of the active region on each of the two sides of the trench are unchanged, and the depth of the trench and the length of the trench are unchanged, the width of the buried gate formed in the disclosure is increased, i.e., the width of the gate conductive layer is increased, and the resistance of the gate conductive layer is reduced, such that the manufactured buried gate has good electrical performance. The method for manufacturing the buried gate in the disclosure will be described below in detail with specific examples. As shown inFIG.2, the method for manufacturing the buried gate in the disclosure may include the following steps. In Step S100: a trench is provided on an active region of a substrate. As shown inFIG.3andFIG.4a,FIG.4ais a side sectional view along a BB′ section line inFIG.3. The active region AA is defined on the substrate100, and the trench101is provided on the active region AA. Specifically, there may be one trench101, and may also be multiple parallel trenches101, which may have the same size or different sizes. The trench101in the active region AA may extend along a direction parallel to a surface of the substrate100(a length direction of the trench) to two sides to penetrate through the active region AA. The substrate100may be one of a silicon wafer, a germanium wafer, a silicon-on-insulator (SOI) wafer, a germanium-on-insulator (GOI) wafer, a silicon-germanium wafer and a substrate formed with an epitaxial layer102. In this example, the substrate100uses the silicon wafer. Specifically, the trench is provided on the substrate100, which may be implemented by first forming a mask layer on the substrate100, defining an etching pattern with the mask layer, and then etching the substrate100by an etching process to provide the trench. The mask layer may be a hard mask, and may specifically use silicon nitride or silicon oxide. Specifically, the trench may be formed with a self-aligned quadruple patterning (SAQP) process. With the technique of SAQP, the small-sized structure may be obtained. In an example, an isolation structure110is further formed on the substrate100. The isolation structure110is formed by filling a dielectric layer in an isolation trench. Adjacent active regions AA are electrically isolated by the isolation structure110. Specifically, before Step S100, the isolation structure110may be formed on the substrate100and the active region AA may be defined by the isolation structure110. The isolation structure110may be the silicon nitride or the silicon oxide, and may also be a composite structure of the silicon nitride and the silicon oxide. In the example, the isolation structure110includes a first isolation layer111formed on an inner wall of the isolation trench, a second isolation layer112covering the first isolation layer111and a third isolation layer113covering the second isolation layer112and fully filling the isolation trench. The first isolation layer111and the third isolation layer113may be silicon oxide, the second isolation layer112may be silicon nitride, and thus the isolation structure110is of a silicon oxide-silicon nitride-silicon oxide composite isolation structure. In an example, while the trench is provided on the active region AA, a trench is also correspondingly provided on the isolation structure110, and while the trench on the active region AA is filled with the following steps, the trench on the isolation structure110is also filled with the same steps. In Step S200: a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed. The gate structure is filled in the bottom of the trench with a preset thickness. The gate structure does not fully fill the trench. The trench portion filled with the gate structure is defined as the bottom trench, and the trench portion above the bottom trench is defined as the top trench. By this time, the gate structure is only filled in the bottom trench but does not filled in the top trench, thereby forming the buried gate. After the gate structure is formed, there is a need to expose the trench sidewalls above the gate structure outside. In an example, the gate structure is filled in the bottom of the trench, which may include the following steps. In Step S211: a dielectric layer is formed on an inner wall of the trench. As shown inFIG.4b, the dielectric layer121is formed on the inner wall of the trench, with which the gate dielectric layer is formed. In an example, the dielectric layer121may be formed by using a deposition process. The dielectric layer121shape-retaining covers the exposed surface. The so-called “shape-retaining coverage” refers to that the thickness of the dielectric layer121is uniform and consistent. As shown inFIG.4b, the dielectric layer121is respectively formed on the inner wall of the trench, on the substrate100out of the trench and on the isolation structure110. The deposition process may specifically use chemical vapor deposition (CVD) or atomic layer deposition (ALD). The CVD may use plasma enhancing CVD (PECVD), and may also use other appropriate deposition process. Specifically, the formed dielectric layer121may be an oxide, and may also be a nitride. In another example, the dielectric layer121may also be formed by using a thermal oxidation process. With the thermal oxidation process, an oxide layer may be formed on the surface of the exposed substrate100and on the inner wall of the trench. Therefore, the oxide layer formed on the inner wall of the trench and on the surface of the substrate100out of the trench may serve as the dielectric layer121. In an example, as shown inFIG.4b, after the dielectric layer121is formed on the inner wall of the trench, and before Step S220, the method further includes that: a metal nitride layer122is formed on the dielectric layer121. Specifically, the metal nitride layer122includes titanium nitride. In Step S212: a first conductive layer is filled in the trench, and the first conductive layer is back-etched to a preset depth. Further referring toFIG.4b, the first conductive layer123is filled in the trench. Specifically, the first conductive layer123may be deposited with a deposition process. The deposition process may also be the above described any deposition process. The first conductive layer123deposited herein is relatively thick, thus it overflows from the trench for a certain height after fully filling the trench. Further, the step that the first conductive layer123is back-etched includes that: first, the first conductive layer123is ground with a grinding process to remove the first conductive layer123out of the trench, and then the first conductive layer123in the trench is etched to a preset depth with a dry etching process. Thus, the gate structure120includes the first conductive layer123and the dielectric layer121clamped between the first conductive layer123and the inner wall of the trench, in which the first conductive layer123serves as the gate conductive layer, and the portion of the dielectric layer121clamped between the first conductive layer123and the inner wall of the trench is the gate dielectric layer. In an example, the first conductive layer123uses a metal having good conductivity. For example, tungsten, molybdenum, cobalt, ruthenium, copper, silver, aluminum, tungsten-copper alloy, graphene and the like may be used as low-resistivity materials. The first conductive layer123may use a material selected from the above materials but is not limited thereto. It may also use other appropriate conductive material. In an example, when the metal nitride layer122is further formed on the dielectric layer121, after the first conductive layer123is filled, both the first conductive layer123and the metal nitride layer122are back-etched to a preset depth. Specifically, the first conductive layer123and the metal nitride layer122may be back-etched to the preset depth at the same time, such that upper surface of the first conductive layer123and the metal nitride layer122are flush. In an example, after the first conductive layer123is back-etched, the dielectric layer121may also be further back-etched to the preset depth, to remove the dielectric layer121other than that in the gate structure120. In another example, after the first conductive layer123is back-etched, the dielectric layer121is not back-etched, but retained on the trench sidewall above the gate structure120and on the surface of the substrate100out of the trench. In an example, when the first conductive layer123is metal, after the first conductive layer123is back-etched to the preset depth, the method may further include that: a polysilicon layer124covering the first conductive layer123is formed in the trench, which does not fully fill the trench. At this time, the gate structure120includes the polysilicon layer124, the first conductive layer123, the metal nitride layer122and the dielectric layer121clamped between the metal nitride layer122and the inner wall of the trench. During the specific process, the relatively thick polysilicon layer124may be deposited in the trench with the deposition process, and then the polysilicon layer124is back-etched to a target thickness. At this time, as shown inFIG.4c, the polysilicon layer124covers the first conductive layer123and does not fully fill the trench. In this example, by forming the polysilicon layer124on the first conductive layer123, the polysilicon layer124has a small work function, thus may reduce the gate-induced leakage. In other examples, materials such as Al, Ta, Nb and Zr may also be used to replace the polysilicon layer124. In an example, after the gate structure120is filled in the bottom of the trench, the method may further include the following step. In Step S220: a protective layer covering the upper surface of the gate structure and exposing the trench sidewall above the gate structure is formed. In an example, Step S220may be divided into the following sub-steps. In Step S221: a protective layer covering the trench sidewall, an upper surface of the gate structure and an upper surface of the substrate out of the trench is formed. As shown inFIG.4d, the protective layer130with an uniform thickness is deposited on the structural surfaces in the trench and out of the trench with a deposition process. At this time, the protective layer130shape-retaining covers the trench sidewall, the upper surface of the gate structure120and the upper surface of the substrate100out of the trench. Specifically, the deposition process is the ALD process. In Step S222: with an etching process, the protective layer on the trench sidewall is removed and the protective layer covering the upper surface of the gate structure is retained. In an example, the etching process is lateral etching. As shown inFIG.4e, after the protective layer130is deposited, the protective layer130is laterally etched to remove the protective layer130on the trench sidewall, meanwhile retain the protective layers130on the upper surface of the gate structure120and on the upper surface of the substrate100out of the trench, such that only the substrate on the trench sidewall is exposed, therefore, in the subsequent epitaxial growth process, the epitaxial layer is only formed on the trench sidewalls. In other examples, as shown inFIG.5a, the protective layer on the trench sidewall and on the upper surface of the substrate out of the trench may be removed together, while only the protective layer130on the upper surface of the gate structure120is retained, such that the trench sidewall and the substrate out of the trench are exposed at the same time, therefore, in the subsequent epitaxial growth process, the epitaxial layer is formed on the trench sidewall and the substrate out of the trench at the same time; and after the epitaxial growth, the excessive epitaxial layer out of the trench may be removed with the grinding process. The lateral etching may be wet etching which as a relatively larger etching rate to the sidewall. For example, after the substrate100is placed into an etchant, an external electric field is applied to a space where the etchant is present. Depending on the applied external electric field, corrosive negative ions and/or positive ions in the etchant are driven to a direction to be etched. In the example, the direction to be etched is a horizontal direction (lateral) toward the trench sidewall. By controlling the direction of the wet etching, the etching selectivity of the wet etching is improved. The protective layer130on the trench sidewall is etched, whereas the degree of etching on the protective layers130covering the upper surface of the gate structure120and the upper surface of the substrate100is relatively low, such that after the protective layer130on the trench sidewall is etched completely and the trench sidewall are exposed, the upper surface of the gate structure120and the upper surface of the substrate100are still covered by the protective layers130. Specifically, the protective layer130may be silicon nitride or silicon oxide, and may also be other appropriate dielectric material. In an example, when only the protective layer130is formed on the trench sidewall, by just removing the protective layer130on the sidewall the trench sidewall can be exposed. In another example, when other structure is clamped between the trench sidewall and the protective layer, after the protective layer130is removed, the other structure on the sidewall is exposed, and the exposed other structure needs to be further etched till the trench sidewall themselves are exposed. For example, when the gate structure120is manufactured, the formed dielectric layer121, that covers the inner wall of the trench and the upper surface of the substrate100out of the trench, is not removed before Step S222, then in Step S222, the dielectric layer121on the trench sidewall is exposed after the protective layer130on the trench sidewall is removed. T this time, the dielectric layer121is further etched till the trench sidewall is exposed. In the above example, after a protective layer is formed, the protective layer on the sidewall is removed and the protective layer130covering the gate structure120is retained to expose the trench sidewall above the gate structure120. In another example, the protective layer130may be only deposited in a target region by a patterning deposition technique. For example, the protective layer130is only deposited on the gate structure120and on the structural surface out of the trench but not deposited on the trench sidewall above the gate structure120, such that the trench sidewall above the gate structure120retain being exposed. In still another example, the protective layer may also be fully filled in the trench above the gate structure120, then the protective layer is back-etched to reduce its height, and a part of protective layer on the top of the trench is removed. As shown inFIG.5a, only a part of the protective layer is retained to cover the gate structure. In Step S300: an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, which does not close the trench. As shown inFIG.4f, the epitaxial layer102is grown on the exposed trench sidewall with the epitaxial growth process, and the epitaxial layer102does not close the trench, i.e., the epitaxial layer102on each of the two sides of the trench does not contact with one another. The grown epitaxial layer102is the same as the substrate100in property thus it may be taken as a part of the substrate100. The thickness of the epitaxial layer102may be specifically set as required. The thickness of the epitaxial layer102can be controlled by controlling the time or condition for the epitaxial growth. Specifically, the trench provided on the active region of the substrate100has a width in a range of 5 nm to 50 nm, and each epitaxial layer102has a width in a range of 0.1 nm to 20 nm. In an example, as shown inFIG.4f, when the protective layer130is formed on the surface of each of the gate structure120and the substrate out of the trench, the epitaxial growth is only performed on the exposed trench sidewall, i.e., the epitaxial layer102is only formed on the trench sidewall. In an example, as shown inFIG.5b, when the protective layer130only covers the gate structure120, the epitaxial growth may be performed on the exposed trench sidewalls and on the substrate out of the trench. At this time, the epitaxial layer102is respectively formed on the trench sidewall and on the substrate out of the trench. In combination withFIG.5c, after the epitaxial growth, the undesired epitaxial layer out of the trench may be removed with a grinding process, and only the epitaxial layer102on the trench sidewall is retained. In an example, before the epitaxial growth, in-situ cleaning is performed on the exposed surface of the trench sidewall of the substrate100, to remove impurities on the surface of the substrate100. Specifically, SiCoNi in-situ precleaning may be performed, and other dry cleaning or separated wet etching may also be used. In an example, the step that the epitaxial layer102is grown on the exposed trench sidewalls with the epitaxial growth process, may include the following steps. In Step S310: the substrate is dried in an environment at a temperature of 605° C. to 705° C. Specifically, the substrate is placed into an epitaxial growth furnace chamber, and the temperature of the furnace chamber is set at 605° C. to 705° C. to dry the surface of the substrate as well as the inner wall of the furnace chamber, and make the temperature of the substrate uniform. In Step S320: the temperature is elevated to 840° C. to 860° C. and hydrogen is charged to perform baking. Specifically, the temperature of the furnace chamber is heated to 840° C. to 860° C., and the hydrogen is charged for baking, so as to remove the oxide film on the exposed surface of the trench sidewall of the substrate. In Step S330: the temperature is lowered to 715° C. to 725° C. and a pressure is lowered to 9 torr to 11 torr, and then epitaxial growth reaction gases are charged for a preset period for the epitaxial growth. Specifically, the temperature in the furnace chamber is lowered to 715° C. to 725° C. and the pressure is lowered to 9 torr to 11 torr, and then the epitaxial growth reaction gases are charged. The reaction gases may be a combination of SiH4, HCl and hydrogen, a combination of SiCl4and hydrogen or a combination of SiHCl3and hydrogen. During the epitaxial growth, the residual reaction gases and reaction product gases need to be pumped out continuously. In Step S340: the pressure is restored to a barometric pressure, and the temperature is restored to 605° C. to 705° C., to complete the epitaxial growth. Upon the formation of the epitaxial layer, the trench further needs to be filled with the dielectric, and thus Step S400is performed. In Step S400: an isolation layer is filled in the trench. As shown inFIG.4g, the isolation layer140is filled in the trench; and specifically, the isolation layer140may be deposited with the deposition process. Specifically, the isolation layer140may be an oxide layer or a nitride layer. According to the above method for manufacturing the buried gate, the trench is provided on the substrate100, the gate structure120is filled in the bottom of the trench and the trench sidewall above the gate structure120is exposed, and the epitaxial layer102is grown on the exposed trench sidewall with the epitaxial growth technique. In the disclosure, the trench having an opening with a large width may be first provided on the substrate100, in which the gate structure120is filled. The large width of the opening of the trench is beneficial to filling the gate structure120. After the gate structure120is filled, the epitaxial layer102is grown on the top trench sidewall with the epitaxial growth technique to reduce the width of the opening of the trench, thereby ensuring the width W2of the active region. Comparisons may be made onFIG.1andFIG.4g. The buried gate formed according to the conventional art is shown inFIG.1, in which the gate conductive layer has the width W1′ and the height H1′, and an active region on one side of the trench has the width W2′. The buried gate formed according to the disclosure is shown inFIG.4g, in which the gate conductive layer has the width W1and the height H1, and an active region on the same side of the trench has the width W2. When the size of the selected substrate is unchanged, the height of the gate conductive layer is unchanged and the size of the active region is unchanged, i.e., H1=H1′, W2=W2′, the width of the gate structure formed by the disclosure is increased, and the width of the gate conductive layer is also correspondingly increased, i.e., W1>W1′. Therefore, for the buried gate formed by the manufacturing method of the disclosure, the resistance of the gate conductive layer is reduced, such that the buried gate has a good electrical performance. The disclosure further relates to a method for manufacturing a semiconductor device. The method may include steps in which a gate structure is manufactured on a substrate by any of the above methods for manufacturing the buried gate; and an active region on two sides of the gate structure is doped to form a source/drain region, thus a transistor is produced, thereby forming the semiconductor device including the transistor structure. Therefore, any semiconductor device including the transistor structure may be manufactured with the above manufacturing method. For example, the above semiconductor device may be a laterally-diffused metal-oxide semiconductor (LDMOS), or a vertically-diffused metal-oxide semiconductor (LDMOS). In an example, the above semiconductor device is a dynamic random access memory (DRAM) including a transistor structure, which is provided with a word line and a bit line. The word line is connected to the above formed gate structure120, and the bit line is connected to a drain of the transistor; and a source of the transistor is connected to a storage capacitor. An on-off state of the corresponding transistor is controlled through the word line, thereby controlling a voltage of the source and changing a charge-discharge state of the storage capacitor to implement data storage. According to the above method for manufacturing the semiconductor device, as the gate structure is formed with the improved method for manufacturing the buried gate, the gate conductive layer of the formed gate structure has a larger width and the gate conductive layer has a smaller resistance, without changing the level of integration of the device, such that the semiconductor device has the good electrical performance. The above examples only describe several implementation modes of the disclosure. The description is specific and detailed, but cannot be understood as a limit to a scope of the disclosure accordingly. It should be pointed out that those of ordinary skill in the art may further make multiple changes and improvements without departing from a concept of the disclosure and those also belong to the protection scope of the disclosure. Therefore, the protection scope of the disclosure shall be subjected to the appended claims. | 27,554 |
11862698 | DETAILED DESCRIPTION A semiconductor device of embodiments includes: a first electrode; a second electrode; a first semiconductor region of a first conductive type provided between the first electrode and the second electrode and electrically connected to the first electrode; a plurality of second semiconductor regions of a second conductive type provided between the first semiconductor region and the second electrode; a third semiconductor region of the first conductive type provided between the second semiconductor region and the second electrode and electrically connected to the second electrode; a conductive portion provided between the first electrode and the second electrode, the conductive portion including a first conductive portion and a second conductive portion, the first conductive portion provided on a side of the conductive portion facing the first electrode in a first direction from the first electrode to the first semiconductor region, the second conductive portion provided on a side of the conductive portion facing the second electrode in the first direction, the second conductive portion disposed between the second semiconductor regions in a second direction crossing the first direction, and the second conductive portion having an impurity concentration lower than an impurity concentration of the first conductive portion; a first insulating portion provided between the first conductive portion and the first semiconductor region; a gate electrode provided between the second semiconductor region and the second conductive portion in the second direction; a second insulating portion provided between the second conductive portion and the gate electrode; and a third insulating portion provided between the second semiconductor region and the gate electrode. In addition, a method of manufacturing a semiconductor device of embodiments includes: forming a trench in a first semiconductor region of a first conductive type from a surface of the first semiconductor region in a first direction; forming a first insulating portion on a surface of the trench; forming a first conductive portion on the first insulating portion in the trench; forming a second conductive portion in contact with the first conductive portion and having an impurity concentration lower than an impurity concentration of the first conductive portion, the first conductive portion being disposed between the first insulating portion and the second conductive portion in the first direction; removing a part of the first insulating portion to expose a part of the second conductive portion and a part of an inner wall of the trench in a second direction crossing the first direction; forming a second insulating portion by oxidizing a surface of the second conductive portion; forming a third insulating portion by oxidizing the inner wall of the exposed trench; forming a gate electrode between the second insulating portion and the third insulating portion; forming a second semiconductor region of a second conductive type facing the gate electrode in the first semiconductor region, the third insulating portion interposed between the second semiconductor region and the gate electrode in the second direction; and forming a third semiconductor region of the first conductive type between the surface and the second semiconductor region. Hereinafter, embodiments will be described with reference to the diagrams. In this description, the same portions are denoted by the same reference numerals throughout the diagrams. In addition, the dimensional ratio of each diagram is not limited to the ratio shown in the diagram. In addition, the present embodiment does not limit the invention. First Embodiment (Structure of Semiconductor Device100) The detailed structure of a semiconductor device100according to a first embodiment will be described with reference toFIGS.1A,1B,1C,2A,2B, and2C.FIG.1Ais a cross-sectional view of the semiconductor device100according to the first embodiment,FIG.1Bis a cross-sectional view showing a chain line A portion ofFIG.1A, andFIG.1Cis a cross-sectional view of the semiconductor device100according to the first embodiment.FIG.2Ais a plan view of the semiconductor device100according to the first embodiment,FIG.2Bis a cross-sectional view taken along the line C-C′ ofFIG.2A, andFIG.2Cis a cross-sectional view taken along the line D-D′ ofFIG.2A. Hereinafter, a case where the first conductive type is n type and the second conductive type is p type will be described as an example. In addition, in the following description, the notations of n+, n, n−, p+, p, and p−indicate the relative high and low of the impurity concentration in each conductive type. That is, n+indicates that the n-type impurity concentration is relatively higher than n, and n−indicates that the n-type impurity concentration is relatively lower than n. In addition, p+indicates that the p-type impurity concentration is relatively higher than p, and p−indicates that the p-type impurity concentration is relatively lower than p. In addition, n+-type and n−-type may be simply described as n-type, p+-type and p−-type may be simply described as p-type. The impurity concentration in the semiconductor region can be measured by, for example, time of flight-secondary ion mass spectrometry (TOF-SIMS). In addition, the relative high and low of the impurity concentration can be determined from, for example, the high and low of the carrier concentration obtained by scanning capacitance microscopy (SCM). In addition, the distance such as the depth and thickness of an impurity region can be calculated by, for example, the TOF-SIMS. In addition, the distance such as the depth, thickness, and width of an impurity region and a distance between impurity regions can be calculated from, for example, a composite image of an SCM image and an atomic force microscope (AFM) image. In addition, the concentration of impurities contained in an insulating layer can be measured by, for example, energy dispersive X-ray spectroscopy (EDX). The semiconductor device100according to the first embodiment shown inFIGS.1A,1B, and1Cis a MOSFET. The semiconductor device100includes a drain electrode10(first electrode), a gate electrode13, a source electrode (second electrode), a first semiconductor region of n-type20, a second semiconductor region of p-type23, a third semiconductor region of n+-type26, a conductive portion30, and an insulating layer40. The direction from the drain electrode10to the first semiconductor region of n-type20is assumed to be a Z direction (first direction). In addition, the direction perpendicular to the Z direction is assumed to be an X direction (second direction). In addition, the direction perpendicular to the X and Z directions is assumed to be a Y direction (third direction).FIGS.1A,1B, and1Cshow cross-sectional views of the semiconductor device100on the XZ plane. In addition, although the X, Y, and Z directions are shown in a relationship in which the X, Y, and Z directions are perpendicular to each other in the present embodiment, the X, Y, and Z directions are not limited to being perpendicular to each other and may be in a relationship in which the X, Y, and Z directions cross each other. In addition, for the sake of explanation, the direction from the drain electrode10to the first semiconductor region of n-type20is referred to as “up”, and the opposite direction is referred to as “down”. The first semiconductor region of n-type20, the second semiconductor region of p-type23, and third semiconductor region of n+-type26contain silicon (Si) or silicon carbide (SiC) as a semiconductor material. When silicon is used as a semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) can be used as an n-type impurity. Boron (B) can be used as a p-type impurity. The first semiconductor region of n-type20has an n+-type drain region21and an n−-type drift region22. The n+-type drain region21is provided on the drain electrode10and is electrically connected to the drain electrode10. The n−-type drift region22is provided on the n+-type drain region21in the Z direction. The n−-type drift region22is electrically connected to the drain electrode10through the n+-type drain region21. The second semiconductor region of p-type23has a p-type base region24and a p+-type contact region25. A plurality of second semiconductor regions of p-type23are provided. A plurality of p-type base regions24are spaced from each other in the X direction. The p-type base region24is provided on the n−-type drift region22. The p+-type contact region25is provided on each p-type base region24. The third semiconductor region of n+-type26is an n+-type source region. The third semiconductor region of n+-type26is provided on the p-type base region24. FIG.1Bis an enlarged cross-sectional view of a region shown by the chain line A portion ofFIG.1A. The insulating layer40has a first insulating portion41, a second insulating portion42, a third insulating portion43, and a fourth insulating portion44. InFIG.1B, the first insulating portion41is shown by a two-dot chain line, the second insulating portion42and the third insulating portion43are shown by a chain line, and the fourth insulating portion44is shown by a one-dot chain line. The first insulating portion41, the second insulating portion42, the third insulating portion43, and the fourth insulating portion44are integrally formed. The insulating layer40contains an insulating material such as silicon oxide. The first insulating portion41, the second insulating portion42, the third insulating portion43, and the fourth insulating portion44may contain impurities (for example, boron). The specific structure of the insulating layer40will be described later. The conductive portion30and the gate electrode13contain a conductive material such as polysilicon. Impurities such as phosphorus are added to the conductive material. The conductive portion30is provided between the drain electrode10and the source electrode14. The conductive portion30is a field plate electrode. The conductive portion30has a first conductive portion31and a second conductive portion32. The first conductive portion31is provided in the n−-type drift region22. The first insulating portion41is provided between the first conductive portion31and the n−-type drift region22. The first conductive portion31is provided on the drain electrode10side of the conductive portion30in the Z direction. The second conductive portion32is provided on the first conductive portion31. The lower portion of the second conductive portion32is provided in the n−-type drift region22. The first insulating portion41is provided between the lower portion of the second conductive portion32and the n−-type drift region22. The upper portion of the second conductive portion32is provided in the n−-type drift region22. The second insulating portion42is provided between the upper portion of the second conductive portion32and the n−-type drift region22. The second conductive portion32is provided closer to the source electrode14than the first conductive portion31in the Z direction. The second conductive portion32is provided on the source electrode14side of the first conductive portion31in the Z direction. The impurity concentration in the second conductive portion32is lower than the impurity concentration in the first conductive portion31. The first insulating portion41is a field plate insulating film. The first insulating portion41is provided between the first conductive portion31and the first semiconductor region20. The first insulating portion41is provided between the lower portion of the second conductive portion32and the first semiconductor region20. The first insulating portion41insulates the conductive portion30from the gate electrode13, the first semiconductor region20, the second semiconductor region23, and the third semiconductor region26. The second insulating portion42insulates the conductive portion30from the gate electrode13, the first semiconductor region20, the second semiconductor region23, and the third semiconductor region26. The gate electrode13is provided on the first insulating portion41. The specific structure in the vicinity of the gate electrode13will be described later. The source electrode14is provided on the n+-type source region26and the p+-type contact region25. The source electrode14is electrically connected to the conductive portion30, the n+-type source region26, and the p+-type contact region25. The fourth insulating portion44is provided between the gate electrode13and the source electrode14. The gate electrode13and the source electrode14are electrically separated from each other by the fourth insulating portion44. As shown inFIGS.1A and1B, the gate electrode13is provided between the p-type base region24and the second conductive portion32in the X direction. The gate electrode13is provided between the n+-type source region26which is provided on the p-type base region24and the second conductive portion32in the X direction. The third insulating portion43is provided between the p-type base region24and the gate electrode13and between the n+-type source region26and the gate electrode13. The p-type base region24and the gate electrode13are electrically separated from each other by the third insulating portion43. The n+-type source region26and the gate electrode13are electrically separated from each other by the third insulating portion43. The second insulating portion42is provided between the gate electrode13and the second conductive portion32. The gate electrode13and the second conductive portion32are electrically separated from each other by the second insulating portion42. In addition, as shown inFIGS.1A,1B, and1C, a plurality of gate electrodes13may be provided. In this case, the other gate electrode13is provided between the second conductive portion32and the p-type base region24different from the p-type base region24described above. In addition, the other gate electrode13is provided between the second conductive portion32and the n+-type source region26different from the n+-type source region26described above. The second insulating portion42is provided between the second conductive portion32and the gate electrode13, and the second conductive portion32and the other gate electrode13are electrically separated from each other by the second insulating portion42. The third insulating portion43is provided between the other gate electrode13and the p-type base region24. In addition, the third insulating portion43is provided between the other gate electrode13and the n+-type source region26. As described above, the semiconductor device100shown inFIGS.1A,1B, and1Chas a structure in which the p-type base region24(or the n+-type source region26), the third insulating portion43, the gate electrode13, the second insulating portion42, the second conductive portion32, the second insulating portion42, the gate electrode13, the third insulating portion43, and the p-type base region24(or the n+-type source region26) are arranged in this order in the X direction. In addition, in the semiconductor device100, the above-described structure is repeatedly provided in the X direction as shown inFIG.1C. FIG.2Ashows a plan view of the semiconductor device100, and the source electrode14shown inFIGS.1A,1B, and1Care omitted. In addition, a boundary portion between the p-type base region24(or the n+-type source region26) and the third insulating portion43is shown by a chain line. As shown inFIG.2A, the p+-type contact region25extends in the Y direction. Similarly to the p+-type contact region25, each region provided in the semiconductor device100, for example, each of the p-type base region24, the n+-type source region26, the conductive portion30, and the gate electrode13extends in the Y direction. In addition, in the cross section taken along the line B-B′ ofFIG.2A, the semiconductor device100has a structure shown inFIG.1A. The region having a structure shown inFIG.1Ais an element region through which a current flows. In a part of the semiconductor device100, a gate pad53connected to an external power supply (or a gate controller) is provided so as to be spaced from the element region. The region which surrounds the element region and through which no current flows is called a termination region. The semiconductor device100has an element region and a termination region. A gate wiring is electrically connected to the gate pad53. The gate wiring is the gate electrode13disposed on the fourth insulating portion44inFIG.2C. The gate wiring is electrically separated from the source electrode14. The gate wiring is provided on the surface of the semiconductor device100. The cross-sectional view taken along the line C-C′ ofFIG.2AisFIG.2B. The conductive portion30extending in the Y direction is electrically connected to the source electrode14through the source contact portion51in the termination region of the semiconductor device100. The conductive portion30is in contact with the source contact portion51. The source contact portion51is in contact with the source electrode14. The conductive portion30is electrically pulled out to the surface side of the semiconductor device100by the source contact portion51, thereby being electrically connected to the source electrode14. In addition, the cross-sectional view taken along the line D-D′ ofFIG.2AisFIG.2C. The gate electrode13extending in the Y direction is electrically connected to the gate wiring (that is, the gate pad53) through a gate contact portion52in the termination region of the semiconductor device100. The gate electrode13is electrically pulled out to the surface side of the semiconductor device100by the gate contact portion52, thereby being electrically connected to the gate wiring (that is, the gate pad53). In addition, in the present embodiment, the source contact portion51is disposed closer to the termination region of the semiconductor device100than the gate contact portion52. The positions where the source contact portion51and the gate contact portion52are formed can be changed by appropriately changing the design of the gate electrode13and the second conductive portion32. The gate contact portion52may be disposed closer to the termination region than the source contact portion51. (Operation of Semiconductor Device100) The operation of the semiconductor device100will be described. First, a turn-on operation will be described. With a positive voltage applied to the drain electrode10, a voltage equal to or more than a threshold voltage is applied to the gate electrode13. Therefore, a channel (inversion layer) is formed in the p-type base region24adjacent to the gate electrode13with the third insulating portion43interposed therebetween, and the semiconductor device100is turned on. Electrons flow from the source electrode14to the drain electrode10through the channel. That is, when the semiconductor device100is in the on state, the current flows from the drain electrode10to the source electrode14. Next, a turn-off operation will be described. When a voltage lower than the threshold voltage is applied to the gate electrode13, the channel in the p-type base region24disappears and the semiconductor device100is turned off. When the semiconductor device100is switched to the off state, the positive voltage applied to the drain electrode10increases. On the other hand, a negative voltage (for example, ground) relative to the drain electrode10is applied to the source electrode14. As a result, from the interface between the n−-type drift region22and the first insulating portion41provided around the conductive portion30serving as a field plate electrode, a depletion layer spreads toward the n−-type drift region22. Due to the spread of the depletion layer, electric field concentration in the n−-type drift region22is suppressed, so that it is possible to increase the breakdown voltage of the semiconductor device100. In addition, due to the spread of the depletion layer, the n-type impurity concentration in the n−-type drift region22is increased while maintaining the breakdown voltage of the semiconductor device100, so that it is possible to reduce the on-resistance of the semiconductor device100. (Method of Manufacturing Semiconductor Device100) FIGS.3A to10Bare process cross-sectional views showing a manufacturing process of the semiconductor device100according to the first embodiment. An example of the method of manufacturing the semiconductor device100according to the first embodiment will be described with reference toFIGS.3A to10B. First, an n+-type semiconductor substrate21is prepared. The semiconductor substrate21is the n+-type semiconductor region21. As shown inFIG.3A, by epitaxial growth on the n+-type semiconductor region21in the Z direction, the n−-type semiconductor region22is formed. In addition, the n-type impurity concentration in the n−-type semiconductor region22is, for example, equal to or more than 1×1015cm−3and equal to or less than 1×1016cm−3. As shown inFIG.3B, a plurality of trenches T extending along the Y direction are formed on the upper surface of an n−-type semiconductor region1aby reactive ion etching (RIE). As shown inFIG.4A, a first insulating layer41ais formed along the upper surface of the n−-type semiconductor region22and the inner surface of the trench T. The first insulating layer41ais formed by thermally oxidizing the n−-type semiconductor region22. Alternatively, the first insulating layer41amay be formed by depositing the first insulating layer41aby a chemical vapor deposition method (CVD method). The first insulating layer41acontains silicon oxide. As shown inFIG.4B, a conductive layer31ais formed on the first insulating layer41aso as to bury the trench T by using the CVD method. The conductive layer31ais, for example, polysilicon, and contains, for example, phosphorus or boron as conductive impurities. As shown inFIG.5A, the conductive layer31aformed on the first insulating layer41ais partially removed by reactive ion etching (RIE) to form the first conductive portion31. As shown inFIG.5B, a conductive layer32ais formed on the first conductive portion31and the first insulating layer41aby the CVD method. The conductive layer32ais, for example, polysilicon. The conductive layer32amay contain conductive impurities (for example, phosphorus). The conductive impurity concentration in the conductive layer32ais lower than the impurity concentration in the first conductive portion31. A part of the upper surface of the conductive layer32ais removed by chemical dry etching (CDE) or the like. As a result, as shown inFIG.6A, the second conductive portion32is formed, and the conductive portion30formed by the first conductive portion31and the second conductive portion32is provided in each of the plurality of trenches T. In addition, the impurity concentration in the conductive portion30is, for example, equal to or more than 1×1019cm−3and equal to or less than 1×1021cm−3. A part of the first insulating layer41ais removed by wet etching or CDE, so that the upper surface of the first insulating layer41ais recessed to form the first insulating portion41. As a result, as shown inFIG.6B, the upper portion of the second conductive portion32including the upper surface and the side surface is exposed. In addition, the upper surface of the n−-type semiconductor region22is exposed. The side surface of the n−-type semiconductor region22is exposed to the inner wall of the trench T. The upper surface and the side surface of the n−-type semiconductor region22and the upper surface and the side surface of the second conductive portion32are oxidized by oxidation treatment. As shown inFIG.7A, the second insulating portion42is formed by oxidizing a part of the second conductive portion32. The second insulating portion42may be formed by thermally oxidizing a part of the second conductive portion32. A part of the second conductive portion32that has not been oxidized remains as a conductive layer having a reduced width. The third insulating portion43is formed by oxidizing the surface of the n−-type semiconductor region22. The third insulating portion43may be formed by thermally oxidizing the surface of the n−-type semiconductor region22. As shown inFIG.7B, a conductive layer13ais formed on the first insulating portion41, on the n−-type drift region22, and between the second insulating portion42and the third insulating portion43by using the CVD. This conductive layer contains polysilicon. The conductive layer13amay contain conductive impurities (for example, phosphorus). A part of the conductive layer13ais removed by CDE or the like to retract the upper surface of the conductive layer13a. As a result, as shown inFIG.8A, the gate electrode13is formed in the trench T. As shown inFIG.8B, p-type impurities are ion-implanted into the upper portion of the n−-type semiconductor region22to form the p-type base region24. Then, n-type impurities are ion-implanted to form the n+-type source region26. As shown inFIG.9A, a fourth insulating layer44acovering each of the gate electrode13, the second insulating portion42, the third insulating portion43, and the n+-type source region26is formed. As shown inFIG.9B, a part of the n+-type source region26, a part of the p+-type contact region25, and a part of the fourth insulating layer44aon the n+-type source region26are removed. Therefore, an opening OP that reaches the p-type base region24through the n+-type source region26is formed. As a result, a part of the n+-type source region26and a part of the p-type base region24are exposed. As shown inFIG.10A, p-type impurities are ion-implanted into the exposed p-type base region24to form the p+-type contact region25. As shown inFIG.10B, the source electrode14buried in the opening OP is formed on the fourth insulating portion44. The drain electrode10is formed below the n+-type drift region. Through the above steps, the semiconductor device100shown inFIGS.1A,1B, and1Cis manufactured. As described above, the second insulating portion42is formed by oxidizing the second conductive portion32containing impurities such as phosphorus. The concentration of impurities contained in the second conductive portion32is equal to or more than 1×1019cm−3and equal to or less than 1×1021cm−3. On the other hand, the first insulating portion41and the third insulating portion43are formed by oxidizing the n−-type semiconductor region22. The n-type impurity concentration in the n−-type semiconductor region22is equal to or more than 1×1015cm−3and equal to or less than 1×1016cm3. Therefore, the concentration of impurities contained in the second insulating portion42is higher than the concentration of impurities contained in the first insulating portion41and the concentration of impurities contained in the third insulating portion43. Effect of First Embodiment The effect of the semiconductor device100according to the first embodiment will be described with reference to a semiconductor device400according to a comparative example shown inFIG.11. The semiconductor device400according to a first comparative example is different from the semiconductor device100according to the first embodiment in that the conductive portion30is formed only by the first conductive portion31. Both the semiconductor device100according to the first embodiment and the semiconductor device400according to the first comparative example have a structure in which a part of the conductive portion30is disposed between the gate electrodes13in the X direction. For example, in the case of a semiconductor device having a breakdown voltage equal to or more than 100 V, in order to increase the width of the insulating layer40in the X direction, it is necessary to increase the width of the trench T inFIG.3Bshown in the above-described manufacturing process. At that time, in the case of a structure in which only one gate electrode13is provided in one trench T, that is, in the case of a structure in which a part of the conductive portion30is not disposed between the two gate electrodes13in the X direction, the width of the gate electrode13in the X direction is increased. Accordingly, there is a possibility that the burying formation of the gate electrode13will be insufficient. On the other hand, by adopting a structure in which a part of the conductive portion30is disposed between the two gate electrodes13in the X direction, that is, a structure in which the two gate electrodes13are formed in one trench T, the width of one gate electrode13is reduced. Therefore, the burying accuracy of the gate electrode13can be improved. In the comparative example, the second insulating portion42between the gate electrode13and the conductive portion30is formed by oxidizing the conductive portion30, for example. As described above, since the conductive portion30is electrically connected to the source electrode14, the conductive portion30contains a high concentration of impurities in order to reduce the connection resistance (wiring resistance) between the conductive portion30and the source electrode14. However, in polysilicon with a high impurity concentration, the grain size tends to be non-uniform, so that large and small grains are likely to be mixed and formed. If polysilicon with a non-uniform grain size is oxidized, large grains push out relatively small grains, and accordingly, relatively small grains may be captured in the oxide film. In a place where small grains are included, the insulating film (oxide film) is formed thin by the grain size. For this reason, the film thickness of the second insulating portion42becomes non-uniform, and accordingly, the breakdown tolerance of the insulating film between the gate electrode13and the conductive portion30is reduced. As a result, the second insulating portion42between the gate electrode13and the conductive portion30may breaks down while repeating the on/off operation of the semiconductor device400, which leads to a short circuit between the gate electrode and the source electrode. As an example of making the film thickness of the second insulating portion42uniform to secure the breakdown tolerance of the insulating film, a method of reducing the width of the conductive portion30in the X direction can be considered. If the width of the conductive portion30in the X direction is reduced, polysilicon grains can grow only up to the trench width when forming the conductive portion30. Since the generation and growth of polysilicon having a non-uniform grain size are suppressed, it is easy to make the grain size of polysilicon uniform. As a result, small silicon grains are relatively less likely to be formed, which reduces the possibility that small grains will be captured in the oxide film. However, when the conductive portion30is formed by CVD, if the thickness of the conductive portion30in the X direction is reduced, the burying property of polysilicon deteriorates, which may cause voids. Therefore, it is desirable to secure a certain thickness of the conductive portion30in the X direction from the viewpoint of the reliability of the semiconductor device. Based on the above discussions, the effect of the semiconductor device100according to the first embodiment will be described. In the semiconductor device100, the second insulating portion42between the gate electrode13and the second conductive portion32is formed by oxidizing the second conductive portion32. Since the impurity concentration in the second conductive portion32is lower than the impurity concentration in the first conductive portion31, non-uniform polysilicon grain size formation is suppressed. Therefore, when a part of the second conductive portion32is oxidized, it is possible to suppress the capturing of grains in the second insulating portion42. As a result, in the semiconductor device100according to the first embodiment, it is possible to suppress the variation in the film thickness of the second insulating portion42between the gate electrode13and the second conductive portion32while maintaining the width of the conductive portion30in the X direction. In addition, since the first conductive portion31has a high impurity concentration, it is possible to reduce the connection resistance between the conductive portion30and the source electrode14. Therefore, in the semiconductor device100, since it is possible to maintain the breakdown tolerance of the insulating film between the gate electrode13and the conductive portion30, it is possible to suppress breakdown of the element during operation. In addition, in the semiconductor device100, since it is possible to reduce the connection resistance between the conductive portion30and the source electrode14, the formation of a depletion layer during the OFF operation is promoted. Therefore, the breakdown voltage can be secured. Modification Example of First Embodiment A semiconductor device101according to a modification example of the first embodiment will be described with reference toFIGS.12A and12B.FIG.12Ais a cross-sectional view of the semiconductor device101according to the modification example of the first embodiment, andFIG.12Bis a cross-sectional view showing a chain line E portion ofFIG.12A. The semiconductor device101according to the modification example of the first embodiment further include a plurality of third conductive portions33compared with the first embodiment. The plurality of third conductive portions33are provided around the lower portion of the second conductive portion32. The plurality of third conductive portions33are provided so as to be spaced from each other in the X direction. The third conductive portion33is provided between the lower portion of the second conductive portion32and the first insulating portion41in the X direction. In addition, the third conductive portion33is in contact with the first conductive portion31. In addition, the third conductive portion33is in contact with the first insulating portion41. The sum of the width of the second conductive portion32and the width of the third conductive portion33in the X direction is larger than the width of the second conductive portion32interposed between the two gate electrodes13in the X direction. The third conductive portion33is formed of, for example, polysilicon. In addition, the third conductive portion33can be replaced with an insulating layer such as silicon nitride (SiN). Here, the points overlapping the semiconductor device100according to the first embodiment will not be described. A method of manufacturing the semiconductor device101according to the modification example of the first embodiment will be described. After forming the first conductive portion31as shown inFIG.4Ain the method of manufacturing the semiconductor device100according to the first embodiment, a conductive layer33ais formed on each of the surface of the first insulating layer41aand a part of the surface of the conductive portion31by using a CVD method as shown inFIG.13A. As shown inFIG.13B, the conductive layer33aformed on the surface of the first insulating layer41aoutside the trench T and a part of the conductive layer33aformed on the first conductive portion31are removed by wet etching or CDE. As shown inFIG.14A, the conductive layer32ais formed on the first conductive portion31and between the left and right conductive layers33aby using the CVD method. The conductive layer32ais buried in the trench T. As shown inFIG.14B, a part of the first insulating layer41aand a part of the conductive layer33aare removed by wet etching or CDE. Therefore, the upper surface of the first insulating layer41aand the upper surface of the conductive layer33aare recessed. As a result, the second conductive portion32and the third conductive portion33are formed. In the method of manufacturing the semiconductor device101according to the modification example of the first embodiment, the steps after the step of forming the second insulating portion42by oxidizing the second conductive portion32as shown inFIG.7Aare the same as in the method of manufacturing the semiconductor device100according to the first embodiment. The structure of the semiconductor device101according to the modification example of the first embodiment is the same as the structure of the semiconductor device100according to the first embodiment except for the points described above. In addition, the method of manufacturing the semiconductor device101is the same as the method of manufacturing the semiconductor device100except for the points described above. In addition, the semiconductor device101according to the modification example of the first embodiment has the same effect as the semiconductor device100according to the first embodiment. Since the width of the semiconductor device101in the X direction is further reduced only in the upper portion of the conductive portion30, it is possible to further suppress the variation in the grain size of the polysilicon of the second conductive portion32. Therefore, it is possible to further suppress the variation in the film thickness of the second insulating portion42formed by oxidizing a part of the second conductive portion32. As a result, in the semiconductor device101, since it is possible to improve the breakdown tolerance of the insulating film between the gate electrode13and the conductive portion30, it is possible to suppress breakdown of the element during operation. In addition, since the width of the first conductive portion31in the X direction can be maintained constant, the first conductive portion31is easily buried and formed in the manufacturing process. Therefore, it is possible to manufacture the semiconductor device101in which the breakdown tolerance of the insulating film between the gate electrode13and the conductive portion30is secured and the connection resistance between the conductive portion30and the source electrode14is small. Second Embodiment A semiconductor device200according to a second embodiment will be described with reference toFIGS.15A and15B.FIG.15Ais a cross-sectional view of the semiconductor device200according to the second embodiment, andFIG.15Bis a cross-sectional view showing a chain line F portion ofFIG.15A. The semiconductor device200according to the second embodiment is different from the semiconductor device100according to the first embodiment in that a region immediately above the second conductive portion32and the source electrode14are directly connected to each other. More specifically, a part of the source electrode14connected to the second conductive portion32is formed between the n+-type source regions26adjacent to each other in the X direction. The points overlapping the semiconductor device100according to the first embodiment will not be described. The two gate electrodes13are adjacent to each other with the second insulating portion42interposed therebetween, for example. In addition, the two gate electrodes13are adjacent to each other with the source electrode14interposed therebetween, for example. Alternatively, the two gate electrodes13are adjacent to each other with the second conductive portion32and the source electrode14interposed therebetween, for example. In this case, a boundary between the part of the source electrode14and the second conductive portion32is provided closer to the drain electrode10than a boundary between the fourth insulating portion44and the gate electrode13in the direction from the drain electrode10to the first semiconductor region of n-type20. A method of manufacturing the semiconductor device200according to the second embodiment will be described. After forming the fourth insulating portion44that covers the gate electrode13as shown inFIG.9Ain the method of manufacturing the semiconductor device100according to the first embodiment, a part of the fourth insulating layer44ais removed as shown inFIG.16A. At this time, in addition to a part of the fourth insulating layer44aon the n+-type source region26, a part of the n+-type source region26, and a part of the p+-type contact region25, a part of the fourth insulating layer44aformed on the second conductive portion32is removed. As a result, the fourth insulating portion44is formed. In addition, a first opening OP1that reaches the p-type semiconductor region24through the n+-type semiconductor region26and a second opening OP2that reaches the second conductive portion32through the fourth insulating portion44are formed. As shown inFIG.16B, p-type impurities are ion-implanted into the p-type semiconductor region24through the first opening OP1to form the p+-type semiconductor region25. The source electrode14is formed on the fourth insulating portion44so as to bury the first opening OP1and the second opening OP2. The drain electrode10is formed below the n+-type drain region21. Through the above steps, the semiconductor device200shown inFIGS.15A and15Bis manufactured. The structure of the semiconductor device200according to the second embodiment is the same as the structure of the semiconductor device100according to the first embodiment except for the points described above. In addition, the method of manufacturing the semiconductor device200is the same as the method of manufacturing the semiconductor device100except for the points described above. In addition, the semiconductor device200has the same effect as the semiconductor device100. Here, when the MOSFET is turned off, a phenomenon called dynamic avalanche may occur in which holes remaining in the semiconductor layer without being discharged are concentrated and accordingly, the breakdown voltage of the MOSFET is reduced. In addition, the MOSFET in which dynamic avalanche has occurred causes current loss or deterioration of switching efficiency. On the other hand, for example, there is a structure in which, by providing the field plate electrode in the semiconductor layer as shown in the semiconductor device400according to the comparative example, the depletion layer is expanded in the semiconductor layer to maintain the breakdown voltage when the MOSFET is turned off. However, if the voltage abruptly changes when the MOSFET is turned off, a surge current may flow from the drain electrode10to the conductive portion30through the insulating layer40. In this case, the voltage applied to the conductive portion30rises. Since the voltage applied to the source electrode (field plate electrode) is normally 0 V, the formation of the depletion layer is promoted during the OFF operation of the MOSFET. However, when the voltage applied to the conductive portion30rises, the formation of the depletion layer is suppressed. For this reason, the occurrence of the above-described dynamic avalanche becomes more noticeable. In the case of the semiconductor device200according to the second embodiment, since the region immediately above the second conductive portion32and the source electrode14are directly connected to each other, the resistance of the conductive portion30in the Z direction can be reduced. That is, holes that have entered the conductive portion30during the OFF operation can be efficiently discharged from the source electrode14. As a result, it is possible to suppress the occurrence of the dynamic avalanche of the semiconductor device200during the OFF operation. Therefore, in the semiconductor device200, it is possible to increase the breakdown voltage, reduce the current loss, and improve the switching efficiency. The effect of the semiconductor device200according to the second embodiment will be described with reference to the above semiconductor device400according to the comparative example. FIG.17Ashows a plan view of the semiconductor device400according to the comparative example, and the source electrode14shown inFIG.11is omitted.FIG.17Bshows a cross-sectional view taken along the line H-H′ ofFIG.17A, andFIG.17Cshows a cross-sectional view taken along the line I-I′ ofFIG.17A. The cross-sectional view taken along the line G-G′ ofFIG.17Ais a cross-sectional view of the semiconductor device400according to the comparative example shown inFIG.11. In addition, inFIG.17A, a boundary portion between the p-type base region24(or the n+-type source region26) and the third insulating portion43is shown by a chain line. As shown inFIG.17B, the semiconductor device400according to the comparative example is a semiconductor device in which a field plate electrode30is formed in a stripe shape. Therefore, in order to electrically connect the field plate electrode30and the source electrode14to each other, it is necessary to form the source contact portion51. The source contact portion51is provided in the termination region of the field plate electrode30. FIG.18Ashows a plan view of the semiconductor device200according to the second embodiment, and the source electrode14shown inFIGS.15A and15Bis omitted.FIG.18Bshows a cross-sectional view taken along the line J-J′ ofFIG.18A. The cross-sectional view taken along the line K-K′ ofFIG.18Ais a cross-sectional view of the semiconductor device200according to the second embodiment shown inFIGS.15A and15B. In the case of the semiconductor device200according to the second embodiment, the upper portion of the second conductive portion32and the source electrode14are directly connected to each other in the Z direction. In the case of the semiconductor device200according to the second embodiment, the source electrode14and the second conductive portion32are connected to each other in the element region. As a result, it is not necessary to provide the source contact portion51unlike in the semiconductor device400according to the comparative example shown inFIG.17A. The p-type base region24, the n+-type source region26, and the p+-type contact region25are not formed in the source contact portion51. Therefore, the source contact portion51becomes an invalid region in which no current flows during the ON operation. In the semiconductor device200according to the second embodiment, since it is not necessary to provide the source contact portion51, the effective area through which a current flows during the ON operation can be increased. Therefore, in the semiconductor device200according to the second embodiment, it is possible to reduce the on-resistance. Modification Example of Second Embodiment A semiconductor device201according to a modification example of the second embodiment will be described with reference toFIG.19.FIG.19shows a plan view of the semiconductor device201having a dot trench type field plate structure. InFIG.19, the source electrode14shown inFIGS.15A and15Bis omitted. In addition, the cross-sectional view taken along the line L-L′ ofFIG.19is the same as the cross-sectional view of the semiconductor device200according to the second embodiment shown inFIGS.15A and15B. The semiconductor device201according to the modification example of the second embodiment has a dot trench type field plate structure. Similarly to the semiconductor device200, in the semiconductor device201, the upper portion of the second conductive portion32and the source electrode14are directly connected to each other in the Z direction. Therefore, the semiconductor device201can have a dot trench type field plate structure as in this modification example. Similarly to the semiconductor device200according to the second embodiment, in the semiconductor device201according to the modification example of the second embodiment, it is possible to increase the effective area through which a current flows during the ON operation. Third Embodiment A semiconductor device300according to a third embodiment will be described with reference toFIGS.20A and20B.FIG.20Ais a cross-sectional view of the semiconductor device300according to the third embodiment, andFIG.20Bis a cross-sectional view showing a chain line M portion ofFIG.20A. The semiconductor device300according to the third embodiment further includes a fourth conductive portion34compared with the second embodiment. The fourth conductive portion34is provided so as to extend in the Z direction from above the first conductive portion31. In addition, the second conductive portion32is provided between the fourth conductive portion34and the first insulating portion41in the X direction. In addition, the second conductive portion32is provided between the fourth conductive portion34and the gate electrode13in the X direction. In addition, the second conductive portion32is provided between the fourth conductive portion34and the second insulating portion42in the X direction. The second conductive portion32is formed of polysilicon or silicon nitride (SiN). The impurity concentration in the second conductive portion32is lower than the impurity concentration in the fourth conductive portion34. In addition, similarly to the semiconductor device200, a region immediately above the second conductive portion32and the source electrode14in the semiconductor device300are directly connected to each other. Here, the points overlapping the semiconductor device100according to the second embodiment will not be described. A method of manufacturing the semiconductor device300according to the third embodiment will be described. FIG.21Ais a cross-sectional view showing a method of manufacturing the semiconductor device300according to the third embodiment, andFIG.21Bis a cross-sectional view showing a method of manufacturing the semiconductor device300according to the third embodiment. In addition,FIG.22Ais a cross-sectional view showing a method of manufacturing the semiconductor device300according to the third embodiment, andFIG.22Bis a cross-sectional view showing a method of manufacturing the semiconductor device300according to the third embodiment. In addition,FIG.23is a cross-sectional view showing another method of manufacturing the semiconductor device300according to the third embodiment. After forming the first conductive portion31as shown inFIG.5Ain the method of manufacturing the semiconductor device100according to the first embodiment, the conductive layer32ais formed by the CVD method as shown inFIG.21A. In addition, a conductive layer34ais formed on the conductive layer32aby the CVD method. A part of the upper surface of the conductive layer32aand a part of the upper surface of the conductive layer34aare removed by chemical dry etching (CDE) or the like. As a result, as shown inFIG.21B, the second conductive portion32and the fourth conductive portion34are formed. The conductive portion30formed by the first conductive portion31, the second conductive portion32, and the fourth conductive portion34is provided in each of the plurality of trenches T. A part of the first insulating layer41ais removed by wet etching or CDE, so that the upper surface of the first insulating layer41ais recessed to form the first insulating portion41. As a result, as shown inFIG.22A, the upper portion of the second conductive portion32including the upper surface and the side surface, the upper portion of the fourth conductive portion34, and the upper surface of the n−-type semiconductor region22are exposed. The side surface of the n−-type semiconductor region22is exposed to the inner wall of the trench T. The upper surface and the side surface of the n−-type semiconductor region22and the upper surface and the side surface of the second conductive portion32are oxidized by oxidation treatment. As shown inFIG.22B, the second insulating portion42is formed by oxidizing a part of the second conductive portion32and a part of the fourth conductive portion34. In addition, a part of the second conductive portion32that has not been oxidized and the fourth conductive portion34are formed. The fourth conductive portion34may be formed widely in the X direction by injecting impurities into the second conductive portion32. In this case, in the method of manufacturing the semiconductor device200according to the second embodiment, as shown inFIG.16B, a part of the fourth insulating layer44aformed on the second conductive portion32and the fourth conductive portion34is removed to form the second opening OP2. Thereafter, as shown inFIG.23, by injecting impurities into the second conductive portion32and the fourth conductive portion34through the second opening OP2, the fourth conductive portion34in a portion electrically connected to the source electrode14can be formed to be large. The semiconductor device300according to the third embodiment has the same structure as the semiconductor device200according to the second embodiment except for the points described above. In addition, the method of manufacturing the semiconductor device300is the same as the method of manufacturing the semiconductor device200except for the points described above. In the semiconductor device300according to the third embodiment, the upper portion of the fourth conductive portion34and the source electrode14are directly connected to each other in the Z direction, similarly to the semiconductor device200according to the second embodiment. Therefore, in the semiconductor device300according to the third embodiment, since it is not necessary to provide the source contact portion51, the effective area through which a current flows during the ON operation can be increased. As a result, it is possible to reduce the on-resistance. In addition, in the semiconductor device300according to the third embodiment, the second conductive portion32having a lower impurity concentration than the fourth conductive portion34is provided between the fourth conductive portion34and the gate electrode13and between the fourth conductive portion34and the second insulating portion42in the X direction. For this reason, it is possible to further suppress the variation in the grain size of the polysilicon of the second conductive portion32. Therefore, it is possible to further suppress the variation in the film thickness of the second insulating portion42formed by oxidizing a part of the second conductive portion32. As a result, in the semiconductor device300, it is possible to maintain the breakdown tolerance of the insulating film between the gate electrode13and the conductive portion30and reduce the on-resistance. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the semiconductor device and the method of manufacturing a semiconductor device described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 54,980 |
11862699 | DETAILED DESCRIPTION Referring toFIG.1, a substrate11, multiple discrete bit line structures13located on the substrate11, isolation walls14and capacitor contact holes15are provided. Conductive contact regions are provided in the substrate11. The bit line structures13are arranged to expose the conductive contact regions12. The isolation walls are located on sidewalls of the bit line structures13. The capacitor contact holes15are constituted by regions defined by the isolation walls14between adjacent bit line structures, which expose the conductive contact regions12, and are configured to be filled with a conductive material to form conductive plugs. Referring toFIG.2, the capacitor contact holes15are filled with the conductive material to form conductive plugs16. Since the thicknesses of the isolation walls14in a direction perpendicular to the sidewalls of the bit line structures13are generally the same, the contour morphologies of the capacitor contact holes15depend on those the sidewalls of the bit line structures13. In a direction parallel to the orientation of the bit line structures13, the top width of the bit line structures13is equal to their bottom width, and the top width of the capacitor contact holes15is equal to their bottom width. When the aspect ratio of the capacitor contact holes15is larger, top openings of the capacitor contact holes15may be sealed in advance during filling the conductive material, thereby forming conductive plugs16with voids17. The existence of the voids17would increases the resistance values of the conductive plugs16. Referring toFIG.3, the conductive plugs16are etched back to expose the voids17(refer toFIG.2); and the conductive material is filled again to eliminate the voids17and form conductive plugs16. During etching the conductive plugs16to expose the voids17, the conductive material may be oxidized due to being exposed to an oxygen environment and finally forms non-conductive oxide layers18. The existence of the oxide layer18also increases the resistance of the conductive plugs16, thereby influencing the conductive performance of the conductive plugs16. In order to solve the aforementioned problems, an embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof. By doping ions to a second isolation part of an isolation layer, a first isolation part and the second isolation part of the isolation layer have different material properties, thereby replacing successively stacked layers of two film layers with different material properties. Accordingly, the effects of reducing the number of the isolation layers and reducing the total thickness of the isolation walls are achieved. The thinning of the isolation walls helps to increase the bottom areas of the capacitor contact holes, which further reduces the resistance values of the conductive plugs and reduces the parasitic capacitance between a conductive plug and the conductive structure adjacent thereto. In addition, by increasing the top width of the capacitor contact holes and enlarging the process windows of the capacitor contact holes, the top openings of capacitor contact holes may be prevented from being sealed in advance in the material deposition process. The conductive material is ensured to fill up the capacitor contact holes, and further the conductive plugs without the voids or the oxide layer and having smaller resistance values are formed. To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below in combination with the accompanying drawings. Those of ordinary skilled in the art can understand that, in various embodiments of the present disclosure, many technical details are presented to make readers understand the present disclosure better, whereas, the technical solutions claimed by the present disclosure can also be implemented even without these technical details and various changes and modifications made based on the following embodiments. FIG.4toFIG.13are schematic diagrams of the sectional structures corresponding to various operations of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Referring toFIG.4, a substrate21is provided. Conductive contact regions22are provided in the substrate21. The substrate21exposes the conductive contact region22. Multiple discrete initial bit line structures230are formed on the substrate21, in which the top width is equal to the bottom width of the initial bit line structures230in a direction parallel to the orientation of the initial bit line structures230. An initial bit line structure230includes a conductive contact layer231, a metal gate layer232, and a top dielectric layer233, which are arranged in sequence in a direction perpendicular to the substrate21. The material of the conductive contact layer231includes polysilicon, the metal gate layer232includes a stacked structure of titanium nitride-tungsten-titanium nitride, and the material of the top dielectric layer233includes silicon nitride. In other embodiments, the top width of the initial bit line structures may also be greater than or less than the bottom width. Referring toFIG.5, a deposition process is performed to form a first isolation layer24on a sidewall of the initial bit line structure230. The first isolation layer24is configured to protect the metal gate layer232in the initial bit line structure230, preventing the metal gate layer232from being damaged in subsequent etching, cleaning and other processes, thereby ensuring that the metal gate layer232has a good conductive performance and a good signal transmission performance. In the embodiment, the first isolation layer24is separately formed by a deposition process. Since the first isolation layer24plays a role of protection and sidewall supporting, it may be formed by atomic layer deposition process, by which the first isolation layer24has higher compactness and better step coverage. In the embodiment, the material of the first isolation layer24is the same as that of the top dielectric layer233. As such, in the subsequent etching process, a specific etchant may be selected for the material of the first isolation layer24, so that the etching process has a faster etching rate, which helps to reduce the manufacturing period of a semiconductor structure. Referring toFIG.6, spacer layers29are formed, the spacer layers29divide trenches between the adjacent initial bit line structures230into multiple discrete grooves, and each of the grooves is configured to form a conductive plug. A parasitic capacitance may exist between conductive plugs in adjacent grooves, and the parasitic capacitance may also exist between the conductive plug in a certain groove and the metal gate layer in the initial bit line structure adjacent to the groove. The value of the parasitic capacitance is related to the resistance value of the conductive plug. The smaller the resistance of the conductive plug, the smaller the parasitic capacitance. In addition, the value of the parasitic capacitance is also related to the dielectric constant of an intermediate isolation material. The smaller the dielectric constant, the smaller the parasitic capacitance. The resistance value of a conductive plug is related to the bottom area of the conductive plug, that is, the larger the bottom area, the smaller the resistance value. The resistance value of the conductive plug is also related to the structure and the material of the conductive plug. When there are fewer or smaller voids in the conductive plug and less dielectric material is contained in the conductive plug, the conductive plug has smaller resistance value. It should be noted that, adjusting the top structure of the initial bit line structure230and forming the isolation wall on the sidewalls of the initial bit line structure230are primarily taken as exemplary illustration in the drawings herein. Indeed, in the embodiments of the present disclosure, the top structure of a spacer layer29is also adjusted accordingly and an isolation wall is formed on a sidewall of the spacer layer29. Referring toFIG.7, an etching process is performed to the initial bit line structures230and the first isolation layer24. In the embodiment, after forming the first isolation layer24, a dry etching process with an etching angle is performed to the first isolation layer24and the initial bit line structure230to form a bit line structure23with a chamfer θ at the top. The angle of the chamfer θ is the same as the etching angle. The angle of the chamfer θ is 5°-35°, for example 10°, 15°, 20° or 30°. In an actual process procedure, the optimal angle of the chamfer θ is 15°. The formation of the chamfer θ within the numerical range helps to enlarge the process window for subsequently forming capacitor contact holes, and prevent the capacitor contact holes from being sealed in advance when the conductive material is deposited. In addition, the setting of an upper limit value of the chamfer θ helps to reduce the process difficulty and prevent the metal gate layer232from being damaged by the dry etching process, thereby ensuring the conductive performances of the bit line structures23. In the embodiment, the etching process removes some of the material at the top corners of the top dielectric layer233. The top dielectric layer233with a changed structure, the metal gate layer232and the conductive contact layer231together constitute the new bit line structure23. In addition, the etching process also removes the first isolation layer24on the bottom of the groove between the adjacent bit line structures23and the first isolation layer24on the top of the bit line structures23. In the embodiment, the dry etching process is performed by adopting a mixed plasma of three gases SF6, CF4and O2, and the residual gases are cleaned by using an inert gas (for example argon). Referring toFIG.8, a first ion doping process is performed to the first isolation layer24. In the embodiment, the first isolation layer24includes a first isolation part close to the bit line structures23and a second isolation part deviating from the bit line structures23. An ion doping process is performed to the second isolation part, so that the dielectric constant of the second isolation part of the first isolation layer24is smaller than the dielectric constant of the first isolation part. In this way, the hardness of the first isolation part may be maintained such that the first isolation part may have a better sidewall supporting effect, and the isolation wall may have a lower dielectric constant without adding an additional film layer. In addition, the ion doping is only performed to the second isolation part, so that damage to the metal gate layer232caused by the ion doping process is avoided, and a good conductive performance of the metal gate layer232is ensured. In the embodiment, the first ion doping process not only performs the ion doping to the second isolation part of the first isolation layer24, but also to the top dielectric layer233exposed by the first isolation layer24. In this way, when performing the first ion doping process, only the energy of the doped ion needs to be controlled to control the doping depth, and the doping position does not need to be limited, so that the doping difficulty is reduced, and the second isolation part of the first isolation layer24may be effectively doped. In the embodiment, the material of the first isolation layer24includes silicon nitride, the first ion doping process performs an oxygen ion doping to the second isolation part of the first isolation layer24, the material of the doped second isolation part includes silicon oxynitride, and the silicon oxynitride layer has a lower dielectric constant relative to the silicon nitride layer. In the embodiment, taking oxygen as an oxygen source, the silicon nitride is doped with the oxygen plasma. The radio frequency power for forming the oxygen plasma is 600 to 2000 W, for example be 800 W, 1200 W or 1600 W. The temperature of the oxygen plasma is 800° C. to 1000° C., for example be 850° C., 900° C. or 950° C. Referring toFIG.9, A second isolation layer25is formed on the side of the first isolation layer24deviating from the bit line structures23. Specifically, the second isolation layer25is mainly configured to reduce the dielectric constant of the isolation wall, and the dielectric constant of the material of the second isolation layer25is smaller than that of the material of the first isolation layer24. In the embodiment, the material of the second isolation layer25includes silicon oxide. The second barrier layer25may be formed through an atomic layer deposition process. Specifically, LTO250 and oxygen or N zero and oxygen may be used to react to generate silicon oxide. Referring toFIG.10, a second ion doping process is performed to a second isolation part of the second isolation layer25. In the embodiment, the ion doping is performed to the second isolation part of the second isolation layer25, such that the hardness of the second isolation part in the second isolation layer25is greater than the hardness of the first isolation part. In this way, the isolation wall can have higher sidewall supporting capacity without adding an additional film layer, and damages to the structures of isolation wall caused by stresses from adjacent structures may be avoided. Specifically, the material of the second isolation layer25includes silicon oxide. A nitrogen ion doping process is performed to the second isolation part of the second isolation layer25during the second ion doping process, and the material of the doped second isolation part includes silicon nitride and/or silicon oxynitride. Compared with silicon oxide, silicon nitride and silicon oxynitride have higher hardness, so that the isolation wall has higher structure stability. In the embodiment, using a nitrogen gas or an ammonia gas as a nitrogen source, the ion doping may be performed to the silicon oxide with nitrogen plasma. The radio frequency power for forming the nitrogen plasma is 600 W to 2000 W, and for example be 800 W, 1200 W, or 1600 W. The temperature of the nitrogen plasma is 600° C. to 800° C., for example be 650° C., 700° C., or 750° C. Since the thermal shock resistance of the silicon oxide is weaker than that of the silicon nitride, the ion doping is performed under a lower plasma temperature, which is beneficial to avoid stress concentration, fracture, surface peeling and other damages to the second isolation layer25due to a larger thermal shock, ensuring that the isolation wall has a higher structure stability. Referring toFIG.11, an etching process is performed to expose the conductive contact regions22. In the embodiment, after removing the bottom dielectric layer, the remaining first isolation layer24and second isolation layer25constitute the isolation wall26. The region surrounded by the isolation walls26between adjacent bit line structures23constitutes the capacitor contact hole27, and the capacitor contact hole27exposes the conductive contact region22. In the embodiment, in a direction parallel to the orientation of the bit line structure23, the isolation wall26include multiple dielectric materials stacked sequentially, which constitute nitride-oxide-nitride structures (NON structure). The dielectric material (nitride) of the isolation wall26in contact with structures adjacent thereto (for example, the bit line structure23, the conductive plug, and the spacer layer29) has a higher hardness, and has the sidewall supporting effect. The damage to the structure of the isolation wall26caused by the external stress is avoided. The dielectric material (oxide) of the isolation wall26deviating from the adjacent structures has a lower dielectric constant, so that the isolation wall26has a lower dielectric constant, thereby reducing the parasitic capacitance between the bit line structure23and the conductive plug. In the embodiment, the ion doping process is adopted, so that one single isolation layer has the good sidewall supporting effect and the lower dielectric constant at the same time. It is not necessary to form a new dielectric layer additionally, which is beneficial to avoid the sidewall morphology problem occurred when forming multiple dielectric layers and the thickness of the isolation layer walls26is reduced, thereby reserving more space for the capacitor contact hole27, and further, and the conductive plug filled in the capacitor contact hole27has a lower resistance. It should be noted that in actual process steps, a deposition process and an etching process are required each time for forming one dielectric layer, and multiple deposition processes and multiple etching processes may cause changes of the sidewall morphologies of the dielectric layers, so that a preset performance requirement may not be met. In addition, during the processes of forming dielectric layers, each dielectric layer has a corresponding minimum thickness due to the limitation of the forming process itself, and at the same time, since the distance between adjacent bit line structures23is fixed, the fewer the dielectric layers are, the larger the bottom area of the capacitor contact hole27for forming the conductive plugs is, and the smaller the resistance value of the subsequently formed conductive plug is. In the embodiment, in a direction parallel to the orientation of the bit line structures23, the top width of the capacitor contact hole27is greater than its bottom width. In addition, referring toFIG.12, in a direction parallel to the orientation of the spacer layer29, the top width of the spacer layer29is smaller than its bottom width, the isolation wall26is located on the sidewalls of the spacer layer29, and the top width of the capacitor contact hole27are greater than its bottom width. In the embodiment, the dry etching process is performed by adopting the mixed plasma of three gases SF6, CF4and O2, and the residual gas is cleaned by using an inert gas (for example argon). Referring toFIG.13, the capacitor contact hole27is filled with a conductive material to form a conductive plug28in contact with the conductive contact region22. In the embodiment, the conductive material includes polysilicon. Before performing a polysilicon deposition possess, a seed layer with a good step coverage may be formed firstly by adopting an atomic layer deposition process. The silicon source of the polysilicon may be H3SiN(C3H7)2, Si2H6or SiH [N(CH3)2]3, the reaction temperature to form the polysilicon may be 380° C.-500° C., and the gas pressure may be 1 torr to 3 torr. In the embodiment, the capacitor contact hole27have a larger process window, so that the top opening of the capacitor contact hole27may be prevented from being sealed in advance during filling the conductive material, ensuring the conductive material fills up the capacitor contact hole, and the conductive plug28with smaller resistance value is formed. In the embodiment, the ion doping possess is performed to the second isolation parts of the isolation layers, so that the first isolation parts and the second isolation parts of the isolation layers have different material properties, thereby replacing successively stacked two film layers with different material properties, and the effects of reducing the number of the isolation layers and reducing the total thickness of the isolation walls are achieved. The thinning of the isolation walls helps to increase the bottom areas of the capacitor contact holes, which further reduce the resistance values of the conductive plugs and reduce the parasitic capacitance between conductive plugs and adjacent conductive structures. In addition, by increasing the top width of the capacitor contact holes and enlarging the process window of the capacitor contact holes, the top opening of capacitor contact holes can be prevented from being sealed in advance in the material deposition process, the conductive material is ensured to fill up the capacitor contact holes, and further the conductive plugs without a void or an oxide layer and having a smaller resistance value are formed. Accordingly, the embodiments of the invention further provide a semiconductor structure. The semiconductor structure may be manufactured by adopting the above methods for manufacturing the semiconductor structure. Referring toFIG.13, the semiconductor structure includes: a substrate21, bit line structures23and isolation walls26located on sidewalls of the bit line structures23and capacitor contact holes27. Conductive contact regions22are provided in the substrate, and the substrate21exposes the conductive contact regions22. Each isolation wall26includes at least one isolation layer. The isolation layer includes a first isolation part close to the bit line structures23and a second isolation part deviating from the bit line structures23, and the second isolation part of the at least one isolation layer has doped ions. In the isolation layer with the doped ions, the hardness of the second isolation part is greater than that of the first isolation part, or the dielectric constant of the second isolation part is smaller than that of the first isolation part. The capacitor contact holes27are constituted by regions surrounded by the isolation walls26between adjacent bit line structures23. The capacitor contact holes27expose the conductive contact regions22, and the top width is greater than the bottom width of the capacitor contact holes27in a direction parallel to the orientation of the bit line structures23. In the embodiment, an isolation wall26include a first isolation layer24and a second isolation layer25, which are sequentially stacked. The first isolation layer24is located between the bit line structure23and the second isolation layer25. First doped ions are included in the second isolation part of the first isolation layer24, such that the dielectric constant of the second isolation part of the first isolation layer24is smaller than that of the first isolation part. Second doped ions are included in the second isolation part of the second isolation layer25, and the hardness of the second isolation part of the second isolation layer25is greater than that of the first isolation part. Specifically, the first isolation layer24includes a silicon nitride layer. The doped ions in the second isolation part of the first isolation layer24include oxygen ions, and the material of the second isolation part includes silicon oxynitride. The second isolation layer25includes a silicon oxide layer, the doped ions in the second isolation part of the second isolation layer25include nitrogen ions, and the material of the second isolation part includes silicon nitride and/or silicon oxynitride. In the embodiment, the tops of the bit line structures23have chamfers. The angle of the chamfers is 5°-35°, for example 10°, 15°, 20° or 30°. In the embodiment, there are doped ions in the second isolation part of the at least one isolation layer. The presences of the doped ions change the property of the material of the isolation layer, such that the first isolation part and the second isolation part of the isolation layer have different properties. In other words, two sequentially stacked film layers which have different properties may be replaced by one isolation layer with the second isolation part contains the doped ions. Therefore, the number of isolation layers is reduced, and the total thickness of the isolation walls is reduced, thereby increasing the bottom area of the capacitor contact holes, further reducing the resistance of the conductive plugs and further reducing the parasitic capacitance between the conductive plugs and the adjacent conductive structures. In addition, the top width of the capacitor contact holes are greater than the bottom width of the capacitor contact holes, which is beneficial to ensure that when the capacitor contact holes are used to be filled with a conductive material to form the conductive plugs, the conductive material is ensured to fill up the capacitor contact holes, avoiding the void problem, therefore the conductive plugs are ensured to have a smaller resistance value. Those of ordinary skilled in the art can understand that aforementioned embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in the forms and details may be made thereto without departing from the spirit and scopes of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scopes of the present disclosure, and therefore the protection scope of the present disclosure, should be defined by the scopes of the claims. | 24,997 |
11862700 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. While the embodiments of this disclosure are discussed with respect to nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In cases where gate all around (GAA) transistor structures are adapted, the GAA transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure. FIGS.1-34Bshow exemplary sequential processes for manufacturing a semiconductor device structure100, in accordance with some embodiments. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1-34B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. As shown inFIG.1, a stack of semiconductor layers104is formed over a substrate101. The substrate101may be a semiconductor substrate. As shown inFIG.1, a semiconductor device structure100includes the stack of semiconductor layers104formed over a surface (e.g., front side) of the substrate101. The substrate101may include a single crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In this embodiment, the substrate101is made of Si. In some embodiments, the substrate101is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide. The substrate101may include one or more buffer layers (not shown) on the surface of the substrate101. The buffer layers can serve to gradually change the lattice constant from that of the substrate101to that of the source/drain (S/D) regions to be grown on the substrate101. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, germanium tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, and InP. In one embodiment, the substrate101includes SiGe buffer layers epitaxially grown on the silicon substrate101. The germanium concentration of the SiGe buffer layers may increase from 30 atomic percent germanium for the bottom-most buffer layer to 70 atomic percent germanium for the top-most buffer layer. The substrate101may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on circuit design, the dopants may be, for example boron for an p-type (or p-channel) field effect transistor (FET) and phosphorus for an n-type (or n-channel) FET. The stack of semiconductor layers104includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate device, such as nanosheet channel FETs or forksheet FETs. In some embodiments, the stack of semiconductor layers104includes first semiconductor layers106and second semiconductor layers108. In some embodiments, the stack of semiconductor layers104includes alternating first and second semiconductor layers106,108. The first semiconductor layers106are aligned with the second semiconductor layers108. The first semiconductor layers106and the second semiconductor layers108are made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layers106may be made of Si and the second semiconductor layers108may be made of SiGe. In some examples, the first semiconductor layers106may be made of SiGe and the second semiconductor layers108may be made of Si. In some cases, the SiGe in the first or second semiconductor layers106,108can have a germanium composition percentage between about 10% and about 80%. Alternatively, in some embodiments, either of the semiconductor layers106,108may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combinations thereof. The first semiconductor layers106or portions thereof may form nanosheet channel(s) of the semiconductor device structure100in later fabrication stages. The term nanosheet is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including, for example, a cylindrical in shape or substantially rectangular cross-section. The nanosheet channel(s) of the semiconductor device structure100may be surrounded by a gate electrode. For example, at least three surfaces of the nanosheet channel(s) may be surrounded by the gate electrode, and the transistor is a forksheet transistor. The semiconductor device structure100may include a nanosheet transistor and/or a forksheet transistor. The nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode surrounding the channels. It is noted that while three layers of the first semiconductor layers106and three layers of the second semiconductor layers108are alternately arranged as illustrated in FIG.1, it is for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. It is contemplated that any number of first and second semiconductor layers106,108can be formed in the stack of semiconductor layers104, and the number of layers depending on the predetermined number of channels for the semiconductor device structure100. In some embodiments, the number of first semiconductor layers106, which is the number of channels, is between 2 and 8. The first and second semiconductor layers106,108are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the stack of semiconductor layers104may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. The substrate101may include a sacrificial layer107on the stack of semiconductor layers104. The sacrificial layer107protects the stack of semiconductor layers104during the subsequent processes and is removed along with a portion of a cladding layer (FIG.11) prior to formation of the sacrificial gate stack (FIG.12). In cases where the first semiconductor layer106of the stack of semiconductor layers104is Si, the sacrificial layer107includes SiGe epitaxially grown on the first semiconductor layer106. As will be described in more detail below, the first semiconductor layers106may serve as channels for the semiconductor device structure100and the thickness is chosen based on device performance considerations. In some embodiments, each first semiconductor layer106has a thickness ranging from about 1 nanometer (nm) to about 20 nm, such as about 3 nm to about 10 nm. The sacrificial layer107may have a thickness that is equal, less, or greater than the thickness of the first semiconductor layer106. The thickness of the sacrificial layer107may range from about 2 nm to 50 nm. The second semiconductor layers108may eventually be removed and serve to define a vertical distance between adjacent nanosheet channels for the semiconductor device structure100and the thickness is chosen based on device performance considerations. In some embodiments, each second semiconductor layer108has a thickness ranging from about 5 nm to about 20 nm, such as about 8 nm to 16 nm. If the thickness of the second semiconductor layer108is less than 5 nm, the space created as a result of removal of the second semiconductor layers108may be too small for the subsequent gate electrode layer to get in and form around the first semiconductor layers106. On the other hand, if the thickness of the second semiconductor layer108is greater than 20 nm, the manufacturing cost is increased without significant advantage and the scaling down of the device is compromised. A mask structure110is formed over the sacrificial layer107. The mask structure110may include an oxygen-containing layer and a nitrogen-containing layer. The oxygen-containing layer may be a pad oxide layer, such as a SiO2layer. The nitrogen-containing layer may be a pad nitride layer, such as Si3N4. The mask structure110may be formed by any suitable deposition process, such as chemical vapor deposition (CVD) process. FIG.2is a perspective view of one of the various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.2, fin structures112(112a-112c) are formed from the stack of semiconductor layers104. Each fin structure112has an upper portion including the semiconductor layers106,108and a well portion116formed from the substrate101. The fin structures112may be fabricated using multi-patterning operations including photo-lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. The photo-lithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing post-exposure bake processes, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches114(e.g.,114a,114b) in unprotected regions through the mask structure110, through the stack of semiconductor layers104, and into the substrate101, thereby leaving the plurality of extending fin structures112(e.g.,112a,112b,112c). The trenches114extend along the X direction. The trenches114may be etched using a dry etch (e.g., RIE), a wet etch, and/or combination thereof. As shown inFIG.2, the trenches114aand114bare formed with different widths between the fin structures112a,112b,112c. The trench114ais formed between the fin structure112aand the fin structure112band has a width W01, which corresponds to the first distance D1shown inFIG.4. The trench114bis formed between the fin structure112band the fin structure112cand has a width W02, which corresponds to the second distance D2shown inFIG.4. The width W02may be equal, less, or greater than the width W01of the trench114a. In the embodiment shown inFIG.2, the width W01is greater than the width W02. The width of the trenches114a,114bmay vary upon the width of the fin structures112a,112b,112c, which varies depending on the channel width of the devices needed in the semiconductor device structure100. As described above, the first semiconductor layers106may serve as channels in a nanosheet and/or forksheet transistor device. The devices with a wider channel, such as the device fabricated from the fin structure112a, may be more suitable for high-speed applications, such as a NAND device. The devices with a narrower channel, such as the device fabricated from the fin structures112b,112c, may be more suitable for low-power and low-leakage applications, such as an inverter device. Therefore, trenches with wider width (e.g., trench114a) may be formed in regions where devices/transistors require higher voltage current and/or higher performance, while trenches with narrower width (e.g., trench114b) may be formed in regions where greater density of devices/transistors is desired. FIG.3is a perspective view of one of the various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. After the fin structures112are formed, an insulating material118is formed on the substrate101. The insulating material118fills the trenches114(FIG.2) between neighboring fin structures112until the fin structures112are embedded in the insulating material118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the top of the fin structures112is exposed. The insulating material118may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material118may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD). Next, the insulating material118is recessed to form an isolation region120, as shown inFIG.3. The recess of the insulating material118exposes portions of the fin structures112, such as the stack of semiconductor layers104. The recess of the insulating material118reveals the trenches114between the neighboring fin structures112. The isolation region120may be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. A top surface of the insulating material118may be level with or slightly below a surface of the second semiconductor layer108in contact with the well portion116formed from the substrate101. Thereafter, the mask structures110is removed by any suitable process, such as ashing, dry etch, wet etch, or a combination thereof. FIGS.4-11are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along cross-section A-A ofFIG.3, in accordance with some embodiments. As shown inFIG.4, the semiconductor device structure100has three fin structures112a,112b, and112cformed along the Y direction. The fin structure112amay have a first width W1, and the fin structures112b,112cmay each has a second width W2. In the embodiment shown inFIG.4, the first width W1is greater than the second width W2. The widths W1and W2may correspond to the device's channel width. In one embodiment, the width W2is in a range between 5 nm to about 120 nm, for example about 10 nm to about 100 nm. As discussed above, the distances between adjacent fins112a,112b, and112cmay vary depending on the devices to be formed in the area. In some embodiments, adjacent fin structures used to form similar devices may be spaced apart by a first distance D1, and adjacent fin structures used to form different devices may be spaced apart by a second distance D2. The distance D1or D2between adjacent fin structures may be defined by the distance between a first sidewall of one fin structure and a second sidewall of the adjacent fin structure facing the first sidewall. The first distance D1and the second distance D2define the width of the subsequent first and second dielectric features130,134(FIG.10). In one embodiment shown inFIG.4, the first distance D1is greater than the second distance D2. The second distance D2may be in a range from about 2 nm to about 40 nm, for example about 3 nm to about 30 nm. With the smaller distance D2(i.e., reduced fin-to-fin spacing) between the fin structures112band112c, layers of a first dielectric feature130(FIG.6) subsequently formed in the trench114bmay merge, while the trench114abetween the fin structures112aand112bremains open after the deposition of layers of the first dielectric feature130due to the wider distance D1. The merged layers of the first dielectric feature130allow the nanosheet channels to attach to both sides of the first dielectric feature130and form forksheet transistors at a later stage. The reduced fin-to-fin spacing and fork-like nanosheet transistors enable greater device density (even with greater channel width) and superior area and performance scalability. Depending on the application, the trenches114cand114dmay have a width corresponding to the first distance D1or the second distance D2. In some embodiments, a fin structure (not shown) having a width corresponding to W1may be disposed adjacent to and spaced apart the fin structure112aby the trench114d. Likewise, a fin structure (not shown) having a width corresponding to W2may be disposed adjacent to and spaced apart the fin structure112cby the trench114c. As shown inFIG.5, a first dielectric layer126is formed on the exposed surfaces of the semiconductor device structure100and in the trenches114a,114b,114c,114d(FIG.4). The first dielectric layer126may include a high-K material having a K value of 7 or above. Exemplary materials may include, but are not limited to HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, etc. The first dielectric layer126may be formed by a conformal process, such as an ALD process. The first dielectric layer126may be formed on the exposed surface of the insulating material118at the bottom of the trenches114a,114b,114c,114dand on the exposed portions of the fin structures112a,112b,112c(e.g., first and second semiconductor layers106,108and the sacrificial layer107). The first dielectric layer126may have a thickness ranging from about 0.5 nm to about 10 nm. Next, a second dielectric layer128is formed on the first dielectric layer126in the trench114a,114b,114c,114d, and over the fin structures112a,112b,112c. The second dielectric layer128fills the trench114b(FIG.4) due to the small distance D2but not the trench114a(FIG.4). The second dielectric layer128may include a low-K dielectric material (e.g., a material having a K value lower than 7). In some embodiments, the second dielectric layer128is a silicon-containing low-K dielectric material such as SiO2, SiN, SiCN, SiOC, or SiOCN. The second dielectric layer128may be formed by a conformal process, such as an ALD process. The second dielectric layer128may have a thickness ranging from about 5 nm to about 30 nm. If the thickness of the second dielectric layer128is less than about 5 nm, the trench114bmay not be filled. On the other hand, if the thickness of the second dielectric layer128is greater than about 30 nm, the trench114amay be filled. As shown inFIG.6, the first dielectric layer126and the second dielectric layer128are recessed. The recess of the first dielectric layer126and the second dielectric layer128may be performed by any suitable removal process, such as dry etch, wet etch, or a combination thereof. The removal process may be selective etch processes that remove portions of the first dielectric layer126and the second dielectric layer128but not the sacrificial layers107, the first semiconductor layers106, the second semiconductor layers108, and the insulating material118. Because the trench114a(FIG.4) is not completely filled and has a larger dimension (i.e., first distance D1) in the Y direction compared to that of the trench114b(FIG.4), the etchant removes more of the first dielectric layer126and the second dielectric layer128in the trench114athan the first dielectric layer126and the second dielectric layer128in the trench114b. As a result, the first dielectric layer126and the second dielectric layer128in the trench114aare etched at a faster rate than the etch rate of the first dielectric layer126and the second dielectric layer128in the trench114b. In cases where the first dielectric layer126and the second dielectric layer128include different materials, and a first etch process may be performed to recess the second dielectric layer128followed by a second etch process to recess the first dielectric layer126. While not shown, the tops of the first dielectric layer126and the second dielectric layer128may have a concave profile due to etching effects from the removal process. The removal process is performed until the first dielectric layer126and the second dielectric layer128in the trenches114a,114c,114dare completely etched away. The removal process also removes the first dielectric layer126and the second dielectric layer128on exposed surfaces of the fin structure112a,112b,112cand the insulating material118. As a result of the removal process, the first dielectric layer126and the second dielectric layer128on exposed surfaces of the semiconductor device structure100are removed except for the first dielectric layer126and the second dielectric layer128filled in the trench114b. The first dielectric layer126and the second dielectric layer128in the trench114bmay be referred to herein as a first dielectric feature130. As shown below inFIG.7, the sidewalls127(127a,127b) and the bottom129of the second dielectric layer128are in contact with the first dielectric layer126. The sidewall127aopposes the sidewall127b, and the bottom129connects the sidewall127ato sidewall127b. As shown inFIG.7, a cladding layer132is formed on the exposed surfaces of the stack of semiconductor layers104, the dielectric feature130(e.g., a top surface of the first dielectric layer126and a top surface of the second dielectric layer128), and the insulating material118. The cladding layer132may be formed by a conformal process, such as an ALD process. The cladding layer132may have substantially the same thickness ranging from about 2 nm to about 20 nm, for example about 5 nm to about 13 nm. The thickness of the cladding layer132formed on the sidewalls of the fin structures112a,112b,112cmay define the space for an IL178(FIG.29), a HK dielectric layer180(FIG.29), and first/second gate electrode layers182/184(FIG.29) to be formed therein after subsequent removal of the cladding layers132. Thus, if the thickness of the cladding layer132is more than about 20 nm, the trench114amay be filled, resulting in the second dielectric feature134and the subsequent layers from not forming in the trench114a. In some embodiments, the cladding layer132includes a semiconductor material. In some embodiments, the cladding layer132and the second semiconductor layers108are made of the same material having the same etch selectivity. For example, the cladding layer132and the second semiconductor layers108include SiGe. The cladding layer132and the second semiconductor layer108may be removed subsequently to create space for the gate electrode layer. As shown inFIG.8, portions of the cladding layer132are removed. The removal of the cladding layer132may be performed by any suitable removal process, such as dry etch, wet etch, or a combination thereof. The removal process may be an anisotropic etch process to remove the cladding layer132formed on horizontal surfaces of the fin structures112a,112b,112c(e.g., top surfaces of the sacrificial layer107, the first dielectric layer126and the second dielectric layer128) and on the insulating material118. The removal process does not remove the cladding layer132formed on vertical surfaces of the fin structures112a,112b,112c. As shown inFIG.9, a second dielectric feature134is formed in the trenches114a,114c,114d(FIG.4). The second dielectric feature134includes a third dielectric layer136and a fourth dielectric layer138formed on the third dielectric layer136. The third dielectric layer136may include the same material and have substantially the same thickness as the first dielectric layer126. Likewise, the fourth dielectric layer138may include the same material as the second dielectric layer128. The second dielectric feature134may be formed in a similar fashion as the first dielectric feature130. For example, the third dielectric layer136may be formed on the cladding layer132and on the exposed surface of the insulating material118at the bottom of the trenches114a,114c,114dand on the exposed portions of the first dielectric feature (e.g., top surfaces of the first and second dielectric layers126,128), using a conformal process, such as an ALD process. The fourth dielectric layer138is then formed in the trenches114a,114c,114dand over the fin structures112a,112b,112cand the first dielectric feature130. The fourth dielectric layer138may be formed by a flowable process, such as an FCVD process. The fourth dielectric layer138may have a thickness ranging from about 2 nm to about 15 nm. The fourth dielectric material138fills the trenches114a,114c,114d. Thus, if the thickness of the fourth dielectric layer138is less than about 2 nm, the trenches114a,114c,114dmay not be filled. Next, a planarization process is performed to expose the top surfaces of the third dielectric layer136, the cladding layer132, the sacrificial layer107, the fourth dielectric layer138, the first dielectric layer126, and the second dielectric layer128, as shown inFIG.9. The planarization process may be any suitable process, such as a CMP process. As the result of the planarization process, the second dielectric feature134is formed in the trenches114a,114c,114d(FIG.4). The sidewalls133(133a,133b) and the bottom135of the fourth dielectric layer138are in contact with the third dielectric layer136. The sidewall133aopposes the sidewall133b, and the bottom135connects the sidewall133ato sidewall133b. As shown inFIG.10, portions of the first dielectric feature130and the second dielectric feature134are recessed. The recess of the first dielectric feature130and the second dielectric feature134may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In cases where the first and second dielectric features130,134are formed of the same material, the recess of the first dielectric feature130and the second dielectric feature134may be a selective process so that the semiconductor material of the sacrificial layers107and the cladding layers132are not substantially affected. The recess process may be controlled so that the tops of the first and second dielectric features130,134are substantially at the same level as or below a top surface of the topmost first semiconductor layer106in the stack of semiconductor layers104. In some embodiments, the top surface of the first and second dielectric features130,134may be about 0 nm to about 10 nm below the level of the top surface of the topmost first semiconductor layer106. As a result of the recess process, trenches (not shown) are formed above the first and second dielectric features130,134and between adjacent fin structures112. Next, a dielectric layer140is formed in each trench formed above the first and second dielectric features130,134and between adjacent fins112. Suitable materials may include, but are not limited to, SiO, SiN, SiON, SiCN, SiOCN, HfSixOy, ZrSixOy, AlSixOy, HfO2, ZrO2, HfAlOx, Al2O3, any suitable material having a K value greater than that of silicon oxide, etc. The dielectric layer140may be formed by any suitable process, such as a CVD, PECVD, FCVD, or ALD process. The dielectric layer140may have a height along the Z direction ranging from about 10 nm to about 30 nm. The dielectric layer140may be utilized to separate, or cut-off, the subsequently formed gate electrode layers. Thus, if the height is less than about 10 nm, the gate electrode layers may not be sufficiently cut-off. On the other hand, if the height is greater than about 30 nm, the manufacturing cost is increased without significant advantage. The dielectric layer140may be initially formed in the trenches (not shown) formed as a result of removal of the portions of the first and second dielectric features130,134. Portions of the dielectric layer140formed over the sacrificial layer107and the cladding layer132are then removed by a planarization process so that the top surfaces of the sacrificial layer107and the cladding layer132are substantially co-planar with the top surfaces of the dielectric layer140. The dielectric layer140and each of the first dielectric feature130and the second dielectric feature134together may be referred to as a dielectric structure141. The dielectric structures141can separate the subsequent S/D epitaxial features and the gate electrode layers between different FETs. In some embodiments, the dielectric structure141is a hybrid fin, which can include a single dielectric material or two or more dielectric materials. As shown inFIG.11, the sacrificial layers107and portions of the cladding layers132are removed. The removal of the sacrificial layers107and the recess of the cladding layers132may be performed by any suitable etch process, such as dry etch, wet etch, or a combination thereof. The etch process may be controlled so that the remaining cladding layers132are substantially at the same level as the top surface143of the topmost first semiconductor layer106in the stack of semiconductor layers104. In cases where the cladding layers132and the sacrificial layers107are made of SiGe, the etch process may be a selective etch process that removes the cladding layers132and the sacrificial layers107, but does not remove the layers of the dielectric structures141(e.g., first and second dielectric features130,134). The removal of the sacrificial layers107exposes the top surfaces of the fin structures112a,112b,112c. FIG.12is a perspective view of one of the various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.13A-19Aare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along cross-section A-A ofFIG.12, in accordance with some embodiments. Cross-section A-A is in a plane of sacrificial gate stacks142along the Y direction.FIGS.13B-19Bare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along cross-section B-B ofFIG.12, in accordance with some embodiments. Cross-section B-B is in a plane perpendicular to cross-section A-A and is in the fin structure112calong the X direction. As shown inFIGS.12,13A and13B, one or more sacrificial gate stacks142are formed on the semiconductor device structure100. The sacrificial gate stacks142may each include a sacrificial gate dielectric layer144, a sacrificial gate electrode layer146, and a mask structure148. The sacrificial gate dielectric layer144may include one or more layers of dielectric material, such as SiO2, SiN, a high-K dielectric material, and/or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer144may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layer146may include polycrystalline silicon (polysilicon). The mask structure148may include an oxygen-containing layer150and a nitrogen-containing layer152. The sacrificial gate electrode layer146and the mask structure148may be formed by various processes such as layer deposition, for example, CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. The sacrificial gate stacks142may be formed by first depositing blanket layers of the sacrificial gate dielectric layer144, the sacrificial gate electrode layer146, and the mask structure148, followed by pattern and etch processes. For example, the pattern process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etch (e.g., RIE), wet etch, other etch methods, and/or combinations thereof. By patterning the sacrificial gate stack142, the stacks of semiconductor layers104of the fins112a,112b,112care partially exposed on opposite sides of the sacrificial gate stack142. While two sacrificial gate stacks142are shown, the number of the sacrificial gate stacks142is not limited to two. More than two sacrificial gate stacks142may be arranged along the X direction in some embodiments. Next, a spacer154is formed on the sidewalls of the sacrificial gate stacks142. The spacer154may be formed by first depositing a conformal layer that is subsequently etched back to form sidewall spacers154. For example, a spacer material layer can be disposed conformally on the exposed surfaces of the semiconductor device structure100. The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etch is performed on the spacer material layer using, for example, RIE. During the anisotropic etch process, most of the spacer material layer is removed from horizontal surfaces, such as the tops of the fin structures112a,112b,112c, the cladding layers132, the third dielectric layers136, and the fourth dielectric layers138, leaving the spacers154on the vertical surfaces, such as the sidewalls of sacrificial gate stacks142. The spacer154may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. InFIGS.14A and14B, exposed portions of the fin structures112a,112b,112cand exposed portions of the cladding layers132not covered by the sacrificial gate stacks142and the spacers154are selectively recessed by using one or more suitable etch processes, such as dry etch, wet etch, or a combination thereof. Portions of the dielectric layer140may also be removed or recessed. In some embodiments, exposed portions of the stacks of semiconductor layers104of the fin structures112a,112b,112care removed, exposing portions of the well portions116of the substrate101. For example, the exposed portions of the fin structures112a,112b,112cmay be recessed to a level at or below the top surface of the insulating material118. The etch processes may include an etch process that recesses the exposed portions of the fin structures112a,112b,112cand the exposed portions of the cladding layers132. At this stage, end portions of the stacks of semiconductor layers104under the sacrificial gate stacks142and the spacers154have substantially flat surfaces which may be flush with corresponding spacers154, as shown inFIG.14B. In some embodiments, the end portions of the stacks of semiconductor layers104under the sacrificial gate stacks142and spacers154are slightly horizontally etched. InFIGS.15A and15B, the edge portions of each second semiconductor layer108and the edge portions of the cladding layers (not shown) are removed to form a gap. In some embodiments, the portions of the semiconductor layers108are removed by a selective wet etching process that does not remove the first semiconductor layers106. For example, in cases where the second semiconductor layers108are made of SiGe, and the first semiconductor layers106are made of silicon, a selective wet etching including an ammonia and hydrogen peroxide mixtures (APM) may be used. Next, dielectric spacers158are formed in the gaps formed as the result of removal of the second semiconductor layer108and the cladding layers, as shown inFIG.15B. In some embodiments, the dielectric spacers158may be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the dielectric spacers158may be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers158. The dielectric spacers158may be protected by the first semiconductor layers106during the anisotropic etching process. InFIGS.16A and16B, epitaxial S/D features160are formed on the well portions116of the fin structures112a,112b,112c. For n-channel FETs, the epitaxial S/D features160may include one or more layers of Si, SiP, SiC, SiCP, or a group III-V material (InP, GaAs, AlAs, InAs, InAlAs, InGaAs). In some embodiments, the epitaxial S/D features160may be doped with n-type dopants, such as phosphorus (P), arsenic (As), etc, for n-type devices. For p-channel FETs, the epitaxial S/D features160may include one or more layers of Si, SiGe, SiGeB, Ge, or a group III-V material (InSb, GaSb, InGaSb). In some embodiments, the epitaxial S/D features160may be doped with p-type dopants, such as boron (B). The epitaxial S/D features160may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate101. The epitaxial S/D features160are formed by an epitaxial growth method using CVD, ALD or MBE. The epitaxial S/D features160are in contact with the first semiconductor layers106and dielectric spacers158, as shown inFIG.16B. The epitaxial S/D features160may be the S/D regions. For example, one of a pair of epitaxial S/D features160located on one side of the stack of semiconductor layers104can be a source region, and the other of the pair of epitaxial S/D features160located on the other side of the stack of semiconductor layers104can be a drain region. A pair of epitaxial S/D features160includes a source epitaxial feature160and a drain epitaxial feature160connected by the channels (i.e., the first semiconductor layers106). In this disclosure, a source and a drain are interchangeably used, and the structures thereof are substantially the same. Depending on the circuit design, the devices on the fin structures112aand112cmay be designed for p-channel FETs and the devices on the fin structure112bmay be designed for n-channel FETs, or vice versa. After the formation of the epitaxial S/D features160, a contact etch stop layer (CESL)162may be formed on the epitaxial S/D features160, the dielectric structures140, the cladding layers132, and the sacrificial gate stack142, as shown inFIGS.16A and16B. The CESL162may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof. The CESL162may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL162is a conformal layer formed by the ALD process. Next, an interlayer dielectric (ILD) layer164is formed on the CESL162. The materials for the ILD layer164may include an oxide formed from tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer164may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer164, the semiconductor device structure100may be subject to a thermal process to anneal the ILD layer164. InFIGS.17A and17B, a planarization process is performed to expose the sacrificial gate electrode layer146. The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the ILD layer164and the CESL162disposed on the sacrificial gate stacks142. The ILD layer164may be recessed to a level below the top of the sacrificial gate electrode layer146. In some cases, a nitrogen-containing layer (not shown), such as a SiCN layer, may be formed on the recessed ILD layer164to protect the ILD layer164during subsequent etch processes. InFIGS.18A and18B, the sacrificial gate electrode layer146(FIG.17B) and the sacrificial gate dielectric layer144(FIG.17B) are removed, exposing the top surfaces of the cladding layers132and the stacks of semiconductor layers104. The sacrificial gate electrode layer146may be first removed by any suitable process, such as dry etch, wet etch, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer144, which may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer146but not the spacers154, the dielectric structures140, and the CESL162. InFIGS.19A and19B, the cladding layers132and the second semiconductor layers108are removed. The removal process exposes the dielectric spacers158and the first semiconductor layers106. The removal process may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The removal process may be a selective etch process that removes the cladding layers132and the second semiconductor layers108but not the first semiconductor layers106, the spacers154, the dielectric structures140, and the CESL162. In cases where the cladding layers132and the second semiconductor layers108are made of SiGe, and the first semiconductor layers106are made of silicon, a selective wet etching including an ammonia and hydrogen peroxide mixtures (APM) may be used. As a result of the etch process, openings166are formed, leaving the first semiconductor layers106protruded from opposing sides of the first dielectric feature130. Specifically, each of the first semiconductor layers106has a first end in contact with the first dielectric layer126and a second end extending away from the first end, as shown inFIG.19A. The portion of the first semiconductor layers106not covered by the dielectric spacers158may be exposed in the openings166. Each first semiconductor layer106serves as a nanosheet channel of the nanosheet transistor/fork-like gate nanosheet transistor. Upon removal of the cladding layers132and the second semiconductor layers108, an end cap region181is formed between distal ends of the first semiconductor layers106and sidewalls of the dielectric features130,134. In some embodiments, the end cap region181has a spacing D3along the Y direction ranging between about 5 nm to about 13 nm. That is, the dielectric structure141is spaced apart from the distal ends of the first semiconductor layers106by the spacing D3. If the spacing D3is less than 5 nm, the subsequent IL178and HK dielectric layer180(FIG.20) may immaturely block the end cap regions181at distal ends of the topmost first semiconductor layers106, which in turn prevents the subsequent layers (e.g., dummy material183and gate electrode layers182,184, etc.) from getting in and forming around the first semiconductor layers106. On the other hand, if the spacing D3is greater than 13 nm, the benefit of scaling down of the device is compromised. The removal of the second semiconductor layers108also forms a channel-to-channel region185between the immediately adjacent nanosheet channels (i.e., adjacent first semiconductor layers106). The channel-to-channel region185has a spacing D4along the Z direction ranging between about 8 nm to about 16 nm. In various embodiments, the spacing D4is greater than the spacing D3. In one embodiment, the ratio of the spacing D4to the spacing D3(D4:D3) is about 1:1 to about 3.2:1, for example about 1.2:1 to about 1.6:1. FIGS.20-29and31are cross-sectional views of the semiconductor device structure100taken along cross-section A-A ofFIG.12during various stages of manufacturing, in accordance with some embodiments. InFIG.20, after the cladding layers132and the second semiconductor layers108are removed, an interfacial layer (IL)178is formed to surround at least three surfaces (except for the surface being in contact with the first dielectric layer126) of the first semiconductor layers106. In some embodiments, a portion of the IL178may be in contact with the first dielectric layer126. In some embodiments, the IL178may also form on the exposed surfaces of the well portion116of the substrate101. The IL178may include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, oxynitride, hafnium silicate, etc. The IL178may be formed by CVD, ALD or any suitable conformal deposition technique. In one embodiment, the IL178is formed using ALD. Next, a high-K (HK) dielectric layer180is formed on the exposed surfaces of the semiconductor device structure100. In some embodiments, the HK dielectric layer180is formed on the IL178, the insulating material118, the dielectric layer140, and on the exposed surfaces of the first and second dielectric features130,134(e.g., the first dielectric layers126and the third dielectric layers136), as shown inFIG.20. The HK dielectric layer180may include or made of hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-k materials. In some embodiments, the HK dielectric layer180may include or made of the same material as the sacrificial gate dielectric layer144. The HK dielectric layer180may be a conformal layer formed by a conformal process, such as an ALD process or a CVD process. The thickness of the IL148and the HK dielectric layer180is chosen based on device performance considerations. In some embodiments, the IL178has a thickness ranging from about 0.5 nm to about 2 nm, for example about 1 nm. The HK dielectric layer180may have a thickness of about 0.5 nm to about 3 nm, for example about 1.5 nm to about 1.8 nm. The combined thickness of the IL178and the HK dielectric layer180reduces the spacing D3(FIG.19) of the end cap regions181. If the combined thickness of the IL178is greater than about 5 nm, the subsequent layers (e.g., dummy material183inFIG.21and gate electrode layers182,184inFIG.29) may immaturely merge with the HK dielectric layer180and block the end cap regions181at distal ends of the topmost first semiconductor layers106, which in turn prevents the subsequent layers from forming on the HK dielectric layer180and around the first semiconductor layers106. On the other hand, if the combined thickness of the IL178and the HK dielectric layer180is less than about 1 nm, the IL178and the HK dielectric layer180may not function properly as intended and result in reliability issues such as increased leakage current and/or deteriorated capacitance characteristics. InFIG.21, after the formation of the IL178and the HK dielectric layer180, a dummy material183is formed on the exposed surfaces of the semiconductor device structure100. Particularly, the dummy material183is formed on the HK dielectric layer180to surround a portion of each first semiconductor layer106and on the HK dielectric layer180that is in contact with the dielectric layer140and the first and second dielectric features130,134. The dummy material183is deposited to help subsequent patterning process and will be removed at later stage. Since the spacing D3of the end cap regions181is smaller than the spacing D4of the channel-to-channel regions185, the dummy material183formed over the first semiconductor layers106and the dummy material183formed over the first and second dielectric features130,134are eventually merged as the thickness of the dummy material183increases. The dummy material183merged at the end cap regions181prevents the subsequent dummy material183from filling in the channel-to-channel regions185between the first semiconductor layers106, resulting in air gaps187formed in the channel-to-channel regions185. The material of the dummy material183is chosen to have different etch selectivity and/or oxidation rates than the subsequent gate electrode layers. The dummy material183may include an oxygen-containing material and/or a nitrogen-containing material. Exemplary materials of the dummy material183may include, but are not limited to, SiOx, AlOx, ZrO2, SiN, TiN, or the like, or any combination thereof. In one embodiment, the dummy material183is a conformal layer formed by a conformal process, such as an ALD process or a CVD process. InFIG.22, after the formation of the dummy material183, the dummy material183is recessed by a removal process. The recess of the dummy material183provides a space for the subsequent mask material189(FIG.23), which protects the dummy material183at the p-channel FETs during subsequent removal of the dummy material183at the n-channel FETs. The removal process may be a selective etch process that removes the dummy material183but does not substantially remove the HK dielectric layer180. In some embodiments, the removal process is a controlled isotropic process so that portions of the dummy material183over the dielectric layer140and the top surface143of the topmost first semiconductor layer106are removed, while the dummy material183between the distal ends of the first semiconductor layers106and the first and second dielectric features130,134remains substantially intact. As a result of the removal process, the top of the dummy material183may be recessed to a level below the top surface of the dielectric layer140. In some embodiments, the top of the dummy material183is at a level between the top surface of the dielectric layer140and the top surface of the topmost first semiconductor layer106. In some embodiments, a portion of the dummy material183is further recessed to a level into the end cap region181of the topmost first semiconductor layer106. In such a case, the dummy material183may be recessed to a level at or below the top surface143of the topmost first semiconductor layer106. In cases where the thickness of the first semiconductor layer106(i.e., channel height) is about 3 nm to about 10 nm, the distance D5between the top of the dummy material183and the top surface143of the topmost first semiconductor layer106may be 0 nm to about 1.5 nm. InFIG.23, after the recess of the dummy material183, a mask layer189is formed on the exposed surfaces of the semiconductor device structure100. The mask layer189is formed over the dielectric layer140and the topmost first semiconductor layers106. Portions of the mask layer189also fill the end cap regions181and are in contact with the dummy material183at the end cap regions181. The mask layer189protects the dummy material183at the p-channel FETs from being over-etched during subsequent removal of the dummy material183at the n-channel FETs. The formation of the mask layer189increases the critical dimension of the dielectric structures141which provides extra footing for the subsequent resist layer191. The mask layer189may include an oxygen-containing material and/or a nitrogen-containing material. Exemplary materials of the mask layer189may include, but are not limited to, SiOx, AlOx, ZrO2, SiN, TiN, or the like, or any combination thereof. In some embodiments, the mask layer189and the dummy material183are formed from different material. In one embodiment, the mask layer189is a conformal layer formed by a conformal process, such as an ALD process or a CVD process. Next, a resist layer191is formed on one or more exposed portions of the mask layer189. The resist layer191can be formed in the selected regions depending on the needs to control the gates at different FETs. In some embodiments, the resist layer191is formed to cover regions of the p-channel FETs, such as the p-channel FETs formed on the fin structures112cas shown inFIG.23. The resist layer191protects the one or more of the portions of the dummy material183and the mask layer189so that the unprotected portions of the dummy material183and the mask layer189are removed and replaced by the subsequently formed gate electrode layer182(FIG.26). The resist layer191may be formed by first forming a blanket layer on the semiconductor device structure100, followed by patterning and etching processes to remove portions of the blanket layer to form the resist layer191. The resist layer191may be any suitable masking material, such as a photoresist layer, a BARC (bottom anti-reflective coating) layer, a SOG (spin-on-glass) layer, or a SOC (spin-on-carbon) layer, and may be deposited by spin coating or any suitable deposition technique. InFIG.24, the portions of the mask layer189and the dummy material183not covered by the resist layer191are removed. The removal of the portions of the mask layer189and the dummy material183may reveal portions of the HK dielectric layer180over the fin structures112a,112b. The removal process used to remove the mask layer189and the dummy material183may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The removal of the mask layer189and the dummy material183may be performed by multiple etch processes. In some embodiments, a first etch process is performed to remove the exposed portions of the mask layer189. The first etch process may be a selective etch process that removes the mask layer189but not the HK dielectric layer180. After the exposed mask layer189is removed, a second etch process is performed to remove the exposed portions of the dummy material183. Likewise, the second etch process may be a selective etch process that removes the dummy material183but not the HK dielectric layer180. Due to the narrow spacing at the end cap regions181(FIG.20), the second etch process may use an etchant heavier than the etchant used in the first etch process in order to etch through the materials at the end cap regions181. As indicated previously, the mask layer189protects the dummy material183at the p-channel FETs (e.g., p-channel FETs on the fin structure112c) from being over-etched during removal of the dummy material183at the n-channel FETs. If the removal process was performed without the mask layer189formed between the resist layer191and the HK dielectric layer180, the etchant used during the removal of the dummy material183at the n-channel FETs (n-channel FETs on the fin structure112b) may spread over to the dummy material183at the p-channel FETs along the dummy material183between the resist layer191and the HK dielectric layer180on the top surface of the dielectric layer140, leading to unwanted etching of the dummy material183under the resist layer191. InFIG.25, the resist layer191and the mask layer189are removed. The resist layer191may be removed by any suitable removal process, such as ashing, dry etch, wet etch, or a combination thereof. Then, the mask layer189remaining on the HK dielectric layer180is removed. The removal process for the mask layer189may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The removal process may be a selective etch process that removes the mask layer189but does not remove the HK dielectric layer180and the dummy material183at the end cap region181. The air gaps187remain intact since the removal process does not remove the dummy material183on the fin structure112c. Upon removal of the resist layer191and the mask layer189, the dummy material183at the end cap region181is exposed. The dummy material183remains in contact with portions of the HK dielectric layer180formed over the second dielectric feature134and the first semiconductor layers106of the fin structure112c. InFIG.26, after the resist layer191and the mask layer189are removed, a first gate electrode layer182is formed on the exposed surfaces of the semiconductor device structure100. The first gate electrode layer182is formed on the HK dielectric layer180to surround a portion of each first semiconductor layer106and on the HK dielectric layer180that is in contact with the dielectric layer140and the first and second dielectric features130,134. The first gate electrode layer182may be also deposited over the first and second dielectric features130,134. The first gate electrode layer182may have a thickness in a range of about 0.5 nm to about 2.5 nm. Since the spacing D3(FIG.19A) of the end cap regions181is smaller than the spacing D4(FIG.19A) of the channel-to-channel regions185, the first gate electrode layer182formed over the first semiconductor layers106and the first gate electrode layer182formed over the first and second dielectric features130,134are eventually merged as the thickness of the first gate electrode layer182increases. The first gate electrode layer182merged at the end cap regions181prevents the subsequent first gate electrode layer182from filling in the channel-to-channel regions185between the first semiconductor layers106, resulting in air gaps187′ formed in the channel-to-channel regions185. The air gaps187′ has a spacing D6in a range about 2 nm to about 5 nm, which may vary according to the channel-to-channel spacing D4(FIG.19A) and the thickness of the IL178, the HK dielectric layer180, and the first gate electrode layer182. The first gate electrode layer182includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The first gate electrode layers182may be formed by PVD, CVD, ALD, electro-plating, or other suitable method. In some embodiments, the first gate electrode layer182includes an n-type gate electrode layer such as TiAlC, TaAlC, TiSiAlC, TiC, TaSiAlC, or other suitable material. InFIG.27, a resist layer191′ is formed on one or more exposed portions of the first gate electrode layer182. The resist layer191′ can be formed in the selected regions depending on the needs to control the gates at different FETs. In some embodiments, the resist layer191′ is formed to cover regions of n-channel FETs and p-channel FETs, such as the n-channel FET formed on the fin structure112band p-channel FET formed on the fin structure112aas shown inFIG.27. The resist layer191′ protects the one or more of the portions of the first gate electrode layer182so that the unprotected portions of the first gate electrode layer182are removed and replaced by the subsequently formed second gate electrode layer184(FIG.29). The resist layer191′ may include or be formed of the same material as the resist layer191discussed above and may be deposited by the same deposition process. Next, portions of the first gate electrode layer182not covered by the resist layer191′ are removed. The removal process uses an etchant that selectively removes the first gate electrode layer182but not the HK dielectric layer180and the dummy material183. The exposed first gate electrode layer182is removed to expose the dummy material183at the end cap region181of the first semiconductor layer106. Since the first gate electrode layer182is not merged at the end cap region181, the removal process may use a lighter etchant for removing the first gate electrode layer182. While removing the dummy material183, a small portion of the exposed first gate electrode layer182between the resist layer191′ and the HK dielectric layer180over the first dielectric feature130may be slightly etched. Since the etchant is lighter, it does not get spread over to the first gate electrode layer182at the n-channel FET formed on the fin structure112band p-channel FET formed on the fin structure112a. InFIG.28, after the portions of the first gate electrode layer182is removed, a removal process is performed to remove the exposed dummy material183. The removal process may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The removal process may be a selective etch process that removes the dummy material183but not the HK dielectric layer180and the first gate electrode layer182. Due to the narrow spacing at the end cap regions181(FIG.20), the selective etch process may use an etchant heavier than the etchant used for removing the first gate electrode layer182in order to etch through the materials at the end cap regions181. Upon removal of the dummy material183, the HK dielectric layer180not covered by the resist layer191′ (the HK dielectric layer180surrounding portions of the first semiconductor layers106of the fin structure112cand on the dielectric structure141) is exposed. InFIG.29, after the dummy material183is removed, a second gate electrode layer184is formed on the exposed surfaces of the semiconductor device structure100. The second gate electrode layer184is formed on the HK dielectric layer180to surround a portion of each first semiconductor layer106of the fin structure112c(i.e., p-channel FET formed on the fin structure112c) and on the HK dielectric layer180that is in contact with the dielectric layer140and the second dielectric feature134. The second gate electrode layer184is also in contact with the first gate electrode layer182of n-channel FETs and p-channel FETs, such as the n-channel FET formed on the fin structure112band p-channel FET formed on the fin structure112a. The second gate electrode layer184may be also deposited over the first and second dielectric features130,134. The second gate electrode layer184may have a thickness in a range of about 0.5 nm to about 2.5 nm. Due to the narrower spacing at the end cap region181(between the dielectric structure141and the distal ends of the first semiconductor layers106of the fin structure112c), the second gate electrode layer184is eventually merged at the end cap region181as the thickness of the second gate electrode layer184increases. The second gate electrode layer184merged at the end cap region181prevents the subsequent second gate electrode layer184from filling in the channel-to-channel regions185between the first semiconductor layers106, resulting in air gaps187″ formed in the channel-to-channel regions185. The air gaps187″ has a spacing D7in a range about 2 nm to about 5 nm, which may vary according to the channel-to-channel spacing D4(FIG.19A) and the thickness of the IL178, the HK dielectric layer180, and the second gate electrode layer184. The second gate electrode layer184includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The second gate electrode layers184may be formed by PVD, CVD, ALD, electro-plating, or other suitable method. In some embodiments, the second gate electrode layer184includes a p-type gate electrode layer such as TiN, TaN, TSN, Mo, TiSiN, TiTaN, TiAlN, WCN, W, Ni, Co, or other suitable material. Depending on the threshold voltage needed for the n-channel FETs and p-channel FETs at different regions of the semiconductor device structure100, one or more p-type or n-type gate electrode layers may be further formed on the second gate electrode layer184. It is contemplated that the thickness of each gate electrode layer may also be controlled to adjust the work function of the gate electrode. FIGS.30A and30Bare cross-sectional side views of one of various stages of manufacturing the semiconductor device structure100taken along cross-section A-A and cross-section B-B ofFIG.29, respectively, in accordance with some embodiments.FIG.30Ashows each nanosheet channel has a length L1in a range of about 6 nm to about 14 nm. The length of the nanosheet channel herein refers to a lateral length of the first semiconductor layers106between two adjacent spacers154. InFIG.31, a metal layer186is formed on the exposed surfaces of the semiconductor device structure100.FIGS.32A and32Bare cross-sectional side views of the semiconductor device structure100taken along cross-section A-A and cross-section B-B ofFIG.31, respectively, in accordance with some embodiments. The metal layer186is formed in the space defined between two adjacent dielectric structures141(e.g., between the first and second dielectric features130,134, between two adjacent first dielectric features130, or between two adjacent second dielectric features134) and in contact with the first gate electrode layer182, the second gate electrode layer184, the HK dielectric layer180, the spacers154, and the CESL162. The metal layer186may provide a signal, such as an electrical current, to the second gate electrode layer184located therebelow. In the embodiment shown inFIG.31, since a portion of the first gate electrode layer182is in contact with the second gate electrode layer184, the signal can be provided to both first and second gate electrode layers182,184via the metal layer186. In such a case, a single signal sent to the metal layer186may control nanosheet channel regions in both n-channel FET and p-channel FET. The metal layer186may include or be formed of W, Ru, Mo, Co, TaN, Cu, Ti, Ta, TiN, or the like. The metal layer186may be formed by PVD, CVD, ALD, or other suitable process. The metallic surfaces of the multiple layers of work function of metal of the gate electrode layers182,184promote preferential growth of the metal layer186on the first and second gate electrode layers182,184over the dielectric material of the spacers154and the CESL162. Thus, the metal layer186may be formed in a bottom-up fashion. In some embodiments, the metal layer186is optional and may not exist. FIGS.33A and33Bare cross-sectional side views of one of various stages of manufacturing the semiconductor device structure100taken along cross-section A-A and cross-section B-B ofFIG.31, respectively, in accordance with some embodiments. InFIGS.33A and33B, one or more metal gate etching back (MGEB) processes are performed to remove portions of the metal layer186, the second gate electrode layer184, and the HK dielectric layer180over the fin structure112c. A resist layer, such as the resist layer191′ shown inFIG.28, may be deposited over the n-channel FETs and p-channel FETs, such as the n-channel FET formed on the fin structure112band p-channel FET formed on the fin structure112a, before performing the MGEB process on the p-channel FETs, such as the p-channel FET on the fin structure112c. The MGEB processes are performed so that the top surfaces of the second gate electrode layer184and the HK dielectric layer180are substantially co-planar. In some embodiments, portions of the spacers154are also etched back so that the top surface of the spacers154is higher than the top surfaces of the second gate electrode layer184and the HK dielectric layer180, as shown inFIG.33A. After the MGEB process is performed on the p-channel FETs, one or more MGEB processes are performed to remove the first gate electrode layer182, the second gate electrode layer184, and the HK dielectric layer180. Likewise, a resist layer, such as the resist layer191shown inFIG.24, may be deposited over the p-channel FETs, such as the p-channel FET on the fin structure112c, before performing the MGEB process on the n-channel FETs and p-channel FETs, such as the n-channel FET formed on the fin structure112band p-channel FET formed on the fin structure112a. The MGEB processes are performed so that the top surfaces of the first gate electrode layer182, the second gate electrode layer184, and the HK dielectric layer180are substantially co-planar. In some embodiments, portions of the spacers154are also etched back so that the top surface of the spacers154is higher than the top surfaces of the first gate electrode layer182, the second gate electrode layer184, and the HK dielectric layer180, as shown inFIG.33B. By etching the spacers154below the CESL162, the spacers154can be protected by the subsequently formed SAC layer188while forming source/drain metal contacts. In addition, keeping the spacers154at a level higher than the HK dielectric layer180and the first and second gate electrode layer182,184allows the first and second gate electrode layer182,184remain protected by the spacers154. Next, a self-aligned contact (SAC) layer188is filled in the trenches formed above the metal layer186as a result of the MGEB processes. The SAC layer188can be used as an etch stop layer during subsequent trench and via patterning for metal contacts. The SAC layer188may be any dielectric material that has different etch selectivity than the CESL layer162and the subsequently formed source/drain metal contact (e.g., S/D contacts190inFIGS.34A and34B). Suitable materials for the SAC layer188may include, but are not limited to, SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, SiOCN, ZrN, SiCN, or any combinations thereof. The SAC layer188may be formed by a suitable deposition process, such as CVD, FCVD, PVD, or ALD. Alternatively, the SAC layer188is optional and may not exist. After filling the trenches with the SAC layer188, a planarization process, such as a CMP process, is performed to remove excess deposition of the SAC layer188to expose the top surface of the ILD layer164, as shown inFIGS.33A and33B. FIGS.34A and34Bare cross-sectional side views of one of various stages of manufacturing the semiconductor device structure100taken along cross-section A-A and cross-section B-B ofFIG.31, respectively, in accordance with some embodiments. InFIGS.34A and34B, S/D contracts190are formed through the ILD layer164and the CESL162to be in contact with the epitaxial S/D features160via a silicide layer139. The S/D contracts190may be made of a material including one or more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN and TaN, any suitable metal material, and can be formed by CVD, ALD, electro-plating, or other suitable deposition technique. The silicide layers139may be made of a metal or metal alloy silicide, and the metal includes a noble metal, a refractory metal, a rare earth metal, alloys thereof, or combinations thereof. For n-channel FETs, the silicide layers139may be made of a material including one or more of TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, or combinations thereof. For p-channel FETs, the silicide layers139may be made of a material including one or more of NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or combinations thereof. Once the S/D contracts190are formed, a planarization process, such as CMP, is performed to expose the top surface of the SAC layer188(or top surface of the metal layer186if the SAC layer188was not used). FIG.35is an exemplary layout diagram200of a section of an IC circuit in accordance with some embodiments. The layout diagram200includes a cell structure206having cells210,250. The cell210includes first, second, and third transistor regions211,212,213, gates214, source and drain (S/D) region216, and active regions217,218,219. The gates214have S/D region216disposed on either side thereof. The active regions217,218,219each includes fin structures, such as fin structures112a,112bshown inFIG.31. The active regions217,218,219extend from left to right cell boundaries207of the cell210. The active regions217,218,219are separated by either a portion of the substrate or an isolation structure220. Metal portion “M” are coupled to the gates214to connect circuit elements. A dielectric feature225, such as the dielectric feature130shown inFIG.31, is formed between and coupled to two adjacent fin structures in the active regions217,218,219to form forksheet transistors. The cell250includes first, second, and third transistor regions251,252,253, gates254, source and drain (S/D) region256, and active regions257,258,259. The gates254have S/D region256disposed on either side thereof. The active regions257,258,259each includes fin structures extending from left to right cell boundaries209of the cell250. The active regions257,258,259are separated by either a portion of the substrate or an isolation structure260. Metal portion “M” are coupled to the gates254to connect circuit elements. The cell structure206further includes a plurality of conductors232,234,236alternately arranged and extended across the cell structure206along the X-axis. The conductors232,236are coupled to power supply VDD, and the conductor234is coupled to power supply VSS. The layout diagram200are arranged with respect to track lines, including track lines205(1),205(2),205(3), . . . ,205(10), and205(11), which are oriented substantially parallel to the X-axis. Track lines205(1)-205(11) have a pitch “TP”, determined by the design rules and scale of the corresponding semiconductor process technology node. The track lines205(1)-205(11) are formed in a metal layer at a different level (i.e., above the transistor level) and are used to route signal (interconnect) lines for passing signals between the cells. A standard cell's height is determined by the number of horizontal tracks extending between the uppermost and lowermost cell boundaries207,209of the cells210,250, respectively. Standard cells typically range in height from approximately 7 to 15 tracks, for example. In the embodiment shown inFIG.35, each of the transistor regions211,212,213in the cell210employs forksheet transistors formed in accordance with various embodiments of the present disclosure, such as the forksheet transistor shown in the semiconductor device100ofFIG.31. That is, the nanosheet channels of the forksheet transistors in each of the transistor regions211,212,213in the cell210have distal ends formed at a reduced distance to adjacent dielectric features, that is, reduced end cap region (e.g., end cap region181between distal ends of the first semiconductor layers106and sidewalls of the dielectric features130,134as shown inFIG.19A). In contrast, each of the transistor regions251,252,253in the cell250employ traditional nanosheet transistor which does not require a dielectric isolation between n-type and p-type transistors. Therefore, while both cells210,250occupy the same number of the track lines205(1)-205(11), the overall density of the active transistors in each transistor region211,212,213is increased due to narrower end cap region of the inventive forksheet transistors. The increased density of the active transistors represents a reduction in cell's height of the cell210as compared to the cell250. It is understood that the semiconductor device structure100may undergo further complementary metal oxide semiconductor (CMOS) and/or back-end-of-line (BEOL) processes to form various features such as transistors, contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure100may also include backside contacts (not shown) on the backside of the substrate101by flipping over the semiconductor device structure100, removing the substrate101, and selectively connecting source or drain feature/terminal of the epitaxial S/D features160to a backside power rail (e.g., positive voltage VDD or negative voltage VSS) through the backside contacts. The present disclosure provides a semiconductor device structure including one or more nanosheet channels extended from two opposing sides of a dielectric feature to form a forksheet transistor. The dielectric structure is disposed between p-channel FET and n-channel FET devices. The distal ends of nanosheet channels of the forksheet transistor are formed at a reduced distance to adjacent dielectric features so that a subsequent gate electrode layer is merged at a region formed between the distal ends of the nanosheet channels of the forksheet transistor and the adjacent dielectric features. The improved forksheet transistor allows a further reduction of cell-height and overall cell area reduction. An embodiment is a semiconductor device structure. The structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap. Another embodiment is a semiconductor device structure. The structure includes a first dielectric feature having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer extending laterally from the first sidewall, a second semiconductor layer extending laterally from the second sidewall, a third semiconductor layer extending laterally from the first sidewall, the third semiconductor layer being parallel to and spaced apart from the first semiconductor layer by a first spacing, a fourth semiconductor layer extending laterally from the second sidewall and being parallel to the second semiconductor layer, a first gate electrode layer surrounding at least three surfaces of each of the first and third semiconductor layers, and a second dielectric feature disposed adjacent to the first and third semiconductor layers, the second dielectric feature being spaced apart from the first and third semiconductor layers by a second spacing, wherein the second spacing is smaller than the first spacing. A further embodiment is a method. The method includes forming first and second fin structures from a substrate, wherein the first fin includes a first plurality of semiconductor layers, and the second fin includes a second plurality of semiconductor layers, wherein each of the first and second plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers, forming a first dielectric feature between the first plurality of semiconductor layers and the second plurality of semiconductor layers, forming a second dielectric feature adjacent the first plurality of semiconductor layers, forming a third dielectric feature adjacent the second plurality of semiconductor layers, forming a sacrificial gate stack on a portion of the first fin, the second fin, and the first, second, and third dielectric features, wherein a portion of the first fin, the second fin, and the first, second, and third dielectric features are exposed, removing a portion of exposed portions of the first and second fins not covered by the sacrificial gate stack, removing the sacrificial gate stack to expose portions of the first and second fins, removing the second semiconductor layers of the first and second plurality of semiconductor layers so that the first semiconductor layers are spaced apart from each other by a first spacing, and the second dielectric feature is spaced apart from the first semiconductor layers by a second spacing smaller than the first spacing, and forming a first gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first plurality of semiconductor layers, wherein the first gate electrode layer is exposed to a first air gap. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 82,489 |
11862701 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term encompasses numbers that are within certain variations (such as +/−10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term “about 5 nm” may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc. This application generally relates to semiconductor structures and fabrication processes, and more particularly to integrate circuit (IC) chips having stacked transistors with different active channel layer numbers. In various embodiments, at least two gate-all-around (GAA) transistors with different (or varying) numbers of active channel layers are stacked on top of one another. The different numbers of active channel layers help to obtain balanced driving currents from the GAA transistor on the top and the GAA transistor at the bottom. The two stacked GAA transistors may have the same number of semiconductor channel layers (or referred to as channel layers) but at least one or more are floating ones that leads to different numbers of active channel layers, according to various aspects of the present disclosure. The pair of stacked GAA transistors can be of opposite conductivity types, such as one n-type FET (nFET) over one p-type FET (pFET), or vice versa, or of the same conductivity type, such as two stacked nFETs or two stacked pFETs. Further, one IC chip may include two regions, one having stacked GAA transistors with the same number of active channel layers, and another having stacked GAA transistors with different numbers of active channel layers, fitting different application needs on one chip. The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanied drawings, which illustrate a process of making stacked GAA transistors, according to some embodiments. A GAA transistor refers to a transistor having vertically-stacked horizontally-oriented channel layers, such as nanowires, nanosheets, other nanostructures, and/or other appreciable variations. Stacked GAA devices are promising candidates to take CMOS to the next stage of the roadmap due to their high device density, better gate control ability, lower leakage current, and fully FinFET device layout compatibility. Stacked GAA transistors refer to two or more GAA transistors vertically stacked on one another. The stacked GAA transistors may be of the same conductivity type (n-type or p-type) or different conductivity types (n-type and p-type). Channel layers of the GAA transistors may share the same gate structure, e.g., a common gate structure. Alternatively, each GAA transistor may have its own individual gate structure. The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIGS.1,17,34,51,68, and85are flowcharts illustrating methods100,300,500,700,900, and1100of forming a semiconductor device from a workpiece according to embodiments of the present disclosure. Methods100,300,500,700,900, and1100are merely examples and are not intended to limit the present disclosure to what is explicitly illustrated in methods100,300,500,700,900, and1100. Additional steps can be provided before, during and after the methods100,300,500,700,900, and1100, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the methods. Not all steps are described herein in detail for reasons of simplicity. Methods100,300,500,700,900, and1100are described below in conjunction withFIGS.2A-16C,18A-33C,35A-50C,52A-67C,69A-84C,86A-98C, respectively, which are fragmentary cross-sectional views of the workpiece at different stages of fabrication according to embodiments of methods100,300,500,700,900, and1100.FIGS.99-100provides fragmentary cross-sectional views along a channel region that provide summary and further illustrate alternative embodiments according to various aspects of the present disclosure. For better illustration of various aspects of the present disclosure, each of the figures ending with the capital letter A illustrates a fragmentary cross-sectional view along a channel region (i.e., a cut along a lengthwise direction of a channel layer), each of the figures ending with the capital letter B illustrates a fragmentary cross-sectional view of a source region (i.e., a cut in a source region that is perpendicular to the lengthwise direction of a channel layer), and each of the figures ending with the capital letter C illustrates a fragmentary cross-sectional view of a drain region (i.e., a cut in a drain region that is perpendicular to the lengthwise direction of a channel layer). Referring toFIGS.1and2A-C, method100includes a block102where a workpiece200is provided. It is noted that because the workpiece200will be fabricated into a semiconductor device, the workpiece200may also be referred to as the semiconductor device (or device)200as the context requires. The workpiece200may include a substrate portion202and a stack portion204disposed above the substrate portion202. The substrate portion202may also be referred to as the substrate202. Although not explicitly shown in the figures, the substrate202may include an n-type well region and a p-type well region for fabrication of transistors of different conductivity types. In one embodiment, the substrate202may be a silicon (Si) substrate. In some other embodiments, the substrate202may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate202may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. When present, each of the n-type well and the p-type well is formed in the substrate202and includes a doping profile. An n-type well may include a doping profile of an n-type dopant, such as phosphorus (P) or arsenic (As). A p-type well may include a doping profile of a p-type dopant, such as boron (B). The doping in the n-type well and the p-type well may be formed using ion implantation or thermal diffusion and may be considered portions of the substrate202. For avoidance of doubts, the X direction, the Y direction and the Z direction are perpendicular to one another. As shown inFIGS.2A-C, the stack portion204includes a plurality of channel layers208interleaved by a plurality of sacrificial layers206. The channel layers208and the sacrificial layers206may have different semiconductor compositions. In some implementations, the channel layers208are formed of silicon (Si) and sacrificial layers206are formed of silicon germanium (SiGe). In these implementations, the additional germanium content in the sacrificial layers206allow selective removal or recess of the sacrificial layers206without substantial damages to the channel layers208. In some embodiments, the sacrificial layers206and channel layers208are epitaxy layers and may be deposited using an epitaxy process. Suitable epitaxy processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes. The sacrificial layers206and the channel layers208are deposited alternatingly, one-after-another, to form the stack portion204. As explained in greater detail below, the channel layers208in the bottom portion of the stack portion204will provide channel members of a bottom GAA transistor, and the channel layers208in the top portion of the stack portion204will provide channel members of a top GAA transistor. The term “channel member(s)” is used herein to designate any material portion for channel(s) in a transistor with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. Accordingly, the channel layers208in the bottom portion of the stack portion204and respective interleaved sacrificial layers206collectively define a first stack204a, and the channel layer208in the top portion of the stack portion204and respective interleaved sacrificial layers206collectively define a second stack204b. The one sacrificial layer206sandwiched between the first stack204a and the second stack204bis particularly denoted as the middle sacrificial layer206M. State differently, the first stack204aincludes sacrificial layers206and channel layers208below the middle sacrificial layer206M, and the second stack204bincludes sacrificial layers206and channel layers208above the middle sacrificial layer206M. It is noted that three (3) layers of the channel layers208in the first stack204aand an equal number of the channel layers208in the second stack204bare illustrated inFIGS.2A-C, which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of the channel layers208can be independently formed in the first stack204aand the second stack204b. The number of layers depends on the desired number of channels members for the device200. In some embodiments, the number of the channel layers208in each stack is between 2 and 10. In some embodiments, each sacrificial layer206has a thickness ranging from about 2 nanometers (nm) to about 6 nm. The sacrificial layers206may be substantially uniform in thickness. Yet in the illustrated embodiment, the middle epitaxial layer206M is thicker (e.g., double or triple the thickness) than other epitaxial layers206. In some embodiments, each channel layer208has a thickness ranging from about 6 nm to about 12 nm. In some embodiments, the channel layers208of the stack are substantially uniform in thickness. The thickness of each sacrificial layer206and channel layer208is chosen based on device performance considerations. Referring toFIGS.1and3A-C, method100includes a block104where a fin-shaped structure209is formed from the stack portion204. In some embodiments, the stack portion204and a top portion of the substrate202are patterned to form the fin-shaped structure209. For patterning purposes, a hard mask layer may be deposited over the stack portion204. The hard mask layer may be a single layer or a multilayer. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. As shown inFIGS.3A-C, the fin-shaped structure209extends vertically along the Z direction from the substrate202and extends lengthwise along the X direction. The fin-shaped structure209includes a base portion209B formed from the substrate202and a stack portion209S formed from the stack of channel layers208and interleaved sacrificial layers206. The fin-shaped structure209may be patterned using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin-shaped structure209by etching the stack portion204and the substrate202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In some implementations shown inFIGS.3A-C, after the fin-shaped structure209is formed, a first liner210may be deposited conformally over the workpiece200. The first liner210may include silicon nitride and may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD). Still referring toFIGS.1and3A-C, method100includes a block106where buried power rails (or referred to as bottom power rails)211are formed. In some embodiments, before the first liner210is etched back, a metal layer for the buried power rails211is deposited over the workpiece200using metal-organic CVD or PVD. The deposited metal layer is recessed to form buried power rails211. The metal layer for the buried power rails211may include tungsten (W), ruthenium (Ru), copper (Cu), aluminum (Al), silver (Ag), molybdenum (Mo), rhenium (Re), iridium (Ir), cobalt (Co), or nickel (Ni). In the depicted embodiment, each of the buried power rails211includes a width W between about 40 nm and 80 nm and a height H between about 30 nm and about 50 nm. As shown inFIGS.3A-C, the buried power rails211includes a first buried power rail211-1and a second buried power rail211-2. Referring toFIGS.1and4A-C, method100includes a block108where an isolation feature214is formed. In some embodiments, to protect the buried power rails211from oxidation, a second liner213is deposited over the buried power rails211. The second liner213may be similar to the first liner210in terms of composition and formation. As shown inFIGS.4A-C, the buried power rails211are sandwiched by the first liner210and the second liner213. The isolation feature214is then formed over the second liner213. The isolation feature214may also be referred to as a shallow trench isolation (STI) feature214. In an example process, a dielectric material for the isolation feature214is deposited over the first liner210using CVD, subatmospheric CVD (SACVD), flowable CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), spin-on coating, and/or other suitable process. Then the deposited dielectric material is planarized and recessed until the fin-shaped structure209rises above the isolation feature214. That is, after the recess of the isolation feature214, the base portion209B of the fin-shaped structure209is surrounded by the isolation feature214. The dielectric material for the isolation feature214may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. After the isolation feature214is formed, the first liner210and the second liner213are selectively recessed until the stack portion204of the fin-shaped structure209is exposed. Referring toFIGS.1and5A-C, method100includes a block110where a dummy gate stack222is formed over the stack portion204. In some embodiments, a gate replacement process (or gate-last process) is adopted where the dummy gate stack222serves as placeholders for a functional gate structure. Other processes and configuration are possible. To form the dummy gate stack222, a dummy dielectric layer216, a dummy gate electrode layer218, and a gate-top hard mask layer220are deposited over the workpiece200. The deposition of these layers may include use of low-pressure CVD (LPCVD), CVD, plasma-enhanced CVD (PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. The dummy dielectric layer216may include silicon oxide, the dummy gate electrode layer218may include polysilicon, and the gate-top hard mask layer220may be a multi-layer that includes silicon oxide and silicon nitride. Using photolithography and etching processes, the gate-top hard mask layer220is patterned. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. The etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. Thereafter, using the patterned gate-top hard mask220as the etch mask, the dummy dielectric layer216and the dummy gate electrode layer218are then etched to form the dummy gate stack222. The dummy gate stack222extends lengthwise along the Y direction to wrap over the fin-shaped structure209and lands on the isolation feature214. The portion of the fin-shaped structure209underlying the dummy gate stack222is a channel region. The channel region and the dummy gate stack222also define source/drain regions that are not vertically overlapped by the dummy gate stack222. The channel region is disposed between two source/drain regions along the X direction. Referring toFIGS.1and6A-C, method100includes a block112where source/drain portions of the fin-shaped structure209are recessed to form source/drain recesses224. Operations at block112may include formation of a gate spacer layer223over the sidewalls of the dummy gate stack222before the source/drain portions of the fin-shaped structure209are recessed. In some embodiments, the formation of the gate spacer layer223includes deposition of one or more dielectric layers over the workpiece200. In an example process, the one or more dielectric layers are deposited using CVD, SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and/or combinations thereof. In an example process, after the deposition of the gate spacer layer223, the workpiece200is etched in an etch process that selectively recesses the source/drain regions of the fin-shaped structure209. The selective recess of the source/drain regions results in source/drain trenches224between adjacent dummy gate stacks222. The etch process at block112may be a dry etch process or a suitable etch process. An example dry etch process may implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. As shown inFIG.6A, sidewalls of the sacrificial layers206and the channel layers208in the channel region are exposed in the source/drain trenches224. Referring toFIGS.1and7A-C, method100includes a block114where inner spacer features226are formed. At block114, the sacrificial layers206, including the middle sacrificial layer206M, exposed in the source/drain trenches224are selectively and partially recessed to form inner spacer recesses, while the exposed channel layers208are substantially unetched. In an embodiment where the channel layers208consist essentially of silicon (Si) and sacrificial layers206consist essentially of silicon germanium (SiGe), the selective and partial recess of the sacrificial layers206may include a SiGe oxidation process followed by a SiGe oxide removal. In that embodiments, the SiGe oxidation process may include use of ozone (O3). In some other embodiments, the selective recess may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent at which the sacrificial layers206are recessed is controlled by duration of the etching process. The selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include a hydro fluoride (HF) or NH4OH etchant. After the formation of the inner spacer recesses, an inner spacer material layer is deposited over the workpiece200, including in the inner spacer recesses. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess inner spacer material layer over the gate spacer layer and sidewalls of the channel layers208, thereby forming the inner spacer features226as shown inFIG.7A. In some embodiments, the etch back process at block114may be a dry etch process that includes use of an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas (e.g., CF3I), other suitable gases and/or plasmas, and/or combinations thereof. Referring toFIGS.1and8A-C, method100includes a block118where a sacrificial dielectric layer215is deposited in the source/drain trenches224. The sacrificial dielectric layer215may include silicon oxide, silicon oxycarbide, or a dielectric material that allows selective etching of the sacrificial dielectric layer215while keeping the inner spacer features226substantially intact. The sacrificial dielectric layer215may be deposited using CVD. Then the sacrificial dielectric layer215is etched back to expose the second stack204b, while sidewalls of the first stack204aremains covered. That is, after the etching back of the sacrificial dielectric layer215, sidewalls of the channel layers208of the second stack204band respective inner spacer features interleaved therein are exposed in the source/drain trenches224. The etch process may be a dry etch process, a wet etch process, or a suitable etch process. The extent at which the sacrificial dielectric layer215are recessed is controlled by duration of the etching process. Operations at block118also includes conformally depositing a third liner225over the workpiece200. The sidewalls of the first stack204bare covered by the third liner225. The third liner225may include silicon nitride, silicon carbonitride, or other suitable dielectric material that provides etching contrast to the sacrificial dielectric layer215. The third liner225may be deposited using CVD, ALD, or other suitable deposition process. Referring toFIGS.1and9A-C, method100includes a block120where lateral portion of the third liner225is removed. By using an anisotropic etching, such as RIE or other suitable dry etch process, vertical portion of the third liner225remains covering the sidewalls of the second stack204b, while lateral portion of the third liner225is removed from the source/drain trenches224, exposing the sacrificial dielectric layer215. Operations at block120also includes removing the sacrificial dielectric layer215in a selective etch process to release the first stack204a. In an example where the sacrificial dielectric layer215is formed of an oxide and the inner spacer features226and the third liner225are formed of nitrides, the sacrificial dielectric layer215may be selectively removed using diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). Here, BHF includes hydrofluoric acid and ammonium fluoride. Upon conclusion of the operations at block120, the sidewalls of the channel layers208of the first stack204aare exposed in the source/drain trenches224, while the sidewalls of the channel layers208of the second stack204band a top portion of the middle sacrificial layer206M remain covered by the third liner225. Referring toFIGS.1and10A-C, method100includes a block122where a first source feature228S and a first drain feature228D are formed in the source/drain trenches224. In some embodiments, the first source feature228S and the first drain feature228D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the composition of the substrate202as well as the channel layers208. The exposed sidewalls of the channel layers208of the first stack204afunctionally serve as semiconductor seed layers. Therefore, the epitaxial growth of the first source feature228S and the first drain feature228D may take place from both the top surface of the substrate202and the exposed sidewalls of the channel layers208of the first stack204a. As illustrated inFIG.10A, the first source feature228S and the first drain feature228D are therefore in physical contact with (or adjoining) the channel layers208or the released channel of the first stack204a. Since the channel layers208in the second stack204bare covered by the third liner225, epitaxial growth won't take place from the sidewalls thereof. The duration of the epitaxial growth is controlled such that the first source feature228S and the first drain feature228D do not extend upwardly beyond the middle sacrificial layer206M. Depending on the conductivity type of the to-be-formed bottom GAA transistor, the first source feature228S and the first drain feature228D may be n-type source/drain features or p-type source/drain features. Example n-type source/drain features may include Si, GaAs, GaAsP, SiP, or other suitable material and may be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus (P), arsenic (As), or ex-situ doped using an implantation process (i.e., a junction implant process). Example p-type source/drain features may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable material and may be in-situ doped during the epitaxial process by introducing a p-type dopant, such as boron (B), or ex-situ doped using an implantation process (i.e., a junction implant process). Referring toFIGS.1and11A-C, method100includes a block126where a first contact etch stop layer (CESL)230and a first interlayer dielectric (ILD) layer232are deposited on the first source feature228S and the first drain feature228D. Operations at block126includes removal of the third liner225to release the second stack204bin an etching process. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. The first CESL230may include silicon nitride, silicon oxynitride, and/or other materials known in the art and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the first CESL230is first conformally deposited on the workpiece200and the first ILD layer232is deposited over the first CESL230by a PECVD process or other suitable deposition technique. Subsequently the first CESL230and the first ILD layer232are etched back in a selective etching process. Both the first CESL230and the first ILD layer232are recessed below the bottommost channel layer208of the second stack204b. Upon conclusion of the operations at block126, the first CESL230is conformally deposited on surfaces of the first source feature228S, the first drain features228D, and partially on the sidewalls of the middle sacrificial layer206M. The first ILD layer232may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, after formation of the first ILD layer232, the workpiece200may be annealed to improve integrity of the first ILD layer232. Referring toFIGS.1and12A-C, method100includes a block128where interconnection features, such as a first drain contact234, a first source contact236, a first source contact via238are formed. Taking interconnection features in the source region to illustrate an example process, lithography processes are used to form a contact opening that exposes the first source feature228S. Additional lithography processes may be used to form a via opening for the first source contact via238and the via opening extends through at least the CESL230and the isolation feature214and exposes the first buried power rail211-1. To reduce contact resistance, a silicide layer240may be formed on the first source feature228S by depositing a metal layer over the first source feature228S and performing an anneal process to bring about silicidation between the metal layer and the first source feature228S. Suitable metal layer may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The silicide layer240may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). After the formation of the silicide layer240, a metal fill layer may be deposited into the contact opening and the contact via openings. The metal fill layer may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). Similar to the first source contact236, a contact opening is first made to expose the first drain feature228D, a silicide layer240is formed on the first drain feature228D, and a metal fill layer is deposited to fill the rest of the contact opening to form the first drain contact234. A contact etch back process may follow to remove excess material to recess a top surface to the first drain contact234and the first source contact236below the bottommost channel layer208of the second stack204b. Notably, a source and a drain can be interchangeably used in various other embodiments, such as interconnection features electrically couple the first drain feature228D to the first buried power rail211-1in one embodiment. Still referring toFIGS.1and12A-C, method100includes a block130where a dielectric isolation layer242is deposited over the first ILD layer232and covering interconnection features formed in earlier operations at block128. The dielectric isolation layer242may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer242may be formed by filling the source/drain trenches224with dielectric isolation material (e.g., by using a CVD process or a spin-on glass process), and etching back the dielectric isolation material in a selective etching process. As shown inFIG.12A, the dielectric isolation layer242covers opposite sidewalls of at least the bottommost channel layer208of the second stack204b. In some embodiments, the dielectric isolation layer242adjoins more than one bottom channel layers208in the second stack204b. Referring toFIGS.1and13A-C, method100includes a block132where a second source feature248S and a second drain feature248D are formed in the source/drain trenches224. Similar to the first source feature228S and the first drain feature228D, the second source feature248S and the second drain feature248D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the channel layers208. The exposed sidewalls of the channel layers208of the second stack204bfunctionally serve as semiconductor seed layers. Therefore, the epitaxial growth of the second source feature248S and the second drain feature248D may take place from the exposed sidewalls of the channel layers208of the second stack204b, but not from the ones adjoined by the dielectric isolation layer242. As illustrated inFIG.13A, the second source feature248S and the second drain feature248D are therefore in physical contact with (or adjoining) the upper channel layers208of the second stack204b, forming active channel layers. The term “active channel layer” refers to a channel layer adjoined by source/drain features on both ends such that carriers can travel through. Since the bottommost channel layer208in the second stack204bis covered by the dielectric isolation layer242, epitaxial growth won't take place from the sidewalls thereof. Isolated form the second source feature248S and the second drain feature248D by the dielectric isolation layer242, the bottommost channel layer208of the second stack204bbecomes a “floating” (or inactive) channel layer. The term “floating channel layer” refers to a channel layer insulated from contacting source/drain features on one or both ends such that carriers cannot travel through. Depending on the conductivity type of the to-be-formed top GAA transistor, the second source feature248S and the second drain feature248D may be n-type source/drain features or p-type source/drain features. Example n-type source/drain features may include Si, GaAs, GaAsP, SiP, or other suitable material and may be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus (P), arsenic (As), or ex-situ doped using an implantation process (i.e., a junction implant process). Example p-type source/drain features may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable material and may be in-situ doped during the epitaxial process by introducing a p-type dopant, such as boron (B), or ex-situ doped using an implantation process (i.e., a junction implant process). In some embodiments, the to-be-formed top and bottom GAA transistors are of opposite types, such as an nFET over a pFET, or vice versa. Accordingly, the second source/drain features and the first source/drain features have opposite conductivity type, in some embodiments. In some other embodiments, the to-be-formed top and bottom GAA transistors are of the same types, such as nFET over an nFET, or a pFET over a pFET. Accordingly, the second source/drain features and the first source/drain features have the same conductivity type, in some other embodiments. Notably, directly stacked above the first source feature228S and the first drain feature228D, respectively, the second source feature248S and the second drain feature248D are less in height and less in volume, due to the less total number of active channel layers of the second stack for epitaxial source/drain feature growth. Also, although first and second source/drain features inFIGS.13A-Care illustrated as with crystalline facets (e.g., hexagon shape) in Y-Z plane (reproduced inFIG.102A), other shapes are possible, such as bar-like shape, such as shown inFIG.102B. Further, although first and second source/drain features inFIGS.13A-Care illustrated as filling up the source/drain trenches224in X-Z plane (reproduced inFIG.102C), since the source/drain features in a same source/drain trench224are grown from the opposing sidewalls of active channel layers, the source/drain features may not laterally merged, such as shown inFIG.102Dwhich corresponds to source/drain features with crystalline facets, and as shown inFIG.102Ewhich corresponds to source/drain features with bar-like shape. Furthermore, since the first and second source/drain features are epitaxially grown from the sidewalls of the active channel layers, air gaps may be trapped when neighboring source/drain features merge, such as shown inFIGS.103A-B. InFIG.103A, air gaps249are trapped adjacent to inner spacer features226and between dielectric isolation layer242and merged source/drain features. InFIG.103B, air gaps249are trapped between dielectric isolation layer242and merged source/drain features.FIGS.103C-Dillustrate fragmentary cross-sectional views in Y-Z plane with air gaps249trapped between dielectric isolation layer242and merged source/drain features with crystalline facets or bar-like shape, respectively. For avoidance of doubts, both the first source/drain features228S/D and the second source/drain features248S/D can have the various source/drain feature profiles illustrated inFIGS.102A-103D. Referring toFIGS.1and14A-C, method100includes a block136where a second CESL250and a second interlayer dielectric (ILD) layer252are deposited on the second source feature248S and the second drain feature248D. The second CESL250may include silicon nitride, silicon oxynitride, and/or other materials known in the art and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the second CESL250is first conformally deposited on the workpiece200and the second ILD layer252is deposited over the second CESL250by a PECVD process or other suitable deposition technique. The second ILD layer252may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, after formation of the second ILD layer252, the workpiece200may be annealed to improve integrity of the second ILD layer252. Upon conclusion of the operations at block136, the second CESL250is conformally deposited on surfaces of the second source feature248S, the second drain features248D, and on the sidewalls of the gate spacer layer223. To remove excess materials and to expose top surfaces of the dummy gate stacks222, a planarization process, such a chemical mechanical polishing (CMP) process may be performed. In some embodiments, the gate-top hard mask layer220is removed in the CMP process and the dummy gate electrode layer218is exposed. Referring toFIGS.1and15A-C, with the exposure of the dummy gate stack222, method100proceeds to block138where the dummy gate stack222is removed and replaced by a gate structure254. The removal of the dummy gate stack222may include one or more etching processes that are selective to the material in the dummy gate stack222. For example, the removal of the dummy gate stack222may be performed using as a selective wet etch, a selective dry etch, or a combination thereof. After the removal of the dummy gate stack222, sidewalls of the channel layers208and sacrificial layers206of both the first and second stack204a/bin the channel region, which is disposed between the source region and the drain region, are exposed. Thereafter, the sacrificial layers206in the channel region are selectively removed to release the channel layers208as the channel members. Here, because the dimensions of the channel members are nanoscale, the channel members may also be referred to as nanostructures. The selective removal of the sacrificial layers206may be implemented by selective dry etch, selective wet etch, or other selective etch processes. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by a silicon germanium oxide removal. For example, the oxidation may be provided by ozone clean and then silicon germanium oxide removed by an etchant such as NH4OH. With the channel members released, the gate structure254is deposited to wrap around each of the channel layers (including active or floating ones) of both the first and second stack204a/bin the channel region, thereby forming a bottom GAA transistor260aand a top GAA transistor260bstacked on the bottom GAA transistor260a. Since the gate structure254engages channel layers in both the top and bottom GAA transistors, the gate structure254is also referred to as a common gate structure254. The common gate structure254includes a common gate dielectric layer256and a common gate electrode layer258over the gate dielectric layer256. The common gate dielectric layer256includes an interfacial layer (not explicitly shown) and a high-k dielectric layer around and in contact with the channel members. In some embodiments, the interfacial layer includes silicon oxide and may be formed in a pre-clean process. An example pre-clean process may include use of RCA SC-1 (ammonia, hydrogen peroxide and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide and water). The high-k dielectric layer is then deposited over the interfacial layer using ALD, CVD, and/or other suitable methods. The high-k dielectric layer is formed of high-K dielectric materials. As used and described herein, high-k dielectric materials include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The high-k dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3(STO), BaTiO3(BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3(BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material. The common gate electrode layer258is then deposited over the common gate dielectric layer256using ALD, PVD, CVD, e-beam evaporation, or other suitable methods. The common gate electrode layer258may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the common gate electrode layer258may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof. Further, where the semiconductor device200includes n-type transistors and p-type transistors, different common gate electrode layers may be formed separately for n-type transistors and p-type transistors, which may include different metal layers (e.g., for providing different n-type and p-type work function metal layers). Operations at block138may also include forming a self-aligned capping (SAC) layer253over the common gate structure254. In some embodiments, the SAC layer253includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, SiO3NO4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s). The SAC layer253protects the common gate structure254from etching and CMP processes that are used for etching S/D contact holes. The SAC layer253may be formed by recessing the gate structure, depositing one or more dielectric materials over the recessed gate structure, and performing a CMP process to the one or more dielectric materials. Referring toFIGS.1and16A-C, method100includes a block140where interconnection features, such as a second source contact262, a second drain contact264, a second source contact via266, a second drain contact via268, and a first drain contact via270are formed. The second drain contact264is formed over and in contact with the second drain feature248D. Similar to the formation of the first drain contact234at block128, a contact opening is first made to expose the second drain feature248D, a silicide layer269is formed on the second drain feature248D, and a metal fill layer is deposited to fill the rest of the contact opening. Additional lithography processes may be used to form a via opening for the second source contact via266and the via opening extends through at least the second CESL250, the dielectric isolation layer242, the first ILD layer232, the first CESL230, and the isolation feature214and exposes the second buried power rail211-2. The metal fill layer may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). In some embodiments, each of the contact vias may include a liner between the metal fill layer and neighboring dielectric material to improve electrical integrity. Such liner may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN), or tantalum nitride (TaN). The second source contact via266serves to couple the second source contact262and the second buried power rail211-2. Operations at block140also includes forming a top interconnect layer272above the second ILD layer252. The top interconnect layer272includes a dielectric layer and a second power rail in the dielectric layer. The second power rail includes conductive lines (not explicitly shown) and via features coupling the underneath contacts to the conductive lines in the second power rail, such as the second drain contact via268and the first drain contact via270. Lithography processes may be used to form a via opening for the first drain contact via270which extend through at least dielectric isolation layer242, the second CESL250, the second ILD layer252, and a metal fill layer is deposited to fill the via opening. In a similar fashion, the second drain contact via268is formed over and couples the second drain contact264to the second power rail in the top interconnect layer272. Because formation of the second drain contact via268and the first drain contact via270requires forming a via opening that extends into the top interconnect layer272, these via openings may not be simultaneously formed with via openings for the first and second source contact features. In some other embodiments, the formation of the via openings for the first and second drain contact features are separately formed and are etched in several etch stages. Reference is now made toFIGS.16A-C. Upon conclusion of the operations in method100, a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aare formed. The bottom GAA transistor260aincludes channel layers (or referred to as channel members) sandwiched between the first source feature228S and the first drain feature228D. The top GAA transistor260bincludes a same number of channel layers as the bottom GAA transistor260a. One difference is that not all channel layers of the top GAA transistor260bare sandwiched between the second source feature248S and the second drain feature248D and function as active channel layers for carriers to flow through. At least a bottommost channel layer is adjoined by the dielectric isolation layer242and becomes a “floating” (inactive) channel layer. Accordingly, the top GAA transistor260bhas one less active channel layer than the bottom GAA transistor260a. In various embodiments, two or more bottom channel layers of the top GAA transistor260bmay be adjoined by the dielectric isolation layer242, and thus the top GAA transistor260bmay have two or more active channel layers less than the bottom GAA transistor260a. Less number of active channel layers weakens current driving capability of the top GAA transistor260b, which however may balance the current output in the pair of stacked GAA transistors. For example, when the top GAA transistor is an nFET and the bottom GAA transistor is a pFET, an nFET often provides a stronger current driving capability due to higher carrier mobility. By reducing a total active channel layer number of the nFET, a balanced current output from the pair of nFET and pFET can be achieved. A common gate structure254wraps around each channel layer of the top and bottom GAA transistors260aand260b, while the dielectric isolation layer242interposes the first source228S and the second source248S, and also interposes the first drain228D and the second drain248D. The first source feature228S is coupled to a bottom power rail by way of the first source contact236and the first source contact via238. The second source feature248S is couple to the bottom power rail by way of the second source contact262and the second source contact via266. The first source contact via238and the second source contact via266are disposed on two sides of the first source228S. The first drain feature228D is coupled to a top power rail by way of the first drain contact234and the first drain contact via270. The second drain feature248D is coupled to the top power rail by way of the second drain contact264and the second drain contact via268. The top power rail is disposed in the top interconnect layer272. Attention is now turned to method300.FIG.17illustrates a flow chart of method300, according to various aspects of the present disclosure. Throughout the present disclosure, similar reference numerals denote similar features in terms composition and formation. Some details of operations in method300may be simplified or omitted if similar details have been described in conjunction with method100. Referring toFIGS.17and18A-C, method300includes a block302where a workpiece200is provided. The workpiece200includes a substrate portion (also referred to as substrate)202and a stack portion204over the substrate202. The stack portion204includes a first stack204aand a second stack204bover the first stack204a. Because the substrate202and the stack portion204have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.17and19A-C, method300includes a block304where a fin-shaped structure209is formed from the stack portion204. Because operations at block304are similar to those at block104, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.17and19A-C, method300includes a block306where buried power rails211are formed. Because operations at block306are similar to those at block106, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and20A-C, method300includes a block308where an isolation feature214is formed. Because operations at block308are similar to those at block108, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and21A-C, method300includes a block310where a dummy gate stack222is formed over the stack portion204. Because operations at block310are similar to those at block110, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and22A-C, method300includes a block312where source/drain portions of the fin-shaped structure209are recessed to form source/drain recesses224. Because operations at block312are similar to those at block112, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and23A-C, method300includes a block314where inner spacer features226are formed. Because operations at block314are similar to those at block114, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and24A-C, method300includes a block316where a first dielectric isolation layer241is deposited in the source/drain recesses224. The first dielectric isolation layer241may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer241may be formed by filling the source/drain trenches224with dielectric isolation material (e.g., by using a CVD process or a spin-on glass process), and etching back the dielectric isolation material in a selective etching process. As shown inFIG.24A, the first dielectric isolation layer241covers opposite sidewalls of at least the bottommost channel layer208of the first stack204a. In some embodiments, the first dielectric isolation layer241adjoins more than one bottom channel layers208in the first stack204a. In Referring toFIGS.17and25A-C, method300includes a block318where a sacrificial dielectric layer215is deposited in the source/drain trenches224and covers the first dielectric isolation layer241. The sacrificial dielectric layer215may include silicon oxide, silicon oxycarbide, or a dielectric material that allows selective etching of the sacrificial dielectric layer215while keeping the inner spacer features226substantially intact. The sacrificial dielectric layer215may be deposited using CVD. Then the sacrificial dielectric layer215is etched back to expose the second stack204b, while sidewalls of the first stack204aremains covered. That is, after the etching back of the sacrificial dielectric layer215, sidewalls of the channel layers208of the second stack204band respective inner spacer features interleaved therein are exposed in the source/drain trenches224. The etch process may be a dry etch process, a wet etch process, or a suitable etch process. The extent at which the sacrificial dielectric layer215are recessed is controlled by duration of the etching process. Operations at block318also includes conformally depositing a third liner225over the workpiece200. The sidewalls of the first stack204bare covered by the third liner225. The third liner225may include silicon nitride, silicon carbonitride, or other suitable dielectric material that provides etching contrast to the sacrificial dielectric layer215. The third liner225may be deposited using CVD, ALD, or other suitable deposition process. Referring toFIGS.17and26A-C, method300includes a block320where lateral portion of the third liner225is removed. By using an anisotropic etching, such as RIE or other suitable dry etch process, vertical portion of the third liner225remains covering the sidewalls of the second stack204b, while lateral portion of the third liner225is removed from the source/drain trenches224, exposing the sacrificial dielectric layer215. Operations at block320also includes removing the sacrificial dielectric layer215in a selective etch process to release upper portions of the first stack204a, while the bottommost channel layer208remains covered by the first dielectric isolation layer241. In an example where the sacrificial dielectric layer215is formed of an oxide and the inner spacer features226, the third liner225, and the first dielectric isolation layer241are formed of nitrides, the sacrificial dielectric layer215may be selectively removed using diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). Here, BHF includes hydrofluoric acid and ammonium fluoride. Upon conclusion of the operations at block320, the sidewalls of the upper channel layers208of the first stack204aare exposed in the source/drain trenches224, while the sidewalls of the channel layers208of the second stack204band a top portion of the middle sacrificial layer206M remain covered by the third liner225. Referring toFIGS.17and27A-C, method300includes a block322where a first source feature228S and a first drain feature228D are formed in the source/drain trenches224. The first source feature228S and the first drain feature228D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the channel layers208. The exposed sidewalls of the channel layers208of the first stack204afunctionally serve as semiconductor seed layers. Therefore, the epitaxial growth of the first source feature228S and the first drain feature228D may take place from the exposed sidewalls of the channel layers208of the first stack204a, but not from the ones (e.g., the bottommost one in the illustration) adjoined by the first dielectric isolation layer241. As illustrated inFIG.27A, the first source feature228S and the first drain feature228D are therefore in physical contact with (or adjoining) the upper channel layers208of the first stack204a, forming active channel layers. Since the bottommost channel layer208in the first stack204ais covered by the first dielectric isolation layer241, epitaxial growth won't take place from the sidewalls thereof. Isolated form the first source feature228S and the first drain feature228D by the first dielectric isolation layer241, the bottommost channel layer208of the first stack204abecomes a “floating” (or inactive) channel layer. Since the channel layers208in the second stack204bare covered by the third liner225, epitaxial growth won't take place from the sidewalls thereof. The duration of the epitaxial growth is controlled such that the first source feature228S and the first drain feature228D do not extend upwardly beyond the middle sacrificial layer206M. Because the material compositions of the first source feature228S and the first drain feature228D have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.17and28A-C, method300includes a block326where a first contact etch stop layer (CESL)230and a first interlayer dielectric (ILD) layer232are deposited on the first source feature228S and the first drain feature228D. Because operations at block326are similar to those at block126, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and29A-C, method300includes a block328where interconnection features, such as a first drain contact234, a first source contact236, a first source contact via238are formed. Because operations at block328are similar to those at block128, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.17and29A-C, method300includes a block330where a second dielectric isolation layer242is deposited over the first ILD layer232and covering interconnection features formed in earlier operations at block328. The second dielectric isolation layer242may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer242may be formed by filling the source/drain trenches224with dielectric isolation material (e.g., by using a CVD process or a spin-on glass process), and etching back the dielectric isolation material in a selective etching process. As shown inFIG.29A, the dielectric isolation layer242covers the inner spacer features226that are on sidewalls of the middle sacrificial layer206M but not on sidewalls of the bottom channel layer208of the second stack204b. State differently, the sidewalls of the bottom channel layers208of the second stack204bremain exposed in the source/drain trenches224. Referring toFIGS.17and30A-C, method300includes a block332where a second source feature248S and a second drain feature248D are formed in the source/drain trenches224. The second source feature248S and the second drain feature248D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the channel layers208. The exposed sidewalls of the channel layers208of the second stack204bfunctionally serve as semiconductor seed layers. Since there are no channel layers208adjoined to the second dielectric isolation layer242, the epitaxial growth of the second source feature248S and the second drain feature248D may take place from the exposed sidewalls of all the channel layers208of the second stack204b. As illustrated inFIG.30A, the second source feature248S and the second drain feature248D are therefore in physical contact with (or adjoining) each channel layers208of the second stack204b, turning all the channel layers208of the second stack204binto active channel layers. Because the material compositions of the second source feature248S and the second drain feature248D have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.17and31A-C, method300includes a block336where a second CESL250and a second interlayer dielectric (ILD) layer252are deposited on the second source feature248S and the second drain feature248D. Because operations at block336are similar to those at block136, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and32A-C, method300includes a block338where the dummy gate stack222is removed and replaced by a common gate structure254. Because operations at block338are similar to those at block138, detailed descriptions thereof are omitted for brevity. Referring toFIGS.17and33A-C, method300includes a block340where interconnection features, such as a second source contact262, a second drain contact264, a second source contact via266, a second drain contact via268, a first drain contact via270, and a top interconnect layer272are formed. Because operations at block340are similar to those at block140, detailed descriptions thereof are omitted for brevity. Reference is now made toFIGS.33A-C. Upon conclusion of the operations in method300, a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aare formed. The top GAA transistor260bincludes channel layers (or referred to as channel members) sandwiched between the second source feature248S and the second drain feature248D. The bottom GAA transistor260aincludes a same number of channel layers as the top GAA transistor260b. One difference is that not all channel layers of the bottom GAA transistor260aare sandwiched between the first source feature228S and the first drain feature228D and function as active channel layers for carriers to flow through. At least a bottommost channel layer is adjoined by the first dielectric isolation layer241and becomes a “floating” (inactive) channel layer. Accordingly, the bottom GAA transistor260ahas one less active channel layer than the top GAA transistor260b. In various embodiments, two or more bottom channel layers of the bottom GAA transistor260amay be adjoined by the first dielectric isolation layer241, and thus the bottom GAA transistor260amay have two or more active channel layers less than the top GAA transistor260b. Less number of active channel layers weakens current driving capability of the bottom GAA transistor260a, which however may balance the current output in the pair of stacked GAA transistors. For example, when the top GAA transistor is an pFET and the bottom GAA transistor is an nFET, an nFET often provides a stronger current driving capability due to higher carrier mobility. By reducing a total active channel layer number of the nFET, a balanced current output from the pair of nFET and pFET can be achieved. A common gate structure254wraps around each channel layer of the top and bottom GAA transistors260band260a, while the second dielectric isolation layer242interposes the first source228S and the second source248S, and also interposes the first drain228D and the second drain248D. The first source feature228S is coupled to a bottom power rail by way of the first source contact236and the first source contact via238. The second source feature248S is couple to the bottom power rail by way of the second source contact262and the second source contact via266. The first source contact via238and the second source contact via266are disposed on two sides of the first source228S. The first drain feature228D is coupled to a top power rail by way of the first drain contact234and the first drain contact via270. The second drain feature248D is coupled to the top power rail by way of the second drain contact264and the second drain contact via268. The top power rail is disposed in the top interconnect layer272. Attention is now turned to method500.FIG.34illustrates a flow chart of method500, according to various aspects of the present disclosure. Throughout the present disclosure, similar reference numerals denote similar features in terms composition and formation. Some details of operations in method500may be simplified or omitted if similar details have been described in conjunction with method100. Referring toFIGS.34and35A-C, method500includes a block502where a workpiece200is provided. The workpiece200includes a substrate portion (also referred to as substrate)202and a stack portion204over the substrate202. The stack portion204includes a first stack204aand a second stack204bover the first stack204a. Because the substrate202and the stack portion204have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.34and36A-C, method500includes a block504where a fin-shaped structure209is formed from the stack portion204. Because operations at block504are similar to those at block104, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.34and36A-C, method500includes a block506where buried power rails211are formed. Because operations at block506are similar to those at block106, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and37A-C, method500includes a block508where an isolation feature214is formed. Because operations at block508are similar to those at block108, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and38A-C, method500includes a block510where a dummy gate stack222is formed over the stack portion204. Because operations at block510are similar to those at block110, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and39A-C, method500includes a block512where source/drain portions of the fin-shaped structure209are recessed to form source/drain recesses224. Because operations at block512are similar to those at block112, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and40A-C, method500includes a block514where inner spacer features226are formed. Because operations at block514are similar to those at block114, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and41A-C, method500includes a block518where a sacrificial dielectric layer215is deposited in the source/drain trenches224to cover the sidewalls of the channel layer208of the first stack204aand a third liner225is conformally deposited over the workpiece200to cover the sidewalls of the channel layer208of the second stack204b. Because operations at block518are similar to those at block118, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and42A-C, method500includes a block520where a lateral portion of the third liner225is removed to expose the sacrificial dielectric layer215and the sacrificial dielectric layer215is subsequently removed in a selective etch process to release the first stack204a. Because operations at block520are similar to those at block120, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and43A-C, method500includes a block522where first source feature228S and a first drain feature228D are formed in the source/drain trenches224adjoining the channel layers208of the first stack204a. Since the channel layers208in the second stack204bare covered by the third liner225, epitaxial growth won't take place from the sidewalls thereof. Because operations at block522are similar to those at block122, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and44A-C, method500includes a block526where the third liner225is removed to release the second stack204band a first CESL230and a first ILD layer232are deposited on the first source feature228S and the first drain feature228D. Because operations at block526are similar to those at block126, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and45A-C, method500includes a block528where interconnection features, such as a first drain contact234, a first source contact236, a first source contact via238are formed. Because operations at block528are similar to those at block128, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.34and45A-C, method500includes a block530where a dielectric isolation layer242is deposited over the first ILD layer232and covering interconnection features formed in earlier operations at block528. The dielectric isolation layer242may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer242may be formed by filling the source/drain trenches224with dielectric isolation material (e.g., by using a CVD process or a spin-on glass process), and etching back the dielectric isolation material in a selective etching process. As shown inFIG.45A, the dielectric isolation layer242covers the inner spacer features226that are on sidewalls of the middle sacrificial layer206M but not on sidewalls of the bottom channel layer208of the second stack204b. State differently, the sidewalls of the bottom channel layers208of the second stack204bremain exposed in the source/drain trenches224. Referring toFIGS.34and46A-C, method500includes a block532where a second source feature248S and a second drain feature248D are formed in the source/drain trenches224. The second source feature248S and the second drain feature248D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the channel layers208. The exposed sidewalls of the channel layers208of the second stack204bfunctionally serve as semiconductor seed layers. Since there are no channel layers208adjoined to the dielectric isolation layer242, the epitaxial growth of the second source feature248S and the second drain feature248D may take place from the exposed sidewalls of all the channel layers208of the second stack204b. As illustrated inFIG.46A, the second source feature248S and the second drain feature248D are therefore in physical contact with (or adjoining) each channel layers208of the second stack204b. Because the material compositions of the second source feature248S and the second drain feature248D have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.34and47A-C, method500includes a block534where the second source feature248S and the second drain feature248D are etched back to release at least the topmost channel layer208in the second stack204b, exposing sidewalls thereof. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. As illustrated inFIG.47A, top surfaces of the second source feature248S and the second drain feature248D are recessed below the topmost channel layer208but remain covering other channel layers208thereunder. In some embodiments, top surfaces of the second source feature248S and the second drain feature248D are recessed below two or more top channel layers208in the second stack204b. Referring toFIGS.34and48A-C, method500includes a block536where a second CESL250and a second interlayer dielectric (ILD) layer252are deposited on the second source feature248S and the second drain feature248D. In some embodiments, the second CESL250is first conformally deposited on the workpiece200by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. The conformal second CESL250covers the recessed top surfaces of the second source feature248S and the second drain feature248D and also covers the exposed sidewalls of the topmost channel layer208in the second stack204b. Isolated form the second source feature248S and the second drain feature248D by the second CESL250, the topmost channel layer208in the second stack204bbecomes a “floating” (or inactive) channel layer. The second ILD layer252is deposited over the second CESL250by a PECVD process or other suitable deposition technique. Because the material compositions of the second CESL250and the second ILD layer252have been described above, detailed descriptions thereof are omitted here. To remove excess materials and to expose top surfaces of the dummy gate stacks222, a planarization process, such a chemical mechanical polishing (CMP) process may be performed. In some embodiments, the gate-top hard mask layer220is removed in the CMP process and the dummy gate electrode layer218is exposed. Referring toFIGS.34and49A-C, method500includes a block538where the dummy gate stack222is removed and replaced by a common gate structure254. Because operations at block538are similar to those at block138, detailed descriptions thereof are omitted for brevity. Referring toFIGS.34and50A-C, method500includes a block540where interconnection features, such as a second source contact262, a second drain contact264, a second source contact via266, a second drain contact via268, a first drain contact via270, and a top interconnect layer272are formed. Because operations at block540are similar to those at block140, detailed descriptions thereof are omitted for brevity. Reference is now made toFIGS.50A-C. Upon conclusion of the operations in method100, a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aare formed. The bottom GAA transistor260aincludes channel layers (or referred to as channel members) sandwiched between the first source feature228S and the first drain feature228D. The top GAA transistor260bincludes a same number of channel layers as the bottom GAA transistor260a. One difference is that not all channel layers of the top GAA transistor260bare sandwiched between the second source feature248S and the second drain feature248D and function as active channel layers for carriers to flow through. At least a topmost channel layer is adjoined by the second CESL250and becomes a “floating” (inactive) channel layer. Accordingly, the top GAA transistor260bhas one less active channel layer than the bottom GAA transistor260a. In various embodiments, two or more top channel layers of the top GAA transistor260bmay be adjoined by the second CESL250, and thus the top GAA transistor260bmay have two or more active channel layers less than the bottom GAA transistor260a. Less number of active channel layers weakens current driving capability of the top GAA transistor260b, which however may balance the current output in the pair of stacked GAA transistors. For example, when the top GAA transistor is an nFET and the bottom GAA transistor is a pFET, an nFET often provides a stronger current driving capability due to higher carrier mobility. By reducing a total active channel layer number of the nFET, a balanced current output from the pair of nFET and pFET can be achieved. A common gate structure254wraps around each channel layer of the top and bottom GAA transistors260aand260b, while the dielectric isolation layer242interposes the first source228S and the second source248S, and also interposes the first drain228D and the second drain248D. The first source feature228S is coupled to a bottom power rail by way of the first source contact236and the first source contact via238. The second source feature248S is couple to the bottom power rail by way of the second source contact262and the second source contact via266. The first source contact via238and the second source contact via266are disposed on two sides of the first contact228S. The first drain feature228D is coupled to a top power rail by way of the first drain contact234and the first drain contact via270. The second drain feature248D is coupled to the top power rail by way of the second drain contact264and the second drain contact via268. The top power rail is disposed in the top interconnect layer272. Attention is now turned to method700.FIG.51illustrates a flow chart of method500, according to various aspects of the present disclosure. Throughout the present disclosure, similar reference numerals denote similar features in terms composition and formation. Some details of operations in method700may be simplified or omitted if similar details have been described in conjunction with method100. Referring toFIGS.51and52A-C, method700includes a block702where a workpiece200is provided. The workpiece200includes a substrate portion (also referred to as substrate)202and a stack portion204over the substrate202. The stack portion204includes a first stack204aand a second stack204bover the first stack204a. Because the substrate202and the stack portion204have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.51and53A-C, method700includes a block704where a fin-shaped structure209is formed from the stack portion204. Because operations at block704are similar to those at block104, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.51and53A-C, method700includes a block706where buried power rails211are formed. Because operations at block706are similar to those at block106, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and54A-C, method700includes a block708where an isolation feature214is formed. Because operations at block708are similar to those at block108, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and55A-C, method700includes a block710where a dummy gate stack222is formed over the stack portion204. Because operations at block710are similar to those at block110, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and56A-C, method700includes a block712where source/drain portions of the fin-shaped structure209are recessed to form source/drain recesses224. Because operations at block712are similar to those at block112, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and57A-C, method700includes a block714where inner spacer features226are formed. Because operations at block714are similar to those at block114, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and58A-C, method700includes a block718where a sacrificial dielectric layer215is deposited in the source/drain trenches224to cover the sidewalls of the channel layer208of the first stack204aand a third liner225is conformally deposited over the workpiece200to cover the sidewalls of the channel layer208of the second stack204b. Because operations at block718are similar to those at block118, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and59A-C, method700includes a block720where a lateral portion of the third liner225is removed to expose the sacrificial dielectric layer215and the sacrificial dielectric layer215is subsequently removed in a selective etch process to release the first stack204a. Because operations at block720are similar to those at block120, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and60A-C, method700includes a block722where first source feature228S and a first drain feature228D are formed in the source/drain trenches224adjoining the channel layers208of the first stack204a. Since the channel layers208in the second stack204bare covered by the third liner225, epitaxial growth won't take place from the sidewalls thereof. Because operations at block722are similar to those at block122, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and61A-C, method700includes a block724where the first source feature228S and the first drain feature228D are etched back to release at least the topmost channel layer208in the first stack204a, exposing sidewalls thereof. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. As illustrated inFIG.61A, top surfaces of the first source feature228S and the first drain feature228D are recessed below the topmost channel layer208in the first stack204abut remain covering other channel layers208thereunder. In some embodiments, top surfaces of the first source feature228S and the first drain feature228D are recessed below two or more top channel layers208in the first stack204a. Referring toFIGS.51and62A-C, method700includes a block726where the third liner225is removed to release the second stack204band a first CESL230and a first ILD layer232are deposited on the first source feature228S and the first drain feature228D. In some embodiments, the first CESL230is first conformally deposited on the workpiece200by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. The first ILD layer232is deposited over the first CESL230by a PECVD process or other suitable deposition technique. Subsequently, the first CESL230and the first ILD layer232are etched back to expose the second stack204b. The conformal first CESL230still covers the recessed top surfaces of the first source feature228S and the first drain feature228D and also covers the exposed sidewalls of the topmost channel layer208in the first stack204a. Isolated form the first source feature228S and the first drain feature228D by the first CESL230, the topmost channel layer208in the first stack204abecomes a “floating” (or inactive) channel layer. Because the material compositions of the first CESL230and the first ILD layer232have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.51and63A-C, method700includes a block728where interconnection features, such as a first drain contact234, a first source contact236, a first source contact via238are formed. Because operations at block728are similar to those at block128, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.51and63A-C, method700includes a block730where a dielectric isolation layer242is deposited over the first ILD layer232and covering interconnection features formed in earlier operations at block728. The dielectric isolation layer242may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer242may be formed by filling the source/drain trenches224with dielectric isolation material (e.g., by using a CVD process or a spin-on glass process), and etching back the dielectric isolation material in a selective etching process. As shown inFIG.63A, the dielectric isolation layer242covers the inner spacer features226that are on sidewalls of the middle sacrificial layer206M but not on sidewalls of the bottom channel layer208of the second stack204b. State differently, the sidewalls of the bottom channel layers208in the second stack204bremain exposed in the source/drain trenches224. Referring toFIGS.51and64A-C, method700includes a block732where a second source feature248S and a second drain feature248D are formed in the source/drain trenches224. The second source feature248S and the second drain feature248D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the channel layers208. The exposed sidewalls of the channel layers208of the second stack204bfunctionally serve as semiconductor seed layers. Since there are no channel layers208adjoined to the dielectric isolation layer242, the epitaxial growth of the second source feature248S and the second drain feature248D may take place from the exposed sidewalls of all the channel layers208of the second stack204b. As illustrated inFIG.64A, the second source feature248S and the second drain feature248D are therefore in physical contact with (or adjoining) each channel layers208of the second stack204b. Because the material compositions of the second source feature248S and the second drain feature248D have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.51and65A-C, method700includes a block736where a second CESL250and a second interlayer dielectric (ILD) layer252are deposited on the second source feature248S and the second drain feature248D. Because operations at block736are similar to those at block136, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and66A-C, method700includes a block738where the dummy gate stack222is removed and replaced by a common gate structure254. Because operations at block738are similar to those at block138, detailed descriptions thereof are omitted for brevity. Referring toFIGS.51and67A-C, method700includes a block740where interconnection features, such as a second source contact262, a second drain contact264, a second source contact via266, a second drain contact via268, a first drain contact via270, and a top interconnect layer272are formed. Because operations at block740are similar to those at block140, detailed descriptions thereof are omitted for brevity. Reference is now made toFIGS.67A-C. Upon conclusion of the operations in method700, a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aare formed. The top GAA transistor260bincludes channel layers (or referred to as channel members) sandwiched between the second source feature248S and the second drain feature248D. The bottom GAA transistor260aincludes a same number of channel layers as the top GAA transistor260b. One difference is that not all channel layers of the bottom GAA transistor260aare sandwiched between the first source feature228S and the first drain feature228D and function as active channel layers for carriers to flow through. At least a topmost channel layer is adjoined by the first CESL230and becomes a “floating” (inactive) channel layer. Accordingly, the bottom GAA transistor260ahas one less active channel layer than the top GAA transistor260b. In various embodiments, two or more top channel layers of the bottom GAA transistor260amay be adjoined by the first CESL230, and thus the bottom GAA transistor260amay have two or more active channel layers less than the top GAA transistor260b. Less number of active channel layers weakens current driving capability of the bottom GAA transistor260a, which however may balance the current output in the pair of stacked GAA transistors. For example, when the top GAA transistor is a pFET and the bottom GAA transistor is an nFET, an nFET often provides a stronger current driving capability due to higher carrier mobility. By reducing a total active channel layer number of the nFET, a balanced current output from the pair of nFET and pFET can be achieved. A common gate structure254wraps around each channel layer of the top and bottom GAA transistors260aand260b, while the dielectric isolation layer242interposes the first source228S and the second source248S, and also interposes the first drain228D and the second drain248D. The first source feature228S is coupled to a bottom power rail by way of the first source contact236and the first source contact via238. The second source feature248S is couple to the bottom power rail by way of the second source contact262and the second source contact via266. The first source contact via238and the second source contact via266are disposed on two sides of the first contact228S. The first drain feature228D is coupled to a top power rail by way of the first drain contact234and the first drain contact via270. The second drain feature248D is coupled to the top power rail by way of the second drain contact264and the second drain contact via268. The top power rail is disposed in the top interconnect layer272. Attention is now turned to method900.FIG.68illustrates a flow chart of method900, according to various aspects of the present disclosure. Throughout the present disclosure, similar reference numerals denote similar features in terms composition and formation. Some details of operations in method900may be simplified or omitted if similar details have been described in conjunction with method100. Referring toFIGS.68and69A-C, method900includes a block902where a workpiece200is provided. The workpiece200includes a substrate portion (also referred to as substrate)202and a stack portion204over the substrate202. The stack portion204includes a first stack204aand a second stack204bover the first stack204a, where the first stack204ahas one or more channel layers208than the second stack204b. Because material compositions of the substrate202and the stack portion204have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.68and70A-C, method900includes a block904where a fin-shaped structure209is formed from the stack portion204. Because operations at block904are similar to those at block104, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.68and70A-C, method900includes a block906where buried power rails211are formed. Because operations at block906are similar to those at block106, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and71A-C, method900includes a block908where an isolation feature214is formed. Because operations at block908are similar to those at block108, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and72A-C, method900includes a block910where a dummy gate stack222is formed over the stack portion204. Because operations at block910are similar to those at block110, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and73A-C, method900includes a block912where source/drain portions of the fin-shaped structure209are recessed to form source/drain recesses224. Because operations at block912are similar to those at block112, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and74A-C, method900includes a block914where inner spacer features226are formed. Because operations at block914are similar to those at block114, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and75A-C, method900includes a block918where a sacrificial dielectric layer215is deposited in the source/drain trenches224to cover the sidewalls of the channel layer208in the first stack204aand a third liner225is conformally deposited over the workpiece200to cover the sidewalls of the channel layer208in the second stack204b. Because operations at block918are similar to those at block118, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and76A-C, method900includes a block920where a lateral portion of the third liner225is removed to expose the sacrificial dielectric layer215and the sacrificial dielectric layer215is subsequently removed in a selective etch process to release the first stack204a. Because operations at block920are similar to those at block120, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and77A-C, method900includes a block922where first source feature228S and a first drain feature228D are formed in the source/drain trenches224adjoining the channel layers208of the first stack204a. Since the channel layers208in the second stack204bare covered by the third liner225, epitaxial growth won't take place from the sidewalls thereof. Because operations at block922are similar to those at block122, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and78A-C, method900includes a block926where the third liner225is removed to release the second stack204band a first CESL230and a first ILD layer232are deposited on the first source feature228S and the first drain feature228D. Because operations at block926are similar to those at block126, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and79A-C, method900includes a block928where interconnection features, such as a first drain contact234, a first source contact236, a first source contact via238are formed. Because operations at block928are similar to those at block128, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.68and79A-C, method900includes a block930where a dielectric isolation layer242is deposited over the first ILD layer232and covering interconnection features formed in earlier operations at block928. The dielectric isolation layer242may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer242may be formed by filling the source/drain trenches224with dielectric isolation material (e.g., by using a CVD process or a spin-on glass process), and etching back the dielectric isolation material in a selective etching process. As shown inFIG.79A, the dielectric isolation layer242covers the inner spacer features226that are on sidewalls of the middle sacrificial layer206M but not on sidewalls of the bottom channel layer208of the second stack204b. State differently, the sidewalls of the bottom channel layers208of the second stack204bremain exposed in the source/drain trenches224. Referring toFIGS.68and80A-C, method900includes a block932where a second source feature248S and a second drain feature248D are formed in the source/drain trenches224. The second source feature248S and the second drain feature248D may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the channel layers208. The exposed sidewalls of the channel layers208of the second stack204bfunctionally serve as semiconductor seed layers. Since there are no channel layers208adjoined to the dielectric isolation layer242, the epitaxial growth of the second source feature248S and the second drain feature248D may take place from the exposed sidewalls of all the channel layers208of the second stack204b. As illustrated inFIG.80A, the second source feature248S and the second drain feature248D are therefore in physical contact with (or adjoining) each channel layers208in the second stack204b. Because the material compositions of the second source feature248S and the second drain feature248D have been described above, detailed descriptions thereof are omitted here. Referring toFIGS.68and81A-C, method900includes a block936where a second CESL250and a second interlayer dielectric (ILD) layer252are deposited on the second source feature248S and the second drain feature248D. Because operations at block936are similar to those at block136, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and82A-C, method900includes a block938where the dummy gate stack222is removed and replaced by a common gate structure254. Because operations at block938are similar to those at block138, detailed descriptions thereof are omitted for brevity. Referring toFIGS.68and83A-C, method900includes a block940where interconnection features, such as a second source contact262, a second drain contact264, a second source contact via266, a second drain contact via268, a first drain contact via270, and a top interconnect layer272are formed. Because operations at block940are similar to those at block140, detailed descriptions thereof are omitted for brevity. Reference is now made toFIGS.83A-C. Upon conclusion of the operations in method900, a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aare formed. The top GAA transistor260bincludes channel layers (or referred to as channel members) sandwiched between the second source feature248S and the second drain feature248D. The bottom GAA transistor260aincludes channel layers sandwiched between the first source feature228S and the first drain feature228D. Each channel layer208in the first stack204aand the second stack204bis an active channel layer. One difference is that since the first stack204ahas at least one more channel layer208than the second stack204b, the bottom GAA transistor260ahas at least one more channel layer208than the top GAA transistor260b. Accordingly, the bottom GAA transistor260ahas at least one more active channel layer than the top GAA transistor260b. In various embodiments, the bottom GAA transistor260amay have two or more active channel layers than the top GAA transistor260b. Alternatively, if method900at block902starts with a second stack204bthat has at least one more channel layer208than the first stack204b, upon conclusion of the operations in method900, the top GAA transistor260bwould thus have at least one more active channel layer than the bottom GAA transistor260a. Such alternative embodiment of method900is illustrated inFIGS.84A-C. In furtherance of the alternative embodiment, the top GAA transistor260bmay have two or more active channel layers than the bottom GAA transistor260a. In both embodiments illustrated inFIGS.83A-Cand84A-C, a common gate structure254wraps around each channel layer of the top and bottom GAA transistors260aand260b, while the second dielectric isolation layer242interposes the first source228S and the second source248S, and also interposes the first drain228D and the second drain248D. The first source feature228S is coupled to a bottom power rail by way of the first source contact236and the first source contact via238. The second source feature248S is couple to the bottom power rail by way of the second source contact262and the second source contact via266. The first source contact via238and the second source contact via266are disposed on two sides of the first contact228S. The first drain feature228D is coupled to a top power rail by way of the first drain contact234and the first drain contact via270. The second drain feature248D is coupled to the top power rail by way of the second drain contact264and the second drain contact via268. The top power rail is disposed in the top interconnect layer272. Attention is now turned to method1100.FIG.85illustrates a flow chart of method1100, according to various aspects of the present disclosure. Throughout the present disclosure, similar reference numerals denote similar features in terms composition and formation. Some details of operations in method1100may be simplified or omitted if similar details have been described in conjunction with method100. Referring toFIGS.85and86A-C, method1100includes a block1102where a workpiece200is provided. The workpiece200includes a substrate202and a first stack204over the substrate202. The first stack204includes a plurality of channel layers208interleaved by a plurality of sacrificial layers206. It is noted that three (3) layers of the channel layers208in the first stack204aare illustrated inFIGS.86A-C, which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of the channel layers208can be formed in the first stack204a. The number of layers depends on the desired number of channels members for the device200. In some embodiments, the number of the channel layers208in the first stack204ais between 2 and Because material compositions of the substrate202and the first stack204ahave been described above, detailed descriptions thereof are omitted here. Referring toFIGS.85and87A-C, method1100includes a block1104where a fin-shaped structure209is formed from the first stack204a. Because operations at block1104are similar to those at block104, detailed descriptions thereof are omitted for brevity. Still referring toFIGS.85and87A-C, method1100includes a block1106where buried power rails211are formed. Because operations at block1106are similar to those at block106, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and88A-C, method1100includes a block1108where an isolation feature214is formed. Because operations at block1108are similar to those at block108, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and89A-C, method1100includes a block1110where a dummy gate stack222is formed over the stack portion204. Because operations at block1110are similar to those at block110, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and90A-C, method1100includes a block1112where source/drain portions of the fin-shaped structure209are recessed to form source/drain recesses224. Because operations at block1112are similar to those at block112, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and91A-C, method1100includes a block1114where inner spacer features226are formed. Because operations at block1114are similar to those at block114, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and92A-C, method1100includes a block1116where first source feature228S and a first drain feature228D are formed in the source/drain trenches224adjoining the channel layers208of the first stack204a. Because operations at block1116are similar to those at block122, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and93A-C, method1100includes a block1118where a first CESL230and a first ILD layer232are deposited on the first source feature228S and the first drain feature228D. Because operations at block1118are similar to those at block126, detailed descriptions thereof are omitted for brevity. To remove excess materials and to expose top surfaces of the dummy gate stacks222, a planarization process, such a chemical mechanical polishing (CMP) process may be performed. In some embodiments, the gate-top hard mask layer220is removed in the CMP process and the dummy gate electrode layer218is exposed. Referring toFIGS.85and94A-C, method1100includes a block1120where the dummy gate stack222is removed and replaced by a first gate structure254a. Because operations at block1120are similar to those at block138, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and95A-C, method1100includes a block1122where interconnection features, such as a first drain contact234, a first source contact236, a first source contact via238are formed. Because operations at block1122are similar to those at block128, detailed descriptions thereof are omitted for brevity. Referring toFIGS.85and96A-C, method1100includes a block1124where a dielectric isolation layer242is deposited over the first ILD layer232and covering interconnection features formed in earlier operations at block1122. The dielectric isolation layer242may include silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or other suitable isolation material. In an embodiment, the dielectric isolation layer242may be formed by CVD, PECVD, or other suitable process. Still referring toFIGS.85and96A-C, method1100includes a block1126where a second stack204bis bonded over to the workpiece200. Like the first stack204a, the second stack204balso include a plurality of channel layers208interleaved by a plurality of sacrificial layers206. In the embodiments shown inFIG.96A, the first stack204aand the second stack204bhave different number of channel layers208. Particularly in the illustrated embodiment, the first stack204ahas more channel layers208than the second stack204b. However, the present disclosure is not so limited that the first stack204amay have less channel layers208than the second stack204b, or have different configurations, such as different thicknesses of layers. To facilitate bonding, a gluing layer (not explicitly shown) may be formed on a bottom surface of the second stack204b. The second stack204band the gluing layer may be regarded as another substrate, as opposed to the substrate202. In some implementations, the gluing layer includes silicon oxide and may also be referred to as a gluing oxide layer. In some embodiments, the second stack204bmay be directly bonded to the workpiece200by utilizing the interface between the dielectric isolation layer242and the gluing layer. In an example direct bonding process, both the dielectric isolation layer242and the gluing layer are cleaned using RCA SC-1 (ammonia, hydrogen peroxide and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide and water). The cleaned dielectric isolation layer242and gluing layer are then mated and pressed together. The direct bonding may be strength by an anneal process. In some alternative embodiments, the sacrificial layers206and channel layers208in the second stack204bare epitaxy layers and may be deposited on the workpiece200using an epitaxy process. Suitable epitaxy processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes. Referring toFIGS.85and97A-C, method1100includes a block1128where operations in blocks1104,1110-1120are performed to the second stack204b. Due to the similarity in process steps, operations at block1128are only summarized for simplicity. At block1104, the second stack204bis patterned to form a second fin-shaped structure. At block1110, a second dummy gate stack is formed over the channel region of the second fin-shaped structure to serve as a placeholder for a functional second gate structure. At block1112, the source/drain portion of the second fin-shaped structure are recessed to form source/drain recesses, similar to the source/drain trenches224. At block1114, the sacrificial layers206in the channel region are selectively and partially etched to form inner spacer recesses and inner spacer features are formed in such inner spacer recesses. At block1116, a second source feature248S and a second drain feature248D are formed in the source/drain recesses. At block1118, a second CESL250and a second ILD layer252are deposited on the second source feature248S and the second drain feature248D. At block1120, the dummy gate stack over the second fin-shaped structure is replaced by a second gate structure254b. The sacrificial layers206in the channel region are selectively removed to release the channel layers208as channel members and the second gate structure254bwraps around each of the channel members in the second stack204b. Referring toFIGS.85and98A-C, method1100includes a block1130where interconnection features, such as a second source contact262, a second drain contact264, a second source contact via266, a second drain contact via268, a first drain contact via270, and a top interconnect layer272are formed. Because operations at block1130are similar to those at block140, detailed descriptions thereof are omitted for brevity. Reference is now made toFIGS.98A-C. Upon conclusion of the operations in method1100, a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aare formed. The top and bottom GAA transistors are separated by a dielectric isolation layer242. The top GAA transistor260bincludes channel layers (or referred to as channel members) sandwiched between the second source feature248S and the second drain feature248D. The bottom GAA transistor260aincludes channel layers sandwiched between the first source feature228S and the first drain feature228D. Each channel layer208in the first stack204aand the second stack204bis an active channel layer. One difference is that since the first stack204ahas at least one more channel layer208than the second stack204b, the bottom GAA transistor260ahas at least one more channel layer208than the top GAA transistor260b. Accordingly, the bottom GAA transistor260ahas at least one more active channel layer than the top GAA transistor260b. In various embodiments, the bottom GAA transistor260amay have two or more active channel layers than the top GAA transistor260b. Alternatively, if method900at block902starts with a second stack204bthat has at least one more channel layer208than the first stack204a, upon conclusion of the operations in method900, the top GAA transistor260bwould thus have at least one more active channel layer than the bottom GAA transistor260a. In furtherance of the alternative embodiment, the top GAA transistor260bmay have two or more active channel layers than the bottom GAA transistor260a. A first gate structure254awraps around each channel layer of the bottom GAA transistors260a. A second gate structure254bwraps around each channel layer of the top GAA transistor260b. The dielectric isolation layer242interposes the first gate structure254aand the second gate structure254b, interposes the first source228S and the second source248S, and also interposes the first drain228D and the second drain248D. The first source feature228S is coupled to a bottom power rail by way of the first source contact236and the first source contact via238. The second source feature248S is couple to the bottom power rail by way of the second source contact262and the second source contact via266. The first source contact via238and the second source contact via266are disposed on two sides of the first contact228S. The first drain feature228D is coupled to a top power rail by way of the first drain contact234and the first drain contact via270. The second drain feature248D is coupled to the top power rail by way of the second drain contact264and the second drain contact via268. The top power rail is disposed in the top interconnect layer272. FIGS.99and100illustrate some embodiments of a workpiece with a bottom GAA transistor260aand a top GAA transistor260bstacked over the bottom GAA transistor260aby using methods100,300,500,700,900,1100, or combinations thereof. Examples I-XV inFIGS.99and100are for the sake of example and are non-limiting. For example, a difference of number of active channel layers may be two or three or even more between stacked GAA transistors so formed by the illustrative processes. Example I illustrates an embodiment where a workpiece is formed by method100. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a same number of channel layers as the bottom GAA transistor260a. One difference is that not all channel layers of the top GAA transistor260bare sandwiched between the second source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer242and becomes a “floating” (inactive) channel layer. Accordingly, the top GAA transistor260bhas one less active channel layer than the bottom GAA transistor260a. In an alternative embodiment, two or more bottom channel layers of the top GAA transistor260bmay be adjoined by the dielectric isolation layer242, and thus the top GAA transistor260bmay have two or more active channel layers less than the bottom GAA transistor260a. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the fewer total number of active channel layers of the second stack for epitaxial source/drain feature growth, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. For avoidance of doubts, both the first and second source/drain features in Example I, as well as in Examples II-XV below or other alternative embodiments, can have the various source/drain feature profiles illustrated inFIGS.102A-103D. Example II illustrates an embodiment where a workpiece is formed by method300. The top GAA transistor260bincludes channel layers sandwiched between the first source/drain features. The bottom GAA transistor260aincludes a same number of channel layers as the top GAA transistor260b. One difference is that not all channel layers of the bottom GAA transistor260aare sandwiched between the first source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer241and becomes a “floating” channel layer. Accordingly, the bottom GAA transistor260ahas one less active channel layer than the top GAA transistor260b. In an alternative embodiment, two or more bottom channel layers of the bottom GAA transistor260amay be adjoined by the dielectric isolation layer241, and thus the bottom GAA transistor260amay have two or more active channel layers less than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the fewer total number of active channel layers of the first stack for epitaxial source/drain feature growth, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Example III illustrates an embodiment where a workpiece is formed by method500. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a same number of channel layers as the bottom GAA transistor260a. One difference is that not all channel layers of the top GAA transistor260bare sandwiched between the second source/drain features and able to function as active channel layers. At least a topmost channel layer is adjoined by a CESL250and becomes a “floating” channel layer. Accordingly, the top GAA transistor260bhas one less active channel layer than the bottom GAA transistor260a. In an alternative embodiment, two or more top channel layers of the top GAA transistor260bmay be adjoined by the CESL250, and thus the top GAA transistor260bmay have two or more active channel layers less than the bottom GAA transistor260a. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the recessed top surfaces, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Example IV illustrates an embodiment where a workpiece is formed by method700. The top GAA transistor260bincludes channel layers sandwiched between the second source/drain features. The bottom GAA transistor260aincludes a same number of channel layers as the top GAA transistor260b. One difference is that not all channel layers of the bottom GAA transistor260aare sandwiched between the first source/drain features and able to function as active channel layers. At least a topmost channel layer is adjoined by a CESL230and becomes a “floating” channel layer. Accordingly, the bottom GAA transistor260ahas one less active channel layer than the top GAA transistor260b. In an alternative embodiment, two or more top channel layers of the bottom GAA transistor260amay be adjoined by the CESL230, and thus the bottom GAA transistor260amay have two or more active channel layers less than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the recessed top surfaces, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Example V illustrates an embodiment where a workpiece is formed by method900. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes channel layers sandwiched between the second source/drain features. Each channel layer is an active channel layer. One difference is that the bottom GAA transistor260ahas at least one more channel layer208than the top GAA transistor260b. Accordingly, the bottom GAA transistor260ahas at least one more active channel layer than the top GAA transistor260b. In various embodiments, the bottom GAA transistor260amay have two or more active channel layers than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less channel layers for epitaxial source/drain feature growth, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Example VI illustrates an alternative embodiment of method900, where the top GAA transistor260bhas at least one more channel layer and thus one more active channel layer than the bottom GAA transistor260a. Due to the less channel layers for epitaxial source/drain feature growth, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Other features of the alternative embodiment of Example VI are structurally similar to Example V. Example VII illustrates an embodiment where structures formed using method100and structures formed using method500are combined. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a same number of channel layers as the bottom GAA transistor260a. One difference is that not all channel layers of the top GAA transistor260bare sandwiched between the second source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer242and becomes a “floating” channel layer. Also, at least a topmost channel layer is adjoined by a CESL250and becomes a “floating” channel layer. Accordingly, the top GAA transistor260bhas at least two active channel layers less than the bottom GAA transistor260a. In an alternative embodiment, the top GAA transistor260bmay have three or more active channel layers less than the bottom GAA transistor260a. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less total number of active channel layers of the second stack for epitaxial source/drain feature growth and recessed top surfaces, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Example VIII illustrates an embodiment where structures formed using method300and structures formed using method700are combined. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a same number of channel layers as the bottom GAA transistor260a. One difference is that not all channel layers of the bottom GAA transistor260aare sandwiched between the first source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer241and becomes a “floating” channel layer. Also, at least a topmost channel layer is adjoined by a CESL230and becomes a “floating” channel layer. Accordingly, the bottom GAA transistor260ahas at least two active channel layers less than the top GAA transistor260b. In an alternative embodiment, the bottom GAA transistor260amay have three or more active channel layers less than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the fewer total number of active channel layers of the first stack for epitaxial source/drain feature growth and recessed top surfaces, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Example IX illustrates an embodiment where structures formed using method100, structures formed using method500, and structures formed using method900are combined. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a less number of channel layers than the bottom GAA transistor260a. Further, not all channel layers of the top GAA transistor260bare sandwiched between the second source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer242and becomes a “floating” channel layer. Also, at least a topmost channel layer is adjoined by a CESL250and becomes a “floating” channel layer. Accordingly, the top GAA transistor260bhas only a single active channel layer in the illustrated embodiment. State differently, the top GAA transistor260bhas at least three active channel layers less than the bottom GAA transistor260a. In an alternative embodiment, the top GAA transistor260bmay have four or more active channel layers less than the bottom GAA transistor260a. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less total number of active channel layers of the second stack for epitaxial source/drain feature growth and recessed top surfaces, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Example X illustrates an embodiment where structures formed using method300, structures formed using method700, and structures formed using method900are combined. The top GAA transistor260bincludes channel layers sandwiched between the second source/drain features. The bottom GAA transistor260aincludes a fewer number of channel layers than the top GAA transistor260b. Further, not all channel layers of the bottom GAA transistor260aare sandwiched between the first source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer241and becomes a “floating” channel layer. Also, at least a topmost channel layer is adjoined by a CESL230and becomes a “floating” channel layer. Accordingly, the bottom GAA transistor260ahas only a single active channel layer in the illustrated embodiment. State differently, the bottom GAA transistor260ahas at least three less active channel layers than the top GAA transistor260b. In an alternative embodiment, the bottom GAA transistor260amay have four or more active channel layers less than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the fewer total number of active channel layers of the first stack for epitaxial source/drain feature growth and recessed top surfaces, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Example XI illustrates an embodiment where structures formed using method100and structures formed using method900are combined. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a less number of channel layers than the bottom GAA transistor260a. Further, not all channel layers of the top GAA transistor260bare sandwiched between the second source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer242and becomes a “floating” channel layer. Accordingly, the top GAA transistor260bhas at least two less active channel layers than the bottom GAA transistor260a. In an alternative embodiment, the top GAA transistor260bmay have three or more active channel layers less than the bottom GAA transistor260a. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less total number of active channel layers of the second stack for epitaxial source/drain feature growth, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Example XII illustrates an embodiment where structures formed using method300and structures formed using method900are combined. The top GAA transistor260bincludes channel layers sandwiched between the second source/drain features. The bottom GAA transistor260aincludes a less number of channel layers than the top GAA transistor260b. Further, not all channel layers of the bottom GAA transistor260aare sandwiched between the first source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a dielectric isolation layer241and becomes a “floating” channel layer. Accordingly, the bottom GAA transistor260ahas at least two active channel layers less than the top GAA transistor260b. In an alternative embodiment, the bottom GAA transistor260amay have three or more active channel layers less than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less total number of active channel layers of the first stack for epitaxial source/drain feature growth, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Example XIII illustrates an embodiment where structures formed using method500and structures formed using method900are combined. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes a less number of channel layers than the bottom GAA transistor260a. Further, not all channel layers of the top GAA transistor260bare sandwiched between the second source/drain features and able to function as active channel layers. At least a bottommost channel layer is adjoined by a CESL250and becomes a “floating” channel layer. Accordingly, the top GAA transistor260bhas at least two less active channel layers than the bottom GAA transistor260a. In an alternative embodiment, the top GAA transistor260bmay have three or more active channel layers less than the bottom GAA transistor260a. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less total number of active channel layers of the second stack for epitaxial source/drain feature growth and recessed top surfaces, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Example XIV illustrates an embodiment where structures formed using method700and structures formed using method900are combined. The top GAA transistor260bincludes channel layers sandwiched between the second source/drain features. The bottom GAA transistor260aincludes a less number of channel layers than the top GAA transistor260b. Further, not all channel layers of the bottom GAA transistor260aare sandwiched between the first source/drain features and able to function as active channel layers. At least a topmost channel layer is adjoined by a CESL230and becomes a “floating” channel layer. Accordingly, the bottom GAA transistor260ahas at least two less active channel layers than the top GAA transistor260b. In an alternative embodiment, the bottom GAA transistor260amay have three or more active channel layers less than the top GAA transistor260b. A common gate structure wraps around each channel layer of the top and bottom GAA transistors. Due to the less total number of active channel layers of the first stack for epitaxial source/drain feature growth and recessed top surfaces, the first source/drain features of the bottom GAA transistor260aare less in height and volume than the second source/drain features of the top GAA transistor260b. Example XV illustrates an embodiment where a workpiece is formed by method1100. The top and bottom GAA transistors are separated by a dielectric isolation layer242. Each of the top and bottom GAA transistors has its own gate structure. The bottom GAA transistor260aincludes channel layers sandwiched between the first source/drain features. The top GAA transistor260bincludes channel layers sandwiched between the second source/drain features. Each channel layer is an active channel layer. One difference is that the bottom GAA transistor260ahas at least one more channel layer208than the top GAA transistor260b. Accordingly, the bottom GAA transistor260ahas at least one more active channel layer than the top GAA transistor260b. In various embodiments, the bottom GAA transistor260amay have two or more active channel layers than the top GAA transistor260b. Due to the less channel layers for epitaxial source/drain feature growth, the second source/drain features of the top GAA transistor260bare less in height and volume than the first source/drain features of the bottom GAA transistor260a. Alternatively, the top GAA transistor260bmay have at least one more active channel layer than the bottom GAA transistor260ain some other embodiments. Reference is now made toFIG.101. Depending on performance needs of a device, the workpiece200may have different regions having equal or different active channel members in the pair of stacked GAA transistors, respectively. In the illustrated embodiment, Region I has a pair of stacked GAA transistors that each has equal number of active channel layers, while Region II has a pair of stacked GAA transistor that have different numbers of active channel layers. Structures similar to Example I is shown in Region II, which is for the sake of example and are non-limiting. For example, Examples II-XV inFIGS.99and100may be formed in Region II by applying processes described in methods100,300,500,700,900,1100, or combinations thereof to Region II. Embodiments of the present disclosure provide advantages. The present disclosure provides different number of active channel layers for transistors in a stacked configuration in different embodiments. By having different number of active channel layers in the stacked configuration, output currents from the pair of stacked transistors can be balanced. Further, one IC chip may include two regions, one having stacked GAA transistors with the same number of active channel layers, and another having stacked GAA transistors with different numbers of active channel layers, providing flexibility to fit different application needs on one chip and improving device performance. Furthermore, the stacked transistors formation method can be easily integrated into existing semiconductor fabrication processes. In one exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a stack of first channel layers; first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, wherein the first and second S/D epitaxial features have a first conductivity type; a stack of second channel layers stacked over the first channel layers; and third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, wherein the third and fourth S/D epitaxial features have a second conductivity type, wherein a total active channel layer number of the first channel layers is different from that of the second channel layers. In some embodiments, a difference between the total active channel layer numbers of the first channel layers and the second channel layers is equal to or larger than two. In some embodiments, the semiconductor device further includes a dielectric isolation layer that isolates at least one of the first, second, third, and fourth S/D epitaxial features from adjoining one of the first and second channel layers. In some embodiments, the dielectric isolation layer is disposed between the first channel layers and the second channel layers, wherein the dielectric isolation layer isolates both the third and fourth S/D epitaxial features from adjoining a bottommost channel layer of the second channel layers. In some embodiments, the dielectric isolation layer is disposed below a topmost channel layer of the first channel layers, wherein the dielectric isolation layer isolates both the first and second S/D epitaxial features from adjoining a bottommost channel layer of the first channel layers. In some embodiments, at least one of the first and second S/D epitaxial features has a top surface below a topmost channel layer of the first channel layers. In some embodiments, at least one of the third and fourth S/D epitaxial features has a top surface below a topmost channel layer of the second channel layers. In some embodiments, the semiconductor device further includes a first power rail under the first channel layers and a second power rail above the second channel layers, wherein the first and third S/D epitaxial features are electrically coupled to the first power rail, and the second and fourth S/D epitaxial features are electrically coupled to the second power rail. In some embodiments, the third S/D epitaxial feature is directly above the first S/D epitaxial feature, and the fourth S/D epitaxial feature is directly above the second S/D epitaxial feature. In some embodiments, the semiconductor device further includes a gate structure that wraps around each of the first and second channel layers. In some embodiments, the first and second conductivity types are opposite. In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate; a first transistor over the substrate, the first transistor including first channel layers and a first source/drain (S/D) feature adjoining active members of the first channel layers; and a second transistor over the first transistor, the second transistor including second channel layers and a second S/D feature adjoining active members of the second channel layers, wherein a number of the active members of the first channel layers is different from that of the active members of the second channel layers. In some embodiments, a number of the first channel layers is different from that of the second channel layers. In some embodiments, a number of the first channel layer equals that of the second channel layers. In some embodiments, the semiconductor device further includes a gate structure that wraps around each of the first and second channel layers. In some embodiments, the semiconductor device further includes a first gate structure that wraps around each of the first channel layers; a second gate structure that wraps around each of the second channel layers; and an isolation layer disposed between the first and second gate structures. In some embodiments, the semiconductor device further includes a power rail under the first channel layers, wherein both of the first and second S/D features are electrically coupled to the power rail. In yet another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece including a substrate portion and a stack portion over the substrate portion, the stack portion including a first stack of first channel layers interleaved by first sacrificial layers and a second stack of second channel layers interleaved by second sacrificial layers, the second stack being above the first stack; forming a fin-shaped structure from the stack portion and the substrate portion, the fin-shaped structure including a source region and a drain region; forming a first source feature in the source region and a first drain feature in the drain region; depositing an isolation layer over the first source feature and the first drain feature, the isolation layer adjoining at least a bottommost one of the second channel layers; and forming a second source feature in the source region and over the isolation layer and a second drain feature in the drain region and over the isolation layer. In some embodiments, the method further includes recessing the second source feature and the second drain feature below a topmost one of the second channel layers; and depositing a dielectric layer over the second source feature and the second drain feature, the dielectric layer adjoining the topmost one of the second channel layers. In some embodiments, the method further includes forming a first power rail under the first stack; forming a second power rail above the second stack; forming first interconnection features that electrically couple the first source feature and the second source feature to the first power rail; and forming second interconnection features that electrically couple the first drain feature and the second drain feature to the second power rail. The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 139,205 |
11862702 | DESCRIPTION OF THE EMBODIMENTS Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires). Embodiments described herein may be directed to back-end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL. Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing. One or more embodiments described herein are directed to nanowire (NW) or nanoribbon (NR) devices formed on silicon on insulator (SOI) substrates with a removed (oxidized) body beneath a channel region and remaining body beneath source and drain regions to enable high-quality bottom-seeded epitaxial growth and eliminate a need for subfin doping isolation. Embodiments may be directed to isolation schemes for nanowire (NW) and/or nanoribbon (NR) transistors using insulator fins on insulator substrates. Embodiments may be implemented to provide a nanowire/nanoribbon transistor having reduced leakage. Embodiments with reference to a nanowire may encompass wires nanowires sized as wires or ribbons, unless specifically stated for nanowire-only dimensions. To provide context, in state of the art gate-all-around (GAA) technology, the source/drain (S/D) junction can connect to substrate leading to an undesired high leaking path. State-of-the-art solutions for blocking or inhibiting source to drain leakage through semiconductor structures (such as subfin structures) beneath a nanowire device include subfin doping and/or physically increasing a gap between nanowires/nanoribbons and the underlying substrate structure. Both approaches, however, are associated with added process complexity. Embodiments of the present disclosure may be implemented to provide for: (1) the use of a bottom-seeded epitaxial region in a source/drain of a NW/NR device formed on an SOI substrate or layer transferred substrate (such as GeOI, SiGeOI, III-VOI, etc.), (2) a NW/NR process which does not require a subfin isolation scheme, yet provides high channel strain and good quality epi S/D regions, and/or (3) selective depopulation of an SOI body beneath a gated region. To provide further context, there are several integration approaches for forming NW/NR devices: (1) forming a NW/NR device on an SOI or layer transferred bulk substrate with an epitaxial region seeded laterally from channel stubs (e.g., as described below in association withFIG.1A), and (2) forming a NW/NR device on a bulk or SOI substrate with an epitaxial region seeded from the substrate beneath and from channel stubs (e.g., as described below in association withFIG.1Bfor a bulk substrate, and in association withFIG.1Cfor an SOI or XOI substrate. As a comparative example,FIG.1Aillustrates a cross-sectional view of a gate-all-around integrated circuit structure on an insulator substrate. Referring toFIG.1A, an integrated circuit structure100is on an insulator substrate104/102, such as a substrate having an insulator layer104(such as silicon oxide) on a bulk semiconductor material102(such as crystalline silicon). A vertical arrangement of horizontal semiconductor nanowires106is over the insulator substrate104/102. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires106, the gate stack including a gate electrode108and a gate dielectric110. The gate stack is on the insulator layer104of the insulator substrate104/102. A gate spacer112is on either side of the gate stack. A pair of epitaxial source or drain structures114is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires106and on the insulator layer104of the insulator substrate104/102. Source or drain contacts116are on the pair of epitaxial source or drain structures114. In one embodiment, the pair of epitaxial source or drain structures114includes defects118. Referring again toFIG.1A, a NW/NR device can be fabricated with source/drain (S/D) epitaxial material (epi) seeded laterally from channel stubs (within circled regions107). Seeding epi in this manner has been shown to produce defected/low-quality epi in the S/D. For simplicity, the epi shape in the S/D is shown generically, but it may be faceted/incompletely filled or voided/etc. Forming the device on an SOI substrate does, however, eliminate the need for a subfin doping solution to eliminate leakage current and to provide for CMOS isolation. Although, the poor quality epi grown in this and similar devices may not produce high channel stress needed for optimal device performance. As another comparative example,FIG.1Billustrates a cross-sectional view of a gate-all-around integrated circuit structure on a semiconductor substrate. Referring toFIG.1B, an integrated circuit structure120is on a bulk semiconductor substrate122(such as a bulk crystalline silicon substrate). A vertical arrangement of horizontal semiconductor nanowires126is over the bulk semiconductor substrate122. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires126, the gate stack including a gate electrode128and a gate dielectric130. The gate stack is on the bulk semiconductor substrate122. A gate spacer132is on either side of the gate stack. A pair of epitaxial source or drain structures134is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires126and on the bulk semiconductor substrate122. Source or drain contacts136are on the pair of epitaxial source or drain structures134. Referring again toFIG.1B, a NW/NR structure formed on a bulk substrate with S/D epi seeded largely from the horizontal exposed substrate123and less so from the channel stubs127. This configuration of epi growth has been shown experimentally to produce a much higher-quality/less-defected epi region than the structure shown inFIG.1A. The structure ofFIG.1Bmay, however, require a subfin isolation doping scheme to eliminate the subfin leakage paths (such as138) and provide for CMOS isolation. As another comparative example,FIG.1Cillustrates a cross-sectional view of a gate-all-around integrated circuit structure on a semiconductor body on an insulator substrate. Referring toFIG.1C, an integrated circuit structure140is on a semiconductor body145(such as a silicon body) on a buried oxide layer144(such as a silicon oxide layer) on a bulk semiconductor material142(such as crystalline silicon). A vertical arrangement of horizontal semiconductor nanowires146is over the semiconductor body145. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires146, the gate stack including a gate electrode148and a gate dielectric150. The gate stack is on the semiconductor body145. A gate spacer152is on either side of the gate stack. A pair of epitaxial source or drain structures154is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires146and on the semiconductor body145. Source or drain contacts156are on the pair of epitaxial source or drain structures154. Referring again toFIG.1C, similar structure to that of the structure ofFIG.1B, a state-of-the-art NW/NR device is fabricated on a SOI or XOI substrate with bottom-seeded epi (e.g., seeded largely from or entirely from the horizontal exposed substrate143and less so or not at all from the channel stubs147). This structure also may require a subfin doping scheme to prevent leakage current (pathway158) and provide for CMOS isolation. Disadvantages of the structures ofFIGS.1A-1Cinclude the tradeoff between channel strain and a need for a complicated subfin isolation solution. In many regards, a subfin isolation doping scheme for a NW/NR device is more complicated than that required for a finfet. Specifically, all of the NWs/NRs in same device may need to have the same nominal doping (and ideally be undoped for optimal mobility) so as to have the same electrostatics (i.e., one wire should not conduct before or after the other wires, and the Vt should be the same). Providing further context, to prevent subfin conduction, doping of approximately 3E18/cm3may be required beneath the gate in the substrate (bulk device) or body region (XOI device). To provide for highest mobility, the lowest NW/NR may be undoped (or effectively less than about 3E16/cm3). Such a doping gradient cannot be easily realized for a wide ribbon/wire via implant alone for greater than two wires spaced at about 10 nm apart. Rather, a complicated implant/dose-loss process may be required which will likely result in less optimal performance of the lower-most NW/NR. Embodiments described herein eliminate the need for such a complicated integration process and provides for high-quality epitaxial S/D growth. Embodiments described herein may be implemented to include benefits or advantages from each of the approaches described in association withFIGS.1A-1Cto provide a device structure based on a bottom-seeded epi fabricated from an SOI/XOI body, with the channel region body material “removed from” (oxidized) beneath the channel. The process may eliminate the need for a subfin isolation process. Advantages to implementing embodiments described herein include providing for high channel stress (through less-defected, higher-quality epi) and eliminating the need for a subfin isolation scheme on a NW/NR device. Value can be realized as a higher-performing device (higher channel strain), and a less costly/easier integration (no need for subfin isolation). Processes described herein integrates well with non-Si NW/NR structures (which are potentially much easier to integrate from a XOI or layer-transferred substrate). In accordance with an embodiment of the present disclosure, regarding detectability in a final product, integrated circuit structure described herein can differ from state-of-the-art NW/NR structures in regard to the “depopulated” body region beneath the channel and remnant body region beneath the S/D of the device. Structures can be formed on an SOI/XOI substrate with the body region selectively depopulated beneath the gate of the device. As an exemplary device having an insulator fin on an insulator substrate,FIG.2Aillustrates a cross-sectional view of a gate-all-around integrated circuit structure having an insulator fin on an insulator substrate, in accordance with an embodiment of the present disclosure. Referring toFIG.2A, an integrated circuit structure200is in a dielectric layer218on an insulator fin211on an insulator substrate204/202, such as a substrate having an insulator layer204(such as silicon oxide) on a bulk semiconductor material202(such as crystalline silicon). A vertical arrangement of horizontal semiconductor nanowires206is over the insulator fin211. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires206, the gate stack including a gate electrode208and a gate dielectric210. The gate stack is also overlying the insulator fin211. A gate spacer212is on either side of the gate stack. A pair of epitaxial source or drain structures214is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires206. In one embodiment, the pair of epitaxial source or drain structures214is on corresponding lower source or drain portions205at first and second ends of the insulator fin211. Thus, source or drain structures for integrated circuit structure200may be formed as epitaxial source or drain structures214together with lower source or drain portions205. Source or drain contacts216are on the pair of epitaxial source or drain structures214. Referring again toFIG.2A, epi is seeded from a crystalline body of an SOI/XOI layer at surface203(as opposed to being seeded from channel stubs207). In one embodiment, the body region is oxidized beneath the channel of the device which eliminates the need for subfin isolation doping (i.e., the oxidized body provides for isolation). As another exemplary device having an insulator fin on an insulator substrate,FIG.2Billustrates a cross-sectional view of another gate-all-around integrated circuit structure having an insulator fin on an insulator substrate, in accordance with another embodiment of the present disclosure. Referring toFIG.2B, an integrated circuit structure220is in a dielectric layer238on an insulator fin231on an insulator substrate224/222, such as a substrate having an insulator layer224(such as silicon oxide) on a bulk semiconductor material222(such as crystalline silicon). A vertical arrangement of horizontal semiconductor nanowires226is over the insulator fin231. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires226, the gate stack including a gate electrode228and a gate dielectric230. The gate stack is also overlying the insulator fin231. A gate spacer232is on either side of the gate stack. A pair of epitaxial source or drain structures234is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires226. In one embodiment, the pair of epitaxial source or drain structures234is on corresponding lower source or drain portions225at first and second ends of the insulator fin231. Thus, source or drain structures for integrated circuit structure220may be formed as epitaxial source or drain structures234together with lower source or drain portions225. Source or drain contacts236are on the pair of epitaxial source or drain structures234. Referring again toFIG.2B, referring again toFIG.2B, epi is seeded from a crystalline body at surface223(as opposed to being seeded from channel stubs237). A body region is oxidized with a catalytic oxidant (catox) material from both above and below to form insulator fin231. In one such embodiment, the process may also result in a region of the substrate also being oxidized to form oxidized substrate portion242. A remnant region240of the catalytic oxidant source may also exist in this region. In one embodiment, the catalytic oxidant source is alumina (AlOx). With reference to a process flow for fabricating the structures ofFIGS.2A and2B, in accordance with an embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes forming a vertical arrangement of horizontal semiconductor nanowires above a semiconductor fin above an insulator substrate. A dummy gate stack is then formed, the dummy gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the dummy gate stack overlying the semiconductor fin. A pair of epitaxial source or drain structures is formed at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the semiconductor fin. The dummy gate stack is then removed. The semiconductor fin is then oxidized to form an insulator fin. A permanent gate stack is then formed, the permanent gate stack surrounding the channel region of the vertical arrangement of horizontal semiconductor nanowires, and the permanent gate stack overlying the insulator fin. In an embodiment, the semiconductor fin oxidized to form the insulator fin using catalytic oxidation within a gate tub formed upon removal of the dummy gate stack. In one embodiment, alumina (AlOx) is used as a catalytic oxidant. The catalytic oxidant is deposited in the gate tub and then recessed to be confined to a subfin structure or lowest nanowire. The subfin structure or lowest nanowire is then oxidized using the catalytic oxidant which may layer be removed or retained. In an alternative embodiment, a helmeted process is used to enable wet etch of an underlying semiconductor body. Further advantages for implementing embodiments described herein include the ability to fabricate a robust transistor structure for a low power product or application. In some embodiments, a starting Si thickness in the SOI substrate is either the same as or different from the overlying nanowire or nanoribbon channel Si thickness. In some embodiments, the channel material is Si of is different than Si such as SiGe or group III-V materials. In some embodiments, the insulator material is silicon oxide or is different from silicon oxide, such as silicon nitride. In some embodiments, a source or drain structure lands on the top surface of the insulator substrate. As another exemplary device having an insulator fin on an insulator substrate,FIGS.3A and3Billustrate a gate cut cross-sectional view and a fin cut cross-sectional view, respectively, of a gate-all-around integrated circuit structure having an insulator fin on an insulator substrate, in accordance with an embodiment of the present disclosure. Referring toFIGS.3A and3B, an integrated circuit structure300includes an insulator fin305on an insulator substrate304/302, such as a substrate having an insulator layer304(such as silicon oxide) on a bulk semiconductor material302(such as crystalline silicon). A vertical arrangement of horizontal semiconductor nanowires306is over the insulator fin305. A gate stack308/308A surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires306. The gate stack308/308A is also overlying the insulator fin305(e.g., is along a top and sides of the fin305). Gate spacers314may also be included. A pair of epitaxial source or drain structures316is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires306and at first and second ends of the insulator fin305. In one embodiment, the pair of epitaxial source or drain structures316is formed as lower and upper portions, indicated by dashed line399. In an embodiment, the insulator fin305has a vertical thickness approximately the same as a vertical thickness of each of the horizontal semiconductor nanowires306of the vertical arrangement of horizontal semiconductor nanowires306, as is depicted. In another embodiment, the insulator fin305has a vertical thickness greater than a vertical thickness of each of the horizontal semiconductor nanowires306of the vertical arrangement of horizontal semiconductor nanowires306. In another embodiment, the insulator fin305has a vertical thickness less than a vertical thickness of each of the horizontal semiconductor nanowires306of the vertical arrangement of horizontal semiconductor nanowires306. In an embodiment, the insulator fin305includes silicon oxide, and the vertical arrangement of horizontal semiconductor nanowires306includes silicon. In another embodiment, the vertical arrangement of horizontal semiconductor nanowires306includes silicon germanium. In another embodiment, the vertical arrangement of horizontal semiconductor nanowires306includes a group III-V material. In an embodiment, the insulator substrate304/302includes a layer304of silicon oxide, and the insulator fin305is on the layer of silicon oxide. In another embodiment, the insulator substrate304/302includes a layer304of silicon nitride, and the insulator fin305is on the layer of silicon nitride. In an embodiment, a bottom of the pair of epitaxial source or drain structures316is on the insulator substrate304/302, as is depicted. In one such embodiment, the bottom of the pair of epitaxial source or drain structures316is co-planar with a bottom of the insulator fin305, as is depicted. In an embodiment, the pair of epitaxial source or drain structures316is a pair of non-discrete epitaxial source or drain structures, as is depicted, and as is described in greater detail below. For clarity of illustration, gate stacks308and308A are depicted as separate structures. However, in an embodiment, the regions308and308A are continuous structures. In one such embodiment, the gate stack includes a gate electrode312and a gate dielectric310. It is to be appreciated that both the gate electrode312and a gate dielectric310may be continuous around and between the insulator fin305and the vertical arrangement of horizontal semiconductor nanowires306. As another exemplary device having an insulator fin on an insulator substrate,FIG.4illustrates a cross-sectional view of another gate-all-around integrated circuit structure having an insulator fin on an insulator substrate, in accordance with another embodiment of the present disclosure. Referring toFIG.4, an integrated circuit structure400includes a vertical arrangement of horizontal semiconductor nanowires406above an insulator fin405. A gate stack408A/408B (with gate electrode408A and gate dielectric408B) surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires406and overlies the insulator fin405(e.g., is along a top and sides of the insulator fin405, although only the former depicted in the view ofFIG.4where side coverage by the gate stack408A/408B along sides of the insulator fin405is at locations into and out of the page of the perspective ofFIG.4). A pair of non-discrete epitaxial source or drain structures410is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires406and at first and second ends of the insulator fin405. In one embodiment, the pair of epitaxial source or drain structures410is formed as lower and upper portions, indicated by dashed line499. A pair of dielectric spacers412is between the pair of non-discrete epitaxial source or drain structures410and the gate stack408A/408B. In one embodiment, the pair of dielectric spacers412and the gate stack408A/408B have co-planar top surfaces, e.g., at surface420, as is depicted. In one such embodiment, an etch stop layer or dielectric layer416is formed on the surface420. In one embodiment, the pair of dielectric spacers412, the insulator fin405and the pair of non-discrete epitaxial source or drain structures410have co-planar bottom surfaces, e.g., at surface430, as is depicted. The surface430is on an insulator substrate454/452, such as a substrate having an insulator layer454(such as silicon oxide) on a bulk semiconductor material452(such as crystalline silicon). In an embodiment, one or both of the pair of non-discrete epitaxial source or drain structures has a dielectric material thereon (represented by414in one embodiment). In one such embodiment, wherein the dielectric material414, the pair of dielectric spacers412and the gate stack408A/408B have co-planar top surfaces, as is depicted at surface420. In an embodiment, one or both of the pair of non-discrete epitaxial source or drain structures has a top conductive contact thereon (represented by414in another embodiment). In one such embodiment, wherein the top conductive contact414, the pair of dielectric spacers412and the gate stack408A/408B have co-planar top surfaces, as is depicted at surface420. In an embodiment, insulator fin405blocks or eliminates a parasitic conduction path (e.g., path460from Source410to Drain410) for improved device performance. In accordance with an embodiment of the present disclosure, with reference again toFIG.4, a method of fabricating an integrated circuit structure400includes forming a vertical arrangement of horizontal semiconductor nanowires406above an insulator fin405above a semiconductor substrate (not shown). A gate stack408A/408B is then formed, the gate stack408A/408B surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires406, and the gate stack408A/408B overlying the insulator fin405. A pair of epitaxial source or drain structures410is formed at first and second ends of the vertical arrangement of horizontal semiconductor nanowires406and at first and second ends of the insulator fin405. The semiconductor substrate is removed to expose a bottom of the insulator fin405and a bottom of the epitaxial source or drain structures410. An insulator substrate454/452is bonded to the bottom of the insulator fin405and to the bottom of the epitaxial source or drain structures410. It is to be appreciated that, in a particular embodiment, channel layers of nanowires (or nanoribbons) and initial (pre-oxidation) underlying fins or subfins may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material composed of a very substantial amount of, if not all, silicon. However, it is to be appreciated that, practically, 100% pure Si may be difficult to form and, hence, could include a tiny percentage of carbon, germanium or tin. Such impurities may be included as an unavoidable impurity or component during deposition of Si or may “contaminate” the Si upon diffusion during post deposition processing. As such, embodiments described herein directed to a silicon layer may include a silicon layer that contains a relatively small amount, e.g., “impurity” level, non-Si atoms or species, such as Ge, C or Sn. It is to be appreciated that a silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic. It is to be appreciated that, in a particular embodiment, release layers between channel layers of nanowires (or nanoribbons) and underlying fins or subfins may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of substantial portions of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In particular embodiments, a silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si40Ge60). In other embodiments, the amount of silicon is greater than the amount of germanium. In particular embodiments, a silicon germanium layer includes approximately 30% germanium and approximately 70% silicon (Si70Ge30). It is to be appreciated that, practically, 100% pure silicon germanium (referred to generally as SiGe) may be difficult to form and, hence, could include a tiny percentage of carbon or tin. Such impurities may be included as an unavoidable impurity or component during deposition of SiGe or may “contaminate” the SiGe upon diffusion during post deposition processing. As such, embodiments described herein directed to a silicon germanium layer may include a silicon germanium layer that contains a relatively small amount, e.g., “impurity” level, non-Ge and non-Si atoms or species, such as carbon or tin. It is to be appreciated that a silicon germanium layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic. It is to be appreciated that the embodiments described herein can also include other implementations such as nanowires and/or nanoribbons with various widths, thicknesses and/or materials including but not limited to Si, Ge, SiGe and/or Group III-V materials. Described below are various devices and processing schemes that may be used to fabricate a device with an insulator fin on an insulator substrate. It is to be appreciated that the exemplary embodiments need not necessarily require all features described, or may include more features than are described. As another exemplary device having an insulator fin on an insulator substrate,FIG.5illustrates an angled cross-sectional view of another gate-all-around integrated circuit structure having an insulator fin on an insulator substrate, in accordance with another embodiment of the present disclosure. Referring toFIG.5, an integrated circuit structure includes a plurality of insulator fins505on an insulator substrate595/597, such as a substrate having an insulator layer595(such as silicon oxide) on a bulk semiconductor material597(such as crystalline silicon). A corresponding vertical arrangement of horizontal semiconductor nanowires540is over each of the plurality of insulator fins505. A corresponding gate stack surrounds a channel region of each of the vertical arrangements of horizontal semiconductor nanowires540. The gate stack can include a gate electrode570and a gate dielectric562. Each gate stack is also overlying a corresponding insulator fin505. A gate spacer550is on either side of the gate stack. Epitaxial source or drain structures544is at first and second ends of each of the vertical arrangement of horizontal semiconductor nanowires540and at first and second ends of the insulator fins505. In one embodiment, the epitaxial source or drain structures544are formed as lower and upper portions, indicated by dashed line544A. An etch stop layer599may be formed over the epitaxial source or drain structures544and the gate stacks, as is depicted. In another aspect, integrated circuit structures described herein may be fabricated using a back-side reveal of front-side structures fabrication approach. In some exemplary embodiments, reveal of the back-side of a transistor or other device structure entails wafer-level back-side processing. A reveal of the back-side of a transistor approach may be employed for example to remove at least a portion of a carrier layer and intervening layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a carrier layer in the donor-host substrate is polished (e.g., CMP) and/or etched with a wet or dry (e.g., plasma) etch process. Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the carrier layer may be employed. For example, where the carrier layer is a group IV semiconductor (e.g., silicon) a CMP slurry known to be suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed. In some embodiments, the above is preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intervening layer. The cleaving or fracture process may be utilized to remove a substantial portion of the carrier layer as a bulk mass, reducing the polish or etch time needed to remove the carrier layer. For example, where a carrier layer is 400-900 μm in thickness, 100-700 μm may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly may then be polished or etched to complete removal. Alternatively, where the carrier layer is not fractured, the grind, polish and/or etch operation may be employed to remove a greater thickness of the carrier layer. Next, exposure of an intervening layer is detected. Detection is used to identify a point when the back-side surface of the donor substrate has advanced to nearly the device layer. Any endpoint detection technique known to be suitable for detecting a transition between the materials employed for the carrier layer and the intervening layer may be practiced. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorbance or emission of the back-side surface of the donor substrate during the polishing or etching performed. In some other embodiments, the endpoint criteria are associated with a change in optical absorbance or emission of byproducts during the polishing or etching of the donor substrate back-side surface. For example, absorbance or emission wavelengths associated with the carrier layer etch byproducts may change as a function of the different compositions of the carrier layer and intervening layer. In other embodiments, the endpoint criteria are associated with a change in mass of species in byproducts of polishing or etching the back-side surface of the donor substrate. For example, the byproducts of processing may be sampled through a quadrupole mass analyzer and a change in the species mass may be correlated to the different compositions of the carrier layer and intervening layer. In another exemplary embodiment, the endpoint criteria is associated with a change in friction between a back-side surface of the donor substrate and a polishing surface in contact with the back-side surface of the donor substrate. Detection of the intervening layer may be enhanced where the removal process is selective to the carrier layer relative to the intervening layer as non-uniformity in the carrier removal process may be mitigated by an etch rate delta between the carrier layer and intervening layer. Detection may even be skipped if the grind, polish and/or etch operation removes the intervening layer at a rate sufficiently below the rate at which the carrier layer is removed. If an endpoint criteria is not employed, a grind, polish and/or etch operation of a predetermined fixed duration may stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch. In some examples, the carrier etch rate: intervening layer etch rate is 3:1-10:1, or more. Upon exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be removed uniformly by a polish, for example. Alternatively, a thickness of the intervening layer may be removed with a masked or blanket etch process. The process may employ the same polish or etch process as that employed to thin the carrier, or may be a distinct process with distinct process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polish or etch process that favors removal of the intervening layer over removal of the device layer. Where less than a few hundred nanometers of intervening layer thickness is to be removed, the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled than that employed for removal of the carrier layer. A CHIP process employed may, for example employ a slurry that offers very high selectively (e.g., 100:1-300:1, or more) between semiconductor (e.g., silicon) and dielectric material (e.g., SiO) surrounding the device layer and embedded within the intervening layer, for example, as electrical isolation between adjacent device regions. For embodiments where the device layer is revealed through complete removal of the intervening layer, back-side processing may commence on an exposed back-side of the device layer or specific device regions there in. In some embodiments, the back-side device layer processing includes a further polish or wet/dry etch through a thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region. The above described processing scheme may result in a donor-host substrate assembly that includes IC devices that have a back-side of an intervening layer, a back-side of the device layer, and/or back-side of one or more semiconductor regions within the device layer, and/or front-side metallization revealed. Additional back-side processing of any of these revealed regions may then be performed during downstream processing. In accordance with one or more embodiments of the present disclosure, following a backside reveal process an insulator substrate, such as a substrate having an insulator layer (such as silicon oxide) on a bulk semiconductor material (such as crystalline silicon) is bonded to exposed bottom surfaces of the bottommost wires (fins) and to exposed bottom surfaces of epitaxial source or drain structures. It is to be appreciated that the structures resulting from the above exemplary processing schemes may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and/or NMOS device fabrication. As an example of a possible completed device, and as another exemplary device having an insulator fin on an insulator substrate,FIG.6illustrates a cross-sectional views of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. Referring toFIG.6, a semiconductor structure or device600includes a non-planar active region (e.g., a fin structure including protruding fin portion604) on a dielectric layer695of an insulator substrate697/695. In an embodiment, instead of a solid fin, the non-planar active region is separated between regions604A and604B to provide a semiconductor nanowire604A and an insulator fin604B (e.g., oxidized semiconductor fin) with the gate structure608there between. In either case, for ease of description for non-planar integrated circuit structure600, a non-planar active region604is referenced below as a protruding fin portion. A gate line608is disposed over the protruding portions604of the non-planar active region (including, if applicable, surrounding nanowire604A and insulator fin604B), as well as over a portion of the dielectric layer695. As shown, gate line608includes a gate electrode650and a gate dielectric layer652. In one embodiment, gate line608may also include a dielectric cap layer654. A gate contact614, and overlying gate contact via616are also seen from this perspective, along with an overlying metal interconnect660, all of which are disposed in inter-layer dielectric stacks or layers670. An etch stop layer699may be formed on the interconnect660and inter-layer dielectric stacks or layers670, as is depicted. Also seen from the perspective ofFIG.6, the gate contact614is, in one embodiment, disposed over dielectric layer695, but not over the non-planar active regions. In another embodiment, however, the gate contact614is over the non-planar active regions. In an embodiment, the semiconductor structure or device600is a non-planar device such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines608surround at least a top surface and a pair of sidewalls of the three-dimensional body. Although not depicted inFIG.6, it is to be appreciated that source or drain regions of or adjacent to the protruding fin portions604are on either side of the gate line608, i.e., into and out of the page. In one embodiment, the material of the protruding fin portions604in the source or drain locations is removed and replaced with another semiconductor material, e.g., by epitaxial deposition to form epitaxial source or drain structures. The source or drain regions may extend to the top surface of the dielectric layer695. In accordance with an embodiment of the present disclosure, the insulator fin604B inhibits source to drain leakage. With reference again toFIG.6, in an embodiment, nanowires604A are composed of crystalline silicon layer which may be doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof. In an embodiment, insulator fin604B is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Gate line608may be composed of a gate electrode stack which includes a gate dielectric layer652and a gate electrode layer650. In an embodiment, the gate electrode layer650of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer652is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer652may include a layer of native oxide formed from the top few layers of the nanowires604A. In an embodiment, the gate dielectric layer652is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer652is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In one embodiment, the gate electrode layer650is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode layer650is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer650may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer650may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer650may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Gate contact614and overlying gate contact via616may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). In an embodiment (although not shown), a contact pattern which is essentially perfectly aligned to an existing gate pattern608is formed while eliminating the use of a lithographic step with exceedingly tight registration budget. In an embodiment, the contact pattern is a vertically symmetric contact pattern, or an asymmetric contact pattern. In other embodiments, all contacts are front-side connected and are not asymmetric. In one such embodiment, the self-aligned approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts. In an embodiment, providing structure600involves fabrication of the gate stack structure608by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid. Referring again toFIG.6, the arrangement of semiconductor structure or device600places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region, e.g., over a nanowire604A, and in a same layer as a trench contact via. It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a sub-10 nanometer (10 nm) technology node. In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods. In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect. In an embodiment, as is also used throughout the present description, hardmask materials, capping layers, or plugs are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer, capping or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hardmask, capping or plug layers known in the arts may be used depending upon the particular implementation. The hardmask, capping or plug layers maybe formed by CVD, PVD, or by other deposition methods. In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion lithography (i193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer. In another aspect, one or more embodiments are directed to neighboring semiconductor structures or devices separated by self-aligned gate endcap (SAGE) structures. Particular embodiments may be directed to integration of multiple width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by a SAGE wall. In an embodiment, nanowires/nanoribbons are integrated with multiple Wsi in a SAGE architecture portion of a front-end process flow. Such a process flow may involve integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., portions of nanowires removed and then source or drain (S/D) growth is performed). To provide further context, advantages of a self-aligned gate endcap (SAGE) architecture may include the enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing. To provide illustrative comparison,FIG.7illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. Referring to the left-hand side (a) ofFIG.7, an integrated circuit structure700includes a substrate702having fins704protruding there from by an amount706above an isolation structure708laterally surrounding lower portions of the fins704. Corresponding nanowires705are over the fins704. A gate structure may be formed over the integrated circuit structure700to fabricate a device. However, breaks in such a gate structure may be accommodated for by increasing the spacing between fin704/nanowire705pairs. Referring again to part (a) ofFIG.7, in an embodiment, during a replacement gate process, the exposed portions of fins704are oxidized to form insulator fins beneath the nanowires705. Oxidation may be only for the exposed portion (i.e., to level734) but could also extend into the fin (i.e., to level732) or all the way through the fin (i.e., to level730), effectively providing an insulator fin on a bulk substrate (as opposed to on an insulator substrate as described above). By contrast, referring to the right-hand side (b) ofFIG.7, an integrated circuit structure750includes a substrate752having fins754protruding therefrom by an amount756above an isolation structure758laterally surrounding lower portions of the fins754. Corresponding nanowires755are over the fins754. Isolating SAGE walls760(which may include a hardmask thereon, as depicted) are included within the isolation structure752and between adjacent fin754/nanowire755pairs. The distance between an isolating SAGE wall760and a nearest fin754/nanowire755pair defines the gate endcap spacing762. A gate structure may be formed over the integrated circuit structure750, between insolating SAGE walls to fabricate a device. Breaks in such a gate structure are imposed by the isolating SAGE walls. Since the isolating SAGE walls760are self-aligned, restrictions from conventional approaches can be minimized to enable more aggressive diffusion to diffusion spacing. Furthermore, since gate structures include breaks at all locations, individual gate structure portions may be layer connected by local interconnects formed over the isolating SAGE walls760. In an embodiment, as depicted, the SAGE walls760each include a lower dielectric portion and a dielectric cap on the lower dielectric portion. Referring again to part (b) ofFIG.7, in an embodiment, during a replacement gate process, the exposed portions of fins754are oxidized to form insulator fins beneath the nanowires755. Oxidation may be only for the exposed portion (i.e., to level784) but could also extend into the fin (i.e., to level782) or all the way through the fin (i.e., to level780), effectively providing an insulator fin on a bulk substrate (as opposed to on an insulator substrate as described above). A self-aligned gate endcap (SAGE) processing scheme involves the formation of gate/trench contact endcaps self-aligned to fins without requiring an extra length to account for mask mis-registration. Thus, embodiments may be implemented to enable shrinking of transistor layout area. Embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls or self-aligned gate endcap (SAGE) walls. In an embodiment, as described throughout, self-aligned gate endcap (SAGE) isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another. Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide. To highlight an exemplary integrated circuit structure having two vertically arranged nanowires over an insulator fin,FIG.8Aillustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.FIG.8Billustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure ofFIG.8A, as taken along the a-a′ axis.FIG.8Cillustrates a cross-sectional channel view of the nanowire-based integrated circuit structure ofFIG.8A, as taken along the b-b′ axis. Referring toFIG.8A, an integrated circuit structure800includes one or more vertically stacked nanowires (804set) above a substrate802. In an embodiment, as depicted, an insulator layer802B and a bulk semiconductor layer802A are included in substrate802, as is depicted. Embodiments herein are targeted at both single wire devices and multiple wire devices. As an example, a two nanowire-based devices having nanowires804B and804C is shown for illustrative purposes. For convenience of description, nanowire804B is used as an example where description is focused on one of the nanowires. It is to be appreciated that where attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or essentially the same attributes for each of the nanowires. In either case, the one nanowire or the plurality of nanowires is over an insulator fin899(which may be an oxidized nanowire804A). Each of the nanowires804B and804C includes a channel region806in the nanowire. The channel region806has a length (L). The channel region also has a perimeter orthogonal to the length (L). Referring to bothFIGS.8A and8C, a gate electrode stack808surrounds the entire perimeter of each of the channel regions806. The gate electrode stack808includes a gate electrode along with a gate dielectric layer between the channel region806and the gate electrode (not shown). In an embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack808without any intervening material such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments having a plurality of nanowires804, the channel regions806of the nanowires are also discrete relative to one another. Referring to bothFIGS.8A and8B, integrated circuit structure800includes a pair of non-discrete source or drain regions810/812. The pair of non-discrete source or drain regions810/812is on either side of the channel regions806of the plurality of vertically stacked nanowires804. Furthermore, the pair of non-discrete source or drain regions810/812is adjoining for the channel regions806of the plurality of vertically stacked nanowires804. In one such embodiment, not depicted, the pair of non-discrete source or drain regions810/812is directly vertically adjoining for the channel regions806in that epitaxial growth is on and between nanowire portions extending beyond the channel regions806, where nanowire ends are shown within the source or drain structures. In another embodiment, as depicted inFIG.8A, the pair of non-discrete source or drain regions810/812is indirectly vertically adjoining for the channel regions806in that they are formed at the ends of the nanowires and not between the nanowires. In an embodiment, as depicted, the source or drain regions810/812are non-discrete in that there are not individual and discrete source or drain regions for each channel region806of a nanowire804. Accordingly, in embodiments having a plurality of nanowires804, the source or drain regions810/812of the nanowires are global or unified source or drain regions as opposed to discrete for each nanowire. That is, the non-discrete source or drain regions810/812are global in the sense that a single unified feature is used as a source or drain region for a plurality (in this case, 3) of nanowires804and, more particularly, for more than one discrete channel region806. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions806, each of the pair of non-discrete source or drain regions810/812is approximately rectangular in shape with top vertex portion, as depicted inFIG.8B. In other embodiments, however, the source or drain regions810/812of the nanowires are relatively larger yet discrete non-vertically merged epitaxial structures such as nubs. In accordance with an embodiment of the present disclosure, and as depicted inFIGS.8A and8B, integrated circuit structure800further includes a pair of contacts814, each contact814on one of the pair of non-discrete source or drain regions810/812. In one such embodiment, in a vertical sense, each contact814completely surrounds the respective non-discrete source or drain region810/812. In another aspect, the entire perimeter of the non-discrete source or drain regions810/812may not be accessible for contact with contacts814, and the contact814thus only partially surrounds the non-discrete source or drain regions810/812, as depicted inFIG.8B. In a contrasting embodiment, not depicted, the entire perimeter of the non-discrete source or drain regions810/812, as taken along the a-a′ axis, is surrounded by the contacts814. Referring again toFIG.8A, in an embodiment, integrated circuit structure800further includes a pair of spacers816. As is depicted, outer portions of the pair of spacers816may overlap portions of the non-discrete source or drain regions810/812, providing for “embedded” portions of the non-discrete source or drain regions810/812beneath the pair of spacers816. As is also depicted, the embedded portions of the non-discrete source or drain regions810/812may not extend beneath the entirety of the pair of spacers816. In an embodiment, the nanowires804B and804C may be sized as wires or ribbons, as described below, and may have squared-off or rounder corners. In an embodiment, the nanowires804B and804C are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single-crystalline. For example, for a silicon nanowire, a single-crystalline nanowire may be based from a (100) global orientation, e.g., with a <100> plane in the z-direction. As described below, other orientations may also be considered. In an embodiment, the dimensions of the nanowires, from a cross-sectional perspective, are on the nano-scale. For example, in a specific embodiment, the smallest dimension of the nanowire is less than approximately 20 nanometers. In an embodiment, the nanowires are composed of a strained material, particularly in the channel regions806. Referring toFIG.8C, in an embodiment, each of the channel regions806has a width (Wc) and a height (Hc), the width (Wc) approximately the same as the height (Hc). That is, in both cases, the channel regions806are square-like or, if corner-rounded, circle-like in cross-section profile. In another aspect, the width and height of the channel region need not be the same, such as the case for nanoribbons as described throughout. In an embodiment, as described throughout, an integrated circuit structure effectively includes an oxidized non-planar device such as, but not limited to, an oxidized finFET or an oxidized tri-gate device, with corresponding one or more overlying nanowire structures. In one embodiment, a gate structure surrounds each of the one or more discrete nanowire channel portions and, possibly, a portion of the oxidized finFET or the oxidized tri-gate device. In an embodiment, as described throughout, an underlying semiconductor substrate (which can ultimately be removed and replaced with an insulator substrate or an insulator on semiconductor substrate, or which is already beneath an overlying insulator layer) may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. A bulk substrate may alternatively be composed of a group III-V material. In an embodiment, a bulk substrate is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is composed of a group III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein. FIG.9illustrates a computing device900in accordance with one implementation of an embodiment of the present disclosure. The computing device900houses a board902. The board902may include a number of components, including but not limited to a processor904and at least one communication chip906. The processor904is physically and electrically coupled to the board902. In some implementations the at least one communication chip906is also physically and electrically coupled to the board902. In further implementations, the communication chip906is part of the processor904. Depending on its applications, computing device900may include other components that may or may not be physically and electrically coupled to the board902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The communication chip906enables wireless communications for the transfer of data to and from the computing device900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip906may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device900may include a plurality of communication chips906. For instance, a first communication chip906may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip906may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor904of the computing device900includes an integrated circuit die packaged within the processor904. The integrated circuit die of the processor904may include one or more structures, such as gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, built in accordance with implementations of embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip906also includes an integrated circuit die packaged within the communication chip906. The integrated circuit die of the communication chip906may include one or more structures, such as gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, built in accordance with implementations of embodiments of the present disclosure. In further implementations, another component housed within the computing device900may contain an integrated circuit die that includes one or structures, such as gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, built in accordance with implementations of embodiments of the present disclosure. In various implementations, the computing device900may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device900may be any other electronic device that processes data. FIG.10illustrates an interposer1000that includes one or more embodiments of the present disclosure. The interposer1000is an intervening substrate used to bridge a first substrate1002to a second substrate1004. The first substrate1002may be, for instance, an integrated circuit die. The second substrate1004may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1000is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1000may couple an integrated circuit die to a ball grid array (BGA)1006that can subsequently be coupled to the second substrate1004. In some embodiments, the first and second substrates1002/1004are attached to opposing sides of the interposer1000. In other embodiments, the first and second substrates1002/1004are attached to the same side of the interposer1000. And in further embodiments, three or more substrates are interconnected by way of the interposer1000. The interposer1000may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer1000may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer1000may include metal interconnects1008and vias1010, including but not limited to through-silicon vias (TSVs)1012. The interposer1000may further include embedded devices1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1000. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer1000or in the fabrication of components included in the interposer1000. Thus, embodiments of the present disclosure include gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate. The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. Example embodiment 1: An integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin. Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein the insulator fin has a vertical thickness approximately the same as a vertical thickness of each of the nanowires of the vertical arrangement of horizontal semiconductor nanowires. Example embodiment 3: The integrated circuit structure of example embodiment 1, wherein the insulator fin has a vertical thickness greater than a vertical thickness of each of the nanowires of the vertical arrangement of horizontal semiconductor nanowires. Example embodiment 4: The integrated circuit structure of example embodiment 1, wherein the insulator fin has a vertical thickness less than a vertical thickness of each of the nanowires of the vertical arrangement of horizontal semiconductor nanowires. Example embodiment 5: The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the insulator fin includes silicon oxide, and the vertical arrangement of horizontal semiconductor nanowires includes silicon. Example embodiment 6: The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the vertical arrangement of horizontal semiconductor nanowires includes silicon germanium or a group III-V material. Example embodiment 7: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the insulator substrate includes a layer of silicon oxide, and the insulator fin is on the layer of silicon oxide. Example embodiment 8: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the insulator substrate includes a layer of silicon nitride, and the insulator fin is on the layer of silicon nitride. Example embodiment 9: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein a bottom of the pair of epitaxial source or drain structures is on the insulator substrate. Example embodiment 10: The integrated circuit structure of example embodiment 9, wherein the bottom of the pair of epitaxial source or drain structures is co-planar with a bottom of the insulator fin. Example embodiment 11: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein the insulator substrate includes a remnant catalyst material beneath the insulator fin. Example embodiment 12: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures. Example embodiment 13: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the gate stack includes a high-k gate dielectric layer and a metal gate electrode. Example embodiment 14: A method of fabricating an integrated circuit structure includes forming a vertical arrangement of horizontal semiconductor nanowires above a semiconductor fin above an insulator substrate. A dummy gate stack is then formed, the dummy gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the dummy gate stack overlying the semiconductor fin. A pair of epitaxial source or drain structures is formed at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the semiconductor fin. The dummy gate stack is then removed. The semiconductor fin is then oxidized to form an insulator fin. A permanent gate stack is then formed, the permanent gate stack surrounding the channel region of the vertical arrangement of horizontal semiconductor nanowires, and the permanent gate stack overlying the insulator fin. Example embodiment 15: The method of example embodiment 14, wherein forming the pair of epitaxial source or drain structures includes forming a non-discrete pair of epitaxial source or drain structures. Example embodiment 16: A computing device includes a board, and a component coupled to the board. The component includes an integrated circuit structure including an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin. Example embodiment 17: The computing device of example embodiment 16, further including a memory coupled to the board. Example embodiment 18: The computing device of example embodiment 16 or 17, further including a communication chip coupled to the board. Example embodiment 19: The computing device of example embodiment 16, 17 or 18, wherein the component is a packaged integrated circuit die. Example embodiment 20: The computing device of example embodiment 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. | 82,872 |
11862703 | DESCRIPTION OF THE EMBODIMENTS Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires). Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL. Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing. One or more embodiments described herein are directed to structures including stacks of nanoribbons of differing composition. One or more embodiments are directed to a thick gate high voltage silicon germanium (SiGe) PMOS nanoribbons integration scheme for system on chip (SoC) designs. To provide context, state-of-the-art CMOS nanoribbon transistors utilize silicon (Si) nanoribbons to fabricate both NMOS and PMOS transistors. Fundamentally, SiGe channel material is more favorable for PMOS logic and high-voltage/analog capable transistors. NMOS and PMOS FinFETs have been fabricated using silicon and either well doping or N/P type work functions to distinguish the two devices. For the 7 nm node and beyond, strain engineering using conventional source/drain (S/D) epitaxial growth or liners is very challenging. A silicon germanium based PFET is a potential solution to engineering PMOS devices. Embodiments described herein include a process scheme that enables co-integration of high-performance Si nanoribbon NMOS and SiGe nanoribbon PMOS transistors. In an embodiment, co-integration of high-performance Si nanoribbon NMOS with SiGe nanoribbon PMOS transistors can be implemented to fabricate logic, analog and high-voltage devices. Advantages for implementing one or more embodiments described herein can include one or more of (1) integration compatibility with current nodes in development/manufacturing, (2) mobility enhancement and reliability advantage of SiGe nanoribbons, and/or (3) multi Vt systems meet both high-performance and low power design needs. Embodiments described herein can be revealed by cross-sectional transmission electron microscope (TEM) imaging to show two-dimensional (2D) silicon (Si) nanoribbon transistors and 2D SiGe nanoribbon devices on a same chip. Embodiments may pertain to nanoribbons, FinFETs, SoC thick gate, and/or SiGe channel applications. As used throughout, a nanowire typically refers to a structure having similar or the same width and height dimensions orthogonal to a channel length. A nanoribbon typically refers to a structure having differing width and height dimensions orthogonal to a channel length, e.g., greater width than height orthogonal to a channel length. In general, unless described relative to one another, e.g., a structure having both a nanowire stack and a nanoribbon stack, or unless specified as such, the term nanowire is often used throughout to exemplify a gate-all-around device which could be sized as a nanoribbon or a nanowire. For comparative purposes,FIG.1illustrates cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure having a singular nanowire/nanoribbon channel structure. Referring to part (a) ofFIG.1, a starting structure100includes a substrate102having a sacrificial base layer104and a plurality of active layers106. A plurality of additional sacrificial release layers108is interleaved with the plurality of active layers106. The starting structure100can also include a dielectric layer110thereon, as is depicted. Referring to part (b) ofFIG.1, a fin pattern and etch process is used to form nanowire-forming (or nanoribbon-forming) stacks112on a patterned substrate102A. Each nanowire-forming stack112includes a sub-fin structure103formed from etching into substrate102. Each nanowire-forming stack112also includes a patterned sacrificial base layer104A, and a plurality of nanowire layers106A, and a plurality of sacrificial nanowire release layers108A interleaved with the plurality of nanowire layers106A. Each nanowire-forming stack112can also include a dielectric cap110A thereon, as is depicted. As explained in greater detail in other embodiments described herein, channel regions of the plurality of nanowire-forming stacks112may then be exposed, e.g., during a replacement gate process, prior to performing the subsequent nanowire release process described below. Part (c) ofFIG.1is taken through such a channel region. Referring to part (c) ofFIG.1, an isolation structure114, such as a shallow trench isolation (STI) structure is formed adjacent to the sub-fin structures103. The patterned sacrificial base layers104A and the plurality of sacrificial nanowire release layers108A are removed to form nanowire stacks116. Each nanowire stack116includes released nanowires106B and, if included, an overlying released dielectric cap110B. Embodiments described herein can involve modification of the nanoribbon process flow ofFIG.1with additional patterning operations to create regions of Si nanoribbon NMOS and SiGe nanoribbon PMOS transistors. As a generalized example,FIG.2illustrates cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure having a dual nanowire/nanoribbon channel structure, in accordance with an embodiment of the present disclosure. Referring to part (a) ofFIG.2, a starting structure200includes a substrate202having a sacrificial base layer204and a plurality of first active layers206. A plurality of second active layers208is interleaved with the plurality of first active layers206. The starting structure200can also include a dielectric layer210thereon, as is depicted. In an embodiment, substrate202is a monocrystalline silicon substrate, the plurality of first active layers206is a plurality of silicon layers, the sacrificial base layer204is a silicon germanium base layer, and the plurality of second active layers208is a plurality of silicon germanium layers. In an embodiment, dielectric layer210is or includes silicon oxide, silicon dioxide, silicon nitride, or silicon oxynitride. Referring to part (b) ofFIG.2, a fin pattern and etch process is used to form first nanowire-forming (or nanoribbon-forming) stacks212and second nanowire-forming (or nanoribbon-forming) stacks213on a patterned substrate202A. Each nanowire-forming stack212or213includes a sub-fin structure203formed from etching into substrate202. Each nanowire-forming stack212or213also includes a patterned sacrificial base layer204A. Each nanowire-forming stack212can be viewed as including a plurality of first nanowire layers206A, and a plurality of first sacrificial nanowire release layers208A interleaved with the plurality of first nanowire layers206A. On the other hand, each nanowire-forming stack213can be viewed as including a plurality of second nanowire layers208A, and a plurality of second sacrificial nanowire release layers206A interleaved with the plurality of second nanowire layers208A. Each nanowire-forming stack212or213can also include a dielectric cap210A thereon, as is depicted. As explained in greater detail in other embodiments described herein, channel regions of the plurality of nanowire-forming stacks212or213may then be exposed, e.g., during a replacement gate process, prior to performing the subsequent nanowire release process described below. Part (c) ofFIG.2is taken through such a channel region. Referring to part (c) ofFIG.2, an isolation structure214, such as a shallow trench isolation (STI) structure is formed adjacent to the sub-fin structures203. The patterned sacrificial base layers204A are removed. For nanowire-forming stacks212, the plurality of first sacrificial nanowire release layers208A are removed to form nanowire stacks216. Each nanowire stack216includes released nanowires206B and, if included, an overlying released dielectric cap210B, as is depicted. For nanowire-forming stacks213, the plurality of second sacrificial nanowire release layers206A are removed to form nanowire stacks217. Each nanowire stack217includes released nanowires208B and, if included, an overlying released dielectric cap. However, in some embodiments, the dielectric cap of each nanowire stack217is removed, as is depicted, to enable access of a gate structure to the top surface of the top nanowire of the released nanowires208B. In an embodiment, individual ones of the released nanowires208B of each nanowire stack217are thinner (vertical direction) than the individual ones of the released nanowires206B of each nanowire stack216, as is depicted. In another embodiment, individual ones of the released nanowires208B of each nanowire stack217are thicker (vertical direction) than the individual ones of the released nanowires206B of each nanowire stack216. In another embodiment, individual ones of the released nanowires208B of each nanowire stack217are the same thickness (vertical direction) as the individual ones of the released nanowires206B of each nanowire stack216. As an exemplary process flow for achieving a dual nanowire/nanoribbon structure ofFIG.2,FIGS.3A-3Iillustrate cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure having a dual nanowire/nanoribbon channel structure, in accordance with an embodiment of the present disclosure. Referring toFIG.3A, a starting structure300includes a substrate302having a sacrificial base layer304and a plurality of first active layers306. A plurality of second active layers308is interleaved with the plurality of first active layers306. The starting structure300can also include a dielectric layer310thereon, as is depicted. In an embodiment, substrate302is a monocrystalline silicon substrate, the plurality of first active layers306is a plurality of silicon layers, the sacrificial base layer304is a silicon germanium base layer, and the plurality of second active layers308is a plurality of silicon germanium layers. In an embodiment, dielectric layer310is or includes silicon oxide, silicon dioxide, silicon nitride, or silicon oxynitride. Referring toFIG.3B, a fin pattern and etch process is used to form first nanowire-forming (or nanoribbon-forming) stacks312and second nanowire-forming (or nanoribbon-forming) stacks313on a patterned substrate302A. Each nanowire-forming stack312or313includes a sub-fin structure303formed from etching into substrate302. Each nanowire-forming stack312or313also includes a patterned sacrificial base layer304A. Each nanowire-forming stack312can be viewed as including a plurality of first nanowire layers306A, and a plurality of first sacrificial nanowire release layers308A interleaved with the plurality of first nanowire layers306A. On the other hand, each nanowire-forming stack313can be viewed as including a plurality of second nanowire layers308A, and a plurality of second sacrificial nanowire release layers306A interleaved with the plurality of second nanowire layers308A. Each nanowire-forming stack312or313can also include a dielectric cap310A thereon, as is depicted. In an embodiment, nanowire-forming stacks312are for fabricating NMOS devices, and nanowire-forming stacks313are for fabricating PMOS devices. As explained in greater detail in other embodiments described herein, channel regions of the plurality of nanowire-forming stacks312or313may then be exposed, e.g., during a replacement gate process, prior to performing the subsequent nanowire release process described below.FIGS.3C-3Iare taken through such a channel region. Referring toFIG.3C, an isolation structure314, such as a shallow trench isolation (STI) structure is formed adjacent to the sub-fin structures303. The patterned sacrificial base layers304A are removed from nanowire-forming stacks312or313to form corresponding partially released nanowire-forming stacks316or317, respectively. In one embodiment, the upper portions of the plurality of nanowire-forming stacks312or313are protected, e.g., by a helmet protecting layer, while sacrificial base layers304A are exposed for release. Referring toFIG.3D, the nanowire-forming stacks313are masked, e.g., by a lithographically patterned hardmask320. The nanowire-forming stacks312are exposed. Referring toFIG.3E, the plurality of first sacrificial nanowire release layers308A is removed from the partially released nanowire-forming stacks316to form nanowire stacks316A. Each nanowire stack316A includes released nanowires306B and, if included, an overlying released dielectric cap310B, as is depicted. Referring toFIG.3F, the lithographically patterned hardmask320is removed. The nanowire stacks316A are masked, e.g., by a lithographically patterned hardmask322. The partially released nanowire-forming stacks317are exposed. Referring toFIG.3G, the plurality of second sacrificial nanowire release layers306A is removed from the partially released nanowire-forming stacks317to form nanowire stacks317A. Each nanowire stack317A includes released nanowires308B and, if included, an overlying released dielectric cap. However, in some embodiments, the dielectric cap of each nanowire stack317A is removed, as is depicted, to enable access of a gate structure to the top surface of the top nanowire of the released nanowires308B. Referring toFIG.3H, the lithographically patterned hardmask322is removed to reveal nanowire stacks316A and nanowire stacks317A. In an embodiment, individual ones of the released nanowires308B of each nanowire stack317A are thinner (vertical direction) than the individual ones of the released nanowires306B of each nanowire stack316A, as is depicted. In another embodiment, individual ones of the released nanowires308B of each nanowire stack317A are thicker (vertical direction) than the individual ones of the released nanowires306B of each nanowire stack316A. In another embodiment, individual ones of the released nanowires308B of each nanowire stack317A are the same thickness (vertical direction) as the individual ones of the released nanowires306B of each nanowire stack316A. Referring toFIG.3I, the nanowire stacks316A and317B ofFIG.3Iare subjected to further processing, such as gate stack and gate spacer fabrication, and epitaxial source or drain region fabrication. In particular, with reference to a single structure in the NMOS region, a gate stack including a gate electrode330and a gate dielectric332is formed over and surrounding the released dielectric cap310B and the nanowires306B of one of the nanowire stacks316A. Gate spacers334are also formed. Epitaxial source of drain structures336are formed on sides of the gate stack. The epitaxial source of drain structures336can be partially recessed into the isolation structure314, as is depicted. With reference to a single structure in the PMOS region, a gate stack including a gate electrode340and a gate dielectric342is formed over and surrounding the nanowires308B of one of the nanowire stacks317A. Gate spacers344are also formed. Epitaxial source of drain structures346are formed on sides of the gate stack. The epitaxial source of drain structures346can be partially recessed into the isolation structure314, as is depicted. In accordance with an embodiment of the present disclosure, with reference again toFIG.3I, an integrated circuit structure includes a first vertical arrangement of nanowires306B above a substrate302A. A dielectric cap310B is over the first vertical arrangement of nanowires306B. A second vertical arrangement of nanowires308B is above the substrate302A. Individual ones of the second vertical arrangement of nanowires308B are laterally staggered with individual ones of the first vertical arrangement of nanowires306B and the dielectric cap310B. In an embodiment, there is a dielectric cap310B over the first vertical arrangement of nanowires306B but there is no dielectric cap over the second vertical arrangement of nanowires308B, as is depicted. In an embodiment, a bottommost nanowire of the first vertical arrangement of nanowires306B is below a bottommost nanowire of the second vertical arrangement of nanowires308B, as is depicted. In an embodiment, an uppermost nanowire of the first vertical arrangement of nanowires306B is below an uppermost nanowire of the second vertical arrangement of nanowires308B, as is depicted. In an embodiment, the dielectric cap310B is above an uppermost nanowire of the second vertical arrangement of nanowires308B. In an embodiment, the first vertical arrangement of nanowires306B is composed of a different semiconductor material than the second vertical arrangement of nanowires308B. In one such embodiment, the first vertical arrangement of nanowires is composed of silicon, and the second vertical arrangement of nanowires is composed of silicon germanium. In an embodiment, the first vertical arrangement of nanowires306B has a same number of nanowires as the second vertical arrangement of nanowires308B, as is depicted. In another embodiment, the first vertical arrangement of nanowires306B has a different number of nanowires than the second vertical arrangement of nanowires308B, exemplary structures for which are described in greater detail below. In an embodiment, a first gate stack330/332is over the first vertical arrangement of nanowires306B and the dielectric cap310B, and a second gate stack340/342is over the second vertical arrangement of nanowires308B. In an embodiment, first epitaxial source or drain structures336are at ends of the first vertical arrangement of nanowires306B, and second epitaxial source or drain structures346are at ends of the second vertical arrangement of nanowires308B. In one such embodiment, the first336and second346epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures, as is depicted. In another such embodiment, the first336and second346epitaxial source or drain structures are discrete first and second epitaxial source or drain structures, exemplary structures for which are described in greater detail below. In an embodiment, the first vertical arrangement of nanowires306B is over a first sub-fin303, and the second vertical arrangement of nanowires308B is over a second sub-fin303, as is depicted. It is to be appreciated that, in a particular embodiment, channel layers (or corresponding release layers) of a first plurality of nanowires (or nanoribbons) may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material composed of a very substantial amount of, if not all, silicon. However, it is to be appreciated that, practically, 100% pure Si may be difficult to form and, hence, could include a tiny percentage of carbon, germanium or tin. Such impurities may be included as an unavoidable impurity or component during deposition of Si or may “contaminate” the Si upon diffusion during post deposition processing. As such, embodiments described herein directed to a silicon layer may include a silicon layer that contains a relatively small amount, e.g., “impurity” level, non-Si atoms or species, such as Ge, C or Sn. It is to be appreciated that a silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic. It is to be appreciated that, in a particular embodiment, channel layers (or corresponding release layers) of a first plurality of nanowires (or nanoribbons) may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of substantial portions of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In particular embodiments, a silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si40Ge60). In other embodiments, the amount of silicon is greater than the amount of germanium. In particular embodiments, a silicon germanium layer includes approximately 30% germanium and approximately 70% silicon (Si70Ge30). It is to be appreciated that, practically, 100% pure silicon germanium (referred to generally as SiGe) may be difficult to form and, hence, could include a tiny percentage of carbon or tin. Such impurities may be included as an unavoidable impurity or component during deposition of SiGe or may “contaminate” the SiGe upon diffusion during post deposition processing. As such, embodiments described herein directed to a silicon germanium layer may include a silicon germanium layer that contains a relatively small amount, e.g., “impurity” level, non-Ge and non-Si atoms or species, such as carbon or tin. It is to be appreciated that a silicon germanium layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic. It is to be appreciated that although some embodiments describe the use of Si or SiGe (wire or ribbon) and complementary Si or SiGe (sacrificial) layers, other pairs of semiconductor materials which can be alloyed and grown epitaxially could be implemented to achieve various embodiments herein, for example, InAs and InGaAs. In another aspect, one or more embodiments described herein are directed to nanoribbon transistor channel depopulation and/or nanowire transistor channel depopulation. Embodiments described herein allow for tunable drive current capability for thick gate devices by selectively removing one or more nanoribbons from either a top or bottom of the stack in order to modify the total channel area available for conduction or drive strength. Implementation of embodiments described herein enable the ability to remove nanoribbons from the middle, bottom or top of the stack and modify/tune the drive current of the transistor. Approaches described herein can enable the drive current of a device to be fine-tuned by selectively removing one or more nanoribbons. Cross-sectional SEM/TEM imaging can reveal areas having a combination of full and etched nanoribbon stacks, in accordance with embodiments described herein. To provide further context, integration of nanowire and/or nanoribbon complementary metal oxide semiconductor (CMOS) transistors is faced with the challenge of creating devices with different strengths. In the current FinFET technology, device strength granularity is achieved by varying the number of fins in the device channel. This option is unfortunately not easily available for nanowire and nanoribbon architectures since the channels are vertically stacked. Furthermore, transistors with different drive currents may be needed for different circuit types. Embodiments disclosed herein are directed to achieving different drive currents by de-populating the number of nanowire transistor channels in device structures. One or more embodiments provide an approach for deleting discrete numbers of wires from a transistor structure. Approaches may be suitable for both ribbons and wires (RAW). As mentioned above, in one aspect, nanowire release processing may be performed through a replacement gate trench. Examples of such release processes are described below. Additionally, in another aspect, backend (BE) interconnect scaling can result in lower performance and higher manufacturing cost due to patterning complexity. Embodiments described herein may be implemented to enable front and back-side interconnect integration for nanowire transistors. Embodiments described herein may provide an approach to achieve a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance. One or more embodiments described herein are directed dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire/nanoribbon transistors which are partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain side enables direct contact to a back-side interconnect level. In an exemplary process flow,FIGS.4A-4Jillustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure. Referring toFIG.4A, a method of fabricating an integrated circuit structure includes forming a starting stack400which includes alternating silicon germanium layer404and silicon layers406above a fin402, such as a silicon fin. The silicon layers406may be referred to as a vertical arrangement of silicon nanowires. A protective cap408may be formed above the alternating silicon germanium layer404and silicon layers406, as is depicted. Referring toFIG.4B, a gate stack410is formed over the vertical arrangement of nanowires406. Portions of the vertical arrangement of nanowires406are then released by removing portions of the silicon germanium layer404to provide recessed silicon germanium layers404′ and cavities412, as is depicted inFIG.4C. It is to be appreciated that the structure ofFIG.4Cmay be fabricated to completion without first performing the deep etch and asymmetric contact processing described below in association withFIG.4D. In other embodiments, the processing of silicon and silicon and germanium can be reversed, as described in association withFIGS.2and3A-3I. In either case (e.g., with or without asymmetric contact processing), in an embodiment, a fabrication process involves use of a process scheme that provides a gate-all-around integrated circuit structure having a depopulated channel structure. Referring toFIG.4D, upper gate spacers414are formed at sidewalls of the gate structure410. Cavity spacers416are formed in the cavities412beneath the upper gate spacers414. A deep trench contact etch is then performed to form trenches418and to formed recessed nanowires406′. A sacrificial material420is then formed in the trenches418, as is depicted inFIG.4E. Referring toFIG.4F, a first epitaxial source or drain structure (e.g., left-hand features422) is formed at a first end of the vertical arrangement of nanowires406′. A second epitaxial source or drain structure (e.g., right-hand features422) is formed at a second end of the vertical arrangement of nanowires406′. An inter-layer dielectric (ILD) material424is then formed at the sides of the gate electrode410and adjacent to the source or drain structures422, as is depicted inFIG.4G. Referring toFIG.4H, a replacement gate process is used to form a permanent gate dielectric428and a permanent gate electrode426. In an embodiment, subsequent to removal of gate structure410and form a permanent gate dielectric428and a permanent gate electrode426, the recessed silicon germanium layers404′ are removed to leave upper active nanowires or nanoribbons406′. In an embodiment, the recessed silicon germanium layers404′ are removed selectively with a wet etch that selectively removes the silicon germanium while not etching the silicon layers. Etch chemistries such as carboxylic acid/nitric acid/HF chemistry, and citric acid/nitric acid/HF, for example, may be utilized to selectively etch the silicon germanium. Halide-based dry etches or plasma-enhanced vapor etches may also be used to achieve the embodiments herein. Referring again toFIG.4H, one or more of the bottommost nanowires or nanoribbons406′ is then removed for depopulation such as at location499. Also, or alternatively, one or more of the uppermost nanowires or nanoribbons406′ is then removed for depopulation. The permanent gate dielectric428and a permanent gate electrode426is then formed to surround the remaining nanowires or nanoribbons406′. Referring toFIG.4I, the ILD material424is then removed. The sacrificial material420is then removed from one of the source drain locations (e.g., right-hand side) to form trench432, but is not removed from the other of the source drain locations to form trench430. Referring toFIG.4J, a first conductive contact structure434is formed coupled to the first epitaxial source or drain structure (e.g., left-hand features422). A second conductive contact structure436is formed coupled to the second epitaxial source or drain structure (e.g., right-hand features422). The second conductive contact structure436is formed deeper along the fin402than the first conductive contact structure434. In an embodiment, although not depicted inFIG.4J, the method further includes forming an exposed surface of the second conductive contact structure436at a bottom of the fin402. In an embodiment, the second conductive contact structure436is deeper along the fin402than the first conductive contact structure434, as is depicted. In one such embodiment, the first conductive contact structure434is not along the fin402, as is depicted. In another such embodiment, not depicted, the first conductive contact structure434is partially along the fin402. In an embodiment, the second conductive contact structure436is along an entirety of the fin402. In an embodiment, although not depicted, in the case that the bottom of the fin402is exposed by a back-side substrate removal process, the second conductive contact structure436has an exposed surface at a bottom of the fin402. In another aspect, in order to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, integrated circuit structures described herein may be fabricated using a back-side reveal of front-side structures fabrication approach. In some exemplary embodiments, reveal of the back-side of a transistor or other device structure entails wafer-level back-side processing. In contrast to a conventional through-Silicon via TSV-type technology, a reveal of the back-side of a transistor as described herein may be performed at the density of the device cells, and even within sub-regions of a device. Furthermore, such a reveal of the back-side of a transistor may be performed to remove substantially all of a donor substrate upon which a device layer was disposed during front-side device processing. As such, a microns-deep TSV becomes unnecessary with the thickness of semiconductor in the device cells following a reveal of the back-side of a transistor potentially being only tens or hundreds of nanometers. Reveal techniques described herein may enable a paradigm shift from “bottom-up” device fabrication to “center-out” fabrication, where the “center” is any layer that is employed in front-side fabrication, revealed from the back-side, and again employed in back-side fabrication. Processing of both a front-side and revealed back-side of a device structure may address many of the challenges associated with fabricating 3D ICs when primarily relying on front-side processing. A reveal of the back-side of a transistor approach may be employed for example to remove at least a portion of a carrier layer and intervening layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a carrier layer in the donor-host substrate is polished (e.g., CMP) and/or etched with a wet or dry (e.g., plasma) etch process. Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the carrier layer may be employed. For example, where the carrier layer is a group IV semiconductor (e.g., silicon) a CMP slurry known to be suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed. In some embodiments, the above is preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intervening layer. The cleaving or fracture process may be utilized to remove a substantial portion of the carrier layer as a bulk mass, reducing the polish or etch time needed to remove the carrier layer. For example, where a carrier layer is 400-900 μm in thickness, 100-700 μm may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly may then be polished or etched to complete removal. Alternatively, where the carrier layer is not fractured, the grind, polish and/or etch operation may be employed to remove a greater thickness of the carrier layer. Next, exposure of an intervening layer is detected. Detection is used to identify a point when the back-side surface of the donor substrate has advanced to nearly the device layer. Any endpoint detection technique known to be suitable for detecting a transition between the materials employed for the carrier layer and the intervening layer may be practiced. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorbance or emission of the back-side surface of the donor substrate during the polishing or etching performed. In some other embodiments, the endpoint criteria are associated with a change in optical absorbance or emission of byproducts during the polishing or etching of the donor substrate back-side surface. For example, absorbance or emission wavelengths associated with the carrier layer etch byproducts may change as a function of the different compositions of the carrier layer and intervening layer. In other embodiments, the endpoint criteria are associated with a change in mass of species in byproducts of polishing or etching the back-side surface of the donor substrate. For example, the byproducts of processing may be sampled through a quadrupole mass analyzer and a change in the species mass may be correlated to the different compositions of the carrier layer and intervening layer. In another exemplary embodiment, the endpoint criteria is associated with a change in friction between a back-side surface of the donor substrate and a polishing surface in contact with the back-side surface of the donor substrate. Detection of the intervening layer may be enhanced where the removal process is selective to the carrier layer relative to the intervening layer as non-uniformity in the carrier removal process may be mitigated by an etch rate delta between the carrier layer and intervening layer. Detection may even be skipped if the grind, polish and/or etch operation removes the intervening layer at a rate sufficiently below the rate at which the carrier layer is removed. If an endpoint criteria is not employed, a grind, polish and/or etch operation of a predetermined fixed duration may stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch process. In some examples, the carrier etch rate: intervening layer etch rate is 3:1-10:1, or more. Upon exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be removed uniformly by a polish, for example. Alternatively, a thickness of the intervening layer may be removed with a masked or blanket etch process. The process may employ the same polish or etch process as that employed to thin the carrier, or may be a distinct process with distinct process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polish or etch process that favors removal of the intervening layer over removal of the device layer. Where less than a few hundred nanometers of intervening layer thickness is to be removed, the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled than that employed for removal of the carrier layer. A CHIP process employed may, for example employ a slurry that offers very high selectively (e.g., 100:1-300:1, or more) between semiconductor (e.g., silicon) and dielectric material (e.g., SiO) surrounding the device layer and embedded within the intervening layer, for example, as electrical isolation between adjacent device regions. For embodiments where the device layer is revealed through complete removal of the intervening layer, back-side processing may commence on an exposed back-side of the device layer or specific device regions there in. In some embodiments, the back-side device layer processing includes a further polish or wet/dry etch through a thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region. In some embodiments where the carrier layer, intervening layer, or device layer back-side is recessed with a wet and/or plasma etch, such an etch process may be a patterned etch or a materially selective etch that imparts significant non-planarity or topography into the device layer back-side surface. As described further below, the patterning may be within a device cell (i.e., “intra-cell” patterning) or may be across device cells (i.e., “inter-cell” patterning). In some patterned etch embodiments, at least a partial thickness of the intervening layer is employed as a hard mask for back-side device layer patterning. Hence, a masked etch process may preface a correspondingly masked device layer etch. The above described processing scheme may result in a donor-host substrate assembly that includes IC devices that have a back-side of an intervening layer, a back-side of the device layer, and/or back-side of one or more semiconductor regions within the device layer, and/or front-side metallization revealed. Additional back-side processing of any of these revealed regions may then be performed during downstream processing. It is to be appreciated that the structures resulting from the above exemplary processing schemes may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as CMOS, PMOS and/or NMOS device fabrication. As an example of a completed device,FIG.5illustrate a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. Referring toFIG.5, a semiconductor structure or device500includes a non-planar active region (e.g., a fin structure including protruding fin portion504and sub-fin region505) within a trench isolation region506. In an embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires504A and504B) above sub-fin region505, as is represented by the dashed lines. In either case, for ease of description for non-planar integrated circuit structure500, a non-planar active region504is referenced below as a protruding fin portion. In an embodiment, a fabrication process involves use of a process based on scheme reversal of processing of silicon and silicon and germanium, as described in association withFIGS.2and3A-3I. In an embodiment, a fabrication process involves use of a process scheme that provides active regions504as a depopulated channel structure. For example, in one embodiment, lower nanowires504B are removed. In another embodiment, upper nanowires504A are removed. A gate line508is disposed over the protruding portions504of the non-planar active region (including, if applicable, surrounding nanowires504A and504B), as well as over a portion of the trench isolation region506. As shown, gate line508includes a gate electrode550and a gate dielectric layer552. In one embodiment, gate line508may also include a dielectric cap layer554. A gate contact514, and overlying gate contact via516are also seen from this perspective, along with an overlying metal interconnect560, all of which are disposed in inter-layer dielectric stacks or layers570. Also seen from the perspective ofFIG.5, the gate contact514is, in one embodiment, disposed over trench isolation region506, but not over the non-planar active regions. In an embodiment, the semiconductor structure or device500is a non-planar device such as, but not limited to, a fin-FET device, a tri-gate device, a nano-ribbon device, or a nano-wire device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines508surround at least a top surface and a pair of sidewalls of the three-dimensional body. As is also depicted inFIG.5, in an embodiment, an interface580exists between a protruding fin portion504and sub-fin region505. The interface580can be a transition region between a doped sub-fin region505and a lightly or undoped upper fin portion504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and sub-fin dopants are supplied from an adjacent solid state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide. Although not depicted inFIG.5, it is to be appreciated that source or drain regions of or adjacent to the protruding fin portions504are on either side of the gate line508, i.e., into and out of the page. In one embodiment, the source or drain regions are doped portions of original material of the protruding fin portions504. In another embodiment, the material of the protruding fin portions504is removed and replaced with another semiconductor material, e.g., by epitaxial deposition to form discrete epitaxial nubs or non-discrete epitaxial structures. In either embodiment, the source or drain regions may extend below the height of dielectric layer of trench isolation region506, i.e., into the sub-fin region505. In accordance with an embodiment of the present disclosure, the more heavily doped sub-fin regions, i.e., the doped portions of the fins below interface580, inhibits source to drain leakage through this portion of the bulk semiconductor fins. In an embodiment, the source and drain structures are N-type epitaxial source and drain structures, both including phosphorous dopant impurity atoms. In accordance with one or more embodiments of the present disclosure, the source and drain regions have associated asymmetric source and drain contact structures, as described above in association withFIG.4J. With reference again toFIG.5, in an embodiment, fins504/505(and, possibly nanowires504A and504B) are composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof. In one embodiment, the concentration of silicon atoms is greater than 97%. In another embodiment, fins504/505are composed of a group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. Trench isolation region506may be composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Gate line508may be composed of a gate electrode stack which includes a gate dielectric layer552and a gate electrode layer550. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer552is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer552may include a layer of native oxide formed from the top few layers of the protruding fin portions504. In an embodiment, the gate dielectric layer552is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer552is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In one embodiment, the gate electrode layer550is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode layer550is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer550may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer550may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Gate contact514and overlying gate contact via516may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). In an embodiment (although not shown), a contact pattern which is essentially perfectly aligned to an existing gate pattern508is formed while eliminating the use of a lithographic step with exceedingly tight registration budget. In an embodiment, the contact pattern is a vertically asymmetric contact pattern, such as described in association withFIG.4J. In other embodiments, all contacts are front-side connected and are not asymmetric. In one such embodiment, the self-aligned approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts. In an embodiment, providing structure500involves fabrication of the gate stack structure508by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid. Referring again toFIG.5, the arrangement of semiconductor structure or device500places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region, e.g., over a sub-fin505, and in a same layer as a trench contact via. It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a gate-all-around (GAA) device, a tri-gate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a sub-10 nanometer (10 nm) technology node. In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods. In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect. In an embodiment, as is also used throughout the present description, hardmask materials, capping layers, or plugs are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer, capping or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hardmask, capping or plug layers known in the arts may be used depending upon the particular implementation. The hardmask, capping or plug layers maybe formed by CVD, PVD, or by other deposition methods. In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion litho (i193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer. In another aspect, one or more embodiments are directed to neighboring semiconductor structures or devices separated by gate endcap structures. Particular embodiments may be directed to integration of multiple width (multi-Wsi) nanowires and nanoribbons in a gate end cap architecture and separated by a gate end cap wall. In an embodiment, nanowires/nanoribbons are integrated with multiple Wsi in a gate endcap architecture portion of a front end process flow. Such a process flow may involve integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., portions of nanowires removed and then source or drain (S/D) growth is performed) or formed by vertical merging (e.g., epitaxial regions are formed around existing wires), as described in greater detail below in association withFIGS.9A-9E. To provide further context, advantages of a gate endcap architecture may include the enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing. To provide illustrative comparison,FIG.6illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a gate endcap architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. Referring to the left-hand side (a) ofFIG.6, an integrated circuit structure600includes a substrate602having sub-fins604protruding therefrom within an isolation structure608laterally surrounding the sub-fins604. Corresponding nanowires649and605are over the sub-fins604. In one embodiment, lower nanowires649are removed. In another embodiment, upper nanowires605are removed. A gate structure may be formed over the integrated circuit structure600to fabricate a device. However, breaks in such a gate structure may be accommodated for by increasing the spacing between sub-fin604/nanowire649/605pairings. By contrast, referring to the right-hand side (b) ofFIG.6, an integrated circuit structure650includes a substrate652having sub-fins654protruding therefrom within an isolation structure658laterally surrounding the sub-fins654. Corresponding nanowires699and655are over the sub-fins654. In one embodiment, lower nanowires699are removed. In another embodiment, upper nanowires655are removed. Isolating gate endcap walls660are included within the isolation structure658and between adjacent sub-fin654/nanowire699/655pairings. The distance between an isolating gate endcap wall660and a nearest sub-fin654/nanowire699/655pairings defines the gate endcap spacing662. A gate structure may be formed over the integrated circuit structure650, between insolating gate endcap walls to fabricate a device. Breaks in such a gate structure are imposed by the isolating gate endcap walls. Since the isolating gate endcap walls660are self-aligned, restrictions from conventional approaches can be minimized to enable more aggressive diffusion to diffusion spacing. Furthermore, since gate structures include breaks at all locations, individual gate structure portions may be layer connected by local interconnects formed over the isolating gate endcap walls660. In an embodiment, as depicted, the gate endcap walls660each include a lower dielectric portion and a dielectric cap on the lower dielectric portion, as is depicted. In accordance with an embodiment of the present disclosure, a fabrication process for structures associated withFIG.6involves use of a process scheme based on reversal of processing of silicon and silicon and germanium, as described in association withFIGS.2and3A-3I. In an embodiment, a fabrication process involves use of a process scheme that provides a depopulated channel structure. A gate endcap processing scheme involves the formation of gate/trench contact endcaps self-aligned to fins without requiring an extra length to account for mask mis-registration. Thus, embodiments may be implemented to enable shrinking of transistor layout area. Embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls or gate endcap walls. In an exemplary processing scheme for structures having gate endcap walls separating neighboring devices,FIG.7illustrates cross-sectional views representing various operations in a method of fabricating a gate endcap structure with gate-all-around devices, in accordance with an embodiment of the present disclosure. Referring to part (a) ofFIG.7, a starting structure includes a nanowire patterning stack704above a substrate702. A lithographic patterning stack706is formed above the nanowire patterning stack704. The nanowire patterning stack704includes alternating silicon germanium layers710and silicon layers712. A protective mask714is between the nanowire patterning stack704and the lithographic patterning stack706. In one embodiment, the lithographic patterning stack706is trilayer mask composed of a topographic masking portion720, an anti-reflective coating (ARC) layer722, and a photoresist layer724. In a particular such embodiment, the topographic masking portion720is a carbon hardmask (CHM) layer and the anti-reflective coating layer722is a silicon ARC layer. Referring to part (b) ofFIG.7, the stack of part (a) is lithographically patterned and then etched to provide an etched structure including a patterned substrate702and trenches730. Referring to part (c) ofFIG.7, the structure of part (b) has an isolation layer740and a gate endcap material742formed in trenches730. The structure is then planarized to leave patterned topographic masking layer720′ as an exposed upper layer. Referring to part (d) ofFIG.7, the isolation layer740is recessed below an upper surface of the patterned substrate702, e.g., to define a protruding fin portion and to provide a trench isolation structure741beneath gate endcap walls742. Referring to part (e) ofFIG.7, the silicon germanium layers710are removed at least in the channel region to release silicon nanowires712A and712B. In accordance with an embodiment of the present disclosure, a fabrication process for structures associated withFIG.7involves use of a process scheme based on reversal of processing of silicon and silicon and germanium, as described in association withFIGS.2and3A-3I. In an embodiment, a fabrication process involves use of a process scheme that provides a depopulated channel structure. For example, referring to part (e) ofFIG.7, in an embodiment, nanowire712B and nanoribbon712A are removed. In another such embodiment, nanowire712B and nanoribbon799A are removed. In another such embodiment, nanowire799B and nanoribbon799A are removed. Subsequent to the formation of the structure of part (e) ofFIG.7, one or more gate stacks may be formed around the active nanowires and/or nanoribbons, over protruding fins of substrate702, and between gate endcap walls742. In one embodiment, prior to formation of the gate stacks, the remaining portion of protective mask714is removed. In another embodiment, the remaining portion of protective mask714is retained as an insulating fin hat as an artifact of the processing scheme. Referring again to part (e) ofFIG.7, it is to be appreciated that a channel view is depicted, with source or drain regions being locating into and out of the page. In an embodiment, the channel region including nanowires712B has a width less than the channel region including nanowires712A. Thus, in an embodiment, an integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although structures of712B and712A may be differentiated as nanowires and nanoribbons, respectively, both such structures are typically referred to herein as nanowires. It is also to be appreciated that reference to or depiction of a fin/nanowire pair throughout may refer to a structure including a fin and one or more overlying nanowires (e.g., two overlying nanowires are shown inFIG.7). To highlight an exemplary integrated circuit structure having three vertically arranged nanowires,FIG.8Aillustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.FIG.8Billustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure ofFIG.8A, as taken along the a-a′ axis.FIG.8Cillustrates a cross-sectional channel view of the nanowire-based integrated circuit structure ofFIG.8A, as taken along the b-b′ axis. Referring toFIG.8A, an integrated circuit structure800includes one or more vertically stacked nanowires (804set) above a substrate802. An optional fin between the bottommost nanowire and the substrate802is not depicted for the sake of emphasizing the nanowire portion for illustrative purposes. Embodiments herein are targeted at both single wire devices and multiple wire devices. As an example, a three nanowire-based devices having nanowires804A,804B and804C is shown for illustrative purposes. For convenience of description, nanowire804A is used as an example where description is focused on one of the nanowires. It is to be appreciated that where attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or essentially the same attributes for each of the nanowires. Each of the nanowires804includes a channel region806in the nanowire. The channel region806has a length (L). Referring toFIG.8C, the channel region also has a perimeter (Pc) orthogonal to the length (L). Referring to bothFIGS.8A and8C, a gate electrode stack808surrounds the entire perimeter (Pc) of each of the channel regions806. The gate electrode stack808includes a gate electrode along with a gate dielectric layer between the channel region806and the gate electrode (not shown). In an embodiment, the channel region806is discrete in that it is completely surrounded by the gate electrode stack808without any intervening material such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments having a plurality of nanowires804, the channel regions806of the nanowires are also discrete relative to one another. In accordance with an embodiment of the present disclosure, a fabrication process for structures associated withFIGS.8A-8Cinvolves use of a process scheme based on reversal of processing of silicon and silicon and germanium, as described in association withFIGS.2and3A-3I. In an embodiment, a fabrication process involves use of a process scheme that provides a depopulated channel structure. For example, in one embodiment, nanowire804A is removed. In another embodiment, both nanowire804A and nanowire804B are removed. In one embodiment, nanowire804C is removed. In another embodiment, both nanowire804C and nanowire804B are removed. Referring to bothFIGS.8A and8B, integrated circuit structure800includes a pair of non-discrete source or drain regions810/812. The pair of non-discrete source or drain regions810/812is on either side of the channel regions806of the plurality of vertically stacked nanowires804. Furthermore, the pair of non-discrete source or drain regions810/812is adjoining for the channel regions806of the plurality of vertically stacked nanowires804. In one such embodiment, not depicted, the pair of non-discrete source or drain regions810/812is directly vertically adjoining for the channel regions806in that epitaxial growth is on and between nanowire portions extending beyond the channel regions806, where nanowire ends are shown within the source or drain structures. In another embodiment, as depicted inFIG.8A, the pair of non-discrete source or drain regions810/812is indirectly vertically adjoining for the channel regions806in that they are formed at the ends of the nanowires and not between the nanowires. In an embodiment, as depicted, the source or drain regions810/812are non-discrete in that there are not individual and discrete source or drain regions for each channel region806of a nanowire804. Accordingly, in embodiments having a plurality of nanowires804, the source or drain regions810/812of the nanowires are global or unified source or drain regions as opposed to discrete for each nanowire. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions806, each of the pair of non-discrete source or drain regions810/812is approximately rectangular in shape with a bottom tapered portion and a top vertex portion, as depicted inFIG.8B. In other embodiments, however, the source or drain regions810/812of the nanowires are relatively larger yet discrete non-vertically merged epitaxial structures such as nubs described in association withFIGS.4F-4J. In accordance with an embodiment of the present disclosure, and as depicted inFIGS.8A and8B, integrated circuit structure800further includes a pair of contacts814, each contact814on one of the pair of non-discrete source or drain regions810/812. In one such embodiment, in a vertical sense, each contact814completely surrounds the respective non-discrete source or drain region810/812. In another aspect, the entire perimeter of the non-discrete source or drain regions810/812may not be accessible for contact with contacts814, and the contacts814thus only partially surrounds the non-discrete source or drain regions810/812, as depicted inFIG.8B. In a contrasting embodiment, not depicted, the entire perimeter of the non-discrete source or drain regions810/812, as taken along the a-a′ axis, is surrounded by the contacts814. In accordance with an embodiment of the present disclosure, although not depicted, the pair of contacts814is an asymmetric pair of contacts, as described in association withFIG.4J. Referring toFIGS.8B and8C, the non-discrete source or drain regions810/812are global in the sense that a single unified feature is used as a source or drain region for a plurality (in this case, 3) of nanowires804and, more particularly, for more than one discrete channel region806. In an embodiment, the pair of non-discrete source or drain regions810/812is composed of a semiconductor material different than the semiconductor material of the discrete channel regions806, e.g., the pair of non-discrete source or drain regions810/812is composed of a silicon germanium while the discrete channel regions806are composed of silicon. In another embodiment, the pair of non-discrete source or drain regions810/812is composed of a semiconductor material the same or essentially the same as the semiconductor material of the discrete channel regions806, e.g., both the pair of non-discrete source or drain regions810/812and the discrete channel regions806are composed of silicon. Referring again toFIG.8A, in an embodiment, integrated circuit structure800further includes a pair of spacers816. As is depicted, outer portions of the pair of spacers816may overlap portions of the non-discrete source or drain regions810/812, providing for “embedded” portions of the non-discrete source or drain regions810/812beneath the pair of spacers816. As is also depicted, the embedded portions of the non-discrete source or drain regions810/812may not extend beneath the entirety of the pair of spacers816. Substrate802may be composed of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate802includes a lower bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a group III-V compound semiconductor material. An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride is on the lower bulk substrate. Thus, the structure800may be fabricated from a starting semiconductor-on-insulator substrate. Alternatively, the structure800is formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer. In another alternative embodiment, the structure800is formed directly from a bulk substrate and doping is used to form electrically isolated active regions, such as nanowires, thereon. In one such embodiment, the first nanowire (i.e., proximate the substrate) is in the form of an omega-FET type structure. In an embodiment, the nanowires804may be sized as wires or ribbons, as described below, and may have squared-off or rounder corners. In an embodiment, the nanowires804are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires804are single-crystalline. For example, for a silicon nanowire804, a single-crystalline nanowire may be based from a (100) global orientation, e.g., with a <100> plane in the z-direction. As described below, other orientations may also be considered. In an embodiment, the dimensions of the nanowires804, from a cross-sectional perspective, are on the nano-scale. For example, in a specific embodiment, the smallest dimension of the nanowires804is less than approximately 20 nanometers. In an embodiment, the nanowires804are composed of a strained material, particularly in the channel regions806. Referring toFIG.8C, in an embodiment, each of the channel regions806has a width (Wc) and a height (Hc), the width (Wc) approximately the same as the height (Hc). That is, in both cases, the channel regions806are square-like or, if corner-rounded, circle-like in cross-section profile. In another aspect, the width and height of the channel region need not be the same, such as the case for nanoribbbons as described throughout. In another aspect, methods of fabricating a nanowire portion of a fin/nanowire integrated circuit structure are provided. For example,FIGS.9A-9Eillustrate three-dimensional cross-sectional views representing various operations in a method of fabricating a nanowire portion of a fin/nanowire structure, in accordance with an embodiment of the present disclosure. A method of fabricating a nanowire integrated circuit structure may include forming a nanowire above a substrate. In a specific example showing the formation of two silicon nanowires,FIG.9Aillustrates a substrate902(e.g., composed of a bulk substrate silicon substrate902A with an insulating silicon dioxide layer902B there on) having a silicon layer904/silicon germanium layer906/silicon layer908stack thereon. It is to be understood that, in another embodiment, a silicon germanium layer/silicon layer/silicon germanium layer stack may be used to ultimately form two silicon germanium nanowires. Referring toFIG.9B, a portion of the silicon layer904/silicon germanium layer906/silicon layer908stack as well as a top portion of the silicon dioxide layer902B is patterned into a fin-type structure910, e.g., with a mask and plasma etch process. It is to be appreciated that, for illustrative purposes, the etch forFIG.9Bis shown as forming two silicon nanowire precursor portions. Although the etch is shown for ease of illustration as ending within a bottom isolation layer, more complex stacks are contemplated within the context of embodiments of the present disclosure. For example, the process may be applied to a nanowire/fin stack as described in association withFIG.7. The method may also include forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length. In a specific example showing the formation of three gate structures over the two silicon nanowires,FIG.9Cillustrates the fin-type structure910with three sacrificial gates912A,912B, and912C thereon. In one such embodiment, the three sacrificial gates912A,912B, and912C are composed of a sacrificial gate oxide layer914and a sacrificial polysilicon gate layer916which are blanket deposited and patterned with a plasma etch process. Following patterning to form the three sacrificial gates912A,912B, and912C, spacers may be formed on the sidewalls of the three sacrificial gates912A,912B, and912C, doping may be performed (e.g., tip and/or source and drain type doping), and an interlayer dielectric layer may be formed to cover the three sacrificial gates912A,912B, and912C. The interlayer dielectric layer may be polished to expose the three sacrificial gates912A,912B, and912C for a replacement gate, or gate-last, process. Referring toFIG.9D, the three sacrificial gates912A,912B, and912C are removed, leaving spacers918and a portion of the interlayer dielectric layer920remaining. Additionally, the portions of the silicon germanium layer906and the portion of the insulating silicon dioxide layer902B of the fin structure910are removed in the regions originally covered by the three sacrificial gates912A,912B, and912C. Discrete portions of the silicon layers904and908thus remain, as depicted inFIG.9D. The discrete portions of the silicon layers904and908shown inFIG.9Dwill, in one embodiment, ultimately become channel regions in a nanowire-based device. Thus, at the process stage depicted inFIG.9D, channel engineering or tuning may be performed. For example, in one embodiment, the discrete portions of the silicon layers904and908shown inFIG.9Dare thinned using oxidation and etch processes. Such an etch process may be performed at the same time the wires are separated by etching the silicon germanium layer906. Accordingly, the initial wires formed from silicon layers904and908begin thicker and are thinned to a size suitable for a channel region in a nanowire device, independent from the sizing of the source and drain regions of the device. Thus, in an embodiment, forming the channel region includes removing a portion of the nanowire, and the resulting perimeters of the source and drain regions (described below) are greater than the perimeter of the resulting channel region. In accordance with an embodiment of the present disclosure, following removal of the three sacrificial gates912A,912B, and912C and removal of the portions of the silicon germanium layer906and the portion of the insulating silicon dioxide layer902B of the fin structure910from the regions originally covered by the three sacrificial gates912A,912B, and912C, a fabrication process is performed that provides a gate-all-around integrated circuit structure based on reversal of processing of silicon and silicon and germanium, as described in association withFIGS.2and3A-3I. In an embodiment, a fabrication process involves use of a process scheme that provides a depopulated channel structure. The method may also include forming a gate electrode stack surrounding the entire perimeter of the channel region. In the specific example showing the formation of three gate structures over the two silicon nanowires,FIG.9Eillustrates the structure following deposition of a gate dielectric layer922(such as a high-k gate dielectric layer) and a gate electrode layer924(such as a metal gate electrode layer), and subsequent polishing, in between the spacers918. That is, gate structures are formed in the trenches921ofFIG.9D. Additionally,FIG.9Edepicts the result of the subsequent removal of the interlayer dielectric layer920after formation of the permanent gate stack. The portions of the silicon germanium layer906and the portion of the insulating silicon dioxide layer902B of the fin structure910are also removed in the regions originally covered by the portion of the interlayer dielectric layer920depicted inFIG.9D. Discrete portions of the silicon layers904and908thus remain, as depicted inFIG.9E. The method may also include forming a pair of source and drain regions in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region. Specifically, the discrete portions of the silicon layers904and908shown inFIG.9Ewill, in one embodiment, ultimately become at least a portion of the source and drain regions in a nanowire-based device. In one such embodiment, epitaxial source or drain structures are formed by merging epitaxial material around existing nanowires904and908. In another embodiment, epitaxial source or drain structures are embedded, e.g., portions of nanowires904and908are removed and then source or drain (S/D) growth is performed. In the latter case, in accordance with an embodiment of the present disclosure, such epitaxial source or drain structures may be non-discrete, as exemplified in association withFIGS.8A and8B, or may be discrete, as exemplified in association withFIG.4J. In either case, in one embodiment, source or drain structures are N-type epitaxial source or drain structures, both including phosphorous dopant impurity atoms. The method may subsequently include forming a pair of contacts, a first of the pair of contacts completely or nearly completely surrounding the perimeter of the source region, and a second of the pair of contacts completely or nearly completely surrounding the perimeter of the drain region. In an embodiment, the pair of contacts is an asymmetric pair of source and drain contact structures, such as described in association withFIG.4J. In other embodiments, the pair of contacts is a symmetric pair of source and drain contact structures. Specifically, contacts are formed in the trenches925ofFIG.9Efollowing epitaxial growth. One of the trenches may first be recessed further than the other of the trenches. In an embodiment, the contacts are formed from a metallic species. In one such embodiment, the metallic species is formed by conformally depositing a contact metal and then filling any remaining trench volume. The conformal aspect of the deposition may be performed by using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow. In an embodiment, as described throughout, an integrated circuit structure includes non-planar devices such as, but not limited to, a finFET or a tri-gate device with corresponding one or more overlying nanowire structures. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, the gate structures surround at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions. In an embodiment, as described throughout, a substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. A bulk substrate may alternatively be composed of a group III-V material. In an embodiment, a bulk substrate is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is composed of a group III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. In an embodiment, as described throughout, a trench isolation layer may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, a trench isolation layer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In an embodiment, as described throughout, gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another. Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide. Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein. FIG.10illustrates a computing device1000in accordance with one implementation of an embodiment of the present disclosure. The computing device1000houses a board1002. The board1002may include a number of components, including but not limited to a processor1004and at least one communication chip1006. The processor1004is physically and electrically coupled to the board1002. In some implementations the at least one communication chip1006is also physically and electrically coupled to the board1002. In further implementations, the communication chip1006is part of the processor1004. Depending on its applications, computing device1000may include other components that may or may not be physically and electrically coupled to the board1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The communication chip1006enables wireless communications for the transfer of data to and from the computing device1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip1006may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device1000may include a plurality of communication chips1006. For instance, a first communication chip1006may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip1006may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor1004of the computing device1000includes an integrated circuit die packaged within the processor1004. The integrated circuit die of the processor1004may include one or more structures, such as gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures built in accordance with implementations of embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip1006also includes an integrated circuit die packaged within the communication chip1006. The integrated circuit die of the communication chip1006may include one or more structures, such as gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures built in accordance with implementations of embodiments of the present disclosure. In further implementations, another component housed within the computing device1000may contain an integrated circuit die that includes one or structures, such as gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures built in accordance with implementations of embodiments of the present disclosure. In various implementations, the computing device1000may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device1000may be any other electronic device that processes data. FIG.11illustrates an interposer1100that includes one or more embodiments of the present disclosure. The interposer1100is an intervening substrate used to bridge a first substrate1102to a second substrate1104. The first substrate1102may be, for instance, an integrated circuit die. The second substrate1104may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1100is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1100may couple an integrated circuit die to a ball grid array (BGA)1106that can subsequently be coupled to the second substrate1104. In some embodiments, the first and second substrates1102/1104are attached to opposing sides of the interposer1100. In other embodiments, the first and second substrates1102/1104are attached to the same side of the interposer1100. And in further embodiments, three or more substrates are interconnected by way of the interposer1100. The interposer1100may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer1100may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer1100may include metal interconnects1108and vias1110, including but not limited to through-silicon vias (TSVs)1112. The interposer1100may further include embedded devices1114, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1100. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer1100or in the fabrication of components included in the interposer1100. Thus, embodiments of the present disclosure include gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures. The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. Example embodiment 1: An integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap. Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein a bottommost nanowire of the first vertical arrangement of nanowires is below a bottommost nanowire of the second vertical arrangement of nanowires. Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, wherein an uppermost nanowire of the first vertical arrangement of nanowires is below an uppermost nanowire of the second vertical arrangement of nanowires. Example embodiment 4: The integrated circuit structure of example embodiment 1, 2 or 3, wherein the dielectric cap is above an uppermost nanowire of the second vertical arrangement of nanowires. Example embodiment 5: The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the first vertical arrangement of nanowires includes a different semiconductor material than the second vertical arrangement of nanowires. Example embodiment 6: The integrated circuit structure of example embodiment 5, wherein the first vertical arrangement of nanowires includes silicon, and the second vertical arrangement of nanowires includes silicon germanium. Example embodiment 7: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the first vertical arrangement of nanowires includes a same number of nanowires as the second vertical arrangement of nanowires. Example embodiment 8: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the first vertical arrangement of nanowires includes a different number of nanowires than the second vertical arrangement of nanowires. Example embodiment 9: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7 or 8, further including a first gate stack over the first vertical arrangement of nanowires and the dielectric cap, and a second gate stack over the second vertical arrangement of nanowires. Example embodiment 10: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, further including first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires. Example embodiment 11: The integrated circuit structure of example embodiment 10, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures. Example embodiment 12: The integrated circuit structure of example embodiment 10, wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures. Example embodiment 13: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the first vertical arrangement of nanowires is over a first sub-fin, and the second vertical arrangement of nanowires is over a second sub-fin. Example embodiment 14: An integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A second vertical arrangement of nanowires is above the substrate. The first vertical arrangement of nanowires includes a different semiconductor material than the second vertical arrangement of nanowires. There is a dielectric cap is over the first vertical arrangement of nanowires but there is no dielectric cap over the second vertical arrangement of nanowires. Example embodiment 15: The integrated circuit structure of example embodiment 14, wherein individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap. Example embodiment 16: The integrated circuit structure of example embodiment 14 or 15, further including a first gate stack over the first vertical arrangement of nanowires and the dielectric cap, and a second gate stack over the second vertical arrangement of nanowires. Example embodiment 17: The integrated circuit structure of example embodiment 14, 15 or 16, further including first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires; and second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires. Example embodiment 18: A computing device includes a board, and a component coupled to the board. The component includes an integrated circuit structure including a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap. Example embodiment 19: The computing device of example embodiment 18, further including a memory coupled to the board. Example embodiment 20: The computing device of example embodiment 18 or 19, further including a communication chip coupled to the board. Example embodiment 21: The computing device of example embodiment 18, 19 or 20, further including a camera coupled to the board. Example embodiment 22: The computing device of example embodiment 18, 19, 20 or 21, further including a battery coupled to the board. Example embodiment 23: The computing device of example embodiment 18, 19, 20, 21 or 22, further including an antenna coupled to the board. Example embodiment 24: The computing device of example embodiment 18, 19, 20, 21, 22 or 23, wherein the component is a packaged integrated circuit die. Example embodiment 25: The computing device of example embodiment 18, 19, 20, 21, 22, 23 or 24, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. | 102,503 |
11862704 | DETAILED DESCRIPTION Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. It will be understood that when an element is referred to as being “on” another element, it may be directly on the other element, or an intervening element may also be present. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Throughout the specification, “the” or similar demonstrative expressions may refer to both a singular form and a plural form. Also, unless an order of operations of a method is clearly indicated or contradicted by the context, the operations may be performed in an appropriately variable order and are not limited to the described order. All examples or terms introducing examples are used merely to describe the present disclosure in detail and do not limit the scope of the present disclosure unless defined in the claims. In the following description, an electronic device according to embodiments is a semiconductor-based device and may have a gate stack structure including a ferroelectric and a gate electrode. The electronic device may include, for example, a logic device or a memory device. FIG.1is a cross-sectional view of an electronic device100according to an example embodiment. Referring toFIG.1, the electronic device100includes a substrate110, and a carbon layer130, a ferroelectric layer140, and a gate electrode150sequentially stacked on the substrate110. A channel element115may be provided in the substrate110at a location corresponding to the gate electrode150, and a source (S)121and a drain (D)122may be provided at both sides of the channel element115. The source121may be electrically connected to a side of the channel element115, and the drain122may be electrically connected to the other side of the channel element115. The source121and the drain122may be formed by implanting impurities into different regions of the substrate110, and a region of the substrate110between the source121and the drain122may be defined as the channel element115. The substrate110may be a semiconductor substrate. For example, the substrate110may be a silicon (Si) substrate or may be a substrate including a material other than Si, e.g., germanium (Ge), silicon-germanium (SiGe), or a group III-V semiconductor. In this case, the channel element115may include Si, Ge, SiGe, or the group III-V semiconductor. The material of the substrate110is not limited to the above-mentioned examples and may be variously changed. As will be described below, the channel element115may not be provided as a part of the substrate110and may be provided as a material layer separate from the substrate110. The carbon layer130is provided on an upper surface of the channel element115of the substrate110. The carbon layer130may include carbon having an sp2bonding structure. The carbon layer130having an sp2bonding structure may include nanocrystalline graphene including nano-sized crystals. Herein, nanocrystalline graphene refers to graphene including nano-sized crystals. For example, nanocrystalline graphene may include crystals having a size that is greater than 0 nm and less than or equal to about 100 nm. Normal crystalline graphene, nanocrystalline graphene according to embodiments, and an amorphous carbon layer will now be compared. A ratio of carbon having an sp2bonding structure to total carbon may be obtained by measuring a D-parameter through x-ray photoelectron spectroscopy (XPS) analysis. Specifically, in XPS analysis, a peak shape of an Auger spectrum of carbon varies with the ratio of carbon having an sp2bonding structure to total carbon. The gap between the highest point and the lowest point on a D-parameter spectrum obtained by differentiating the peak shape serves as the D-parameter. Therefore, normal crystalline graphene, nanocrystalline graphene, and the amorphous carbon layer may be identified by measuring the D-parameter on the Auger spectrum of carbon. The content of hydrogen, which will be described below, may be obtained by performing composition analysis through, for example, Rutherford backscattering spectroscopy (RBS). Normal crystalline graphene may also be called intrinsic graphene and may include crystals having a size greater than, for example, about 100 nm. The D-parameter of normal crystalline graphene on the Auger spectrum of carbon may be about 23 eV. In this case, the ratio of carbon having an sp2bonding structure to total carbon may be almost 100%. Normal crystalline graphene may contain almost no hydrogen. In addition, normal crystalline graphene may have a density of, for example, about 2.1 g/cc and have a sheet resistance of, for example, about 100 Ohm/sq to about 300 Ohm/sq. Nanocrystalline graphene may include crystals smaller than those of normal crystalline graphene. Specifically, for example, nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm. The D-parameter of nanocrystalline graphene on the Auger spectrum of carbon may be about 18 eV to about 22.9 eV. In this case, the ratio of carbon having an sp2bonding structure to total carbon may be, for example, about 50% to about 99%. Nanocrystalline graphene may contain, for example, about 1 atomic percent (at %) to about 20 at % of hydrogen. Nanocrystalline graphene may have a density of, for example, about 1.6 g/cc to about 2.1 g/cc and a sheet resistance greater than, for example, about 1,000 Ohm/sq. The D-parameter of the amorphous carbon layer on the Auger spectrum of carbon may have a value between a D-parameter of diamond, e.g., about 13 eV, and the D-parameter of nanocrystalline graphene. In this case, the ratio of carbon having an sp2bonding structure to total carbon may be, for example, about 30% to about 50%. The amorphous carbon layer may contain, for example, more than about 20 at % of hydrogen. The carbon layer130having an sp2bonding structure may be a carbon layer130including nanocrystalline graphene. The carbon layer130may be on the upper surface of the channel element115of the substrate110. The carbon layer130may be formed by depositing nanocrystalline graphene on the upper surface of the channel element115of the substrate110through, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). Herein, the carbon layer130may include, for example, about 1 layer to about 100 layers of nanocrystalline graphene, but is not limited thereto. The carbon layer130may have a thickness of about 0.4 nm to about 100 nm. For example, the carbon layer130may have a thickness of about 0.4 nm to about 10 nm. However, the carbon layer130is not limited thereto. The ferroelectric layer140may be provided on an upper surface of the carbon layer130having an sp2bonding structure. A ferroelectric may have a non-centrosymmetric charge distribution in a unit cell of a crystallized material structure and thus may have spontaneous electric dipoles, e.g., spontaneous polarization. The ferroelectric may have remnant polarization by the dipoles without application of an external electric field. A polarization direction of the ferroelectric may be switched in domain units by an external electric field. The ferroelectric may have or may not have hysteresis characteristics depending on an external electric field, and the electronic device100may be implemented as a logic device or a memory device depending on whether the ferroelectric has or does not have hysteresis characteristics. As will be described below, the ferroelectric layer140may be formed by depositing a certain ferroelectric material as an amorphous ferroelectric layer on the upper surface of the carbon layer130having an sp2bonding structure, by, for example, CVD or ALD, and then by crystallizing the amorphous ferroelectric layer through an annealing process. The ferroelectric layer140may include an oxide including at least one of, for example, Si, aluminum (Al), hafnium (Hf), and zirconium (Zr). For example, the ferroelectric layer140may include at least one of Hf-based oxide and Zr-based oxide. Herein, the Hf-based oxide may include, for example, HfO or HfZrO, and the Zr-based oxide may include, for example, ZrO. In some embodiments, the ferroelectric layer140may further include a dopant. The dopant may include at least one of, for example, Si, Al, Zr, yttrium (Y), lanthanum (La), gadolinium (Gd), strontium (Sr), and Hf, but is not limited thereto. When the ferroelectric layer140includes the dopant, the dopant may be doped at the same concentration everywhere or may be doped at different concentrations in different regions. Alternatively, different regions of the ferroelectric layer140may be doped with different dopants. The gate electrode150may be provided on an upper surface of the ferroelectric layer140. Herein, the gate electrode150may be positioned at a side opposite to the channel element115of the substrate110. The gate electrode150may include a conductive metal. Alternatively, the gate electrode150may include a carbon material having an sp2bonding structure. Herein, the carbon material having an sp2bonding structure may include, for example, normal crystalline graphene or nanocrystalline graphene. Since the electronic device100according to the current embodiment includes the ferroelectric layer140, a subthreshold swing (SS) of the electronic device100may be lowered. FIG.2is a graph for describing improvement of SS characteristics of a logic transistor according to an example embodiment. InFIG.2, curve A indicates operating voltage Vg-current Id characteristics of a general Si-based logic transistor, and curve B indicates operating voltage Vg-current Id characteristics of the logic transistor according to an example embodiment. Referring toFIG.2, a SS of the general Si-based logic transistor may be limited to about 60 mV/dec. However, the logic transistor according to an example embodiment uses a ferroelectric layer and thus may lower a SS to below 60 mV/dec by voltage amplification occurring due to domain switching in a ferroelectric. In the electronic device100according to the current embodiment, since the carbon layer130having an sp2bonding structure may be provided between the ferroelectric layer140and the channel element115, diffusion of metal or oxygen in the ferroelectric layer140into the substrate110may be limited and/or prevented. For example, in a Si-based electronic device including a ferroelectric layer and a metal layer, since metal or oxygen in the ferroelectric layer diffuses into a Si substrate due to a high temperature in an annealing process, electrical leakage may occur. In addition, since an undesired Si oxide layer or silicide is formed, characteristics of the electronic device may deteriorate. However, in the electronic device100according to the current embodiment, since the carbon layer130having an sp2bonding structure may be provided between the ferroelectric layer140and the substrate110, the carbon layer130having an sp2bonding structure may limit and/or prevent diffusion of metal or oxygen in the ferroelectric layer140into the substrate110in a high-temperature annealing process. As such, current leakage may be limited and/or prevented and formation of an undesired Si oxide layer or silicide may also be limited and/or prevented. In addition, since the diffusion limitation and/or prevention effect may be achievable even when the carbon layer130having an sp2bonding structure may have a small thickness of about 1 nm, a total thickness of the electronic device100may be reduced. Therefore, the electronic device100may be easily scaled down. Furthermore, in the electronic device100according to the current embodiment, since the carbon layer130having an sp2bonding structure may have a high charge density, an equipotential may be formed between the carbon layer130and the channel element115. Therefore, the carbon layer130having an sp2bonding structure may screen a non-uniform electric potential due to a multi-domain structure of the ferroelectric layer140and thus may increase uniformity in characteristics of the electronic device100. FIG.3is a cross-sectional view of an electronic device200according to another example embodiment. The following description is focused on differences from the afore-described embodiment. Referring toFIG.3, the electronic device200includes a substrate210, and a channel layer215, a carbon layer230, a ferroelectric layer240, and a gate electrode250sequentially stacked on the substrate210, wherein the carbon layer230may have an sp2bonding structure. A source electrode221and a drain electrode222may be provided at both sides of the channel layer215. The substrate210may be a semiconductor substrate. For example, the substrate210may be a Si, Ge, SiGe, or a group III-V semiconductor, but is not limited thereto. The channel layer215may be provided on an upper surface of the substrate210. The channel layer215may not be provided as a part of the substrate210and may be provided as a material layer separate from the substrate210. The channel layer215may include at least one of, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, quantum dots (QDs), and an organic semiconductor. Herein, the oxide semiconductor may include, for example, InGaZnO, the 2D material may include, for example, transition metal dichalcogenide (TMD) or graphene, and the QDs may include, for example, colloidal or nanocrystal QDs. When the channel layer215includes graphene, the graphene may be treated, thickened (e.g., more than 5 monolayers of graphene), and/or narrowed (e.g., smaller than 10 nm) in order to make the band gap of the graphene in the channel layer215more than 0 eV. However, the above-mentioned materials are merely examples and the current embodiment is not limited thereto. The source electrode221and the drain electrode222may be provided at both sides of the channel layer215. The source electrode221may be connected to a side of the channel layer215, and the drain electrode222may be connected to the other side of the channel layer215. The source electrode221and the drain electrode222may be made of a conductive material such as a metal, a metal compound, or a conductive polymer. The carbon layer230, the ferroelectric layer240, and the gate electrode250sequentially stacked on the channel layer215have been described above and thus detailed descriptions thereof will not be provided herein. FIG.4is a cross-sectional view of an electronic device300according to another example embodiment. The following description is focused on differences from the afore-described embodiments. Referring toFIG.4, the electronic device300includes a substrate310, and an insulating layer360, a carbon layer330, a ferroelectric layer340, and a gate electrode350sequentially stacked on the substrate310, wherein the carbon layer330may have an sp2bonding structure. A channel element315may be provided in the substrate310at a location corresponding to the gate electrode350, and a source (S)321and a drain (D)322may be provided at both sides of the channel element315. The source321may be electrically connected to a side of the channel element315, and the drain322may be electrically connected to the other side of the channel element315. The source321and the drain322may be formed by implanting impurities into different regions of the substrate310, and a region of the substrate310between the source321and the drain322may be defined as the channel element315. The substrate310may be a semiconductor substrate. For example the substrate310may be a Si, Ge, SiGe, or a group III-V semiconductor, but is not limited thereto. Meanwhile, the channel element315may not be provided as a part of the substrate310and may be provided as a material layer separate from the substrate310. The insulating layer360may be provided on an upper surface of the channel element315. The insulating layer360may have a small thickness of greater than 0 nm and equal to or less than, for example, about 5 nm. However, the insulating layer360is not limited thereto and may have a thickness greater than about 5 nm. The insulating layer360may include, for example, Si oxide, Al oxide, Hf oxide, Zr oxide, or a 2D insulator such as hexagonal boron nitride (h-BN). However, the material of the insulating layer360is not limited thereto and may be changed. The insulating layer360may serve to suppress or prevent electrical leakage and may also be used for capacitance matching in a gate stack structure. The carbon layer330having an sp2bonding structure may be provided on an upper surface of the insulating layer360. Herein, the carbon layer330having an sp2bonding structure may include nanocrystalline graphene including nano-sized crystals. Herein, nanocrystalline graphene may include crystals smaller than those of normal crystalline graphene. Specifically, for example, nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm. A ratio of carbon having an sp2bonding structure to total carbon may be, for example, about 50% to about 99%. Nanocrystalline graphene may contain, for example, about 1 at % to about 20 at % of hydrogen. Nanocrystalline graphene may have a density of, for example, about 1.6 g/cc to about 2.1 g/cc and a sheet resistance greater than, for example, about 1,000 Ohm/sq. The carbon layer330having an sp2bonding structure may have a thickness of about 0.4 nm to about 100 nm. For example, the carbon layer330may have a thickness of about 0.4 nm to about 10 nm. However, the carbon layer330is not limited thereto. As described above, the carbon layer330having an sp2bonding structure may limit and/or prevent diffusion of metal or oxygen in the ferroelectric layer340through the insulating layer360into the substrate310. In addition, since the diffusion limitation and/or prevention effect is achievable even when the carbon layer330having an sp2bonding structure may have a small thickness of about 1 nm, a total thickness of the electronic device300may be reduced. Therefore, the electronic device100may be easily scaled down. The carbon layer330having an sp2bonding structure may have a high charge density and thus may increase uniformity in characteristics of the electronic device300. The ferroelectric layer340may be provided on an upper surface of the carbon layer330having an sp2bonding structure. The ferroelectric layer340may include an oxide including at least one of, for example, Si, Al, Hf, and Zr. Specifically, for example, the ferroelectric layer340may include at least one of Hf-based oxide and Zr-based oxide. Herein, the Hf-based oxide may include, for example, HfO or HfZrO, and the Zr-based oxide may include, for example, ZrO. In some embodiments, the ferroelectric layer340may further include a dopant. The dopant may include at least one of, for example, Si, Al, Zr, Y, La, Gd, Sr, and Hf, but is not limited thereto. When the ferroelectric layer340includes the dopant, the dopant may be doped at the same concentration everywhere or doped at different concentrations in different regions. Alternatively, different regions of the ferroelectric layer340may be doped with different dopants. The gate electrode350may be provided on an upper surface of the ferroelectric layer340. The gate electrode350may include a conductive metal. Alternatively, the gate electrode350may include a carbon material having an sp2bonding structure. Herein, the carbon material having an sp2bonding structure may include, for example, normal crystalline graphene or nanocrystalline graphene. Due to the ferroelectric layer340, a SS of the electronic device300may be lowered. FIG.5is a cross-sectional view of an electronic device400according to another example embodiment. The following description is focused on differences from the afore-described embodiments. Referring toFIG.5, the electronic device400includes a substrate410, and a carbon layer430, an insulating layer460, a ferroelectric layer440, and a gate electrode450sequentially stacked on the substrate410, wherein the carbon layer430may have an sp2bonding structure. A channel element415may be provided in the substrate410at a location corresponding to the gate electrode450, and a source (S)421and a drain (D)422may be provided at both sides of the channel element415. The carbon layer430having an sp2bonding structure may be provided on an upper surface of the channel element415. Herein, the carbon layer430having an sp2bonding structure may include nanocrystalline graphene including nano-sized crystals. The carbon layer430having an sp2bonding structure may have a thickness of about 0.4 nm to about 100 nm. The insulating layer460may be provided on an upper surface of the carbon layer430having an sp2bonding structure. The insulating layer460may have a small thickness equal to or less than, for example, about 5 nm. However, the insulating layer460is not limited thereto. The insulating layer460may include, for example, Si oxide, Al oxide, Hf oxide, Zr oxide, or a 2D insulator such as h-BN. The ferroelectric layer440may be provided on an upper surface of the insulating layer460. The ferroelectric layer440may include an oxide including at least one of, for example, Si, Al, Hf, and Zr. The ferroelectric layer440may further include a dopant. The dopant may include at least one of, for example, Si, Al, Zr, Y, La, Gd, Sr, and Hf, but is not limited thereto. The gate electrode450may be provided on an upper surface of the ferroelectric layer440. The gate electrode450may include a conductive metal or a carbon material having an sp2bonding structure. FIGS.6A to6Fare cross-sectional views for describing a method of manufacturing an electronic device500, according to an example embodiment. Referring toFIG.6A, a substrate510including a channel element515, a source (S)521, and a drain (D)522may be prepared. The source521and the drain522may be formed by implanting impurities into different regions of the substrate510, and a region of the substrate510between the source521and the drain522may be defined as the channel element515. The substrate510may include a semiconductor (e.g., Si, Ge, SiGe, or a group III-V semiconductor). In this case, the channel element515may also include Si, Ge, SiGe, or a group III-V semiconductor like the substrate510. The material of the substrate510is not limited to the above-mentioned examples and may be variously changed. The timing at which the source521and the drain522are formed may vary. For example, the source521and the drain522may be formed in the substrate510after a gate electrode550(seeFIG.6D) may be formed as will be described below. The channel element515may not be formed as a part of the substrate510and may be formed on an upper surface of the substrate510as a material layer separate from the substrate510. In this case, the channel element515may include various materials. For example, the channel element515may include at least one of, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D material, QDs, and an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO, the 2D material may include, for example, TMD or graphene, and the QDs may include, for example, colloidal or nanocrystal QDs. However, the above-mentioned materials are merely examples and the current embodiment is not limited thereto. Referring toFIG.6B, a carbon layer530having an sp2bonding structure may be formed on an upper surface of the channel element515of the substrate510. Herein, the carbon layer530having an sp2bonding structure may include nanocrystalline graphene including nano-sized crystals. For example, nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm. In nanocrystalline graphene, a ratio of carbon having an sp2bonding structure to total carbon may be about 50% to about 99%, and about 1 at % to about 20 at % of hydrogen may be contained. Nanocrystalline graphene may have a density of, for example, about 1.6 g/cc to about 2.1 g/cc and a sheet resistance greater than, for example, about 1,000 Ohm/sq. The carbon layer530having an sp2bonding structure may be formed by depositing nanocrystalline graphene on the upper surface of the channel element515of the substrate510by, for example, CVD or ALD. Herein, the carbon layer530having an sp2bonding structure may include, for example, about 1 layer to about 100 layers of nanocrystalline graphene, but is not limited thereto. The carbon layer130may have a thickness of about 0.4 nm to about 100 nm, but is not limited thereto. Referring toFIG.6C, an amorphous ferroelectric layer540′ may be formed on an upper surface of the carbon layer530having an sp2bonding structure. The amorphous ferroelectric layer540′ may be formed by depositing a certain ferroelectric material on the upper surface of the carbon layer530having an sp2bonding structure, through, for example, CVD or ALD. The amorphous ferroelectric layer540′ may be a thin film having a high dielectric constant. For example, the dielectric constant of the amorphous ferroelectric layer540′ may be equal to or greater than about 10. Therefore, the amorphous ferroelectric layer540′ may serve as a high-k dielectric layer. The amorphous ferroelectric layer540′ may include an oxide including at least one of, for example, Si, Al, Hf, and Zr. Specifically, for example, the amorphous ferroelectric layer540′ may include at least one of Hf-based oxide and Zr-based oxide. Herein, the Hf-based oxide may include, for example, HfO or HfZrO, and the Zr-based oxide may include, for example, ZrO. The amorphous ferroelectric layer540′ may further include a dopant. Herein, the dopant may include at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf. When the amorphous ferroelectric layer540′ includes the dopant, the dopant may be doped at the same concentration everywhere or doped at different concentrations in different regions. Alternatively, different regions of the amorphous ferroelectric layer540′ may be doped with different dopants. The amorphous ferroelectric layer540′ may be doped while the amorphous ferroelectric layer540′ is being formed, or doped in a separate process after the amorphous ferroelectric layer540′ is formed. Referring toFIG.6D, a gate electrode550may be formed on an upper surface of the amorphous ferroelectric layer540′. The gate electrode550may be formed by depositing a conductive material on the upper surface of the amorphous ferroelectric layer540′ by, for example, CVD, physical vapor deposition (PVD), or ALD. The gate electrode550may include a conductive metal. Alternatively, the gate electrode550may include a carbon material having an sp2bonding structure. Herein, the carbon material having an sp2bonding structure may include, for example, normal crystalline graphene or nanocrystalline graphene. Referring toFIG.6E, an annealing process for crystallizing the amorphous ferroelectric layer540′ is performed. The annealing process may be performed at a temperature of, for example, about 400° C. to about 1,000° C. The annealing process may be performed within about 1 min. However, the temperature and time of the annealing process are not limited thereto and may be variously changed. The amorphous ferroelectric layer540′ may be crystallized through the annealing process. When the amorphous ferroelectric layer540′ is completely crystallized, a ferroelectric layer540may be obtained as illustrated inFIG.6Fand thus the electronic device500may be manufactured. The above-described method of manufacturing the electronic device500may further include generating an insulating layer (not shown) on the upper surface of the channel element515of the substrate510, before the carbon layer530having an sp2bonding structure is formed. In this case, the carbon layer530having an sp2bonding structure may be formed on an upper surface of the insulating layer. The insulating layer may be formed by depositing a certain insulating material on the upper surface of the channel element515of the substrate510by, for example, CVD or ALD. The insulating layer may have a small thickness equal to or less than, for example, about 5 nm, but is not limited thereto. The insulating layer may include, for example, Si oxide, Al oxide, Hf oxide, Zr oxide, or a 2D insulator such as h-BN, but is not limited thereto. The above-described method of manufacturing the electronic device500may further include generating an insulating layer (not shown) on the upper surface of the carbon layer530having an sp2bonding structure, after the carbon layer530having an sp2bonding structure is formed and before the amorphous ferroelectric layer540′ is formed. In this case, the amorphous ferroelectric layer540′ may be formed on an upper surface of the insulating layer. FIG.7Ais a scanning electron microscopy (SEM) image of normal crystalline graphene (SLG) formed on a Si substrate. InFIG.7A, SLG denotes single layer graphene.FIG.7Bis a SEM image of nanocrystalline graphene (ncG) and hafnium zirconium oxide (HZO) formed on a Si substrate. Referring toFIG.7A, a SiO2insulating layer may be formed on an upper surface of the Si substrate, and SLG may be formed on an upper surface of the SiO2insulating layer. Herein, it is shown that a ferroelectric layer such as HZO is not formed on an upper surface of SLG. Referring toFIG.7B, a SiO2insulating layer may be formed on an upper surface of the Si substrate, and ncG may be formed on an upper surface of the SiO2insulating layer. HZO serving as a ferroelectric layer may be formed to a thickness of about 3 nm on an upper surface of ncG. Therefore, it is shown that ncG provides a high adhesive force to the ferroelectric layer formed thereon. FIGS.8A through8Dillustrate a method of manufacturing an electronic device according to an example embodiment. Referring toFIG.8A, a channel film may be formed on the substrate210and patterned into the channel layer215. Then, the source electrode221and drain electrode222may be formed on ends of the channel layer215. Referring toFIG.8B, the carbon layer230may then be formed on the channel layer215. The carbon layer230may be patterned as shown inFIG.8Bsuch that sides of the carbon layer230may be spaced apart from the source electrode221and drain electrode222. Referring toFIG.8C, an amorphous ferroelectric layer240′ and a gate electrode250may be formed on the carbon layer230. Referring toFIG.8D, an annealing process may be performed on the amorphous ferroelectric layer240′. The annealing process may crystallize the amorphous ferroelectric layer240′ into ferroelectric layer240shown inFIG.3. FIGS.9A through9Dillustrate a method of manufacturing an electronic device according to an example embodiment. FIGS.9A to9Care similar toFIGS.6B to6F, except the insulating layer360may be formed before forming the carbon layer330. Referring toFIG.9A, the insulating layer360may be formed on the substrate310and the carbon layer330may be formed on the insulating layer330. The insulating layer360may be formed directly on the substrate310. Referring toFIG.9B, the amorphous ferroelectric layer340′ may be formed on the carbon layer330. Referring toFIG.9C, the gate electrode350may be formed on the amorphous ferroelectric layer340′. Referring toFIG.9D, an annealing process may be performed on the amorphous ferroelectric layer340′. The annealing process may crystallize the amorphous ferroelectric layer340′ into ferroelectric layer340shown inFIG.4. According to afore-described embodiments, using a ferroelectric layer, an electronic device capable of lowering a SS by voltage amplification occurring due to domain switching in a ferroelectric may be implemented. Furthermore, by providing a carbon layer having an sp2bonding structure between the ferroelectric layer and a channel element, diffusion of metal or oxygen in the ferroelectric layer into a substrate in an annealing process may be limited and/or prevented. As such, current leakage may be limited and/or prevented and formation of an undesired Si oxide layer or silicide may also be limited and/or prevented. In addition, since the diffusion limitation and/or prevention effect is achievable even when the carbon layer having an sp2bonding structure may have a small thickness of about 1 nm, a total thickness of the electronic device may be reduced. Therefore, the electronic device may be easily scaled down. Since the carbon layer having an sp2bonding structure may have a high charge density, an equipotential may be formed between the carbon layer and the channel element. Therefore, the carbon layer having an sp2bonding structure may screen a non-uniform electric potential due to a multi-domain structure of the ferroelectric layer and thus may increase uniformity in characteristics of the electronic device. The carbon layer including nanocrystalline graphene may provide a high adhesive force to the ferroelectric layer deposited thereon. It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. | 34,564 |
11862705 | DETAILED DESCRIPTION Reference will now be made in detail to example embodiments, some of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, some example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, some example embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items (e.g., A, B, and C). Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and “at least one of A, B, or C” may be construed as covering any one of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.” Hereinafter, an electronic device and a method of manufacturing the same according to various embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals in the following drawings represent like elements, and the size of each of components in the drawings may be exaggerated for clarity and convenience of explanation. It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. The terms are used only to distinguish one component from other components. As used herein, the singular forms “a,” “an,” and the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when a portion “comprises” a component, this means that a portion may further comprise other components instead of excluding other components, unless specifically stated to the contrary. In addition, the size or thickness of each of components in the drawings may be exaggerated for clarity of explanation. In addition, when it is described that a particular (or, alternatively, predetermined) material layer is present on a substrate or another layer, the material layer may be in direct contact with the substrate or another layer, or another third layer may be present therebetween. Restated, when an element or layer is referred to as being “on” or “above” another element or layer, the element or layer may be directly on the other element or layer (e.g., in direct contact therewith), or the element or layer may be indirectly on the other element or layer (e.g., isolated from direct contact with the other element or layer by one or more interposing spaces and/or structures). Where an element is described as being directly between two other elements, the element may be in direct contact with each of the two other elements, for example opposite sides or surfaces of the element may each be in direct contact with a separate element of the two other elements. In some example embodiments described herein, a described material for forming each layer is just an example, and other materials than the described material may be used. In addition, the terms “ . . . portion,” “module”, etc. described in the present specification mean a unit for processing at least one function or operation, and this unit may be implemented with hardware or software or a combination of hardware and software. Specific implementations described in some example embodiments are examples and do not limit the technical scope in any way. For brevity of the specification, descriptions of electronic configurations according to the related art, control system, software, and other functional aspects of the systems may be omitted. In addition, connections of lines between components shown in the drawings or connection members for the components are illustrative examples of functional connections and/or physical or circuit connections and in a real device, may be represented as alternative or additional various functional connections, physical connections, or circuit connections. The use of the term “above” and similar indication terms may be applied to both singular and plural. The steps that make up the method can be done in a suitable order, unless there is a clear statement that they should be done in the order described. In addition, the use of all example terms (e.g., etc.) is merely for describing the technical idea in detail, and the scope of rights is not limited by these terms unless it is limited by the claims. It will be understood that elements and/or properties thereof may be recited herein as being “the same,” “similar to,” or “equal” as other elements, and it will be further understood that elements and/or properties thereof recited herein as being “the same” as, “similar” to, or “equal” to other elements may be “the same” as or “equal” to or “substantially the same” as or “substantially equal” to the other elements and/or properties thereof. Elements and/or properties thereof that are “substantially the same” as or “substantially equal” to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are the same as or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances. Elements and/or properties thereof that are the same or substantially the same as other elements and/or properties thereof may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same. It will be understood that elements and/or properties thereof (e.g., structures, properties of one or more elements, lengths, distances, energy levels, energy barriers, or the like) described herein as being the “substantially” the same or “similar” thereto encompasses elements and/or properties thereof (e.g., structures, properties of one or more elements, lengths, distances, energy levels, energy barriers, or the like) that are the same within manufacturing tolerances and/or material tolerances and/or elements and/or properties thereof (e.g., structures, properties of one or more elements, lengths, distances, energy levels, energy barriers, or the like) that have a relative difference in magnitude that is equal to or less than 10%. Further, regardless of whether elements and/or properties thereof (e.g., structures, properties of one or more elements, lengths, distances, energy levels, energy barriers, or the like) are modified as “substantially,” it will be understood that these elements and/or properties thereof (e.g., structures, properties of one or more elements, lengths, distances, energy levels, energy barriers, or the like) should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated elements and/or properties thereof (e.g., structures, properties of one or more elements, lengths, distances, energy levels, energy barriers, or the like). When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a tolerance of ±10% around the stated numerical value. When ranges are specified, the range includes all values therebetween such as increments of 0.1%. Where elements, properties, or the like are described herein to have a “small” or “very small” difference between each other, it will be understood that a variation between the magnitudes of said elements and/or properties may be equal to or less than 10% of the magnitudes of the elements, properties, or the like being described. Throughout the specification, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements, should not be limited by these terms. These terms are only used to distinguish one element from another element. It will be understood that, where an element, layer, structure, or the like is described herein to be “made of” and/or “formed of” one or more materials, the element, layer, structure, or the like may “at least partially comprise” said one or more materials. FIG.1illustrates an electronic device according to some example embodiments. An electronic device100may include a substrate110, a seed layer120on the substrate110(e.g., directly on the substrate110so as to be in direct contact with the top surface110S of the substrate110), and a ferroelectric layer130on the seed layer120(e.g., directly on the seed layer120so as to be in direct contact with the top surface120S of the seed layer120). In some example embodiments, the substrate110may be omitted and/or the seed layer120may serve as a substrate on which the ferroelectric layer130is formed. It will be understood that in some example embodiments, the adjacent layers120-140(e.g., layers120and110, layers130and120, and layers140and130) may not be directly on each other, such that the layers are isolated from direct contact with each other by one or more interposing spaces and/or structures. For example, seed layer120may be indirectly on the substrate110, the ferroelectric layer130may be indirectly on the seed layer120and between the upper layer140and the seed layer120, and the upper layer140may be indirectly on the ferroelectric layer130. The substrate110may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a III-V-group compound semiconductor, or a two-dimensional (2D) material. However, a material for forming the substrate110is not limited by the above description and may be variously changed. For example, the substrate110may include Si, Ge, SiGe, Group III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductor materials, quantum dots, or organic semiconductors, any combination thereof, and or the like. The seed layer120may include a two-dimensional (2D) material, for example. The seed layer120may have a lattice structure similar to (e.g., the same or substantially the same as) that of the ferroelectric layer130. FIG.2is a plan view of the lattice structure of the seed layer120, andFIG.3is a front view of the lattice structure of the seed layer120. The seed layer120may have a hexagonal lattice structure, as shown in region A, for example. As shown in region A ofFIG.2, separate elements of the hexagonal lattice structure of the seed layer120may be spaced apart by a distance d1. The seed layer120may include, for example, at least one of 1T-MoTe2, 1T-WTe2, 2H—MoTe2, 2H—WTe2, 1T-ZrS2, 1T-HfS2, 2H—ZrS2, 2H—HfS2, 2H—CrTe2, 2H—HfSe2, 1T-PdS2, 1T-PtS2, 2H—SnS2, 2H—TiSe2, 2H—VTe2, 2H—NbSe2, or GaS. In some example embodiments, the seed layer120may include a metallic 2D material. The seed layer120may have a structure of a 2D material made of Van der Waals bonds. The seed layer120may have the thickness 120 T (e.g., in the Z-direction) of about 0.3 nm to about 100 nm, for example. The seed layer120may include a thin film, which may contribute to miniaturization of the size of the electronic device100. The ferroelectric layer130may include a material having a fluorite structure. The ferroelectric layer130may have a greater dielectric constant than about 20, for example. However, example embodiments of the present disclosure are not limited thereto. For example, the ferroelectric layer130may include an oxide of at least one of Si, aluminum (Al), hafnium (Hf), or zirconium (Zr). For example, the ferroelectric layer130may include at least one of a Hf-based oxide or a Zr-based oxide. Here, the Hf-based oxide may include hafnium oxide (HfO) or hafnium zirconium oxide (HfZrO), for example, and the Zr-based oxide may include zirconium oxide (ZrO), for example. In addition, the ferroelectric layer130may further include a dopant. The dopant may include, for example, at least one of Hf, Si, Al, Zr, yttrium (Y), lanthanum (La), gadolinium (Gd), or strontium (Sr). Accordingly, the ferroelectric layer130may include at least one of hafnium (Hf), silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), or strontium (Sr). FIG.4is a plan view of the lattice structure of the ferroelectric layer130. The ferroelectric layer130may have a hexagonal lattice structure, as shown in region B ofFIG.4. In this way, the seed layer120and the ferroelectric layer130may have similar lattice structure (e.g., a substantially same lattice structure). As shown in region B ofFIG.4, separate elements of the hexagonal lattice structure of the ferroelectric layer130may be spaced apart by a distance d2. For example, the ferroelectric layer130may be configured to be aligned within a range of equal to or less than ±30 degrees with respect to a direction in which a (111) crystal direction is perpendicular to the top surface110S of the substrate110. In another example, including example embodiments where the substrate110is absent from the electronic device100, the ferroelectric layer130may be configured to be aligned within a range of equal to or less than ±30 degrees with respect to a direction in which a (111) crystal direction is perpendicular to the top surface120S of the seed layer120. In some example embodiments, the ferroelectric layer130may be arranged with ±20 degrees with respect to a direction in which the (111) crystal direction is perpendicular to the substrate110and/or the top surface120S of the seed layer120. Because the ferroelectric layer130may have a lattice structure similar to that of the seed layer120, when the ferroelectric layer130is deposited on the seed layer120, the ferroelectric layer130may be arranged in such a way that the (111) crystal direction of the ferroelectric layer130may be perpendicular to the substrate110(e.g., perpendicular to the top surface110S of the substrate110, for example in the Z-direction that extends perpendicular to the top surface110S). The ferroelectric layer130may have ferroelectric or anti-ferroelectric properties (e.g., may include a ferroelectric material or an anti-ferroelectric material). The seed layer120may have a lattice constant having a magnitude that is in the range of about 90% to about 110% with respect to the magnitude of the lattice constant of the ferroelectric layer130. The seed layer120may have a lattice constant in the range from about 2.16 to about 3.96, for example. The seed layer120may have a lattice constant in the range from about 3.16 to about 3.8, for example. The ferroelectric layer130may have a lattice constant having a magnitude that is in the range of about 90% to about 110% with respect to the magnitude of the lattice constant of the seed layer120. When the lattice constants of the seed layer120and the ferroelectric layer130are similar to each other, the crystal direction of the ferroelectric layer130may be adjusted to correspond to (e.g., to match) the crystal direction of the seed layer120. The seed layer120may include, for example, a material with an energy band gap of about 2 or less. The seed layer120may include, for example, a material with an energy band gap that is greater than or equal to about 0.2 and less than or equal to about 1.8. An upper layer140may be further provided on the ferroelectric layer130(e.g., directly on the ferroelectric layer130so as to be in direct contact with the top surface130S of the ferroelectric layer130). The upper layer140may be, for example, a protective layer, an electrode layer, or a metal layer. The upper layer140may include, for example, at least one of a dielectric, silicon oxide (SiO), aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), yttrium oxide (YO), lanthanum oxide (LaO), or strontium oxide (SrO). In addition, the upper layer140may further include a dopant. In some example embodiments, the upper layer140may include, for example, at least one of Hf, Si, Al, Zr, Y, La, Gd, or Sr. In some example embodiments, the upper layer140may include metal, a metal nitride, or a metal oxide. In some example embodiments, the upper layer140may include at least one of Si, germanium (Ge), a thin film semiconductor, an oxide semiconductor, a III-V-group compound, a 2D material, transition metal dichalcogenides, a quantum dot, a colloidal QD, a nanocrystal, or an organic material. The ferroelectric layer130may be crystalized through an annealing process of at least part of an amorphous dielectric material (which may be implemented based on heat generated by a heat source being applied to the amorphous dielectric material), as will be described later. The ferroelectric layer130may have the effect of reducing a subthreshold swing (SS) of the electronic device100due to ferroelectric or anti-ferroelectric properties, thereby improving the functional performance thereof. Ferroelectric materials have a spontaneous electric dipole, that is, spontaneous polarization, due to non-centrosymmetric charge distribution in a unit cell in a crystallized material structure. The ferroelectric materials have remnant polarization due to a dipole even in the absence of an external electric field. Furthermore, the direction of polarization may be changed on a domain basis by the external electric field. Anti-ferroelectric materials may include an array of electric dipoles but remnant polarization of the anti-ferroelectric materials may be zero or close to zero. Because, in the absence of an electric field, the directions of adjacent dipoles are reversed and the polarization is canceled, the total spontaneous polarization and the remnant polarization may be zero or close to zero. However, in a state in which the external electric field is applied, polarization characteristics and switching characteristics may be exhibited. FIG.5is a graph showing the effect of enhancing subthreshold swing (SS) characteristics of an electronic device according to some example embodiments (e.g., the electronic device shown inFIG.1), when the electronic device according to some example embodiments is applied to a logic transistor. The electronic device according to some example embodiments may include a seed layer and a ferroelectric layer. InFIG.5, curve “C” shows an operating voltage Vg (e.g., in mV) and current Id (e.g., in A/μm2) characteristics of a silicon-based logic transistor according to the related art, and curve “D” shows an operating voltage Vg and current Id characteristics of an electronic device according to some example embodiments (e.g., the electronic device shown inFIG.1). Referring toFIG.5, it is known that, in the silicon-based transistor according to the related art, the subthreshold swing (SS) is limited to about 60 mV/dec (e.g., as shown in curve “C”). Contrary to this, in the electronic device according to some example embodiments (e.g., as shown in curve “D”), the subthreshold swing (SS) may be decreased to 60 mV/dec or less based on voltage amplification occurring when a domain of inside the ferroelectric is switched. Thus, the operating voltage of the electronic device according to some example embodiments may be decreased, and thus the operational performance and/or efficiency (e.g., improved power consumption efficiency and/or reduced power consumption) of the electronic device may be improved, for example based on including a ferroelectric layer as described herein. FIG.6illustrates a static dielectric constant and an energy gap of a high-k dielectric material. Here, the high-k dielectric material may refer to a material having a higher dielectric constant than a silicon oxide. Referring toFIG.6, the ferroelectric layer130may include a material having a high dielectric constant, for example, ZrO2or HfO2. However, this is just an example, and the ferroelectric layer130may include other various high-k dielectric materials than the material. When the ferroelectric layer130is crystallized and when the ferroelectric layer130is stacked on the seed layer120, a dielectric constant may be increased (e.g., to a dielectric constant that is greater than about 20), which may result in a decreased operating voltage of an electronic device that includes the ferroelectric layer130stacked on the seed layer120, and thus the operational performance and/or efficiency (e.g., improved power consumption efficiency and/or reduced power consumption) of the electronic device may be improved. A dopant may be further included in the ferroelectric layer130. The dopant may include at least one of Si, Al, Zr, Y, La, Gd, Sr, or Hf, for example, but example embodiments of the present disclosure are not limited thereto. When a dopant is included in the ferroelectric layer130, the dopant may be doped at the same concentration as a whole (e.g., the ferroelectric layer130may have a uniform concentration of the dopant throughout the ferroelectric layer130), or may also be doped at different concentrations depending on regions. In addition, different dopants may be doped depending on regions of the ferroelectric layer130(e.g., the ferroelectric layer130may include different dopants in different regions of the ferroelectric layer130). FIG.7shows energy changes according to the amount of charges. Here, E is for an SiO2layer, F is for a ferroelectric, and G is for the sum of SiO2and the ferroelectric. Referring toFIG.7, capacitance may be greater in a structure in which SiO2and ferroelectric layers are stacked, compared to the SiO2layer. However, in this case, the thickness of SiO2is large and is not suitable for a small electronic device. In some example embodiments, the seed layer may be used to reduce the thickness while increasing the capacitance. In some example embodiments, based on using a seed layer having a lattice structure similar to that of the ferroelectric layer, the (111) crystal direction of the ferroelectric layer may be adjusted so that the capacitance may be increased and thus the operating voltage may be decreased, thereby improving the operational performance and/or efficiency (e.g., improved power consumption efficiency and/or reduced power consumption) of an electronic device that includes the ferroelectric layer (e.g., ferroelectric layer130). FIGS.8,9, and10show a structure for a metal layer so as to compare with a comparison example in which the seed layer of the electronic device according to some example embodiments includes a 2D material.FIG.8shows an x-ray diffraction (XRD) analysis result of a tungsten layer at the room temperature (e.g., between 20-30 degrees Celsius), for example.FIG.8shows a (110) crystal direction and a (200) crystal direction.FIG.9shows an XRD analysis result of a tungsten layer at 350 degrees Celsius, for example.FIG.9shows the (110) crystal direction.FIG.10shows an XRD analysis result of a tungsten layer at 450 degrees Celsius, for example.FIG.10shows the (110) crystal direction and the (200) crystal direction. Referring toFIGS.8through10, the metal layer such as tungsten does not represent the (111) crystal direction. Thus, when a ferroelectric layer is stacked on the metal layer (e.g., directly on the metal layer so as to be in direct contact with a surface of the metal layer), the (111) crystal direction of the ferroelectric layer may not be easily adjusted. Thus, when the ferroelectric layer is stacked on (e.g., directly on) the metal layer, it is difficult to expect the effect of decreasing the operating voltage. FIG.11shows an electronic device according to some example embodiments. An electronic device200may include a substrate210, a seed layer220on the substrate210(e.g., directly on the substrate210as shown inFIG.11), a ferroelectric layer230on the seed layer220(e.g., directly on the seed layer220as shown inFIG.11), and an upper layer240on the ferroelectric layer230(e.g., directly on the ferroelectric layer230as shown inFIG.11). The electronic device200may be applied to (e.g., included in) a capacitor element. The substrate210may include a metal layer, for example. Here, the substrate210may be a metal layer, and a metal layer may also be between the substrate210and the seed layer220. The upper layer240may include a metal layer, for example. The seed layer220may include a 2D material and may have a lattice structure similar to that of the ferroelectric layer230. The seed layer220and the ferroelectric layer230are substantially the same as the seed layer120and the ferroelectric layer130described with reference toFIG.1and thus, a detailed description thereof will be omitted. The ferroelectric layer230may be arranged in a direction in which the (111) crystal direction is perpendicular to the top surface210S of the substrate210due to the seed layer220. When the ferroelectric layer230has this crystal structure and when the electronic device200is applied to (e.g., is included in) a capacitor, the capacitance of the capacitor may be increased, and thus, the operating voltage may be decreased and thus the operational performance and/or efficiency (e.g., improved power consumption efficiency and/or reduced power consumption) of the capacitor may be improved. It will be understood that in some example embodiments, the adjacent layers210-240(e.g., layers220and210, layers230and220, and layers240and230) may not be directly on each other, such that the layers are isolated from direct contact with each other by one or more interposing spaces and/or structures. For example, seed layer220may be indirectly on the substrate210, the ferroelectric layer230may be indirectly on the seed layer220and between the upper layer240and the seed layer220, and the upper layer240may be indirectly on the ferroelectric layer230. FIG.12schematically illustrates an electronic device according to some example embodiments. An electronic device300may include a substrate310, a seed layer330on the substrate310(e.g., directly on the substrate310as shown inFIG.12), a ferroelectric layer340on the seed layer330(e.g., directly on the seed layer330as shown inFIG.12), and an upper layer350on the ferroelectric layer340(e.g., directly on the ferroelectric layer340as shown inFIG.12). A source electrode321and a drain electrode322may be provided at both sides (e.g., opposite sides) of the substrate310. The electronic device300may be applied to (e.g., included in) a transistor. The upper layer350may be a gate electrode layer, for example. The upper layer350may include a conductive material. In the electronic device300according to some example embodiments, the source electrode321may be provided at one side of the substrate310, and the drain electrode322may be provided at the other side of the substrate310. The source electrode321and the drain electrode322may be formed by injecting impurities into different regions of the substrate310, and a region320of the substrate310between the source electrode321and the drain electrode322may be defined as a channel element (e.g., a channel layer). However, sin some example embodiments an electronic device300may include a channel layer (not shown) that may also be provided independently of the substrate310(e.g., may be a separate piece of material in relation to the substrate310). The substrate310may be a Si substrate, for example, and may include other semiconductor materials, for example, Ge, SiGe, a III-V-group semiconductor, etc., than Si. However, a material for forming the substrate310is not limited to the above description and may be variously changed. It will be understood that in some example embodiments, the adjacent layers310-350(e.g., layers330and310, layers340and330, and layers350and340) may not be directly on each other, such that the layers are isolated from direct contact with each other by one or more interposing spaces and/or structures. For example, seed layer330may be indirectly on the substrate310, the ferroelectric layer340may be indirectly on the seed layer330and between the upper layer350and the seed layer330, and the upper layer350may be indirectly on the ferroelectric layer340. An electronic device described in some example embodiments that is a semiconductor-based device may have a gate stack structure including a ferroelectric layer having a higher dielectric constant than that of silicon oxide and a gate electrode. The electronic device may be applied to (e.g., included in) a logic device or memory device, for example. Hereinafter, a method of manufacturing an electronic device, according to some example embodiments will be described. FIGS.13,14,15, and16illustrate a method of manufacturing an electronic device, according to some example embodiments. Referring toFIG.13, a seed layer420may be stacked on a substrate410(e.g., directly on the substrate410such that the seed layer420is in direct contact with the top surface410S of the substrate410), but it will be understood than the seed layer420may be stacked to be indirectly on the substrate410and isolated from direct contact with the top surface410S thereof. The substrate410may include, for example, Si, Ge, SiGe, a III-V-group compound semiconductor, or a 2D material. The seed layer420may include, for example, a 2D material. The seed layer420may include, for example, at least one of 1T-MoTe2, 1T-WTe2, 2H—MoTe2, 2H—WTe2, 1T-ZrS2, 1T-HfS2, 2H—ZrS2, 2H—HfS2, 2H—CrTe2, 2H—HfSe2, 1T-PdS2, 1T-PtS2, 2H—SnS2, 2H—TiSe2, 2H—VTe2, 2H—NbSe2, or GaS. Referring toFIG.14, a ferroelectric layer430may be deposited on the seed layer420(e.g., directly on the seed layer420such that the ferroelectric layer430is in direct contact with the top surface420S of the seed layer420), but it will be understood that the ferroelectric layer430may be stacked to be indirectly on the seed layer420and isolated from direct contact with the top surface420S thereof. A deposition method may include deposition layer deposition (ALD) or chemical vapor deposition (CVD). The ferroelectric layer430may be in an amorphous state (e.g., an amorphous material layer). When the seed layer420includes a 2D material and the ferroelectric layer430is deposited on the seed layer420, the ferroelectric layer430may be aligned within the range of ±30 degrees with respect to a direction in which the (111) crystal direction of the ferroelectric layer430is perpendicular to the substrate410(e.g., ±30 degrees with respect to the Z-direction). The ferroelectric layer430may be aligned within the range of ±20 degrees with respect to a direction in which the (111) crystal direction of the ferroelectric layer430is perpendicular to the substrate410(e.g., ±20 degrees with respect to the Z-direction). According to some example embodiments, the (111) crystal direction may be aligned even before the ferroelectric layer430is crystallized. Moreover, when the ferroelectric layer430is deposited on the seed layer420, the ferroelectric layer430may also be crystallized by using pulsed laser deposition. Referring toFIG.15, an upper layer440may be deposited on the ferroelectric layer430(e.g., directly on the ferroelectric layer430such that the upper layer440is in direct contact with the top surface430S of the ferroelectric layer430), but it will be understood that the upper layer440may be stacked to be indirectly on the ferroelectric layer430and isolated from direct contact with the top surface430S thereof. The upper layer440may include a metal layer, a protective layer, or an electrode layer, for example. The upper layer440may be deposited by using ALD, CVD, or physical vapor deposition (PVD). Referring toFIG.16, a ferroelectric layer430A may be crystallized through an annealing process, for example based on annealing a structure shown inFIG.15, to form an electronic device400as shown inFIG.16. Such annealing may be implemented based on a heat source generating heat that is applied to at least the ferroelectric layer430to implement annealing of at least the amorphous material of the ferroelectric layer430to thus cause the crystallizing. Restated, the ferroelectric layer430may be crystallized to form the ferroelectric layer430A through an annealing process. The ferroelectric layer430A may be crystallized so that a polarization value of the ferroelectric layer430A may be increased. In addition, in a structure in which the crystal direction of the ferroelectric layer430A is aligned, a threshold shift or memory window may be greater than a structure in which the crystal direction is random. In addition, when the crystal direction of the ferroelectric layer430A is aligned in a logic application device, uniformity may be enhanced compared to a case where the crystal direction is random, and thus operational performance and/or efficiency (e.g., improved power consumption efficiency and/or reduced power consumption) of a logic application device that includes at least the ferroelectric layer430A may be improved. In some example embodiments, the annealing may be performed on the structure shown inFIG.14, prior to forming the upper layer440as shown inFIG.15, so that the ferroelectric layer430is annealed to form the ferroelectric layer430A through crystallization of the material of the ferroelectric layer430. The upper layer440may be subsequently formed on the ferroelectric layer430A, or a structure that includes the ferroelectric layer430A may omit the upper layer440such that the upper layer440is not formed on the ferroelectric layer430A. Moreover, the method of manufacturing an electronic device according to some example embodiments may further include removing the substrate410from the seed layer420(e.g., detaching a structure that includes at least the ferroelectric layer430,430A, etc.) from the substrate410). After the substrate410is removed, the other structure may be transferred onto another structure layer. The electronic device according to some example embodiments may decrease the operating voltage while reducing the size by using a seed layer including a 2D material, and therefore the operational performance of the electronic device may be improved. In the method of manufacturing an electronic device according to some example embodiments, a ferroelectric layer may be crystallized by using the seed layer including a 2D material. It will be understood that the electronic devices100,200, and300may be formed (e.g., manufactured) via a method that is similar to the method shown inFIGS.13-16. For example, with regard to the electronic device300shown inFIG.12, a method for manufacturing the electronic device300may include providing a substrate310that is as described above with reference toFIG.12. In addition, the method for manufacturing the electronic device300may include forming a seed layer330on the channel layer region320of the substrate310via a method similar or the same as the process for forming the seed layer420as described above with reference toFIG.13. The seed layer330may be formed directly on the channel layer region320(e.g., directly on the portion of the top surface310S of the substrate310that defines a top surface of the channel layer region320). In addition, the method for manufacturing the electronic device300may include forming a ferroelectric layer340on the seed layer330via a method similar or the same as the process for forming the ferroelectric layer430and/or ferroelectric layer430A as described above with reference toFIGS.14-16. In addition, the method for manufacturing the electronic device300may include forming an upper layer350on the ferroelectric layer340via a method similar or the same as the process for forming the upper layer440as described above with reference toFIGS.15-16. FIG.17shows a schematic of a system1301configured to control the formation (also referred to herein interchangeably as “fabrication” or “manufacturing”) of an electronic device according to some example embodiments. As used herein, a system1301may be referred to as a “set.” Referring toFIG.17, system1301includes a computing device3010(also referred to herein interchangeably as an electronic device), a manipulator device3040, composition (e.g., gas, fluid, etc.) sources3030-1to3030-N (where N is a positive integer), a heat source3060, and a process chamber3020. Referring first to the computing device3010, the computing device3010may include processing circuitry3012(also referred to herein as simply a processor), memory3014, a power supply3015, and a communication interface3016that are communicatively and/or electrically coupled together via a bus3011. The computing device3010may be included in one or more various electronic devices, including, for example, a mobile phone, a digital camera, a sensor device, or the like. In some example embodiments, the computing device3010may include one or more of a server, a mobile device, a personal computer (PC), a tablet computer, a laptop computer, a netbook, some combination thereof, or the like. A mobile device may include a mobile phone, a smartphone, a personal digital assistant (PDA), some combination thereof, or the like. The computing device3010may be referred to herein as simply “processing circuitry.” The memory3014, the processing circuitry3012, the power supply3015, and the communication interface3016may communicate with one another through the bus3011. The communication interface3016may communicate data to and/or from an external device using various communication protocols. In some example embodiments, the communication interface may be connected to an electronic line (e.g., wire) and may be configured to receive and process electrical signals from one or more external devices. The processing circuitry3012may execute a program and control one or more aspects of the system1301, via the communication interface3016as shown inFIG.17. A program code to be executed by the processing circuitry3012may be stored in the memory3014. The memory3014may store information. The memory3014may be a volatile or a nonvolatile memory. The memory3014may be a non-transitory computer readable storage medium. The memory may store computer-readable instructions that, when executed, cause the execution of one or more methods, functions, processes, etc. as described herein. In some example embodiments, the processing circuitry3012may execute one or more of the computer-readable instructions stored at the memory3014to cause the system1301to perform some of all of the methods described herein, including the method illustrated inFIGS.13-16and/orFIG.20, and/or any method for forming (e.g., “fabricating,” “manufacturing,” etc.) any electronic devices according to any of the example embodiments. In some example embodiments, the communication interface3016may include a USB and/or HDMI interface. In some example embodiments, the communication interface3016may include a wireless communication interface. Still referring toFIG.17, the process chamber3020may be any of the process chambers described herein and may include a pedestal and/or chuck3022that is configured to structurally support a substrate3050upon which an electronic device4000(which may be any of the example embodiments of electronic devices according to any of the example embodiments described herein) according to any of the example embodiments may be formed (e.g., “fabricated,” “manufactured,” etc.). In some example embodiments, the substrate3050may be at least a portion of a substrate, first electrode, or the like that is at least partially included in the electronic device4000according to any example embodiments (e.g., substrate110, substrate210, substrate310, substrate410, or the like). As shown, the pedestal and/or chuck3022may be coupled to a motor such that the electronic device3010(e.g., “processing circuitry”) may be configured to cause the pedestal and/or chuck3022to move, via control signals communicated from communication interface3016, for example to enable the substrate3050and/or electronic device4000to be moved within, into, and/or out of the process chamber3020. Still referring toFIG.17, system1301includes a manipulator device3040, which may be any device for manipulating thin-film structures and/or substrates into and/or out of a process chamber3020, and the process chamber3020may include a portal3021(e.g., door) via which the manipulator device3040may access the interior of the process chamber3020to provide a substrate3050and/or to retrieve at least an electronic device4000formed therein. As shown, the manipulator device3040and the portal3021may be controlled by the electronic device3010(e.g., “processing circuitry”). Still referring toFIG.17, the system1301includes one or more composition sources3030-1to3030-N (N being a positive integer) which may store various materials, including any materials, dopants, and/or compositions described herein, or any combination thereof, as described herein. The materials may be stored as a gas, as a liquid, as a solid, as any type of fluid, or any combination thereof. As shown, each separate composition source is coupled to the process chamber3020via a separate supply control device3032-1to3032-N (e.g., control valve), where each control device3032-1to3032-N is configured (e.g., based on being a control valve) to control a supply of a separate material held in a separate (e.g., corresponding) coupled composition source3030-1to3030-N to the process chamber. The composition sources3030-1to3030-N and/or control devices3032-1to3032-N may be controlled by electronic device3010(e.g., “processing circuitry”). Still referring toFIG.17, system1301includes a heat source3060, which may be a heating device, heating element, heater, or the like that may be utilized to generate heat and provide the generated heat to the process chamber3020(e.g., to heat at least a portion of the process chamber3020), for example implement annealing of a structure that includes a ferroelectric layer as described herein. As shown, the heat source3060may be controlled by the electronic device3010(e.g., “processing circuitry”). As shown inFIG.17, the electronic device3010(e.g., “processing circuitry”) may, for example based on processing circuitry3012executing a program of instruction stored on memory3014, communicate with various elements of the system1301via communication lines3018to cause the system1301to form an electronic device4000according to any example embodiments herein (e.g., form any of the electronic devices100,200,300,400as described herein with regard to any example embodiments, including any of the methods described herein with reference toFIGS.13-16). It will be understood that the system1301may omit one or more of the elements shown inFIG.17(e.g., the heat source3060, the pedestal or chuck3022, or the like). FIG.18shows a schematic of an electronic device according to some example embodiments. As shown, the electronic device1400includes one or more electronic device components, including a processor (e.g., processing circuitry)1420and a memory1430that are communicatively coupled together via a bus1410. The electronic device1400may be referred to herein as a “computing device.” The processing circuitry1420, may be included in, may include, and/or may be implemented by one or more instances of processing circuitry such as hardware including logic circuits, a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry1420may include, but is not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphic processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC) a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), etc. In some example embodiments, the memory1430may include a non-transitory computer readable storage device, for example a solid state drive (SSD), storing a program of instructions, and the processing circuitry1420may be configured to execute the program of instructions to implement the functionality of the electronic device1400. In some example embodiments, the electronic device1400(e.g., “computing device”) may include an electronic device (e.g., logic transistor) according to any of the example embodiments in one or more of the processing circuitry1420or the memory1430, where said electronic device includes at least a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer, where the ferroelectric layer is configured to be aligned within a range of ±30 degrees with respect to a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer. The electronic device1400(e.g., “computing device”) may exhibit improved operational performance as a result, e.g., based on one or more portions of the electronic device1400(e.g., the processing circuitry1420and/or memory1430) having improved characteristics. FIG.19shows a schematic of a system1500configured to control the formation of an electronic device (e.g., “computing device”) according to some example embodiments, andFIG.20is a flowchart illustrating a method implemented by the system1500to manufacture an electronic device (e.g., “computing device”) according to some example embodiments. As shown, the system1500may include system1301, which is configured to form one or more electronic devices4000according to any of the example embodiments of the inventive concepts (S1602), including forming one or more electronic device4000that include electronic device400according to the method shown inFIGS.13-16. In some example embodiments, where the one or more electronic devices formed at S1602are configured to be incorporated into a separate electronic device (e.g., “computing device”, such as electronic device1400), the one or more electronic devices formed at S1602may be referred to as “sub-devices.” For example, an electronic device4000formed based on system1301implementing a method for forming an electronic device (e.g., the method as shown inFIGS.13-16) may be a device that is configured to be incorporated into an electronic device that is a computing device (e.g., electronic device1400as shown inFIG.18). The system1500further includes a fabrication assembly1504that is configured to incorporate the electronic device(s) formed by system1301(e.g., electronic device400) with various electronic device (e.g., “computing device”) sub-components1502(where the sub-components1502may include printed circuit boards, power supplies, buses, communication interface components, processing circuitry components, memory components, any combination thereof, or the like). The fabrication assembly1504may incorporate the electronic device(s)4000that are sub-device(s) with the sub-components1502(S1604), to fabricate (“manufacture”) electronic device (e.g., “computing device”) components (e.g., processing circuitries1420, memories1430, any combination thereof, or the like) and/or electronic devices (e.g., “computing device”) themselves, to manufacture (“fabricate”) separate electronic device(s)1400(e.g., “computing devices”) that include one or more electronic devices (e.g., electronic devices100,200,300, and/or400) according to any example embodiments of the inventive concepts (S1606). Such incorporation (S1604) and manufacturing (S1606) may include, for example, assembling an electronic device (e.g., “computing device”) component (e.g., processing circuitry1420and/or memory1430based on incorporating said electronic devices to additional electronic device sub-components, etc.) based on coupling the electronic device(s)4000to one or more electronic device sub-components and coupling the electronic device component to other electronic device components (e.g., printed circuit board, or PCB) to manufacture the electronic device (e.g.,1400). It should be understood that some example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in some example embodiments. While some example embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. | 48,564 |
11862706 | DETAILED DESCRIPTION It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc., as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm. Metal gate stacks, which are commonplace in modern-day transistors, may be formed using a gate-first process or a gate-last process. In the former, the functional metal gate stack is formed before formation of several features, such as source/drain features and an interlayer dielectric layer. In the latter, a non-functional dummy gate stack is first formed as a placeholder for a later-formed metal gate stack to undergo fabrication processes for the source/drain feature and the interlayer and then the dummy gate stack is removed and replaced with the functional metal gate stack. To replace the dummy gate stack, the dummy gate stack is first removed to form a gate trench and then a plurality of layers is deposited in the gate trench to form the functional metal gate stack. In some instances, one or more dipole layers may be deposited over the gate dielectric layer to provide transistors with different threshold voltages. An interface dipole may be created at the interface between a dipole layer and an underlying silicon oxide interfacial layer due to oxygen atom density differential. Depending on the polarity of the interface dipole, the interface dipole may increase or reduce the threshold voltage of the subject transistor. While a dipole layer may be used to modulate the threshold voltage, an additional dipole layer may further reduce the process windows for satisfactorily depositing the plurality of layers in the functional metal gate stack. In cases where the gate trench is not straight, the process window may be further reduced. For example, before deposition of all the plurality of layers in the gate trench to form the functional metal gate stack, two sides of a layer may merge and close the opening of the trench, preventing deposition of subsequent layers in the gate trench. To alleviate the foregoing problems, the present disclosure provides a method of forming a semiconductor device. In some embodiments of the present disclosure, the method includes depositing a gate dielectric layer over gate trenches in a first device region, a second device region, and a third device region on a workpiece. A first dipole layer is then deposited over the gate dielectric layer in gate trenches in a first device region, a second device region, and a third device region. The first dipole layer over the gate trench in the second device region is selectively removed while the gate dielectric layer in the first device region and the third device region remain covered by the first dipole layer. A second dipole layer is then deposited over the first dipole layer in the gate trenches in the first device region and the third device region, as well as the gate dielectric layer in the second device region. The first dipole layer and the second dipole layer are then removed from over the gate dielectric layer in the third device region. The workpiece is then annealed at a temperature between about 500° C. and about 900° C. such that ingredients in the first dipole layer and the second dipole layer may thermally diffuse into the gate dielectric layer to alter threshold voltages. After the first dipole layer and the second dipole layer are then removed from the gate trenches of the workpiece, a substantially identical gate structure is formed in the gate trenches in the first device region, the second device region, and the third device region to form a first transistor in the first device region, a second transistor in the second device region, and a third transistor in the third device region. The first transistor in the first device region, the second transistor in the second device region, and the third transistor in the third device region have different threshold voltages. Because the dipole layers are not included in the gate trenches and only serve as vehicles for diffusive dopants, the process window for forming the functional metal gate stack is not reduced. Embodiments having four device regions are also provided. FIG.1illustrates a flow chart of a method100for forming a semiconductor device according to various aspects of the present disclosure.FIGS.2-15are fragmentary cross-sectional views of a workpiece at various stages of fabrication of the method100inFIG.1. Additional steps can be provided before, during, and after method100, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method100. Additional features can be added in the contact structure depicted inFIGS.2-15, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the interconnect structure depicted inFIGS.2-15. Referring toFIGS.1and2, the method100includes a block102where a workpiece200is received. Upon conclusion of the method100, the workpiece200may be fabricated into a semiconductor device200. In that sense, the workpiece200may also be referred to as a semiconductor device200in suitable context. The semiconductor device200can be included in a microprocessor, a memory, and/or other IC device. In some implementations, the semiconductor device200is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The transistors may be planar transistors or multi-gate transistors, such as fin-like FETs (FinFETs) or gate-all-around (GAA) transistors. As illustrated inFIG.2, the semiconductor device200includes a substrate (wafer)202. In the depicted embodiment, substrate202includes silicon. Alternatively or additionally, substrate202includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some implementations, substrate202includes one or more group III-V materials, one or more group II-IV materials, or combinations thereof. In some implementations, substrate202is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. Substrate202can include various doped regions (not shown) configured according to design requirements of semiconductor device200, such as p-type doped regions, n-type doped regions, or combinations thereof. P-type doped regions (for example, p-type wells) include p-type dopants, such as boron, indium, other p-type dopant, or combinations thereof. N-type doped regions (for example, n-type wells) include n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. In some implementations, substrate202includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions can be formed directly on and/or in substrate202, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and/or other suitable doping process can be performed to form the various doped regions. Semiconductor device200includes an active region204over substrate202. The active region204may be a fin-shape semiconductor feature, or a vertical stack of nanostructures. As shown inFIG.2, the active region204horizontally extends along the X-direction over the substrate202and extends vertically along the Z-direction from the substrate202. In some implementations, the active region204may be a portion of substrate202(such as a portion of a material layer of substrate202). For example, silicon active region204may be formed from silicon substrate202. Alternatively, in some implementations, the active region204is defined in a material layer, such as one or more semiconductor material layers formed over substrate202. For example, the active region204can include a semiconductor layer stack having various semiconductor layers (such as a heterostructure) disposed over substrate202. The semiconductor layers can include any suitable semiconductor materials, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers can include same or different materials, etching rates, constituent atomic percentages, constituent weight percentages, thicknesses, and/or configurations depending on design requirements of the semiconductor device200. In some implementations, the semiconductor layer stack includes alternating semiconductor layers, such as semiconductor layers composed of a first material and semiconductor layers composed of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (for example, SiGe/Si/SiGe/Si/SiGe/Si from bottom to top). In some implementations, the semiconductor layer stack includes semiconductor layers of the same material but with alternating constituent atomic percentages, such as semiconductor layers having a constituent of a first atomic percent and semiconductor layers having the constituent of a second atomic percent. For example, the semiconductor layer stack includes silicon germanium layers having alternating silicon and/or germanium atomic percentages (for example, SiaGeb/SicGed/SiaGeb/SicGed/SiaGeb/SicGedfrom bottom to top, where a, c are different atomic percentages of silicon and b, d are different atomic percentages of germanium). The active region204may be formed over substrate202by any suitable process. In some implementations, a combination of deposition, lithography and/or etching processes are performed to define the active region204illustrated inFIG.2. For example, forming the active region204includes performing a lithography process to form a patterned resist layer over substrate202(or a material layer, such as a heterostructure, disposed over substrate202) and performing an etching process to transfer a pattern defined in the patterned resist layer to substrate202(or the material layer, such as the heterostructure, disposed over substrate202). The lithography process can include forming a resist layer on substrate202(for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. The etching process uses the patterned resist layer as an etch mask to remove portions of substrate202(or a material layer disposed over substrate202). The etching process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, other suitable etching process, or combinations thereof. After the etching process, the patterned resist layer is removed from substrate202, for example, by a resist stripping process. Alternatively, the active region204is formed by a multiple patterning process, such as a double patterning lithography (DPL) process (for example, a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning process, or combinations thereof), a triple patterning process (for example, a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning process, or combinations thereof), other multiple patterning process (for example, self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some implementations, directed self-assembly (DSA) techniques are implemented while forming the active region204. Further, in some implementations, the exposure process can implement maskless lithography, electron-beam (e-beam) writing, ion-beam writing, and/or nanoimprint technology for patterning the resist layer and/or other layers. An isolation feature (not shown) is formed over and/or in substrate202to isolate various regions, such as various device regions, of the semiconductor device200. For example, the isolation feature separates and isolates the active region204from an adjacent active region. In some embodiment, the isolation feature may surround a bottom portion of the active region204and expose a top portion of the active region204. The isolation feature may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. The isolation feature can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. In some implementations, STI features can be formed by etching a trench in substrate202(for example, by using a dry etch process and/or wet etch process) and filling the trench with insulator material (for example, by using a chemical vapor deposition process or a spin-on glass process). A chemical mechanical polishing (CMP) process may be performed to remove excessive insulator material and/or planarize a top surface of isolation feature. In some implementations, STI features can be formed by depositing an insulator material over substrate202after forming the active region204(in some implementations, such that the insulator material layer fills gaps (trenches) between the active region204and an adjacent active region) and etching back the insulator material layer to form isolation feature. In some implementations, the isolation feature includes a multi-layer structure that fills trenches, such as a bulk dielectric layer disposed over a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements (for example, a bulk dielectric layer that includes silicon nitride disposed over a liner dielectric layer that includes thermal oxide). In embodiments illustrated inFIG.2, the workpiece200includes a dummy gate stack208over and around a channel region10in the active region204. Each of the dummy gate stack208may include a dummy gate dielectric layer205and a dummy gate electrode207. In the embodiments represented inFIG.2, the dummy gate stack208includes a dummy gate dielectric layer205over the active region204and a dummy gate electrode207over the dummy gate dielectric layer205. In some implementations, the dummy gate dielectric layer205may be formed of silicon oxide and the dummy gate electrode207may be formed of polysilicon. A gate spacer layer210may be formed along sidewalls of the dummy gate stack208by any suitable process and include a dielectric material. The dielectric material for the gate spacer layer210may include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some implementations, the gate spacer layer210may include a multi-layer structure, such as a first spacer layer that includes silicon nitride and a second spacer layer that includes silicon oxide. In some implementations, the gate spacer layer210may include more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, formed adjacent to the gate stacks. It is noted that the cross-sectional view inFIG.2depicts a cross section that cut across a top surface of the active region204along the X-direction. For example, when the active region204is a fin-shape active region (or a fin), the dummy gate stack208inFIG.2are shown to be disposed on a top surface of the fin. The workpiece200may further include source/drain features212formed in source/drain regions20adjacent the channel region10. As shown inFIG.2, the source/drain features212are disposed adjacent the dummy gate stack208. In some implementations, source/drain features212are formed over source/drain regions20of the active region204using an epitaxy process. The epitaxy process can implement CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. Source/drain features212may be doped with n-type dopants and/or p-type dopants. In some implementations, where the transistor is configured as an n-type device (for example, having an n-channel), source/drain features212can be silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers doped with phosphorus, other n-type dopant, or combinations thereof (for example, forming Si:P epitaxial layers or Si:C:P epitaxial layers). In some implementations, where the transistor is configured as a p-type device (for example, having a p-channel), source/drain features212can be silicon-and-germanium-containing epitaxial layers doped with boron, other p-type dopant, or combinations thereof (for example, forming Si:Ge:B epitaxial layers). In some implementations, annealing processes are performed to activate dopants in source/drain features212of the semiconductor device200. The workpiece200may include a contact etch stop layer (CESL)214deposited on the source/drain features212. In some instances, the CESL214may also be deposited over the side surfaces of the gate spacer layer210. In some embodiments, the CESL214may be formed of silicon nitride, silicon oxynitride, or silicon carbonitride and may be conformally deposited using atomic layer deposition (ALD). A dielectric layer216, which may also be referred to as an interlayer dielectric (ILD) layer216, is deposited over the CESL214. The dielectric layer216may be formed using a flowable chemical vapor deposition (FCVD) process. In some implementations, after deposition using a FCVD process, the deposited dielectric layer216may be cured by incidence of ultraviolet (UV) radiation, annealing, or both. In some embodiments, the dielectric layer216may include a dielectric material including, for example, silicon oxide, TEOS formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric material, or combinations thereof. Referring toFIGS.1and3, the method100includes a block104where the dummy gate stack208is removed to form a gate trench218. In some embodiments, the dummy gate stack208may be removed using a combination of suitable dry etch processes and wet etch processes to form the gate trench218. The gate trench218exposes the channel region10of the active region204. While the dummy gate stack208and the gate trench218are depicted as having straight sidewalls along the Z direction, they may not be straight and may include a necking profile in some implementations. The necking profile may reduce the process window to deposit a plurality of layers in the gate trench218to form the functional metal gate stack. Referring toFIGS.1and4, the method100includes a block106where an interfacial layer220is deposited in the gate trench218. In some implementations, the interfacial layer220may be formed of silicon oxide. Referring toFIGS.1and5, the method100includes a block108where a gate dielectric layer222is deposited over the interfacial layer220. The gate dielectric layer222may include dielectric materials having a high dielectric constant, for example, greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable constituent, or combinations thereof. In some implementations, the gate dielectric layer222may include includes a high-k dielectric material including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, other suitable high-k dielectric material, or combinations thereof. As will be described below, the workpiece200may include multiple device regions (such as three device regions, four device regions, or more device regions) for transistors having different threshold voltages and the structure shown inFIGS.2-5may be repeated across these multiple device regions but the repeated structures are omitted, which is representatively shown by ellipses (“ . . . ”) inFIGS.2-5. Operations of the method100that treat different device regions differently will be described below in conjunction withFIGS.6-15. For simplicity and clarity of descriptions,FIGS.6-14illustrate fragmentary cross-sectional views of area “I” in different device regions. Referring toFIGS.1and6, the method100includes a block110where a first dipole layer224is deposited over the gate dielectric layer222. In the embodiments illustrated inFIGS.6-15, the workpiece200includes three device regions—a first device region1100, a second device region1200, and a third device region1300. As described above,FIG.6illustrates the fragmentary cross-sectional views of the area “I” in the first device region1100, the second device region1200, and the third device region1300. The first dipole layer224is deposited on the gate dielectric layer222in the gate trenches in the first device region1100, the second device region1200, and the third device region1300. In some embodiments, the first dipole layer224may be formed of lanthanum oxide, yttrium oxide, or aluminum oxide and may be deposited using atomic layer deposition (ALD). In some implementations, the ALD process used to form the first dipole layer224may include between about 2 and about 10 cycles. In those implementations, the first dipole layer224may have a thickness between about 1 Å and about 10 Å. In one embodiment, the first dipole layer224may be formed of lanthanum oxide. Referring toFIGS.1,7,8, and9, the method100includes a block112where the first dipole layer224is selectively removed from the second device region1200. In some embodiments, photolithography techniques and etch techniques may be used to perform the operations at block112. An example process is shown inFIGS.7-9. Reference is first made toFIG.7. A hard mask layer226is first formed over the first dipole layer224and a bottom antireflective coating (BARC) layer228is deposited over the hard mask layer226. In some instances, the hard mask layer226may be a single layer or a multi-layer. When the hard mask layer226is a single layer, the hard mask layer226may include silicon oxide, silicon nitride, or silicon oxynitride. When the hard mask layer226is a multi-layer, the hard mask layer226may include a silicon layer and a silicon nitride layer on the silicon layer. The BARC layer228may include silicon oxynitride, a polymer, or a suitable material. To pattern the BARC layer228and the hard mask layer226, a photoresist layer may be blanketly deposited over the workpiece200, including over the BARC layer228in the first device region1100, the second device region1200, and the third device region1300. The photoresist layer may be a single layer or a multi-layer, such as a tri-layer. The photoresist layer is then exposed to radiation going through or reflected from a mask, baked in a post-bake process, and developed in a developer solution to form a patterned photoresist mask. The BARC layer228and the hard mask layer226are then patterned using the patterned photoresist mask to form an etch mask having an opening over the second device region1200. The etch mask is then used in an etch process to selectively etch away the first dipole layer224in the gate trench in the second device region1200, as illustrated inFIG.8. The etch process may be a dry etch process, a wet etch process, or a suitable etch process. Referring toFIG.9, after the first dipole layer224is selectively removed from the gate trench in the second device region1200, the hard mask layer226and the BARC layer228in the first device region1100and the third device region1300are removed using a suitable etching process. Referring toFIGS.1and10, the method100includes a block114where a second dipole layer230is deposited over the workpiece200. As shown inFIG.10, the second dipole layer230is deposited on the first dipole layer224in the gate trenches in the first device region1100and the third device region1300as well as on the gate dielectric layer222in the gate trench in the second device region1200. In some embodiments, the second dipole layer230and the first dipole layer224may have the same composition. Similar to the first dipole layer224, the second dipole layer230may also be formed of lanthanum oxide, yttrium oxide, or aluminum oxide and may be deposited using atomic layer deposition (ALD). In some implementations, the ALD process used to form the second dipole layer230may include between about 2 and about 10 cycles. In those implementations, the second dipole layer230may have a thickness between about 1 Å and about 10 Å. In one embodiment, the second dipole layer230may be formed of lanthanum oxide. Referring toFIGS.1,11,12, and13, the method100includes a block116where the second dipole layer230is selectively removed from the third device region1300. Similar to operations at block112, operations at block116may also be performed using photolithography and etch techniques. For example, a hard mask layer232and a BARC layer234may be formed over the second dipole layer230, as shown inFIG.11. As the hard mask layer232may be similar to the hard mask layer226and the BARC layer234may be similar to the BARC layer228, detailed descriptions of the hard mask layer232and the BARC layer234are omitted for brevity. Thereafter a photoresist layer may then be deposited over the BARC layer234. The photoresist layer, the BARC layer234, and the hard mask layer232are then patterned in fashions similar to those described with respect to block112and will not be repeated here. The patterned hard mask layer232allows selective removal of the first dipole layer224and the second dipole layer230in the gate trench in the third device region1300, exposing the gate dielectric layer222in the gate trench in the third device region1300. As illustrated inFIG.12, at this point, the gate trench in the first device region1100includes thereover the first dipole layer224and the second dipole layer230; the gate trench in the second device region1200includes thereover the second dipole layer230; and the gate trench in the third device region1300is free of the first dipole layer224and the second dipole layer230. Put differently, the total thickness (along the Z direction) of the first dipole layer224and the second dipole layer230in the gate trench in the first device region1100is greater than the total thickness of the second dipole layer230in the gate trench in the second device region1200, while the gate trench in the third device region1300is free of any dipole layer. After the first dipole layer224and the second dipole layer230are selectively removed from the gate trench in the third device region1300, the hard mask layer232and the BARC layer234may then be removed from the first device region1100and the second device region1200, as illustrated inFIG.13. Referring toFIGS.1and13, the method100includes a block118where the workpiece200is annealed in an anneal process300. At block118, the anneal process300is used to thermally drive elements in the first dipole layer224and/or the second dipole layer230into the gate dielectric layer222in the gate trenches in the first device region1100and the second device region1200. The first dipole layer224and the second dipole layer230serve as a diffusion doping vehicle to bring its elements to be in direct contact with the gate dielectric layer222. The anneal process300may be a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. In some implementation, the anneal process300includes a high anneal temperature between about 500° C. and about 900° C. so as to allow lanthanum, yttrium, or aluminum in the first dipole layer224and/or the second dipole layer230to diffuse into the gate dielectric layer222in gate trenches in the first device region1100and the second device region1200. Because the gate trench in the third device region1300is free of any dipole layer, the anneal process300at block118does not result in any dipole layer material diffusing into the gate dielectric layer222in the third device region1300. In some implementations, the anneal process300may last between about 5 seconds and about 20 seconds. Referring toFIGS.1and14, the method100include a block120where the first dipole layer224and the second dipole layer230are removed from the workpiece200. After the element in the first dipole layer224and the second dipole layer230is thermally driven into the gate dielectric layer222at block118, the first dipole layer224and the second dipole layer230are removed from the gate trench in the first device region1100and the second dipole layer230is removed from the gate trench in the third device region1300. The operations at block120may be performed using a dry etch process, a wet etch process, or a suitable etch process. As shown inFIG.14, the anneal process300at block118results in a first gate dielectric layer2221in the gate trench in the first device region1100and a second gate dielectric layer2222in the gate trench in the second device region1200. Due to lack of any dipole layer, the gate dielectric layer222in the gate trench in the third device region1300remains substantially unchanged. It has also been observed that a thicker dipole layer contributes to a greater doping concentration of the dipole layer material in the gate dielectric layer222. For example, when the gate dielectric layer222is formed of hafnium oxide and the first dipole layer224/second dipole layer230is formed of lanthanum oxide, operations at block118may result in a first lanthanum concentration in the first gate dielectric layer2221in the first device region1100and a second lanthanum concentration in the second gate dielectric layer2222in the second device region1200. Because the gate trench in the third device region1300is free of any dipole layer, the gate dielectric layer222in the gate trench in the third device region1300includes a third lanthanum concentration that is zero. Because the gate trench in the first device region1100includes both the first dipole layer224and the second dipole layer230, the first lanthanum concentration is greater than the second lanthanum concentration, which is greater than the zero third lanthanum concentration. Each of the first, second and third lanthanum concentration may be represented as a ratio of lanthanum concentration (i.e., [lathanum] or [La] from the first dipole layer224/second dipole layer230) to hafnium (i.e., [Hafnium] or [Hf] in the gate dielectric layer222). In the example described above, the first lanthanum concentration (i.e., first lanthanum to hafnium ratio) may be about 0.4 ([La]/[Hf]) and the second lanthanum concentration (i.e., second lanthanum to hafnium ratio) may be about 0.2 ([La]/[Hf]), while the third lanthanum concentration (i.e., third lanthanum to hafnium ratio) is zero. The foregoing description generally applies to other dipole layer materials, such as yttrium and aluminum, and other gate dielectric material, such as HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, provided that different dipole layer material may have different diffusivity and different dipole layer may have different solid solubility in different gate dielectric layers. Referring toFIGS.1and15, the method100includes a block122where further processes are performed to form a first transistor410in the first device region1100, a second transistor420in the second device region1200, and a third transistor430in the third device region1300. As shown inFIG.15, the first transistor410includes the first gate dielectric layer2221, the second transistor420includes the second gate dielectric layer2222, and the third transistor430includes the gate dielectric layer222. Each of the first transistor410, the second transistor420, and the third transistor430includes a functional metal gate stack236in addition to the interfacial layer220and the first gate dielectric layer2221/second gate dielectric layer2222/gate dielectric layer222. Because the first gate dielectric layer2221in the first transistor410, the second gate dielectric layer2222in the second transistor420, and the gate dielectric layer222in the third transistor430are different only in composition but not in dimensions, the functional metal gate stack236is structurally and dimensionally uniform across the different device regions1100,1200, and1300. The functional metal gate stack236may include one or more work function layer and a metal fill layer. N-type devices and p-type devices may have different work functional layers. In some implementations, while n-type device regions and p-type device regions may share certain common work function layers, n-type device regions may include one or more work function layers that are not present in the p-type device regions. Similarly, in alternative implementations, p-type device regions may include one or more work function layers that are not present in the n-type device regions. P-type work function layer includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function material, or combinations thereof. N-type work function layer includes any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function material, or combinations thereof. It is noted that p-type work function layers are not limited to use in p-type device regions and n-type work function layers are not limited to use in n-type device regions. P-type work function layers and n-type work function layers may be applied in n-type device regions and p-type device regions to achieve desired threshold voltage. The metal fill layer may be deposited on n-type work function layer(s) and p-type work function layer(s), such that metal fill layer fills any remaining portion of gate trenches in different device regions. The metal fill layer may include a suitable conductive material, such as aluminum (Al), tungsten (W), ruthenium (Ru), and/or copper (Cu). The metal fill layer may additionally or collectively include other metals, metal nitrides, other suitable materials, or combinations thereof. The first transistor410in the first device region1100, the second transistor420in the second device region1200, and the third transistor430in the third device region have different threshold voltages due to different interface dipoles as a result of use of the first gate dielectric layer2221, the second gate dielectric layer2222, and the gate dielectric layer222. Different metal oxides have different areal density of oxygen atoms. For example, areal densities of oxygen atoms in lanthanum oxide and yttrium oxide are greater than that of silicon oxide while areal densities of oxygen atoms in aluminum oxide and hafnium oxide are greater than that of the silicon oxide. Out of these metal oxides, aluminum oxide has the highest areal density of oxygen atoms. In embodiments where the gate dielectric layer222consists essentially of hafnium oxide and the interfacial layer220consists essentially of silicon oxide, an interface dipole toward the gate dielectric layer222may be formed. When lanthanum or yttrium (having lower areal densities of oxygen atoms than silicon oxide) in the first dipole layer224and the second dipole layer230is allowed to diffuse into the gate dielectric layer222, the interface dipole toward the gate dielectric layer may be reduced or reversed. When aluminum (having higher areal densities of oxygen atoms than silicon oxide) in the first dipole layer224and the second dipole layer230is allowed to diffuse into the gate dielectric layer222, the interface dipole toward the gate dielectric layer may be increased. In one embodiment where the first gate dielectric layer2221has the first lanthanum concentration (i.e., first lanthanum to hafnium ratio) at about 0.4 ([La]/[Hf]), the second gate dielectric layer2222has the second lanthanum concentration (i.e., second lanthanum to hafnium ratio) at about 0.2 ([La]/[Hf]), and the gate dielectric layer222has the zero third lanthanum concentration (i.e., third lanthanum to hafnium ratio) at about 0 ([La]/[Hf]), the first transistor410has a first threshold voltage (Vt1), the second transistor420has a second threshold voltage (Vt2) and the third transistor430has a third threshold voltage (Vt3). When the first transistor410, the second transistor420, and the third transistor430are n-type transistors, Vt1 may be lower than Vt3 by about 150 mV and Vt2 may be lower than Vt3 by about 50 mV. When the first transistor410, the second transistor420and the third transistor430are p-type transistors, Vt1 may be greater than Vt3 by about 150 mV and Vt1 may be greater than Vt2 by about 50 mV. The first transistor410, the second transistor420, and the third transistor430may be implemented in a static random access memory (SRAM) cell to improve its signal-to-noise margin (SNM) and write margin (WM). For example, the first transistor410, the second transistor420, and the third transistor430may be implemented in an eight-transistor (8T) SRAM cell900shown inFIGS.29and30or a ten-transistor (10T) SRAM cell1000shown inFIGS.31and32. Reference is first made to a circuit diagram of the 8T SRAM cell900shown inFIG.29. The 8T SRAM cell900includes a first pull-up transistor (PU1)906and a first pull-down transistor (PD1)910forming a first inverter, a second pull-up transistor (PU2)908and a second pull-down transistor (PD2)912forming a second inverter cross-coupled with the first inverter, a first pass-gate transistor (PG1)902and a second pass-gate transistor (PG2)904configured to write data to be stored by the cross-coupled first and second inverters. The 8T SRAM cell900further includes a read pull-down transistor (RPD)914and a read pass-gate transistor (RPG)916forming a read port (RP)918to access data stored by the cross-coupled first and second inverters. Drain electrodes of the first pull-up transistor (PU1)906, the first pull-down transistor (PD1)910, and the first pass-gate transistor (PG1)902are electrically connected at a first data storage node Q. Drain electrodes of the second pull-up transistor (PU2)908, the second pull-down transistor (PD2)912, and the second pass-gate transistor (PG2)904are electrically connected at a second data storage node QB. Gate electrodes of the second pull-up transistor (PU2)908and the second pull-down transistor (PD2)912are electrically connected to the drain electrodes of the first pull-down transistor (PD1)910, the first pass-gate transistor (PG1)902, and the first pull-up transistor (PU1)906through the first data storage node Q, while gate electrodes of the first pull-up transistor (PU1)906and the first pull-down transistor (PD1)910are electrically connected to the drain electrodes of the second pull-down transistor (PD2)912, the second pass-gate transistor (PG2)904, and the second pull-up transistor (PU2)908through the second data storage node QB. Source electrodes of the first pull-down transistor (PD1)910, second pull-down transistors (PD2)912and the read pull-down transistor (RPD) are connected to a first power supply node Vss, while source electrodes of the first and second pull-up transistors (PU1)906and (PU2)908are connected to a second power supply node Vdd. According to one embodiment, the first power supply node Vss is electrically connected to a virtual ground920, and the second power supply node Vdd is electrically connected to a positive electrical potential, supplied from a power supply circuit (not shown) of the SRAM. In some implementations, the virtual ground920includes a hold transistor922and a power gate transistor924. The circuit diagram inFIG.29may be implemented in a layout of the 8T SRAM cell900shown inFIG.30. In some implementations, each of the first pass-gate transistor (PG1)902, the second pass-gate transistor (PG2)904, the first pull-down transistor (PD1)910, the second pull-down transistor (PD2)912, the read pull-down transistor (RPD)914, and the read pass-gate transistor (RPG)916includes a gate structure903disposed over two active regions905. Each of the first pull-up transistor (PU1)906and the second pull-up transistor (PU2)908includes a gate structure903(including a first gate structure903-1and a second gate structure903-2) disposed over a single active region905. In instances where the active regions are fin-shaped, the former may be referred to as double-fin devices and the latter may be referred to as single-fin devices. In an embodiment, the power gate transistor924may be a first transistor410. As the first transistor410has the highest threshold voltage (the first threshold voltage, Vt1) among the first transistor410, the second transistor420, and the third transistor430, it has the smallest leakage current and may reduce leakage at the power gate transistor924. In the same embodiment, the read port (RP)918may be formed of the third transistor430. As the third transistor430has the lowest threshold voltage (the third threshold voltage, Vt3) among the first transistor410, the second transistor420, and the third transistor430, it has the highest switching speed and may improve read speed of the 8T SRAM cell900. In the same embodiment, the second transistor420, which has the median threshold voltage level (the second threshold voltage Vt2), may be applied to each of the first pass-gate transistor (PG1)902, the second pass-gate transistor (PG2)904, the first pull-down transistor (PD1)910, and the second pull-down transistor (PD2)912to have balanced SNMs. As the first gate structure903-1is shared among the first pull-down transistor (PD1)910, the second pass-gate transistor (PG2)904, and the read pass-gate transistor (RPG)916, the first gate structure903-1is shared among two second transistors420(implemented as PD1and PG1) and one third transistor430(implemented as RPG). Similarly, as the second gate structure903-2is shared among the first pass-gate transistor (PG1)902, the second pull-down transistor (PD2)912, and the read pull-down transistor (RPD)914, the second gate structure903-2is shared among two second transistors420(implemented as PD2and PG2) and one third transistor430(implemented as RPD). As used herein, a gate structure is referred to as being shared by or multiple transistors as its functional metal gate stack extend over these transistors. Reference is made toFIG.15. While the first transistor410, the second transistor420, and the third transistor430have different gate dielectric layers, they may have a common functional metal gate stack236. The common functional metal gate stack236allows transistors of the present disclosure to be shared among more than one transistor. Reference is then made to a circuit diagram of the 10T SRAM cell1000shown inFIG.31. The 10T SRAM cell1000includes a first pull-up transistor (PU1)1006and a first pull-down transistor (PD1)1010forming a first inverter, a second pull-up transistor (PU2)1008and a second pull-down transistor (PD2)1012forming a second inverter cross-coupled with the first inverter, a first pass-gate transistor (PG1)1002and a second pass-gate transistor (PG2)1004configured to write data to be stored by the cross-coupled first and second inverters. The 10T SRAM cell1000further includes a first read port (RP1)1014and a second read port (RP)1016to access data stored by the cross-coupled first and second inverters. The first read port (RP)1014includes a first read pull-down transistor (RPD1)1018and a first read pass-gate transistor (RPG1)1020and the second read port (RP2)1016includes a second read pull-down transistor (RPD2)1022and a second read pass-gate transistor (RPG2)1024. Drain electrodes of the first pull-up transistor (PU1)1006, the first pull-down transistor (PD1)1010, and the first pass-gate transistor (PG1)1002are electrically connected at a first data storage node Q. Drain electrodes of the second pull-up transistor (PU2)1008, the second pull-down transistor (PD2)1012, and the second pass-gate transistor (PG2)1004are electrically connected at a second data storage node QB. Gate electrodes of the second pull-up transistor (PU2)1008and the second pull-down transistor (PD2)1012are electrically connected to the drain electrodes of the first pull-down transistor (PD1)1010, the first pass-gate transistor (PG1)1002, and the first pull-up transistor (PU1)1006through the first data storage node Q, while gate electrodes of the first pull-up transistor (PU1)1006and the first pull-down transistor (PD1)1010are electrically connected to the drain electrodes of the second pull-down transistor (PD2)1012, the second pass-gate transistor (PG2)1004, and the second pull-up transistor (PU2)1008through the second data storage node QB. Source electrodes of the first pull-down transistor (PD1)1010, the second pull-down transistor (PD2)1012, the first read pull-down transistor (RPD1)1018, and the second read pull-down transistor (RPD2)1022are connected to a first power supply node Vss, while source electrodes of the first and second pull-up transistors (PU1)1006and (PU2)1008are connected to a second power supply node Vdd. According to one embodiment, the first power supply node Vss is electrically connected to a virtual ground1026, and the second power supply node Vdd is electrically connected to a positive electrical potential, supplied from a power supply circuit (not shown) of the SRAM. In some implementations, the virtual ground1026includes a hold transistor1028and a power gate transistor1030. The circuit diagram inFIG.31may be implemented in a layout of the 10T SRAM cell1000shown inFIG.32. In some implementations, each of the first pass-gate transistor (PG1)1002, the second pass-gate transistor (PG2)1004, the first pull-down transistor (PD1)1010, the second pull-down transistor (PD2)1012, the first read pull-down transistor (RPD1)1018, the first read pass-gate transistor (RPG1)1020, the second read pull-down transistor (RPD2)1022, the second read pass-gate transistor (RPG2)1024includes a gate structure1003disposed over two active regions1005. Each of the first pull-up transistor (PU1)1006and the second pull-up transistor (PU2)1008includes a gate structure1003(including a first gate structure1003-1and a second gate structure1003-2) disposed over a single active region1005. In instances where the active regions are fin-shaped, the former may be referred to as double-fin devices and the latter may be referred to as single-fin devices. In an embodiment, the power gate transistor1030may be a first transistor410. As the first transistor410has the highest threshold voltage (the first threshold voltage, Vt1) among the first transistor410, the second transistor420, and the third transistor430, it has the smallest leakage current and may reduce leakage at the power gate transistor1030. In the same embodiment, the first read port (RP1)1014and the second read port (RP2)1016may be formed of the third transistor430. As the third transistor430has the lowest threshold voltage (the third threshold voltage, Vt3) among the first transistor410, the second transistor420, and the third transistor430, it has the highest switching speed and may improve read speed of the 10T SRAM cell1000. In the same embodiment, the second transistor420, which has the median threshold voltage level (the second threshold voltage Vt2), may be applied to each of the first pass-gate transistor (PG1)1002, the second pass-gate transistor (PG-2)1004, the first pull-down transistor (PD1)1010, and the second pull-down transistor (PD2)1012to have balanced SNMs. As the first gate structure1003-1is shared among first read pull-down transistor (RPD1)1018, the first pull-down transistor (PD1)1010, the second pass-gate transistor (PG2)1004, and the second read pass-gate transistor (RPG2)1024, the first gate structure1003-1is shared among two second transistors420(implemented as PD1and PG1) and two third transistors430(implemented as RPD1and RPG2). Similarly, as the second gate structure1003-2is shared among first read pass-gate transistor (RPG1)1020, the first pass-gate transistor (PG1)1002, the second pull-down transistor (PD2)1012, and the second read pull-down transistor (RPD2)1022, the second gate structure1003-2is shared among two second transistors420(implemented as PD2and PG2) and two third transistor430(implemented as RPG1and RPD2). As described above, a gate structure is referred to as being shared by or multiple transistors as its functional metal gate stack extend over these transistors. Reference is made toFIGS.28A and28B. While the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840have different gate dielectric layers, they may have a common functional metal gate stack236. The common functional metal gate stack236allows transistors of the present disclosure to be shared among more than one transistor. FIG.16illustrates a flow chart of a method500for forming a semiconductor device according to various aspects of the present disclosure.FIGS.2-5,17-27,28A and28Bare fragmentary cross-sectional views of a workpiece200at various stages of fabrication of the method500inFIG.16. Additional steps can be provided before, during, and after method500, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method500. Additional features can be added in the contact structure depicted inFIGS.2-5,17-27,28A and28B, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the interconnect structure depicted inFIGS.2-5,17-27,28A and28B. Referring toFIGS.16and2, the method500includes a block502where a workpiece200is received. As operations at block502are similar to those at block102described above, descriptions thereof will not be repeated. In addition, detailed descriptions of the workpiece200and various features thereon have been described above and are also omitted here for brevity. Referring toFIGS.16and3, the method500includes a block504where the dummy gate stack208is removed to form a gate trench218. As operations at block504are similar to those at block104described above, descriptions thereof will not be repeated. In addition, detailed descriptions of the dummy gate stack208and the gate trench218have been described above and are also omitted here for brevity. Referring toFIGS.16and4, the method500includes a block506where an interfacial layer220is deposited in the gate trench218. As operations at block506are similar to those at block106described above, descriptions thereof will not be repeated. In addition, detailed descriptions of the interfacial layer220have been described above and are also omitted here for brevity. Referring toFIGS.16and5, the method500includes a block508where a gate dielectric layer222is deposited over the interfacial layer220. As operations at block508are similar to those at block108described above, descriptions thereof will not be repeated. In addition, detailed descriptions of the gate dielectric layer222have been described above and are also omitted here for brevity. As will be described below, the workpiece200may include multiple device regions (such as three device regions, four device regions, or more device regions) for transistors having different threshold voltages and the structure shown inFIGS.2-5may be repeated across these multiple device regions but the repeated structures are omitted, which is representatively shown by ellipses (“ . . . ”) inFIGS.2-5. Operations of the method500that treat different device regions differently will be described below in conjunction withFIGS.17-27,28A and28B. For simplicity and clarity of descriptions,FIGS.17-27illustrate fragmentary cross-sectional views of area “I” in different device regions. Referring toFIGS.16and6, the method500includes a block510where a first dipole layer224is deposited over the gate dielectric layer222. In the embodiments illustrated inFIGS.17-27,28A and28B, the workpiece200includes four device regions—a first device region3100, a second device region3200, a third device region3300, and a fourth device region3400. As described above,FIG.17illustrates the fragmentary cross-sectional views of the area “I” in the first device region3100, the second device region3200, the third device region3300, and the fourth device region3400. The first dipole layer224is deposited on the gate dielectric layer222in the gate trenches in the first device region3100, the second device region3200, the third device region3300, and the fourth device region3400. In some embodiments, the first dipole layer224may be formed of lanthanum oxide, yttrium oxide, or aluminum oxide and may be deposited using atomic layer deposition (ALD). In some implementations, the ALD process used to form the first dipole layer224may include between about 2 and about 10 cycles. In those implementations, the first dipole layer224may have a thickness between about 1 Å and about 10 Å. In one embodiment, the first dipole layer224may be formed of lanthanum oxide. Referring toFIGS.16,18,19, and20, the method500includes a block512where the first dipole layer224is selectively removed from the third device region3300and the fourth device region3400. In some embodiments, photolithography techniques and etch techniques may be used to perform the operations at block512. An example process is shown inFIGS.18-20. Reference is first made toFIG.18. A hard mask layer226is first formed over the first dipole layer224and a bottom antireflective coating (BARC) layer228is deposited over the hard mask layer226. In some instances, the hard mask layer226may be a single layer or a multi-layer. When the hard mask layer226is a single layer, the hard mask layer226may include silicon oxide, silicon nitride, or silicon oxynitride. When the hard mask layer226is a multi-layer, the hard mask layer226may include a silicon layer and a silicon nitride layer on the silicon layer. The BARC layer228may include silicon oxynitride, a polymer, or a suitable material. To pattern the BARC layer228and the hard mask layer226, a photoresist layer may be blanketly deposited over the workpiece200, including over the BARC layer228in the first device region3100, the second device region3200, the third device region3300, and the fourth device region3400. The photoresist layer may be a single layer or a multi-layer, such as a tri-layer. The photoresist layer is then exposed to radiation going through or reflected from a mask, baked in a post-bake process, and developed in a developer solution to form a patterned photoresist mask. The BARC layer228and the hard mask layer226are then patterned using the patterned photoresist mask to form an etch mask having openings over the third device region3300and the fourth device region3400. The etch mask is then used in an etch process to selectively etch away the first dipole layer224in the gate trench in the third device region3300and the fourth device region3400, as illustrated inFIG.19. The etch process may be a dry etch process, a wet etch process, or a suitable etch process. Referring toFIG.20, after the first dipole layer224is selectively removed from the gate trench in the third device region3300and the fourth device region3400, the hard mask layer226and the BARC layer228in the first device region3100and the second device region3200are removed using a suitable etching process. Referring toFIGS.16and21, the method500includes a block514where a first anneal process600is performed to anneal the workpiece200. At block514, the first anneal process600is used to thermally drive elements in the first dipole layer224into the gate dielectric layer222in the gate trenches in the first device region3100and the second device region3200. The first dipole layer224serves as a diffusion doping vehicle to bring its elements to be in direct contact with the gate dielectric layer222in the first device region3100and the second device region3200. The first anneal process600may be a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. In some implementation, the first anneal process600includes a high anneal temperature between about 500° C. and about 900° C. so as to allow lanthanum, yttrium, or aluminum in the first dipole layer224to diffuse into the gate dielectric layer222in gate trenches in the first device region3100and the second device region3200. Because the gate trenches in the third device region3300and the fourth device region3400are free of the first dipole layer224, the first anneal process600at block514does not result in any dipole layer material diffusing into the gate dielectric layer222in the third device region3300and the fourth device region3400. In some implementations, the first anneal process600may last between about 5 seconds and about 20 seconds. As shown inFIG.22, after the first anneal process600at block514, elements in the first dipole layer224diffuse into the gate dielectric layers222to form the second gate dielectric layer2232in gate trenches in the first device region3100and the second device region3200. Referring toFIGS.16and22, the method500includes a block516where the first dipole layer224is selectively removed from the workpiece200. In some embodiments, photolithography and etch techniques may be used at block516to prevent damages to the gate dielectric layer222in the third device region3300and the fourth device region3400. For example, a hard mask layer, a BARC layer, and a photoresist layer may be deposited over the workpiece200. The photoresist layer, the BARC layer, and the hard mask layer are then patterned to form an etch mask that expose the first dipole layer224in the gate trenches in the first device region3100and the second device region3200. The first dipole layer224is then etched by a dry etch process, a wet etch process, or a suitable etch process using the etch mask. The etch mask, which is formed of the hard mask layer and the BARC layer, is then removed. At the conclusion of block516, the second gate dielectric layer2232in the gate trenches in the first device region3100and the second device region3200and the gate dielectric layer222in the gate trenches in the third device region3300and the fourth device region3400are exposed. Referring toFIGS.16and23, the method500includes a block518where a second dipole layer240is deposited over the workpiece200. As shown inFIG.23, the second dipole layer240is deposited on the second gate dielectric layer2232in the gate trenches in the first device region3100and the second device region3200as well as on the gate dielectric layer222in the gate trenches in the third device region3300and the fourth device region3400. In some embodiments, the second dipole layer240and the first dipole layer224may have the same composition. Similar to the first dipole layer224, the second dipole layer240may also be formed of lanthanum oxide, yttrium oxide, or aluminum oxide and may be deposited using atomic layer deposition (ALD). In some implementations, the ALD process used to form the second dipole layer240may include between about 2 and about 5 cycles. In those implementations, the second dipole layer240may have a thickness between about 1 Å and about 5 Å. In one embodiment, the second dipole layer240may be formed of lanthanum oxide. Different from the second dipole layer230in the embodiments illustrated inFIGS.2-15, the second dipole layer240in the embodiments illustrated inFIGS.17-27,28A and28Bare thinner. The second dipole layer240, with a thickness between about 1 Å and about 5 Å, is thinner than the first dipole layer224, which has a thickness between about 1 Å and about 10 Å. Referring toFIGS.16,24,25, and26, the method500includes a block520where the second dipole layer240is selectively removed from the gate trenches in the second device region3200and the fourth device region3400. Similar to operations at block112in method100, operations at block520may also be performed using photolithography and etch techniques. For example, a hard mask layer242and a BARC layer244may be formed over the second dipole layer240, as shown inFIG.24. As the hard mask layer242may be similar to the hard mask layer226and the BARC layer244may be similar to the BARC layer228, detailed descriptions of the hard mask layer242and the BARC layer244are omitted for brevity. Thereafter a photoresist layer may then be deposited over the BARC layer244. The photoresist layer, the BARC layer244, and the hard mask layer242are then patterned in fashions similar to those described with respect to block112of method100and will not be repeated here. The patterned hard mask layer242allows selective removal of the second dipole layer240in the gate trenches in the second device region3200and the fourth device region3400, exposing the second gate dielectric layer2232in the second device region3200and gate dielectric layer222in the fourth device region3400. As illustrated inFIG.25, at this point, the gate trench in the first device region3100includes thereover the second gate dielectric layer2232and the second dipole layer240; the gate trench in the second device region3200includes thereover the second gate dielectric layer2232; the gate trench in the third device region3300includes thereover the second dipole layer240; and the gate trench in the fourth device region3400includes the gate dielectric layer222uncovered by any dipole layer. After the second dipole layer240is selectively removed from the gate trenches in the second device region3200and the fourth device region3400, the hard mask layer242and the BARC layer244may then be removed from the first device region3100and the third device region3300, as illustrated inFIG.26. Referring toFIGS.16and26, the method500includes a block522where the workpiece200is annealed in a second anneal process700. At block522, the second anneal process700is used to thermally drive elements in the second dipole layer240into the second gate dielectric layer2232in the gate trench in the first device region3100and into the gate dielectric layer222in the gate trench in the third device region3300. The second dipole layer240serves as a diffusion doping vehicle to bring its elements to be in direct contact with the second gate dielectric layer2232and the gate dielectric layer222. The second anneal process700may be a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. In some implementation, the second anneal process700includes a high anneal temperature between about 500° C. and about 900° C. so as to allow lanthanum, yttrium, or aluminum in the second dipole layer240to diffuse into the second gate dielectric layer2232in gate trench in the first device region3100and into the gate dielectric layer222in the gate trench in the third device region3300. Because the gate trench in the fourth device region3400is free of any dipole layer, the second anneal process700at block522does not result in any dipole layer material diffusing into the gate dielectric layer222in the fourth device region3400. In some implementations, the second anneal process700may last between about 5 seconds and about 20 seconds. Referring toFIGS.16and27, the method500include a block524where the second dipole layer240are removed from the workpiece200. The operations at block524may be performed using a dry etch process, a wet etch process, or a suitable etch process. After the element in the second dipole layer240is thermally driven into the second gate dielectric layer2232in the first device region3100and gate dielectric layer222in the third device region3300. At block524, the second dipole layer240is removed from the gate trenches in the first device region3100and the third device region3300. Due to the second anneal process700at block522, a first gate dielectric layer2231is formed over the gate trench in the first device region3100and a third gate dielectric layer2233is formed over the gate trench in the third device region3300. To summarize, the first gate dielectric layer2231in the first device region3100is formed as a result of the first dipole layer224driven in by the first anneal process600and the second dipole layer240driven in by the second anneal process700; the second gate dielectric layer2232in the second device region3200is formed as a result of the first dipole layer224driven in by the first anneal process600; the third gate dielectric layer2233in the third device region3300is formed as a result of the second dipole layer240driven in by the second anneal process700, and the gate dielectric layer222in the fourth device region3400is free of diffusion elements from any dipole layer. It has also been observed that a thicker dipole layer and increased anneal processes contribute to a greater doping concentration of the dipole layer material in the gate dielectric layer222. For example, when the gate dielectric layer222is formed of hafnium oxide and the first dipole layer224/second dipole layer240is formed of lanthanum oxide, operations at block626may result in a first lanthanum concentration in the first gate dielectric layer2231in the first device region3100, a second lanthanum concentration in the second gate dielectric layer2232in the second device region3200, a third lanthanum concentration in the third device region3300, and a fourth lanthanum concentration in the fourth device region3400. The first lanthanum concentration is greater than the second lanthanum concentration, the second lanthanum concentration is greater than the third lanthanum concentration, and the third lanthanum concentration is greater than the fourth lanthanum concentration. Because the gate trench in the fourth device region3400is free of any dipole layer, the fourth lanthanum concentration that is zero. Each of the first, second, third, and fourth lanthanum concentrations may be represented as a ratio of lanthanum concentration (i.e., [lathanum] or [La] from the first dipole layer224/second dipole layer240) to hafnium (i.e., [Hafnium] or [Hf] in the gate dielectric layer222). In the example described above, the first lanthanum concentration (i.e., first lanthanum to hafnium ratio) may be about 0.6 ([La]/[Hf]), the second lanthanum concentration (i.e., second lanthanum to hafnium ratio) may be about 0.4 ([La]/[Hf]), and the third lanthanum concentration (i.e., third lanthanum to hafnium ratio) may be about 0.2 ([La]/[Hf]), while the fourth lanthanum concentration (i.e., fourth lanthanum to hafnium ratio) is zero. The foregoing description generally applies to other dipole layer materials, such as yttrium and aluminum, and other gate dielectric material, such as HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, provided that different dipole layer material may have different diffusivity and different dipole layer may have different solid solubility in different gate dielectric layers. Referring toFIGS.16,28A and28B, the method500includes a block526where further processes are performed to form a first transistor810in the first device region3100, a second transistor820in the second device region3200, a third transistor830in the third device region3300, and a fourth transistor840in the fourth device region3400. As shown inFIGS.28A and28B, the first transistor810includes the first gate dielectric layer2231, the second transistor820includes the second gate dielectric layer2232, the third transistor830includes the third gate dielectric layer2233, and the fourth transistor840includes the gate dielectric layer222. Each of the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840includes a functional metal gate stack236in addition to the interfacial layer220and the first gate dielectric layer2231/second gate dielectric layer2232/third gate dielectric layer2233/gate dielectric layer222. Because the first gate dielectric layer2231in the first transistor810, the second gate dielectric layer2232in the second transistor820, the third gate dielectric layer2233in the third transistor830, and the gate dielectric layer222in the fourth transistor840are different only in composition but not in dimensions, the functional metal gate stack236is structurally and dimensionally uniform across the different device regions3100,3200,3300, and3400. The functional metal gate stack236may include one or more work function layer and a metal fill layer. N-type devices and p-type devices may have different work functional layers. In some implementations, while n-type device regions and p-type device regions may share certain common work function layers, n-type device regions may include one or more work function layers that are not present in the p-type device regions. Similarly, in alternative implementations, p-type device regions may include one or more work function layers that are not present in the n-type device regions. P-type work function layer includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function material, or combinations thereof. N-type work function layer includes any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function material, or combinations thereof. It is noted that p-type work function layers are not limited to use in p-type device regions and n-type work function layers are not limited to use in n-type device regions. P-type work function layers and n-type work function layers may be applied in n-type device regions and p-type device regions to achieve desired threshold voltage. The metal fill layer may be deposited on n-type work function layer(s) and p-type work function layer(s), such that metal fill layer fills any remaining portion of gate trenches in different device regions. The metal fill layer may include a suitable conductive material, such as aluminum (Al), tungsten (W), ruthenium (Ru), and/or copper (Cu). The metal fill layer may additionally or collectively include other metals, metal nitrides, other suitable materials, or combinations thereof. The first transistor810in the first device region3100, the second transistor820in the second device region3200, the third transistor830in the third device region3300, and the fourth transistor840in the fourth device region3400have different threshold voltages due to different interface dipoles as a result of use of the first gate dielectric layer2231, the second gate dielectric layer2232, the third gate dielectric layer2233, and the gate dielectric layer222. Different metal oxides have different areal density of oxygen atoms. For example, areal densities of oxygen atoms in lanthanum oxide and yttrium oxide are greater than that of silicon oxide while areal densities of oxygen atoms in aluminum oxide and hafnium oxide are greater than that of the silicon oxide. Out of these metal oxides, aluminum oxide has the highest areal density of oxygen atoms. In embodiments where the gate dielectric layer222consists essentially of hafnium oxide and the interfacial layer220consists essentially of silicon oxide, an interface dipole toward the gate dielectric layer222may be formed. When lanthanum or yttrium (having lower areal densities of oxygen atoms than silicon oxide) in the first dipole layer224and the second dipole layer240is allowed to diffuse into the gate dielectric layer222, the interface dipole toward the gate dielectric layer may be reduced or reversed. When aluminum (having higher areal densities of oxygen atoms than silicon oxide) in the first dipole layer224and the second dipole layer240is allowed to diffuse into the gate dielectric layer222, the interface dipole toward the gate dielectric layer may be increased. In one embodiment where the first gate dielectric layer2231has the first lanthanum concentration (i.e., first lanthanum to hafnium ratio) at about 0.6 ([La]/[Hf]), the second gate dielectric layer2232has the second lanthanum concentration (i.e., second lanthanum to hafnium ratio) at about 0.4 ([La]/[Hf]), the third gate dielectric layer2233has the third lanthanum concentration (i.e., third lanthanum to hafnium ratio) at about 0.2 ([La]/[Hf]), and the gate dielectric layer222has the zero fourth lanthanum concentration (i.e., fourth lanthanum to hafnium ratio) at about 0 ([La]/[Hf]), the first transistor810has a first threshold voltage (Vt1), the second transistor820has a second threshold voltage (Vt2), the third transistor830has a third threshold voltage (Vt3), and the fourth transistor840has a fourth threshold voltage (Vt4). When the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840are n-type transistors, Vt1 may be lower than Vt4 by about 250 mV, Vt2 may be lower than Vt4 by about 150 mV, and Vt3 may be lower than Vt4 by about 50 mV. When the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840are p-type transistors, Vt1 may be greater than Vt4 by about 250 mV, Vt1 may be greater than Vt3 by about 150 mV, and Vt1 may be greater than Vt2 by about 50 mV. The first transistor810, the second transistor820, the third transistor830, and the fourth transistor840may be implemented in in a static random access memory (SRAM) cell to improve its signal-to-noise margin (SNM) and write margin (WM). For example, the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840may be implemented in the 8T SRAM cell900shown inFIGS.29and30or the 10T SRAM cell1000shown inFIGS.31and32. In some embodiments, the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840may be implemented in the 8T SRAM cell900shown inFIGS.29and30. In one example, the first transistor810, with the first threshold voltage Vt1, may be implemented as the first pass-gate transistor (PG1)902and the second pass-gate transistor (PG2)904; the second transistor820, with the second threshold voltage Vt2, may be implemented as the first pull-down transistor (PD1)910and the second pull-down transistor (PD2)912; the third transistor830, with the third threshold voltage Vt3, may be implemented as the read pass-gate transistor (RPG)916; and the fourth transistor840, with the fourth threshold voltage Vt4, may be implemented as the read pull-down transistor (RPD)914. In this example, because the third transistor830and the fourth transistor840have lower threshold voltages than the first transistor810and the second transistor820, the read port918may have faster read speed. Additionally, because transistors with greater threshold voltages have smaller leakage currents (i.e., drive currents), the leakage currents through the first pass-gate transistor (PG1)902and the second pass-gate transistor (PG2)904are smaller than those through the first pull-down transistor (PD1)910and the second pull-down transistor (PD2)912. This arrangement may allow the 8T SRAM cell900to have an increased beta ((3) ratio, which translates into increased read stability. In these embodiments, as the first gate structure903-1is shared among the first pull-down transistor (PD1)910, the second pass-gate transistor (PG2)904, and the read pass-gate transistor (RPG)916, the first gate structure903-1is shared among one first transistor810(implemented as PG2), one second transistor820(implemented as PD1), and one third transistor830(implemented as RPG). Similarly, as the second gate structure903-2is shared among the first pass-gate transistor (PG1)902, the second pull-down transistor (PD2)912, and the read pull-down transistor (RPD)914, the second gate structure903-2is shared among one first transistor810(implemented as PG1), one second transistor820(implemented as PD2) and one fourth transistor840(implemented as RPD). As described above, a gate structure is referred to as being shared by or multiple transistors as its functional metal gate stack extend over these transistors. Reference is made toFIGS.28A and28B. While the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840have different gate dielectric layers, they may have a common functional metal gate stack236. The common functional metal gate stack236allows transistors of the present disclosure to be shared among more than one transistor. In some other embodiments, the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840may be implemented in the 10T SRAM cell1000shown inFIGS.31and32. In one example, the first transistor810, with the first threshold voltage Vt1, may be implemented as the first pass-gate transistor (PG1)1002and the second pass-gate transistor (PG2)1004; the second transistor820, with the second threshold voltage Vt2, may be implemented as the first pull-down transistor (PD1)1010and the second pull-down transistor (PD2)1012; the third transistor830, with the third threshold voltage Vt3, may be implemented as the first read pass-gate transistor (RPG1)1020and the second read pass-gate transistor (RPG2)1024; and the fourth transistor840, with the fourth threshold voltage Vt4, may be implemented as the first read pull-down transistor (RPD1)1018and the second read pull-down transistor (RPD2)1022. In this example, because the third transistor830and the fourth transistor840have lower threshold voltages than the first transistor810and the second transistor820, the first read port1014and the second read port1016may have faster read speeds. Additionally, because transistors with greater threshold voltages have smaller leakage currents (i.e., drive currents), the leakage currents through the first pass-gate transistor (PG1)1002and the second pass-gate transistor (PG2)1004are smaller than those through the first pull-down transistor (PD1)1010and the second pull-down transistor (PD2)1012. This arrangement may allow the 10T SRAM cell1000to have an increased beta (β) ratio, which translates into increased read stability. In these other embodiments, as the first gate structure1003-1is shared among first read pull-down transistor (RPD1)1018, the first pull-down transistor (PD1)1010, the second pass-gate transistor (PG2)1004, and the second read pass-gate transistor (RPG2)1024, the first gate structure1003-1is shared among one first transistor810(implemented as PG2), one second transistor820(implemented as PD1), one third transistor830(implemented as RPG2), and one fourth transistor840(implemented as RPD1). Similarly, as the second gate structure1003-2is shared among first read pass-gate transistor (RPG1)1020, the first pass-gate transistor (PG1)1002, the second pull-down transistor (PD2)1012, and the second read pull-down transistor (RPD2)1022, the second gate structure1003-2is shared among one first transistor810(implemented as PG1), one second transistor820(implemented as PD2), one third transistor830(implemented as RPG1), and one fourth transistor840(implemented as RPD2). As described above, a gate structure is referred to as being shared by or multiple transistors as its functional metal gate stack extend over these transistors. Reference is made toFIGS.28A and28B. While the first transistor810, the second transistor820, the third transistor830, and the fourth transistor840have different gate dielectric layers, they may have a common functional metal gate stack236. The common functional metal gate stack236allows transistors of the present disclosure to be shared among more than one transistor. Throughout the present disclosure, similar reference numerals may be used for similar features with similar compositions, provided that multiple device regions and features thereon may be renumbered for different embodiments. For example, the three device regions inFIG.6are the first device region1100, the second device region1200, and the third device region1300while the fourth device regions inFIG.17are the first device region3100, the second device region3200, the third device region3300, and the fourth device region3400. The same numbering convention applies to the gate dielectric layers (e.g.,222,2221,2222inFIGS.15and222,2231,2232, and2233inFIGS.28A and28B), transistors (e.g.,410,420, and430inFIGS.15and810,820,830, and840inFIGS.28A and28B). In addition, while the first dipole layer224may be similar with respect to both methods100and500, the second dipole layer230in method100and the second dipole layer240in method500may not be similar. For that reason, they are referred to by different reference numerals. Furthermore, the interfacial layer220, the gate dielectric layer222(or the first, second, or third gate dielectric layer, as the case may be in different embodiments), and the functional metal gate stack236may be referred to as a metal gate structure or a functional metal gate structure in some instances. Methods according to the present disclosure provide a mechanism to provide for transistors with different threshold voltages without impacting the process window for gate structure formation. Instead of introducing an additional dipole layer that is going to stay in the gate trench, one or more dipole layers are selectively deposited on a gate dielectric layer and serve as vehicles of diffusion dopants to dope the gate dielectric layer. Depending on the thickness of the dipole layer, the anneal process duration, and the material of the dipole layer, the gate dielectric layer being doped may have different interface dipoles at its interface with the interfacial layer. After the doping process, the use of dipole layer(s) is removed from the gate trench. That is, methods of the present disclosure preserve the up-sides of having different threshold voltages using a dipole layer without the associated down-sides. The present disclosure provides embodiments to implement three levels of threshold voltages in a semiconductor device having three device regions and embodiments to implement four levels of threshold voltages in a semiconductor device having four device regions. Transistors having different levels of threshold voltages of the present disclosure may be applied in SRAM cells, such as 8T SRAM cells or 10T SRAM cells, to improve their performance. After reviewing the present disclosure, a person of ordinary skill in the art will appreciate that more threshold voltages in more device regions are possible. The present disclosure provides embodiments of semiconductor devices and methods of forming the same. In one embodiment, the present disclosure provides a semiconductor device that includes a first transistor, a second transistor and a third transistor. The first transistor includes a first active region, a first gate dielectric layer over the first active region and including a first concentration of a dipole layer material, and a first gate structure disposed over the first gate dielectric layer. The second transistor includes a second active region, a second gate dielectric layer over the second active region and including a second concentration of the dipole layer material, and a second gate structure disposed over the second gate dielectric layer. The third transistor includes a third active region, a third gate dielectric layer over the third active region including a third concentration of the dipole layer material, and a third gate structure disposed over the third gate dielectric layer. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration. In some implementations, the first gate structure, the second gate structure and the third gate structure are substantially identical to one another. In some instances, the third concentration is zero. In some implementations, the first transistor, the second transistor and the third transistor are n-type transistors. The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, and the third transistor includes a third threshold voltage. The first threshold voltage is smaller than the second threshold voltage and the second threshold voltage is smaller than the third threshold voltage. In some implementations, the first transistor, the second transistor and the third transistor are p-type transistors. The first transistor includes a first threshold voltage, the second transistor includes a second threshold voltage, and the third transistor includes a third threshold voltage. The first threshold voltage is greater than the second threshold voltage and the second threshold voltage is greater than the third threshold voltage. In some instances, the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer further include hafnium oxide. In another embodiment, the present disclosure provides a method that includes providing a workpiece including a first device region, a second device region and a third device region, forming a first gate trench in the first device region, a second gate trench in the second device region, and a third gate trench in the third device region, depositing a gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench, depositing a first dipole layer over the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench, selectively removing the first dipole layer in the second gate trench, depositing a second dipole layer over the first dipole layer in the first gate trench, the gate dielectric layer in the second gate trench, and the first dipole layer in the third gate trench, selectively removing the first dipole layer and the second dipole layer in the third gate trench, and annealing the workpiece. In some implementations, the method may further include after the annealing of the workpiece, removing the first dipole layer and the second dipole layer from the workpiece. In some instances, the first dipole layer and the second dipole layer include lanthanum oxide, aluminum oxide, or yttrium oxide. In some implementations, the annealing of the workpiece includes a temperature between about 500° C. and about 900° C. In some instances, the annealing of the workpiece includes a duration between about 5 seconds and about 20 seconds. In some implementations, a thickness of the first dipole layer and a thickness of the second dipole layer are between about 1 Å and about 10 Å. In some instances, the selectively removing of the first dipole layer in the second gate trench includes depositing a hard mask layer over the workpiece, depositing a bottom antireflective coating (BARC) layer over the hard mask layer, patterning the BARC layer and the hard mask layer to expose the second gate trench, and removing the first dipole layer in the second gate trench while the first gate trench and the third gate trench are covered by the hard mask layer and the BARC layer. In some instances, the first dipole layer includes a first thickness, the second dipole layer includes a second thickness, and the first thickness is substantially identically to the second thickness. In yet another embodiment, the present disclosure provides a method that includes providing a workpiece having a first device region, a second device region, a third device region, and a fourth device region, forming a first gate trench in the first device region, a second gate trench in the second device region, a third gate trench in the third device region, a fourth gate trench in the fourth device region, depositing a gate dielectric layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench, depositing a first dipole layer over the gate dielectric layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench, selectively removing the first dipole layer in the third gate trench and the fourth gate trench, performing a first anneal process to the workpiece, removing the first dipole layer in the first gate trench and the second gate trench, after the removing of the first dipole layer, depositing a second dipole layer over the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench, selectively removing the second dipole layer in the second gate trench and the fourth gate trench, performing a second anneal process to the workpiece, and removing the second dipole layer from the workpiece. In some implementations, the first dipole layer includes a first thickness, the second dipole layer includes a second thickness, and the first thickness is greater than the second thickness. In some instances, the first thickness is between about 5 Å and about 10 Å and the second thickness is between about 1 Å and about 5 Å. In some implementations, the first dipole layer and the second dipole layer include lanthanum oxide, aluminum oxide, or yttrium oxide. In some instances, the first anneal process and the second anneal process includes a temperature between about 500° C. and about 900° C. In some instances, the first anneal process and the second anneal process includes a duration between about 5 seconds and about 20 seconds. The foregoing has outlined features of several embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. | 94,476 |
11862707 | DETAILED DESCRIPTION FIG.1shows a first embodiment of the present HEMT transistor, designated by1. In detail, the HEMT transistor1comprises a semiconductor body2, which in turn comprises a first layer4and a second layer6, referred to hereinafter as the bottom layer4and the top layer6, respectively. The bottom layer4is of a first semiconductor material, such as for example a first semiconductor alloy of elements of Groups III and V of the Periodic Table; purely by way of example, in what follows it is assumed that the bottom layer4is of gallium nitride (GaN). The top layer6overlies the bottom layer4, with which it is in direct contact, and is of a second semiconductor material, such as for example a second semiconductor alloy of elements of Groups III-V of the Periodic Table, this second semiconductor alloy being different from the first semiconductor alloy. Purely by way of example, in what follows it is assumed that the top layer6is of aluminum gallium nitride (AlGaN). The bottom layer4and the top layer6are, for example, of an N type. Furthermore, the bottom layer4has a thickness of, for example, between 20 nm and 7 μm, while the top layer6has a thickness of, for example, between 5 nm and 400 nm. Although not shown, the semiconductor body2further comprises a substrate, made for example of silicon, on which the bottom layer4is formed. Since this substrate is irrelevant for the purposes of the present disclosure, it will not be mentioned any further in the present description. The HEMT transistor1further comprises a passivation region8, which overlies, in direct contact, the top layer6and is made, for example, of silicon nitride. For instance, the passivation region8has a thickness of 100 nm. The passivation region8forms a first surface Saof the HEMT transistor1. The HEMT transistor1further comprises a gate region10, which extends inside a trench15and is of conductive material; for example, the gate region10may be made up of one or more metal layers, made for example of aluminum, nickel, or tungsten. In detail, the trench15extends through the passivation region8, starting from the first surface Sa, as well as through the top layer6. Furthermore, the trench15traverses a top portion of the bottom layer4, arranged in contact with the top layer6. In greater detail, the trench15is delimited by a first side wall Pl1, a second side wall Pl2, a third side wall Pl3, and a fourth side wall Pl4, which are mutually parallel and are perpendicular to the first surface Sa. Further, the trench15is delimited by a first bottom wall Pb1, a second bottom wall Pb2, and a third bottom wall Pb3, which are parallel to one another and to the first surface Sa. In particular, the first bottom wall Pb1extends in the bottom layer4, to a first depth (measured, for example, with respect to the first surface Sa). Also the second bottom wall Pb2and the third bottom wall Pb3extend in the bottom layer4, to the same depth, which is less than the aforementioned first depth. Furthermore, the first side wall Pl1connects the first and second bottom walls Pb1, Pb2; the third side wall Pl3connects, instead, the first and third bottom walls Pb1, Pb3. Furthermore, the second side wall Pl2connects the second bottom wall Pb2to the first surface Sa; the fourth side wall Pl4connects the third bottom wall Pb3to the first surface Sa. In practice, as shown in greater detail inFIG.2, the first bottom wall Pb1and the first side wall Pl1form a first edge E1; further, the first side wall Pu and the second bottom wall Pb2form a second edge E2, which is parallel to the first edge E1, with which it is coplanar. In addition, the second bottom wall Pb2and the second side wall Pl2form a third edge E3, which is parallel to the second edge E2, with which it is coplanar. In turn, the second side wall Pl2forms a fourth edge E4with the first surface Sa(not shown inFIG.2). In addition, the first bottom wall Pb1and the third side wall Pl3form a fifth edge E5; further, the third side wall Pl3and the third bottom wall Pb3form a sixth edge E6, which is parallel to the fifth edge E5, with which it is coplanar. In addition, the third bottom wall Pb3and the fourth side wall Pl4form a seventh edge E7, which is parallel to the sixth edge E6, with which it is coplanar. In turn, the fourth side wall Pl4forms an eighth edge E8with the first surface Sa. In even greater detail, the first and third side walls Pl1, Pl3are set apart from one another by a distance equal to L1(measured in a direction perpendicular to the first and third side walls Pl1, Pl3), which thus represents the width of the first bottom wall Pb1. The widths of the second and third bottom walls Pb2, Pb3are instead designated, respectively, by L2and L3. In addition, the first and third side walls Pl1, Pl3have a height equal to H1, measured in a direction perpendicular to the first bottom wall Pl1. Furthermore, as shown inFIG.1, each one of the second and fourth side walls Pl2, Pl4has a respective bottom portion, which extends starting, respectively, from the third and seventh edges E3, E7until it contacts the top layer6, this portion having a height H2. In practice, the trench15forms a first cavity22and a second cavity24, communicating with one another and having the same length. The first cavity22gives out onto the first surface Sa, overlies the second cavity24and has a width equal to L1+L2+L3; the second cavity24has a width equal to L1. Purely by way of example, each of the widths L1, L2and L3may be comprised between 0.1 μm and 10 μm; further, the height H1may, for example, be comprised between 1 nm and 500 nm, whereas the height H2may, for example, be comprised between 0 and 500 nm. In other words, the first side wall Pl1and the second bottom wall Pb2form a first step, i.e., a first shoulder, of a lateral structure LS that delimits the trench15laterally and extends from a side of the first bottom surface Pb1. In particular, denoting the ensemble of the semiconductor body2and of the passivation region8as the main body, the lateral structure LS is formed by the main body. Furthermore, the second bottom wall Pb2, the second side wall Pl2, and the first surface Saform a sort of second step of the aforementioned lateral structure LS. The first and second steps are arranged in succession, in such a way that the lateral structure LS assumes a staircase profile. The HEMT transistor1further comprises a dielectric region18, which is formed, for example, by aluminum nitride (AlN), or silicon nitride (SiN), or silicon oxide (SiO2), and coats the first surface Sa. Furthermore, the dielectric region18internally coats the trench15, i.e., coats, among others, the first, second, and third bottom walls Pb1, Pb2, Pb3, as well as the first, second, third, and fourth side walls Pl1, Pl2, Pl3and Pl4. In this connection, as previously mentioned, the first, second, and third bottom walls Pb1, Pb2, Pb3are formed by the bottom layer4, as also the first and third side walls Pl1, Pl3, while each of the second and fourth side walls Pl2, Pl4is formed by the bottom layer4, the top layer6, and the passivation region8. In greater detail, the gate region10comprises a bottom portion11a, arranged within the second cavity24, and a central portion11b, arranged within the first cavity22, on the bottom portion11a, with which it is in direct contact. The dielectric region18surrounds the bottom portion11aand the central portion11bof the gate region10, which are thus arranged in the trench15more internally than the dielectric region18and are coated by the latter. In particular, the dielectric region18insulates the bottom portion11aand the central portion11bof the gate region10from the semiconductor body2, as well as from the passivation region8. In even greater detail, the bottom portion11aand the central portion11bof the gate region10are both parallelepipedal in shape and have a width D1and a width D2, respectively, with D1<L1and D2>L1. Furthermore, without any loss of generality, the bottom portion11aextends to a depth W11a(measured starting from the first surface Sa), greater than the maximum depth to which the top layer6(designated by W6) extends; the central portion11bextends, instead, to a depth W11b<W11a. Without any loss of generality, in the embodiment shown inFIG.1we have W6<W11b. In other words, as shown in greater detail inFIG.3, the gate region10is delimited at the bottom by a first horizontal wall O1, a second horizontal wall O2, and a third horizontal wall O3and by a first vertical wall V1and a second vertical wall V2. In particular, the first horizontal wall O1delimits, at the bottom, the bottom portion11aof the gate region10, which is delimited laterally by the first and second vertical walls V1, V2. The central portion11bof the gate region10is delimited, at the bottom (in part), by the second and third horizontal walls O2, O3. The first vertical wall V1connects the first and second horizontal walls O1, O2, with which it forms a corresponding step of the gate region10. Likewise, the second vertical wall V2connects the first and third horizontal walls O1, O3, with which it forms a corresponding step of the gate region10. Furthermore, the first horizontal wall O1and the first vertical wall V1form a first edge G1of the gate region10, parallel to the first edge E1of the trench15, while the first vertical wall V1and the second horizontal wall O2form a second edge G2of the gate region10, parallel to the second edge E2of the trench15. As shown again inFIG.3, the gate region10further comprises a top portion11c, which extends on the central portion11b, with which it is in direct contact. Furthermore, the central portion11bof the gate region10is delimited laterally by a third vertical wall V3and a fourth vertical wall V4, which are parallel to one another and face, respectively, the second and fourth side walls Pl2, Pl4of the trench15. The third vertical wall V3forms a third edge G3and a fourth edge G4of the gate region10with the second horizontal wall O2and the top portion11cof the gate region10, respectively. In practice, to a first approximation, the dielectric region18has an approximately constant thickness inside the trench15; i.e., it forms a sort of conformal layer that coats the walls of the trench15; consequently, the part of gate region10contained within the trench15is delimited by a surface that follows the profile of the trench15(and thus of the lateral structure LS). Consequently, corresponding to each edge/step of the trench15is an edge/step of the part of gate region10contained within the trench15. Again with reference toFIG.1, the portion of dielectric region18that extends on the first surface Sais delimited at the top by a second surface Sb, substantially parallel to the first surface Sa. Furthermore, the top portion11cof the gate region10has a width greater than L1+L2+L3and projects laterally both with respect to the second side wall Pl2and with respect to the fourth side wall Pl4. Without any loss of generality, in the embodiment shown inFIG.1, the top portion11cof the gate region10projects laterally from the second side wall Pl2to a greater extent than the top portion11cprojects from the fourth side wall Pl4. The HEMT transistor1further comprises a source metallization26and a drain metallization28, arranged on sides opposite to the trench15and to the top portion11cof the gate region10. Each one of the source metallization26and the drain metallization28traverses the portion of dielectric region18arranged on top of the front surface Saand the portion underlying the passivation region8until it contacts the top layer6. In a per se known manner, each one of the source metallization26and the drain metallization28may be formed, for example, by a corresponding plurality of metal layers (for example, of titanium, aluminum, and tungsten); further, a top portion of each one of the source metallization26and the drain metallization28extends up to a height greater than the height of the second surface Sb. In greater detail, the second and fourth side walls Pl2, Pl4of the trench15face the drain metallization28and the source metallization26, respectively. In use, the gate region10, the dielectric region18, and the bottom layer4form a MOSFET, the channel of which extends in the bottom layer4, underneath the first bottom wall Pb1. This channel, of the normally off type, may be modulated by applying a voltage to the gate region10. In a per se known manner, underneath the interface between the bottom layer4and the top layer6, thus in the bottom layer4, a so-called “two-dimensional electron gas” (2DEG) is formed, which represents the channel (of the normally on type) of the HEMT transistor1. Also this channel is modulated by the voltage present on the gate region10, thanks to the presence, in the top portion11cof the gate region10, of a projection that extends, with respect to the underlying central portion11b, towards the drain metallization28, thus overlying a corresponding portion of the two-dimensional electron gas. In other words, the top layer6functions as barrier layer, whereas the bottom layer4functions as buffer layer. The HEMT transistor1has thus, as a whole, a channel of the normally off type, thanks to the presence of the aforementioned MOSFET. Furthermore, it may be shown that the HEMT transistor1exhibits a leakage current of the type illustrated inFIG.4, where there further appears an example of leakage current of a HEMT transistor of a known type. In practice, the HEMT transistor1is not affected by the DIBL phenomenon. This is due to the fact that, thanks to the presence of the aforementioned first step of the trench15, the electrical field at the aforementioned first edge E1presents a pattern as a function of the drain voltage that is of the type shown inFIG.5(on the hypothesis of zero gate and source voltages), which further represents an example of the corresponding plot of the electrical field that arises in a HEMT transistor of a known type and where the gate region is formed in a recess of a traditional shape, at a bottom edge of this recess. In fact, the presence of the aforementioned first step of the lateral structure implies the presence, in the semiconductor body2, of the third edge E3; consequently, the electrical field is approximately shared between the first and third edges E1, E3. Further possible are embodiments of the type shown inFIG.1, but where the trench15extends to depths different from what has been described previously. For instance, as shown inFIG.6, it is possible for the first bottom wall Pb1of the trench15to lie in the plane of the interface between the bottom layer4and the top layer6. In this case, the gate region10is entirely on top of the bottom layer4. Consequently, the second edge E2of the trench15and the aforementioned first step of the trench15are formed by the top layer6. The first edge E1is instead still in contact with the bottom layer4, and thus guarantees the aforementioned reduction of the electrical field. According to a different embodiment, shown inFIG.7, the HEMT transistor1is of the same type as the one shown inFIG.1, apart from the fact that the second edge E2of the trench15is formed by the top layer6. Without any loss of generality, assuming that the passivation region8extends to a depth W8, we have W11b>W8even though variations where we have W11b=W8are in any case possible. In general, the embodiments shown inFIGS.6and7are characterized by low resistances between the source metallization26and drain metallization28, since in both cases a part of the channel of the MOSFET is formed in the top layer6; the consequent greater extension of the two-dimensional gas thus entails a reduction of the so-called RON. FIG.8shows, instead, a further embodiment in which the lateral structure LS comprises more than two steps. For instance, without any loss of generality, in the embodiment shown inFIG.8the lateral structure LS forms, in addition to the aforementioned first and second steps (the upper edges of which E2, E4are shown inFIG.8), a further three steps, the upper edges of which are designated by Ex1, Ex2, and Ex3, respectively. Purely by way of example, the edges Ex1, Ex2, and Ex3are formed by the top layer6. The central portion11of the gate region10thus forms another three corresponding additional steps, the upper edges of which are designated by Gx1, Gx2and Gx3, respectively; without any loss of generality, inFIG.8the edge Gx3is set coplanar with the interface between the bottom layer4and the top layer6. It may be shown that, as the number of steps of the lateral structure LS increases, the electrical field present between the gate region10and the drain metallization28is distributed more evenly along the lateral structure LS since the corresponding peaks, located in the presence of the edges, reduce their own amplitude. In this way, any deterioration of the HEMT transistor during the turning off steps, in which the transistor is subjected to high drain voltages, is prevented. The present HEMT transistor1may be produced, for example, by implementing the manufacturing method described in what follows. Without any loss of generality and purely by way of non-limiting example, the manufacturing method is described with reference to production of the HEMT transistor1shown inFIG.1. Initially, as shown inFIG.9, the main body, including the semiconductor body2and the passivation region8, is provided in a per se known manner. Next, as shown inFIG.10, in a per se known manner, a photolithographic process and a subsequent etching process are carried out in order to remove selectively a portion of the passivation region8, an underlying portion of the top layer6, and an underlying portion of the bottom layer4for forming a first recess40, which has the shape of a parallelepiped and has a depth greater than the aforementioned depth W11b. The first recess40is delimited, at the bottom, by a plane surface SR, formed by the bottom layer4, and is designed to house the central portion11bof the gate region10and the portion of dielectric region18that coats it. Next, as shown inFIG.11, in a per se known manner a further photolithographic process and a subsequent further etching process are carried out in order to remove selectively a portion of the bottom layer4, starting from the plane surface SR. In particular, a portion of the bottom layer4that forms a central portion of the plane surface SR is removed, said central portion separating a pair of lateral portions of the plane surface SR, which in turn form the second and third bottom walls Pb2, Pb3, respectively, of the trench15. In this way, a second recess42is formed, which is delimited at the bottom by the first bottom wall Pb1and has a smaller width than the first recess40. The second recess42is further delimited laterally by the first and third side walls Pl1, Pl3and is designed to house the bottom portion11aof the gate region10, and thus extends to a depth greater than the aforementioned depth W11a. The first and second recesses40,42form the trench15. Next, as shown inFIG.12, formed on the first surface Saand within the trench15is a dielectric layer50, made, for example, of aluminum nitride or silicon nitride. The dielectric layer50thus coats the walls of the trench15and is formed, for example, by deposition. Next, as shown inFIG.13, the source metallization26and the drain metallization28are formed in a per se known manner. For this purpose, even though not shown in detail, it is possible to carry out a further photolithographic process and a subsequent etching process for removing selectively portions of the dielectric layer50and underlying portions of the passivation region8, to form cavities designed to house, respectively, the source metallization26and the drain metallization28, which are subsequently formed within these cavities by the so-called “lift-off” technique. According to the lift-off technique, by photolithography a resist mask is formed, which leaves exposed just the regions of the HEMT transistor1that are to be overlaid by the source metallization26and by the drain metallization28. Next, metal material is deposited on the HEMT transistor1; subsequent removal of the resist mask also entails removal of the metal material overlying the resist mask itself. Once the source metallization26and the drain metallization28are formed, what remains of the dielectric layer50forms the dielectric region18. Next, even though not shown, a thermal process is carried out, for example at a temperature comprised between 500° C. and 900° C. for formation of the contacts. Next, as shown inFIG.14, the gate region10is formed, the bottom and central portions11a,11bof which extend within the trench15. Also the gate region10may be formed by a corresponding lift-off process, which envisages forming a corresponding resist mask, depositing conductive material both on the mask and on the portion of HEMT transistor1left free from the mask, and subsequently removing the resist mask and the conductive material arranged on top of it. As regards, instead, embodiments of the type shown inFIG.8, i.e., embodiments in which the lateral structure LS forms more than two steps, they may be formed for example by carrying out the steps (not shown) of: a) removing selectively a top portion of the main body for removing a corresponding recess, delimited by a bottom surface; b) starting from the aforementioned bottom surface, removing selectively an underlying portion of main body for forming a further recess, delimited by a respective bottom surface, the further recess having a width smaller than the previous recess and being laterally staggered with respect to the side walls of the previous recess; and c) iterating step b) until formation of the desired number of steps. In the case where the manufacturing method just described above is adopted, the shape of the trench15may differ from what is shown inFIG.8; in particular, the portion of trench15facing the source metallization26may include a number of steps equal to that of the lateral structure LS. From what has been described and illustrated previously, the advantages that the present solution affords emerge clearly. In particular, the present HEMT transistor is substantially immune from the DIBL phenomenon since, in use, the electrical field at the first edge E1(in contact with the first layer4) is reduced, thanks to the presence in the semiconductor body2of at least the third edge E3. In conclusion, it is clear that modifications and variations may be made to what has been described and illustrated so far, without thereby departing from the scope of the present disclosure. For instance, each one of the source metallization26and the drain metallization28may penetrate in part within the top layer6, as well as possibly also in a top portion of the bottom layer4. The bottom layer4may include a respective top portion and a respective bottom portion (not shown), which are doped for example with carbon atoms; in this case, the top portion is doped with carbon atoms to an extent smaller than the bottom portion and functions as so-called channel layer, whereas the bottom portion of the bottom layer4functions as buffer layer. In this case, if the second and third bottom walls Pb2, Pb3are formed by the bottom layer4, they may be formed indifferently by the top portion or by the bottom portion of the bottom layer4. Doping of the semiconductor body2may be of a type different from what has been described. For instance, the bottom layer4and the top layer6may be of a P type. As regards the trench15, the portion of trench15arranged between the first bottom wall Pb1and the source metallization26may have a shape different from what has been described. For instance, embodiments are possible of the type shown inFIG.1but where the third bottom wall Pb3is absent, in which case the third and fourth side walls Pl3, Pl4are replaced by a single side wall. In this connection, it may be noted how, for the purposes of prevention of the DIBL phenomenon, the shape of the further lateral structure that delimits the trench15laterally and is opposite to the lateral structure LS is to a first approximation irrelevant since the electrical field between the source metallization26and the gate region10is less intense than the electrical field present between the gate region10and the drain metallization28. The passivation region18may be absent, in which case the first surface Sais formed by the top layer6. Again, as shown inFIG.15, between the bottom layer4and the top layer6there may be present a spacer layer200, made, for example, of aluminum nitride and having a smaller thickness, for example of 1 nm; the spacer layer200has the purpose of improving the mobility of the two-dimensional electron gas. In general, there are thus possible further embodiments that correspond to embodiments described previously but further include the spacer layer200. In these further embodiments, the spatial distribution of the steps and of the edges of the lateral structure LS may, for example, correspond to that of the corresponding embodiments described previously in the sense that, if in a previous embodiment an edge of a step is formed by a given layer (for example, the bottom layer4or the top layer6), in the corresponding further embodiment the corresponding edge is again formed by that given layer. Once again with reference to the lateral structure LS, even though previously orthogonal steps have been described, i.e., steps that connect pairs of horizontal surfaces by vertical surfaces, it is, however, possible for the vertical surfaces of one or more steps to be transverse with respect to the corresponding horizontal surfaces and/or for one or both of the horizontal surfaces of one or more steps to be replaced by surfaces that are not parallel to the first surface Sa. In other words, in general the walls and the vertical surfaces may be not perfectly orthogonal to the first surface Sa. The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. | 26,610 |
11862708 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Transistor and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the transistors are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In the illustrated exemplary embodiments, the formation of Fin Field-Effect Transistors (FinFETs) is used as an example to explain the concepts of the present disclosure. Planar transistors may also adopt the concept of the present disclosure. FIGS.1through21illustrate the cross-sectional views and perspective views of intermediate stages in the formation of FinFETs in accordance with some embodiments of the present disclosure. The steps shown inFIGS.1through21are also reflected schematically in the process flow shown inFIG.22. FIG.1illustrates a perspective view of an initial structure. The initial structure includes wafer10, which further includes substrate20. Substrate20may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. Substrate20may be doped with a p-type or an n-type impurity. Isolation regions22such as Shallow Trench Isolation (STI) regions may be formed to extend from a top surface of substrate20into substrate20, wherein the top surface of substrate20is a major surface10A of wafer10. The portions of substrate20between neighboring STI regions22are referred to as semiconductor strips24. The top surfaces of semiconductor strips24and the top surfaces of STI regions22may be substantially level with each other in accordance with some exemplary embodiments. STI regions22may include a liner oxide (not shown), which may be a thermal oxide formed through a thermal oxidation of a surface layer of substrate20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI regions22may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, or the like. Referring toFIG.2, STI regions22are recessed, so that the top portions of semiconductor strips24protrude higher than the top surfaces of STI regions22to form protruding fins24′. The etching may be performed using a dry etching process, wherein HF3and NH3are used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of STI regions22is performed using a wet etch process. The etching chemical may include HF, for example. Referring toFIG.3, dummy gate stack30is formed on the top surfaces and the sidewalls of (protruding) fins24′. It is appreciated that although one dummy gate stack30is illustrated for clarity, there may be a plurality of dummy gate stacks formed, which are parallel to each other, with the plurality of dummy gate stacks crossing the same semiconductor fin(s)24′. Dummy gate stack30may include dummy gate dielectric32and dummy gate electrode34over dummy gate dielectric32. Dummy gate electrode34may be formed, for example, using polysilicon, and other materials may also be used. Dummy gate stack30may also include one (or a plurality of) hard mask layer36over dummy gate electrode34. Hard mask layer36may be formed of silicon nitride, silicon carbo-nitride, or the like. Dummy gate stack30may cross over a single one or a plurality of protruding fins24′ and/or STI regions22. Dummy gate stack30also has a lengthwise direction perpendicular to the lengthwise directions of protruding fins24′. Next, gate spacers38are formed on the sidewalls of dummy gate stack30. In accordance with some embodiments of the present disclosure, gate spacers38are formed of a dielectric material such as silicon carbon-oxyitride (SiCN), silicon nitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. An etching step (referred to as source/drain recessing hereinafter) is then performed to etch the portions of protruding fins24′ that are not covered by dummy gate stack30and gate spacers38, resulting in the structure shown inFIG.4. The recessing may be anisotropic, and hence the portions of fins24′ directly underlying dummy gate stack30and gate spacers38are protected, and are not etched. The top surfaces24A of the recessed semiconductor strips24may be lower than the top surfaces22A of STI regions22in accordance with some embodiments. Recesses40are accordingly formed between STI regions22. Recesses40are located on opposite sides of dummy gate stack30. Next, epitaxy regions (source/drain regions) are formed by selectively growing a semiconductor material in recesses40, resulting in the structure inFIG.5. In accordance with some exemplary embodiments, epitaxy regions42include silicon germanium or silicon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP) or silicon carbon phosphorous (SiCP) may be grown. In accordance with alternative embodiments of the present disclosure, epitaxy regions42is formed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof. After epitaxy regions42fully fill recesses40, epitaxy regions42start expanding horizontally, and facets may be formed. After the epitaxy step, epitaxy regions42may be further implanted with a p-type or an n-type impurity to form source and drain regions, which are also denoted using reference numeral42. In accordance with alternative embodiments of the present disclosure, the implantation step is skipped when epitaxy regions42are in-situ doped with the p-type or n-type impurity during the epitaxy. Epitaxy regions42include lower portions42A that are formed in STI regions22, and upper portions42B that are formed over the top surfaces22A of STI regions22. Lower portions42A, whose sidewalls are shaped by the shapes of recesses40(FIG.4), may have (substantially) straight edges, which may also be substantial vertical edges that are substantial perpendicular to the major surfaces (such as bottom surface20B) of substrate20. FIG.6Aillustrates a perspective view of the structure with Inter-Layer Dielectric (ILD)46being formed. In accordance with some embodiments of the present disclosure, a buffer oxide layer (not shown) and a Contact Etch Stop Layer (CESL)47are formed on source and drain regions42before the formation of ILD46. The buffer oxide layer may be formed of silicon oxide, and the CESL47may be formed of silicon nitride, silicon carbo-nitride, or the like. The buffer oxide layer and CESL47may be formed using a conformal deposition method such as ALD, for example. ILD46may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or other deposition methods. ILD46may also be formed of Tetra Ethyl Ortho Silicate (TEOS) oxide, Plasma Enhanced CVD (PECVD) oxide (SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like. A planarization step such as Chemical Mechanical Polish (CMP) or mechanical grinding may be performed to level the top surfaces of ILD46, dummy gate stack30, and gate spacers38with each other. A cross-sectional view of the structure shown inFIG.6Ais illustrated inFIG.6B, wherein the cross-sectional view is obtained from the vertical plane containing line A-A inFIG.6A. In the cross-sectional view, two of the plurality of dummy gate stacks30are illustrated, and source/drain regions42formed between neighboring dummy gate stacks30are illustrated. It is appreciated that more dummy gate stacks30and source/drain regions42may be formed in an alternating layout. Next, dummy gate stacks30, which include hard mask layers36, dummy gate electrodes34and dummy gate dielectrics32are replaced with replacement gate stacks, which include metal gates and replacement gate dielectrics as shown inFIGS.7through10. The cross-sectional views shown inFIGS.7through10and the subsequentFIGS.11through21are obtained from the same vertical plane containing line A-A inFIG.6A. InFIGS.7through21, the level22A of the top surfaces of STI regions22are illustrated, and semiconductor fins24′ are over level22A. When replacing gate stacks, hard mask layers36, dummy gate electrodes34, and dummy gate dielectrics32as shown inFIGS.6A and6Bare first removed in one or a plurality of etching steps, resulting in trenches/openings48as shown inFIG.7. The respective step is illustrated as step202in the process flow shown inFIG.22. The top surfaces and the sidewalls of protruding semiconductor fins24′ are exposed to trenches48. FIG.8illustrates the formation of gate spacers50in accordance with some embodiments. The respective step is illustrated as step204in the process flow shown inFIG.22. In accordance with alternative embodiments, gate spacers50are not formed. To form gate spacers50, one or more blanket gate spacer layers is formed, for example, using a deposition method such as ALD or CVD. The blanket gate spacer layer is conformal. In accordance with some embodiments of the present disclosure, the gate spacer layer is formed of silicon nitride (SiN), SiC, SiON, Silicon oxy-carbo nitride, silicon oxynitride, or other dielectric materials, which may be the same or different from either one of the materials of gate spacers38and the materials of CESL47and ILD46. Gate spacers50separate the subsequently formed metal gates farther away from source/drain regions42, so that the possibility of leakage and electrical shorting between them are reduced. In accordance with some embodiments, gate spacers50are formed of a low-k dielectric material, which may have a dielectric constant (k value) lower than about 3.0. Throughout the description, the k value of silicon oxide (SiO2), which is about 3.9, is used to distinguish low k values from high k values. Accordingly, the k values lower than 3.8 are referred to as low k values, and the respective dielectric materials are referred to as low-k dielectric materials. Conversely, the k values higher than 3.9 are referred to as high k values, and the respective dielectric materials are referred to as high-k dielectric materials. For example, gate spacers50may be formed of SiON or SiOCN, which are formed as being porous in order to have the desired low-k value. The formation of the low-k dielectric spacers50advantageously reduces the parasitic capacitance between the subsequently formed metal gates and source/drain regions42. For example, during the deposition of the blanket dielectric layer, porogen may be added, and an anneal is performed subsequent to the deposition to drive out the porogen, so that pores are generated. The k value of SiOCN may also be adjusted by adjusting the percentage of elements (such as carbon) therein. The blanket gate spacer layer is etched in an anisotropic etching to remove horizontal portions, and the remaining vertical portions form gate spacers50. Each of gate spacer50may be formed of a single layer having a homogenous dielectric material, or may be formed of a plurality of dielectric layers formed of different dielectric materials. For example, gate spacer50may include sub-spacer50A and sub-spacer50B. The formation process may include depositing a conformal dielectric layer and performing an anisotropic etch to form sub-spacer50A, and then depositing another conformal dielectric layer and performing another anisotropic etch to form sub-spacer50B. In the embodiments in which gate spacers50include sub-spacers, either one of sub-spacers50A and sub-spacers50B is formed of a low-k dielectric material such as SiON or SiOCN (with pores), and the other sub-layer may be formed of a low-k dielectric material, silicon oxide (which is neither low-k nor high-k), or a high-k dielectric material. Silicon oxide or high-k dielectric materials have good insulating ability. Accordingly, with one of the sub-layers formed of low-k dielectric materials, and the other formed of silicon oxide or a high-k dielectric material, the isolating ability is good, and the parasitic capacitance is also low. In accordance with some embodiments, sub-spacers50A and50B are formed of a same material (such as SiON or SiOCN) but have different porosity. For example, sub-spacers50A may have a higher porosity than sub-spacers50B, or sub-spacers50B may have a higher porosity than sub-spacers50A. Next, referring toFIG.9, (replacement) gate dielectric layer52is formed, which extend into trenches48(FIG.8). The respective step is illustrated as step206in the process flow shown inFIG.22. In accordance with some embodiments of the present disclosure, gate dielectric layer52includes Interfacial Layer (IL)54as its lower part. IL54is formed on the exposed surfaces of protruding fins24′. IL54may include an oxide layer such as a silicon oxide layer, which is formed through the thermal oxidation of protruding fins24′, a chemical oxidation process, or a deposition process. Gate dielectric layer52may also include high-k dielectric layer56formed over IL54. High-k dielectric layer56includes a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0. High-k dielectric layer56is overlying, and may contact, IL54. High-k dielectric layer56is formed as a conformal layer, and extends on the sidewalls of protruding fins24′ and the top surface and the sidewalls of gate spacers38/50. In accordance with some embodiments of the present disclosure, high-k dielectric layer56is formed using ALD or CVD. Referring further toFIG.9, stacked layers58are deposited. The respective step is illustrated as step208in the process flow shown inFIG.22. The sub-layers in stacked layers58are not shown separately, while in reality, the sub-layers are distinguishable from each other. The deposition may be performed using a conformal deposition method such as ALD or CVD, so that thickness T1of the vertical portions and thickness T2of the horizontal portions of stacked layers58(and each of sub-layers) are substantially equal to each other. Stacked layers58extend into trenches48(FIG.8), and include some portions over ILD46. Stacked layers58may include a diffusion barrier layer and one (or more) work-function layer over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work-function layer determines the work function of the gate, and includes at least one layer, or a plurality of layers formed of different materials. The specific material of the work-function layer is selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work-function layer may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work-function layer may include a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. After the deposition of the work-function layer(s), another barrier layer, which may be another TiN layer, is formed. Next, metallic material60is deposited, which may be formed of tungsten or cobalt, for example. Metallic material60fully fills remaining trenches48(FIG.8). In a subsequent step as shown inFIG.10, a planarization step such as CMP or mechanical grinding is performed, so that the portions of layers56,58, and60over ILD46are removed. The respective step is illustrated as step210in the process flow shown inFIG.22. As a result, metal gate electrodes62are formed, which include the remaining portions of layers58and60. The remaining portion of layers52,58, and60are referred to as replacement gate stacks64hereinafter. As shown inFIG.10, the top surfaces of metal gate62, spacers38/50, CESL47, and ILD46may be substantially coplanar at this time. The thickness T3of ILD46and CESL47may be in the range between about 15 nm and about 25 nm. InFIG.10, dashed lines (marked as64/50) are illustrated as aligned to the outer edges of gate spacers50to show that gate spacers50and replacement gate stacks64extend below the illustrated top surfaces of semiconductor fins24′, and extend onto the sidewalls of semiconductor fins24′. The dashed lines indicate that these portions of gate spacers50and replacement gate stacks64are not in the illustrated plane. Also, although not shown, gate spacers38also extend onto the sidewalls of semiconductor fins24′, as shown inFIG.3. FIGS.11through20illustrate the formation of source/drain contact plugs and gate contact plugs. In the illustrated example, three source/drain regions42are shown, and the illustrated process only shows the formation of the three source/drain contact plug connected to the leftmost source/drain regions. In actual process, there may also be source/drain contact plugs formed to connect to the center and rightmost source/drain regions42. These source/drain contact plugs, however, are formed in different planes than illustrated, and hence are not visible. Similarly, there may be a gate contact plug formed directly over the left gate stack64, which is in a different plane than illustrated, and hence is not shown. Referring toFIG.11, in accordance with some embodiments of the present disclosure, dielectric mask66is formed. Between the planarization for forming gate electrodes62and the formation of dielectric mask66, no etch-back is performed to recess gate electrodes62. Dielectric layer66may be formed of a high-k dielectric material with a k value higher than 3.9. In accordance with some embodiments of the present disclosure, dielectric mask66is formed of AlxOy, HfO2, SiN, or SiOCN (with no pores or substantially no pores inside). Dielectric layer66may (or may not) also be formed of a same material (such as SiOCN) as gate spacers50, with gate spacers50being more porous than dielectric mask66in order to have a low k value. The thickness of dielectric mask66may be in the range between about 2 nm and about 4 nm. The formation method may include PECVD, ALD, CVD, or the like. Next, ILD68is formed over dielectric mask66. ILD68has a k value higher than the k value of the low-k dielectric material in gate spacers50, and lower than the k value of subsequently formed contact spacers82(FIG.14). The material of ILD68may be selected from the same candidate materials (and methods) for forming ILD46, and ILDs46and68may be formed of the same or different dielectric materials. For example, dielectric layer68may be formed using PECVD, and may include silicon oxide (SiO2). Thickness T4of dielectric layer68may be in the range between about 700 Å and about 800 Å. In according with alternative embodiments of the present disclosure, dielectric mask66is not formed, and ILD68is in direct contact with the underlying replacement gate stacks64, gate spacers38/50, CESL47, and ILD46. Accordingly, dielectric mask66is illustrated using dashed lines to indicate it is formed optionally. In these embodiments, between the planarization for forming gate electrodes62and the formation of ILD68, no etch-back is performed to recess gate electrodes62. Metal hard mask70, which is used as an etching mask in subsequent etching, is then formed over ILD68. Metal hard mask70may be formed of a metal nitride such as titanium nitride. Pad oxide layer72, which may be formed of silicon oxide, is then formed over hard mask layer70. Photo resist74is then applied and patterned, forming opening76. The patterned photo resist74is then used to etch the underlying pad oxide layer72and metal hard mask70, so that opening76extends into metal hard mask70. Next, photo resist74is removed, for example, in an ashing process. The remaining pad oxide layer72and metal hard mask70are then used as an etching mask to etch ILD68, dielectric mask66(if any), ILD46, and CESL47, so that source/drain contact opening78is formed, as shown inFIG.12. The respective step is illustrated as step212in the process flow shown inFIG.22. During this etching process, dielectric mask66(if formed) is not used as an etching stop layer. Accordingly, the etching of ILD68, dielectric mask66, and ILD46may be performed in a single continuous etching process using an etching gas attacking all of ILD68, dielectric mask66, and ILD46. CESL47may be used as an etching stop layer in the etching of layers68,66, and46. The etching process is then changed, for example, using a different etching gas, and the exposed portion of CESL47is etched, exposing the underlying source/drain region42. Referring toFIG.13, dielectric layer80is formed, for example, using a conformal deposition method such as CVD or ALD. Dielectric layer80may be a high-k dielectric layer with a k value greater than 3.9, so that it has good isolation ability. The candidate materials include AlxOy, HfO2, SiN, and SiOCN (with no pores or substantially no pores inside). The thickness of dielectric layer80may be in the range between about 2 nm and about 4 nm. An anisotropic etch is then performed, so that the horizontal portions of dielectric layer80are removed, and the remaining vertical portions on the sidewalls of opening78form contact spacer82, which forms a ring when viewed from the top of wafer10. The resulting structure is shown inFIG.14. The respective step is illustrated as step214in the process flow shown inFIG.22. In accordance with alternative embodiments of the present disclosure, rather than forming contact spacer82at this stage, contact spacer82may be formed simultaneously as contact spacer88in the step shown inFIG.16. Accordingly, inFIG.14, contact spacer82is illustrated as being dashed to indicate it may or may not be formed at this time. Referring toFIG.15, photo resist84is applied and patterned to form an opening therein. Next, ILD68and dielectric mask66are etched to extend the opening down and to form gate contact opening86, through which gate electrode62is exposed. The respective step is illustrated as step216in the process flow shown inFIG.22. Gate contact opening86may be wide enough, so that gate spacers38/50are exposed. Gate contact opening86may also be smaller than illustrated, and gate spacers50/38are not exposed. Photo resist84is then removed. Next, as shown inFIG.16, (gate) contact spacer88is formed on the sidewalls of opening86in accordance with some embodiments. In accordance with alternative embodiments, contact spacer88is not formed. When contact spacer82has already been formed in preceding steps, contact spacer88may not be formed. If contact spacer82hasn't been formed in preceding steps, contact spacers82and88are formed simultaneously in the step shown inFIG.16. Contact spacer88may be formed of a high-k dielectric material, which may be selected from the same group of candidate materials for forming contact spacer82(and corresponding dielectric layer80). Accordingly, contact spacer88is illustrated as dashed to indicate it may or may not be formed, and contact spacer82is illustrated as solid to indicate it has been formed. In accordance with alternative embodiments, contact opening86is formed prior to the formation of contact opening78, and hence contact spacer88is formed, while contact spacer82is formed optionally. Referring toFIG.17, metal layer90(such as a titanium layer or a cobalt layer) is deposited, for example, using PVD. Barrier layer92, which may be a metal nitride layer such as a titanium nitride layer or a tantalum nitride layer is then formed over metal layer90. The respective step is illustrated as step218in the process flow shown inFIG.22. Barrier layer92may be formed using CVD. Layers90and92are both conformal, and extend into openings78and86. An anneal is then performed to form source/drain silicide region94, as shown inFIG.18. The respective step is illustrated as step220in the process flow shown inFIG.22. The anneal may be performed through Rapid Thermal Anneal (RTA), furnace anneal, or the like. Accordingly, the bottom portion of metal layer90reacts with source/drain region42to form silicide region94. The sidewall portions of metal layer90remain after the silicidation process. In accordance with some embodiments of the present disclosure, the top surface of silicide region94is in contact with the bottom surface of barrier layer92. Next, as shown inFIG.19, metallic material96is deposited over and in contact with barrier layer92. The respective step is illustrated as step222in the process flow shown inFIG.22. Metallic material96may be selected from the same group of candidate materials of metal-containing material60, and may include tungsten or cobalt. A planarization step such as CMP or mechanical grinding is then performed to remove the portions of layers90,92, and96over ILD68. The resulting structure is shown inFIG.20, which includes source/drain contact plug98and gate contact plug102. FIG.21illustrates the formation of etch stop layer103, dielectric layer104, gate contact plug (via)106, and source/drain contact plug (via)108in etch stop layer103and dielectric layer104. Etch stop layer103may be formed of silicon carbide, silicon oxynitride, silicon carbo-nitride, or the like, and may be formed using a deposition method such as CVD. Dielectric layer104may include a material selected from PSG, BSG, BPS G, Fluorine-doped Silicon Glass (FSG), TEOS oxide, or PECVD oxide (SiO2). Dielectric layer104may be formed using spin coating, FCVD, or the like, or formed using a deposition method such as PECVD or Low Pressure Chemical Vapor Deposition (LPCVD). Dielectric layer104and etch stop layer103are etched to form openings (occupied by plugs/vias106and108). The etching may be performed using, for example, Reactive Ion Etch (RIE). In a subsequent step, plugs/vias106and108are formed. In accordance with some embodiments of the present disclosure, plugs/vias106and108include barrier layer110and metal-containing material112over barrier layer110. In accordance with some embodiments of the present disclosure, the formation of plugs/vias106and108includes etching layers103and104to form contact openings, forming a blanket barrier layer and a metal-containing material over the blanket barrier layer, and performing a planarization to remove excess portions of the blanket barrier layer and the metal-containing material. Barrier layer110may be formed of a metal nitride such as titanium nitride or tantalum nitride. The material, the structure, and the formation methods of metal-containing material112may be selected from the candidate materials, the candidate structures, and the candidate formation methods, respectively, of metal-containing material60, and hence the details are not repeated herein. In the resulting structure, the source regions in source/drain regions42may be electrically interconnected, the drain regions in source/drain regions42may be electrically interconnected, and gate electrodes64may be interconnected through contact plugs and overlying plugs/vias, metal lines (not shown), so that the resulting structure forms FinFET100. The embodiments of the present disclosure have some advantageous features. After the formation of metal gate electrode62, the metal gate electrode is not etched back, and no hard mask is formed in the resulting recess. Accordingly, the cost for etching-back and forming hard mask is saved. The height of the metal gate is also reduced since it doesn't need to be etched back. Accordingly, the aspect ratio of the opening for filling the metal gate is reduced, and the filling of metal gate is easier. The formation of the high-k contact spacers82/88and the high-k dielectric mask66improves the isolation between the metal gate and the adjacent source/drain contact plugs. The formation of the low-k gate spacers improves the isolation between the metal gate and the source/drain regions without causing the increase in the parasitic capacitance. In accordance with some embodiments of the present disclosure, a method includes forming a transistor, which includes forming a source/drain region on a side of a dummy gate, forming a first ILD covering the source/drain region, removing the dummy gate to form a trench in the first ILD, forming a gate dielectric layer extending into the trench, forming a metallic material over the gate dielectric layer, and performing a planarization to remove excess portions of the gate dielectric layer and the metallic material to form a gate dielectric and a metal gate, respectively. The method further includes forming a second ILD over the first ILD and the metal gate. At a time the second ILD is formed, a top surface of the metal gate is coplanar with a top surface of the first ILD. The method further includes forming a source/drain contact plug electrically coupling to the source/drain region, wherein the source/drain contact plug penetrates through both the first ILD and the second ILD, and forming a gate contact plug over and in contact with the metal gate. In accordance with some embodiments of the present disclosure, a method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an ILD. The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate. In accordance with some embodiments of the present disclosure, a device includes a first ILD, a first gate spacer in the first ILD, a gate dielectric in an opening located between opposite portions of the first gate spacer, and a metal gate over the gate dielectric. A top surface of the metal gate, a top end of the first gate spacer, and a top surface of the first ILD are in contact with a bottom surface of a same overlying dielectric layer. The device further includes a second ILD over the first ILD, a source/drain region adjacent to the metal gate, and a source/drain contact plug over and electrically coupling to the source/drain region. The source/drain contact plug penetrates through both the first ILD and the second ILD. A contact spacer encircles the source/drain contact plug. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 33,598 |
11862709 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” may encompass the dimension range from 4.5 nm to 5.5 nm. The present disclosure is generally related to ICs and semiconductor devices and methods of forming the same. More particularly, the present disclosure is related to vertically-stacked horizontally-oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. These types of transistors are sometimes referred to as gate-all-around (GAA) transistors, multi-bridge-channel (MBC) transistors, or some other names. In the present disclosure, they are broadly referred to as nano-sheet-based transistors (or devices). A nano-sheet-based device includes a plurality of suspended channel layers stacked one on top of another and engaged by a gate structure. The channel layers of a nano-sheet-based device may include any suitable shapes and/or configurations. For example, the channel layers may be in one of many different shapes, such as wire (or nanowire), sheet (or nanosheet), bar (or nano-bar), and/or other suitable shapes. In other words, the term nano-sheet-based devices broadly encompasses devices having channel layers in nanowire, nano-bars, and any other suitable shapes. Further, the channel layers of the nano-sheet-based devices may engage with a single, contiguous gate structure, or multiple gate structures. The channel layers connect a pair of source/drain features, such that the charge carriers may flow from the source region to the drain region through the channel layers during the operation (such as when the transistors are turned on). Additionally, inner spacers are formed between the source/drain features and the gate structures such that the source/drain features may be shielded from the operations targeting the gate structure. The inner spacers may have varying lateral widths across the vertical dimension (such as the dimension perpendicular to the top surface of the substrate). In some approaches, the inner spacers may have rounded sidewall surfaces, where the top and bottom portions of each inner spacers have significantly reduced lateral widths as compared to the middle portions. As the overall dimensions of the inner spacers reduce along with the scale-down of the device, those top and bottom portions of the inner spacers may become too thin to provide sufficient protection for the source/drain features in subsequent processing. Damages may therefore occur to the source/drain features, which have been shown to degrade device performances. Conversely, to avoid such damages by increasing the overall dimensions of the inner spacers impedes the overall goal of scale-down. It is therefore a challenge to achieve the desired feature density without compromising feature integrity in these approaches. Accordingly, the present disclosure provides methods that form inner spacer structures that have less rounded (or more square-like) sidewall surfaces, such that the top and bottom portions of the inner spacers may maintain a relatively large lateral width for the purpose of maintaining feature integrity, while the middle portion of the inner spacers may have reduced lateral width to facilitate the scale-down effort. This results in overall performance improvements of the device. The nano-sheet based devices presented herein may be a complementary metal-oxide-semiconductor (CMOS) device, a p-type metal-oxide-semiconductor (PMOS) device, or an n-type metal-oxide-semiconductor (NMOS) device. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure. An example nano-sheet-based transistor100(or nano-sheet-based device100, or transistor100, or device100) is illustrated inFIGS.1A and1B.FIG.1Ais a three-dimensional (3D) perspective view of an embodiment of the device100of the present disclosure.FIG.1Bis an expanded 3D view of the circled region of the device100inFIG.1A.FIG.1Cis a cross-sectional view of the device100ofFIG.1Aalong the line A-A′ inFIG.1A. As illustrated, the device100includes a semiconductor substrate105(or hereinafter referred to as substrate105). Fin structures (or fins), such as fin structures108, are formed over the substrate105, each extending lengthwise horizontally in an X-direction and separated from each other horizontally in a Y-direction. The X-direction and the Y-direction are horizontal directions that are perpendicular to each other, and that the Z-direction is a vertical direction that is orthogonal (or normal) to a horizontal XY plane defined by the X-direction and the Y-direction. The substrate105may have its top surface parallel to the XY plane. The fin structures108each have a source region102, a drain region102(collectively, source/drain regions102) disposed along the X-direction and spaced away from each other. Epitaxial source/drain features210are formed in the source/drain regions102of the fin structures108. The fin structures108each further have a channel region104disposed between and connecting the source and drain regions102. A stack of suspended semiconductor layers120(also interchangeably referred to as “semiconductor layers120” or “channel layers120”) are formed in the channel region104connecting the epitaxial source/drain features210; and the stack extends vertically (e.g. along the Z-direction) from the substrate105. The suspended semiconductor layers120may each be in one of many different shapes, such as wire (or nanowire), sheet (or nanosheet), bar (or nano-bar), and/or other suitable shapes, and may be spaced away from each other. The semiconductor layers120may each engage with a single, contiguous gate structure250. The gate structure250includes a metal gate stack and gate spacers layers200on both sides of the metal gate stack, and optionally gate spacer layers202on two sides of the gate spacer layers200. The device100further includes inner spacers206formed between the gate structures250and the epitaxial source/drain features210. The inner spacers206may have a sidewall surface206w. Furthermore, the sidewall surface206wincludes a footing region206f. As described in detail later, the sidewall surface206wis engineered to have a reduced curvature as compared to other approaches, and that the footing region206fhas a sidewall surface that is less canted from the vertical direction (or the Z-direction) as compared to other approaches. Note that the metal gate stack is illustrated as a transparent feature inFIGS.1A and1Bin order to illustrate the features (such as the semiconductor layers120) that the metal gate stacks cover. Moreover,FIGS.1A-1Cdo not depict details of the metal gate stack for simplicity. Those details are described in later figures. The device100further includes isolation features150within or over the substrate105, separating adjacent fin structures108from each other. The isolation features150may be shallow trench isolation (STI) features or any other suitable isolation structures. The device100further includes interlayer dielectric (ILD) layer230over the epitaxial source/drain features210, and contact etch stop layers220between the epitaxial source/drain features210and the ILD layer230. Device100may include other suitable features, that have been omitted for simplicity and conciseness. FIGS.2A-2Billustrate a flow chart for an embodiment of a method10for fabricating a device100of the present disclosure.FIGS.3A,4A,5,6,7A-10A,11,12,13,14A, and15Aare cross-sectional views of the device100along the line A-A′ inFIG.1Aconstructed at various fabrication stages of the method10.FIGS.3B,4B,7B-10B,14B, and15B, are expanded cross-sectional views of the circled area of the device100of theFIGS.3A,4A,7A-10A,14A, and15A, respectively, constructed at various fabrication stages of the method10.FIG.7Cis an expanded 3D view of the circled region of the device100inFIG.7A. Referring to block12ofFIG.2AandFIG.3A, the device100includes a substrate105. The substrate105contains a semiconductor material, such as bulk silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), or combinations thereof. The substrate105may also include a semiconductor-on-insulator substrate, such as Si-on-insulator (SOI), SiGe-on-insulator (SGOI), Ge-on-insulator (GOI) substrates. Referring to block14ofFIG.2AandFIGS.3A,3B, stacks of semiconductor layers are formed over the substrate105. The stacks of semiconductor layers include semiconductor layers110and semiconductor layers120alternating with each other. For example, a semiconductor layer110is formed over the substrate105; a semiconductor layer120is formed over the semiconductor layer110; and another semiconductor layer110is formed over the semiconductor layer120, so on and so forth. In some embodiments, epitaxial growth of semiconductor layers110and semiconductor layers120is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metalorganic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth process, or combinations thereof. In such embodiments, semiconductor layers110and semiconductor layers120can be referred to as epitaxial layers. In some embodiments, the deposition and growth of the semiconductor layers110and120implement precursor gases that include elements of the respective semiconductor layers. For example, the deposition of a silicon (Si) semiconductor layer may implement Si-containing precursors such as silicon tetrachloride (SiCl4), silicon dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), silane (SiH4), other suitable Si-containtain precursors, or combinations thereof. Moreover, the deposition of a silicon germanium (SiGe) semiconductor layer may implement a Si precursor, such as those listed above, and a germanium (Ge) precursor, such as isobutylgermane, alkylgermanium trichlorides, and dimethylaminogermanium trichloride, other suitable Ge-containtain precursors, or combinations thereof. As described in detail later, SiGe semiconductor layers (or sublayers) may have different Si concentrations (such as Si atomic percentages) and different Ge concentrations (such as Ge atomic percentages). This may be controlled by a flow rate ratio of the Si precursor flow rate to the Ge precursor flow rate. For example, to achieve a SiGe semiconductor layer where 50% of the total atoms are Si, and 50% of the total atoms are Ge, the flow rate ratio of the silicon precursor and the germanium precursor may be set at 1:1. For example, to achieve a SiGe semiconductor layer where 75% of the total atoms are Si and 25% of the total atoms are Ge, the flow rate ratio of the silicon precursor and the germanium precursor may be set at 3:1. As described in detail later, in some embodiments, the semiconductor layers110and120may have uniform compositions. Accordingly, the flow rates of the precursor gases remain unchanged during the epitaxy process. In some other embodiments, the semiconductor layers110and120may have varying compositions. Accordingly, the flow rates of the precursor gases vary as the deposition and growth process proceeds. Additional reactive gas or carrying gas may also be implemented to facilitate the deposition or growth of the semiconductor layers. As described further below, semiconductor layers120or portions thereof form channel regions of device100, and semiconductor layers110are replaced by other features of the device. In the depicted embodiment, the semiconductor layer stack includes three semiconductor layers110and three semiconductor layers120, configured to form three semiconductor layer pairs disposed over substrate105. After undergoing subsequent processing, such configuration will result in the device100having three channel layers (or channels). However, the present disclosure contemplates embodiments where semiconductor layer stack includes more or fewer semiconductor layers, for example, depending on a number of channels desired for device100or design requirements of device100. For example, the semiconductor layer stack can include two to ten semiconductor layers110and two to ten semiconductor layers120. In the depicted embodiment, the semiconductor layers110each have a substantially uniform thickness, referred to as the thickness300, while the semiconductor layers120each have a substantially uniform thickness, referred to as the thickness310. The thickness310may be the same as, or different from, the thickness300. The thickness300and thickness310are chosen based on fabrication and/or device performance considerations for device100. For example, thickness310can be configured to achieve desired thickness of channels of device100, thickness300can be configured to define a desired distance (or gap) between adjacent channels of device100(e.g., between semiconductor layers120). Both thickness300and thickness310can be configured to achieve desired performance of device100. In some embodiments, thickness300may be about 3 nm to about 15 nm; and thickness310may be about 3 nm to about 15 nm. The semiconductor layers110are configured to include materials different from that of the semiconductor layers120in order to achieve etching selectivity during subsequent processing. Generally, layers with different materials present different etch rates in a particular etching chemical (or chemical etchant, or etchant) in absence of other environmental factors (such as those described later). These etch rates are referred to herein as the intrinsic etch rates. As described in detail later, difference in intrinsic etch rates may also arise from layers having different material compositions (such as constituent atomic percentages) even though the materials (such as elements) are identical. However, such differences in intrinsic etch rates tend to be smaller than those caused by material differences. The intrinsic etch rates are determined by the layer materials (or material compositions), the etching chemical, and the etching parameters. Additionally, as described later, etch rates of particular layers may be perturbed (or changed) by environmental factors such that differences in actual etch rates are reduced or increased as compared to differences in intrinsic etch rates. In some embodiments, semiconductor layers110have a first etch rate (or first etch rates, as described in detail below) to an etching chemical; and semiconductor layers120have a second etch rate to the etching chemical, where the second etch rate is less than the first etch rate. In the depicted embodiment, semiconductor layers110and semiconductor layers120include different materials, for example, the semiconductor layers110contain silicon germanium (SiGe), while the semiconductor layers120contain silicon (Si). The compositions of the etching chemical and the etching parameters are configured to provide a Si etch rate that is less than a SiGe etch rate. In some embodiments, the semiconductor layers110each includes a multi-sublayer structure, for example, a three-sublayer structure. In the depicted embodiments ofFIGS.3A and3B, the semiconductor layers110each includes a sublayer110A formed on a semiconductor layer120(or, for the lowest semiconductor layer110, on the substrate105), a sublayer110B formed on the sublayer110A, and a sublayer110C formed on the sublayer110B. The sublayers110A,110B, and110C each include a same material (here, SiGe), but with different constituent atomic percentages (such as Ge atomic percentages and Si atomic percentages). This allows different etch rates to be achieved between the sublayers110A and110B, and between the sublayers110B and110C. As described in detail below, such etch rate differences allow the profile of the sidewall surfaces206w(seeFIG.1B) of the subsequently formed inner spacers to be controlled and modulated across the thickness dimensions of the sublayers110A,110B, and110C (such as along the Z-direction), which results in improved device performances. Meanwhile, etch rate differences arising out of differences in atomic percentages are generally much less pronounced than etch rate differences arising out of different materials. Accordingly, the etch rate of the semiconductor layers120remain much less than etch rates of each of the sublayers110A,110B, and110C. The integrity of the semiconductor layers120are thus maintained. The proper constituent atomic percentages may be determined based on criteria explained in detail later. In some embodiments, the sublayers110A may have a Ge atomic percentage of about 20% to about 60%; the sublayers110B may have a Ge atomic percentage of about 5% to about 50%; the sublayer110C may have a Ge atomic percentage of about 20% to about 60%. Similarly, sublayers110A and110C may have a Si atomic percentage different from sublayer110B. For example, the sublayer110A may have a Si atomic percentage of about 40% to about 80%; the sublayer110B may have a Si atomic percentage of about 50% to about 95%; the sublayer110C may have a Si atomic percentage of about 40% to about 60%. In some embodiments, the compositions of the sublayers110A are similar to or about the same as the compositions of the sublayers110C, but are different from the composition of the sublayers110B. In some embodiments, a difference (Δ1) between the Ge atomic percentage in the sublayer110A (or the sublayer110C) (“Ge atom % of110A/C”) and the Ge atomic percentage in the sublayer110B (“Ge atom % of110B”), as measured against the total atomic numbers of the respective semiconductor sublayer, is about 5% to about 15% (i.e., Δ1=Ge atom % of110A/C−Ge atom % of110B=about 5% to about 15%). In some embodiments, a ratio (γ1) of the Ge atomic percentage in the sublayer110A (or the sublayer110C) to the Ge atomic percentage in the sublayer110B is about 1.1 to about 7.0 (i.e., γ1=Ge atom % of110A/C:Ge atom % of110B=about 1.1 to about 7.0). For example, the ratio (γ1) may be from about 1.2 to about 3.0 (i.e., γ1=Ge atom % of110A/C:Ge atom % of110B=about 1.2 to about 3.0). If the difference Δ1is too small (such as less than about 5%), or the ratio γ1 is too small (such as less than about 1.1), there may be insufficient difference between the intrinsic etch rates of the sublayers such that the ability to modulate the profiles of the inner spacers may be limited. If the difference Δ1is too large (such as greater than about 15%), or the ratio γ1 is too large (such as greater than about 7.0), epitaxy dislocations or stacking faults may be formed at the interface of the sublayers, which may degrade device performance. In some embodiments, the sublayers110A may have a Ge atomic percentage of about 30% to about 50%; the sublayers110B may have a Ge atomic percentage of about 15% to about 35%; the sublayer110C may have a Ge atomic percentage of about 30% to about 50%. The sublayers110A,110B, and110C may have the same or different thicknesses. The sum of the thicknesses of the sublayers110A,110B, and110C equals the thickness300of the semiconductor layer110. In the depicted embodiment, the sublayers110A and the sublayers110C have the same thickness, referred to as thickness320, and the sublayer110B has a thickness different from the thickness320, referred to as the thickness330. In some embodiments, the thickness330is greater than the thickness320. In some embodiments, the thickness320may be about 0.5 nm to about 2.5 nm; and the thickness330may be about 2.5 nm to about 5 nm. In some embodiments, a thickness ratio (γ2) of the thickness320to the thickness330is about 0.1 to about 1. As described above, the material composition differences allow modulation of the sidewall profiles of the inner spacers across the thickness dimension of the sublayers110A,110B, and110C. If the ratio γ2 is too small, such as smaller than 0.1, the contribution of the sublayers110A and110C to the overall sidewall profile of the inner spacers may be too small to cause any meaningful improvements. In other words, any issues observed in a single layer semiconductor layer110will be manifested in the sublayer110B itself. Conversely, if the ratio γ2 is too large, such as greater than 1, the beneficial effect of the different material compositions may be diluted across the thickness of the sublayers110A and110C. In other words, any issues observed in a single layer semiconductor layer110will be manifested in the sublayers110A and110C themselves. As described above, the formation of the semiconductor layers110and120may implement precursor gases. In the depicted embodiments, the semiconductor layers120include a uniform Si material. Accordingly, the precursor gas implemented for the formation of the semiconductor layers120includes a Si precursor gas or Si precursor gases. Moreover, the semiconductor layers110include SiGe where atomic percentages of Si and Ge vary in different sublayers110A,110B, and110C. Accordingly, the precursor gases implemented during the formation of the semiconductor layers110may include a Si precursor gas and a Ge precursor gas where the flow rates are adjusted throughout the deposition or the growth process, to provide different flow rate ratios that result in different atomic percentages in different sublayers. For example, the flow rate of the Ge precursor gas and the flow rate of the Si precursor gas are first adjusted such that the flow rate ratio provides for (or matches) the target ratio between the Ge atomic percentage and the Si atomic percentage for the sublayers110A. When the target thickness of the sublayer110A is reached, the flow rates of the Ge precursor gas and the Si precursor gas are adjusted such that the flow rate ratio provides for (or matches) the target ratio between the Ge atomic percentage and the Si atomic percentage for the sublayers110B. And when the target thickness of the sublayer110B is reached, the flow rates of the Ge precursor gas and the Si precursor gas are further adjusted such that the flow rate ratio provides for (or matches) the target ratio between the Ge atomic percentage and the Si atomic percentage for the sublayers110C. In the depicted embodiments, this leads to a first decrease in the flow rate ratio of the Ge precursor gas to the Si precursor gas, and then an increase of the flow rate ratio. For example, the flow rate ratio is maintained at rAduring the formation of the sublayers110A, changed to rBduring the formation of the sublayer110B, and further changed to rCduring the formation of the sublayers110C. The ratios rA, rB, and rCdo not change during the course of the deposition or growth. In some embodiments, a ratio of rAto rBand rCto rBmay be about 1.1 to about 7.0, such as about 1.2 to about 3.0, so as to provide the desired ratio of Ge atomic percentage ratios between the sublayers as described above. In some embodiments, the changes in the flow rate ratios may be abrupt, resulting in the sublayers110A,110B, and110C having clear boundaries. While the above disclosure describes the sublayers110A,110B, and110C each include SiGe and varying only in constituent atomic percentages, they may alternatively include different materials, provided that those materials provide different etch rate amongst themselves, which are also substantially different from the etch rate of the Si material of the semiconductor layers120. FIGS.3A and3Babove present one embodiment of the method10of the present disclosure to achieve the control over the sidewall profiles of subsequently formed inner spacers. Alternatively, similar control may be achieved by engineering the semiconductor layers110to be a single layer having a gradient structure. Referring toFIGS.4A and4B, the single layer semiconductor layers110each includes a region110A′ over a semiconductor layer120(or for the lowest semiconductor layer110, over the substrate105), a region110B′ over the region110A′, and a region110C′ over the region110B′. The regions110A′,110B′, and110C′ may each have varying compositions throughout their respective thickness dimensions (such as along the Z-direction). In some embodiments, the regions110A′,110B′, and110C′ have the same thicknesses320,330, and320as the sublayers110A,110B, and110C (FIG.3B), respectively. Moreover, the composition may vary continuously and gradually across the adjacent regions, such as from the region110A′ to the region110B′, and from the region110B′ to the region110C′. Furthermore, the variations across an interface between two regions may be consistent (such as in a same direction) as the variation within the regions close to the interface. In some embodiments, boundaries (or interfaces) between the regions may be defined by the plane at which an atomic percentage of a constituent atom (such as Ge) changes fastest against the Z-direction. In other embodiments, however, there may be less clear boundaries between the first region110A′ and the second region110B′, or between the second region110B′ and the third region110C′. In such embodiments, the regions110A′,110B′, and110C′ are only assigned based on the thickness320and thickness330to aid the descriptions.FIGS.4A and4Bmay use the same reference numerals as those ofFIGS.3A and3Bto describe similar features for the purpose of simplicity and clarity. In the depicted embodiments, the region110A′, the region110B′, and the region110C′ each includes silicon germanium. Moreover, the average composition (for example, the average Ge atomic percentage and the average Si atomic percentage) of the region110A′ resembles that of the sublayer110A ofFIGS.3A and3B. Accordingly, the region110A′ may include an average Ge atomic percentage of about 20% to about 60% and an average Si atomic percentage of about 40% to about 80%. The average composition of the region110B′ resembles that of the sublayer110B ofFIGS.3A and3B. Accordingly, the region110B′ may include an average Ge atomic percentage of about 5% to about 50% and an average Si atomic percentage of about 50% to about 95%. The average composition of the region110C′ resembles that of the sublayer110C ofFIGS.3A and3B. Accordingly, the region110C′ may include an average Ge atomic percentage of about 20% to about 60% and an average Si atomic percentage of about 40% to about 80%. In some embodiments, there is a parabolic distribution of the Ge atomic percentage within the semiconductor layer110with the vertex (lowest point) of the distribution being located at the mid-height of the semiconductor layer110, and the highest point of the distribution being located at the interfaces of the semiconductor layer110with the semiconductor layers120(or the substrate105). In addition, there is another parabolic distribution of Si atomic percentage that is opposite to the distribution of the Ge atomic percentage. The formation of the gradient structure of the semiconductor layer110generally resembles that described above with respect toFIGS.3A and3B. For example, the flow rate of the Ge precursor gas and the Si precursor gas are adjusted such that the flow rate ratio provides for the target ratio of the Ge atomic percentage to the Si atomic percentage for the particular region being formed. As the deposition or growth transitions from one region to another, the flow rates are adjusted such that the flow rate ratio changes accordingly. This similarly leads to first decrease of the flow rate ratio of the Ge precursor gas to the Si precursor gas, and then increase of the flow rate ratio. Unlike the embodiment described with respect toFIGS.3A and3B, the flow rate ratios are not changed abruptly at the interfaces between sublayers, but rather continuously and gradually within regions and across the regions. This results in a gradient structure where constituent atomic percentages changes continuously and gradually. For example, during the forming of the region110A′, the flow rate ratio rAof the Ge precursor gas to the Si precursor gas continuously and gradually decreases. At the conclusion of the formation of the region110A′, the flow rate ratio rAcontinuously and gradually decreases so the process transitions into the forming of the region110B′. During the forming of the region110B′, the flow rate ratio rBfirst continuously decreases until a minimum is reached at the mid-height of the region110B′. Then, the flow rate ratio rBgradually and continuously increases until the desired thickness of the region110B′ is reached. During the formation of the region110C′, the flow rate ratio rCcontinuously increases until the desired thickness of the region110C′ is reached. Therefore, the flow rate ratios rAand rBare equal at the interface between the regions110A′ and110B′, and the flow rate ratios rBand rCare equal at the interface between the regions110B′ and110C′. In some embodiments, the changes of the flow rate ratios against the thickness dimension of the semiconductor layer110may follow a parabolic curve, such that the Ge atomic percentage is at the highest at the interface with the semiconductor layers120(or the substrate105) and at the lowest at the mid-height of the semiconductor layer110. In some embodiments, the curve representing the change of the flow rate ratios against the thickness dimension before and after reaching the mid-height of the regions110B′ may form a mirror image to each other. The configuration ofFIGS.4A and4Bis described above as the semiconductor layer110having a gradient composition. Alternatively, this configuration may also be viewed as the semiconductor layer110having an infinite number of sublayers, each sublayer overlaying another sublayer, with the lowest sublayer overlaying the semiconductor layer120(or the substrate105for the lowest semiconductor layer110), and with the highest sublayer on a bottom surface of another semiconductor layer120. Accordingly, the configuration inFIGS.4A and4Brepresents the upper limit of the number of sublayers that may be present within the semiconductor layer110. In that sense, the configuration inFIGS.3A and3Brepresents the lower limit of the number of sublayers that may be present within the semiconductor layer110. In some embodiments, there may be any number of sublayers between these two limits (that is between three and infinite) that constitute the semiconductor layer110. For example, there may be five sublayers within the semiconductor layer110. In furtherance of the example, a first sublayer overlays the semiconductor layer120(or the substrate105) and may have a first composition (such as a uniform or constant composition) of Si and Ge; a second sublayer overlays the first sublayer and may have a second composition of Si and Ge; a third sublayer overlays the second sublayer and may have a third composition of Si and Ge; a fourth sublayer overlays the third sublayer and may have a fourth composition of Si and Ge; and a fifth sublayer overlays the fourth sublayer and may have a fifth composition of Si and Ge. In some embodiments, the first Ge atomic percentage of the first sublayer is greater than the second Ge atomic percentage of the second sublayer, which is greater than the third Ge atomic percentage of the third sublayer. Moreover, the third Ge atomic percentage of the third sublayer is less than the fourth Ge atomic percentage of the fourth sublayer, which is less than the fifth Ge atomic percentage of the fifth sublayer. For example, there may be six sublayers within the semiconductor layer110. In furtherance of the example, a first sublayer overlays the semiconductor layer120(or the substrate105) and may have a first composition (such as a uniform or constant composition) of Si and Ge; a second sublayer overlays the first sublayer and may have a second composition of Si and Ge; a third sublayer overlays the second sublayer and may have a third composition of Si and Ge; a fourth sublayer overlays the third sublayer and may have a fourth composition of Si and Ge; a fifth sublayer overlays the fourth sublayer and may have a fifth composition of Si and Ge; and a sixth sublayer overlays the fifth sublayer and may have a sixth composition of Si and Ge. In some embodiments, the first Ge atomic percentage of the first sublayer is greater than the second Ge atomic percentage of the second sublayer, which is greater than the third Ge atomic percentage of the third sublayer. The third Ge atomic percentage of the third sublayer may be about the same as the fourth Ge atomic percentage of the fourth sublayer. Moreover, the fourth Ge atomic percentage of the fourth sublayer is less than the fifth Ge atomic percentage of the fifth sublayer, which is less than the sixth Ge atomic percentage of the sixth sublayer. Alternatively, there may be any other number (greater than 2) of sublayers, such as four sublayers, seven sublayers, eight sublayers, etc. The stacks of semiconductor layers described above (either as illustrated inFIGS.3A and3B, or alternatively as illustrated inFIGS.4A and4B) are patterned into a plurality of fin structures, for example, fin structures108, such that they each have a width dimension along the Y-direction, a height dimension along the Z-direction, and each extending along and have a length dimension along the X-direction. The fin structures108may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins. The patterning may utilize multiple etching processes which may include a dry etching and/or wet etching. The fin structures108may have lateral widths that are the same between each other or different from each other. Referring to block16ofFIG.2AandFIG.5, gate structures250are formed over a portion of each of the fin structures108. In some embodiments, the gate structures250are also formed over the isolation features150in between adjacent fin structures. The gate structures250may be configured to extend lengthwise in parallel to each other, for example, each along the Y-direction. In some embodiments, the gate structures250each wrap around the top surface and side surfaces of each of the fin structures108. The gate structures250includes dummy gate stacks240and gate spacers200and202. The dummy gate stacks240may include polysilicon or any other suitable materials. In some embodiments, the gate structures250also include one or more mask layers (not shown), which are used to pattern the dummy gate stacks240. The dummy gate stacks240may undergo a gate replacement process through subsequent processing to form metal gates, such as a high-k metal gate, as discussed in greater detail below. The dummy gate stacks240may be formed by a procedure including deposition, lithography, patterning, and etching processes. The deposition processes may include CVD, ALD, PVD, other suitable methods, and/or combinations thereof. Gate spacers are formed on the sidewalls of the dummy gate stacks240and the top layer of the semiconductor layers120. Gate spacers may include a single layer or a multi-layer structure. For example, in the depicted embodiment, a gate spacer layer200is formed over the top surface of the device100, and a gate spacer layer202is formed over the gate spacer layer200. The gate spacer layers200and202may each include silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon doped oxide, nitrogen doped oxide, porous oxide, or combinations thereof. In some embodiments, the gate spacer layers200and202may collectively has a thickness in the range of a few nanometers (nm). In some embodiments, the gate spacer layers200and202may be formed by depositing a spacer layer (containing the dielectric material) over the dummy gate stack240, followed by an anisotropic etching process to remove portions of the spacer layer from the top surfaces of the dummy gate stacks240. After the etching process, portions of the spacer layer on the sidewall surfaces of the dummy gate stacks240substantially remain and become the gate spacer layers200or202. In some embodiments, the anisotropic etching process is a dry (e.g. plasma) etching process. Additionally or alternatively, the formation of the gate spacer layers200and202may also involve chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable methods. Processing continues to form source/drain trenches for source/drain features. Referring to block18ofFIG.2AandFIG.6, portions of the fin structure108adjacent to and exposed by the gate structures250(e.g. in the source/drain regions102) are at least partially recessed (or etched away) by process500to form the source/drain trenches204. Meanwhile, the portions of the fin structure108underneath the gate structures250remain intact. Additional mask elements (not shown) may also be employed to protect areas not designed to be removed during the process500. In the depicted embodiment, the process500removes not only the exposed portions of fin structure108, but also a portion of the underlying substrate105. Accordingly, the source/drain trenches204extends below the top surface of the substrate105. In some embodiments (not shown), the process500removes only the exposed portions of the fin structure108, such that the top surface of the substrate105is exposed in the source/drain trenches204. Accordingly, the source/drain trenches204extends to a depth along the top surface of the substrate105. In some other embodiments (not shown), the process500removes only some, but not all, of the fin structure108adjacent the gate structures250, such that the substrate105is not exposed in the source/drain trenches204. Accordingly, the source/drain trenches204extends to a depth above the top surface of the substrate105. The process500may include multiple lithography and etching steps, and may use any suitable methods, such as dry etching and/or wet etching. The formation of the source/drain trenches204exposes sidewalls of the stack of semiconductor layers110and120. Referring to block20ofFIG.2AandFIGS.7A and7B, portions of the semiconductor layers110are removed through the exposed sidewall surfaces in the source/drain trenches204via a selective etching process, such as process520. The process520recesses the semiconductor layers110in a lateral direction along the X-direction and thus can be referred to as lateral etching process520or lateral recessing process520. The process520is designed to remove portions of the semiconductor layers110but only minimally affect (or not affect) the semiconductor layers120. For example, two side portions (or interchangeably referred to as end portions) of the semiconductor layers110may be removed to form openings205while the side portions of the semiconductor layers120directly above and below the openings205are substantially preserved. In some embodiments, those side portions of the semiconductor layers120may have their thicknesses (along the Z-direction) slightly reduced (such as by about 1% to about 10%) during the process520. Moreover, sidewall surfaces of the semiconductor layer120may be slightly altered during the process520. The selective etching process may be any suitable processes. In the depicted embodiment, the semiconductor layers120include Si and the semiconductor layers110include SiGe. The process520may be a wet etching process, such as a Standard Clean 1 (SC-1) solution. The SC-1 solution includes ammonia hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). The SiGe-based semiconductor layers110may be etched away in the SC-1 solution at a substantially faster rate than the Si-based semiconductor layers120. The etching duration is adjusted such that the size of the removed portions of SiGe layers is controlled. As a result, desired portions of the semiconductor layers110are removed while the semiconductor layers120are only minimally affected (or not affected). The optimal condition may be reached by additionally adjusting the etching temperature, dopant concentration, as well as other experimental parameters, taking into account factors to be discussed below. FIGS.7A and7Billustrate situations where the semiconductor layers110each include three sublayers110A,110B, and110C (that is, the embodiment illustrated inFIGS.3A and3B). The sublayers110A are etched by a different amount than the sublayer110B; and the sublayers110B are etched by a different amount than the sublayer110C. Accordingly, the etched semiconductor layer110and the openings205each have a sidewall surface400(or interface400) that has a segmented or semi-curved profile. The sidewall surface400later becomes a sidewall surface206wof the subsequently formed inner spacers206(seeFIGS.10A,10B). In the depicted embodiment, after the processing520, the sublayer110A is recessed by at least a distance of distance350; the sublayer110B is recessed by a distance of distance360; and the sublayer110C is recessed by at least a distance of distance350. As illustrated inFIG.7B, sidewall surfaces of the sublayer110A of the semiconductor layer110interfaces with the semiconductor layer120at interface line420(extending along the Y-direction). The distance along the X-direction between the interface line420and the YZ plane (along which the sidewall surface402of the semiconductor layer120extends) is the distance350; and the maximum distance along the X-direction between the sublayer110B and the YZ plane (along which the sidewall surface402extends) is the distance360. As illustrated, the distance350is less than the distance360. Meanwhile, as described above, the semiconductor layers120are largely preserved during the process520due to their superior etching resistance to the etching chemical. In the depicted embodiments, the profiles of the sidewall surfaces402are substantially unchanged. However, in some embodiments, the etching chemical may nevertheless affect the profile of the sidewall surfaces402of the semiconductor layers120. For example, corners of the semiconductor layers120may be slightly etched during the process520. Accordingly, after the process520, the semiconductor layers120may have rounded (or curved) surfaces. In some embodiments, different portions of the sublayer110A are etched by a different amount. For example, the bottom portion of the sublayer110A (such as the portion at the interface with the semiconductor layer120or the substrate105) is etched by the distance350. However, the top portion of the sublayer110A (such as the portion at the interface with the sublayer110B) is etched by the distance360. The portions between the top portions and the bottom portions are etched by an amount between the distance350and distance360. The etched amount changes gradually and continuously between adjacent portions throughout the thickness dimension of the sublayer110A (along the Z-direction). Without being limited by theory, this may be because the semiconductor layer120functions as a physical barrier that partially blocks diffusions of the etching chemical from approaching a particular region of the sublayer110A. The closer the particular region of the sublayer110A is to the physical barrier, the less diffusion of etching chemical occurs. Because the probability of being etched (hence the etch rate) scales with the diffusion of the etching chemical, the regions of the sublayer110A that is closer to the semiconductor layer120is etched less than regions that are further away. This produces a sidewall surface400A that is canted from the vertical direction (such as the Z-direction). This etch rate difference between different regions of the sublayer110A is not related to the intrinsic properties of the material or material compositions. For example, the materials and material compositions of these regions may be uniform and the same as each other. Rather, this etch rate difference is an effect of the environmental effect around the target for the etching process. In other words, the different magnitude of environmental effect experienced by different portions of the sublayer110A causes the otherwise same etch rates to decrease to a different extent, which results in the canted sidewall profile of the sidewall surface400A. In the depicted embodiments, the sidewall surface400A is substantially straight. However, in some embodiments, the sidewall surface400A may also be curved, depending on the adopted etching conditions. In some embodiments, a tangential direction of the sidewall surfaces400A of the sublayer110A spans an angle α that is less than 90° from the top surface of the adjacent semiconductor layer120. For example, the angle α may be about 30° to about 90°. The angle α may be at least partially determined by the materials of the sublayer110A and the etching chemical. Furthermore, the angle α may be tuned by adjusting the etching parameters, such as etching temperature, etching gas flow rate, other suitable etching parameters, or combinations thereof. If the angle α is too small, such as less than 30°, the curvature of the sidewall surfaces400of the etched semiconductor layer110(and that of the sidewall surfaces of the subsequently formed inner spacer) may be too large such that damage-prone areas may be formed. Conversely, the sidewall surfaces of the sublayer110A and that of the semiconductor layer120may present diffusional restrictions (or serving as physical barriers) to any materials deposited into the angled area between them. If the angle α is too large, such as greater than 90°, such diffusional restrictions may be too severe for the tip area between the sidewalls to be properly filled. Accordingly, voids may form therein which has been shown to cause increased resistances. The angle α in conjunction with the thickness of the sublayer110A define the footing region206f. In the depicted embodiment, the footing region206fhas a lateral width372at the interface between the sublayer110A and the semiconductor layer120. The lateral width372equals to the difference between the distance350and the distance360. In some embodiments, a ratio of the lateral width372to the thickness320of the sublayer110A (seeFIG.3B) is about 0.5 nm to about 2 nm. This ratio is correlated with the magnitude of the angle α. Similarly, the sublayer110C has a sidewall surface400C. The sidewall surfaces400C may also be canted for reasons similar to that for the sublayer110A. For example, the sidewall surfaces400C form another footing region206fat the interface with another semiconductor layer120. In some embodiments, the sidewall surfaces400C may span the angle α from the top surface of the adjacent semiconductor layer120. However, the sidewall surfaces400C may alternatively span a different angle from the bottom (and top) surface of the adjacent semiconductor layer120. In the depicted embodiments, the sublayers110A,110B, and110C are configured such that all portions of the sublayer110B are sufficiently far away from any physical barriers (such as the adjacent semiconductor layers120). Accordingly, the physical barrier effect described above due to the presence of the semiconductor layers120causes only minimal variations in the etched amount for different portions of the sublayer110B. The sublayer110B thus has a sidewall surface400B that is substantially vertical or close to vertical. However, in other embodiments, the sublayers110B may be configured such that the top and bottom portions of the sublayer110B are still affected by the physical barrier effect, albeit to an extent less than portions of the sublayers110A and110C. Accordingly, the sublayer110B may still have a curved sidewall surface400B. For example, the top and bottom portions of the sublayer110B are etched by a smaller amount than the middle portion of the sublayer110B. In other words, the sidewall surface of the sublayer110B has a concaved profile with the middle portion of the profile protruding from the openings205into the remaining portions of the sublayer110B. In such embodiments, the distance360refers to the maximum distance along the X-direction between the sidewall surface of the sublayer110B and the YZ plane along which the sidewall surfaces402extends. This distance360corresponds to the width of the openings205at the mid-height level. Other portions (such as top and bottom portions) of the openings205have widths less than the distance360and greater than the distance350. The sidewall surfaces400A,400B, and400C collectively form the sidewall surface400that later becomes the sidewall surfaces206wof the subsequently formed inner spacer206. As described above, it may be beneficial to form sidewall surfaces206whaving smaller curvatures. In some embodiments, this is achieved by configuring the sublayers110A and110C with higher Ge atomic percentages. For example, the subsequent etching process may be configured to provide etch rates that depends on the Ge atomic percentages. Therefore, sublayers110A and110C having greater Ge atomic percentages are etched at a rate faster than sublayer110B having a smaller Ge atomic percentage. Accordingly, the intrinsic etch rate for the sublayers110A and110C are greater than the intrinsic etch rate for the sublayer110B. Meanwhile, the sublayers110A and110C are closer to the physical barrier (i.e. semiconductor layers120and substrate105). Accordingly, environmental factors (such as the physical location) affect the sublayers110A and110C more than they affect the sublayer110B. The actual etch rate of a sublayer is a combination of the intrinsic etch rate and the environmental factors. In the depicted embodiment, the environmental effect dominates over the effect of the increased Ge atomic percentages, such that sublayers110A and110C are etched to a smaller extent than the sublayer110B. Nevertheless, at least a portion of the environmental effect is offset by the effect of the increased Ge atomic percentage. Therefore, as compared to a semiconductor layer110that has uniform Ge atomic percentage (e.g. an atomic percentage that corresponds to the average Ge atomic percentages of sublayers110A,110B, and110C), the curvature of the sidewall surfaces206wis reduced and the profile of206wis more rectangular (or more square). In the depicted embodiment, a ratio of the distance350to the distance360is about 0.65 to about 1. This ratio provides a measure for the curvature of the sidewall surfaces400of the etched semiconductor layers110. This curvature in turn determines the curvature of the sidewall surfaces206wof the subsequently formed inner spacers206. As described above and discussed in more detail later, the inner spacers206with more square-like profiles provide for better protection of source/drain features during channel release processes and better isolation between source/drain features and metal gates for TDDB (Time Dependent Dielectric Breakdown) performance concerns. If the ratio is too small, such as less than 0.65, the curvature may be too large (or, the sidewall surface may be too rounded) such that the subsequently formed device may not provide sufficient isolation between source/drain features and metal gates. Conversely, if the ratio is too large, such as greater than 1, voids may be formed in the tip areas between the sidewall surface of the etched semiconductor layer110and the top or bottom surface of the semiconductor layers120and such voids may not be easily filled with gate dielectric and gate metals and may cause non-uniformity among transistors. The ratio of the distance350to the distance360may be determined collectively by the thicknesses of the sublayers, the difference in the material composition between the sublayer110B and that of the sublayer110A or the sublayer110C, in conjunction with the etching chemicals and conditions. Accordingly, referring toFIG.7C, by engineering the thicknesses and the material compositions of the sublayers and choosing appropriate etching chemicals and conditions, proper profile of the sidewall surfaces206wand the proper profile of the footing region206fmay be achieved. As described above, alternative to the three-sublayer structure illustrated inFIGS.7A and7B, a single layer semiconductor layer110that has a gradient structure (such as those illustrated inFIGS.4A and4B) may be implemented to achieve the inner spacers206that have sidewalls with the reduced curvature. In such embodiments, the processing520results in a device100that has a structure illustrated inFIGS.8A and8B. The structures ofFIGS.8A and8Bgenerally resemble those already described above with respect toFIGS.7A and7B. The structures differ here in that the material compositions vary gradually and continuously across the thickness dimension of the semiconductor layer110. Accordingly, the amount of etching also varies gradually and continuously across the thickness dimension of the semiconductor layer110. As a result, the sidewall surfaces of the region110A′, sidewall surfaces of the region110B′, and the sidewall surfaces of the region110C′ transitions gradually and continuously from one region to the other without sharp interfaces. In other words, no clearly segmented sidewall surface portions like400A,400B, and400C ofFIGS.7A and7Bare produced. Additionally, the openings205have substantially smooth and curved sidewall surfaces. As described above, the profile of the sidewall surfaces400of the etched semiconductor layer110determines the profile of the sidewall surfaces206wof the subsequently formed inner spacers206(seeFIGS.10A,10B). In some embodiments, sidewall surfaces of the region110A′ of the semiconductor layer110interfaces with the semiconductor layer120at interface line420(extending along the Y-direction). The distance along the X-direction between the interface line420and the YZ plane along which the sidewall surface402of the semiconductor layer120extends is the distance350; and the maximum distance along the X-direction between the region110B′ and the sidewall surface402is the distance360. Similar to that described above with respect toFIGS.7A and7B, a ratio of the distance350to distance360is about 0.65 to about 1. Moreover, the sidewall surface of the region110A′ may have a tangential direction at the interface line420that spans an angle α from the top (or bottom) surface of the semiconductor layer120. Also similar to that described above with respect toFIGS.7A and7B, the angle α may be about 30° to about 90°. Moreover, footing regions206fare also formed at the interface between the regions110A′ and the semiconductor layer120(or the substrate105) or between the regions110C′ and the semiconductor layer120(or the substrate105). The footing regions206fmay be similar to the foot regions206fdescribed above with respect toFIGS.7A and7B. However, the profiles of the footing regions206fmay be different. For example, rather than having a substantially straight sidewall surface, the footing regions206fhere may have a curved sidewall surface, or vice versa. Alternatively, footing regions206fdescribed inFIGS.7A and7Band inFIGS.8A and8Bmay both be curved although with different curvatures. As described above, configurations that include more than three sublayers may similarly adopted by reference to the methods described herein. In the depicted embodiments, the semiconductor layers120include Si and the semiconductor layers110include SiGe. In another embodiment, the semiconductor layers120include SiGe and the semiconductor layers110includes Si. In such an embodiment, in order to achieve the designed device structure, the selective etching may be designed such that SiGe is etched at an etch rate less than Si. For example, a cryogenic deep reactive ion etching (DRIE) process may be used to selectively etch away the Si-based semiconductor layer110. For example, the DRIE process may implement a sulfur hexafluoride-oxygen (SF6—O2) plasma. The optimal condition may be reached by adjusting the etching temperature, the power of the Inductively Coupled Plasma (ICP) power source and/or Radio Frequency (RF) power source, the ratio between the SF6concentration and the O2concentration, the dopant (such as boron) concentrations, as well as other experimental parameters. For example, the etch rate of a Si-based semiconductor layer110using a SF6—O2plasma (with approximately 6% O2) may exceed about 8 μm/min at a temperature of about −80° C.; while the SiGe-based semiconductor layers120are not substantially affected during the process. Processing continues to form various features of the device100. Subsequent illustrations of the method proceed from theFIGS.8A and8B, using the single layer semiconductor layer110with gradient structure as an example. However, the same processing method applies to other alternative methods as well. Referring to block22ofFIG.2BandFIGS.9A and9B, a dielectric material306is deposited into both the source/drain trenches204and the openings205(compareFIG.8A). The dielectric material306may be selected from SiO2, SiON, SiOC, SiOCN, or combinations thereof. In some embodiments, the proper selection of the dielectric material may be based on its dielectric constant (as described later). The deposition of the dielectric material306may be any suitable methods, such as CVD, PVD, PECVD, MOCVD, ALD, PEALD, or combinations thereof. In the depicted embodiment, the dielectric material306may have a top surface that extends along a top surface of the dummy gate stack240. In other embodiments, the dielectric material306may have a top surface that extends above the top surface of the dummy gate structure240, and a CMP process may be performed to planarize the top surfaces of the device, and to expose the top surfaces of the dummy gate stack240. Referring toFIGS.10A and10B, the dielectric material306is partially etched back by process540to form new source/drain trenches208. The partial etching-back completely removes the dielectric materials306within the original source/drain trenches204(compareFIG.6), and removes a portion, but not all, of the dielectric materials306within the original openings205(compareFIG.8A). The dielectric materials306remaining in the openings205become the inner spacers206. Accordingly, the inner spacers206are formed between vertically adjacent semiconductor layers120and on sidewall surfaces of the etched semiconductor layers110. In an embodiment, the etching-back is a self-aligned anisotropic dry-etching process, such that the gate spacer layers200or202are used as the masking element. Alternatively, a different masking element (e.g. a photoresist) may be used. As described above, the inner spacers206interfaces with the etched semiconductor layers110at the interface400. Accordingly, the interface400becomes a sidewall surface206wof the inner spacers206. Additionally, the inner spacers206have a new sidewall surface430exposed in the source/drain trenches208. The distance between the sidewall surfaces400and430defines the lateral width of the inner spacers206. The new sidewall surface430may be of a same or different profile as that of the sidewall surface400. When the sidewall surfaces400and430have different profiles, the inner spacers206may have varying lateral widths at different heights of the inner spacers206along the Z-direction. For example, a top portion and a bottom portion of the inner spacers206may each have a lateral width370at their respective interfaces with the semiconductor layers120(or the substrate105); while a middle portion of the inner spacers206may have a lateral width380. In some embodiments, the lateral width380may be greater than the lateral width370. In an embodiment, the lateral width370may be about 5 nm to about 7 nm, and the lateral width380of about 5.5 nm to about 11 nm. Moreover, a ratio of the lateral widths370to380may be about 0.65 to about 1. Similar to the ratio of the distance350to the distance360described above, this ratio provides another measure for the curvature of the sidewall surfaces206w. The greater the ratio is (such as approaching 1), the smaller the curvatures are. Sidewall surfaces206whaving a smaller curvature (or square-like profile) provide for better protection of source/drain features during channel release processes and better isolation between source/drain features and metal gates for TDDB performance concerns. If the ratio is too small, such as less than 0.65, the curvature may be too large (or, the sidewall surface may be too rounded) such that the subsequently formed device may not provide sufficient isolation between source/drain features and metal gates. Conversely, if the ratio is too large, such as greater than 1, voids may be formed in the tip areas between the sidewall surface of the etched semiconductor layer110and the top or bottom surface of the semiconductor layers120and such voids may not be easily filled with gate dielectric and gate metals and may cause non-uniformity among transistors. The ratio of the lateral widths370to380is determined collectively by the distance350, the distance360, the spacer materials of the inner spacers206and the conditions for the etch-back process540. Accordingly, the ratio of the lateral widths370to380may be adjusted through the adjustment of the distances350or distance360. Referring to block24ofFIG.2BandFIG.11, epitaxial source/drain features210are formed in the source/drain trenches208. Accordingly, the epitaxial source/drain features210interface with the inner spacers206at the sidewall surfaces430. Multiple processes, including etching and growth processes, may be employed to grow the epitaxial source/drain features210. In the depicted embodiment, the epitaxial source/drain features210have top surfaces that extend higher than the top surface of the topmost semiconductor layer120. However, in other embodiments, the epitaxial source/drain features210may alternatively have top surfaces that are about even with the top surface of the topmost semiconductor layer120. In some embodiments, the epitaxial source/drain features210may merge together, for example, along the Y-direction (see e.g.,FIG.1A), to provide a larger lateral width than an individual epitaxial source/drain feature. In some embodiments, the epitaxial source/drain features210are configured to be part of the PMOS transistor. Accordingly, the epitaxial source/drain features210may include any suitable p-type semiconductor materials, such as Si, SiGe, Ge, SiGeC, or combinations thereof. In some embodiments, the epitaxial source/drain features210are configured to be part of the NMOS transistor. Accordingly, the epitaxial source/drain features210may include any suitable n-type semiconductor materials, such as Si. The epitaxial source/drain features210may further be doped in-situ or ex-situ. For example, the epitaxially grown SiGe source/drain features of a PMOS may be doped with boron (B) to form Si:Ge:B source/drain features; and the epitaxially grown Si source/drain features of an NMOS may be doped with carbon to form silicon:carbon (Si:C) source/drain features, doped with phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (Si:C:P) source/drain features. One or more annealing processes may be performed to activate the dopants in the epitaxial source/drain features210. The annealing processes may comprise rapid thermal annealing (RTA) and/or laser annealing processes. As illustrated inFIG.11, each pair of epitaxial source/drain features210are connected by multiple semiconductor layers120, which serve as the carrier conduit between the epitaxial source/drain features210during the operation. Referring to block26ofFIG.2Band toFIG.12, an ILD layer230is formed over the epitaxial source/drain features210, as well as over the isolation features150(seeFIG.1A). The ILD layer230may also be formed in between the adjacent gate structures250along the X-direction, and in between the adjacent epitaxial source/drain features210along the Y-direction. The ILD layer230may include a dielectric material, such as a high-k material, a low-k material, or an extreme low-k material. For example, the ILD layer230may include SiO2, SiOC, SiON, or combinations thereof. The ILD layer230may include a single layer or multiple layers, and may be formed by a suitable technique, such as CVD, ALD, and/or spin-on techniques. After forming the ILD layer230, a CMP process may be performed to remove excessive ILD layer230and planarized the top surface of the ILD layer230. Among other functions, the ILD layer230provides electrical isolation between the various components of the device100. In some embodiments, a contact etch stop layers220is formed, prior to the forming of the ILD layer230, over the epitaxial source/drain features210, as well as gate spacer layers200and/or202. The etch-stop layer protects the underlying features from subsequent etching processes. Referring to block28ofFIG.2Band toFIG.12, the dummy gate stacks240are selectively removed in process560from the gate structures250. The removal of the dummy gate stacks240creates gate trenches242, which expose the respective top surfaces and the side surfaces of the semiconductor stacks (along the Y direction). The process560may be selected from any suitable lithography and etching processes. In some embodiments, the lithography process may include forming a photoresist layer (resist), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element, which exposes a region including the dummy gate stacks240. Then, the dummy gate stacks240are selectively etched through the masking element. In some other embodiments, the gate spacer layers200and/or202may be used as the masking element or a part thereof. In some embodiments, the forming of the gate trenches in the NMOS region is at a different time than the forming of the gate trenches in the PMOS region. Referring to block30ofFIG.2Band toFIG.13, the remaining portions of the semiconductor layers110are selectively removed through the exposed side surfaces of the semiconductor layers120, for example, in process580. While different regions or sublayers of the semiconductor layers110may have different etching selectivity, the processes520may be configured to remove the entirety of the semiconductor layers110. Moreover, similar to processes520, the semiconductor layers120may be slightly affected during the processes580. For example, the thickness of the semiconductor layers120may be reduced by about 1% to about 10%. The removal of the remaining portions of the semiconductor layers110form suspended semiconductor layers120, as well as openings244in between the vertically adjacent layers. Accordingly, the center portions of the semiconductor layers120each have exposed top and bottom surfaces. In other words, the center portions of each of the semiconductor layers120are now exposed circumferentially around the X-direction. In the depicted embodiments, the surfaces of the openings244are curved. The processes580may be any suitable etching processes. In addition to exposing top and bottom surfaces of the center portions of the semiconductor layers120, these processes also expose the sidewall surfaces of the inner spacers206. The exposed sidewall surfaces may or may not have been modified by the processes580. For example, the process580exposes surface460of the inner spacer206. The surface460may be the same as, or different from, the sidewall surface400, depending on the choices of the etching methods and/or the materials of the inner spacers206. In some embodiments (for example in forming of PMOS transistors), the epitaxial source/drain features210includes SiGe. Moreover, the semiconductor layers110also includes SiGe. Accordingly, there may be minimal (to none) etch rate differences during the etching process of the process580. The inner spacers206separate the epitaxial source/drain features210from the area subject to the etching thereby protecting the epitaxial source/drain features210. In some approaches not implementing the methods provided herein, the inner spacers206may have greater curvatures such that top and bottom portions of the inner spacers206are significantly thinner along the X-direction than the middle portions. Therefore, the inner spacers206at those top and bottom portions may be more likely breached by the etching chemical, thereby causing damages to the epitaxial source/drain features210. By contrast, the inner spacers206has a sidewall with reduced curvatures. Accordingly, there is minimal variation in the strength of protection provided by the inner spacers206across the height dimension of the inner spacers206. Accordingly, the design of overall dimension of the inner spacer206according to the present disclosure provides good protection of the source/drain features210. Referring to block32ofFIG.2BandFIGS.14A and14B, a metal gate stack240′ is formed in the gate trenches242and openings244. For example, a gate dielectric layer246is formed over and between the semiconductor layers120, and a conductive metal layer248is formed over and between the portions of the gate dielectric layers246. In some embodiments, the gate dielectric layer246includes multiple layers. For example, the gate dielectric layer246may include a high-k dielectric layer. The high-k gate dielectric layer may be formed conformally such that it at least partially fills the gate trenches242. In some embodiments, the high-k gate dielectric layer may be formed around the exposed surfaces of each of the semiconductor layers120, such that it wraps around each of the semiconductor layers120in 360 degrees. The high-k gate dielectric layer may further be formed over the side surfaces of the inner spacers206, and the gate spacer layers200. The high-k gate dielectric layer may contain a dielectric material having a dielectric constant greater than a dielectric constant of SiO2, which is approximately 3.9. For example, the high-k gate dielectric layer may include hafnium oxide (HfO2), which has a dielectric constant in a range from about 18 to about 40. As various other examples, the high-k gate dielectric layer may include ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, SrTiO, or combinations thereof. The formation of the high-k gate dielectric layers may be by any suitable processes, such as CVD, PVD, ALD, or combinations thereof. In some embodiments, the gate dielectric layer246further includes an interfacial layer. The interfacial layer is formed between the semiconductor layers120and the high-k dielectric layer. Any suitable methods may be used to form the interfacial layer, such as ALD, CVD, or other deposition methods. Alternatively, the interfacial layer may also be formed by an oxidation process, such as thermal oxidation or chemical oxidation. In this instance, no interfacial layer is formed on the sidewalls of the inner spacers206or the gate spacer layers200. In many embodiments, the interfacial layer improves the adhesion between the semiconductor substrate and the subsequently formed high-k dielectric layer. However, in some embodiments, the interfacial layer is omitted. The conductive metal layer248is formed over the gate dielectric layer246and fills the remaining spaces of the gate trenches242and the openings244. In some embodiments, the gate structures250in the PMOS region is formed at a different time as the gate structures250in the NMOS region. For example, a mask element may be formed to cover the NMOS region while the PMOS region is exposed for processing. After the gate structures250in the PMOS regions are formed, the mask element may be removed from the NMOS region. A second mask element may be formed to cover the PMOS region while the NMOS region is exposed for processing. Accordingly, gate structures250in the n-type transistor region may be formed. This process allows gate structures in the different transistor regions to include different materials. For example, the conductive metal layer248may include a work function metal layer. The work function metal layer for a PMOS transistor may include different materials from that of an NMOS transistor. In some embodiments, the work function metal layer for a PMOS transistor include a suitable p-type work function metal materials, such as titanium nitride (TiN), ruthenium (Ru), iridium (Ir), osmium (Os), rhodium (Rh), or combinations thereof; while the work function metal layer for an NMOS transistor include a suitable n-type work function metal materials, such as aluminum (Al), titanium aluminum (TiAl), or combinations thereof. The conductive metal layer248may further include a fill metal layer. The fill metal layer may include any suitable materials, such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), ruthenium (Ru), or combinations thereof. In some embodiments, a CMP is performed to expose a top surface of the ILD layer230. The gate dielectric layer246and the conductive metal layer248collectively form the metal gate stack240′. The metal gate stack240′ engages multiple semiconductor layers120to form multiple gate channels. Furthermore, because the portions of the metal gate stack240′ between vertically adjacent semiconductor layers120interface with the inner spacers206, those portions have the sidewall surfaces of the curved profile described above. FIGS.15A and15Billustrate device100formed from the alternative structure depicted inFIGS.3A and3B, and throughFIGS.7A-7C. Features illustrated inFIGS.15A and15Bresemble those ofFIGS.14A and14Bwith the exception that the sidewall surfaces400(and sidewall surfaces206w) include three straight segments rather than one continuous curve. Accordingly, the portion of the metal gate stack240′ that interfaces with the inner spacers206also have sidewall surfaces that include the three straight segments. However, as described above, the sidewall surfaces400(hence also sidewall surfaces of the portion of the gate structures250) here may also be tuned, depending on design choices, into curved surfaces by tuning the material compositions, the etching chemicals, or the etching conditions. The method10may continue to form additional features and complete the fabrications of the device100. For example, silicide features, contact features, via features, or metal line features may be formed for the device100. Processing steps may be added to or eliminated from the method10before or after any of the described steps. Additional steps can be provided before, during, and after the method10, and some of the steps described may be replaced or eliminated, for additional embodiments of the method. It is further understood that additional features can be added in the device100, and some of the features described may be replaced or eliminated, for additional embodiments of the device100. Though not intended to be limiting, embodiments of the present disclosure offer benefits for semiconductor processing and semiconductor devices. For example, the disclosed method provides a semiconductor layer110that includes sublayer structures or gradient structures where Ge atomic percentages vary throughout the height dimension. This enables the sidewall surfaces of the inner spacers to have reduced curvatures. As a result, the inner spacers provide similar protection to all area of the epitaxial source drain features, and no particular damage-prone areas are formed. As such, the present disclosure provides methods that improve the device performance, functionality, and/or reliability of nano-sheet-based transistors. Different embodiments may provide different benefits. Not all benefits are required for any embodiment. In an exemplary aspect, the present disclosure is directed to a method. The method includes receiving a substrate and forming a stack over the substrate. The forming of the stack includes forming a first layer over the substrate; forming a second layer over the first layer; and forming a third layer over the second semiconductor layer. The first layer has a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element; and the third layer has the first semiconductor element. Moreover, the second layer has the second semiconductor element at a first concentration in a first region of the second layer and at a second concentration in a second region of the second layer. The second concentration is different from the first concentration. The method includes etching a source/drain trench in a region of the stack to expose a side surface of the stack; and removing a first portion of the second layer from the exposed side surface to form a gap between the first and the third layers. The method further includes forming a spacer in the gap; and forming a source/drain feature in the source/drain trench and on a sidewall of the spacer. In some embodiments, the forming of the second layer further includes forming the second layer having the second semiconductor element at a third concentration in a third region of the second layer. The first region and the third region sandwich the second region therebetween. Moreover, the third concentration is greater than the second concentration, and the first concentration is greater than the second concentration. In some embodiments, the etching of the source/drain trench includes etching using a chemical etchant. The first region of the second layer is etched at a first etch rate in the chemical etchant, and the second region of the second layer is etched at a second etch rate in the chemical etchant. A ratio of the first etch rate to the second etch rate is about 0.65 to about 1. In some embodiments, the first semiconductor element is silicon, the second semiconductor element is germanium, and the first concentration is greater than the second concentration. In some embodiments, a concentration of the second semiconductor element in the second layer changes from the first concentration in the first region to the second concentration in the second region. In some embodiments, the first concentration is about 20% to about 60% by atomic percentages, the second concentration is about 5% to about 50% by atomic percentages, and a ratio of the first concentration to the second concentration is about 1.1 to about 7. In some embodiments, the first concentration is about 30% to about 50% by atomic percentages, the second concentration is about 15% to about 35% by atomic percentages, and a ratio of the first concentration to the second concentration is about 1.2 to about 3. In some embodiments, the forming of the second layer includes forming with a first precursor and a second precursor, and further includes changing a flow rate ratio between the first precursor and the second precursor. In some embodiments, the forming of the second layer includes forming the first region of the second layer from a first precursor dosed at a first flow rate and a second precursor dosed at a second flow rate, and forming the second region of the second layer from the first precursor dosed at a third flow rate and the second precursor dosed at a fourth flow rate. A first ratio of the first flow rate to the second flow rate differs from a second ratio of the third flow rate to the fourth flow rate. In an exemplary aspect, the present disclosure is directed to a method. The method includes receiving a substrate, forming a first semiconductor layer over the substrate, and forming a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a first region over the first semiconductor layer, a second region over the first region, and a third region over the second region. The first region and the third region each include a first material composition, and the second region includes a second material composition different from the first material composition. The method also includes forming a third semiconductor layer over the second semiconductor layer. Moreover, the method includes forming a source/drain trench extending through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. Furthermore, the method includes laterally and selectively etching the second semiconductor layer to form an opening between an end portion of the first semiconductor layer and an end portion of the third semiconductor layer. The opening has a first interface with the etched second semiconductor layer. Additionally, the method includes forming a spacer in the opening, and forming a source/drain feature in the source/drain trench. In some embodiments, the forming of the second semiconductor layer includes forming the first region of the second semiconductor layer from a first precursor and a second precursor. The first precursor and the second precursor are dosed at a first flow rate ratio. The forming of the second semiconductor layer also includes forming the second region of the second semiconductor layer from the first precursor and the second precursor. The first precursor and the second precursor are dosed at a second flow rate ratio. The forming of the second semiconductor layer further includes forming the third region of the second semiconductor layer from the first precursor and the second precursor. The first precursor and the second precursor are dosed at a third flow rate ratio. The first flow rate ratio is substantially the same as the third flow rate ratio, and the first flow rate ratio is different from the second flow rate ratio. In some embodiments, the forming of the second semiconductor layer includes adjusting flow rates of the first precursor and the second precursor such that a flow rate ratio changes against a layer thickness from the first flow rate ratio to the second flow rate ratio following a branch of a parabolic curve, and from the second flow rate ratio to the third flow rate ratio following an opposite branch of the parabolic curve. In some embodiments, the forming of the source/drain trench includes etching with an etchant. The first region of the second semiconductor layer has a first etch rate in the etchant. The second region of the second semiconductor layer has a second etch rate in the etchant. A ratio of the first etch rate to the second etch rate is about 0.65 to about 1. In some embodiments, the forming of the second semiconductor layer includes forming the first region having a semiconductor element at a first concentration of about 20% to about 60% by weight, and forming the second region having the semiconductor element at a second concentration of about 5% to about 50%. A ratio of the first concentration to the second concentration is about 1.1 to about 7. In some embodiments, the first material composition and the second material composition both includes silicon germanium, and the second semiconductor layer includes silicon. In an exemplary aspect, the present disclosure is directed to an integrated circuit (IC) device. The IC device includes a semiconductor substrate having a top surface; a source feature and a drain feature over the semiconductor substrate; a semiconductor layer suspended over the top surface and connecting the source feature and the drain feature along a horizontal direction. The integrated circuit also includes a gate electrode wrapping around and engaging the semiconductor layer, as well as a spacer. The spacer is vertically between an end portion of the semiconductor layer and the top surface, and horizontally between the source feature and the gate electrode. Moreover, the spacer has a lateral dimension along the horizontal direction and a vertical dimension along a vertical direction perpendicular to the top surface. The lateral dimension varies in length across the vertical dimension and has a minimum length at an interface between the spacer and the semiconductor layer, and a maximum length at a half-height level of spacer. A ratio of the minimum length to the maximum length is about 0.65 to about 1. In some embodiments, the spacer has a curved sidewall surface. A tangential direction of the curved sidewall surface at the interface spans an angle from the horizontal direction of about 30° to about 90°. In some embodiments, the suspended semiconductor layer is one of the plurality of suspended semiconductor layers, and the spacer is one of the plurality of spacers. Each of the spacers interface with a respective suspended semiconductor layer of the plurality of suspended semiconductor layers. The plurality of spacers each span a tangential angle from its respective suspended semiconductor layer. The tangential angle is about 30° to about 90°. In some embodiments, the IC device further includes a gate dielectric. The gate dielectric has a curved profile. A tangential direction of the curved profile at an interface between the gate dielectric and the suspended semiconductor layer spans an angle from the horizontal direction. The angle is about 30° to about 90°. A distance between the suspended semiconductor layer and the top surface is about 3 nm to about 15 nm, the minimum length is about 5 nm to about 7 nm, and the maximum length is 5.5 nm to about 11 nm. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 88,456 |
11862710 | DETAILED DESCRIPTION Although this detailed description includes examples of how aspects of the invention can be implemented to form a VTFET, implementation of the teachings recited herein are not limited to a particular type of FET structure or combination of materials. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of transistor device or material, now known or later developed, wherein it is desirable to provide symmetrical source/drain extension junctions. For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Turning now to a description of technologies that are more specifically relevant to the present invention, when a MOSFET is scaled down through various technology nodes, several techniques can be employed to improve device performance. One technique for scaling for 5 nanometer (nm) devices and beyond is to form a vertical transistor such as, for example, a vertical transport field effect transistor (VTFET). VTFETs can have longer gates, which can improve performance, and can be formed using a channel-first process flow. The channel-first process flow allows for defining the gate length and spacer thicknesses by reactive ion etch (ME) and/or chemical mechanical planarization (CMP). To further reduce channel access resistances, it is common to form so-called “extension” regions situated between the source/drain regions and the channel region. One challenge of forming a VTFET using conventional methods is that there can be variations in the gate length, spacer thickness, and extension doping profile due to the integration challenges and geometrical constraints posed by the vertical orientation of the transistor. These geometrical constraints, in particular, have made it challenging to form source/drain extensions. Conventional process flows have attempted to overcome the VTFET geometrical constraints by forming and optimizing the bottom source/drain extension region separately from the top source/drain region. However, forming the extensions separately results in extension region misalignments known to cause undesired increases in resistance. Turning now to an overview of aspects of the invention, embodiments of the invention provide fabrication methods and resulting structures for forming symmetrical source/drain extension junctions in a vertical transistor. In particular, embodiments of the invention employ self-aligned top and bottom spacers capable of facilitating symmetrical source/drain extension in a VTFET. Unlike conventional process flows, embodiments of the invention described herein form the top and bottom source/drain extensions simultaneously, which provides channel length variation (Leff) control while avoiding underlapped extension regions that contribute to increased resistance. Turning now to a more detailed description of fabrication operations and resulting structures according to aspects of the invention,FIGS.1-18depict a semiconductor structure50after various fabrication operations for forming symmetrical source/drain extensions for use in a VTFET. For ease of illustration, the fabrication operations depicted inFIGS.1-18will be described in the context of forming the structure50into a single VTFET, it is intended that fabrication operations described herein apply equally to the fabrication of any number of VTFETs. FIG.1depicts a cross-sectional view of a starting semiconductor structure50configured to include a semiconductor substrate100according to a non-limiting embodiment of the invention. With reference to the X/Y/Z diagram depicted inFIG.1, the various elements that will form a completed VTFET device (not shown inFIG.1) extend along a first axis (e.g., X-axis) to define width dimensions, and extend along a second axis (e.g., Y-axis) perpendicular to the X-axis to define height (or thickness) dimensions. Although not specifically depicted in a two-dimensional (2D) cross-sectional view shown inFIG.1, the various elements that form the VFET device100also extend along a third axis (e.g., Z-axis) perpendicular to the first axis and the second axis to define depth dimensions. The substrate100includes a base substrate101, a punch through stop (PTS) layer102, and a first doped source/drain layer103. The substrate base101can be formed as a bulk substrate or a silicon-on-insulator (SOI) substrate, and can include one or more semiconductor materials. Non-limiting examples of suitable materials for the base substrate101include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CaSe (cadmium selenide), CaS (cadmium sulfide), CaTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. The PTS layer102interposed between the substrate base101and the first (or bottom) doped source/drain layer103. The PTS layer102can be referred to as a “counter-doped layer”, which includes a dopant that is different/opposite the dopant in the first doped source/drain layer103. For example, when the first doped source/drain layer103includes a p-type dopant, the PTS layer102includes an n-type dopant, and when the first doped source/drain layer103includes an n-type dopant, the PTS layer102includes a p-type dopant. The thickness of the PTS layer102can range, for example, from about 5 to about 50 nm. The PTS layer102works together with the first doped source/drain layer103to permit proper electron//hole mobility through the final constructed device. The first source/drain layer103is arranged on the substrate101over a counter-doped layer102. The first source/drain layer103can be epitaxially grown from the PTS layer102and can be heavily doped with a dopant, which can be a p-type dopant (e.g., boron or gallium) or an n-type dopant (e.g., phosphorus or arsenic) so as to serve as a source region for a completed VTFET. In one or more non-limiting embodiments of the invention, the first source/drain layer103has a dopant concentration ranging, for example, from about 1019 to about 1022 atoms/cm. The thickness of the doped first source/drain103can range, for example, from about 50 nm to about 250 nm. FIG.2depicts a cross-sectional view of the semiconductor structure50after having formed on the semiconductor substrate100a first gate120interposed between a first spacer stack121and a second spacer stack123. The first spacer stack121is formed on an upper surface of the first source/drain layer103and includes a first spacer layer110interposed between a pair of opposing dielectric layers107and109. The second spacer stack123is formed on an upper surface of the dummy gate120, and includes a second spacer layer111interposed between a pair of opposing dielectric layers113and115. The first spacer layer110and second spacer layer111can each include an oxide material such as, for example, silicon dioxide (SiO2), SiOCN, dielectric oxynitrides, or any combination thereof. The first spacer110and second spacer111materials are deposited by a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer layer110and the second spacer layer111can have a thickness ranging, for example, from about 3 nm to about 15 nm. The thickness of the first and second spacer layers110and111assist in defining the thickness of subsequently formed source/drain extension regions (not shown inFIG.2), which are described in greater detail below. The dielectric layers107,109,113,115included with the first and second spacer stacks can be formed from a nitride-based material, and can be deposited using various deposition processes including, but not limited to, CVD or PVD. The thickness of the dielectric layers107,109,113,115can range, for example, from about 1 nm to about 20 nm The first gate120can be formed as a dummy gate120(sometimes referred to as a sacrificial gate) and includes a sacrificial gate material such as, for example, amorphous silicon (aSi) or polycrystalline silicon (polysilicon). The sacrificial material can be deposited by a deposition process, including, but not limited to, PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial material forming the dummy gate120has a thickness ranging, for example, from about 8 nm to about 100 nm. A capping layer130is formed on the second spacer stack123and over the dummy gate120. Non-limiting examples of materials for the capping layer130include, but are not limited to, SiO2, tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, or nitride-based materials such as, for example, SiCN and SIBN. The capping layer130has a thickness in a range from about 30 to about 200 nm, or from about 50 to about 100 nm. Turning toFIG.3, a gate trench201is formed through the dielectric capping layer130, second spacer111, and the dummy gate120, while stopping on an upper surface of dielectric layer107. The gate trench201is formed by performing an etch process that is selective to (will not substantially remove) the material of dielectric layer107. The etch process to form the gate trench201can include a single reactive ion etch (RIE) process, or multiple etching processes. The multiple etchings processes can include, for example, a first etching process is performed to remove a portion of the dielectric capping layer130selective to the material of the second spacer111. A second etching process is then performed to remove a portion of the second spacer111, which underlies the portion of the gate trench201formed from the first etching process, selective to the material of the dummy gate120. A third etching process is then performed to remove a portion of the dummy gate120, which underlies the portion of the trench201formed from the second etching process, selective to the material of dielectric layer107. The resulting gate trench201extends through a top surface of the dielectric capping layer130down to a top surface of an exposed portion of dielectric layer107. The width of the gate trench201can range, for example, from about 3 nm to about 20 nm, and the depth of the gate trench201can range from about 50 nm to about 300 nm. Referring toFIG.4, self-aligned dummy gate spacers203are formed on sidewalls of the dummy gate120. Various oxidation techniques such as plasma oxidation, for example, can be performed to form the self-aligned dummy gate spacers203on the dummy gate120. In one or more non-limiting embodiments, a high-density plasma (HDP) can be applied to the dummy gate, which can oxidize a portion of the dummy gate sidewalls to form the dummy gate spacers203, while dielectric layer107prevents oxidation of the underlying source/drain layer103. The gate spacers can have a thickness ranging, for example, from about 2 nm to about 20 nm. Turning now toFIG.5, a portion of the dielectric layer107exposed by the gate trench201is etched away to expose the underlying source/drain layer103and an epitaxial channel501is formed in the trench. The gate trench201can be etched away using a process that is selective to (will not substantially remove) the first source/drain layer103material. For example, the dielectric layer107can be etched using a RIE process that employs a chemical composition that attacks the dielectric layer107without substantially attacking the remaining materials. The epitaxial channel501includes an epitaxial semiconductor material, which can be grown from the exposed portion of the first source/drain layer103. The epitaxial growth in the epitaxial channel501extends over the dielectric capping layer130. The epitaxial channel501can be grown using a suitable growth process, for example, CVD, liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), or other suitable processes. The sources for the material of the epitaxial channel501can include, for example, silicon, germanium, or a combination thereof. The gas source for the deposition of epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. An epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used. With reference now toFIG.6, an access trench510is formed through the dielectric capping layer130and continues until stopping on the upper surface of the first spacer layer110. Accordingly, a portion of the dielectric layer107is exposed by the access trench510. The access trench510can be formed using known lithography techniques which include, for example, patterning a mask layer511formed on the upper surface of the capping layer123, and transferring the pattern through the capping layer, second spacer stack123, dummy gate120and the first spacer stack121until stopping on the upper surface of dielectric layer107. A RIE processes selective to the dielectric layer107can be used to transfer the pattern so as to form the access trench510. Accordingly, the access trench510provides access (i.e., exposes) the first spacer110and the second spacer111. Referring toFIG.7, the first spacer110and second spacer111are removed so as to from a first spacer void512and a second spacer voids514. An etching technique including a hydrofluoric-based (HF-based) chemistry can be performed to remove the first and second spacers110and111. Accordingly, the first and second spacer voids512and514provide access (i.e., expose) to a first portion516and a second portion518of the epitaxial channel501, which will be utilized to form first and second source/drain extension regions, respectively. Turning toFIG.8, the first exposed portion516of the epitaxial channel501is converted into a first (e.g., lower) source/drain extension region520and the second exposed portion518is converted into a second (e.g., upper) source/drain extension region522. A plasma doping technique can be performed to the form the first and second source/drain extension regions520and522. When forming an NFET devices, the first and second source/drain extension regions520and522can be doped with arsenic (As), phosphorus (P) or aluminum (Al). When forming a PFET device the first and second source/drain extension regions520and522can be doped with boron (B), boron trifluoride (BF3) or gallium (Ga). In either case, the dopant concentration can range, for example, from about 5E19 atm/cm3 to about 1E21 atm/cm3. Accordingly, a dopant concentration of the first and second source/drain extension regions520and522is different from a doping concentration, if any, of the non-plasma doped channel region (e.g., channel portion501). Unlike conventional process flows that form one source/drain region separately (i.e., at separate and different times or at different stages of the process flow) from the other source/drain region, the access trench510facilitates simultaneous doping of the first exposed portion516and the second exposed portion518to simultaneously form the first and second source/drain extension regions520and522. In addition, the dummy gate spacers203allow for forming first and second source/drain extension regions520and522having matching thicknesses, i.e., distances extending along the vertical direction of the channel region501. Accordingly, the first source/drain extension region520(e.g., the lower source/drain extension region) is formed to be self-aligned with respect to the second source/drain extension region522(e.g., the upper source/drain extension region). Referring toFIG.9, the access trench510along with the spacer voids512and514are filled with a dielectric fill material524. The dielectric fill material524can include, but is not limited to, SiO2. Filling the access trench510forms a first dielectric portion526and a second dielectric portion528. The first dielectric portion526is interposed between dielectric layers107and109, and surrounds the first source/drain extension region520. The second dielectric portion528is interposed between dielectric layers113and115, and surrounds the second source/drain extension region522. The dielectric fill material can be deposited before or after removing the mask511. When depositing the dielectric fill material524before removing the mask511, a CMP process can be performed to recess any overflow dielectric material along with the mask511. The dielectric fill material524can be deposited using various deposition processes including, but not limited to, CVD. In one or more non-limiting embodiments of the invention, excess dielectric fill material524located on the upper surface of the capping layer123can be removed using a CMP process. Turning toFIG.10, a channel cap701is formed on the channel501. In some embodiments of the invention, the capping layer123is removed and the exposed upper portion of the channel501is converted into a channel cap701. The channel701can be formed by oxidizing the upper portion of the channel501to form an oxide-based channel cap701such as, for example, a SiO2channel cap701. In other embodiments of the invention, the channel cap701can be formed by recessing an upper portion of the channel501to form a void (not shown) in the capping layer123. The void is then re-filled with a dielectric material such as, for example, an oxide material or nitride material, to form the channel cap701. Turning toFIG.11, a top spacer901is formed on the upper surface of dielectric layer115and on the sidewalls of an exposed portion of the upper source/drain region and channel cap701. In some embodiments of the invention, excess portions of the top spacer901can be recessed from the upper portion of the channel cap701using a CMP process. Accordingly, the top spacer901can protect the upper source/drain extension region520and the channel cap701from subsequent process flow etching processes. The top spacer901includes an insulating material, for example, dielectric oxides such as, for example SiO2, which can be deposited on the upper surface of dielectric layer115using various known deposition processes such as, for example, CVD or PVD. The deposited top spacer material can then be patterned according to a lithography/etching process. The top spacer material can be etched using a dry etch process such as a RIE process, for example, while stopping on an upper surface of the dielectric layer115. The remaining top spacer901can have a width ranging, for example, from about 5 nm to about 50 nm. Accordingly, the top spacer901itself can be used as a hardmask for performing a subsequent etching process. Referring now toFIG.12, portions of the second spacer stack123and dummy gate120are recessed to trim the dummy gate120. More specifically, the second spacer111and the dummy gate material120are recessed to removed portions that extend laterally beyond the spacer901material. A dry etch process such as, for example, a RIE process, that is selective to (will not substantially remove) dielectric layer109is performed to remove portions of the second spacer stack123and dummy gate120not covered by the top spacer901, while stopping on the upper surface of dielectric layer109. Referring toFIG.13, the remaining portion of the dummy gate120located beneath the remaining portion of the second spacer stack123is removed (i.e. “pulled) to expose the dummy gate spacers203. The dummy gate120can be removed using a wet etch process, for example, that is selective to (will not substantially remove) the dummy gate spacers203and dielectric layers109and115. In some embodiments of the invention, the wet etch chemistry includes high-temperature ammonia (NH3). Turning now toFIG.14, the dummy gate spacers203(seeFIG.13) are removed before depositing a gate dielectric material1201, a work function metal1202and a metal gate material1401. The gate dielectric material1201, the work function metal1202, and metal gate material1401form a portion of a gate stack1501that replaces the dummy gate120. In accordance with standard VTFET architectures, various elements of a VTFET (e.g., the bottom spacer layer110, gate dielectric1201, gate stack1501, top spacer layer111, and top S/D region1801) extend completely around the sidewalls of the channel in the X, Y, and Z directions. The gate dielectric material1201and the work function metal1202can be deposited such they conform to the upper surface of dielectric layer109, along with the epitaxial channel501, remaining portions of the second spacer stack11and the top spacer901. Thereafter, portions of the gate dielectric material1201and work function metal1202can be removed from the top spacer901and second spacer stack11as further shown inFIG.14. In one or more embodiments of the invention, an anisotropic etch such as a RIE process, for example, can be performed recess the gate dielectric material1201and the work function metal1202while stopping on the upper surface of the metal gate material1401. The gate dielectric material(s) can be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the gate dielectric material1201include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (with a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material can further include dopants such as, for example, lanthanum and aluminum. The gate dielectric material1201layer can be formed by suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. The thickness of the gate dielectric material1201can vary depending on the deposition process as well as the composition and number of high-k dielectric materials used. The work function metal(s)1202deposited over the gate dielectric material1201can be chosen based on the type of transistor. Non-limiting examples of suitable work function metals1202include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal(s)1202can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering. The metal gate material1401is a conductive gate metal that is deposited over the gate dielectric material(s)1201and work function metals1202to form the gate stack1501. Non-limiting examples of suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering. A planarization process, for example, chemical mechanical planarization (CMP), is performed to polish the surface of the conductive gate metal material1401. Referring toFIG.15, an interlayer dielectric (ILD)1701is deposited on the gate stack1501and is planarized using a CMP process, for example, until stopping on the upper surface of the top spacer901. The ILD1701can be formed from, for example, a low-k dielectric material, which can be defined as having a dielectric constant (k) that is less than about 4.0. The low-k material can included, but is not limited to, SiO2, spin-on-glass, a flowable oxide, a high density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD layer1701is deposited by a deposition process, including, but not limited to CVD, PVD, plasma enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or like processes. Referring toFIG.16, the channel cap701and top spacer901are removed. Accordingly, an ILD void1702is formed in the ILD1701, which exposes the upper surface of dielectric layer115along with an upper portion of the upper source/drain extension region520. The top spacer901and channel cap701can be etched selectively using well-known current state-of-the-art techniques RIE or atomic layer etch (ALE) using fluoride-based chemicals such as, for example fluoroform (CHF3). Turning toFIG.17, a second source/drain region1801is epitaxially grown from the upper portion of the epitaxial channel501. The second source/drain region1801can be epitaxially grown using a suitable growth process, for example, chemical vapor deposition (CVD) (liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), or other suitable processes. The second source/drain region1801can be heavily doped with a dopant, which can be a p-type dopant (e.g., boron or gallium) or an n-type dopant (e.g., phosphorus or arsenic) so as to serve as a drain region for a completed VTFET. In one or more non-limiting embodiments of the invention, the second source/drain region1801has a dopant concentration ranging, for example, from about 1019 to about 1022 atoms/cm. The sources for the epitaxial channel material can be, for example, silicon, germanium, or a combination thereof. The gas source for the deposition of epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. An epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used. Referring toFIG.18, a top contact2001is formed to contact the second source/drain region1801(e.g., the drain region1801) and a bottom contact2002is formed to contact the first source/drain region103. The top contact2001is formed by depositing an electrically conductive material in the ILD void1702and on an upper surface of the second source/drain region1801. The bottom contact2002is formed by etching a contact trench (not shown) through the ILD1701and the first spacer stack121until a portion of the first source/drain region103is exposed. An electrically conductive material can then be deposited in the contact trench to form a bottom contact2002that directly contacts the first source/drain region103. The electrically conductive material used for the top and bottom contacts2001and2002can be a conductive metal, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, or sputtering. A planarization process, for example, CMP, can be performed to remove any conductive material from the surface of the ILD1701. The methods and resulting structures described herein can be used in the fabrication of IC chips. The resulting IC chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes IC chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the detailed description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Similarly, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s). The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus. Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.” References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value. The phrase “selective to,” such as, for example, “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop. The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer. As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and IC fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs. In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. Reactive ion etching (RIE), for example, is a type of dry etching that uses chemically reactive plasma to remove a material, such as a masked pattern of semiconductor material, by exposing the material to a bombardment of ions that dislodge portions of the material from the exposed surface. The plasma is typically generated under low pressure (vacuum) by an electromagnetic field. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device. The flowchart and diagrams in the Figures illustrate possible implementations of fabrication and/or operation methods according to various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein. | 41,809 |
11862711 | DETAILED DESCRIPTION The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are merely a part of the embodiments of the present disclosure and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative labor are within the claimed scope of the present disclosure. The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present disclosure. The present disclosure may be embodied in many alternative ways and should not be construed as being limited only to the embodiments described herein. The present disclosure provides a method for fabricating a thin film transistor substrate. Please refer toFIG.1, which is a flowchart of a method for fabricating a thin film transistor substrate according to an embodiment of the present disclosure. The method comprises the following steps. Step S1: providing a substrate100, depositing a light shielding layer on the substrate100, and etching the light shielding layer to form a light shielding layer pattern11. Please refer toFIG.2, which is a schematic diagram of a thin film transistor substrate in step S1in the method according to the embodiment of the present disclosure. Step S2: depositing a buffer layer12and an active layer, and etching the active layer to form an active layer pattern13. Please refer toFIG.3, which is a schematic diagram of a thin film transistor substrate in step S2in the method according to the embodiment of the present disclosure. In this embodiment, the active layer may be composed of indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), but is not limited thereto. In this embodiment, the active layer has a thickness of 400 Å to 600 Å. Step S3: sequentially depositing agate insulating layer14and agate layer on the active layer pattern13, and wet etching the gate layer to form a gate layer pattern15with a photoresist. Please refer toFIG.4, which is a schematic diagram of a thin film transistor substrate in step S3in the method according to the embodiment of the present disclosure. In this embodiment, the gate insulating layer14may be composed of silicon oxide or silicon nitride but is not limited thereto. Step S4: stripping off the photoresist, dry etching a surface of the gate layer pattern15, and forming a protective layer151on the surface of the gate layer pattern15; and dry etching the gate insulating layer14to form a gate insulating layer pattern14, and metalizing a non-channel region131of the active layer pattern13. Please refer toFIG.5, which a schematic diagram of a thin film transistor substrate in step S4in the method according to the embodiment of the present disclosure. The protective layer151is configured to protecting the gate layer pattern15, and preventing the gate layer pattern15from being etched when the gate insulating layer14is etched and the active layer pattern13is metalized. In this embodiment, the protective layer151has a thickness ranging from 40 Å to 60 Å. In this embodiment, the dry etching the surface of the gate layer pattern15is performed with a fluorine-based etching gas, specifically nitrogen trifluoride and oxygen. In this embodiment, the metalizing the non-channel region of the active layer pattern15may be performed by bombarding the non-channel region with argon or helium ions, or by implanting aluminum or calcium ions, but is not limited thereto. The dry etching the gate insulating layer14to form the gate insulating layer pattern14and metalizing the non-channel region131of the active layer pattern13are performed by using the gate layer pattern15as a mask. This step can ensure that width of the gate layer pattern15is equal to that of the gate insulating layer pattern14, and that an orthographic projection of the gate layer pattern15completely coincides with that of the gate insulating pattern14on the substrate. That is, the entire active layer pattern13is under the gate insulating layer pattern14. Therefore, the entire active layer pattern13can be regulated by the gate layer pattern15. This step solves the drawbacks, in the prior art, of no gate on the edge of the gate insulating layer pattern, thereby improving a turn-on current and electrical characteristics of a thin film transistor and improving display effect of a display device. Step S5: depositing an interlayer dielectric layer16, and forming a first via hole161through the interlayer dielectric layer16. Please refer toFIG.6, which is a schematic diagram of a thin film transistor substrate in step S5in the method according to the embodiment of the present disclosure. Step S6: depositing a source/drain layer and etching the source/drain layer to form a source/drain layer pattern17. Please refer toFIG.7, which is a schematic diagram of a thin film transistor substrate in step S6in the method according to the embodiment of the present disclosure Step S7: depositing an organic layer18, and forming a second via hole181through the organic layer18. Please refer toFIG.8, which is a schematic diagram of a thin film transistor substrate in step S7in the method according to the embodiment of the present disclosure. Step S8: depositing a pixel electrode layer and etching the pixel electrode layer to form a pixel electrode19. Please refer toFIG.9, which is a schematic diagram of a thin film transistor substrate in step S8in the method according to the embodiment of the present disclosure. The present disclosure provides a method for fabricating a thin film transistor substrate, comprising: sequentially depositing an active layer, a gate insulating layer, and a gate layer on a substrate, wet etching the gate layer to form a gate layer pattern, forming a protective layer on a surface of the gate layer pattern, and etching the gate insulating layer and metalizing a naked region of the active layer with the gate layer pattern as a mask. This method can ensure that an orthographic projection of the gate layer pattern completely coincides with that of the gate insulating pattern on the substrate. That is, the entire active layer pattern is under the gate insulating layer pattern. Therefore, the entire active layer pattern can be regulated by the gate layer pattern. This method solves the drawbacks, in the prior art, of no gate on the edge of the gate insulating layer pattern, thereby improving a turn-on current and electrical characteristics of a thin film transistor and improving display effect of a display device. The above description is only preferred embodiments of the present disclosure. it should be noted that those skilled in the art can make various modifications to the above embodiments without departing from the technical idea of the present disclosure, and the modifications are all within the scope defined by the claims of the present disclosure. | 7,158 |
11862712 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors or fin-type multi-gate transistors referred to herein as FinFET devices. Such a device may include a P-type metal-oxide-semiconductor FinFET device or an N-type metal-oxide-semiconductor FinFET device. The FinFET device may be a dual-gate device, tri-gate device, bulk device, silicon-on-insulator (SOI) device, and/or other configuration. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure. For example, some embodiments as described herein may also be applied to gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices. The present disclosure is generally related to semiconductor devices and fabrication methods, and more particularly to the formation of devices (e.g., FinFETs) fabricated using epitaxial growth processes for providing a source/drain region, as described in more detail below. However, one of skill in the art would recognize the application to other device types, as discussed above, and also other features of said devices. Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, various embodiments provide a method and related structure for improving capacitance of a FinFET Referring now toFIG.1, illustrated therein is a method100for fabricating a device including an epitaxial layer, in accordance with some embodiments. It is understood that the method100includes steps having features of a complementary metal-oxide-semiconductor (CMOS) technology process flow and thus, are only described briefly herein. Additional steps may be performed before, after, and/or during the method100.FIGS.3,4,5A,6A,7A,7C,8A,9A,10, and11Aprovide isometric views of an embodiment of a semiconductor device300according to various stages of the method100ofFIG.1.FIGS.5B,6B,7B,7D,8B,9B, and11Bare cross-section views (e.g., along an exemplary plane A-A′, as shown inFIG.5A), corresponding to respective isometric views listed above, of an embodiment of the semiconductor device300according to various stages of the method100ofFIG.1.FIG.11Cillustrates a top view a region of the device300ofFIG.11A, according to some embodiments. Further, the semiconductor device300may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the semiconductor device300includes a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Moreover, it is noted that the process steps of method100, including any descriptions given with reference to the figures are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow. In an embodiment, the device300illustrated in the exemplary figures is an n-type FET (nFET). The nFET may be suitable for use in an SRAM application. The device300may be a two-fin structure, such that a single gate structure interfaces two fins and the source/drain regions grown on said fins merge. The method100begins at block102where fin elements, used for subsequent FinFET formation, are formed extending from a substrate. With reference to the example ofFIG.3, in an embodiment of block102, a plurality of fin structures304extending from a substrate302are formed. In some embodiments, the substrate302may be a semiconductor substrate such as a silicon substrate. The substrate302may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate302may include various doping configurations depending on design requirements as is known in the art. The substrate302may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate302may include a compound semiconductor and/or an alloy semiconductor. Further, the substrate302may optionally include one or more epitaxial layers (epi-layers), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features. In some embodiments, an anti-punch through (APT) implant may be performed (e.g., into the substrate302) prior to formation of the fin structures304. In some cases, also prior to formation of the fin structures304, a hard mask (HM) layer(s)306may be formed over the substrate302. The HM layer may include an oxide layer portion306A (e.g., a pad oxide layer that may include SiO2) and a nitride layer portion306B (e.g., a pad nitride layer that may include Si3N4) formed over the oxide layer. In some examples, the oxide layer may include thermally grown oxide, CVD-deposited oxide, and/or ALD-deposited oxide, and the nitride layer may include a nitride layer deposited by CVD or other suitable technique. By way of example, the oxide layer of the HM layer,306A, may have a thickness of between approximately 5 nm and approximately 40 nm. In some embodiments, the nitride layer of the HM layer,306B, may have a thickness of between approximately 20 nm and approximately 160 nm. The fins304, like the substrate302, may include silicon or another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP; or combinations thereof. The fins304may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer over the substrate302(e.g., over an HM layer formed over the substrate302), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate302, and layers formed thereupon, while an etch process forms trenches308in unprotected regions through the HM layer and into the substrate302, thereby leaving the plurality of extending fin structures304with HM layer portion306overlying each fin304. The trenches308may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or other suitable processes. Numerous other embodiments of methods to form the fins304on the substrate302may also be used. The method100then proceeds to block104where isolation regions are formed between fin elements. With reference to the example ofFIG.4, in an embodiment of block104, a plurality of isolation regions402are formed. In some embodiments, the plurality of isolation regions402may include a plurality of shallow trench isolation (STI) features including a dielectric material. By way of example, the dielectric material is first deposited over the substrate302, filling the trenches308with the dielectric material. In some embodiments, the dielectric material may include SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials known in the art. In various examples, the dielectric material may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, after deposition of the dielectric material, the device300may be annealed to improve the quality of the dielectric material. In some embodiments, a field oxide, a LOCOS feature, and/or other suitable isolation features may additionally or alternatively be implemented on and/or within the substrate. However, other embodiments are possible. For example, in some embodiments, the dielectric material (and subsequently formed isolation regions402) may include a multi-layer structure, for example, having one or more liner layers. After deposition of the dielectric material, the deposited dielectric material is thinned and planarized, for example by a CMP process. In some embodiments, such a CMP process may be used to remove excess dielectric material, planarize a top surface of the device300, and form isolation regions (e.g., which are subsequently recessed to form the isolation regions402, as described below). In some embodiments, the CMP process used to planarize the top surface of the device300and form the isolation regions (e.g., prior to recessing the isolation regions) may also serve to remove the HM layer portion306or portions thereof from each of the plurality of fin structures304. In some embodiments, removal of the HM layer portion306includes removal of the oxide layer portion306A and the nitride layer portion306B in concurrent or separate processes (e.g., CMP). Removal of the HM layer portion306, including the oxide layer portion306A and the nitride layer portion306B, may alternately be performed by using a suitable etching process or processes (e.g., dry or wet etching). Whether by using a CMP process and/or an etching process, upon removal of the HM layer portion306from the top of each of the fin structures304, provides for a top surface of the fin structures304(e.g., semiconductor material) to be exposed. After the CMP process to remove the excess dielectric material and planarize the top surface of the device300, the isolation regions around the fin structures304are recessed to laterally expose an upper portion of the fin structures304and form the isolation regions402as illustrated inFIG.4. In various examples, the isolation regions402are configured to isolate fin active regions. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In various embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height ‘H’ of the exposed upper portion of the fin elements304. In some embodiments, the height ‘H’ may be between approximately 30 nm-60 nm. In some cases, a fin width ‘W’ may be between approximately 4 nm-10 nm. The height H and the width W provide for a channel region of the device300and thus, are selected to provide suitable device performance (Vth, Ion, Ioff, DIBL, etc.). In some embodiments, at this stage in the process, the isolation regions402may have a substantially planar top surface. The method100then proceeds to block106where a gate structure is formed over the fin elements. In an embodiment, the gate structure is a dummy gate. In an embodiment, the formation of the gate structure includes forming a gate dielectric layer(s) and gate electrode layer(s), one or more of said layers being sacrificial. With reference to the example ofFIGS.5A and5B, in an embodiment of block106, a gate structure500is formed. In some embodiments, the gate structure500is sacrificial, or in other words, is a dummy gate that is subsequently replaced by a functional gate (e.g.,500′ discussed below). The gate structure500may include an interfacial layer502, which is formed over the exposed upper portion of the fin structures304, a gate dielectric layer504is formed over the interfacial layer502, and an electrode layer506is formed over the dielectric layer504. In some embodiments, one or more of the interfacial layer502, the gate dielectric layer504, and the electrode layer506are formed conformally over the fin structures304, including within trenches between adjacent fin structures304and subsequently patterned. In some embodiments, the interfacial layer502may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer502may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. In various examples, a thickness of the interfacial layer502may be around 0.5-3 nm. The thickness of the interfacial layer502affects the equivalent oxide thickness (EOT) of the device300, an increased thickness can raise the EOT while too thin of an interfacial layer, in some embodiments, can affect the channel integrity (e.g., interfacial trap states). In some embodiments, the interfacial layer502is not formed over the isolation region402. In an embodiment, the dielectric layer504includes silicon oxide. Other compositions are also possible including high-k dielectric materials such as hafnium oxide (HfO2), HfZrO, TiO2, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The gate dielectric layer504may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), ALD, physical vapor deposition (PVD), and/or other suitable methods. In various examples, a thickness of the gate dielectric layer504may be around 1-5 nm. The thickness of the gate dielectric layer504affects the performance of the device300(capacitance), while too thin of a gate dielectric can cause degradation and breakdown during operation which leads to leakage currents. In some embodiments, the electrode layer506may include polycrystalline silicon (polysilicon). Alternatively, in some embodiments, a metal gate electrode layer may be formed including Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. As discussed above, in some cases, the electrode layer506(like the dielectric layer504and possibly the interfacial layer502) is removed in a subsequent replacement gate process, as discussed herein. In other embodiments, the electrode layer506is retained and may provide an N-type or P-type work function, for example, depending on whether an N-type or P-type FinFET is being formed. In various embodiments, the electrode layer506may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. In some examples, a hard mask508may be formed over the gate electrode layer506, where the hard mask508includes an oxide layer508A and a nitride layer508B formed over the oxide layer508A. In some examples, deposition of the hard mask508may be accomplished using CVD, PVD, ALD, thermal oxidation, or other suitable deposition techniques, or a combination thereof. In some embodiments, the oxide layer508A includes a pad oxide layer that may include SiO2. In some embodiments, the nitride layer508B includes a pad nitride layer that may include Si3N4, silicon oxynitride or silicon carbide. Block106includes the deposition of materials as discussed above, and the subsequent patterning of the layers. With reference to the example ofFIGS.5A/5B, the hard mask508and the gate electrode layer506are patterned to form a gate structure500(e.g., using photolithography and etching processes). In some embodiments, the photolithography process may include photoresist coating (e.g., over the hard mask508), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), and/or other suitable lithography techniques, and/or combinations thereof. The photolithography process may provide a patterned photoresist layer which serves as a masking element for the subsequent etching process. The masking element may be used to protect some regions of the device300, while an etching process (e.g., a dry etch, a wet etch, or combination thereof) etches through unprotected regions of the device300including unprotected regions of the hard mask508and the electrode layer506, thereby leaving the (dummy) gate structure500. In some embodiments, the dielectric layers502and/or504may also be patterned. In alternative embodiments, the dielectric layers502and/or504are not patterned. The method100at block106may include formation of one or more spacer layers. With reference to the example ofFIGS.6A/6B, in an embodiment of block106, a spacer material layer is deposited over the substrate302including over the gate structure500. The spacer material layer may, after conformal deposition, be etched back for example exposing a top of the gate500(hard mask508B) to form gate spacers602. In a same or different process, the spacer material layer be etched back such that the fin spacers604of a first height are formed on the fin sidewalls of the source/drain region. In some cases, the spacer layer602may be referred to as an offset spacer. In some embodiments, the spacer layer602and/or604may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiOC, SiOCN, a low-K dielectric material, or combinations thereof. The spacer layer602and/or604may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. In various examples, a thickness of the spacer layer602and/or604may be around 1-8 nm. The thickness of the spacer layers can define the source/drain positioning with respect to the channel region and/or provide sidewalls for subsequent processes (e.g., replacement gate). In some embodiments after conformal deposition, the spacer layer, high-K gate dielectric layer, and/or interfacial layer are etched-back (or pulled-back) to expose the fin304in a source/drain region adjacent the gate structure500with the fin spacers604on the fin304sidewalls in the source/drain region. The method100then proceeds to block108where source/drain features are formed. The source/drain features are formed in a source/drain region of the fin, which is adjacent the gate structure covering the channel region of the fin. The source/drain features may be formed by epitaxially growth. One example method of forming an epitaxial feature suitable for use as a source/drain feature is illustrated in the method200ofFIG.2.FIG.2is exemplary method200including a three-stage epitaxially growth process. However, in some embodiments, one more of the stages, i.e., additional epitaxially growth processes of the method200ofFIG.2may be omitted. In an embodiment, the method200begins at block202where the fin element in the source/drain region is etched back. In some embodiments, block202is omitted. For example, a seed area for the subsequent epitaxial growth described below is provided at a top surface of the fin element, without etch back. Referring to the example ofFIG.7A/7B, the fin structure304is selectively etched back to provide a recessed top surface304A. The recessed top surface304A provides a seed (e.g., a surface on which epitaxial material nucleates) for subsequent epitaxial growth described below. The recessed top surface304A is curvilinear surface of the semiconductor material of the fin304. The recessed top surface304A may be a curvilinear silicon surface. Specifically, the recessed top surface304A may include a bottom portion that is Si(100) crystal orientation. The sides of the curvilinear surface304A may be a different Si crystal orientation, such as Si(111). It is noted that the depicted recessed top surface304A is substantially adjacent the top surface of the isolation feature504. However, in other embodiments, the recessed top surface304A may be below a top surface of the isolation structure504. In yet other embodiments, the recessed top surface304A may be above a top surface of the isolation structure504. Fin spacers604′ material may remain above the isolation features abutting the previously present sidewalls (now recessed) of the fin structure304and be adjacent the recessed top surface304A. It is noted that as illustrated inFIG.7A/7B, the fin spacers604′ have been etched back from the initial height of fin spacers604inFIGS.6A/6B. The etch back process may be separate process than that of the recessing of the fin structure304. In some embodiments, the fin spacers604′ are maintained on both the inner sidewalls and the outer sidewalls of the previously disposed fin304. The height of the inner and outer fin spacers604′ may differ. In an embodiment, the height of the inner spacer604′, as shown, may be less than the height of the outer spacer604′. In an embodiment, the inner fin spacers604′ may connect between adjacent fins, as shown as outline604″ inFIG.8B. In other words, the portion of the spacer material604above the isolation material402between adjacent fins may remain. The etching back process of the fin structure304may be performed by a wet etching process, a dry etching process or combinations thereof. It is noted that an outline of the fin304, removed in some embodiments that include etching back, is provided for ease of reference as a dotted line inFIG.7B. The etching back process of the fin structure304may be selective to the fin material leaving the surrounding dielectrics substantially unetched. Some processes such as the etching back of the fin spacers604and, in some embodiments, though possibly to a lesser extent, the etch back of the fin304, may lead to loss (etching) of the isolation structures402. This is illustrated by the non-planar surface of the isolation features inFIGS.7A/7B. The isolation structures402may be between approximately 17 to 20 nm below the seed area, surface304A. The isolation structure402may be approximately a distance t below the recessed fin surface304A. In an embodiment, “t” is between approximately 17 and 20 nm. The distance ‘t’ affects the crystalline growth properties including the flexibility of the fin structure on which the epitaxy is subsequently grown and the thickness of epitaxial material that is to be growth before merging, which affects device performance as discussed below. The isolation features402may exhibit a circulinear or concave surface as illustrated, for example, inFIG.7B. The method200then proceeds to include a three-stage process that forms a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, which together form the epitaxial feature. For example, a first epitaxial layer is formed on a seed that is the surface of the fin structure. In the case of etch back of block202being performed, the seed surface is the recessed top surface as illustrated by curvilinear surface304A. A first epitaxial layer is formed from this seed area of surface304A. Further as discussed below, a second epitaxial layer wraps around the first epitaxial layer using a seed of a surface/surfaces of the first epitaxial layer. In some further embodiments, a third epitaxial layer may further wrap around the prior epitaxial layer(s), for example, using a seed of a surface of the second epitaxial layer. The method may include additional epitaxial layers or fewer epitaxial layers. This multi-stage process is discussed in further detail below. The method200then proceeds to block204where a first stage of epitaxial growth is performed. In an embodiment, the first stage of epitaxial growth is performed to form a first epitaxial portion702, also referred to as L1 as illustrated inFIGS.7C/7D. In an embodiment, the first epitaxial portion702is doped silicon such as, for example silicon doped with arsenic (As). In an embodiment, the first epitaxial portion702may include silicon doped with phosphorous or silicon phosphide (SiP). In some embodiments, the concentration of phosphorous is lower than that of the second and third epitaxial processes discussed below. In an embodiment, the concentration of phosphorous (P) is for a molar ratio of less than 2% with respect to the silicon precursor. In another embodiment, the first epitaxial portion702may be silicon or silicon carbide (SiC). In another embodiment, the first epitaxial portion702is silicon doped with arsenic (SiAs). A first epitaxy process can be implemented by CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. In an embodiment, the first epitaxial process (like blocks206and/or208) is a VPE. In some implementations, first epitaxial portions702are doped during deposition by adding impurities to a source material of the epitaxy process. In some implementations, first epitaxial portions702are doped by an ion implantation process subsequent to a deposition process. In the depicted embodiment ofFIG.7A/7B, the first epitaxial portion702does not merge with epitaxial regions of the adjacent fins. The first epitaxial portion702may be approximately 1 to 10 nm in thickness. In an embodiment, the first epitaxial portion702includes a first thickness t1 at a sidewall and a second thickness t2 at a bottom region. The thickness t2 may be greater than the thickness t1. In an embodiment, the thickness t2 is between approximately 4 and 8 nm. In an embodiment, the thickness t1 is between approximately 2 and 4 nm. In an embodiment, the thickness t2 to the thickness t1 has a ratio of approximately 1.5:1 to approximately 4:1. While not being bound to any theory, the thickness difference may result from a single epitaxial growth process experiencing different growth rates depending on crystalline plane (e.g., faster growth on plane (100) on the bottom seed area or surface304A. The dopant type, dopant quantity, and thicknesses of the first epitaxial portion702affect the conductivity of the region, the lattice mismatch (e.g., stress) between the first epitaxial portion702and the underlying fin304, and the epitaxial growth rate and facet formation. For example, increased dopant concentration provides increased conductivity and greater lattice mismatch with respect to a silicon fin304. The thickness t1 and t2 should be sufficient to provide an ordered crystalline feature, while excessive thicknesses can provide for undesired shapes of the overall epitaxial feature (e.g., lower merge point by greater growth for the first epitaxial portion702). The first epitaxial portion702may extend above a top surface of the fin spacers604′. In an embodiment, the fin spacers604′ extend below a plane coplanar with the both of the first epitaxial portion702. In an embodiment, the fin spacers604′ have an upper surface that is disposed at a region coplanar to between 40-60% of the height of the first epitaxial layer702. The interface of the fin spacers604′ and the first epitaxial portion may provide for defining a desired U-shaped region and a desired blocking of the growth of the second epitaxial layer802from lower regions on the first epitaxial feature702, which, for example, may provide for a lower merge point. The method200then proceeds to block206where a second stage of epitaxial growth is performed. Referring to the example ofFIGS.8A/8B, in an embodiment, the second stage of epitaxial growth is performed to form a second epitaxial portion802, also referred to as L2-1. In an embodiment, the second epitaxial portion802is doped silicon such as, for example silicon doped with phosphorous (SiP). In an embodiment, the first epitaxial portion702(L1) comprises SiP having a P doping concentration of about 5×1020to about 2×1021atoms/cm−3; and the second epitaxial portion802(L2) comprises SiP having a P doping concentration of about 2.8×1021to about 3.2×1021atoms/cm−3. In another embodiment, the first epitaxial portion702(L1) comprises SiAs having an As doping concentration of about 5×1020to about 5×1021atoms/cm−3; and the second epitaxial portion802(L2) comprises SiP having a P doping concentration of about 2.8×1021to about 3.2×1021atoms/cm−3. The dopant type and dopant quantity affect the conductivity of the region, the lattice mismatch (e.g., stress) between the first epitaxial portion702and the second epitaxial portion802, and the epitaxial growth rate and facet formation. Too low of a dopant concentration provides insufficient carriers to form the device300; too high of dopant concentration increases the lattice mismatch with the underlying layers among other possible concerns. The second epitaxial portion802is grown from a seed that includes the surface of the first epitaxial portion702. In an embodiment, the second epitaxial portion802grows from the inner surface and a portion of the outer surface of the U-shape first epitaxial portion702or sidewall of the residual fin adjacent the upper portion of the U-shaped first epitaxial portion. In a further embodiment, the second epitaxial portion802grows from a portion of the semiconductor surface that extends above the fin spacers604′. In some implementations, second epitaxial portions802are doped (e.g., phosphorous) during deposition by adding impurities to a source material of the epitaxy process. In some implementations, second epitaxial portions802are doped by an ion implantation process subsequent to a deposition process. The second epitaxial portion802merges with second epitaxial portion802of the adjacent fin or fins. The merge point, merge area, and relative dimensions of the second epitaxial portion802are discussed further below. As discussed above, in an embodiment, the first epitaxial portion702wraps an upper active region of each fin structure304(e.g., where the first stage is performed without recessing the fin as described in block202). In a further embodiment, the second epitaxial portion802is similarly formed on exposed surface of the first epitaxial portion702. In such an embodiment, the second epitaxial portion802for one fin continues to merge with an adjacent second epitaxial portion802. In such an embodiment, the merge point and relative dimensions may be substantially similar to as discussed below. In an embodiment, the second epitaxy process is implemented using a vapor-phase epitaxy (VPE) process. In an embodiment, the second epitaxial process is performed in-situ with the first epitaxial process of block204. In an embodiment, the carrier gas of the second epitaxy process may include H2. In a further embodiment, the carrier gas of the second epitaxy process does not include N2. For example, in an embodiment the second epitaxy process includes a source gas(es) including silicon and phosphorous and a carrier gas including H2. In an embodiment, the source gas(es) include a silicon source such as silane, SiH4, or disilane, Si2H6. In an embodiment, the source gas(es) include a phosphorous source such as phosphine, PH3. In an embodiment, the pressure of the second epitaxial process is between approximately 20 Torr to 30 Torr. The carrier gas of H2 may provide for surface activation of the seed; this activation may be improved over that of N2 which may not interact with the seed. The H2 may interact with the dangling bonds on the surface of the first epitaxial portion702providing a faster epitaxial growth rate. The H2 carrier gas may in particular provide for a faster growth rate on the (100)Si oriented surface of the seed (the first epitaxial portion702). The H2 carrier gas can assist in the disassociation of the silicon source gas (e.g., SiH4) rate. It is noted that the carrier gas is not a source gas and thus, does not provide elements to the grown second epitaxial portion802. That is, the H2 carrier gas may be used to activate the surface, but the elemental hydrogen is not included in the grown epitaxial feature. In an embodiment, the deposition temperature of the second epitaxy process may be higher than that of a standard epitaxy process (e.g., first epitaxy process). For example, in an embodiment, the second epitaxy process may include a temperature of approximately 690 to 730° C. In a further embodiment, the second epitaxy process may include a temperature of approximately 700 to 730° C. In comparison, the first epitaxial process (block204) and/or the third epitaxial process (block208) may be performed at a temperature of 670 to 690° C. In an embodiment, the second epitaxy process may be at least 100 degrees Celsius greater than the first epitaxy process and/or the third epitaxy process. The higher temperature may also provide for faster epitaxial growth in particular on the (100)Si oriented surface of the seed (the first epitaxial portion702). In an embodiment, the second epitaxial process includes H2 carrier gas and the elevated temperature discussed above. The faster growth rate may allow for a higher merge point as the growth extends vertically. A lower growth rate provided by a lower temperature may provide a lower merge point due to relatively greater proportion of epitaxial growth in a lateral direction. The higher merge point the more air gap (dielectric) under merged source/drain features, which may reduce capacitance of the device. The highest point of the merged region of second epitaxial portions802is referred to as the merge point, annotated “M” inFIG.8A/8B. In an embodiment, the second epitaxial process provides for a relatively higher merge point M between the second epitaxial portions802of adjacent fin structures304due to the increased growth on the (100) plane of the seed (e.g., temperature and carrier gas dependent). The higher merge point M provides for a taller gap (e.g., air gap) between the fin structures304, above the isolation structure402and underlying the second epitaxial portions802. This air gap804is provided byFIGS.8A/8B. In an embodiment, the merge point M is at approximately 40%-60% of the height H of the fin structure304(above the surface304A). The location of the merge point M can be tuned to determine the capacitance associated with the device. For example, a low merge point height can result in loss of performance for device capacitance. The higher merge point provides for capacitance reduction and improvement of device performance. In an embodiment, the thickness T of the merged region above the merge point M may be between approximately 23.5 and 28.5 nm. In an embodiment, the distance from the isolation region402(top surface) to merge point M may be between approximately 30.5-34 nm. In an embodiment, these measurements are associated with a 65 nm critical dimension process node. In an embodiment, the ratio of the merged thickness T to the critical dimension CD (T/CD) may be between about 0.36 to 0.4. The thickness T affects the available carriers and conductivity between adjacent fins304. For example, too small of a thickness T can lead to discontinuities and reduced interconnection (increased resistance) between adjacent epi features (i.e., left and right feature of second epitaxial portion802). FIG.8Billustrates several additional dimensional illustrations that describe aspects of the second epitaxial portion802. Distance a1 is a vertical distance between a top of the fin structure304and the bottom point of the first epitaxial portion702(e.g., surface304A). Distance b is a length between a top of the fin structure304and a top point of the merge area between second epitaxial portions802. If the distance b is too great, when the subsequent epitaxial layer is grown thereover, the planarity will be decreased. Distance C is a horizontal distance between a fin sidewall and an edge of the second epitaxial portion802. The horizontal distance C is measured at a vertical height of 0.3*a1. Distance d is a measurement of a horizontal distance between adjacent two adjacent fin structures304. The distance d may also be measured at a vertical height of 0.3*a1. The distanced affects the pitch of the devices including device300, the greater the distance d the greater the pitch and the less devices per area of the substrate. In an embodiment, the second epitaxial feature802has a merge top point location at a ratio of b/a1, where b/a1 is between approximately 0.15-0.25. In an embodiment, the second epitaxial feature802has a bottom epitaxial lateral ratio (C*2/d) of between approximately 0.15 and 0.45. If the ratio of the b/a1 is too large, this may impact ability to form a third epitaxial layer having sufficient planarity of the resultant epitaxial feature. These features exemplify the advantages of some embodiments of the method200and block206in particular, that is that the merge top point is higher than features formed by other processes such that the top shape of the second epitaxial portion802is flatter (i.e., distance b is less). The above dimensions provide benefits to the device300including as discussed above and below. Should the dimension C be greater, the merge point M will be lower. A higher merge point M can reduce the capacitance of the device. The merge point M is above a top surface of the fin spacers604′. In an embodiment, there is no fin spacer604′ on the inner sidewalls of the fin304and there is a fin spacer604′ on the outer sidewall of the fin304. In a further embodiment, the merge point M is above a top surface of the fin spacer604′ on the outer sidewall. In an embodiment, there is a fin spacer604′ on the inner and/or outer sidewalls and the merge point (M) is approximately 10-20 nanometers above a top surface of the fin spacer604′. In an embodiment, two inner spacers may connect to one another forming a dielectric region having a U-shape. See dashed line604″ inFIG.8B. In an embodiment, the merge point M is at least 20 nm above a lowest point in the U-shape of the fin spacers604″. In an embodiment, the merge point M is between 20-40 nm above a lowest point in the U-shape of the fin spacers604″. Thus, the air gap formed between the epitaxial feature904(see below) and the nearest dielectric material (e.g., fin spacers604″ or isolation feature402) may be at least 20 nm, or between approximately ⅓ and ⅔ of the fin height above the surface304A. As discussed above, the distance between the merge point M and the fin spacers604″ affect the height of the air gap and thus, the capacitance of the device. An increased air gap provides improved capacitance performance of the device. The method200then proceeds to block208where a third stage of epitaxial growth is performed. Referring to the example ofFIGS.9A/9B, in an embodiment, the third stage of epitaxial growth is performed to form a third epitaxial portion902, also referred to as L2-2. In an embodiment, the third epitaxial portion902is doped silicon such as, for example silicon doped with phosphorous (SiP). In an embodiment, the third epitaxial portion902comprises SiP having a P doping concentration of about 3.8-4.2×1021atoms/cm−3. In an embodiment, the third epitaxial portion902has a dopant concentration (P) greater than the second epitaxial portion802. The third epitaxial portion902is grown from a seed that includes the surface of the second epitaxial portion802. The third epitaxial portion902is grown from all exposed surfaces of the second epitaxial portion802, such that the third epitaxial portion902follows the outline of the second epitaxial portion802. In some implementations, third epitaxial portions902are doped during deposition by adding impurities to a source material of the epitaxy process. In some implementations, third epitaxial portions902are doped by an ion implantation process subsequent to a deposition process. In an embodiment, the third epitaxy process is implemented using a vapor-phase epitaxy (VPE) process. In an embodiment, the third epitaxial process is performed in-situ with the second epitaxial process of block206. In an embodiment, the third epitaxial process is performed at a lower temperature than the second epitaxial process. In an embodiment, the carrier gas of the third epitaxy process (and also, in some embodiments, the first epitaxy process) includes N2. In a further embodiment, the carrier gas of the third epitaxy process does not include H2. For example, in an embodiment the third epitaxy process includes a source gas(es) including silicon and phosphorous and a carrier gas including N2. In an embodiment, the source gas(es) include a silicon source such as silane, SiH4, or disilane, Si2H6. In an embodiment, the source gas(es) include a phosphorous source such as phosphine, PH3. FIG.9Billustrates several dimensional illustrations that show certain aspects of the third epitaxial portion902. The distance e is defined a distance down from the top of the fin structure304that is equal to about ⅕ of the height of the epitaxial feature formed by epitaxial portions702,802,902. The top portion of the second epitaxial portion802is slightly below the distance e, while the top portion of the third epitaxial portion902(and thus, the structure904) is above the distance e. Further, the top surface of the third epitaxial portion902is a distance f2 from the top of the fin304and regions directly overlying the fin304. The distance f2 is a positive value when measured in a first direction, the first direction extending along the height of the fin. The top surface of the third epitaxial layer is a distance f1 from a plane coplanar with a top of the fin304to a top of the third epitaxial portion902measured directly overlying the isolation regions402and/or the merge point M. It is noted that the distance f1 is a positive distance in the first direction, or in other words, the distance f1 is measured in a distance above the top of the fin304. In an embodiment, the ratio of height variation of the epitaxial feature904is (f1/f2) is between approximately 0.5 and 0.9. Because f1 and f2 are positive distances in the first direction, this ratio is a positive number. Should f1 be decreased (e.g., nearer 0 or even negative) or the ratio of f1/further from 1.0, the planarity of the epitaxial feature904surface is decreased. In an embodiment, the dimensions f1 and f2 define not only the distance to the top of the third epitaxial portion902but define the outermost surface of the epitaxial feature904. As illustrated in exemplary figures includingFIGS.9A/9B, the method200may be used to form an epitaxial feature904that includes the first epitaxial portion702, the second epitaxial portion802, and the third epitaxial portion902. Additional epitaxial layers may also be formed. The epitaxial feature904is a merged epitaxial feature. A merged epitaxial feature as described herein provides for the epitaxial feature to extend from one fin to an adjacent fin. While a merged epitaxial feature is illustrated between two fins, a merged epitaxial feature may extend to interface any number of fins. The merged epitaxial feature is referred to as such as the epitaxial growth described herein initiates from a seed surface on at least two fins and through the epitaxial growth joins at least one point such that the epitaxy is laterally merged in a first direction (parallel the gate). It is noted that the first epitaxial layer may not be merged but a second epitaxial layer may be merged. The epitaxial feature904provides a source/drain for FinFET device300. In an embodiment, the epitaxial feature904is suitably doped for a n-type FinFET device300. In some embodiments, the first epitaxial portion702includes a first dopant concentration, the second epitaxial portion802includes a second dopant concentration, and the third epitaxial portion902includes a third dopant concentration. The first dopant concentration may be less than the second dopant concentration; the second dopant concentration may be less than the third dopant concentration. The increasing dopant concentration may serve to provide the appropriate functionality to the device300while also reducing the resistance of the source/drain formed by the epitaxial feature904. In some embodiments, the method200may continue to provide an anneal process. The epitaxial feature904may provide advantageous over that of other embodiments of source/drain features. As illustrated by the dimensional description above, the epitaxial feature904has a relatively flat upper surface of interfacing with the above feature (e.g., contact). That is f1 is a positive dimension substantially close to the length of f2 such that f1/f2 is greater than about 0.5 or that f1 is at least 50% of the length of f2. This increased planarity of the epitaxial feature904may allow for yield improvement for contact element landing on the epitaxial feature904to provide electrical contact to the source/drain feature of the device. The epitaxial feature904also illustrates that the merge point M is increased in height from other embodiments of source/drain features. As illustrated by the dimensional description above, the epitaxial feature904has a larger air gap804. The lateral spread of the second epitaxial portion802is less than half of the distance between fins304(see c). As the growth of the third epitaxial portion902in the air gap is essentially none (due to the merged region preventing source gases from entering the air gap), this distance is maintained in the epitaxial feature904. Returning to the method100ofFIG.1, after formation of the source/drain regions in block108, the method100may proceed to block110where a contact etch stop layer (CESL) and/or an inter-layer dielectric (ILD) layer are formed. Referring to the example ofFIG.10, in an embodiment of block110, a CESL1002and an ILD layer1004are formed over the substrate302. The ILD layer1004may be disposed over the CESL1002. In some examples, the CESL1002includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. The CESL1002may be formed by CVD, ALD, or other suitable process. In some embodiments, the ILD layer1004includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer1004may be deposited by CVD, ALD, or other suitable process. In some embodiments, after formation of the ILD layer1004, an anneal process may be performed to anneal the ILD layer1004. In some examples, after deposition of the CESL1002and the ILD layer1004, a planarization process may be performed to expose a top surface of the gate structure500. The planarization process may include a chemical mechanical planarization (CMP) process which removes portions of the CESL1002and/or the ILD layer1004overlying the gate structure500and planarizes a top surface of the semiconductor device300. The CMP process may also remove the hard mask508of the gate structure500including the oxide layer508A and the nitride layer508B to expose the gate electrode506, which may include a polysilicon layer, as discussed above. The method100then proceeds to block112where, in some embodiments, the gate structure formed in block106is removed for a replacement by a functional meta gate structure. In the embodiment, the dummy gate structure is removed and replaced with a metal gate electrode. In some embodiments, the gate dielectric layer and/or interfacial layers are also removed and replaced. Referring to the example ofFIG.11A, in an embodiment of block112, the dummy gate electrode portion may be removed from the substrate. The removal of the gate electrode layer506may be performed using a selective etching process such as a selective wet etch, a selective dry etch, or a combination thereof. In some embodiments, the gate electrode layer506, dielectric layers502,504are removed. After forms an opening, a metal gate electrode1104may be formed in the trench, as shown inFIG.11A, to form a final gate structure500′. In various examples, the metal gate electrode1104may include a metal, metal alloy, or metal silicide. The metal gate electrode1104may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the metal gate electrode1104may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. In addition, the metal gate electrode1104may provide an N-type work function, may serve as a transistor (e.g., FinFET) gate electrode. In various embodiments, the metal gate electrode1104may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the metal gate electrode1104may be formed separately for N-FET and P-FET transistors which may use different metal layers. In various embodiments, a CMP process may be performed to remove excessive metal from the metal gate electrode1104, and thereby provide a substantially planar top surface of the metal gate electrode1104and of the device300. The gate structure500′ may further include a gate dielectric layer1106and/or an interfacial layer1108. The gate dielectric layer1106may be substantially similar to as discussed above with reference to layer504. In some embodiments, the gate dielectric layer1106is a high-k dielectric material such as hafnium oxide (HfO2), HfZrO, TiO2, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, A10, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The interfacial layer1108may include an oxide such as silicon oxide, silicon oxynitride or other suitable material. The method100may then proceed to block114where contact elements are formed to the source/drain features and/or the gate structure. In some embodiments, an opening is formed in the ILD layer1004over the epitaxial feature904. The opening may be performed by patterning a hard mask or photoresist masking element to define the opening and etching the ILD layer1004through the opening. Patterning may also be implemented or replaced by other proper methods, such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. The removing process to form the opening may include a plasma etch, a reaction ion etch (RIE), a dry etch, a wet etch, another proper removing process, or combinations thereof. A contact fill metal or metals are then formed in the opening and interfacing the epitaxial features904. Various deposition process may be applied to deposit material forming the contacts1202. For example, the deposition of the copper may include PVD to form a seed layer and plating to form bulk copper on the copper seed layer. In some embodiments, prior to filling conductive material in contact openings, silicide may be formed on the epitaxial features904to further reduce the contact resistance. In some embodiments, the silicide may convert a portion of the third epitaxial portion902to a silicide. The silicide includes silicon and metal, such as titanium silicide, tantalum silicide, nickel silicide or cobalt silicide. The silicide may be formed by a process referred to as self-aligned silicide (or salicide). The process includes metal deposition, annealing to react the metal with silicon, and etching to remove unreacted metal. Filling the contact openings form conductive contact features1102as illustrated inFIGS.11A,11B, and the top view ofFIG.11C. As depicted inFIGS.9B and11B, contact1102advantageously contacts a top surface of the epitaxial feature904that is substantially planar. This allows for proper landing of the contact1102onto the epitaxial feature904and suitable interface between the features reducing contact resistance. The semiconductor device300may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form additional interlayer dielectric (ILD) layer(s), additional contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate302, configured to connect the various features to form a functional circuit that may include one or more FinFET devices including FinFET device300. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method100. Thus, the methods100and200and the associated exemplary devices300provide in some embodiments for an improved structural configuration of the source/drain of a FinFET device and/or improvements in the interface between the contact structure and the epitaxial feature forming the source/drain of a FinFET device. Some embodiments provide a method of forming the epitaxial feature that allows for a higher merge point, increasing the air gap (dielectric) under merged source/drain features, which may reduce capacitance of the device. Some embodiments provide for a merged epitaxial feature with a more planar top surface allowing for a more uniform landing area for the contact element. Thus, one of the embodiments of the present disclosure described a method that includes forming a first fin structure and a second fin structure extending from a substrate. A gate structure is formed over the first fin structure and the second fin structure. An epitaxial feature is form over the first fin structure and the second fin structure. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure. In a further embodiment, growing the second epitaxial feature uses hydrogen (H2) as a carrier gas. In another embodiment, the growing the second epitaxial feature includes a silicon source and a phosphorous source and the carrier gas. In an embodiment, growing the second epitaxial feature is performed at a first temperature of between about 690 and 730 degrees Celsius. In a further embodiment, growing the first epitaxial feature is performed a second temperature less than the first temperature. A first distance between an upper point on the merged portion and a top of the first fin structure divided by a height of the first fin structure over an isolation structure extending between the first fin structure and the second fin structure may be between about 0.15 and 0.25. In an embodiment, prior to forming the epitaxial feature, each of the first fin structure and the second fin structure are recessed to form a recessed surface for each of the first fin structure and the second fin structure. The first epitaxial feature is grown from the recessed surfaces. The first epitaxial feature may have a U-shape. In an embodiment, growing the second epitaxial feature includes forming the second epitaxial feature doped with phosphorous. In an embodiment, growing the first epitaxial feature includes growing a U-shaped feature that extends above an adjacent fin spacer. In another of the embodiments, discussed is a method including forming a first fin structure and a second fin structure extending from a substrate and having an isolation region interposing the first fin structure and the second fin structure. A gate structure is formed over each of the first in structure and the second fin structure. A source/drain feature is formed adjacent the gate structure. Forming the source/drain feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure. A second silicon phosphorous (SiP) epitaxial feature is grown over the first and second portions of the first epitaxial feature. Growing the second SiP epitaxial feature uses an H2 carrier gas. The second silicon phosphorous epitaxial feature includes a merged portion between the first fin structure and the second fin structure. A third epitaxial feature is grown over the second SiP epitaxial feature. A contact element is formed to the third epitaxial feature. In a further embodiment, growing the first epitaxial feature includes growing a SiP epitaxial feature using an N2 carrier gas. Growing the third epitaxial feature may further include growing a SiP epitaxial feature using an N2 carrier gas. In an embodiment, growing the second silicon phosphorous (SiP) epitaxial feature is performed at a higher temperature than the growing the first epitaxial feature. In an embodiment, growing the second SiP epitaxial feature includes a silicon source gas, a phosphorous source gas, and the H2 carrier gas. Growing the second SiP epitaxial feature may in some cases include a vapor-phase epitaxy process. In an embodiment, growing the third epitaxial feature includes forming a top surface of the source/drain feature that extends from over the first fin structure to over the second fin structure. The top surface of the source/drain feature is entirely above a plane defined by a top surface of the first fin structure. In another embodiment, discussed is a semiconductor device having a first fin structure and a second fin structure extending from a substrate and having an isolation region interposing the first fin structure and the second fin structure. A gate structure is over a first region of a top surface of each of the first fin structure and the second fin structure. A silicon phosphorous (SiP) epitaxial source/drain feature is disposed adjacent the gate structure. The SiP epitaxial source/drain feature extends over the first fin structure and the second fin structure. The SiP epitaxial source/drain feature includes a top surface above the isolation region between the first and second fin structures above the first region of the top surface of the first fin structure and the second fin structure. In a further embodiment, the SiP epitaxial source/drain feature has a merge point between the isolation region and the top surface of the SiP epitaxial source/drain feature. In some embodiments, the merge point is approximately 40%-60% of a height of the first fin structure above a bottom of the SiP epitaxial source/drain feature. In a further embodiment, spacers elements interface a bottom of the SiP epitaxial source/drain feature. In some implementations, a contact structure interfaces the top surface of the SiP epitaxial source/drain feature. In an embodiment, a bottom of the SiP epitaxial source/drain feature interfaces a recessed portion of the first fin structure and a recessed portion of the second fin structure. In some implementations, a top surface of the isolation region is concave. In yet another of the embodiments, discussed is a semiconductor device. The device includes a substrate including a first fin element and a second fin element extending from the substrate, an isolation structure extending between the first fin element and the second fin element, a gate structure formed over the first fin element and the second fin element; and a source/drain feature adjacent the gate structure and over the first fin element and the second fin element. The source/drain feature has a top surface having a first height above a plane defined by a top surface of the first fin element and a second height above the plane, and a third height above the plane. The first height is defined over the first fin element and the third height is defined over the second fin element. The second height is defined over the isolation structure. A ratio of the third height to the first height is approximately 0.5 to 0.9. In a further embodiment, an air gap is disposed under the source/drain feature. The air gap may extend to a merge point that is approximately 40%-60% of a height of the first fin element above a bottom of the source/drain feature. The third height is measured at a point vertically aligned with the merge point. In a further embodiment, the source/drain feature includes three silicon epitaxial portions each having a different phosphorous doping concentration. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 63,394 |
11862713 | DETAILED DESCRIPTION The present disclosure relates generally to integrated circuit devices, and more particularly, to fin-like field effect transistor (FinFET) devices. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. FIG.1is a flow chart of a method100for fabricating an integrated circuit device according to various aspects of the present disclosure. In some implementations, as described herein, method100fabricates an integrated circuit device that includes a FinFET device. At block110, method100includes forming a fin structure, for example, over a substrate. The fin structure includes a crystalline material (in other words, a material having an ordered atomic structure), such as silicon organized in a crystalline structure. In some implementations, the fin structure includes a channel region disposed between a source region and a drain region. At block120, a doped amorphous layer is formed over the fin structure. The doped amorphous layer includes a material having a non-crystalline structure (in other words, a material having a disordered atomic structure). In some implementations, the doped amorphous layer includes the same material as the fin structure, except the material of the doped amorphous layer has a non-crystalline structure. For example, the fin structure includes silicon in a crystalline structure, while the doped amorphous layer includes silicon in a non-crystalline structure, such as amorphous silicon. In some implementations, the doped amorphous layer and the fin structure include different materials. For example, the fin structure includes silicon germanium in a crystalline structure, and the doped amorphous layer includes silicon in a non-crystalline structure, such as amorphous silicon. In some implementations, the doped amorphous layer has a higher dopant concentration than the fin structure. In implementations where the fin structure and the doped amorphous layer include the same material, but different atomic structures, the material of the doped amorphous layer has a higher dopant concentration than the material of the fin structure. In some implementations, the material of the fin structure is undoped. In some implementations, the doped amorphous layer is formed over the source region and the drain region of the fin structure. In such implementations, before forming the doped amorphous layer, a gate structure can be formed over the channel region of the fin structure. At block130, a knock-on implantation process is performed to drive dopant from the doped amorphous layer into a portion of the fin structure, thereby forming a doped feature. In some implementations, the doped feature is a lightly doped source and drain feature (or region) disposed in the source region and/or the drain region of the fin structure. In some implementations, the doped feature (or region) is a doped well of the FinFET device, such as a doped well for defining an active region of the FinFET device (in such implementations, the fin structure may be undoped before the knock-on implantation process). The knock-on implantation process causes at least a portion of the doped amorphous layer to become a part of the fin structure. In particular, the knock-on implantation process can convert at least a portion of the non-crystalline material of the doped amorphous layer into crystalline material. The knock-on implantation process can thus order an atomic structure of a portion of the doped amorphous layer. In implementations where the fin structure includes silicon and the doped amorphous layer includes amorphous silicon, the knock-on implantation process crystallizes at least a portion of the amorphous silicon, thereby forming a doped silicon feature (region) of the fin structure that includes a converted (or crystallized) portion of the doped amorphous layer and a doped portion of the fin structure. In implementations where the fin structure includes silicon germanium and the doped amorphous layer includes amorphous silicon, the knock-on implantation process crystallizes at least a portion of the amorphous silicon, thereby forming a doped feature (region) of the fin structure that includes a converted (or crystallized) portion of the doped amorphous layer (for example, in some implementations, a silicon capping layer) and a doped portion of the fin structure. In implementations where a portion of the doped amorphous layer becomes a part of the fin structure, method100can proceed with removing a remaining portion of the doped amorphous layer. In such implementations, removing the remaining portion of the doped amorphous layer can include oxidizing the remaining portion of the doped amorphous layer, and performing a wet etching process and/or a cleaning process to remove the oxidized remaining portion. In some implementations, before forming the doped amorphous layer, a trimming process is performed to reduce a dimension (such as a width) of the fin structure. In such implementations, the knock-on implantation process converts the entire doped amorphous layer into a part of the fin structure (in other words, into crystalline material), such that no portion of the doped amorphous layer remains. Such implementations eliminate the need for any subsequent wet etching process and/or subsequent cleaning process. In some implementations, a thickness of the doped amorphous layer is equal to a thickness (or width) of the fin structure removed during the trimming process. At block140, method100can continue to complete fabrication of the FinFET device. For example, in implementations where the gate structure includes a dummy gate, a gate replacement process is performed to replace the dummy gate with a metal gate. In implementations where the doped feature defines an active region of the FinFET device, method100can proceed with forming additional IC features to fabricate a functional FinFET device. Additional steps can be provided before, during, and after method100, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method100. The discussion that follows illustrates various embodiments of FinFET devices that can be fabricated according to method100. FIGS.2A-2Eare fragmentary cross-sectional views of a FinFET device200, in portion or entirety, at various fabrication stages (such as those associated with method100) according to various aspects of the present disclosure. FinFET device200may be included in a microprocessor, a memory, and/or other integrated circuit device. In some implementations, FinFET device200may be a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof.FIGS.2A-2Ehave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in FinFET device200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of FinFET device200. InFIG.2A, FinFET device200includes a substrate (wafer)210. Substrate210includes a crystalline material, which generally refers to a material having an ordered atomic structure (often referred to as a crystalline structure). For example, in the depicted embodiment, substrate210includes silicon in a crystalline structure. Alternatively or additionally, substrate210includes another elementary semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Alternatively, substrate210is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. Substrate210can include various doped regions (not shown) depending on design requirements of FinFET device200. In some implementations, substrate210includes p-type doped regions (for example, p-type wells) doped with p-type dopants, such as boron, indium, other p-type dopant, or combinations thereof. In some implementations, substrate210includes n-type doped regions (for example, n-type wells) doped with n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. In some implementations, substrate210includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions can be formed directly on and/or in substrate210, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and/or other suitable doping process can be performed to form the various doped regions in substrate210. A fin structure220is formed over substrate210using any suitable process. InFIG.2A, fin structure220includes a plurality of fins222extending from substrate210, though the present disclosure contemplates embodiments where fin structure220includes a single fin222extending from substrate210. In some implementations, fin structure220is a portion of substrate210(such as a portion of a material layer of substrate210). For example, in the depicted embodiment, where substrate210includes a crystalline material, fin structure220includes the same crystalline material, such as silicon in a crystalline structure. Alternatively, in some implementations, fin structure220is defined in a material layer including a semiconductor material in a crystalline structure overlying substrate210, such as silicon germanium in a crystalline structure. In some implementations, fin structure220can include a semiconductor layer stack (for example, a heterostructure) having various semiconductor layers. The semiconductor layers include any suitable material in a crystalline structure, such as silicon, germanium, silicon germanium, other suitable material, or combinations thereof. The semiconductor layers can include same or different materials, etching rates, constituent atomic percentages, constituent weight percentages, thicknesses, and/or configurations depending on design requirements of FinFET device200. Each fin222has a height h, a width w1defined by a pair of sidewalls, and a length l defined by a pair of sidewalls (not shown in the depicted view). Adjacent fins222are separated by a space S1, where a pitch P of fins222generally refers to a sum of a width of a particular fin222(such as w1) and a width of a space adjacent to the particular fin222(such as S1) (in other words, P=w1+S1). In some implementations, pitch P is a minimum pitch achievable between fins222by a lithography process for a given technology node. In some implementations, height h is about 30 nm to about 80 nm, and width w1is about 1 nm to about 30 nm. For example, in the depicted embodiment, height h is about 30 nm to about 80 nm, and width w1is about 2 nm to about 20 nm. In some implementations, space S1is about 10 nm to about 30 nm. In some implementations, pitch P is about 10 nm to about 50 nm. The present disclosure contemplates variations in height h, width w1, and length l of fins222that may arise from processing and fabrication of FinFET device200. For example, though each fin222is depicted as having substantially the same width w1along height h, in some implementations, width w1represents an average width of a given fin222. In some implementations, a width of fins222varies from an upper portion of fins222to a lower portion of fins222, where width w1represents an average of the varying widths. In some implementations, the width tapers from the upper portion of fins222to the lower portion of fins222, such that an average width of the upper portion is less than an average width of the lower portion. In some implementations, width w1can vary from about 5 nm to about 15 nm along fins222depending on where width w1is measured along height h of fins222. In some implementations, width w1of fins222varies depending on a position of fins222relative to one another and/or relative to other features of FinFET device200. For example, width w1of center fins222(in the depicted embodiment, FinFET device200includes two center fins222) may be greater than width w1of edge fins222(here, the leftmost fin222and the rightmost fin222, which enclose the two center fins222). In another example, alternatively, width w1of center fins222is less than width w1of edge fins222. In both such implementations, width w1of edge fins222can represent an average width of edge fins222, and width w1of center fins222can represent an average width of center fins222. A combination of deposition, lithography, and/or etching processes are performed to define fins222extending from substrate210as illustrated inFIG.2A. For example, forming fin structure220includes performing a lithography process to form a patterned resist layer over substrate210(or a material layer disposed over substrate210) and performing an etching process to transfer a pattern defined in the patterned resist layer to substrate210(or the material layer disposed over substrate210). The lithography process can include forming a resist layer on substrate210(for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. The etching process removes portions of substrate210, where the etching process uses the patterned resist layer as an etch mask. The etching process can include a dry etching process, a wet etching process, other suitable etching process, or combinations thereof. In some implementations, a reactive ion etching (RIE) process is performed. After the etching process, the patterned resist layer is removed from substrate210, for example, by a resist stripping process. Alternatively, fin structure220is formed by a multiple patterning process, such as a double patterning lithography (DPL) process (for example, a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning process, or combinations thereof), a triple patterning process (for example, a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning process, or combinations thereof), other multiple patterning process (for example, self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some implementations, directed self-assembly (DSA) techniques are implemented while forming fin structure220. Further, in some alternate implementations, the exposure process can implement maskless lithography, electron-beam (e-beam) writing, ion-beam writing, and/or nanoimprint technology for patterning the resist layer. InFIG.2B, a trimming process is performed to trim fin structure220, thereby reducing a dimension of fins222. For example, the trimming process decreases a width of fins222, such that fins222have a width w2after the trimming process that is less than width w1. The trimming process also increases spacing between fins222, such that adjacent fins222are separated by a space S2that is greater than space S1. In some implementations, the trimming process reduces a width of fins222about 2 nm to about 20 nm, though the present disclosure the trimming process removing different amounts of fins222. For example, in some implementations where width w1is about 5 nm to about 30 nm, the trimming process reduces the width of fins222, such that width w2is about 2 nm to about 20 nm. In some implementations, the trimming process can ease formation of subsequently formed layers (for example, by increasing spacing between fins222). Though not depicted, it is understood that the trimming process may reduce height h of fins222. In some implementations, the trimming process is tuned (or controlled) to reduce width w1while minimally affecting height h of fins222(for example, width w1of fins222is reduced at a faster rate than height h of fins222). In some implementations, the trimming process is tuned to reduce width w1and height h at about the same rate, such that fins222also have a reduced height (though such is not depicted). Further, the present disclosure contemplates variations in height h, width w2, and length l of fins222that may arise from the trimming process. For example, width w2may vary along fins222similarly to width w1as described above. In some implementations, the trimming process is applied to a subset of fins222, where some fins222are not trimmed by the trimming process. The trimming process implements any suitable process for reducing the dimension of fins222. For example, in some implementations, the trimming process includes an etching process that can selectively etch fins222relative to other features of FinFET device200. The etching process is a dry etching process, a wet etching process, or combinations thereof. In some implementations, a wet etching process implements an etching solution that includes ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), tetramethylammonium hydroxide (TMAH), other suitable wet etching solution, or combinations thereof. For example, the wet etching solution can utilize an NH4OH:H2O2solution, an NH4OH:H2O2:H2O solution (known as an ammonia-peroxide mixture (APM)), or an H2SO4:H2O2solution (known as a sulfuric peroxide mixture (SPM)). In some implementations, a dry etching process implements an etchant gas that includes a fluorine-containing etchant gas (for example, CF4, SF6, CH2F2, CHF3, and/or C2F6), an oxygen-containing gas, a chlorine-containing gas (for example, Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (for example, HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. In some implementations, the trimming process implements an oxidation process. For example, the trimming process can expose fins222to an ozone environment, thereby oxidizing a portion of fins222, which is subsequently removed by a cleaning process and/or an etching process, such as those described herein. By controlling the trimming process (such as trimming time, trimming process conditions, or other trimming parameter), a profile of fins222can be modified to meet various design requirements of FinFET device200. For example, where the trimming process includes an etching process, various etching parameters, such as etchant used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and/or other suitable etching parameters, are modified to remove a desired amount of fins222and/or to achieve a desired profile of fins222. InFIG.2C, a doped amorphous layer230is formed over fin structure220. Doped amorphous layer230includes a material having a non-crystalline structure (in other words, a material having a disordered atomic structure). In some implementations, doped amorphous layer230and fin structure220include the same material, but with different atomic structures. For example, doped amorphous layer230includes the same material as fin structure210, except the material has a non-crystalline structure. In the depicted embodiment, where fin structure220includes silicon in a crystalline structure, doped amorphous layer230includes silicon in a non-crystalline structure, such as amorphous silicon. Doped amorphous layer230may thus be referred to as a doped amorphous silicon layer. Alternatively, in some implementations, doped amorphous layer230and fin structure include different materials with different atomic structures. For example, fin structure220includes a semiconductor material, such as silicon germanium, and doped amorphous layer230includes silicon in a non-crystalline form, such as amorphous silicon. Depending on design requirements of FinFET device200, doped amorphous layer230includes n-type dopants, p-type dopants, or combinations thereof. Where FinFET device200is configured as a p-type FinFET device, doped amorphous layer230includes p-type dopants, such as boron, germanium, indium, other p-type dopant, or combinations thereof. Where FinFET device200is configured as an n-type FinFET device, doped amorphous layer230includes n-type dopants, such as arsenic, phosphorus, other n-type dopant, or combinations thereof. In some implementations, doped amorphous layer230is heavily doped with a dopant having a dopant concentration in a range from about 1×1021dopants/cm3(cm−3) to about 4×1021cm−3. In some implementations, doped amorphous layer230has a higher dopant concentration than fin structure220. For example, doped amorphous layer230may have a dopant concentration in a range from about 1×1021cm−3to about 4×1021cm−3, while fin structure220may have a dopant concentration in a range from about 1×1010cm−3to about 1×1018cm−3(in some implementations, fin structure220is considered undoped or intrinsic at or below such doping concentrations). Doped amorphous layer230wraps fin structure220. For example, fins222include a top portion defined between sidewall portions (such as the sidewalls defining width w2of fins222), where doped amorphous layer230is disposed on the top portion and sidewall portions. In some implementations, the top portion is a substantially horizontal side (for example, substantially parallel to an x-y plane) of fin structure220, while sidewall portions are substantially vertical sides (for example, substantially parallel to an x-z plane) of fin structure220. Doped amorphous layer230has a thickness t. In some implementations, doped amorphous layer230has a thickness t is about 1 nm to about 10 nm. For example, in the depicted embodiment, thickness t is about 3 nm to about 5 nm. In some implementations, a final width of fins222will meet a defined target width (wt), such as a critical dimension defined by design specifications and/or an integrated circuit (IC) design layout for FinFET device200. In such implementations, a width w3represents width w2of fins222combined with thickness t of doped amorphous layer230(for example, w3≈w2+t), where width w3is substantially equal to target width wt(for example, w3≈wt). In some implementations, thickness t is substantially equal to a width wrof fins222removed during the trimming process (for example, t≈wr). The present disclosure contemplates variations in width w3and thickness t arising from processing as described herein. Doped amorphous layer230is formed by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), spin coating, plating, other deposition method, or combinations thereof. In the depicted embodiment, doped amorphous layer230is conformally deposited over fin structure220, such that thickness t is substantially uniform over exposed surfaces of fin structure220and/or substrate210. Any suitable process (for example, an ion implantation process, a diffusion process, an in-situ doping process, or combinations thereof) can be implemented for doping the material deposited over the fin structure220. In some implementations, a selective epitaxial growth (SEG) process is performed to grow a semiconductor material on exposed portions of fin structure220, where dopants are introduced into the semiconductor material during the SEG process (for example, by adding dopants to a source material of the SEG process), thereby forming doped amorphous layer230. The SEG process can implement CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The SEG process can use gaseous precursors (for example, silicon-containing gases, such as SiH4and/or germanium-containing gases, such as GeH4) and/or liquid precursors, which interact with a composition of fin structure220. For example, in the depicted embodiment, where doped amorphous layer230is a doped amorphous silicon layer, the deposition process can expose fin structure220(and substrate210) to a silicon-containing gas (for example, a silicon hydride containing gas (such as SiH4, Si2H6, Si3H8, Si4H10, or combinations thereof)) and add dopants (for example, germanium, boron, arsenic, phosphorous, or combinations thereof) to the silicon-containing gas. In some implementations, doped amorphous layer230includes materials and/or dopants that achieve desired tensile stress and/or compressive stress in a channel region of FinFET device200. InFIG.2D, a knock-on implantation process240is performed on doped amorphous layer230, thereby forming a doped feature250. Knock-on implantation process240bombards doped amorphous layer230with ions242, where ions242drive dopant from doped amorphous layer230into fin structure220and/or substrate210(in other words, ions242knock dopant from doped amorphous layer230into fin structure220and substrate210). Ions242can include carbon, germanium, argon, nitrogen, and/or ions that will not adversely affect the operating characteristics of FinFET device200. In the depicted embodiment, ions242are argon atoms. In some implementations, ions242are non-doping species. Knock-on implantation process240can be performed at a tilt angle α, where the tilt angle α can be tuned to minimize shadowing effects while maximizing ion depth into doped amorphous layer230and/or dopant depth into fin structure220and/or substrate210. In some implementations, knock-on implantation process240is a plasma immersion ion implantation (PIII) process (also referred to as plasma doping). In some implantations, knock-on implantation process240is performed at a temperature of about 20° C. to about 40° C., and in some implementations, is performed at about room temperature (for example, about 20° C. to about 25° C.). In some implantations, knock-on implantation process240uses a bias voltage (also referred to as an implant voltage) of about 1 kV to about 5 kV. In some implementations, bias voltage generally refers to a DC bias voltage applied to substrate210during knock-on implantation process240. Knock-on implantation process240is achieved with much lower implant voltages than those implemented by traditional doping techniques for fin structure220. For example, traditional ion implantation processes typically require bias voltages of about 8 kV to about 15 kV, while other doping techniques can require bias voltages of about 20 kV to about 50 kV to ensure that dopants penetrate fins to sufficient depths. Such high voltage implantation processes have been observed to damage fins, often damaging a profile of the fins. In contrast, performing knock-on implantation process240on doped amorphous layer230using bias voltages less than about 5 kV can sufficiently drive dopants into fin structure220(in some implementations, driving dopants as much as 20 nm into fin structure220) without damaging a profile of fin structure220, thereby providing improvements over traditional doping techniques. Furthermore, knock-on implantation process240can better control dopant profiles of fin structure220compared to traditional ion implantation processes, which often exhibit less effective dopant profiles, resulting from dopant scattering and dopant angle constraints of the traditional ion implantation processes. By driving dopant into fins222, knock-on implantation process240forms a doped portion252of fins222, while also causing at least a portion of doped amorphous layer230to become a part of fin structure220. In particular, knock-on implantation process240modifies an atomic structure of a portion of doped amorphous layer230, converting (crystallizing) a portion of the non-crystalline material of doped amorphous layer230into crystalline material. In the depicted embodiment, knock-on implantation process240converts doped amorphous layer230into doped layer254, such that doped amorphous layer230in its entirety becomes a part of fin structure220and no portion of doped amorphous layer230remains. Doped feature250thus includes doped portion252and doped layer254. Where fin structure220includes silicon and doped amorphous layer230includes amorphous silicon, knock-on implantation process240crystallizes the amorphous silicon (in other words, reorders its atomic structure), such that doped feature250is a doped silicon feature. Alternatively, where fin structure220includes silicon germanium (or other semiconductor material) and doped amorphous layer230includes amorphous silicon, knock-on implantation process240crystallizes the amorphous silicon (in other words, reorders its atomic structure), such that doped feature250is includes a doped silicon feature and a doped silicon germanium (or other semiconductor material) feature. In some implementations, doped layer254is a silicon capping layer. In some implementations, doped feature250is a lightly doped source and drain (LDD) feature (or region) disposed in a source region and/or a drain region of fin structure220. In some implementations, doped feature250is a doped well (or region) of FinFET device200, such as a doped well for defining an active region of FinFET device200. It has been observed that doped feature250exhibits deeper, greater, and/or more uniform doping profiles compared to doped features formed using traditional doping techniques, such as ion implantation processes and/or knock-on implantation processes using doped layers having materials in crystalline structures. In some implementations, doped feature250has a dopant concentration in a range from about 1×1020cm−3to about 5×1020cm−3. In some implementations, a doping concentration in doped feature250is substantially uniform across a width and/or a height of fins222. In some implementations, the doping concentration is considered substantially uniform when the doping concentrations at any defined number of points across the width of doped feature250, across the height of doped feature250, and/or within doped feature250are within ±5% of each other. In some implementations, a dopant concentration of doped portion252is substantially the same to a dopant concentration of doped layer254. In some implementations, the doping concentration is considered substantially the same when the doping concentration of doped portion252(such as an average doping concentration) and the doping concentration of the doped layer254(such as an averaged doping concentration) are within ±5% of each other. Traditional doping techniques for FinFETs often require removal of a material layer (such as a doped layer) after forming a doped feature, which causes surface damage and/or other damage to the fin structure. By converting the doped amorphous layer230into a part of fin structure220, no further processing is required for removing doped amorphous layer230, leaving FinFET device200as depicted inFIG.2E. Subsequent wet etching processes and/or subsequent cleaning processes can thus be eliminated, minimizing surface damage (such as surface roughness) and/or other damage to fin structure220. Further, converting doped amorphous layer230into a part of fin structure220minimizes space S3between fins222, improving fin-to-fin merging process windows (for example, where epitaxial source and drain features are subsequently formed on fins222, where such epitaxial source and drain features combine to form a merged epitaxial source and drain feature). FIGS.3A-3Eare fragmentary cross-sectional views of a FinFET device300, in portion or entirety, at various fabrication stages (such as those associated with method100) according to various aspects of the present disclosure. In some implementations, FinFET device300may be a portion of IC chip, an SoC, or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, MOSFETs, CMOSs, BJTs, LDMOS s, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. FinFET device300is similar in many respects to FinFET device200. Accordingly, similar features inFIGS.2A-2EandFIG.3A-3Eare identified by the same reference numerals for clarity and simplicity.FIGS.3A-3Ehave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in FinFET device300, and some of the features described below can be replaced, modified, or eliminated in other embodiments of FinFET device300. InFIG.3A, similar to FinFET device200, FinFET device300includes substrate210and fin structure220(including fins222extending from substrate210), which are described in detail above with reference toFIG.2A. In contrast to fabrication of FinFET device200, no trimming process is performed on FinFET device300. InFIG.3B, fabrication of FinFET device300thus proceeds with forming doped amorphous layer230over fin structure220, which is described in detail above with reference toFIG.2C. InFIG.3C, similar to FinFET device200, knock-on implantation process240is performed on doped amorphous layer230, where ions242drive dopant from doped amorphous layer230into fin structure220and/or substrate210, as described in detail above with reference toFIG.2D. In contrast to fabrication of FinFET device200, only a portion of doped amorphous layer230becomes a part of fin structure220during knock-on implantation process240, such that fin structure220includes a doped feature350, which includes a doped portion352of fins222and a doped layer354(alternatively referred to as a converted portion of doped amorphous layer230). For example, knock-on implantation process240converts only a portion of doped amorphous layer230into doped layer354, such that a portion of doped amorphous layer230remains over fin structure220. In particular, knock-on implantation process240modifies an atomic structure of a portion of doped amorphous layer230, converting (crystallizing) a portion of the non-crystalline material of doped amorphous layer230into crystalline material. Where fin structure220includes silicon and doped amorphous layer230includes amorphous silicon, knock-on implantation process240crystallizes the amorphous silicon (in other words, reorders its atomic structure), such that doped feature350is a doped silicon feature. Alternatively, where fin structure220includes silicon germanium (or other semiconductor material) and doped amorphous layer230includes amorphous silicon, knock-on implantation process240crystallizes the amorphous silicon (in other words, reorders its atomic structure), such that doped feature350is includes a doped silicon feature and a doped silicon germanium (or other semiconductor material) feature. In some implementations, doped layer354is a silicon capping layer. In further contrast to FinFET device200, knock-on implantation process140drives dopant partially into fin structure220, such that FinFET device300includes fins222having doped portion352and an undoped portion356(which, in some implementations, indicates portions of fins222having a doping concentration that is less than a doping concentration of doped portion352). After the knock-on implantation process140, doped amorphous layer230has a thickness t1, and doped layer354has a thickness t2, both of which are less than an original thickness of doped amorphous layer230(here, thickness t). In some implementations, thickness t1is about 1 nm to about 7 nm, and thickness t2is about 1 nm to about 3 nm. In some implementations, a final width of fins222will meet a defined target width (wt), such as a critical dimension defined by design specifications and/or an integrated circuit (IC) design layout for FinFET device300. In such implementations, a width w4represents width w1of fins222combined with thickness t2of doped layer354(for example, w4≈w1+t2), where width w4is substantially equal to target width wt(for example, w4≈wt). In some implementations, knock-on implantation process240is tuned to ensure that a sufficient portion of doped amorphous layer230is converted into doped layer354, such that width w4is substantially equal to target width wt. The present disclosure contemplates variations in width w4, thickness t1, and thickness t2arising from processing as described herein. In some implementations, doped feature350is a lightly doped source and drain feature (or region) disposed in a source region and/or a drain region of fin structure220. In some implementations, doped feature350is a doped well (or region) of FinFET device300, such as a doped well for defining an active region of FinFET device300. It has been observed that doped feature350exhibits deeper, greater, and/or more uniform doping profiles compared to doped features formed using traditional doping techniques, such as ion implantation processes and/or knock-on implantation processes using doped layers having materials in crystalline structures. In some implementations, doped feature350has a dopant concentration in a range from about 1×1020cm−3to about 5×1020cm−3. In some implementations, a doping concentration in doped feature350is substantially uniform across its thickness. In some implementations, the doping concentration is considered substantially uniform when the doping concentrations at any defined number of points across a thickness of doped feature350are within ±5% of each other. In some implementations, a dopant concentration of doped portion352is substantially the same to a dopant concentration of doped layer354. In some implementations, the doping concentration is considered substantially the same when the doping concentration of doped portion352(such as an average doping concentration) and the doping concentration of the doped layer354(such as an averaged doping concentration) are within ±5% of each other. Any remaining portion of doped amorphous layer230is removed by a suitable process. InFIG.3D, an oxidation process is performed on doped amorphous layer230, thereby forming an oxidized doped amorphous layer360. In some implementations, the oxidation process is a high temperature oxidation process. For example, doped amorphous layer230is exposed to an ozone environment at a temperature of about 800° C. to about 1,000° C., thereby oxidizing doped amorphous layer230. In some implementations, the oxidation process is a rapid thermal oxidation (RTO) process. Subsequently, oxidized doped amorphous layer360is removed by a suitable wet etching process and/or cleaning process, leaving FinFET device300as depicted inFIG.3E. In some implementations, the cleaning process is an SPM cleaning process, for example, implementing an SPM wet etching solution. In such implementations, the SPM cleaning process can be performed at a temperature of about 150° C. to about 200° C. By oxidizing the doped amorphous layer230, gentler wet etching processes and/or cleaning processes can be implemented to remove oxidized doped amorphous layer360, minimizing or eliminating surface damage (such as surface roughness) and/or other damage to fin structure220, compared to wet etching processes and/or cleaning processes used in traditional doping techniques. Further, converting a portion of doped amorphous layer230into a part of fin structure220minimizes space S4between fins222, improving fin-to-fin merging process windows (for example, where epitaxial source and drain features are subsequently formed on fins222, where such epitaxial source and drain features combine to form a merged epitaxial source and drain feature). FIG.4is a perspective, three-dimensional view of FinFET device400(for example, in an x-y-z plane) after undergoing processing as described with reference toFIGS.2A-2Eto form lightly doped source and drain regions according to various aspects of the present disclosure. FinFET device400may be included in a microprocessor, a memory, and/or other integrated circuit device. In some implementations, FinFET device400may be a portion of IC chip, an SoC, or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, MOSFETs, CMOS s, BJTs, LDMOS s, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. FinFET device400is similar in many respects to FinFET device200. Accordingly, similar features inFIGS.2A-2EandFIG.4are identified by the same reference numerals for clarity and simplicity.FIG.4has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in FinFET device400, and some of the features described below can be replaced, modified, or eliminated in other embodiments of FinFET device400. Similar to FinFET device200, FinFET device400includes substrate210and fin structure220, which includes fins222extending from substrate210. InFIG.4, fins222extend from substrate210in a z-direction, such that fins222have heights defined in the z-direction (such as height h), lengths defined in an x-direction, and widths and/or spacings defined in a y-direction (such as width w1, width w2, width w3, spacing S1, spacing S2, and spacing S3). Each fin222has a channel region402, a source region404, and a drain region406defined along the length of respective fins222(here, along the x-direction), where channel region402is disposed between source region404and drain region406(generally referred to as source/drain regions). Each channel region402includes a top portion defined between sidewall portions of a respective fin222, where the top portion and the sidewall portions engage with a gate structure410(described in detail below), such that current can flow between a respective source region404and a respective drain region406during operation of FinFET device400. InFIG.4, gate structure410blocks view of channel regions402of fins222. In some implementations, the top portion is a substantially horizontal side (for example, substantially parallel to an x-y plane) of fins222, while the two sidewall portions are substantially vertical sides (for example, substantially parallel to an x-z plane) of fins222. Fabricating FinFET device400is similar to fabrication of FinFET device200described with reference toFIGS.2A-2E. However, before forming doped amorphous layer230, an isolation feature(s)420is formed over and/or in substrate210to isolate various regions, such as various device regions, of FinFET device400. For example, isolation features420separate and isolate fins222from each other. In the depicted embodiment, isolation features420surround a portion of fin structure220, such as a bottom portion of fin structure220. Isolation features420include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material, or combinations thereof. Isolation features420can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. In some implementations, isolation features420include STI features that define and electrically isolate fin structures220from other active device regions and/or passive device regions. For example, STI features can be formed by etching trenches in substrate210(for example, by using a dry etch process and/or wet etch process) and filling the trench with insulator material (for example, by using a chemical vapor deposition process or a spin-on glass process). A chemical mechanical polishing (CMP) process may be performed to remove excessive insulator material and/or planarize a top surface of isolation features420. In another example, STI features can be formed by depositing an insulator material over substrate210after forming fin structure220(in some implementations, such that the insulator material layer fills gaps (trenches) between fins222) and etching back the insulator material layer to form isolation features420. In some implementations, STI features include a multi-layer structure that fills the trenches. For example, STI features include a silicon nitride layer disposed over a thermal oxide liner layer. In another example, STI features include a dielectric layer disposed over a doped liner layer (such as a boron silicate glass (BSG) liner layer or a phosphosilicate glass (PSG) liner layer). In yet another example, STI features include a bulk dielectric layer disposed over a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements. Further, in such implementations, before forming doped amorphous layer230, gate structure410can be formed over fin structure220. Gate structure410wraps channel regions402of fins222, thereby engaging fins222and interposing source regions404and drain regions406. In the depicted embodiment, gate structure410engages the top portion and the sidewall portions of channel regions402, such that gate structure410engages three sides of channel regions402. Gate structure410includes a dummy gate stack, portions of which can be replaced with a metal gate during a gate replacement process as described in detail below. In the depicted embodiment, the dummy gate stack includes a gate dielectric430and a gate electrode432. Gate dielectric430is disposed between gate electrode432and fins222, where gate dielectric430and gate electrode432are configured to wrap fins222(in particular, channel regions402). Gate dielectric430includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. Gate electrode432includes a suitable dummy gate material, such as polysilicon. The dummy gate stack can include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some implementations, the dummy gate stack further includes an interfacial layer, such as a silicon oxide layer, disposed between gate dielectric430and gate electrode432. In some implementations, a capping layer, such as a TiN capping layer, can be disposed between gate dielectric430and gate electrode432. Gate structure410is formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. For example, a deposition process can be performed to form a gate dielectric layer over substrate210, particularly over fin structures220and isolation features420, and a deposition process can be performed to form a gate electrode layer over the gate dielectric layer. In some implementations, a deposition process is performed to form an interfacial layer over substrate210before forming the gate dielectric layer. The deposition processes include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. A lithography patterning and etching process can then performed to pattern the gate dielectric layer and the gate electrode layer (and, in some implementations, the interfacial layer) to form gate dielectric430and gate electrode432. The lithography patterning processes include resist coating (for example, spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the resist, rinsing, drying (for example, hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposure process is assisted, implemented, or replaced by other methods, such as maskless lithography, electron-beam writing, or ion-beam writing. In yet another alternative, the lithography patterning process implements nanoimprint technology. The etching processes include dry etching processes, wet etching processes, other etching processes, or combinations thereof. After forming gate structure410, lightly doped source and drain (LDD) features450are formed in source region404and drain region406of FinFET device400. LDD features450are similar to doped feature250of FinFET device200, which is described in detail above with reference toFIGS.2A-2E. For example, a doped amorphous layer is formed over source region404and drain region406of fins222, and a knock-on implantation process is performed on the doped amorphous layer to drive dopant from the doped amorphous layer into source region404and drain region406. The knock-on implantation process also converts the doped amorphous layer into a portion of fins222, such that LDD features450include a doped portion of fins222and converted (re-crystallized) doped amorphous layer. In some implementations (such as the depicted embodiment), a fin trimming process, such as described above, is performed before forming isolation feature420and/or gate structure410. Alternatively, in some implementations, the fin trimming process is performed after forming the isolation feature420and/or gate structure410, such that the a width of a top portion of fins222(such as a portion of fins222extending above isolation feature420) is less than a width of a bottom portion of fins222. Thereafter, FinFET device400can undergo subsequent fabrication, as described below. FIG.5is a perspective, three-dimensional view of FinFET device500(for example, in an x-y-z plane) after undergoing processing as described with reference toFIGS.3A-3Eto form lightly doped source and drain regions according to various aspects of the present disclosure. FinFET device500may be included in a microprocessor, a memory, and/or other integrated circuit device. In some implementations, FinFET device500may be a portion of IC chip, an SoC, or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, MOSFETs, CMOSs, BJTs, LDMOSs, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. FinFET device500is similar in many respects to FinFET device300and FinFET device400. Accordingly, similar features inFIGS.3A-3E,FIG.4, andFIG.5are identified by the same reference numerals for clarity and simplicity.FIG.5has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in FinFET device500, and some of the features described below can be replaced, modified, or eliminated in other embodiments of FinFET device500. Similar to FinFET device300, FinFET device500includes substrate210and fin structure220, which includes fins222extending from substrate210. InFIG.5, fins222extend from substrate210in a z-direction, such that fins222have heights defined in the z-direction (such as height h), lengths defined in an x-direction, and widths and/or spacings defined in a y-direction (such as width w1, width w4, spacing S1, and spacing S4). Each fin222has a channel region502, a source region504, and a drain region506defined along the length of respective fins222(here, along the x-direction), where channel region502is disposed between source region504and drain region506(generally referred to as source/drain regions). Each channel region502includes a top portion defined between sidewall portions of a respective fin222, where the top portion and the sidewall portions engage with gate structure410(described in detail above), such that current can flow between a respective source region504and a respective drain region506during operation of FinFET device500. InFIG.5, gate structure410blocks view of channel regions502of fins222. Fabricating FinFET device500is similar to fabrication of FinFET device300described with reference toFIGS.3A-3E. However, before forming doped amorphous layer230, similar to FinFET device400, isolation feature(s)420is formed over and/or in substrate210to isolate various regions of FinFET device500, as described above. Similar to FinFET device400, before forming doped amorphous layer230, gate structure410is also formed over fin structure220, as described above. After forming gate structure410, LDD features550are formed in source region504and drain region506of FinFET device500. LDD features550are similar to doped feature350of FinFET device300, which is described in detail above with reference toFIGS.3A-3E. For example, a doped amorphous layer is formed over source region504and drain region506of fins222, and a knock-on implantation process is performed on the doped amorphous layer to drive dopant from the doped amorphous layer into a portion of source region504and drain region506. The knock-on implantation process also converts a portion of the doped amorphous layer into a portion of fins222, such that LDD features550include a doped portion of fins222and a converted (re-crystallized) portion of the doped amorphous layer. Thereafter, any remaining doped amorphous layer is removed, for example, by an oxidation removal process. Thereafter, FinFET device500can undergo further processing. FinFET device400and/or FinFET device500can undergo further processing. For example, spacers can be formed adjacent to gate structure410(here, gate dielectric430and gate electrode432). The spacers include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable material, or combinations thereof. In some implementations, the spacers include a multi-layer structure, such as a silicon nitride layer and a silicon oxide layer. The spacers are formed by any suitable process. In some implementations, spacers include more than one set of spacers, such as seal spacers, offset spacers, dummy spacers and/or main spacers formed adjacent to the dummy gate stack. In such implementations, the various sets of spacers can include materials having different etching rates. For example, a silicon oxide layer can be deposited over fin structure220and subsequently anisotropically etched (for example, dry etched) to form a first spacer set adjacent to the dummy gate stack, and a silicon nitride layer can be deposited over fin structure220and subsequently etched (for example, dry etched) to form a second spacer set adjacent to the first spacers set. A gate replacement process can then performed to replace the dummy gate stack of gate structure410with a gate, such as a metal gate stack. For example, an inter-level dielectric (ILD) layer can be formed over substrate210, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof). The ILD layer includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, PSG, borophosphosilicate glass (BPSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Michigan), polyimide, other proper materials, or combinations thereof. In some implementations, the ILD layer can include a multilayer structure having multiple dielectric materials. Subsequent to the deposition of the ILD layer, a CMP process may be performed, such that a top portion of gate structure410is reached (exposed), such as a top portion of gate electrode432. A portion of gate structure410(such as gate electrode432, and in some implementations, gate dielectric430) is then removed, thereby forming a trench (opening), which may expose an interfacial layer and/or gate dielectric (such as gate dielectric430). In some implementations, an etching process selectively removes the dummy gate electrode (and, in some implementations, a dummy gate dielectric). The etching process is a dry etching process, a wet etching process, or combinations thereof. A selective etching process can be tuned, such that the dummy gate electrode layer has an adequate etch rate relative to the interfacial layer, the spacers, and/or the ILD layer. A metal gate stack of gate structure410is then formed in the opening (trench). The metal gate stack includes a gate dielectric and a gate electrode (for example, a work function layer and a metal fill layer). The metal gate stack of gate structure410may include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some implementations, a gate dielectric layer is formed over the interfacial layer, and a gate electrode layer (such as a work function fill layer and a metal fill layer) is formed over the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HMO, HfSiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. In some implementations, the gate dielectric layer is a high-k dielectric layer. In some implementations, where an interfacial layer is omitted from the dummy gate stack, the gate dielectric layer can include an interfacial layer (such as a silicon oxide layer), and a high-k dielectric layer disposed over the interfacial layer. The gate electrode includes a conductive material, such as polysilicon, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive material, or combinations thereof. In some implementations, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and the metal fill layer is a conductive layer formed over the work function layer. In some implementations, the work function layer includes n-type work function materials, such as Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. In some implementations, the work function layer includes a p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The metal fill layer includes a suitable conductive material, such as aluminum, tungsten, or copper. The metal fill layer may additionally or collectively include polysilicon, titanium, tantulum, metal alloys, other suitable materials, or combinations thereof. The gate dielectric layer, the work function layer, and the metal fill layer are formed by various deposition processes, such as ALD, CVD, PVD, and/or other suitable process. In some implementations, the work function layer and the metal fill layer may conform to exposed surfaces in the opening. CMP process can be performed to remove excess material (such as any excess work function layer and/or any excess metal fill layer), planarizing gate structure410. In some implementations, additional source/drain features, such as heavily doped source and drain (HDD) features are formed in fins222. In some implementations, epitaxial source features and epitaxial drain features (referred to as epitaxial source/drain features) are formed over LDD features450and/or LDD features550. For example, forming LDD features450and/or LDD features550, a SEG process is performed to grow a semiconductor material on exposed portions of fins222, thereby forming epitaxial source/drain features over source region404(and/or source region504) and drain region406(and/or drain region506). In some implementations, the epitaxial source/drain features wrap source region404(and/or source region504) and drain region406(and/or drain region506). The SEG process can implement CVD deposition techniques (for example, VPE, UHV-CVD, LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The SEG process can use gaseous precursors (for example, Si-containing gases, such as SiH4and/or Ge-containing gases, such as GeH4) and/or liquid precursors, which interact with a composition of fins222. Dopants may be introduced into the SEG process, such that the epitaxial source/drain features are in situ doped during the SEG process. For example, the epitaxial source/drain features are doped during deposition by adding dopants to a source material of the SEG process. In some implementations, where FinFET device400and/or FinFET device500is configured as an n-type device (for example, having an n-channel), the epitaxial source/drain features include silicon or silicon carbon, where the silicon or silicon carbon is doped with phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, forming Si:P epitaxial layers or Si:C:P epitaxial layers). In some implementations, where FinFET device400and/or FinFET device500is configured as a p-type device (for example, having a p-channel), the epitaxial source/drain features include silicon germanium (SiGe), where the SiGe layers are doped with boron, other p-type dopant, or combinations thereof (for example, forming a Si:Ge:B epitaxial layer). In some implementations, the epitaxial source/drain features include materials and/or dopants that achieve desired tensile stress and/or compressive stress in channel region402and/or channel region502depending on design requirements. Various contacts can be formed to facilitate operation of FinFET device400and/or FinFET device500. For example, an ILD layer can be formed over substrate210(in some implementations, a second ILD layer formed over a first ILD layer (formed during the gate replacement process). Contacts can then be formed in the ILD layer(s). For example, a contact is electrically coupled with gate structure410(particularly, the gate electrode), a contact is electrically coupled to source region404, and a contact is electrically coupled to drain region406. Contacts include a conductive material, such as metal. Metals include aluminum, aluminum alloy (such as aluminum/silicon/copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some implementations, the ILD layer(s) and contacts (for example, extending through the ILD layer(s)) are a portion of a multilayer interconnect (MLI) feature disposed over substrate210. The MLI feature electrically couples various components of FinFET device400and/or FinFET device500, such that the various components are operable to function as specified by design requirements of FinFET device400and/or FinFET device500. The MLI feature can include a combination of metal layers and ILD layers configured to form vertical interconnect features, such as contacts and/or vias, and/or horizontal interconnect features, such as lines. The various conductive features include materials similar to the contacts. In some implementations, a damascene process and/or dual damascene process is used to form a copper-based multilayer interconnection structure. The present disclosure provides for many different embodiments. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material of the fin structure. In some implementations, the fin structure includes a crystalline material, and the knock-on implantation process converts at least a portion of the doped amorphous layer into the crystalline material (for example, by crystallizing the portion of the doped amorphous layer), such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the fin structure includes silicon and the doped amorphous layer includes amorphous silicon, such that the knock-on implantation process crystallizes at least a portion of the amorphous silicon. In some implementations, the method further includes performing a fin trimming process to reduce a dimension of the fin structure before forming the doped amorphous layer. In some implementations, a thickness of the doped amorphous layer is about equal to a thickness of the fin structure removed during the fin trimming process, and the knock-on implantation process causes the doped amorphous layer to become a part of the fin structure. In some implementations, the knock-on implantation process causes a portion of the doped amorphous layer to become a part of the fin structure. In such implementations, the method further includes oxidizing a remaining portion of the doped amorphous layer and removing the oxidized portion of the doped amorphous layer. In some implementations, the doped amorphous layer is formed on a source region and a drain region of the fin structure, and the doped feature is a lightly doped source and drain (LDD) region disposed in the source region and the drain region of the fin structure. In some implementations, the method further includes forming a gate structure over a channel region of the fin structure before forming the doped amorphous layer. In some implementations, the knock-on implantation process uses argon ions to drive the dopant from the doped amorphous layer into the portion of the fin structure. Another exemplary method includes forming a fin structure, forming a doped amorphous silicon layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous silicon layer into the portion of the fin structure, thereby forming a doped feature. In some implementations, the doped amorphous silicon layer wraps a source region and a drain region of the fin structure, and the doped feature is a lightly doped source and drain (LDD) region disposed in the source region and the drain region. In some implementations, forming the doped amorphous silicon layer includes epitaxially growing a semiconductor material over the portion of the fin structure, wherein the semiconductor material is in situ doped during the epitaxially growing. In some implementations, the method further includes reducing a width of the fin structure before forming the doped amorphous silicon layer. In such implementations, a thickness of the doped amorphous layer is about equal to an amount of the fin structure removed when reducing the width of the fin structure, and the knock-on implantation process causes the doped amorphous silicon layer to become a part of the fin structure. In some implementations, the knock-on implantation process causes a portion of the doped amorphous silicon layer to become a part of the fin structure. In such implementations, the method further includes oxidizing a remaining portion of the doped amorphous silicon layer, and removing the oxidized portion of the doped amorphous silicon layer. Yet another exemplary method includes forming a fin structure. The fin structure includes a channel region defined between a source region and a drain region. The fin structure further includes a material having a crystalline structure. The method further includes forming a gate structure over the channel region of the fin structure. The method further includes forming a doped layer over the source region and the drain region of the fin structure. The doped layer includes the material having a non-crystalline structure. The method further includes performing a knock-on implantation process to drive a dopant from the doped layer into the source region and the drain region of the fin structure, wherein the knock-on implantation process converts a portion of the doped layer into the material having the crystalline structure. In some implementations, the knock-on implantation process forms a lightly doped source and drain (LDD) region, wherein a doped portion of the fin structure and at least a portion of the doped layer form the LDD region. In some implementations, the method further includes performing a fin trimming process to reduce a dimension of the source region and the drain region of the fin structure before forming the doped layer, wherein all of the doped layer becomes a part of the LDD region. In some implementations, the method further includes removing any remaining portion of the doped layer. In some implementations, the fin structure includes silicon and the doped layer includes amorphous silicon, such that the knock-on implantation process crystallizes at least a portion of the amorphous silicon. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 73,524 |
11862714 | DETAILED DESCRIPTION It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” In addition, the term “being made of” may mean either “comprising” or “consisting of.” In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. In the entire disclosure, a source and a drain are interchangeably used, and a source/drain refers to one of or both of the source and the drain. FIGS.1-21show various stages for a sequential manufacturing process of a Fin FET device according to embodiments of the present disclosure. It is understood that in the sequential manufacturing process, one or more additional operations can be provided before, during, and after the stages shown inFIGS.1-21, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIG.1shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. As shown inFIG.1, a first semiconductor layer11is epitaxially formed over a substrate10. The substrate10can be a semiconductor substrate formed of, for example, one of Si, Ge, SiGe, SiC, SiP, SiPC, InP, InAs, GaAs, AlInAs, InGaP, InGaAs, GaAsSb, GaPN, AlPN, and any other suitable material. In certain embodiments, a crystalline Si substrate is used as the substrate10. The first epitaxial semiconductor layer11is the same semiconductor as the substrate10in some embodiments. In certain embodiments, the substrate10and the first epitaxial semiconductor layer11are both Si. In other embodiments, the first epitaxial semiconductor layer11is made of Si1-xGex, where 0<x<0.2, and the substrate10is Si. In some embodiments, a thickness D1of the first epitaxial semiconductor layer11is in a range from about 20 nm to about 200 nm, and is in a range from 50 nm to about 100 nm in other embodiments. The first epitaxial semiconductor layer11can be formed by an epitaxial growth method using chemical vapor deposition (CVD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE). In some embodiments, the first epitaxial semiconductor layer is appropriately doped with impurities, such as P, As, In and/or B. In some embodiments, no first epitaxial layer11is formed over the substrate10. FIG.2shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the first epitaxial11is formed, a part of the first epitaxial semiconductor layer11is recessed by one of more lithography and etching operations. In some embodiments, the depth D2of the recess13is in a range from about 10 nm to about 200 nm, and is in a range from 30 nm to about 120 nm in other embodiments. In some embodiments, the depth D2of the recess13is smaller than the thickness of the first epitaxial semiconductor layer11and thus the recess13does not reach the semiconductor substrate10. In other embodiments, the recess13penetrates into the semiconductor substrate10, and thus the depth D2of the recess13is greater than the thickness of the first epitaxial semiconductor layer11. In certain embodiments, the recess etching stops at the surface of the semiconductor substrate10. When no first epitaxial semiconductor is formed, a part of the substrate10is patterned to form the recess13. FIG.3shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the recess13is formed, a second semiconductor layer15is epitaxially formed in the recess13. In some embodiments, the second epitaxial semiconductor15is made of Si1-yGey, where 0.15≤y≤0.85, and in other embodiments, 0.3≤y≤0.6. The second epitaxial semiconductor layer15can be formed by an epitaxial growth method using chemical vapor deposition (CVD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE). In some embodiments, a chemical mechanical polishing (CMP) operation is performed to remove excess portion of the second epitaxial semiconductor layer grown over the upper surface of the first epitaxial semiconductor layer11. In some embodiments, the second epitaxial semiconductor layer15is made of Ge, a Group-IV compound semiconductor (e.g., SiC, SiGeSn, SiSn and GeSn) or a Group III-V compound semiconductor (e.g., InP, InAs, GaAs, AlInAs, GaN, InGaN, AlGaN, InGaP, InGaAs and GaAsSb). In some embodiments, the first epitaxial layer11, the second epitaxial layer15and/or the substrate10are appropriately doped with impurities to form one or more wells. In some embodiments, an n-type well12is formed in and/or below the second epitaxial layer15(in the first epitaxial layer11and/or the substrate10) for a p-type FET, and a p-type well14is formed in and/or below the first epitaxial layer11(and in the substrate10) for an n-type FET, as shown inFIG.3. The wells can be formed before or after the second epitaxial layer15is formed. FIG.4shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. As shown inFIG.4, fin structures are formed. In some embodiments, a hard mask layer including one or more of a SiO2layer, a Si3N4layer, and a SiON layer is formed on the first epitaxial layer11and the second epitaxial layer15. Then, the hard mask layer is patterned into a mask pattern19by using one or more lithography and etching operations. Further, the first and second epitaxial layers are trench etched by using plasma etching with the mask pattern19as an etching mask. Etching gases include one or more CF4, SF6, CH2F2, HBr, Cl2, and/or O2at pressure from about 10 mTorr to about 200 mTorr, source power from about 300 W to about 1000 W, and bias power from about 500 W to about 2000 W, in some embodiments. In some embodiments, the fin structures may be patterned by other suitable methods. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins. In some embodiments, fin structures20including a bottom fin structure22and an upper fin structure24are formed over the n-type well12, and fin structures25are formed over the p-type well14. AlthoughFIG.4shows two fin structures for one or more p-type FETs over the n-type well12and two fin structures for one or more n-type FETs over the p-type well14, the numbers of the fin structures are not limited to two. The widths Wp of the fin structure20is in a range from about 5 nm to about 40 nm in some embodiments, and is in a range from about 10 nm to about 25 nm in other embodiments. The widths Wn of the fin structure25is in a range from about 5 nm to about 40 nm in some embodiments, and is in a range from about 10 nm to about 25 nm in other embodiments. In some embodiments, Wp=Wn. In other embodiments, Wp<Wn, which can improve controllability of drain-induced barrier lowering (DIBL). In other embodiments, Wp>Wn, which can enhance carrier mobility in the p-type FET. FIG.5shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the fin structures20and25are formed, a sacrificial layer30is formed over the fin structures so that the fin structures are fully embedded in the sacrificial layer30, as shown inFIG.5. In some embodiment, the sacrificial layer30includes one or more layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. An anneal operation may be performed after the formation of the sacrificial layer30. In some embodiments, the sacrificial layer is amorphous silicon. FIG.6shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. An etch-back operation is performed to reduce the height of the sacrificial layer30, as shown inFIG.6. In some embodiments, the reduced height of the sacrificial layer30is equal to the level of the interface between the bottom fin structure22and the upper fin structure24. In other embodiments, the reduced height of the sacrificial layer30is lower or higher than the level of the interface between the bottom fin structure22and the upper fin structure24. FIG.7shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. A cover layer35is conformally formed over the exposed fin structures20and25. The cover layer35is made of a different material than the sacrificial layer, and includes silicon nitride or SiON in some embodiments. In some embodiments, anisotropic etching is performed to remove the cover layer formed on the upper surface of the sacrificial layer30, as shown inFIG.7. FIG.8shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the cover layer35is formed, the sacrificial layer30is removed. As shown inFIG.8, the exposed portion of the fin structure25is a bottom fin structure27and a portion covered by the cover layer35of the fin structure25is an upper fin structure29. FIG.9shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the sacrificial layer30is removed, the bottom fin structures22and27are trimmed by a suitable etching operation. In some embodiments, one or more dry etching operations are performed to reduce the width of the bottom fin structures22and27. In other embodiments, a wet etching operation using HF and O3water is performed. As shown inFIG.9, the etching is performed such that the bottom fin structures22and27have a tapered shape having a smallest width at the top. In some embodiments, the dry etching includes repeating an etching phase and a deposition phase, to obtain the tapered shape. FIG.10shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. As shown inFIG.10, the cover layer35is removed, thereby exposing the entire fin structures. In some embodiments, the bottom fin structure22has the smallest width Wpneck at the interface between the bottom fin structure22and the upper fin structure24(“neck portion”). In some embodiments, the width Wpneck of the neck portion is about 50% of Wp to about 95% of Wp. Similarly, the bottom fin structure27has the smallest width Wnneck at the level same as the interface between the bottom fin structure22and the upper fin structure24(“neck portion”). In some embodiments, the width Wnneck of the neck portion is about 50% of Wn to about 95% of Wn. In some embodiments, the hard mask patterns19are removed at this stage of the manufacturing operation. FIG.11shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the cover layer35is removed, corners of the upper fin structures24and29are trimmed to reduce a width of the upper fin structures near the interface between the upper fin structures and the bottom fin structures, as shown inFIG.11. In some embodiments, a wet etching operation is performed. In some embodiments, an aqueous solution containing ammonia and hydrogen peroxide and/or an aqueous solution containing hydrochloric acid and hydrogen peroxide is used as the wet etchant. Since the corners having a sharp angle (e.g., 90 degrees) are more likely be etched than flat portion, the end corners are rounded or beveled. After the end corners of the upper part are trimmed, the end corners are rounded in some embodiments. In other embodiments, the end corners are beveled. A dimension Ht1of the trimmed portion24B of the upper fin structure24is in a range from about 2 nm to about 10 nm in some embodiments. A dimension Ht2of the trimmed portion29B of the upper fin structure29is in a range from about 2 nm to about 10 nm in some embodiments. After the trimming operation, the fin structures20and25have the neck portion at or near the interface between the bottom fin structure and the upper fin structure, and the neck portion has the smallest width except for the top of the fin structures. In some embodiments, the neck portion is located below the center of the fin structure along the vertical direction. In some embodiments, the height Hfinof the upper fin structures24and29is in a range from about 20 nm to about 100 nm in some embodiments, and is in a range from about 30 nm to about 70 nm in other embodiments. In some embodiments, the height Hbotof the bottom fin structures22and27is in a range from about 10 nm to about 80 nm in some embodiments, and is in a range from about 20 nm to about 50 nm in other embodiments. In some embodiments, the height Hbotis smaller than the height Hfin, and in other embodiments, the height Hbotis equal to or greater than the height Hfin, In some embodiments, the dimension Ht1of the trimmed portion24B or Ht2of the trimmed portion29B is about 5% to about 30% of the height Hfinof the upper fin structures24and29, and in other embodiments, is about 10% to about 20%. FIG.12shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. After the trimming operation, one or more fin liner layers40are formed, and an isolation insulating layer45is formed over the fin liner layer40. In some embodiments, the fin liner layer40includes a first liner layer formed over the structures and a second liner layer formed over the first liner layer. The first liner layer is made of silicon oxide or a silicon oxide-based material and the second liner layer is made of SiN or a silicon nitride-based material. In some embodiments, the second liner layer is made of silicon oxide or a silicon oxide-based material and the first liner layer is made of SiN or a silicon nitride-based material. In some embodiments, only one of the first and second liner layers is formed. The isolation insulating layer45(for shallow trench isolation, STI) includes one or more layers of insulating material. As show inFIG.12, the isolation insulating layer45is formed so that the fin structures are fully embedded in the insulating layer. The insulating material for the insulating layer45may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. An anneal operation may be performed after the formation of the insulating layer45. FIG.13shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. As shown inFIG.13, the insulating layer45is recessed to partially expose an upper fin structures24and29covered by the fin liner layer40. In some embodiments, the reduced height of the isolation insulating layer45is equal to the neck portion (the level of the interface between the bottom fin structure and the upper fin structure). FIG.14shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to an embodiment of the present disclosure. As shown inFIG.14, the fin liner layer40is removed to expose the upper fin structures24and29. FIG.15shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure. In some embodiments, the reduced height of the isolation insulating layer45is lower than the neck portion, as shown inFIG.15. In other words, the upper surface of the isolation insulating layer45is located below the neck portion, thereby exposing the neck portion. In some embodiments, the distance Hsti between the neck portion and the upper surface of the isolation insulating layer45is in a range from about 0% of the height Hfinof the upper fin structure to about 20% of the height Hfin. FIGS.16A and16Bshow a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure. After the upper fin structures are exposed, sacrificial gate structures50are formed over the exposed upper fin structures, as shown inFIGS.16A and16B. The sacrificial gate structures50include a sacrificial gate dielectric layer52and a sacrificial gate electrode layer54. The sacrificial gate structures50are formed by first blanket depositing a sacrificial gate dielectric layer52over the fin structures. The sacrificial gate dielectric layer52includes one or more layers of silicon oxide, silicon nitride or silicon oxynitride. The thickness of the sacrificial gate dielectric layer52is in a range from about 1 nm to about 5 nm in some embodiments. A sacrificial gate electrode layer54is then blanket deposited on the sacrificial gate dielectric layer52and over the fin structures, such that the fin structures are fully embedded in the sacrificial gate electrode layer54. The sacrificial gate electrode layer54includes silicon such as poly crystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer54is in a range from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer54is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, a mask layer is formed over the sacrificial gate electrode layer54. The mask layer includes a pad SiN layer and a silicon oxide mask layer in some embodiments. A patterning operation is performed on the mask layer, and the sacrificial gate electrode layer54is patterned into the sacrificial gate structures50. In an embodiment shown inFIGS.16A and16B, one sacrificial gate structure is formed over the two fin structures for a p-type FET, and one sacrificial gate structure is formed over the two fin structures for an n-type FET. However, the configuration of the sacrificial gate structures50is not limited to that ofFIGS.16A and16B. The width of the sacrificial gate electrode layer54is in a range from about 5 nm to about 40 nm in some embodiments. Further, after the sacrificial gate structures50are formed, a blanket layer of an insulating material for sidewall spacers56is conformally formed by using CVD or other suitable methods. The blanket layer is deposited in a conformal manner so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structure. In some embodiments, the blanket layer is deposited to a thickness in a range from about 2 nm to about 10 nm. In one embodiment, the insulating material of the blanket layer is a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof. Then, as shown inFIGS.16A and16B, side wall spacers56are formed on opposite sidewalls of the sacrificial gate structures50. After the blanket layer is formed, anisotropic etching is performed on the blanket layer using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from horizontal surfaces, leaving the dielectric spacer layer on the vertical surfaces such as the sidewalls of the sacrificial gate structures and the sidewalls of the exposed fin structures. In some embodiments, isotropic etching is subsequently performed to remove the insulating material from the sidewalls of the exposed fin structures. FIG.17shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure.FIG.18shows a partial enlarged cross sectional view ofFIG.17.FIG.19shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure. After the sacrificial gate structures50are formed, a source/drain epitaxial layer60for a p-type FET and a source/drain epitaxial layer65for an n-type FET are formed over the source/drain regions of the upper fin structures24and29, respectively. In some embodiments, the source/drain epitaxial layer60includes one or more layers of SiGe, Ge and GeSn. In some embodiments, the source/drain epitaxial layer60is doped with boron. In some embodiments, the source/drain epitaxial layer65includes one or more layers of SiP, SiC and SiCP. In some embodiments, the source/drain epitaxial layer60is doped with phosphorous and/or arsenic. The source/drain epitaxial layers are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). In some embodiments, the source/drain epitaxial layers60and65are a merged structure shared by two adjacent upper fin structures. As shown inFIG.18, the bottom of the epitaxial layers60and65is located at about ±10 nm from the neck portion in the vertical direction (Hsd=±10 nm) in some embodiments. In some embodiments, the epitaxial growth of the epitaxial layer60(65) starts at the bottom fin structure22(27) and the epitaxial layer60(65) covers the neck portion (Hsd>0 nm). In other embodiments, the epitaxial growth of the epitaxial layer60(65) starts at the bottom of the upper fin structure24(29) and the neck portion is exposed from the epitaxial layer60(65) (Hsd<0 nm). In certain embodiments, the epitaxial growth of the epitaxial layer60(65) starts at the neck portion (Hsd=0 nm). In other embodiments, as shown inFIG.19, the source/drain epitaxial layers60′ and65′ are individually formed for each upper fin structure. In some embodiment, an n-type FET has a merged epitaxial source/drain structure as shown inFIG.17, and a p-type FET has an individual epitaxial source/drain structure as shown inFIG.19. FIG.20shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure. After the source/drain epitaxial layers are formed, one or more dielectric material layers are formed for an interlayer dielectric (ILD) layer70. The materials for the ILD layer70may include compounds comprising Si,0, C and/or H, such as SiCOH and SiOC. Organic material, such as polymers, may be used for the ILD layer70. Further, in some embodiments, before forming the ILD layer70, a silicon nitride layer as an etching stop layer may be formed over the source/drain epitaxial layers. FIG.21shows a cross sectional view of one of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure. After the one or more layers of dielectric material layers for the ILD layer70are formed, a planarization operation, such as a CMP operation, is performed to expose the sacrificial gate electrode54. Further, the sacrificial gate structures50are replaced with metal gate structures80. The sacrificial gate electrodes54and the sacrificial gate dielectric layers52are removed, thereby exposing the upper fin structures24and29, which subsequently become channel regions. When the sacrificial gate electrode54is polysilicon, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrodes54. The sacrificial gate dielectric layer52is thereafter removed using plasma dry etching and/or wet etching. The metal gate structures80includes a high-k gate dielectric layer82, one or more layers of work function adjustment material (not shown) and a body gate electrode layer84in some embodiments. In some embodiments, an interfacial layer including a silicon oxide layer is formed before the gate dielectric layer82is formed. In some embodiments, the gate dielectric layer82includes one or more layers of a dielectric material, such as, silicon nitride, HfO2, La2O3, ZrO2, BaO, TiO2, Ta2O5, SrO, Y2O3, HfSiO4, ZrSiO4, Al2O3, MgO, CaO, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer82may be formed from CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layers. The thickness of the gate dielectric layer82is in a range from about 1 nm to about 6 nm in one embodiment. In some embodiments, one or more work function adjustment layers are formed on the gate dielectric layer82. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the nFET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the pFET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the work function adjustment layer84may be formed separately for the nFET and the pFET which may use different metal layers. The body gate electrode layer84is formed to surround each channel region (nanowires). The body gate electrode layer84includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The body gate electrode layer84may be formed from CVD, ALD, electro-plating, or other suitable method. The body gate electrode layer84is also deposited over the upper surface of the ILD layer. The materials for the metal gate structures80over the ILD layer are then planarized by using, for example, CMP, until the top surface of the ILD layer is revealed. In some embodiments, source/drain contacts are formed on the source/drain epitaxial layers60and65, respectively. In some embodiments, one source/drain contact is provided on both the source/drain epitaxial layers60and65. In certain embodiments, a contact connecting the gate electrode and the source/drain epitaxial layer is formed. It is understood that the Fin FETs undergo further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc. FIG.22shows enlarged cross sectional views of channel regions covered by a gate dielectric layer according to an embodiment of the present disclosure. As shown inFIG.22, the metal gate structure, in particular the gate dielectric layer82covers the neck portion in the fin structures. In some embodiments, the largest width W1of the upper fin structure24, the width W2of the neck portion (the minimum width) and a width W3of the bottom fin structure22at the level of the upper surface of the isolation insulating layer45satisfy W2<(W1+W3)/2. Similarly, in some embodiments, the largest width W4of the upper fin structure29, the width W5of the neck portion (the minimum width) and a width W6of the bottom fin structure27at the level of the upper surface of the isolation insulating layer45satisfy W5<(W4+W6)/2. In some embodiments, W2≥0.5W1, and W5≥0.5W4. FIGS.23and24show cross sectional views of the various stages of a sequential manufacturing operation of a fin field-effect transistor (FinFET) according to another embodiment of the present disclosure. Materials, dimensions, configurations, processes, and/or operations as explained with the foregoing embodiments may be employed in the following embodiments, and detailed explanation thereof may be omitted. In some embodiments, after patterning the fin structures20and25, the fin structures20and25have a tapered shape, as shown inFIG.23. After the trimming of the corners of the upper fin structures24and29, the fin structures show the shapes shown inFIG.24. In some embodiments, the largest width W11of the upper fin structure24, the width W12of the neck portion (the minimum width) and a width W13of the bottom fin structure22at the level of the upper surface of the isolation insulating layer45satisfy W12<(W11+W13)/2. Similarly, in some embodiments, the largest width W14of the upper fin structure29, the width W15of the neck portion (the minimum width) and a width W16of the bottom fin structure27at the level of the upper surface of the isolation insulating layer45satisfy W15<(W14+W16)/2. In some embodiments, W12≥0.5W11, and W15≥0.5W14. The various embodiments or examples described herein offer several advantages over the existing art. For example, in the present disclosure, since the channel region has a neck portion having the smallest width (below the portion having the largest width), it is possible to effectively suppress off-leak current, without sacrificing transistor performance. Further, it is possible to improve controllability of drain-induced barrier lowering (DIBL). It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages. In accordance with one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure. In one or more of the foregoing or the following embodiments, the upper part of the fin structure is made of a different semiconductor material than the bottom part of the fin structure. In one or more of the foregoing or the following embodiments, the upper part of the fin structure is made of SiGe and the bottom part of the fin structure is made of Si. In one or more of the foregoing or the following embodiments, after the bottom end corners of the upper part are trimmed, the bottom end corners are rounded or beveled. In one or more of the foregoing or the following embodiments, a portion having a minimum width of the fin structure, which is located below a portion having a largest width, is covered by the dummy gate structure. In one or more of the foregoing or the following embodiments, in the trimming the bottom end corners of the upper part, top end corners of the upper part are also trimmed. In one or more of the foregoing or the following embodiments, the trimming the bottom part is performed such that the bottom part has a tapered shape having a smallest width at a top. In one or more of the foregoing or the following embodiments, the isolation insulating layer is formed such that an upper surface of the isolation insulating layer is located below the interface between the bottom part and the upper part of the fin structure, and a height of the upper surface of the isolation insulating layer measured from the interface is from 0% to 20% of a vertical length of the upper part of the fin structure. In one or more of the foregoing or the following embodiments, before forming the isolation insulating layer, a fin liner layer is formed over the bottom part of the fin structure. In one or more of the foregoing or the following embodiments, the fin liner layer covers a bottom portion of the upper part of the fin structure after the inter layer dielectric layer is formed. In one or more of the foregoing or the following embodiments, the trimming the bottom part is performed while the upper part is covered by a mask layer. In one or more of the foregoing or the following embodiments, to form the mask layer, a sacrificial layer is formed over the fin structure, a height of the sacrificial layer is reduced so that the upper part of the fin structure is exposed, a layer for the mask layer is formed over the exposed upper part, and the sacrificial layer is removed so that the bottom part of the fin structure is exposed. In one or more of the foregoing or the following embodiments, the fin structure has a trapezoid shape having a largest width at a bottom. In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, an epitaxial semiconductor layer is formed over a semiconductor substrate. A fin structure is formed by patterning the epitaxial semiconductor layer and the semiconductor substrate, so that the fin structure has a bottom part corresponding to the semiconductor substrate and an upper part corresponding to the epitaxial semiconductor layer. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of bottoms of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure. In one or more of the foregoing or the following embodiments, the epitaxial semiconductor layer is made of a different semiconductor material than the semiconductor substrate. In one or more of the foregoing or the following embodiments, the epitaxial semiconductor layer is made of SiGe and the semiconductor substrate is made of Si. In one or more of the foregoing or the following embodiments, a portion having a minimum width of the fin structure, which is located below a portion having a largest width, is covered by the metal gate structure. In one or more of the foregoing or the following embodiments, the trimming the bottom part is performed such that the bottom part has a trapezoid shape having a smallest width at a top. In one or more of the foregoing or the following embodiments, a width W2of the bottom part at the interface after the trimming the bottom part is 50% to 95% of a width W1of the upper part at the interface before the trimming the bottom part. In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, an epitaxial semiconductor layer is formed over a recessed part of a semiconductor substrate. A first fin structure is formed by patterning the epitaxial semiconductor layer and the semiconductor substrate and a second fin structure by patterning the semiconductor substrate, so that the first fin structure has a bottom part corresponding to the semiconductor substrate and an upper part corresponding to the epitaxial semiconductor layer and the second fin structure has a bottom part and an upper part both corresponding to the semiconductor substrate. The bottom parts of first and second fin structures are trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part in each of the first and second fin structures. Bottom end corners of the upper part are trimmed to reduce a width of a bottom of the upper part for each of the first and second fin structures. An isolation insulating layer is formed so that the upper part of each of the first and second fin structures protrudes from the isolation insulating layer. A dummy gate structure is formed over the first and second fin structures. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure. In accordance with another aspect of the present disclosure, a semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure having a bottom part and an upper part disposed over the substrate, the upper part protruding the isolation insulating layer, a gate structure disposed over the upper part of the fin structure, and a source/drain structure. The bottom part has a tapered shape and a bottom portion of the upper part has a reverse tapered shape. A portion having a minimum width of the fin structures, which is located below a portion having a largest width, is covered by a gate dielectric layer. In one or more of the foregoing or the following embodiments, the upper part of the fin structure is made of a different semiconductor material than the bottom part of the fin structure. In one or more of the foregoing or the following embodiments, the upper part of the fin structure is made of SiGe and the bottom part of the fin structure is made of Si. In one or more of the foregoing or the following embodiments, bottom end corners of the upper part are rounded. In one or more of the foregoing or the following embodiments, bottom end corners of the upper part are beveled. In one or more of the foregoing or the following embodiments, an upper surface of the isolation insulating layer is located below the interface between the bottom part and the upper part of the fin structure, and a height of the upper surface of the isolation insulating layer measured from the interface is from 0% to 20% of a vertical length of the upper part of the fin structure. In one or more of the foregoing or the following embodiments, the vertical length of the upper part is in a range from 30 nm to 70 nm. In one or more of the foregoing or the following embodiments, a width of the bottom part at an interface between the bottom part and the upper part of the fin structure is 50% to 95% of an average width of the upper part. In one or more of the foregoing or the following embodiments, the source/drain structure includes a source/drain fin structure and a source/drain epitaxial layer. In one or more of the foregoing or the following embodiments, a bottom of the source/drain epitaxial layer is within ±10 nm of an interface between the bottom part and the upper part of the fin structure. In one or more of the foregoing or the following embodiments, top end corners of the upper part are rounded. In one or more of the foregoing or the following embodiments, top end corners of the upper part are beveled. In accordance with another aspect of the present disclosure, a semiconductor device includes an isolation insulating layer disposed over a substrate, a first fin structure and a second fin structure, each having a bottom part and an upper part disposed over the substrate, the upper part protruding the isolation insulating layer, a gate structure disposed over the upper part of each of the first and second fin structures, and a source/drain structure including a source/drain epitaxial layer. A largest width of the upper part of each of the first and second fin structures is located at a level above an interface between the upper part and the bottom part. A portion having a minimum width of each of the first and second fin structures, which is located below a portion having the largest width, is covered by a gate dielectric layer. In one or more of the foregoing or the following embodiments, the bottom part has a tapered shape and a bottom portion of the upper part has a reverse tapered shape. In one or more of the foregoing or the following embodiments, the upper part of the fin structure is made of a different semiconductor material than the bottom part of the fin structure. In one or more of the foregoing or the following embodiments, a height of an upper surface of the isolation insulating layer measured from an interface between the bottom part and the upper part of the fin structure is within 0% to 20% of a vertical length of the upper part of the fin structure. In one or more of the foregoing or the following embodiments, the vertical length of the upper part is in a range from 30 nm to 70 nm. In one or more of the foregoing or the following embodiments, the source/drain epitaxial layer is a merged structure covering the upper part of the first fin structure and the upper part of the second fin structure. In one or more of the foregoing or the following embodiments, a void is present between the isolation insulating layer and the source/drain epitaxial layer between the first and second fin structures. In accordance with another aspect of the present disclosure, a semiconductor device includes an isolation insulating layer disposed over a substrate, a first fin structure and a second fin structure, each having a bottom part and an upper part disposed over the substrate, the upper part protruding the isolation insulating layer, a gate structure disposed over the upper part of each of the first and second fin structures, and a source/drain structure including a source/drain epitaxial layer. The upper part of the first fin structure is made of a different semiconductor material than the bottom part of the first fin structure. The upper part of the second fin structure is made of a same semiconductor material as the bottom part of the second fin structure. A largest width of the upper part of each of the first and second fin structures is located at a level above an interface between the upper part and the bottom part. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 46,181 |
11862715 | DETAILED DESCRIPTION Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout. The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure. In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical. The term “horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as “on,” “above,” “below,” “bottom,” “top,” “side” (as in “sidewall”), “higher,” “lower,” “upper,” “over,” and “under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The terms “on,” “over,” “above,” “higher,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary elements at the interface between the two elements. The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation of a described structure. “An embodiment,” “various embodiments,” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and “coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment. The terms “perpendicular,” “orthogonal,” “coplanar,” and/or “parallel” may mean substantially perpendicular, orthogonal, coplanar, or parallel, respectively (e.g., perpendicular within +/−10 degrees). Further, the figures shown herein may not have precisely vertical or horizontal edges, but rather may have some finite slope and have surface roughness, as is to be expected for fabricated devices. Tunneling field effect transistors (TFETs) represent a class of transistors that can feature performance increases and energy consumption decreases due to a steeper subthreshold slope (for example, smaller sub-threshold swing) in comparison to MOSFETs. A TFET structure can be similar to a MOSFET structure, except that the source and drain terminals of a TFET can be doped of opposite type; that is, a source can be p-type, while the drain can be n-type (or vice-versa). For example, a TFET device structure can include a p-type, intrinsic, n-type (P-I-N or PIN) junction, in which the electrostatic potential of the intrinsic region can be controlled by a gate terminal. In various embodiments, a fin-based TFETs can refer to a transistor architecture that uses raised channels, referred to herein as fins, from source to drain. One characteristic of the fin-based TFET can be that the conducting channel can be wrapped by a thin fin, which can form the body of the fin-based TFET device. In one embodiment, the thickness of the fin (for example, measured in the direction from source to drain) can determine the effective channel length of the device. The wrap-around gate structure can provide electrical control over the channel and can reduce the leakage current other short-channel effects, such as drain-induced barrier lowering (DIBL). Such effects can make it less likely for the voltage on a gate electrode to deplete the channel underneath the gate electrode and thereby stop the flow of carriers through the channel, thereby turning the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it can be possible to wrap the gate around all but one of the gate's sides, providing greater electrostatic control over the carriers within the channel. Further, in one embodiment, nonplanar devices such as fin-based TFETs can be more compact than planar transistors, thereby enabling higher transistor density, which can translate to smaller overall sizes for microelectronic devices. In one embodiment, vertical fin-based TFETs (also referred to herein simply as vertical TFETs) can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches. For example, the vertical TFETs can be used on silicon (Si), germanium (Ge), III-V semiconductors, gallium nitride (GaN), and the like. In another embodiment, the vertical TFETs can be fabricated using an aspect ratio trapping (ART) approach. In one embodiment, ART can refer to can generally refer to the technique(s) of causing defects to terminate at non-crystalline, for example, dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects. In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the substrate (for example, silicon substrate) on which the TFET is fabricated. In one embodiment, this tunneling direction for vertical TFETs can be different, that is perpendicular or near perpendicular, to the tunneling direction in the channel of lateral TFETs. In one embodiment, a junction of the vertical TFET comprising a source (for example, a source comprising p-doped gallium antimonide), a channel (for example, a channel comprising unintentionally doped indium arsenide), and a drain (for example, a drain comprising an n-doped indium arsenide) be gated at a (110) sidewall of the channel. In one embodiment, the design and fabrication of a vertical TFET can reduce and/or simplify the fabrication steps needed, for example, as compared with the fabrication steps needed for a lateral TFET. For example, in one embodiment, there may not be a need for a dual p-source, n-drain regrowth process in the fabrication of the vertical TFET. In one embodiment, the tunneling junction, that is the channel of the vertical TFET may need to be regrown. Accordingly, the vertical tunneling junction may not be exposed to ambient (for example, air) during fabrication, leading to fewer defects, fewer trap-assisted tunneling, and/or fewer Schottky-Reed-Hall (SRH) leakage. In one embodiment, vertical TFETs can have better scalability in fabrication as compared with lateral TFETs. FIG.1shows a diagram an example transistor, for example, a TFET having lateral structure in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor100can include a substrate102. In one embodiment, the substrate102can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate102can include a silicon substrate. In one embodiment, the substrate102can include a p-doped silicon substrate. In one embodiment, the substrate102can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate102can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate102can include a flexible substrate. In various embodiments, substrate102can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and MoS2, organic materials, for example, pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, polycrystalline Ge, polycrystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, the substrate102can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, substrate102comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate102can be a monocrystalline Si substrate. In one embodiment, the substrate102, for example, a silicon wafer can include a periphery devices, for example, input/output devices. In an embodiment, placing the periphery devices under the substrate102can increase the device efficiency while reducing the device area consumption. In an embodiment, the substrate102can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate102can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, substrate102can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon. In one embodiment, the transistor100can include a buffer layer104. In one embodiment, the buffer layer104can include any material suitable to insulate adjacent devices and prevent current leakage. The buffer layer104can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer104can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer104can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer104may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer104can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer104can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer104can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In one embodiment, the transistor100can include a channel106. In another embodiment, the channel106can include an indium arsenide (InAs) material. In one embodiment, the channel106can include an amorphous oxide semiconductor. In another embodiment, the channel106can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel106may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel106can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel106can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel106can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel106can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. In one embodiment, the transistor100can include a source108. In another embodiment, the source108can include a p-doped gallium antimonide (p+ GaSb) layer. In another embodiment, the source108can include a nonreactive metal. In one embodiment, the source108can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source108can include an p-doped indium gallium arsenide layer. In one embodiment, the source108can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source108can be fabricated using MBE. In another embodiment, the source108can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source108can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating electron vacancies in the source108. In one embodiment, source can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source108can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source108can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source108can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source108comprises a non-oxide a single-material semiconductor. In another embodiment, the source108can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source108can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor100can include a drain110. In another embodiment, the drain110can include an n-doped indium arsenide (n+ InAs) layer. In another embodiment, the drain110can include a nonreactive metal. In one embodiment, the drain110can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain110can include an n-doped indium gallium arsenide layer. In one embodiment, the drain110can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain110can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain110can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain110. In another embodiment, the drain110can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain110comprises a non-oxide a single-material semiconductor. In another embodiment, the drain110can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain110can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor100can include a source contact112(also known as a contact electrode). In one embodiment, the source contact112can include a metal. In one embodiment, the source contact210can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The source contact112can include any alloys of such materials. In one embodiment, the source contact112can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact112can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor100can include a drain contact114. In one embodiment, the drain contact114can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The drain contact114can include any alloys of such materials. In one embodiment, the drain contract114can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the drain contract114can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor100can include a gate dielectric116. In one embodiment, the gate dielectric116can include a dielectric material. In another embodiment, the gate dielectric116can include silicon oxide. In another embodiment, the gate dielectric116can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric116. In one embodiment, the gate dielectric116can include hexagonal boron nitride (HBN). In one embodiment, the gate dielectric116can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric116can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. In one embodiment, the transistor100can include a gate118. In one embodiment, a gate118can be deposited on the gate dielectric116. In another embodiment, the gate118can include a metal. In another embodiment, the gate118can include a transition metal. In one embodiment, the gate118can be used to tune the threshold voltage of the device. In one embodiment, gate118can titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate118can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate118can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. In one embodiment, the transistor100can include spacers120and122. In an embodiment, the spacers120and122can serve to provide electrical insulation between the gate118and the source108and/or the drain110. In one embodiment, the spacers120and122can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source108and/or drain110from making electrical contact to the gate118. FIG.2Ashows a first view of a transistor200in accordance with one or more example embodiments of the disclosure. In particular, a second view, that is a cross-sectional view in the direction of 1-1′ of the transistor200as shown inFIG.2Acan be seen inFIG.2B. In one embodiment, the transistor200can include a substrate202. In another embodiment, the substrate202can include a silicon layer. In one embodiment, the substrate202can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate202can include a silicon substrate. In one embodiment, the substrate202can include a p-doped silicon substrate. In one embodiment, the substrate202can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate202can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof). In one embodiment, the transistor200can include a buffer layer204(also referred to herein as a buffer material). In another embodiment, the buffer layer204can include a III-V semiconductor. In one embodiment, the partial structure200of the TFET can include a buffer layer204. In one embodiment, the buffer layer204can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer204can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer204can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer204can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer204may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer204can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer204can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer204can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In an embodiment, the buffer layer204can be patterned and etched to form trenches, such as trench205, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench205can have a depth D of approximately 50 nm to about 300 nm and a width W of approximately 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench205(D/W) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the buffer layer204can be. In one embodiment, the transistor200can include a source206. In one embodiment, the source206can include a first portion and a second portion. In another embodiment, the source206can include a p-doped gallium antimonide layer. In another embodiment, the source206can include a nonreactive metal. In one embodiment, the source206can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source206can include an p-doped indium gallium arsenide layer. In one embodiment, the source206can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source206can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source206can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating electron vacancies in the source206. In one embodiment, source can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source206can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source206can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source206comprises a non-oxide a single-material semiconductor. In another embodiment, the source206can be approximately 1 nm to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source206can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor200can include a channel208. In one embodiment, the channel208is formed on the first portion of the source206. In one embodiment, the channel208includes a first portion and a second portion. In another embodiment, the channel208can include a unintentionally doped (UID) indium arsenide layer. In one embodiment, the channel208can include an amorphous oxide semiconductor. In another embodiment, the channel208can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel208may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel208can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel208can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel208can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel208can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the transistor200can include a gate dielectric216. In one embodiment, the gate dielectric216is formed on the second portion of the channel208. In one embodiment, the gate dielectric216can include a dielectric material. In another embodiment, the gate dielectric216can include silicon oxide. In another embodiment, the gate dielectric216can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric216. In one embodiment, the gate dielectric216can include hexagonal boron nitride (HBN). In one embodiment, the gate dielectric216can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric216can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. In another embodiment, the transistor200can include a gate218. In one embodiment, a gate218can be deposited on the gate dielectric216. In another embodiment, the gate218can include a metal. In another embodiment, the gate218can include a transition metal. In one embodiment, the gate218can be used to tune the threshold voltage of the device. In one embodiment, gate218can titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate218can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate218can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. In one embodiment, the transistor200can include a drain contact214. In one embodiment, the drain contact214is formed on the first portion of the channel208. In one embodiment, the drain contact214can include a metal. In one embodiment, the drain contact214can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The drain contact214can include any alloys of such materials. In one embodiment, the drain contract214can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the drain contract214can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In another embodiment, the transistor200can include spacers220and222. In an embodiment, the spacers220and222can serve to provide electrical insulation between the gate218and the source206and/or the drain212. In one embodiment, the spacers220and222can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source206and/or drain212from making electrical contact to the gate218. In one embodiment, the spacers220and222can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the spacers220and222. That is, the spacers220and222may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers220and222that might remain underneath the source206and/or drain212. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers220and222as well, giving rise to the triangular shape of the spacers220and222. FIG.2Bshows a diagram of a second view of a transistor201in accordance with one or more example embodiments of the disclosure. In particular, the second view of the transistor201comprises a cross-sectional view in the direction of 1-1′ of the transistor200as shown inFIG.2A. In one embodiment, the transistor201can include a substrate202. In one embodiment, the substrate202can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate202can include a silicon substrate. In one embodiment, the substrate202can include a p-doped silicon substrate. In one embodiment, the substrate202can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate202can include a semiconductor material, for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate202can include gallium antimonide (GaSb), silicon on insulator (SOI), germanium on insulator (GOI), or a III-V semiconductor material on silicon (III-V-OI). In one embodiment, the transistor201can include a shallow trench isolation layer (STI layer)203. The STI layer203can also be referred to as an isolation structure herein. In one embodiment, the shallow trench isolation layer203can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the shallow trench isolation layer203can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the shallow trench isolation layer203can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the shallow trench isolation layer203may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the shallow trench isolation layer203can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the shallow trench isolation layer203can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the shallow trench isolation layer203can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In one embodiment, the transistor201can include a buffer layer204. In one embodiment, the buffer layer204can include a III-V semiconductor material. Such III-V semiconductor material layers can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the partial structure200of the TFET can include a buffer layer204. In one embodiment, the buffer layer204can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer204can include a shallow trench isolation (STI) layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer204can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer204can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer204may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer204can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer204can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer204can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In an embodiment, the buffer layer204can be patterned and etched to form trenches, such as trench205, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench205can have a depth D of approximately 50 nm to approximately 300 nm and a width W of approximately 5 nm to approximately 20 nm. In one embodiment, an aspect ratio of the trench205(D/W) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the buffer layer204can be. In one embodiment, the transistor201can include a source206. In another embodiment, the source206can include a p-doped gallium antimonide layer. In another embodiment, the source206can include a nonreactive metal. In one embodiment, the source206can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source206can include a p-doped indium gallium arsenide layer. In one embodiment, the source206can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source206can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source206can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating electron vacancies in the source206. In one embodiment, source can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source206can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source206can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source206comprises a non-oxide a single-material semiconductor. In another embodiment, the source206can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source206can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor201can include a channel208. In another embodiment, the channel208can include a UID indium arsenide layer. In one embodiment, the channel208can include an amorphous oxide semiconductor. In another embodiment, the channel208can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel208may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel208can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel208can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel208can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel208can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. In one embodiment, the transistor201can include a source contact210. In one embodiment, the source contact210can include a metal. In one embodiment, the source contact210can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The source contact210can include any alloys of such materials. In one embodiment, the source contact210can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact210can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In an embodiment, the transistor can include a drain212. In another embodiment, the drain212can include an n-doped indium arsenide layer. In another embodiment, the drain212can include a nonreactive metal. In one embodiment, the drain212can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain212can include an n-doped indium gallium arsenide layer. In one embodiment, the drain212can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain212can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain212can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain212. In another embodiment, the drain212can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain212comprises a non-oxide a single-material semiconductor. In another embodiment, the drain212can be approximately 1 nm to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain212can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In another embodiment, the transistor201can include a gate dielectric216. In one embodiment, the gate dielectric216can include a dielectric material. In another embodiment, the gate dielectric216can include silicon oxide. In another embodiment, the gate dielectric216can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric216. In one embodiment, the gate dielectric216can include hexagonal boron nitride (HBN). In one embodiment, the gate dielectric216can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric216can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. In one embodiment, the transistor201can include a gate218. In one embodiment, a gate218can be deposited on the gate dielectric216. In another embodiment, the gate218can include a metal. In another embodiment, the gate218can include a transition metal. In one embodiment, the gate218can be used to tune the threshold voltage of the device. In one embodiment, gate218can titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate218can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. In one embodiment, the gate218can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. FIG.3Ashows a first view of a partial structure of the transistor300in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor300can include a substrate302. In one embodiment, the substrate302can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate302can include a silicon substrate. In one embodiment, the substrate302can include a p-doped silicon substrate. In one embodiment, the substrate302can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate302can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate302can include gallium antimonide (GaSb), silicon on insulator (SOI), germanium on insulator (GOI), or a III-V semiconductor material on silicon (III-V-OI). In one embodiment, the transistor300can include an STI layer303. In an embodiment, the STI layer303can also referred to as an isolation structure herein. In one embodiment, the STI layer303can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the STI layer303can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the STI layer303can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the STI layer303may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the STI layer303can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the STI layer303can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer204can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In one embodiment, the transistor300can include a buffer layer304(also referred to herein as a buffer material). In another embodiment, the buffer layer304can include a III-V semiconductor material layer. Such III-V semiconductor material layers can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the buffer layer304can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer304can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer304can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer304may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer304can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer304can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer304can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In an embodiment, the buffer layer304can be patterned and etched to form trenches, such as trench305, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench305can have a depth D of approximately 50 nm to about 300 nm and a width W of approximately 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench305(D/W) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the buffer layer304can be. In one embodiment, the transistor300can include a source306. In another embodiment, the source306can include a p-doped gallium antimonide (GaSb) layer. In one embodiment, the source306can further include a p-doped aluminum anitomodnide (AlSb) and/or an indium antimonide (InSb) layer. In another embodiment, the source306can include a nonreactive metal. In one embodiment, the source306can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source306can include an p-doped indium gallium arsenide layer. In one embodiment, the source306can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source306can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source306can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating electron vacancies in the source306. In one embodiment, source can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source306can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source306can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source306comprises a non-oxide a single-material semiconductor. In another embodiment, the source306can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source306can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor300can include a channel308. In another embodiment, the channel308can include an unintentionally doped (UID) indium arsenide (InAs) layer. In one embodiment, UID can refer to dopants that may be integrated into a layer, for example, during the fabrication of that layer, from the environment and/or processes that the layer is exposed to, often in an uncontrolled manner. In one embodiment, the channel308can include an amorphous oxide semiconductor. In another embodiment, the channel308can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel308may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel308can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel308can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on the technology used to fabricate the transistor. In another embodiment, the channel308can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel308can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. FIG.3Bshows a second view of a partial structure of a transistor301using the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, transistor301can include a substrate302. In one embodiment, the substrate302can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate302can include a silicon substrate. In one embodiment, the substrate302can include a p-doped silicon substrate. In one embodiment, the substrate302can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate302can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof). In one embodiment, the transistor301can include a buffer layer304. In another embodiment, the buffer layer304can include a III-V semiconductor material layer. Such III-V semiconductor material layers can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the buffer layer304can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer304can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer304can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer304may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer304can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer304can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer304can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In one embodiment, the transistor301can include a source306. In another embodiment, the source306can include a p-doped gallium antimonide (GaSb) layer. In one embodiment, the source306can further include a p-doped aluminum anitomodnide (AlSb) and/or an indium antimonide (InSb) layer. In another embodiment, the source306can include a nonreactive metal. In one embodiment, the source306can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source306can include an p-doped indium gallium arsenide layer. In one embodiment, the source306can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source306can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source206can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating electron vacancies in the source306. In one embodiment, source306can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source306can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source306can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source306comprises a non-oxide a single-material semiconductor. In another embodiment, the source306can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source306can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor301can include a channel308. In another embodiment, the channel308can include an unintentionally doped indium arsenide layer. In one embodiment, the channel308can include an amorphous oxide semiconductor. In another embodiment, the channel308can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel308may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel308can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel308can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on the technology used to fabricate the transistor. In another embodiment, the channel308can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel308can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. FIG.4Ashows a first view of a partial structure of the transistor400in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor400can include a recess409in the STI layer303that can be formed by a removal a portion of the STI layer303. In one embodiment, the removal of the portion of the STI layer303can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the STI layer303. In various embodiments, the transistor400can include the layers described previously in connection withFIGS.3A and3B. For example, the transistor401can include a substrate302, a buffer layer304, a source306, and a channel308. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3B. FIG.4Bshows a second view of a partial structure of the transistor401in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In various embodiments, the transistor401can include the layers described previously in connection withFIGS.3A and3B, andFIG.4A. For example, the transistor401can include a substrate302, a buffer layer304, an STI303, a source306, and a channel308. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3BandFIG.4A. FIG.5Ashows a first view of a partial structure of the transistor500in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor500can include a gate dielectric510. In one embodiment, the gate dielectric510can include a dielectric material. In another embodiment, the gate dielectric510can include silicon oxide. In another embodiment, the gate dielectric510can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric510. In one embodiment, the gate dielectric510can include hexagonal boron nitride (HBN). In one embodiment, the gate dielectric510can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric510can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. In another embodiment, the transistor500can include a gate512. In one embodiment, a gate512can be deposited on the gate dielectric512. In another embodiment, the gate512can include a metal. In another embodiment, the gate512can include a transition metal. In one embodiment, the gate512can be used to tune the threshold voltage of the device. In one embodiment, gate512can titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate512can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate512can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. In various embodiments, the transistor500can include the layers described previously in connection withFIGS.3A and3B, andFIGS.4A and4B. For example, the transistor500can include a substrate302, a buffer layer304, an STI303, a source306, a channel308, and a drain312. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3BandFIGS.4A and4B. FIG.5Bshows a second view of a partial structure of the transistor501in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In an embodiment, the spacers514can serve to provide electrical insulation between the gate512and the source and/or the drain (for example, source306and drain618, shown and described in connection withFIG.6). In one embodiment, the spacers514can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source and/or drain from making electrical contact to the gate512. In one embodiment, label511serves as a visual indication of the wrap-around gate structure of the vertical TFET. In one embodiment, the spacers514can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the spacers514. That is, the spacers514may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers514. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers514as well, giving rise to the triangular shape of the spacers514. In various embodiments, the transistor501can include the layers described previously in connection withFIGS.3A and3B, andFIGS.4A and4B. For example, the transistor501can include a substrate302, a buffer layer304, an STI303, a source306, and a channel308. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3BandFIGS.4A and4B. FIG.6shows a view of a partial structure of the transistor600in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor600can include a drain618. In another embodiment, the drain212can include an n-doped indium arsenide layer. In another embodiment, the drain618can include a nonreactive metal. In one embodiment, the drain618can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain618can include an n-doped indium gallium arsenide layer. In one embodiment, the drain618can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain618can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain618can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain618. In another embodiment, the drain618can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain618comprises a non-oxide a single-material semiconductor. In another embodiment, the drain618can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain618can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, to reduce gate-induced drain leakage, drain618can have a wider band gap than the material used for channel308. In one embodiment, for example, in an embodiment used in connection with homojunction TFETs, drain618, channel308, and source306can include the same materials, while source618is n-doped, channel308is unintentionally doped, and drain306is p-doped. In various embodiments, the transistor600can include the layers described previously in connection withFIGS.3A and3B,FIGS.4A and4B, andFIGS.5A and5B. For example, the transistor600can include a substrate302, a buffer layer304, an STI303, a source306, a channel308, a drain312, a gate dielectric510, a gate512, and spacers514. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3B,FIGS.4A and4B, andFIG.5AandFIG.5B. FIG.7shows a view of a partial structure of the transistor700in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor700can include an oxide720. In one embodiment, the oxide720can include an interlayer dielectric (ILD) material. In another embodiment, ILD can include silicon dioxide (SiO2), or a low-K material. In one embodiment, the oxide720can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like. In various embodiments, the transistor700can include the layers described previously in connection withFIGS.3A and3B,FIGS.4A and4B,FIGS.5A and5B, andFIG.6. For example, the transistor700can include a substrate302, a buffer layer304, an STI303, a source306, a channel308, a gate dielectric510, a gate512, spacers514, and drain618. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3B,FIGS.4A and4B,FIG.5AandFIG.5B, andFIG.6. FIG.8shows a view of a partial structure of the transistor800in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor800can include a recess822that can in the channel308, and that that can be formed by the removal of a portion of the drain618and a portion of the channel308. In one embodiment, the removal of the portion of the drain618and a portion of the channel303can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the drain618and a portion of the channel303. In various embodiments, the transistor800can include the layers described previously in connection withFIGS.3A and3B,FIGS.4A and4B,FIGS.5A and5B,FIG.6, andFIG.7. For example, the transistor800can include a substrate302, a buffer layer304, an STI303, a source306, a channel308, a gate dielectric510, a gate512, spacers514, drain618, and oxide720. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3B,FIGS.4A and4B,FIG.5AandFIG.5B,FIG.6, andFIG.7. FIG.9shows a view of a partial structure of the transistor900in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor900can include a recess924that can be formed by the removal of one of the oxide720. In one embodiment, the removal of the oxide720can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the one of the oxide720. In one embodiment, spacers914can be thicker than spacers514as further shown and described in connection withFIG.8. The thicker spacers914can be achieved by re-depositing a spacer (similar, but not necessarily identical to, spacers514as shown and described in connection withFIG.5) and then performing an etching step on the spacer. In one embodiment, the thicker spacers914can serve to reduce the likelihood of a shorted ground to source connection and/or a shorted ground to drain connection. In various embodiments, the transistor900can include the layers described previously in connection withFIGS.3A and3B,FIGS.4A and4B,FIGS.5A and5B, andFIG.6. For example, the transistor900can include a substrate302, a buffer layer304, an STI303, a source306, a channel308, a drain312, a gate dielectric510, a gate512, spacers514, drain618, and oxide720. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3B,FIGS.4A and4B,FIG.5AandFIG.5B, andFIG.6. FIG.10shows a view of a partial structure of the transistor1000in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor1000can include a source contact1026. In one embodiment, the source contact1026can include a metal. In one embodiment, the source contact1026can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like The source contact1026can include any alloys of such materials. In one embodiment, the source contact1026can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact1026can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the transistor1000can include a drain contact1028. In one embodiment, the drain contact1028can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. In one embodiment, the drain contact1028can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The drain contact1028can include any alloys of such materials. In one embodiment, the drain contract1028can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the drain contract1028can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In various embodiments, the transistor1000can include the layers described previously in connection withFIGS.3A and3B,FIGS.4A and4B,FIGS.5A and5B, andFIG.6. For example, the transistor1000can include a substrate302, a buffer layer304, an STI303, a source306, a channel308, a drain312, a gate dielectric510, a gate512, spacers514, drain618, and oxide720. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection withFIGS.3A and3B,FIGS.4A and4B,FIG.5AandFIG.5B, andFIG.6. FIG.11shows a diagram of an example flow diagram for the fabrication of a vertical TFET, in accordance with example embodiments of the disclosure. In block1105, a substrate can be provided. In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a p-doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof). In block1110, a shallow trench isolation layer can be deposited on the substrate. In one embodiment, the STI layer can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the STI layer can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the STI layer can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the STI layer may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the STI layer can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the STI layer can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In block1115, a buffer layer can be deposited on the substrate. In another embodiment, the buffer layer can include a III-V semiconductor material layer. Such III-V semiconductor material layers can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the buffer layer can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like. In an embodiment, the buffer layer can be patterned and etched to form trenches, such as trench, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench can have a depth D of approximately 50 nm to about 300 nm and a width W of approximately 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench (D/W) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the buffer layer can be. In block1120, a source can be deposited on the buffer layer. In another embodiment, the source can include a p-doped gallium antimonide (GaSb) layer. In one embodiment, the source can further include a p-doped aluminum anitomodnide (AlSb) and/or an indium antimonide (InSb) layer. In another embodiment, the source can include a nonreactive metal. In one embodiment, the source can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source can include an p-doped indium gallium arsenide layer. In one embodiment, the source can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating electron vacancies in the source. In one embodiment, source can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source comprises a non-oxide a single-material semiconductor. In another embodiment, the source can be approximately 1 nm to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In block1125, a channel can be deposited on the source. In another embodiment, the channel can include an unintentionally doped indium arsenide layer. In one embodiment, the channel can include an amorphous oxide semiconductor. In another embodiment, the channel can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In another embodiment, the channel can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. In block1130, a portion of the shallow trench isolation layer in a direction normal to the plane of the substrate can be removed to a level below an interface between the channel and the source. In one embodiment, the removal of the portion of the shallow trench isolation layer can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the shallow trench isolation layer. In block1135, a gate dielectric can be deposited on the channel and shallow trench isolation layer. In one embodiment, the gate dielectric can include a dielectric material. In another embodiment, the gate dielectric can include silicon oxide. In another embodiment, the gate dielectric can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric. In one embodiment, the gate dielectric can include hexagonal boron nitride (HBN). In one embodiment, the gate dielectric can be deposited using PVD, MBE, MOCVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. In block1140, a gate can be deposited on the gate dielectric. In one embodiment, a gate can be deposited on the gate dielectric. In another embodiment, the gate can include a metal. In another embodiment, the gate can include a transition metal. In one embodiment, the gate can be used to tune the threshold voltage of the device. In one embodiment, gate can titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. In one embodiment, the gate can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In block1145, a first spacer material can be deposited on a sidewall of the gate dielectric. In an embodiment, the first spacer material can serve to provide electrical insulation between the gate and the source and/or the drain. In one embodiment, the first spacer material can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source and/or drain from making electrical contact to the gate. In one embodiment, the first spacer material can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the first spacer material. That is, the first spacer material may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating first spacer material. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the first spacer material as well, giving rise to the triangular shape of the first spacer material. In block1150, a drain can be deposited on the channel, the drain comprising a first portion and a second portion. In another embodiment, the drain can include a nonreactive metal. In one embodiment, the drain can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain can include an n-doped indium gallium arsenide layer. In one embodiment, the drain can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium arsenide antimonide (GaAsSb), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain comprises a non-oxide a single-material semiconductor. In another embodiment, the drain can be approximately 1 nanometer to approximately nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, to reduce gate-induced drain leakage, drain can have a wider band gap than the material used for channel. In one embodiment, for example, in an embodiment used in connection with homojunction TFETs, drain, channel, and source can include the same materials, while source is n-doped, channel308is unintentionally doped, and drain is p-doped. In block1155, an oxide layer can be deposited on the first portion of the drain material. In one embodiment, the oxide can include an interlayer dielectric (ILD) material. In another embodiment, ILD can include silicon dioxide (SiO2), or a low-K material. In one embodiment, the oxide can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like. In block1160, the second portion of the drain can be removed. In an embodiment, the portion of the drain to be removed can include the portion of the drain not covered by the oxide layer. In one embodiment, the removal of the second portion of the drain can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the second portion of the drain. In block1165, a first portion of the channel can be removed. In one embodiment, the removal of the first portion of the channel can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the first portion of the channel. In block1170, the oxide layer can be removed. In one embodiment, the removal of the oxide can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the one of the oxide. In block1175, a second spacer material can be deposited on a sidewall of the gate dielectric and a sidewall of the channel. In an embodiment, the second spacer material can serve to provide electrical insulation between the gate and the source and/or the drain. In one embodiment, the second spacer material can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source and/or drain from making electrical contact to the gate. In one embodiment, the second spacer material can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the second spacer material. That is, the second spacer material may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating second spacer material. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the second spacer material as well, giving rise to the triangular shape of the second spacer material. In block1180, a first contact can be deposited on the source. In one embodiment, the first contact can serve as a source contact. In another embodiment, the source contact can include a metal. In one embodiment, the source contact210can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The source contact can include any alloys of such materials. In one embodiment, the source contact can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In block1185, a second contact can be deposited on the drain. In one embodiment, second contact can serve as a drain contact. In one embodiment, the drain contact can include a metal. In one embodiment, the drain contact can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The drain contact can include any alloys of such materials. In one embodiment, the drain contract can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the drain contract can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. FIG.12depicts an example of a system1200according to one or more embodiments of the disclosure. In one embodiment, the transistors described herein can be used in connection with or formed as a part of any of the devices shown in system1200. In one embodiment, system1200includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system1200can include a system on a chip (SOC) system. In one embodiment, system1200includes multiple processors including processor1210(inFIG.12, processor1210is labeled as1210) and processor N1205, where processor N1205has logic similar or identical to the logic of processor1210. In one embodiment, processor1210has one or more processing cores (represented here by processing core 11212and processing core N1212N, where1212N represents the Nth processor core inside processor1210, where N is a positive integer). More processing cores can be present (but not depicted in the diagram ofFIG.12). In some embodiments, processing core1212includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor1210has a cache memory1216to cache instructions and/or data for system1200. Cache memory1216may be organized into a hierarchical structure including one or more levels of cache memory. In some embodiments, processor1210includes a memory controller (MC)1214, which is configured to perform functions that enable the processor1210to access and communicate with memory1230that includes a volatile memory1232and/or a non-volatile memory1234. In some embodiments, processor1210can be coupled with memory1230and chipset1220. Processor1210may also be coupled to a wireless antenna1278to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna1278operates in accordance with, but is not limited to, the IEEE 1102.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. In some embodiments, volatile memory1232includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory1234includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device. Memory device1230stores information and instructions to be executed by processor1210. In one embodiment, memory1230may also store temporary variables or other intermediate information while processor1210is executing instructions. In the illustrated embodiment, chipset1220connects with processor1210via Point-to-Point (PtP or P-P) interface1217and P-P interface1222. Chipset1220enables processor1210to connect to other elements in system1200. In some embodiments of the disclosure, P-P interface1217and P-P interface1222can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used. In some embodiments, chipset1220can be configured to communicate with processor1210, the processor N1205, display device1240, and other devices1272,1276,1274,1260,1262,1264,1266,1277, etc. Chipset1220may also be coupled to the wireless antenna1278to communicate with any device configured to transmit and/or receive wireless signals. Chipset1220connects to display device1240via interface1226. Display1240may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor1210and chipset1220are integrated into a single SOC. In addition, chipset1220connects to bus1250and/or bus1255that interconnect various elements1274,1260,1262,1264, and1266. Bus1250and bus1255may be interconnected via a bus bridge1272. In one embodiment, chipset1220couples with a non-volatile memory1260, a mass storage device(s)1262, a keyboard/mouse1264, and a network interface1266via interface1224and/or1226, smart TV1276, consumer electronics1277, etc. In one embodiment, mass storage device(s)1262can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface1266is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. While the modules shown inFIG.12are depicted as separate blocks within the system1200, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory1216is depicted as a separate block within processor1210, cache memory1216or selected elements thereof can be incorporated into processor core1212. It is noted that the system1200described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor devices, as disclosed herein. The semiconductor devices (for example, the semiconductor devices described in connection with any ofFIGS.1-11), as disclosed herein, may be provided in any variety of electronic devices including consumer, industrial, military, communications, infrastructural, and/or other electronic devices. In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.). Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof. In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data. Example 1 may include an integrated circuit (IC) structure comprising: an isolation structure on a substrate, the isolation structure including a trench; a buffer material in the trench; a source on the buffer material; a channel on a portion of the source, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric. Example 2 may include the structure of example 1 and/or some other example herein, further comprising a first contact electrode on the source and a second contact electrode on the drain. Example 3 may include the structure of example 1 and/or some other example herein, wherein the trench comprises a silicon aspect ratio trapping (ART) trench. Example 4 may include the structure of example 2 and/or some other example herein, further comprising a first spacer between a sidewall of the gate dielectric and a sidewall of the drain. Example 5 may include the structure of example 4 and/or some other example herein, further comprising a second spacer between a sidewall of the channel and a sidewall of the first contact electrode. Example 6 may include the structure of example 1 and/or some other example herein, wherein the channel is gated by the gate and gate dielectric on at least a first sidewall of the channel. Example 7 may include the structure of example 6 and/or some other example herein, wherein the sidewall of the channel has Miller indices of (110). Example 8 may include the structure of example 1 and/or some other example herein, wherein the substrate comprises silicon, germanium, a III-V semiconductor, or gallium and nitrogen. Example 9 may include the structure of example 1 and/or some other example herein, wherein the buffer material comprises a III-V semiconductor. Example 10 may include the structure of example 1 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein the source comprises a p-doped material. Example 11 may include the structure of example 10 and/or some other example herein, wherein the source comprises gallium and antimony. Example 12 may include the structure of example 1 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein the drain comprises an n-doped material. Example 13 may include the structure of example 12 and/or some other example herein, wherein the drain comprises indium and arsenic. Example 14 may include the structure of example 1 and/or some other example herein, wherein the channel comprises indium and arsenic. Example 15 may include a device including a vertical tunneling field effect transistor (TFET), the device comprising: an isolation structure on a substrate, the isolation structure including a trench; a buffer material in the trench; a source on the buffer material; a channel on a portion of the source, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric. Example 16 may include the device of example 15 and/or some other example herein, further comprising a first contact electrode on the source and a second contact electrode on the drain. Example 17 may include the device of example 15 and/or some other example herein, wherein the trench comprises a silicon aspect ratio trapping (ART) trench. Example 18 may include the device of example 16 and/or some other example herein, further comprising a first spacer between a sidewall of the gate dielectric and a sidewall of the drain. Example 19 may include the device of example 18 and/or some other example herein, further comprising a second spacer between a sidewall of the channel and a sidewall of the first contact electrode. Example 20 may include the device of example 15 and/or some other example herein, wherein the vertical TFET is an n-type vertical TFET and wherein the source comprises a p-doped material. Example 21 may include the device of example 15 and/or some other example herein, wherein the vertical TFET is an n-type vertical TFET and wherein the drain comprises an n-doped material. Example 22 may include a method for fabricating an integrated circuit (IC) structure, the method comprising: depositing an isolation structure on a first portion of a substrate; depositing a buffer material on a second portion of the substrate; depositing a source on the buffer material; depositing a channel on a portion of the source, the channel including a first portion and a second portion; depositing a drain on the first portion of the channel; depositing a gate dielectric on the second portion of the channel; and depositing a gate on the gate dielectric. Example 23 may include the method of example 22 and/or some other example herein, wherein depositing the buffer material comprises depositing a III-V semiconductor. Example 24 may include the method of example 22 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein depositing the source comprises depositing a p-doped material. Example 25 may include the method of example 22 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein depositing the drain comprises depositing an n-doped material. Example 26 may include a device comprising an integrated circuit (IC) structure comprising: an isolation structure on a substrate, the isolation structure including a trench; a buffer material in the trench; a source on the buffer material; a channel on a portion of the source, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric. Example 27 may include the device of example 26 and/or some other example herein, further comprising a first contact electrode on the source and a second contact electrode on the drain. Example 28 may include the device of example 26 and/or some other example herein, wherein the trench comprises a silicon aspect ratio trapping (ART) trench. Example 29 may include the device of example 27 and/or some other example herein, further comprising a first spacer between a sidewall of the gate dielectric and a sidewall of the drain. Example 30 may include the device of example 29 and/or some other example herein, further comprising a second spacer between a sidewall of the channel and a sidewall of the first contact electrode. Example 31 may include the device of example 26 and/or some other example herein, wherein the channel is gated by the gate and gate dielectric on at least a first sidewall of the channel. Example 32 may include the device of example 31 and/or some other example herein, wherein the sidewall of the channel has Miller indices of (110). Example 33 may include the device of example 26 and/or some other example herein, wherein the substrate comprises silicon, germanium, a III-V semiconductor, or gallium and nitrogen. Example 34 may include the device of example 26 and/or some other example herein, wherein the buffer material comprises a III-V semiconductor. Example 35 may include the device of example 26 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein the source comprises a p-doped material. Example 36 may include the device of example 35 and/or some other example herein, wherein the source comprises gallium and antimony. Example 37 may include the device of example 26 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein the drain comprises an n-doped material. Example 38 may include the device of example 37 and/or some other example herein, wherein the drain comprises indium and arsenic. Example 39 may include the device of example 26 and/or some other example herein, wherein the channel comprises indium and arsenic. Example 40 may include a method for fabricating a device comprising an integrated circuit (IC) structure, the method comprising: depositing an isolation structure on a first portion of a substrate; depositing a buffer material on a second portion of the substrate; depositing a source on the buffer material; depositing a channel on a portion of the source, the channel including a first portion and a second portion; depositing a drain on the first portion of the channel; depositing a gate dielectric on the second portion of the channel; and depositing a gate on the gate dielectric. Example 41 may include the method of example 40 and/or some other example herein, wherein depositing the buffer material comprises depositing a III-V semiconductor. Example 42 may include the method of example 40 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein depositing the source comprises depositing a p-doped material. Example 43 may include the method of example 40 and/or some other example herein, wherein the IC structure comprises an n-type vertical TFET and wherein depositing the drain comprises depositing an n-doped material. Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents. While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense. This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the disclosure is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims. | 117,628 |
11862716 | DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The invention described herein, including the various aspects and/or embodiments thereof, meets the unmet needs of the art, as well as others, by providing heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material and modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided. The invention provides ways to control and modulate the carrier type and density of one or more 2D materials on the nanometer length scale, by coupling the 2D materials with multiferroic materials. In some aspects of the invention, a heterostructure is provided in which one layer is comprised of one or more 2D materials (either a single monolayer, or multiple monolayers having the same or different composition), and the adjacent layer is comprised of a multiferroic material. This multiferroic material can be a ferroelectric material, where local electrostatic domains consisting of dipole ensembles produce a local electric field, which penetrates the adjacent 2D material layer and produces an effect identical to that of a voltage applied to a conventional electrostatic gate consisting of an insulating dielectric layer. If the ferroelectric material is a thin film, the strength of the electric field is related to the thickness of the film. These domains can be oriented by a global applied electric field, or manipulated at the micron to nanoscale levels with an optical beam, proximal probe such as a conducting atomic force microscope tip (as illustrated inFIGS.9A-9E), or other techniques including optical probes. These polarization domains in the multiferroic or ferroelectric material can directly change the properties of adjacent 2D material monolayer(s), which are strongly affected by their immediate environment due to lack of bulk screening. The dielectric screening is very low due to their two-dimensional character relative to bulk material, and the screening that would normally occur due to carriers in a three-dimensional material is largely absent. Changes in environment in turn dramatically impact the carrier type and density of the 2D material. Modification of the carrier type and carrier density properties of discrete portions of the 2D material can be accomplished, for example, by variations in the local electric field induced by local dipoles in an adjacent ferroelectric layer. The invention beneficially achieves in-plane p-n type heterojunctions, rather than the conventional approach of stacking p-type and n-type layers vertically. These lateral, in-plane heterojunctions are easier to fabricate than vertical heterostructures, and avoid the significant complexities associated with vertical van der Waals heterostructures. Heterostructures and Devices. The heterostructures of the invention include a multiferroic material layer adjacent to (and preferably directly in contact with) one or more two-dimensional material layers. The two-dimensional (“2D”) materials of the invention may be provided in the heterostructure as a single monolayer, or provided as multiple monolayers. When multiple monolayers are used, preferably from 2 to 20 monolayers are provided, more preferably from 2 to 10, still more preferably from 3 to 6. The monolayers may be formed from a variety of materials, including transition metal dichalcogenides (“TMDs”), silicene, phosphorene, and graphene. The TMDs for use in the apparatus and methods of the invention have the chemical formula MX2, where M is a transition metal, and X is a chalcogen. Transition metals include elements from Groups 3-12 of the periodic table. The transition metals include Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Ac, Rf, Db, Sg, Bh, Hs, Mt, Ds, Rg, and Cn, as well as the lanthanide series elements (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), and actinide series elements (Ac, Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, No, Lr). Preferred transition metals for use in the apparatus and methods of the invention include Mo, W, Nb, Hf, Ta, and V, with Mo, W, Nb, and Ta being particularly preferred. Chalcogens include the elements found in Group 16 of the periodic table. The chalcogens include O, S, Se, Te, and Po. Preferred chalcogens for use in the apparatus and methods of the invention include S, Se, and Te, with S and Se being particularly preferred. In some aspects of the invention, preferred 2D TMD materials for use in the sensors, systems, and methods may be selected from the group consisting of MoS2, MoSe2, WS2, WSe2, VS2, VSe2, VTe2, NbS2, NbSe2, TaS2, TaSe2, and combinations thereof. Additional TMD materials formed from the transition metals and chalcogens set forth above are also within the scope of the invention. The heterostructures of the invention beneficially eliminate the need for impurity doping or physical modification of the 2D layer to create n- or p-type domains. TMD monolayers are known to be ambipolar (i.e., they can be biased to be either n- or p-type). The heterostructures of the invention incorporating multiferroic materials having arrays of polarization domains enable the creation of n- and p-type lateral heterojunctions within the 2D material layers, without the need for extrinsic doping. This obviates problems associated with dopant density, incorporation, activation, diffusion, defect formation, chemical stability, etc., all of which are major issues encountered when using extrinsic dopant atoms. The multiferroic material can be any material that exhibits more than one primary ferroic order parameter (which include ferromagnetism, ferroelectricity, and ferroelasticity). In some aspects of the invention, the multiferroic material is a ferroelectric (FE) material, where local electrostatic domains consisting of dipole ensembles exist and produce a local electric field, modifying the dielectric environment. These local domains modify and control the optical, transport and other electronic properties of the two-dimensional material. The multiferroic materials may include, but are not limited to, BiMnO3, LaMnO3, and BiFeO3, and combinations thereof. Ferroelectric materials may include, but are not limited to, lead zirconate titanate (PZT), barium titanate, lead titanate, lead magnesium niobate-lead titanate (PMN-PT), and combinations thereof. Composites of any of these materials may also be used. The multiferroic layer used in the invention may be provided as a bulk substrate or thin film. When the multiferroic layer is a thin film, it may range from about 1 nm in thickness up to many microns in thickness. The thin film may optionally be supported by a substrate material such as silica (SiO2), silicon, SiO2/Si, or sapphire, but the invention is not limited to any particular substrate material. For example, growth of multiferroic or ferroelectric thin films on periodically poled wafers may be preferred in some aspects of the invention, to provide laterally templated growth of layers deposited thereon. Examples of substrates that may be provided, optionally as templated substrates, are lithium niobate and strontium titanate. The 2D material monolayers of the invention may be exfoliated, mechanically transferred, or grown directly on the multiferroic or ferroelectric material by deposition techniques such as chemical vapor deposition. For example, multiple methods are available to mechanically transfer TMD monolayers, such as WS2, onto alternate substrates, such as multiferroic or ferroelectric films. The transfers may be conducted using a thin layer of a transfer material, such as a PMMA (polymethyl methacrylate), PC (polycarbonate), or PDMS (polydimethylsiloxane)/PC film. The direct integration of the multiferroic with the 2D material results in the smallest possible separation (≤1 nm) between the two, thereby maximizing the electric field resulting from the polarization domains in the ferroelectric material. There is no intervening dielectric layer, as there is in a conventional electrostatic gate contact. Because the ferroelectric dipole electric field decreases with distance R, and corresponds to approximately R−3, the electric field strength at the 2D layer is as large as it can be when the 2D material lies directly on top of the ferroelectric layer. This electric field penetrates the 2D material layer and modifies its local carrier density, making in n-type, p-type, or insulating, which affects transport and optical properties. An ordered array of polarization domains produces a corresponding ordered variation in carrier densities, which impacts electronic and transport properties. A periodic array of such domains may impose a super period on the 2D material layer and a corresponding change in band structure, producing tailored electronic properties that reflect the symmetry of the periodic array. Ferroelectric materials exhibit a spontaneous polarization due to internal electric dipoles which are coupled to the lattice. Typical examples include BaTiO3, BiFeO3, and PbTiO3. They can be polarized in a particular direction and manner by a global applied electric field—this polarization is retained even after the electric field is removed (this is analogous to a magnetic material which exhibits a spontaneous magnetization, and the magnetization is retained in the absence of an applied magnetic field). The polarization can also be reversed by a global applied electric field, and the hysteresis depends upon factors that are both intrinsic (e.g., coupling of the internal dipoles to the lattice) and extrinsic (e.g., interfaces, sample structure and aspect ratio). Ensembles of these dipoles form local domains within the ferroelectric material, with a net polarization oriented in a particular direction (up or down), just as magnetic domains exist in a ferromagnet. The invention beneficially provides methods for forming local domains in the heterostructures and devices, which can be oriented and manipulated on length scales ranging from a single nanometer to several microns, by application of a highly localized electric field applied, for example, using proximal probe techniques, such as through a voltage applied between the ferroelectric material surface and the tip of an atomic force microscope (AFM), which is preferably operated as a conducting atomic force microscope (CAFM). Isolated domains can be created in predetermined locations, or an ordered array of domains may be fabricated. Thus, the properties of the adjacent 2D materials can be controlled and modified with the same spatial resolution, i.e., if a 10 μm×10 μm checkerboard pattern is created in the ferroelectric material, the properties of the 2D material layer will also be modified in a 10 μm×10 μm pattern. The heterostructures of the invention allow for writing and rewriting the polarization domains of the ferroelectric material in any order, size, spacing, or period, and at any time, in a non-destructive and reversible fashion, permitting the heterostructures to form the basis of a reconfigurable electronic system. The polarization domains may be provided in any arrangement, without limitation. Exemplary polarization domain configurations include a checkerboard pattern, or concentric shapes (including, without limitation, squares, rectangles, circles, ovals, shapes exhibiting one or more axes of symmetry, or irregular shapes). The polarization domains are non-volatile, and no refresh power is required. The heterostructures also permit a global erase function, which may be achieved when a global electric field is used to erase any domains written in the ferroelectric layer. The polarization domains in an adjacent ferroelectric layer provide charge doping or local electric fields, and these domains can be used instead of an electrostatic gate to control whether the 2D material is n- or p-type. This beneficially permits fabrication of lateral n- or p-type regions in the 2D material in a reversible, non-volatile manner on a nanometer length scale (i.e., the regions may be formed on a scale of about 1 nm or larger). They have applications in nonvolatile memory, low power electronics, reprogrammable logic, complementary chemical vapor sensors, and tunable optical devices, among others. The heterostructures of the invention may be used in any electronic devices that operate based on modifications in carrier type and density. In particular, in-plane carrier transport can be more readily controlled in a 2D material layer by surface electrostatic gating because the transport channel is so thin (for example, on the order of 1 to 3 nm). A small gate voltage can more easily pinch off the channel than in a bulk three-dimensional structure, producing high “on/off” ratios at lower gate voltage values. In addition, an electrostatic gate in a 2D material layer can effectively control the carrier type as well as the carrier density, so that application of a suitable gate voltage can make the material n-type (n), p-type (p), or intrinsic (i), in which the transport is dominated by electron or hole motion, or is nearly insulating, respectively. The heterostructures of the invention are broadly applicable to devices including diodes, transistors, electroluminescent/light-emitting devices structures exhibiting negative differential resistance, and non-volatile transistor memory. When used in devices, the heterostructures of the invention may optionally be combined with any suitable components, including, but not limited to, electronic contacts, and electromagnetic signal transmitters. Signal transmitters may optionally be used, for example, to generate a signal to indicate that the 2D material layer has interacted with an agent of interest. However, it is to be appreciated that one of the benefits of the invention is the simplified fabrication that it permits by eliminating deposition and lithography steps necessary to deposit and define dielectric layers and top metal layer, as no discrete insulating dielectric layer or top metal contact are required to introduce the local electric fields. In addition, this approach offers lateral spatial resolution that is comparable to or better than that available with existing lithographic techniques. In one preferred application for the heterostructures of the invention, sensors are provided. The conductivity of monolayer TMDs, such as n-type MoS2monolayers, increases when exposed to electron-donating molecules (labeled “e”), and shows no response to hole-donating molecules (labeled “h”). SeeFIG.1. The sensor devices of the invention use the polarization domains in ferroelectric materials underlying the TMD monolayer(s) to create local n- and p-type domains in the TMD monolayer(s), which beneficially permits simultaneous detection of electron- and hole-donating molecules with same detector, enabling more comprehensive detection and more positive identification. SeeFIG.2. Lateral Heterojunctions in 2D Materials. The heterostructures, devices, and methods of the invention may beneficially be used to address the difficulties resulting from the high level of sensitivity that 2D materials exhibit in response to their environment. For example, the resistivity of 2D materials may change with charge transfer from surface adsorbates, which is useful for applications such as chemical sensing. The change with exposure to a given molecule depends upon whether the material is n- or p-type, and many 2D materials are ambipolar (can be gated to be n- or p-type). The heterostructures of the invention may be configured as chemical sensors by forming alternating n/p domains in the 2D material. In some aspects of the invention, the electric field(s) from the multiferroic layer can affect local carrier density, and can be used to make the 2D material layer n-type, p-type, or insulating, which affects transport and optical properties. An ordered array of polarization domains produces a corresponding ordered variation in carrier densities, which impacts electronic and transport properties. A periodic array of domains may impose a super period on the 2D material layer and a corresponding change in band structure, producing tailored electronic properties that reflect the symmetry of the periodic array. Changes in environment can dramatically impact the carrier type and density of the 2D material. Modification of the carrier type and carrier density properties of discrete portions of the 2D material can be accomplished, for example, by variations in the local electric field induced by local dipoles in an adjacent ferroelectric layer. The invention beneficially achieves in-plane p-n type heterojunctions, rather than the conventional approach of stacking p-type and n-type layers vertically. These lateral, in-plane heterojunctions are easier to fabricate than vertical heterostructures, and avoid the significant complexities associated with vertical van der Waals hetero structures. The heterostructures of the invention therefore beneficially include lateral p-n, p-i-n, p-n-p, or n-p-n junctions, or variations thereof appropriate for device functions. The properties of these 2D materials and the heterostructures including them can be modified and controlled by variations in the local electric field induced by dipoles in an adjacent layer. This effect and mechanism is distinct from an electric field applied by an electrostatic gate terminal. Devices incorporating these 2D material heterostructures may include, but are not limited to, diodes, transistors, electroluminescent/light-emitting devices, structures exhibiting negative differential resistance, and non-volatile transistor memory. In accordance with another aspect of the invention, lateral p-n or p-i-n junctions may be formed in a 2D material layer. Stripes of dipole domains oriented up and down may be written into the ferroelectric layer, for example, using an AFM (seeFIG.3A), and a monolayer of 2D material, such as MoSe2, is either mechanically transferred onto this surface, or grown directly thereon. The area of the MoSe2over the “up” domains is rendered p-type, and the area of the MoSe2over the “down” domains is rendered n-type, thus forming a lateral p-n junction (seeFIG.3B). No extrinsic dopant atoms or discrete electrostatic gates are introduced—only the electric field from the ferroelectric dipole domains is used to achieve n- and p-type doping. Electrical contacts may be attached to the p- and n-type sides, and when provided, are used to obtain the current-voltage characteristics of the lateral p-n junction, and are expected to exhibit rectifying behavior typical of such junctions, forming a lateral p-n junction diode. If the dipole domains are separated by an unpoled region of the ferroelectric layer, no net electric field exists in this region, and a p-i-n lateral heterojunction is formed, as illustrated inFIG.3C. These p-n and p-i-n lateral heterojunctions can result in the emission of light—when a bias voltage is applied between the p- and n-type sides, electrons and holes are driven to the junction area and radiatively recombine. The light emitting devices created by the heterostructures of the invention are valuable electronic components, with applications for displays or optical interconnects. An exemplary LED structure formed using the heterostructures of the invention is depicted inFIG.5A. The heterostructures of the invention may alternatively be configured for light absorption. In still other aspects of the invention, a lateral p-n-p or n-p-n heterojunction may be formed to create a lateral bipolar transistor or a tunnel field effect transistor, as depicted inFIGS.5B and5C. Dipole domains written into the ferroelectric layer produce well-defined n- and p-type regions in an adjacent 2D layer, as described above. Extrinsic dopant atoms are not required to form this heterojunction, as is typically done in current semiconductor device technology—only the electric field from the ferroelectric dipole domains is used to achieve n- and p-type doping.FIG.4shows that a conventional gate contact may be used to control current flow through this lateral transistor structure. Similar lateral heterojunction can be designed to exhibit negative differential resistance, where valence band states in the p-layer become resonant with conduction band states in the p-layer for certain gate voltages, leading to enhanced conductivity at these select voltages, and lower conductivity for other gate voltages. In further aspects of the invention, an ordered array of polarization domains may be formed. This produces a corresponding ordered variation in carrier densities in a 2D material layer. A periodic array of such domains may impose a super period on the 2D layer and a corresponding change in band structure. For example, a hexagonal potential modulation imposed by surface contacts upon a semiconductor two dimensional electron gas (2DEG), as may be found in GaAs, may produce a change in band structure resulting in properties similar to that of graphene. The linear band dispersion and Dirac cone characteristic of graphene derive from its hexagonal symmetry. Rather than using surface contacts, this periodic potential modulation may be produced by writing a domain pattern of selected symmetry in a ferroelectric layer, which produces a corresponding periodic potential modulation in an adjacent 2D layer. The resultant transport and optical properties of the 2D layer reflect this symmetry. If the symmetry is hexagonal, the band structure exhibits linear band dispersion rather than the pseudo-parabolic dispersion typical of 2D materials such as MoS2and phosphorene. Methods. The invention also provides methods for forming heterostructures, including, but not limited to, the heterostructures described herein. The methods include providing a multiferroic material layer and applying a local electric field to the multiferroic material layer in order to create one or more polarization domains in the multiferroic layer. For example, when the multiferroic material layer is a ferroelectric material layer, the polarization domains may comprise dipole domains. The local electric field may be applied, for example, using an optical beam, a proximal probe (such as a conducting atomic force microscope tip), or other techniques including optical probes. When a conducting atomic force microscope is used, it may be operated at a bias voltage of from ±1 V to ±10 V. When the multiferroic material layer is a ferroelectric material, a positive tip voltage will result in polarization dipoles in the ferroelectric layer that point into the sample plane, and a negative charge at the surface of the ferroelectric layer. A negative tip voltage will result in polarization dipoles in the ferroelectric layer that point out of the sample plane, and a positive charge at the surface of the ferroelectric layer. An image of the poled surface may also be obtained using the atomic force microscope by operating it in EFM phase mode. The polarization domains may be provided in any size, shape, pattern, or configuration that is desired, based on the properties or functions of the specific heterostructure being formed. The polarization domains may range from a nanometer scale (i.e., features having a width on the order of 1 nm or more) to multiple micron scale (i.e., features having a width on the order of 1 micron, 5 microns, 10 microns, or more). Polarization domains may be separated by domain walls having any desired width. In some aspects of the invention, the polarization domain wall width may be as low as from 1-10 nm, though wider domain walls are also included in the scope of the invention. In some aspects of the invention, the local electric fields may be globally erased, for example, by exposing the entire multiferroic material layer, or the entire heterostructure, to a global electric field. Once erased, the multiferroic material layer may have new local electric fields applied. The process of globally erasing the polarization domains and providing a new configuration of polarization domains may be repeated multiple times. In other aspects of the invention, the polarization domains may be modified only in desired locations, by applying appropriate local electric fields to areas having polarization domains to be changed. The local electric field may be applied to the multiferroic material layer prior to depositing a 2D material layer thereon, or it may be applied after the heterostructure including the multiferroic layer and 2D material layer has been formed. Regardless of the order of these steps, the polarization domains in the multiferroic material layer produce corresponding domains in the two-dimensional material layer that is provided on the multiferroic material layer. The term “corresponding domains” is used to refer to domains in a 2D material layer that is part of a heterostructure, where the domains have properties (such as those described above) that are influenced by or result from proximity to a polarization domain of a multiferroic material. These domains are typically positioned opposite to a polarization domain formed in a multiferroic material. The 2D material layer may be applied to the multiferroic material layer using a technique selected from the group consisting of mechanical exfoliation, mechanical transfer, and growth directly on the multiferroic material layer. The 2D material layer may be applied directly to a multiferroic material layer in some aspects of the invention. When the 2D material layer is applied to a substrate and is transferred to the multiferroic layer, the transfer may be carried out using mechanical techniques. Regardless of the material to which it is applied, the 2D material layer may be deposited by chemical vapor deposition or other deposition or growth technique to a thickness of 1 monolayer (which is about 0.7 nm thick for a TMD monolayer, but those skilled in the art will appreciate that the thickness of the monolayer will depend on the specific monolayer composition). More than one monolayer may also be applied to form the 2D material layer, either by sequential application of layers or by depositing multiple layers simultaneously. EXAMPLES Aspects of the invention will now be particularly described by way of example. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. The following descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive of or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments are shown and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. Example 1 One method for mechanically transferring a TMD monolayer, such as WS2, onto a substrate, such as a ferroelectric film, includes the use of a PMMA film, as illustrated inFIG.6B. A sample including a layer of WS2on an SiO2substrate is coated with a thin layer of PMMA (polymethyl methacrylate) resist and cured on a hot plate at 100° C. for 10 minutes, then submerged in buffered hydrofluoric acid to etch the SiO2, freeing the WS2from the growth substrate. Once fully etched, the film was rinsed in deionized H2O, where it floated on the surface, and was then lifted from the water using the desired substrate. Optionally, adhesion of the WS2layer may be improved by spinning at 2000 rpm and baking at 100° C. An acetone and isopropanol soak removes the PMMA. An optical image of PMMA transferred WS2exhibits a uniform, clean, triangular shape, and is also shown inFIG.6B. Example 2 Another method for mechanically transferring a TMD monolayer, such as WS2, onto a substrate, such as a ferroelectric film, includes the use of a PDMS/PC film, as illustrated inFIG.6C. A sample including a layer of WS2on an SiO2substrate is brought into contact a PDMS/PC film, then retracted. This moves the WS2from Si/SiO2onto the PDMS/PC film. The PDMS/PC/WS2stack is then placed onto clean Si/SiO2. The PDMS stamp is retracted, leaving the PC film on the top surface of WS2, which is then dissolved in chloroform. An optical image following PDMS transfer is also shown inFIG.6C. Example 3 The carrier type and density in a single monolayer films MoSe2was controlled by a voltage applied to the electrostatic gate. A cross section of a monolayer MoSe2was grown directly on an SiO2/Si(001) substrate. A cross-section of the structure is shown inFIG.7A. The current between the source and drain contacts is determined by the external voltage applied to the gate, where the highly doped Si substrate serves as a gate contact, and the SiO2serves as the gate dielectric. As shown inFIG.7B, when the gate voltage is negative, the MoSe2becomes p-type and the current is dominated by hole motion. When the gate voltage is positive, the MoSe2becomes n-type and the current is dominated by electron flow. This characteristic is known as “ambipolar.” For intermediate voltages, the MoSe2is depleted of carriers and becomes nearly insulating, with very little current flow. The ratio between the current in the “on” state for electron flow, and the “off” state where current flow is minimum, is greater than 104. The gate voltages required in this example are large because the SiO2is thick (about 300 nm), and the electric field due to an external voltage applied to the Si substrate decreases as t−1, where t is the thickness of the gate dielectric (SiO2). Example 4 Polarization domains were written into a 150 nm PZT/Pt/SiO2/Si test sample using a conductive atomic force microscope (CAFM) manufactured by Park Systems (Suwon, South Korea), in order to demonstrate that polarization domains in the ferroelectric film control photoluminescence (PL) intensity of mechanically transferred WS2monolayers. The sample is shown inFIG.8. The 6×6 micron image shown inFIG.8was obtained using the AFM operating in electric force microscopy imaging mode. The dark regions of the image correspond to the areas of the sample in which the AFM created dipole domains pointing up. The light regions of the image correspond to the areas of the sample in which the AFM created dipole domains pointing down. This is shown schematically in the accompanying cross section corresponding to the fiducial line drawn through the image. While the dipole domains shown here are about 500 nm in lateral dimension, domains on the scale of a few nanometers can also be successfully created and imaged. Example 5 A large area monolayer WS2grown by a CVD process on a SiO2/Si substrate in a 2 inch tube furnace. WO3powder and sulfur precursors were heated to 825° C. under a 100 sccm argon and 10 sccm hydrogen flow. Perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt was used as seed molecules to promote lateral growth. The monolayer nature was confirmed by Raman and PL mapping. The WS2film was removed from the SiO2/Si growth substrate and transferred onto a 100 nm thick PZT film on a conducting n-type strontium titanate wafer. Transfer was conducted using the method of Example 1. Before transfer, a metal marker grid pattern (Ti/Au) was deposited on the PZT film using either a shadow mask or photolithography technique, in order to assist in locating specific poled areas. Polarization domains were written into the PZT film using a C-AFM (Park Systems NX-10), which was operated using dc voltages of up to ±10 V, using two types of cantilevers: Cr—Pt coated (Multi75E, Budget Sensors) and Au-coated (PPP-NCSTAu, Nanosensors) Si cantilevers. Similar results were obtained with both. A tip voltage of ±10 V direct current (dc) was applied in the contact mode, and polarization domains were written in a checkerboard pattern. Line scan densities of at least 512 lines per 10 μm were used to write the polarization domains into the PZT in a checkerboard pattern with the tip polarities shown. Dynamic contact electrostatic force microscopy was used to image the polarization state of the poled regions, at a frequency of 75-160 kHz. The total image size is 30×30 μm, and each poled square is 10×10 μm. The dashed lines are provided as a guide, and the bias voltages applied to the C-AFM tip are indicated. An image of the poled 100 nm PZT surface was obtained using the same AFM operated in the electrostatic force microscopy phase mode, and an EFM phase image of the area is shown inFIG.9A. FIG.9Bshows a horizontal EFM line scan averaged left to right across the top two panels of the checkerboard pattern. There is strong contrast between the squares written with opposite AFM tip polarities, indicating successful poling of the PZT film. There is little contrast between the areas of PZT that were not poled by the AFM and the squares that were intentionally poled using a +10 V tip bias, due to global poling of the entire PZT film before application of the AFM.FIG.9Cshows a schematic cross section of the PZT film illustrating the orientation of the polarization domains and corresponding surface charge. A PL peak intensity map was obtained from the WS2monolayer over a 30×30 μm area in the sample plane, acquired from a region of the PZT that was intentionally poled by the AFM with the checkerboard pattern, as shown inFIG.9D. A spatial map of the PL linewidth (FWHM) corresponding to the data ofFIG.9Dis shown inFIG.9E. It will, of course, be appreciated that the above description has been given by way of example only and that modifications in detail may be made within the scope of the present invention. Throughout this application, various patents and publications have been cited. The disclosures of these patents and publications in their entireties are hereby incorporated by reference into this application, in order to more fully describe the state of the art to which this invention pertains. The invention is capable of modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts having the benefit of this disclosure. While the present invention has been described with respect to what are presently considered the preferred embodiments, the invention is not so limited. To the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the description provided above. | 35,371 |
11862717 | It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings. DETAILED DESCRIPTION In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific illustrative embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative. It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or “over” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there may be no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed. Embodiments of the disclosure provide a bipolar transistor structure in which a superlattice layer is on a portion of semiconductor layer, e.g., to impede dopant diffusion into the semiconductor layer from overlying layers. The term “superlattice layer,” as used herein, may refer to a layer of material formed from alternating layers of two or more distinct elements. One example of a superlattice material may include, e.g., a layer formed of multiple alternating layers of silicon (Si) and oxygen (O). A bipolar transistor according to the disclosure may include a semiconductor layer formed of single crystal semiconductor over an insulator layer, perhaps in the form of a semiconductor on insulator (SOI) layer of any desired thickness, including layers such as a fully depleted semiconductor on insulator (FDSOI) layer. The semiconductor layer may have an intrinsic base region of a first doping type, and an emitter/collector (E/C) region of a second (opposite) doping type adjacent the intrinsic base region. A superlattice layer is on the E/C region, and a raised E/C terminal of a second single crystal semiconductor material is on the superlattice layer. The superlattice layer separates the raised E/C terminal from the E/C region, thus impeding dopant diffusion from the raised E/C terminal into the E/C region. During operation, the superlattice layer allows the raised E/C to remain significantly more conductive (i.e., more highly doped) than the E/C region thereunder. BJT structures, such as those in embodiments of the disclosure, operate using multiple “P-N junctions.” The term “P-N” refers to two adjacent materials having different types of conductivity (i.e., P-type and N-type), which may be induced through dopants within the adjacent material(s). A P-N junction, when formed in a device, may operate as a diode. A diode is a two-terminal element, which behaves differently from conductive or insulative materials between two points of electrical contact. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the “forward” direction), but provides little to no conductivity in the opposite direction (i.e., the “reverse” direction). In the case of the P-N junction, the orientation of a diode's forward and reverse directions may be contingent on the type and magnitude of bias applied to the material composition of one or both terminals, which affect the size of the potential barrier. In the case of a junction between two semiconductor materials, the potential barrier will be formed along the interface between the two semiconductor materials. Referring toFIG.1, a preliminary structure100(simply “structure” hereafter) suitable to form a bipolar transistor structure according to embodiments of the disclosure is shown. Preliminary structure100may be processed as described herein to yield one or more lateral BJT structures with a marker layer on doped regions of semiconductor material for defining an E/C region. However, it is understood that other techniques, ordering of processes, etc., may be implemented to yield the same bipolar transistor structure(s) or similar bipolar transistor structures in further embodiments.FIG.1shows a cross-sectional view of structure100with a substrate102including, e.g., one or more semiconductor materials. Substrate102may include but is not limited to silicon, germanium, silicon germanium (SiGe), silicon carbide, or any other common IC semiconductor substrates. In the case of SiGe, the germanium concentration in substrate102may differ from other SiGe-based structures described herein. A portion or entire semiconductor substrate102may be strained. Substrate102optionally may include embedded elements for electrically separating active materials formed thereon from other regions and/or materials within substrate102. A buried insulator layer104optionally may be formed within substrate102, e.g., by converting silicon material within substrate102into a higher-resistive material such as polycrystalline or amorphous silicon (poly-Si). Buried insulator layer104may extend horizontally throughout substrate102, and/or may be formed selectively under locations where active materials are formed, examples of which are discussed elsewhere herein. In further implementations, buried insulator layer104may include oxygen doping to form a dielectric insulator or a buried oxide (“BOX”) layer underneath substrate102and electrically isolate overlying active semiconductor materials. Buried insulator layer104thus may include other elements or molecules such as Ge, N, or Si. However embodied, buried insulator layer104may be sized as narrow as possible to provide better interaction with overlying semiconductor materials, and in various embodiments may have a thickness that is at most approximately twenty-five nanometers (nm) to approximately five-hundred nm. Some portions of substrate102may not have buried insulator layer104, and/or multiple insulator layers104may be formed within substrate102at different depths. Additionally, various conductive particles (“dopants”) may be introduced into substrate102via a process known as “pre-doping” of substrate102above buried insulator layer104. Embodiments of the disclosure may include forming a set of trench isolations (TIs)110by forming and filling trenches (not labeled) with an insulating material such as oxide, to isolate one region of substrate102from an adjacent region of substrate102. Various portions of a bipolar transistor structure, including the active semiconductor materials thereof and/or other devices where applicable, may be disposed within an area of substrate102that is isolated by TI(s)110. According to one example, two TIs110are formed, with a semiconductor layer112being horizontally between the two TIs110. Semiconductor layer112may be processed via etching, deposition, doping, etc., to form portions of a lateral bipolar transistor. TIs110may be formed before active materials are formed within substrate102, but this is not necessarily true in all implementations. Each TI110may be formed of any currently-known or later developed substance for providing electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof. TI(s)110and semiconductor layer112may be planarized (e.g., by chemical mechanical planarization or other technique(s)) such that the upper surface(s) of semiconductor layer(s)112is/are substantially coplanar with the upper surface of adjacent TIs110. Structure100may include an insulator layer114on semiconductor layer112and TIs110. Insulator layer114may be used to form an insulative barrier between various semiconductor materials and certain adjustable terminals thereover, e.g., the base terminal of a lateral bipolar transistor according to the disclosure, metal gate structures of a FET-type transistor formed elsewhere over substrate102, etc. The material composition of insulator layer114may include, as non-limiting examples, insulators such as hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), tetraethyl orthosilicate Si(OC2H5)4(“TEOS”) used to form SiO2, silicon nitride (Si3N4), silicon oxynitride (SiON), high-k material or any combination of various currently known or later developed insulator layer materials. Insulator layer114may be formed, e.g., by deposition over semiconductor layer(s)112and TI(s)110such that insulator layer114covers semiconductor layer112and TI(s)110. Structure100also may include a polycrystalline semiconductor (simply “polycrystalline”) layer116over insulator layer114. Polycrystalline layer116, when formed, may be electrically non-conductive or at least less conductive than semiconductor layer112. Polycrystalline layer116, in subsequent processing, may be converted and/or removed and replaced with active semiconductor material to define a portion of a base terminal (e.g., an extrinsic base) in a bipolar transistor structure. An insulative cap118including, e.g., one or more nitride insulators (e.g., silicon nitride (SiN)) and/or other dielectric materials, may be on polycrystalline layer116and may define an uppermost layer of structure100. Insulative cap118may take the form of a “pad nitride” structured for allowing masking material(s) to be formed thereon for targeting, removing, and/or otherwise processing selected portions of structure100. FIG.2depicts removing targeted portions of insulator layer114and polycrystalline layer and forming a spacer layer120on the remaining material(s). Spacer layer(s)120can be provided as one or more bodies of insulating material formed on sidewalls of exposed material(s), e.g., by deposition, thermal growth, etc., to electrically and physically insulate materials subsequently formed on the coated material(s) from other components. According to an example, spacer layer120may have one or more of the same materials as insulative cap118(e.g., nitride insulator materials), such that spacer layer120increases the thickness of insulative cap118where it is formed above polycrystalline layer116. Spacer layer(s)120may be formed, e.g., by depositing the corresponding spacer material such that it covers any exposed surfaces and sidewalls of TI(s), semiconductor layer(s)112, insulator layer114, and/or polycrystalline layer116where applicable. In some implementations, spacer layer(s)120may include a single layer or more than two layers. Referring now toFIG.3, embodiments of the disclosure may include removing portions of spacer layer(s)120using a mask122with an opening124at a targeted position to expose semiconductor layer(s)112. This removal process may include, for example, forming mask122patterned to expose selected portion(s) of spacer layer(s)120and/or insulative cap118. Mask122may include any now known or later developed appropriate masking material, e.g., a nitride hard mask. As shown inFIG.3, any appropriate etching process, e.g., a reactive ion etch (RIE), can remove insulative cap118and spacer layer(s)120, to expose semiconductor layer(s)112, e.g., horizontally adjacent one side of insulator layer114and polycrystalline layer116. This process can be carried out at any location over semiconductor layer(s)112where one collector or emitter terminal of an eventual bipolar transistor structure will be formed. Turning toFIG.3, continued processing may include removing portions of spacer layer(s)120in opening124to expose semiconductor layer(s)112. Etching via RIE, or selective etching processes to remove silicon nitride or other material(s) within spacer layer(S)120, may be implemented to remove exposed portions of spacer layer(s)120within opening124. The same process may also yield a recessed spacer126on portions of insulator layer114and polycrystalline layer116, e.g., due to the greater thickness of insulator cap118above polycrystalline layer116and the downward etching having less effect on portions of spacer layer(s)120on sidewalls of insulator layer114and polycrystalline layer116. The removing of spacer layer(s)120within opening124may also remove a portion of semiconductor layer112thereunder, or such portions of semiconductor layer112may be removed via a subsequent operation (e.g., selective or non-selective etch). FIG.4depicts forming a raised emitter/collector (E/C) terminal130aon semiconductor layer112. In this phase of processing, raised E/C terminal130amay be formed by deposition and/or epitaxial growth of silicon and/or other semiconductor materials on semiconductor layer112and may be of the same doping type as semiconductor layer112. Raised E/C terminal130acan be formed for example by selectively growing silicon material above semiconductor layer112. Raised E/C terminal130a, however, may have a higher concentration of dopants than semiconductor layer112thereunder. The higher doping concentration in raised E/C terminal130amay increase electrical conductivity between raised E/C terminal130aand any overlying contacts for transmitting current to the lateral bipolar transistor structure. In the case where E/C terminal130ais formed using epitaxial growth and/or using deposition, raised E/C terminal130amay extend above the upper surface of spacer layer120. Turning toFIG.5, embodiments of the disclosure may include forming an additional spacer132on all exposed materials to cover insulator cap118, spacer layer120, recessed spacer126, and raised E/C terminal130a. Additional spacer132may be formed, e.g., to increase the thickness of previously recessed spacer materials (e.g., recessed spacer126) and to protect active materials (e.g., raised E/C terminal130a) from being modified or otherwise affected in subsequent processing of other materials. Further processing may include forming an additional mask134on targeted portions of additional spacer132, without forming additional mask134over portions of semiconductor layer112where another E/C terminal is desired. Additional mask134may include an opening136that is vertically over semiconductor layer112, and optionally, an adjacent portion of TI110. Opening136, moreover, may be positioned such that insulator layer114and polycrystalline layer116are horizontally between raised E/C terminal130aand opening136. Spacer layer120and additional spacer132may be removed within opening136to expose TI110and semiconductor layer112thereunder. As part of the same process, or as a subsequent process (e.g., selective silicon etching), a portion of semiconductor layer112also may be removed below opening136without significantly removing adjacent portions of TI110. FIG.6depicts removing additional mask134and forming a superlattice layer140on any exposed surfaces of semiconductor layer112. Superlattice layer140may be formed, e.g., as a silicon/oxygen superlattice made up of alternating layers (films) of oxygen material and silicon material (e.g., single crystalline Si material). In further implementations, other materials and/or combinations (e.g., multiple semiconductors and/or dielectric materials) may be used within superlattice layer140. The individual layers are identified collectively as superlattice layer140for clarity of illustration. However embodied, superlattice layer140may be formed a selective semiconductor growth process on semiconductor layer112within opening136, e.g., using an atomic layer of oxygen deposited in an atomic layer deposition (ALD) tool followed by semiconductor growth or deposition via an appropriate tool (e.g., a chemical vapor deposition (CVD) tool). The equipment used to form superlattice layer140may be connected in-situ using a low pressure (vacuum) transfer chamber. Units for manufacture may be transferred back and forth between the tool(s) used to form each layer without breaking the vacuum and to allow sufficient film growth. Turning now toFIG.7, embodiments of the disclosure may include forming another raised emitter/collector (E/C) terminal130bsuperlattice layer140and above semiconductor layer112. Raised E/C terminal130bmay be the opposite bipolar transistor terminal from raised E/C terminal130a(i.e., terminal130bis a collector when terminal130ais an emitter and vice-versa). As with raised E/C terminal130a, raised E/C terminal130bmay be formed by deposition and/or epitaxial growth of silicon and/or other semiconductor materials on semiconductor layer112and may be of the same doping type as semiconductor layer112. Raised E/C terminal130b, may have a higher concentration of dopants than semiconductor layer112thereunder. Although a direct physical interface between semiconductor layer112and raised E/C terminal130bmay pose a risk of dopant diffusion from raised E/C terminal130binto semiconductor layer112, superlattice layer140may impede such diffusion or block it altogether. However, the conductive composition of superlattice layer140may allow current to flow between semiconductor layer112and raised E/C terminal130bwithout being significantly impeded. Superlattice layer140thus may yield a substantial difference in dopant concentration between semiconductor layer and raised E/C terminal130b. FIG.8depicts the forming of an inter-level dielectric (ILD) layer144above additional spacer132, e.g., by deposition or other techniques of forming an insulative material on a structure. ILD layer144may include the same insulating material as TI(s)110or may include a different electrically insulative material. ILD layer144and TI(s)110nonetheless constitute different components, e.g., due to TI(s)110being formed within and alongside portions of semiconductor layer112instead of being formed thereon. ILD layer144at this stage may indicate only a portion of the eventual ILD layer144material to be formed over the bipolar transistor structure. After depositing ILD layer144, ILD layer144can be planarized (e.g., using CMP) such that its upper surface is substantially coplanar with insulative cap118over polycrystalline layer116. Turning toFIG.9, remaining portions of insulator layer114and polycrystalline layer116can be removed for eventual replacement with active semiconductor material to provide the base terminal of a lateral bipolar transistor structure.FIG.9depicts forming a mask146over ILD layer144and portions of additional spacer132that do not overlie insulator layer114and polycrystalline layer116. With mask146in place, polycrystalline layer116can be removed (e.g., via etching) to create an opening148above semiconductor layer112. Additionally, insulator layer114may provide an “etch stop layer” to initially prevent further etching beneath polycrystalline layer116. In this case, a different type of etching (e.g., selective etching, wet etchants, etc.) can be used to remove insulator layer114without significantly removing or affecting semiconductor layer112thereunder. FIG.10depicts forming a base terminal150(e.g., an extrinsic base material) within opening148(FIG.9). Base terminal150may be formed by deposition and/or epitaxial growth of silicon and/or other semiconductor materials within opening148and may be of the same doping type as semiconductor layer112thereunder. Base terminal150can be formed for example by selectively growing silicon material above semiconductor layer112. Base terminal150, however, may have a higher concentration of dopants than underlying portions of semiconductor layer112. In the eventual lateral bipolar transistor structure, base terminal150may define a highly doped extrinsic base region while the portions of semiconductor layer112below base terminal150may define a less highly doped intrinsic base region. Intrinsic base region112bof semiconductor layer112below base terminal150may have an optional dopant implant before base terminal150is formed and of the same conductivity type as base terminal150to form intrinsic base region112b. The higher doping concentration in base terminal150may increase electrical conductivity between base terminal150and any overlying contacts for controlling the flow of current through the lateral bipolar transistor structure. Despite the higher concentration of dopants, base terminal150may have the same material composition, or a similar material composition, as semiconductor layer112(e.g., silicon, SiGe, or a combination of two, and/or other semiconductor material and may contain carbon doping). When base terminal150is formed by deposition or non-selective growth, it may be planarized by use of chemical mechanical planarization (CMP) such that its upper surface is substantially coplanar with adjacent spacer layer(s)120, additional spacer(s)132, and ILD layer144. In the eventual bipolar transistor structure, base terminal150may be alternatively known as or referred to as an extrinsic base region. Turning toFIG.11, additional portions of ILD layer144can be formed over previously-formed portions of ILD layer144as well as base terminal150, e.g., by deposition or other techniques of forming an insulative material on a structure. In some implementations (not shown), a silicide layer as known in the art could be formed on upper surfaces of raised E/C terminals130a,130band/or base terminal150prior to ILD layer144deposition. For example, a Co, Ti, NI, Pt, or similar self-aligned silicide (silicide) could be formed prior to ILD layer144deposition. Additional metallization layers (not shown) may be formed on ILD layer144during middle-of-line and/or back-end-of-line processing. To electrically couple various components discussed herein to such metallization layers, a set of E/C contacts152may be formed on raised E/C terminals130a,130band within ILD layer144. Portions of insulative cap(s)118and/or additional spacer(s)132on the upper surface of raised E/C terminals130a,130bbe removed by vertical etching (e.g., by RIE) as E/C contacts152are formed, while other portions of insulative cap(s)118may remain intact. Similarly, a set (i.e., one or more) base contacts154may be formed on base terminal150and within ILD layer144. One or more of contacts152,154to overlying circuit elements may be formed within predetermined portions of ILD layer144by a controlled amount of vertical etching to form openings to one or more contact sites, and then filling the openings with a conductor. Each contact152,154may include any currently known or later developed conductive material configured for use in an electrical contact, e.g., tungsten (W), copper (Cu), aluminum (Al), gold (Au), etc. Contacts152,154may additionally include refractory metal liners (not shown) positioned alongside ILD layer144to prevent electromigration degradation, shorting to other components, etc. As discussed herein, selected portions of base terminal150and/or raised E/C terminals130a,130bmay include silicide regions (i.e., portions of semiconductor that are annealed in the presence of an overlying conductor) to increase the electrical conductivity at their physical interface with contact(s)152,154, where applicable. Referring toFIGS.11and12, in whichFIG.12provides a plan view, embodiments of the disclosure provide a lateral bipolar transistor structure160in which superlattice layer140is present at the boundary between semiconductor layer112and raised E/C terminal(s)130a,130bthereover. In some cases, superlattice layer140itself may define the physical boundary between semiconductor layer112and raised E/C terminal(s)130a,130b, e.g., due to horizontally abutting spacer layer(s)120. The composition of superlattice layer140(e.g., alternating thin layers of semiconductor and insulative material) may preserve current flow from raised E/C terminal(s) to semiconductor layer112, while also blocking ingress of dopant particles from raised E/C terminal(s)130a,130binto E/C regions112a,112bof semiconductor layer112thereunder. Moreover, these aspects of superlattice layer140will protect the dopant concentration of an intrinsic base region112bof semiconductor layer112, defined as any portion of semiconductor layer112that is located vertically below base terminal150. The composition of materials within superlattice layer140, furthermore, ensures that P-N junctions will continue to form within active portions of semiconductor layer112that are close to raised E/C terminal(s)130a,130b(i.e., those adjacent superlattice layer140). Where desired, the physical interface between either of E/C region(s)112aof semiconductor layer112and E/C terminal130a,130bthereover may not include superlattice layer140(i.e., it is free of superlattice material), despite superlattice layer140being included between the other E/C region112aand E/C terminal130a,130b. As shown in the plan view ofFIG.12, each base terminal150and raised E/C terminal130a,130bmay have several contacts152,154thereto. Additionally, for lower total base resistance, base terminal150may extend along a lateral length that is greater than raised E/C terminal(s)130a,130bto provide additional surface area for coupling to base contacts154. FIG.13depicts a further embodiment of lateral bipolar transistor structure160in which raised E/C terminal130bis laterally displaced from base terminal150. During processing, the location selected to form superlattice layer140and E/C terminal130bthereover (e.g., using mask134(FIG.5)), may be located at a horizontal distance S away from the eventual location of base terminal150. Horizontal distance S may be chosen to suit a particular application and/or to provide a desired amount of conductivity through semiconductor layer112. As examples, horizontal distance S may be, e.g., between approximately ten nanometers (nm) and approximately fifty μm. In this example, E/C terminal130bcan be the collector terminal and distance S between intrinsic base region112band E/c terminal130bcan be controlled to increase collector-base breakdown voltage (BVCBO). In this example, portions of additional spacer132and/or insulative cap118may be between raised E/C terminal130band/or superlattice layer140across distance S. Furthermore, in still further implementations, the orientation may be horizontally mirrored such that raised E/C terminal130bis horizontally adjacent spacer layer120and base terminal150. In this case, raised E/C terminal130acan be horizontally distal to base terminal150. Turning toFIG.14, further embodiments of the disclosure may include forming superlattice material at multiple locations, instead of on only one portion of semiconductor layer112. In such implementations, processing of semiconductor layer112may include forming multiple openings170, each over a respective portion of semiconductor layer112. One or both opening170may be located adjacent spacer layer(s)120, but this is not necessarily required in all instances. Openings170may be formed substantially as described elsewhere herein regarding opening136(FIG.5). As shown inFIG.15, embodiments of the disclosure may include forming two superlattice layers140a,140bat respective locations and raised E/C terminals130a,130bsubstantially as described elsewhere herein. In this case, both the emitter and collector terminals include a respective superlattice layer140a,140babove semiconductor layer112and below raised E/C terminals130a,130b. FIG.16depicts further processing to form base terminal150as well as ILD layer144and contacts152,154as discussed elsewhere herein. Lateral bipolar transistor structure160thus may include multiple superlattice layers140a,140bwhere desired without substantially modifying or departing from other example processing methodologies discussed herein. Multiple superlattice layers140a,140bbeing included may further impede dopant diffusion from raised E/C terminals130a,130binto semiconductor layer112where desired. The presence of insulative cap118and spacer layer(s)120, additional spacers132may also continue to laterally insulate active portions of lateral bipolar transistor structure160from each other. FIG.17depicts a further implementation of lateral bipolar transistor structure160, in which multiple superlattice layers140a,140bare horizontally displaced from base terminal150and spacer layer(s)120. For instance, superlattice layer140aand raised E/C terminal130athereover may be horizontally displaced from spacer layer(s)120or base terminal150by a first distance S1, such that insulative cap118and/or additional spacer132horizontally separate raised E/C terminal130aand superlattice layer140afrom base terminal150. Similarly, superlattice layer140band raised E/C terminal130bthereover may be horizontally displaced from spacer layer(s)120or base terminal150by a second distance S2, such that insulative cap118and/or additional spacer132horizontally separate raised E/C terminal130band superlattice layer140bfrom base terminal150. In this case, none of raised E/C terminals130a,130bor superlattice layers140a,140bhorizontally abut spacer layer120or base terminal150. The size of distances S1, S2can be controlled, selected, etc., to suit various technical applications (e.g., desired conductivity through semiconductor layer112), IC layouts, or other technical parameters. Embodiments of the disclosure provide various technical and commercial advantages. The use of superlattice layers140on semiconductor layer112may reduce or prevent dopant migration from raised E/C terminal(s)130a,130binto semiconductor layer112. Precise control over dopant concentration in active regions of lateral bipolar transistor structure160may in turn yield electrical properties that are superior to conventional structures, e.g., cut-off frequency (fT), current gain (β), early voltage (VA), etc. Embodiments of the disclosure are particularly suitable for use in PDSOI and FDSOI technology, where the height of a bipolar transistor relative to other devices or transistors affects operational characteristics and/or manufacturing. Methods according to the disclosure may use an additional mask (e.g., mask134(FIG.5)) to form and process superlattice layer140, but this is still advantageous when compared with other processing paradigms to form lateral bipolar transistors. The method and structure as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a center processor. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not. Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately,” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s). The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated. | 36,415 |
11862718 | Similar numbers refer to similar parts throughout the drawings. DETAILED DESCRIPTION A new transistor structure10and method of manufacture and operation thereof is depicted in the present disclosure and throughoutFIGS.1-5. The transistor structure10is a new and improved apparatus, as will be discussed and described hereafter. Referring specifically toFIG.1, a side view of a cross-section for a first embodiment of a transistor structure10in accordance with the present disclosure is shown. Generally, the transistor10is a majority carrier (electron), gate voltage controlled device (i.e., a field effect transistor or “FET”) commonly referred to as a high-electron-mobility transistors (HEMT) (while depicted as planar for clarity, it is appreciated that known techniques may also be applied to achieve a non-planar transistor). Shown in the transistor structure10are a plurality of layers including a substrate12, a pseudomorphic transport layer or channel layer14, barrier layer16and a lateral growth layer18. The substrate12abuts against and is on top of the pseudomorphic transport layer14. The pseudomorphic transport layer14abuts against and is on top of the substrate12and the barrier layer16. The barrier layer16abuts against and is on top of the pseudomorphic transport layer14and the lateral growth layer18, while the lateral growth layer18abuts against and is on top of the barrier layer16. Further included is a contact20. The contact20is located within the lateral growth layer18and abuts the barrier layer16. The contact20may be any known electrical contact and may be electrically coupled to any device or other contact or device as known in the art and as dictated by the desired implementation. In the exemplary embodiments, the lateral growth layer18is substantially single crystalline. Although the lateral growth layer18is referred to herein as “monocrystalline” or “crystalline”, one of ordinary skill will appreciate that a low level of crystal defects may nevertheless be present as artifacts of an imperfect epitaxial growth processes though the goal is perfect crystalline structure. In one embodiment, the substrate12is made of AlN, but may be made of any III-N material. Of all binary materials with large bandgap, AlN has one of, if not the highest thermal conductivity that can serve as a native substrate for III-N based devices. According to another aspect, the substrate may also be made of boron nitride (BN). Further, the pseudomorphic transport layer or channel layer14in one embodiment is made of GaN. The thin pseudomorphic transport layer14allows for aggressive scaling and high frequency performance. In an alternative embodiment the channel layer14is indium nitride (InN). In the pseudomorphic transport layer14the layer laterally strained (extended or compressed) in order to matched the lattice of the crystalline substrate. In further alternative embodiments, the channel layer14is a ternary alloy of GaN, such as aluminum gallium nitride (AlxGa1-xN where x is an integer greater than 2), a ternary alloy of InN, such as aluminum indium nitride (AlxIn1-xN, where x is an integer greater than 2) or a quaternary alloy including at least one group III element and nitrogen, such as InxAlyGa1-x-yN, where x+y are greater than 2. Generally, any III-N materials may be utilized for the barrier layer16, as the barrier layer16choice is dependent on the III-N material selected for the channel layer14to provide the barrier layer16with a larger bandgap than the channel layer14. In an exemplary embodiment, the barrier layer16is substantially monocrystalline and lattice matched to the III-N material utilized in the channel layer14. In the exemplary embodiment, the barrier layer16is of a second III-N material having the same crystallinity as that of the channel layer14to form a heterointerface. The lateral growth layer18in the exemplary embodiment is at least one thick layer of single crystal AlN to be grown epitaxially on top of at least a portion of the barrier layer16and contact20by a number of methods. In an exemplary embodiment, when using an AlN substrate, rather than GaN, the lateral growth layer18can be grown arbitrarily thick. When you have a pseudomorphic GaN layer14, the lateral growth layer can be as thick as the desired implementation requires it to be. For example, in one embodiment the lateral growth layer is 1 nm or greater. In another embodiment it may be 10 nm or greater. In yet another embodiment it may be 100 nm or greater. In further embodiments it may be 1 mm or greater. Prior art may only allow for 3 nm growth before the AlN would completely relax resulting in cracking of the layer. Epitaxy refers to a type of crystal growth or material deposition in which new crystalline layers are formed with a well-defined orientation with respect to the crystalline substrate. The new layers formed are called the epitaxial film or epitaxial layer. The relative orientation of the epitaxial layer to the crystalline substrate is defined in terms of the orientation of the crystal lattice of each material. For epitaxial growth, the new layer will be crystalline and will all have a single orientation relative to the substrate; amorphous growth or multicrystalline growth with random crystal orientation does not meet this criterion. These methods to get epitaxial growth include, but are not limited to, chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), sputtering, pulled laser deposition (PLD), or other such deposition or epitaxy techniques. The growth or deposition occurs in a gate to drain region of a transistor or anywhere there is open semiconductor space between electrodes. Ideally, a single crystal material would be deposited in intimate contact with the electrodes and the gate-to-drain region where the largest thermal gradient occurs. In current material systems, which are lattice-fit to GaN, AlN can only be grown a few nm before it completely relaxes and thermal transport will be compromised. Using AlN as the substrate12enables thick layers of AlN as the lateral growth layer18to be grown on top of the pseudomorphic GaN as the channel layer14, or on other layers such as the barrier layer16, and allow the lateral growth layer18to completely surround the device area at the point of heat generation. AlN is a very good electrical insulator and will not induce breakdown under high voltage or high power operation of an electronic device. In this embodiment or another alternative embodiment, with the right combination of materials lateral epitaxial overgrowth can be used to strategically “encapsulate” metal contacts, such as contact20. Ideally, a single crystal material would be deposited in intimate contact with electrodes and gate-to-drain region where the largest thermal gradient occurs. This solution provides a way to reduce thermal resistivity at the transistor level for better thermal management by spreading heat more efficiently away from the junction where heat is created. After a standard HEMT is grown, including barrier layers, AlN may be grown in as layer18. AlN has a large lattice mismatch with AlN and prior attempts result in cracking, highly amorphous growing or polycrystalline in nature leading to inferior thermal conductivity. Current backside heat extraction using the AlN substrate (or other substrates) and the community at large does not typically attempt topside thermal solutions because they interfere with high frequency operation and device or MMIC fabrication. The presently disclosed single crystal AlN layer as the lateral growth layer18may interfere with high frequency operation as it can act as an insulator and AlN has a dielectric constant around 10. Referring toFIG.2, a side view of a cross-section for a second embodiment of a transistor structure110is shown. The second embodiment is generally similar to the first embodiment with a few noted differences. The second embodiment110includes an etched region122and an etch stop layer124. The barrier layer16abuts against and is on top of the pseudomorphic transport layer14, the etched region122, and the lateral growth layer18, while the lateral growth layer18abuts against and is on top of the barrier layer16, and the etched region122. The contact20abuts a portion of the etched region122is located within the lateral growth layer18and abuts the barrier layer16. As described below with respect to operation, the etched region122is created by surface cleaning an intermediate sacrificial layer (not shown). The etch is selectivity achieved between the layers, therefore the composition of the etch is tailored to the composition of the layers so as to remove the sacrificial layer but not harm the rest of the other layers or package. Surface cleaning may be performed by sputter-etching, chemical etching, reactive gas etching or ion milling. For example, the native oxide of silicon may be removed with a hydrofluoric acid dip, while GaAs is more typically cleaned by a bromine-methanol dip. The resultant ohmic areas can be etched all the way through for ohmic regrowth, and a window can be etched down to the etch stop layer124for gate placement. This would result in a device that is completely encapsulated in a layer of single crystal AlN18. The etched region122allows removal of the dielectric and a reduction in the parasitic capacitance. The ohmic region of a FET transistor (also called the linear region) is the region where the drain current has a linear response to changes in the drain-source voltage which mimics the linear response that would be obtained from Ohm's Law. The drain current depends on the drain-source voltage. Right at the beginning of the curve, when the drain-source voltage is small, the drain current varies nearly linearly with the drain-source voltage. The ohmic region is the only region on a FET characteristics curve where there is a linear response in current from changes in the voltage. Referring toFIG.3, a third embodiment a side view of a cross-section for a third embodiment of a transistor structure210is shown. The third embodiment is generally similar to the first embodiment and second embodiment with a few noted differences. The barrier layer16abuts against and is on top of the pseudomorphic transport layer14, the etched region122, and a material226within the etched region122, and the lateral growth layer18. The lateral growth layer18abuts against and is on top of the barrier layer16, the etched region122and the material226within the etched region122. The contact20abuts a portion of the etched region122and the material226and is located within the lateral growth layer18and abuts the barrier layer16. Further, in an alternative embodiment an additional material via a layer over the contact20grown around and subsequently etched around it, or even used as a sacrificial layer to create an air gap as is discussed in the prior embodiment. After cleaning the intermediate sacrificial layer (not shown), as discussed with the second embodiment, materials can be deposited via sputter deposition (sputtering), evaporation, or chemical vapor deposition (CVD). Sputtering is generally a faster and more a convenient method of metal deposition than evaporation; however, ion bombardment from the plasma may induce surface states or even invert the charge carrier type at the surface. For this reason, the gentler CVD is used more often. Because deposited metals can oxidize in ambient conditions, to the detriment electrical properties of the contacts, it is common to form ohmic contacts with layered structures. Further, when the etched region is removed, it can be replaced with adding a relatively low dielectric material226. A relatively low dielectric material226, as used herein, is a material with a smaller relative dielectric constant relative to silicon dioxide. The relative dielectric constant of silicon dioxide is the ratio of the permittivity of silicon dioxide divided by the permittivity of a vacuum, which is 3.9. Using a relatively low dielectric material226reduces parasitic capacitance. Some examples of relatively low dielectric materials include, but are not limited to, fluorine doped silicone dioxide, organosilicate glass, pourous silicon dioxide, porous organosilicate glass, spin-on organic polymeric dielectrics including: polyimides, polynorbornenes, benzocyclobutenes, and polytetrafluoroethylenes, and spin-on silicone based polymeric dielectrics including: hydrogen silsesquioxane and methylsilsesquioxane. According to another aspect, the relatively low dielectric material226can be air; however, air can cause mechanical instability if used too frequently within the package as a whole. Low permittivity dielectrics can also be added adjacent to gates or other sensitive areas within the package. In some embodiments the relatively low dielectric material226may have a dielectric constant less than 10. Having thus described exemplary non-limiting configurations of the transistor10,110, and210, a method of fabrication and its operation with respect to use within a system will be discussed with reference to some exemplary features used with the various embodiments. Referring specifically toFIG.4, an exemplary flow chart of a method400of fabricating a transistor10, is shown and described. First, a channel layer14is deposited402onto the substrate12. Then, the barrier layer16is deposited404abutting the channel layer14. The contact20is provided406and abuts the barrier layer16. The lateral growth layer18is then grown408epitaxially over the contact20and the barrier layer16. A method of fabricating a transistor110additionally includes an etched region122and an etch stop layer124. The etch stop layer124and the sacrificial layer is deposited410on top of the barrier layer16. The sacrificial layer is then removed412, creating the etched region122. The lateral growth layer18is then grown408over top of the contact so that the contact20abuts against and is on top of the etched region122, within the lateral growth layer18, and abuts the barrier layer16. Generally, the layers12,14,16are deposited or provided prior to placing a contact20and the lateral growth layer18may be deposited after the contact has been placed. A method of fabricating a transistor210further includes the barrier layer16that abuts against the pseudomorphic transport layer14, the etched region122, the material226within the etched region122, and the lateral growth layer18. The lateral growth layer18abuts against the barrier layer16, the etched region122and the material124within the etched region122. The contact20is located abuts against and is on top of the etched region122and within the lateral growth layer18and abuts the barrier layer16. The material226is added414to the transistor210structure. The material may be added416via a number of methods including, adding the material prior to growing the lateral growth layer16, creating an aperture within the lateral growth layer18in which to deposit the material, or by other known methods. After a top side heat sink via the lateral growth layer18on top of the transistor structure10,110,210has been created, a rear side heat sink (Item22inFIG.1and Item416inFIG.4), as used in the art, may be added to the transistor. Such a rear side heat sink structure would further increase the heat dissipation ability and promote greater heat dissipation to allow parts containing the transistor, to have longer usable life. The packages described herein may be particularly suitable for HEMTs that are incorporated into radio frequency (RF) systems for power management or power amplification at various frequencies.FIG.5is a block diagram of an exemplary RF system500in accordance with various embodiments. The RF system500may be a wireless communication device that has an RF front-end502that includes various components, as necessary, to facilitate transmission or reception of RF signals. The components could include, but are not limited to, an antenna switch module, a transmitter, a receiver, an amplifier, a converter, a filter, etc. In addition to the RF front-end502, the RF system500may have an antenna504, a transceiver506, a processor508, and a memory510coupled with each other as shown, or additionally coupled in a way known to those skilled in the art. The RF system500may further include a power supply512coupled to one or more of the other components to provide appropriate power thereto. In various embodiments, HEMTs (or other devices) packaged in accordance the present teachings may be employed in a power management application of the power supply512, an amplification application of the RF front-end502, or other in applications. In various embodiments, the wireless communication device500may be, but is not limited to, a mobile telephone, a paging device, a personal digital assistant, a text-messaging device, a portable computer, a desktop computer, a base station, a subscriber station, an access point, a radar, a satellite communication device, or any other device capable of wirelessly transmitting/receiving RF signals. In another embodiment, the device500is an optical device, specifically a UV emitter. AlN is transparent below 6.2 eV or above about 200 nm. Further, optical devices typically have poor ohmic contacts resulting in heat dissipation and could benefit from the use of AlN grown epitaxially. Various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments. While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure. The above-described embodiments can be implemented in any of numerous ways. For example, embodiments of technology disclosed herein may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code or instructions can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers. Furthermore, the instructions or software code can be stored in at least one non-transitory computer readable storage medium. Also, a computer or smartphone utilized to execute the software code or instructions via its processors may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format. Such computers or smartphones may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks. The various methods or processes outlined herein may be coded as software/instructions that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine. In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, USB flash drives, SD cards, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory medium or tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the disclosure discussed above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present disclosure as discussed above. The terms “program” or “software” or “instructions” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present disclosure need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present disclosure. Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments. Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements. All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms. “Logic”, as used herein, includes but is not limited to hardware, firmware, software and/or combinations of each to perform a function(s) or an action(s), and/or to cause a function or action from another logic, method, and/or system. For example, based on a desired application or needs, logic may include a software controlled microprocessor, discrete logic like a processor (e.g., microprocessor), an application specific integrated circuit (ASIC), a programmed logic device, a memory device containing instructions, an electric device having a memory, or the like. Logic may include one or more gates, combinations of gates, or other circuit components. Logic may also be fully embodied as software. Where multiple logics are described, it may be possible to incorporate the multiple logics into one physical logic. Similarly, where a single logic is described, it may be possible to distribute that single logic between multiple physical logics. Furthermore, the logic(s) presented herein for accomplishing various methods of this system may be directed towards improvements in existing computer-centric or internet-centric technology that may not have previous analog versions. The logic(s) may provide specific functionality directly related to structure that addresses and resolves some problems identified herein. The logic(s) may also provide significantly more advantages to solve these problems by providing an exemplary inventive concept as specific logic structure and concordant functionality of the method and system. Furthermore, the logic(s) may also provide specific computer implemented rules that improve on existing technological processes. The logic(s) provided herein extends beyond merely gathering data, analyzing the information, and displaying the results. Further, portions or all of the present disclosure may rely on underlying equations that are derived from the specific arrangement of the equipment or components as recited herein. Thus, portions of the present disclosure as it relates to the specific arrangement of the components are not directed to abstract ideas. Furthermore, the present disclosure and the appended claims present teachings that involve more than performance of well-understood, routine, and conventional activities previously known to the industry. In some of the method or process of the present disclosure, which may incorporate some aspects of natural phenomenon, the process or method steps are additional features that are new and useful. The articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.” The phrase “and/or,” as used herein in the specification and in the claims (if at all), should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc. As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law. As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc. When a feature or element is herein referred to as being “on” another feature or element, it can be directly on the other feature or element or intervening features and/or elements may also be present. In contrast, when a feature or element is referred to as being “directly on” another feature or element, there are no intervening features or elements present. It will also be understood that, when a feature or element is referred to as being “connected”, “attached” or “coupled” to another feature or element, it can be directly connected, attached or coupled to the other feature or element or intervening features or elements may be present. In contrast, when a feature or element is referred to as being “directly connected”, “directly attached” or “directly coupled” to another feature or element, there are no intervening features or elements present. Although described or shown with respect to one embodiment, the features and elements so described or shown can apply to other embodiments. It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed “adjacent” another feature may have portions that overlap or underlie the adjacent feature. Spatially relative terms, such as “under”, “below”, “lower”, “over”, “upper”, “above”, “behind”, “in front of”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, elements described as “under” or “beneath” other elements or features would then be oriented “over” the other elements or features. Thus, the exemplary term “under” can encompass both an orientation of over and under. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, the terms “upwardly”, “downwardly”, “vertical”, “horizontal”, “lateral”, “transverse”, “longitudinal”, and the like are used herein for the purpose of explanation only unless specifically indicated otherwise. Although the terms “first” and “second” may be used herein to describe various features/elements, these features/elements should not be limited by these terms, unless the context indicates otherwise. These terms may be used to distinguish one feature/element from another feature/element. Thus, a first feature/element discussed herein could be termed a second feature/element, and similarly, a second feature/element discussed herein could be termed a first feature/element without departing from the teachings of the present invention. An embodiment is an implementation or example of the present disclosure. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” “one particular embodiment,” “an exemplary embodiment,” or “other embodiments,” or the like, means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the invention. The various appearances “an embodiment,” “one embodiment,” “some embodiments,” “one particular embodiment,” “an exemplary embodiment,” or “other embodiments,” or the like, are not necessarily all referring to the same embodiments. If this specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element. As used herein in the specification and claims, including as used in the examples and unless otherwise expressly specified, all numbers may be read as if prefaced by the word “about” or “approximately,” even if the term does not expressly appear. The phrase “about” or “approximately” may be used when describing magnitude and/or position to indicate that the value and/or position described is within a reasonable expected range of values and/or positions. For example, a numeric value may have a value that is +/−0.1% of the stated value (or range of values), +/−1% of the stated value (or range of values), +/−2% of the stated value (or range of values), +/−5% of the stated value (or range of values), +/−10% of the stated value (or range of values), etc. Any numerical range recited herein is intended to include all sub-ranges subsumed therein. Additionally, the method of performing the present disclosure may occur in a sequence different than those described herein. Accordingly, no sequence of the method should be read as a limitation unless explicitly stated. It is recognizable that performing some of the steps of the method in a different order could achieve a similar result. In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures. In the foregoing description, certain terms have been used for brevity, clearness, and understanding. No unnecessary limitations are to be implied therefrom beyond the requirement of the prior art because such terms are used for descriptive purposes and are intended to be broadly construed. Moreover, the description and illustration of various embodiments of the disclosure are examples and the disclosure is not limited to the exact details shown or described. | 36,633 |
11862719 | DETAILED DESCRIPTION OF THE DISCLOSURE The aspects of the disclosure and the various features and advantageous details thereof are explained more fully with reference to the non-limiting aspects and examples that are described and/or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and features of one aspect may be employed with other aspects, as the skilled artisan would recognize, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as to not unnecessarily obscure the aspects of the disclosure. The examples used herein are intended merely to facilitate an understanding of ways in which the disclosure may be practiced and to further enable those of skill in the art to practice the aspects of the disclosure. Accordingly, the examples and aspects herein should not be construed as limiting the scope of the disclosure, which is defined solely by the appended claims and applicable law. Moreover, it is noted that like reference numerals represent similar parts throughout the several views of the drawings and in the different embodiments disclosed. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the another element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the another element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. In addition to the type of structure, the characteristics of the semiconductor material from which a transistor is formed may also affect operating parameters. Of the characteristics that affect a transistor's operating parameters, the electron mobility, saturated electron drift velocity, electric breakdown field, and thermal conductivity may have an effect on a transistor's high frequency and high power characteristics. Electron mobility is the measurement of how rapidly an electron is accelerated to its saturated velocity in the presence of an electric field. In the past, semiconductor materials, which had a high electron mobility, were preferred because more current could be developed with a lesser field, resulting in faster response times when a field is applied. Saturated electron drift velocity is the maximum velocity that an electron can obtain in the semiconductor material. Materials with higher saturated electron drift velocities are preferred for high frequency applications because the higher velocity translates to shorter times from source to drain. Electric breakdown field is the field strength at which breakdown of the Schottky junction and the current through the gate of the device suddenly increases. A high electric breakdown field material is preferred for high power, high frequency transistors because larger electric fields generally can be supported by a given dimension of material. Larger electric fields allow for faster transients as the electrons can be accelerated more quickly by larger electric fields than by smaller ones. Thermal conductivity is the ability of the semiconductor material to dissipate heat. In typical operations, all transistors generate heat. In turn, high power and high frequency transistors usually generate larger amounts of heat than small signal transistors. As the temperature of the semiconductor material increases, the junction leakage currents generally increase and the current through the field effect transistor generally decreases due to a decrease in carrier mobility with an increase in temperature. Therefore, if the heat is dissipated from the semiconductor, the material will remain at a lower temperature and be capable of carrying larger currents with lower leakage currents. The disclosure includes both extrinsic and intrinsic semiconductors. Intrinsic semiconductors are undoped (pure). Extrinsic semiconductors are doped, meaning an agent has been introduced to change the electron and hole carrier concentration of the semiconductor at thermal equilibrium. Both p-type and n-type semiconductors are disclosed, with p-types having a larger hole concentration than electron concentration, and n-types having a larger electron concentration than hole concentration. Silicon carbide (SiC) has excellent physical and electronic properties, which should theoretically allow production of electronic devices that can operate at higher temperatures, higher power, and higher frequency than devices produced from silicon (Si) or gallium arsenide (GaAs) substrates. The high electric breakdown field of about 4×E6 V/cm, high saturated electron drift velocity of about 2.0×E7 cm/sec and high thermal conductivity of about 4.9 W/cm-° K indicate that SiC would be suitable for high frequency and high power applications. In some embodiments, the transistor of the present invention comprises Si, GaAs or other suitable substrates. The drain lag in the disclosed HEMTs is in some aspects addressed with the addition of structures. In these structures, a buried p-type layer is used to simultaneously achieve high breakdown, and reduce drain lag without unduly increasing leakage current. The p-type layer helps in optimizing the breakdown voltage and can be charged and discharged easily which ensures reduction of drain lag. In one embodiment, the p-type layer is formed in a SiC substrate. In embodiments where the p-region is formed in the substrate, two problems can be alleviated: 1. It is difficult to form p-type layers in Group III-N using ion-implantation. Selective ion-implantation enables optimization of the device structure by allowing different concentrations of dopants to be obtained in different regions. This can be more difficult with epitaxial growth. However, it should be understood that the buried p-region according to different embodiments of the present invention can be provided solely in the substrate, extend from the substrate to the epitaxial layers, or located solely in epitaxial layers. The dopants can be incorporated into the epitaxial layers by ion implantation alone, through epitaxial growth, or a combination of both. 2. P-type doping of GaN using magnesium (Mg) also exhibits memory effects, which precludes the formation of abrupt interfaces. The disclosed process and structure may enable development of Group III-N HEMTs with high voltage capability suitable for power switching with reduced drain lag effects. The disclosed process and structure may also lead to more compact device structures (due to optimized field shaping) that will lower costs. Additionally, with proper design, the disclosed structures can also be applied to high power RF devices for telecommunication and other applications. An important advantage is the minimization of device memory effects, which is a serious problem for telecommunication applications. FIG.1shows a cross-sectional view of an embodiment of a transistor according to the disclosure. In particular,FIG.1shows a cross-sectional view of a transistor100. The transistor100may include a substrate layer102. The substrate layer102may be made of Silicon Carbide (SiC). In some aspects, the substrate layer102may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and/or the like. In some aspects, the substrate layer102may be very lightly doped. In one aspect, the background impurity levels may be low. In one aspect, the background impurity levels may be 1E15/cm3or less. In one aspect, the substrate layer102may be formed of SiC selected from the group of 6H, 4H, 15R, 3C SiC, or the like, and the SiC is semi-insulating and doped with vanadium or any other suitable dopant or undoped of high purity with defects providing the semi-insulating properties. In another aspect, the substrate layer102may be GaAs, GaN, or other material suitable for the applications described herein. In another aspect, the substrate layer102may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting growth of Group III-nitride materials. Depending on the material of the substrate layer102, a nucleation layer136may be formed on the substrate layer102to reduce a lattice mismatch between the substrate layer102and a next layer in the transistor100. In one aspect, the nucleation layer136is formed directly on the substrate layer102. In other aspects, the nucleation layer136is formed on the substrate layer102with intervening layer(s), such as SiC epitaxial layer(s) formed on a SiC substrate layer102. The nucleation layer136may include different suitable materials, such as a Group III-Nitride material, e.g., AlxIny1-x-yGaN (where 0<=x<=1, 0<=y<=1, x+y<=1). The nucleation layer136may be formed on the substrate layer102using known semiconductor growth techniques such as Metal Oxide Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), or the like. In some embodiments, the nucleation layer is AlN or AlGaN, such as undoped AlN or AlGaN. In some embodiments, a buffer layer104is formed directly on the nucleation layer136or on the nucleation layer136with intervening layer(s). Depending on the embodiment, the buffer layer104may be formed of different suitable materials such as a Group III-nitride such as AlxGayIn(1-x-y)N (where 0<=x<=1, 0<=y<=1, x+y<=1), e.g., GaN, Aluminum Gallium Nitride (AlGaN), Aluminum Nitride (AlN), and the like, or another suitable material. In one aspect, the buffer layer104is formed of GaN. The buffer layer104or portions thereof may be doped with dopants, such as, Fe and/or C or alternatively can be wholly or partly undoped. In one aspect, the buffer layer104is directly on the substrate layer102. In one aspect, the buffer layer104may be high purity GaN. In one aspect, the buffer layer104may be high purity GaN that may be a low-doped n-type. In one aspect, the buffer layer104may also use a higher band gap Group III-nitride layer as a back barrier, such as an AlGaN back barrier, on the other side of the buffer layer104from the barrier layer108to achieve better electron confinement. In one aspect, the buffer layer104may have a buffer layer thickness defined as a distance between an upper surface of the substrate layer102and a lower surface of the barrier layer108. In one aspect, the buffer layer thickness may be less than 0.8 microns, less than 0.7 microns, less than 0.6 microns, less than 0.5 microns, or less than 0.4 microns. In one aspect, the buffer layer thickness may have a range of 0.8 microns to 0.6 microns, 0.7 microns to 0.5 microns, 0.6 microns to 0.4 microns, 0.5 microns to 0.3 microns, 0.4 microns to 0.2 microns, or 0.7 microns to 0.3 microns. In one aspect, the transistor100may have an intervening layer(s) thickness defined as a length between an upper surface of the substrate layer102and a lower surface of the barrier layer108. In one aspect, the intervening layer(s) thickness may be less than 0.8 microns, less than 0.7 microns, less than 0.6 microns, less than 0.5 microns, or less than 0.4 microns. In one aspect, the intervening layer(s) thickness may have a range of 0.8 microns to 0.6 microns, 0.7 microns to 0.5 microns, 0.6 microns to 0.4 microns, 0.5 microns to 0.3 microns, or 0.4 microns to 0.2 microns. A barrier layer108may be formed on the buffer layer104. In one aspect, the barrier layer108may be formed directly on the buffer layer104, and in other aspects, the barrier layer108is formed on the buffer layer104with intervening layer(s). Depending on the embodiment, the buffer layer104may be formed of different suitable materials such as a Group III-nitride such as AlxGayIn(1-x-y)N (where 0<=x<=1, 0<=y<=1, x+y<=1), e.g., AlGaN, AlN, or InAlGaN, or another suitable material. In one aspect, the barrier layer108may be AlGaN, and in another aspect the barrier layer108is AlN. In one aspect, the barrier layer108may be undoped. In one aspect, the barrier layer108may be doped. In one aspect, the barrier layer108may be an n-type material. In some aspects, the barrier layer108may have multiple layers of n-type material having different carrier concentrations. In one aspect, the barrier layer108may be a Group III-nitride or a combination thereof. In one aspect, a bandgap of the buffer layer104may be less than a bandgap of the barrier layer108to form a two-dimensional electron gas (2DEG) at a heterointerface152between the buffer layer104and barrier layer108when biased at an appropriate level. In one aspect, a bandgap of the buffer layer104that may be GaN may be less than a bandgap of the barrier layer108that may be AlGaN to form the two-dimensional electron gas (2DEG) at a heterointerface152between the buffer layer104and barrier layer108when biased at an appropriate level. In one aspect, a source110, a drain112and a gate114are formed on the barrier layer108. The source110, drain112, and/or gate114may be arranged directly on the barrier layer108or may be on intervening layer(s) on the barrier layer108, such as an AlGaN layer on an AlN barrier layer. Other or additional intervening layers are possible. For example, a spacer layer116of SiN, AlO, SiO, SiO2, AlN, or the like or combinations thereof can be provided on the barrier layer108or other intervening layers. In one aspect, the barrier layer108may include a region164under the source110and/or drain112that is a N+ material. In one aspect, the barrier layer108may include a region164under the source110and/or drain112that is Si doped. In one aspect, the n-type dopants in the region164are implanted. To protect and separate the gate114and the drain112, a spacer layer116may be arranged on the barrier layer108, on a side opposite the buffer layer104, adjacent the gate114, the drain112and the source110. The spacer layer116may be a passivation layer made of SiN, AlO, SiO, SiO2, AlN, or the like, or a combination incorporating multiple layers thereof. In one aspect, the spacer layer116is a passivation layer made of SiN. In one aspect, the spacer layer116can be deposited using MOCVD, plasma chemical vapor deposition (CVD), hot-filament CVD, or sputtering. In one aspect, the spacer layer116may include deposition of Si3N4. In one aspect, the spacer layer116forms an insulating layer. In one aspect, the spacer layer116forms an insulator. In one aspect, the spacer layer116may be a dielectric. In some embodiments, the gate114is deposited in a channel formed in the spacer layer116, and a T-gate is formed using semiconductor processing techniques understood by those of ordinary skill in the art. Other gate configurations are possible. In some embodiments, a second spacer layer117is formed on the first spacer layer116and the gate114, and a field plate132can be provided on the second spacer layer117. In other embodiments, for example, the first spacer layer116is formed on the barrier layer108and on the gate114. In such embodiments, a field plate132can be formed directly on the first spacer layer116. Other multiple field plate configurations are possible with the field plate132overlapping or non-overlapping with the gate114and/or multiple field plates132being used. In accordance with aspects of the present invention, a buried p-region or p-type material layer120is formed below the barrier layer108between the barrier layer108and the substrate layer102and/or within the substrate layer102. The p-type material region can be provided solely in the substrate layer102, extend from the substrate layer102to the epitaxial layers, or located solely in epitaxial layers. The dopants can be incorporated into the epitaxial layers by ion implantation alone, through epitaxial growth, or a combination of both. The p-type material layer120can span multiple layers and include multiple areas of different or graded p-doping. Depending on the embodiment, the p-type material layer120or portions thereof can extend from a p-type material contact118in a recess119formed in the transistor100and can extend up to or beyond the source110, up to or beyond the gate114, prior to the gate114, up to the gate114, and/or across the transistor100. In certain embodiments, the p-type material contact118is electrically connected to receive an external signal or bias. In certain embodiments, the source110is electrically connected to the p-type material layer120through a connection138. In certain embodiments, the field plate132is electrically connected to the source110through a connection140. In certain embodiments, the field plate132is connected to the source110, and the source110is connected to the p-type material layer120through a connection140, a connection138, or a single connection to both. In certain embodiments, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In certain embodiments, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In certain embodiments, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. In certain embodiments, the gate114is electrically connected to the p-type material layer120through a connection154. In accordance with aspects of the present invention, at least some portions of the substrate layer102may include a p-type material layer120. In accordance with aspects of the present invention, the p-type material layer120may be formed by ion implantation of aluminum (Al) and annealing. In other aspects, the p-type material layer120may be formed by ion implantation of boron, gallium, or any other material that may form a p-type layer or a combination of these. In one aspect, the p-type material layer120may be formed by implantation and annealing of Al prior to the growth of any GaN layers. In one aspect, the ion implementation may utilize channeling implants. In one aspect, the channeling implants may include aligning the ion beam to the substrate layer102. Alignment of the ion beam may result in increased implanting efficiency. Aspects of the disclosure are based on a realization that implant channeling can be used to controllably form implanted regions in silicon carbide that are highly uniform by depth and also result in reduced lattice damage. Channeling is experienced when ions are implanted along a crystal axis of a semiconductor. When a direction of implantation is close to a major axis of the crystal lattice, the atoms in the crystal lattice appear to “line up” relative to the direction of implantation, and the implanted ions appear to travel down the channels created by the crystal structure. This reduces the likelihood of collisions between the implanted ions and the atoms in the crystal lattice. As a result, the depth of the implant is greatly increased. In general, channeling occurs in silicon carbide when the direction of implantation is within about ±0.2° of a crystallographic axis of the silicon carbide crystal. In some aspects, the implantation may be greater than ±0.2° of the crystallographic axis of the silicon carbide crystal, however the implantation may be less effective. For example, when the direction of implantation is more than about ±0.2° of a crystallographic axis of the silicon carbide crystal, the atoms in the lattice may appear to be randomly distributed relative to the direction of implantation, which may reduce channeling effects. As used herein, the term “implant angle” refers to the angle between the direction of implantation and a crystallographic axis, such as the c-axis or <0001> axis, of the semiconductor layer into which ions are implanted. Thus, an implant angle of less than about 2° relative to the c-axis of a silicon carbide layer may be expected to result in channeling. However, other implant angles may be utilized as well. In one aspect, the p-type material layer120may be formed by ion implantation of27Al in 4H-SiC implanted with channeling conditions with an implant energy of E1=100 keV with a dose of 1E13 cm2at 25° C. In one aspect, the p-type material layer120may be formed by ion implantation of27Al in 4H-SiC implanted with channeling conditions with an implant energy of E2=300 keV with a dose of 1E13 cm2at 25° C. However, other implant energies and doses are contemplated as well. For example, in some aspects the implant energy may be 20 keV to 80 keV, 80 keV to 120 keV, 120 keV to 160 keV, 160 keV to 200 keV, 200 keV to 240 keV, 240 keV to 280 keV, 280 keV to 340 keV, 340 keV to 400 keV, 20 keV to 400 keV, and/or 80 keV to 340 keV; and in some aspects the implant dose may be 0.6E13 cm2to 0.8E13 cm2, 0.8E13 cm2to 1.2E13 cm2, 1.2E13 cm2to 1.6E13 cm2, 1.6E13 cm2to 2E13 cm2, 0.6E13 cm2to 2E13 cm2, and/or 0.8E13 cm2to 1.2E13 cm2. Additionally, it should be noted that the p-type material layer120may be formed by implantation of other materials such as Boron (B), Gallium (Ga), and/or the like, and may be followed by a high temperature anneal. In one aspect, the ion implantation may result in the p-type material layer120being a deep layer. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 1 μm or less. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.7 μm or less. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.5 μm or less. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.3 μm to 0.5 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.2 μm to 0.6 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.4 μm to 0.6 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.6 μm to 0.8 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.6 μm to 1.6 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.6 μm to 2.1 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 1 μm to 5 μm. In one aspect, the p-type material layer120implantation and/or doping may be in the range of 5E15 to 5E17 per cm3and extend to depths up to 5 μm. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.05% to 0.3% of a thickness of the substrate layer102. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.05% to 0.1% of a thickness of the substrate layer102. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.1% to 0.15% of a thickness of the substrate layer102. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.15% to 0.2% of a thickness of the substrate layer102. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.2% to 0.25% of a thickness of the substrate layer102. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 0.25% to 0.3% of a thickness of the substrate layer102. The p-type material layer120may be implanted within the substrate layer102and may be subsequently annealed. Annealing may allow for the implantation to be activated. In one aspect, a masking layer material may be utilized during implantation. In some aspects, during annealing of the p-type material layer120, a cap layer material may be used to cover the wafer surface to prevent dissociation of the substrate at high temperatures. Once the p-type material layer120has been formed, the masking layer material may be removed. Annealing may be performed at a temperature range of 1500-1850° C. for 5 minutes-30 minutes. Other annealing time and temperature profiles are contemplated as well. In some aspects, the substrate layer102may be made of a p-type material SiC substrate. Further in this aspect, the substrate layer102being a p-type material SiC substrate may be subsequently subjected to the processes as described herein including implantation of additional p-type layers. FIGS.2-34show different embodiments and aspects of the present invention with like reference numerals representing analogous parts in the various embodiments and figures. It should be understood that a feature described in one embodiment can be added to another embodiment or replace a feature in another embodiment. As shown inFIGS.2and3, the substrate layer102may include a p+ layer106. The p+ layer106may be used to reduce charging time constants and to achieve contact formation. In some aspects, the p+ layer106may also be formed by ion-implantation and annealing. The p+ layer106may be doped as highly as possible with minimum achievable sheet resistance. In some aspects, the p+ layer106may be present in a gate-source region. In some aspects, the p+ layer106may be present in a gate-source region and also partly under the gate114. In some aspects, the p+ layer106may be present in limited areas as described in further detail below. In some aspects, the p+ layer106may be under 0.6 μm in thickness. In some aspects, the p+ layer106may be under 0.5 μm in thickness. In some aspects, the p+ layer106may be under 0.4 μm in thickness. In some aspects, the p+ layer106may be under 0.3 μm in thickness. In some aspects, the p+ layer106may be under 0.2 μm in thickness. In some aspects, the p+ layer106may be between 0.1 and 0.6 μm in thickness. In some aspects, the p+ layer106may be between 0.5 and 0.6 μm in thickness. In some aspects, the p+ layer106may be between 0.4 and 0.5 μm in thickness. In some aspects, the p+ layer106may be between 0.3 and 0.4 μm in thickness. In some aspects, the p+ layer106may be between 0.2 and 0.3 μm in thickness. In some aspects, the p+ layer106may be between 0.1 and 0.3 μm in thickness. In some aspects, the p+ layer106may be between 0.05 and 0.25 μm in thickness. In some aspects, the p+ layer106may be between 0.15 and 0.25 μm in thickness. In one aspect, the source110may have a p-type material contact118on the p+ layer106. The p-type material contact118may be formed on the p+ layer106in a recess119provided in the buffer layer104and the barrier layer108. The p-type material contact118may be electrically coupled to the p+ layer106. The recess may extend down to the p+ layer106to allow for the p-type material contact118to be created there. The recess119may be formed by etching, and may also use a material to define the recess119. The material may be removed after the recess119has been created. In one aspect, the source110may have a p-type material contact118on the p-type material layer120. The p-type material contact118may be formed on the p-type material layer120in a recess119provided in the buffer layer104and the barrier layer108. The p-type material contact118may be electrically coupled to the p-type material layer120. The recess119may extend down to the p-type material layer120to allow for the p-type material contact118to be created there. The recess119may be formed by etching, and may also use a material to define the recess119. The material may be removed after the recess119has been created. In one aspect, the p-type material contact118may be formed in or on a layer of the transistor100in a recess119provided as indicated by a dashed boxes illustrated inFIG.1. In this aspect, the recess119may be configured as a partial recess, partial trench, or the like in a surface of the transistor100. In one aspect, a region or area under or adjacent the p-type material contact118may be implanted and/or doped with p-dopants to form an electrical connection with the p-type material layer120and/or the p+ layer106. In one aspect, the layer may be an epitaxial material on which is provided the p-type material contact118. In one aspect, a region or area under or adjacent the p-type material contact118may be implanted and/or doped during epitaxial growth of the layer or other layers with p-dopants to form an electrical connection with the p-type material layer120and/or a p+ layer106. Although not illustrated in the remaining figures, this aspect may be included in any aspect of the transistor100illustrated or described herein. In one aspect, the p-type material contact118may be formed in or on the buffer layer104in a recess119provided down to the buffer layer104as indicated by a lower dashed box illustrated inFIG.1. In this aspect, the recess119may be configured as a partial recess, partial trench, or the like in a surface of the transistor100. In one aspect, a region or area under or adjacent the p-type material contact118may be implanted and/or doped with p-dopants to form an electrical connection with the p-type material layer120and/or the p+ layer106. In one aspect, the buffer layer104may be an epitaxial material on which is provided the p-type material contact118. In one aspect, a region or area under or adjacent the p-type material contact118may be implanted and/or doped during epitaxial growth of the buffer layer104or other layers with p-dopants to form an electrical connection with the p-type material layer120and/or a p+ layer106. Although not illustrated in the remaining figures, this aspect may be included in any aspect of the transistor100illustrated or described herein. In one aspect, the p-type material contact118may be formed in or on the barrier layer108as indicated by an upper dashed box illustrated inFIG.1. In this aspect, a recess119may or may not be formed. If a recess119is formed, the recess119may be configured as a partial recess, partial trench, or the like in a surface of the transistor100. In one aspect, a region or area under or adjacent the p-type material contact118may be implanted and/or doped with p-dopants to form an electrical connection with the p-type material layer120and/or a p+ layer106. In one aspect, the barrier layer108may be an epitaxial material on which is provided the p-type material contact118. In one aspect, a region or area under or adjacent the p-type material contact118may be implanted and/or doped during epitaxial growth of the barrier layer108or other layers with p-dopants to form an electrical connection with the p-type material layer120and/or a p+ layer106. Although not illustrated in the remaining figures, this aspect may be included in any aspect of the transistor100illustrated or described herein. In one aspect, a spacer layer116may be provided on the barrier layer108. In one aspect, a second spacer layer117may be provided over the gate114and the first spacer layer116. In one aspect, the spacer layer116may include non-conducting material such as a dielectric. In one aspect, the spacer layer116may include a number of different layers of dielectrics or a combination of dielectric layers. In one aspect, the spacer layer116may be many different thicknesses, with a suitable range of thicknesses being approximately 0.05 to 2 microns. In one aspect, the spacer layer116may include a material such as a Group III nitride material having different Group III elements such as alloys of Al, Ga, or In, with a suitable spacer layer material being AlxInyGa1-x-y(where 0<=x<=1 and 0<=y<=1, x+y<=1). FIG.4shows a cross-sectional view of another aspect of a transistor according to the disclosure; andFIG.5shows a cross-sectional view of another aspect of a transistor according to the disclosure. As shown inFIG.4andFIG.5, an epitaxial layer202may be formed on the substrate layer102. In one aspect, an epitaxial layer202may be formed on the substrate layer102. In one aspect, an epitaxial layer202may be formed directly on the substrate layer102. In the aspects ofFIG.4andFIG.5, the p-type material layer120may be in the epitaxial layer202. In some aspects, the p-type material layer120may be in the epitaxial layer202in certain aspects where the substrate layer102includes GaAs, GaN, or the like substrate materials. In some aspects, the epitaxial layer202may be a Group III-nitride material. In some aspects, the epitaxial layer202may be more than one Group III-nitride material. In one aspect, the epitaxial layer202is formed of SiC. In some aspects, the p-type material layer120may be in the epitaxial layer202and may be SiC. In some aspects, the p-type material layer120may be in the epitaxial layer202and may be SiC and the p-type material layer120may include Al and/or Br. In some aspects, the p-type material layer120may be in the epitaxial layer202and may be SiC and the p-type material layer120may include implantation of Al and/or Br. In some aspects, the p-type material layer120may be in the epitaxial layer202. In some aspects, the p-type material layer120may be in the epitaxial layer202and may be GaN. In some aspects, the p-type material layer120may be in the epitaxial layer202and may be GaN and the p-type material layer120may include magnesium (Mg), carbon (C), and/or Zinc. In some aspects, the p-type material layer120may be in the epitaxial layer202and may be GaN and the p-type material layer120may include implantation of magnesium (Mg), carbon (C), and/or Zinc. In one aspect, the epitaxial layer202may be arranged on top of the substrate layer102. In one aspect, the epitaxial layer202may be arranged directly on top of the substrate layer102. In one aspect, the buffer layer104may be arranged on top of the epitaxial layer202. In one aspect, the buffer layer104may be arranged directly on top of the epitaxial layer202. In one aspect, the p-type material layer120may be implanted within the epitaxial layer202and may be subsequently annealed as described herein. Further in this aspect, the epitaxial layer202may be subsequently subjected to processes as described herein and may include formation and/or implantation of a p+ layer106. In one aspect, the epitaxial layer202may be arranged on top of the substrate layer102and the buffer layer104may be formed on the epitaxial layer202. In one aspect, the epitaxial layer202may be arranged on top of the substrate layer102and the buffer layer104may be formed directly on the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 10% to 20% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 20% to 30% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 30% to 40% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 40% to 50% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 50% to 60% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 60% to 70% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 70% to 80% of a thickness of the epitaxial layer202. In one aspect, the ion implantation may result in the p-type material layer120having a thickness of 80% to 90% of a thickness of the epitaxial layer202. In another aspect, the epitaxial layer202may utilize a p-type material and the epitaxial layer202may be arranged on top of the substrate layer102. In another aspect, the epitaxial layer202may utilize a p-type material and the epitaxial layer202may be arranged directly on top of the substrate layer102. In this regard, in certain aspects, a p-type material epitaxial layer202may be grown that results in an epitaxial layer202having the p-type material layer120and may not require implantation as described herein to form the p-type material layer120. Thereafter, the epitaxial layer202may be subsequently subjected to the processes including implantation of a p+ layer106as described herein. In some aspects, the epitaxial layer202may be formed by epitaxial growth utilizing off-axis oriented wafers. FIG.5shows a cross-sectional view of another aspect of a transistor according to the disclosure. In theFIG.5aspect, the epitaxial layer202may be formed with a p-type material and the epitaxial layer202may be arranged on top of the substrate layer102. In one aspect, the epitaxial layer202may be formed with a p-type material and the epitaxial layer202may be arranged directly on top of the substrate layer102. In this aspect, the entire epitaxial layer202may form the p-type material layer120. Thereafter, the epitaxial layer202may be subsequently subjected to the processes including implantation of a p+ layer106as described herein. In some aspects, the p-type material layer120may also be configured to have a varying doping and/or implantation profile perpendicular to the surface. In some aspects, the p-type material layer120may also be configured to have a varying profile perpendicular to the surface extending into the cross-sectional views of the Figures. The profile may be optimized to achieve desired breakdown voltage, device size, switching time, and the like. In one aspect, the p-type material layer120may be present uniformly under the transistor100for certain applications as shown inFIG.2,FIG.4, andFIG.6. In one aspect, the p-type material layer120may be present uniformly under the transistor100for power switching applications as shown inFIG.2,FIG.4, andFIG.6. In another aspect for certain applications, such as RF applications, the p-type material layer120may be located in limited areas such as in part of the gate-source region of the transistor100as illustrated inFIG.3andFIG.5and described in further detail below. In some aspects, part of the voltage from a drain112to a source110may be dropped in the p-type material layer120region. This may also deplete the channel in the lateral direction. The lateral depletion may reduce the lateral field and increase breakdown voltage. Alternatively, a more compact structure can be obtained for a required breakdown voltage. The p-type material layer120may eliminate the need to have C or Fe doping of the buffer needed to sustain the applied drain voltage. Elimination of C and Fe leads to decreased current reduction under operating conditions (no trapping). Moreover, in some aspects the p-type material layer120may support the field. In some aspects, the epitaxial layer202may include a p+ layer106as shown inFIG.4,FIG.5, andFIG.6. The p+ layer106may be used to reduce charging time constants and to achieve contact formation. In some aspects, the p+ layer106may also be formed by ion-implantation and annealing. The p+ layer106may be doped as highly as possible with minimum achievable sheet resistance. In some aspects, the p+ layer106may be present in a gate-source region. In some aspects, the p+ layer106may be present in a gate-source region and also partly under the gate114. In some aspects, the p+ layer106may be present in limited areas as described in further detail below. In some aspects, the p+ layer106may be under 0.3 μm in thickness. In some aspects, the p+ layer106may be under 0.2 μm in thickness. In some aspects, the p+ layer106may be between 0.1 and 0.3 μm in thickness. In some aspects, the p+ layer106may be between 0.05 and 0.25 μm in thickness. In some aspects, the p+ layer106may be between 0.15 and 0.25 μm in thickness. FIG.7shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.7illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, theFIG.7aspect illustrates that the buffer layer104may include an upper portion602of high purity GaN and the buffer layer104may also include a lower portion604that may form an AlGaN back barrier to achieve better electron confinement. In one aspect, the lower portion604that forms the back barrier may be AlGaN of n type. The back barrier construction may be implemented in any of the aspects of the disclosure. In aspects of the transistor100of the disclosure, the buffer layer104may be designed to be of the high purity type where the Fermi level is in the upper half of the bandgap, which minimizes slow trapping effects normally observed in GaN HEMTs. In this regard, the traps under the Fermi level are filled always and thus slow transients may be prevented. In some aspects, the buffer layer104may be as thin as possible consistent with achieving good crystalline quality. Applicants have already demonstrated 0.4 μm layers with good quality. In aspects of the transistor100of the disclosure, a AlxInyGa1-x-y(where 0<=x<=1 and 0<=y<=1, x+y<=1) nucleation layer136or buffer layer104may be grown on the substrate layer102via an epitaxial crystal growth method, such as MOCVD (Metalorganic Chemical Vapor Deposition), HVPE (Hydride Vapor Phase Epitaxy) or MBE (Molecular Beam Epitaxy). The formation of the nucleation layer136may depend on the material of the substrate layer102. In aspects of the transistor100of the disclosure, the buffer layer104may be formed with Lateral Epitaxial Overgrowth (LEO). LEO can, for example, improve the crystalline quality of GaN layers. When semiconductor layers of a HEMT are epitaxial, the layer upon which each epitaxial layer is grown may affect the characteristics of the device. For example, LEO may reduce dislocation density in epitaxial GaN layers. In aspects of the transistor100of the disclosure, implantation of the p-type material layer120may expand the entire length of the transistor100as shown inFIG.2,FIG.4, andFIG.6. In some aspects, implantation of the p-type material layer120may partially extend the length of the transistor100as shown inFIG.3andFIG.5. In aspects of the transistor100of the disclosure, the p-type material layer120may be neutralized to limit the length of the p-type material layer120. In one aspect, neutralizing may include implantation of impurities. In one aspect, neutralizing the p-type material layer120may include absorbing the charge of the p-type material layer120with a material of opposite polarity. Another way to limit the length of the p-type material layer120may be to etch the p-type material layer120. Another way to limit the length of the p-type material layer120may be to use a masking material to limit the area for implantation. In aspects of the transistor100of the disclosure, the p-type material layer120may be formed by growing the p-type material layer120. Growth may be epitaxial, for example. To limit the length of the p-type material layer120, the p-type material layer120may be etched or otherwise neutralized. In aspects of the transistor100of the disclosure, the substrate layer102may be etched and the p-type material layer120may be formed by growing the p-type material layer120. In one aspect, the growth may be epitaxial. In aspects of the transistor100of the disclosure, the p-type material layer120may be an epitaxial layer formed of SiC. In some aspects, the p-type material layer120may be an epitaxial layer and may be SiC and the p-type material layer120may include Al and/or Br. In some aspects, the p-type material layer120may be an epitaxial layer and may be SiC and the p-type material layer120may include implantation of Al and/or Br. In aspects of the transistor100of the disclosure, the p-type material layer120may be an epitaxial layer and may be GaN. In some aspects, the p-type material layer120may be an epitaxial layer and may be GaN and the p-type material layer120may include magnesium (Mg), carbon (C), and/or Zinc. In some aspects, the p-type material layer120may be an epitaxial layer and may be GaN and the p-type material layer120may include implantation of magnesium (Mg), carbon (C), and/or Zinc. In aspects of the transistor100of the disclosure, the substrate layer102may be etched and the p+ layer106may be formed by growing the p+ layer106. In one aspect, the growth may be epitaxial. In aspects of the transistor100of the disclosure, the p+ layer106may be an epitaxial layer formed of SiC. In some aspects, the p+ layer106may be an epitaxial layer and may be SiC and the p+ layer106may include Al and/or Br. In some aspects, the p+ layer106may be an epitaxial layer and may be SiC and the p+ layer106may include implantation of Al and/or Br. In aspects of the transistor100of the disclosure, the p+ layer106may be an epitaxial layer and may be GaN. In some aspects, the p+ layer106may be an epitaxial layer and may be GaN and the p+ layer106may include magnesium (Mg), carbon (C), and/or Zinc. In some aspects, the p+ layer106may be an epitaxial layer and may be GaN and the p+ layer106may include implantation of magnesium (Mg), carbon (C), and/or Zinc. In aspects of the transistor100of the disclosure, the substrate layer102may be silicon carbide and include a carbon face. In one aspect, the substrate layer102may be silicon carbide and include a carbon face arranged adjacent the buffer layer104. In one aspect, the substrate layer102may be silicon carbide and include a carbon face and the substrate layer102may be flipped so as to be arranged adjacent the buffer layer104. In this aspect, the buffer layer104may be GaN having a nitrogen face adjacent the carbon face of the substrate layer102. In one aspect, the buffer layer104may be GaN having alternating GaN and N layers with a N layer and/or a nitrogen face adjacent the carbon face of the substrate layer102. In aspects of the transistor100of the disclosure, the buffer layer104may include nonpolar GaN. In one aspect, the buffer layer104may include semipolar GaN. In one aspect, the buffer layer104may include hot wall epitaxy. In one aspect, the buffer layer104may include hot wall epitaxy having a thickness in the range of 0.15 microns to 0.25 microns, 0.2 microns to 0.3 microns, 0.25 microns to 0.35 microns, 0.3 microns to 0.35 microns, 0.35 microns to 0.4 microns, 0.4 microns to 0.45 microns, 0.45 microns to 0.5 microns, 0.5 microns to 0.55 microns, or 0.15 microns to 0.55 microns. The p-type material layer120may help avoid breakdowns and problems with material impurities. For example, without a p-type material layer120, the transistor100may need impurities, which do not discharge well. The p-type material layer120may be formed beneath the source110, and may extend toward the gate114of the device. In aspects of the transistor100of the disclosure, the p-type material layer120may extend the entire length and remain as shown inFIG.2,FIG.4, andFIG.6. In one aspect, the p-type material layer120may generally extend the entire length and remain as shown inFIGS.3and5. In another aspect of the disclosure, the p-type material layer120may not extend over the entire area of the transistor100as shown by the arrow LENGTH P120as shown inFIG.3andFIG.5. In this regard, the p-type material layer120may be selectively arranged as described herein, the p-type material layer120may be arranged over the entire length and selectively removed as described herein, the p-type material layer120may be arranged over the entire length and selectively electrically neutralized as described herein, or the like. Accordingly, the specific constructions of the p-type material layer120described below encompass any of these processes that result in the p-type material layer120having an operating construction and arrangement as noted below. In other words, the length and/or size of the p-type material layer120does not include a part that is partially electrically neutralized, partially etched, or the like. The length and/or size of the p-type material layer120may depend on the application of the transistor100, requirements for the transistor100, and the like. Limiting the p-type material layer120so that it does not extend beyond the gate114avoids adverse effects on RF performance for certain transistor applications. With reference to the aspects further described below, the p-type material layer120may extend horizontally parallel to the arrow LENGTH P120. Moreover, the p-type material layer120may extend horizontally parallel to the arrow LENGTH P120to a point defined by a line that is perpendicular to the arrow LENGTH P120and extends through a component of the transistor100as illustrated. In one aspect, of the disclosure, the p-type material layer120may extend laterally from at least beneath the source110toward a first edge124of the gate114as illustrated inFIG.3. In one aspect, of the disclosure, the p-type material layer120may extend laterally from at least beneath the source110to a position beneath a first edge124of the gate114. In certain aspects of the disclosure, the p-type material layer120may extend horizontally to a point within about 0 to about 0.7 μm of the first edge124of the gate114. In certain aspects of the disclosure, the p-type material layer120may extend horizontally to a point within about 0 to about 0.5 μm of the first edge124of the gate114. In certain aspects of the disclosure, the p-type material layer120may extend horizontally to a point within about 0 to about 0.3 μm of the first edge124of the gate114. In one aspect, of the disclosure, the p-type material layer120may extend horizontally from at least beneath the source110to a position beneath a second edge122of the gate114. In certain aspects of the disclosure, the p-type material layer120may extend horizontally to a point within about 0 to about 0.7 μm of the second edge122of the gate114. In certain aspects of the disclosure, the p-type material layer120may extend horizontally to a point within about 0 to about 0.5 μm of the second edge122of the gate114. In certain aspects of the disclosure, the p-type material layer120may extend horizontally to a point within about 0 to about 0.3 μm of the second edge122of the gate114. In other aspects, a length of the p-type material layer120LENGTH P120can be seen in relation to positions and/or lengths of other components as illustrated inFIG.3. A length SD may be the length between an edge142of the source110and an edge144of the drain112as shown inFIG.3by lines150. In one aspect, the length of the p-type material layer120may extend from 10% to 20% of the length of SD, meaning the p-type material layer120may extend 10% to 20% past the edge142of the source110toward the drain112. In one aspect, the length of the p-type material layer120may extend from 20% to 30% of the length of SD, meaning the p-type material layer120may extend 20% to 30% past the edge142of the source110toward the drain112. In one aspect, the length of the p-type material layer120may extend from 30% to 40% of the length of SD, meaning the p-type material layer120may extend 30% to 40% past the edge142of the source110toward the drain112. In one aspect, the length of the p-type material layer120may extend from 40% to 50% of the length of SD, meaning the p-type material layer120may extend 40% to 50% past the edge142of the source110toward the drain112. In one aspect, the length of the p-type material layer120may extend from 50% to 60% of the length of SD, meaning the p-type material layer120may extend 50% to 60% past the edge142of the source110toward the drain112. In one aspect, of the present disclosure, the p+ layer106may not extend over the entire area of the substrate layer102as shown by the arrow LENGTH P+106 as shown in the Figures. In this regard, the p+ layer106may be selectively arranged as described in detail below, the p+ layer106may be arranged over the entire length and selectively removed as described in detail below, the p+ layer106may be arranged over the entire length and selectively electrically neutralized as described in detail below, or the like. Accordingly, the specific constructions of the p+ layer106described below encompass any of these configurations that result in the p+ layer106having an operating construction and arrangement as noted below. In other words, the length and/or size of the p+ layer106does not include a part that is partially electrically neutralized or partially etched. The length and/or size of the p+ layer106may depend on the application of the transistor100, requirements for the transistor100, and the like. With reference to the aspects further described below, the p+ layer106may extend horizontally parallel to the arrow LENGTH P+106. Moreover, the p+ layer106may extend horizontally parallel to the arrow LENGTH P+106 to a point defined by a line that is perpendicular to the arrow LENGTH P+106 and extends through a component of the transistor100as illustrated. In certain aspects of the disclosure, the p+ layer106may extend to a point within about 0 to about 0.7 μm of the first edge124of the gate114. In certain aspects of the disclosure, the p+ layer106may extend to a point within about 0 to about 0.5 μm of the first edge124of the gate114. In certain aspects of the disclosure, the p+ layer106may extend to a point within about 0 to about 0.3 μm of the first edge124of the gate114. In one aspect, of the disclosure, the p+ layer106may extend laterally from at least beneath the source110to a position beneath a second edge122of the gate114. In certain aspects of the disclosure, the p+ layer106may extend to a point within about 0 to about 0.7 μm of the second edge122of the gate114. In certain aspects of the disclosure, the p+ layer106may extend to a point within about 0 to about 0.5 μm of the second edge122of the gate114. In certain aspects of the disclosure, the p+ layer106may extend to a point within about 0 to about 0.3 μm of the second edge122of the gate114. In other aspects, a length of the p+ layer106LENGTH P+106 can also be seen in relation to positions and/or lengths of other components based on the length SD as illustrated inFIG.3. The length SD in this case may be the length between an edge142of the source110toward an edge144of the drain112as shown inFIG.3. In one aspect, the length of the p+ layer106may extend from 10% to 20% of the length of SD, meaning the p+ layer106may extend 10% to 20% past the edge142of the source110toward the drain112. In one aspect, the length of the p+ layer106may extend from 20% to 30% of the length of SD, meaning the p+ layer106may extend 20% to 30% past the edge142of the source110toward the drain112. In one aspect, the length of the p+ layer106may extend from 30% to 40% of the length of SD, meaning the p+ layer106may extend 30% to 40% past the edge142of the source110toward the drain112. In one aspect, the length of the p+ layer106may extend from 40% to 50% of the length of SD, meaning the p+ layer106may extend 40% to 50% past the edge142of the source110toward the drain112. In one aspect, the length of the p+ layer106may extend from 50% to 60% of the length of SD, meaning the p+ layer106may extend 50% to 60% past the edge142of the source110toward the drain112. In one aspect, the length of the p+ layer106may extend from 60% to 70% of the length of SD, meaning the p+ layer106may extend 60% to 70% past the edge142of the source110toward the drain112. In one aspect, the length of the p+ layer106may extend from 70% to 80% of the length of SD, meaning the p+ layer106may extend 70% to 80% past the edge142of the source110toward the drain112. A gate contact may be provided for the gate114in between the source110and the drain112. Furthermore, in certain aspects of the disclosure, the gate contact may be disposed on the barrier layer108. In one aspect, the gate contact may be disposed directly on the barrier layer108. The gate114may be formed of platinum (Pt), nickel (Ni), and/or gold (Au), however, other metals known to one skilled in the art to achieve the Schottky effect, may be used. In one aspect, the gate114may include a Schottky gate contact that may have a three-layer structure. Such a structure may have advantages because of the high adhesion of some materials. In one aspect, the gate114may further include an overlayer of highly conductive metal. In one aspect, the gate114may be configured as a T-shaped gate. In another aspect, one or more metal overlayers may be provided on one or more of the source110, the p-type material contact118, the drain112, and the gate114. The overlayers may be Au, Silver (Ag), Al, Pt, Ti, Si, Ni, Al, and/or Copper (Cu). Other suitable highly conductive metals may also be used for the overlayers. In one or more aspects, the metal overlayer may electrically couple to the p-type material contact118. In another aspect, the source110, the p-type material contact118, the drain112, and the gate114may include Au, Silver (Ag), Al, Pt, Ti, Si, Ni, Al, and/or Copper (Cu). Other suitable highly conductive metals may also be used. FIG.8shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.8illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In theFIG.8aspect, the p-type material layer120may be formed in or on the substrate layer102and the transistor100may include a second buffer layer126. WhileFIG.8illustrates the transistor100with the first buffer layer104and the second buffer layer126, the transistor100may also use only one buffer layer104. In one aspect, to form the p-type material layer120in the substrate layer102, Al may be implanted in the substrate layer102and annealed. In one aspect, the substrate layer102may be doped with the p-type material layer120. In one aspect, the substrate layer102may be boron doped to form the p-type material layer120. Other materials are contemplated as well including Ga. The length of the p-type material layer120near the surface of the p-type material layer120can be limited using the techniques described in other aspects. In one aspect, the second buffer layer126may be deposited or grown on the first buffer layer104on a side of the first buffer layer104opposite of the substrate layer102. In one aspect, the second buffer layer126is formed directly on the first buffer layer104. In one aspect, the second buffer layer126may be a high-purity material such as Gallium Nitride (GaN), AlN, or the like. In one aspect, the second buffer layer126may be a high-purity GaN. In one aspect, the second buffer layer126may be a high-purity AlN. The second buffer layer126may be a p-type material or n-type material. In another aspect, the second buffer layer126may be undoped. In aspects of the transistor100of the disclosure, the contacts of the source110, the gate114, and/or the drain112may include Al, Ti, Si, Ni, and/or Pt. In some aspects, the p-type material contact118may include Al, Ti, Si, Ni, and/or Pt. In particular aspects, the material of the contacts of the source110, the gate114, and/or the drain112may be the same material as the p-type material contact118. In this aspect, utilizing the same material may be beneficial in that manufacturing may be easier, simplified, and/or less costly. In other aspects, the material of the contacts of the source110, the gate114, the drain112, and the p-type material contact118may be different. In aspects of the transistor100of the disclosure, the p+ layer106may be a graded layer. In one aspect, the p+ layer106may be a step-graded layer. In one aspect, the p+ layer106may be multiple layers. In one aspect, the p-type material layer120may be a graded layer. In one aspect, the p-type material layer120may be a step-graded layer. In one aspect, the p-type material layer120may be multiple layers. FIG.9shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.9illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, the transistor100ofFIG.9may include the p+ layer106(not shown inFIG.9) as described above. In other aspects, the transistor100ofFIG.9may not utilize the p+ layer106as shown inFIG.9. In one aspect ofFIG.9, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.9, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.9, the transistor100may be implemented with only the p-type material layer120. FIG.9further illustrates implementation of a field plate132. In one aspect, the field plate132may be arranged on the spacer layer117between the gate114and drain112. In one aspect, the field plate132may be deposited on the spacer layer117between the gate114and the drain112. In one aspect, the field plate132may be electrically connected to one or more other components in the transistor100. In one aspect, the field plate132may not be electrically connected to any other components of the transistor100. In some aspects, the field plate132may be adjacent the gate114and an additional spacer layer117of dielectric material may be included at least partially over the gate114to isolate the gate114from the field plate132. In some aspects, the field plate132may overlap the gate114and an additional spacer layer117of dielectric material may be included at least partially over the gate114to isolate the gate114from the field plate132. The field plate132may extend different distances from the edge of the gate114, with a suitable range of distances being approximately 0.1 to 2 microns. In some aspects, the field plate132may include many different conductive materials with a suitable material being a metal, or combinations of metals, deposited using standard metallization methods. In one aspect, the field plate132may include titanium, gold, nickel, titanium/gold, nickel/gold, or the like. In one aspect, the field plate132may be formed on the spacer layer117between the gate114and the drain112, with the field plate132being in proximity to the gate114but not overlapping the gate114. In one aspect, a space between the gate114and field plate132may be wide enough to isolate the gate114from the field plate132, while being small enough to maximize a field effect provided by the field plate132. In certain aspects, the field plate132may reduce a peak operating electric field in the transistor100. In certain aspects, the field plate132may reduce the peak operating electric field in the transistor100and may increase the breakdown voltage of the transistor100. In certain aspects, the field plate132may reduce the peak operating electric field in the transistor100and may reduce trapping in the transistor100. In certain aspects, the field plate132may reduce the peak operating electric field in the transistor100and may reduce leakage currents in the transistor100. In the embodiments of the disclosure, the heterointerface152may be between the barrier layer108and the buffer layer104. In one aspect, the source110and the drain112electrodes may be formed making ohmic contacts such that an electric current flows between the source110and the drain112electrodes via a two-dimensional electron gas (2DEG) induced at the heterointerface152between the buffer layer104and barrier layer108when a gate114electrode is biased at an appropriate level. In one aspect, the heterointerface152may be in the range of 0.005 μm to 0.007 μm, 0.007 μm to 0.009 μm, and 0.009 μm to 0.011 μm. FIG.10shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.10illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.10may include the p+ layer106(not shown inFIG.10) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.10, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.10, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.10, the transistor100may be implemented with only the p-type material layer120. In various aspects, use of buried p-layers, such as the p+ layer106and/or the p-type material layer120may be beneficial for the transistor100implemented as HEMTs for RF applications to obtain high breakdown voltage and good isolation between the input and output. However, in some applications, such as RF switch applications, the buried p-layer may not be connected to the source110as described herein. In this regard, a forward bias conduction between the p-layer (the p+ layer106and/or the p-type material layer120) and the drain112may cause a loss of input-output isolation when the transistor100is in the OFF condition. To avoid, minimize, and/or limit this problem, aspects illustrated inFIG.10of this disclosure may include connecting the buried p-layer (the p+ layer106and/or the p-type material layer120) to the gate114. In particular,FIG.10further illustrates that the p-type material contact118may be electrically connected to the gate114with a connection154(gate interconnect). In one aspect, the connection154may be formed on the spacer layer116and/or the spacer layer117to extend between the p-type material contact118and the gate114. In some aspects, the connection154may include a conductive material, many different conductive materials, a suitable material being a metal, or combinations of metals, deposited using standard metallization methods. In one aspect, the materials may include one or more of titanium, gold, nickel, or the like. In some aspects, the source110and the drain112may be symmetrical with respect to the gate114. In some switch device application aspects, the source110and the drain112may be symmetrical with respect to the gate114. An additional advantage of theFIG.10configuration may be that the p-layer may be used as a second gate, which allows use of multiple barrier layers108and/or multiple channel layers. In this regard, multiple barrier layers108and/or multiple channel layers may reduce the on-resistance of the transistor100, an important performance characteristic. In further aspects ofFIG.10, the reduced on-resistance may be obtained without significantly increasing an input-output capacitance, another important characteristic. In certain aspects, theFIG.10configuration may enable reduction of Ron-Coff product, an important figure-of-merit for RF switches. FIG.11shows a partial plan view of another aspect of a transistor according to the disclosure. In particular,FIG.11illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.11may be configured such that the p-layer may be provided with a separate contact162and may be configured to receive its own bias and signals. In this way, the p-layer can be used to modulate the characteristics of the transistor100. FIG.11further illustrates the transistor100including the source110, the gate114, and the drain112. In this regard, some of the various layers and components of the transistor100may not be shown for clarity of understanding. In one aspect ofFIG.11, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.11, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.11, the transistor100may be implemented with only the p-type material layer120. In each case, the p+ layer106and the p-type material layer120are shown with a dashed line indicative of the layer or layers being buried. In one aspect, the p-type material layer120may be provided with a contact pad162. In this aspect, the p-type material layer120through the contact pad162may receive its own bias and signals. In this regard, the p-type material layer120may be used to modulate characteristics of the transistor100. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In some aspects, the connection166may include a conductive material, many different conductive materials, a suitable material being a metal, or combinations of metals, deposited using standard metallization methods. In one aspect, the materials may include one or more of titanium, gold, nickel, or the like. In one aspect, the p+ layer106may be provided with a contact pad162. In this aspect, the p+ layer106through the contact pad162may receive its own bias and signals. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. In one aspect, the p+ layer106may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In one aspect, the connection166may be a metallic connection that extends from the p-type material contact118to the contact pad162. In one aspect, the contact pad162may be a buried contact pad. In this regard, the contact pad162may be buried in any one of the above-noted structures of the transistor100. In one aspect, the contact pad162may be arranged on the barrier layer108. In one aspect, the contact pad162may be arranged directly on the barrier layer108. In one aspect, the contact pad162may be arranged on a spacer layer116on the barrier layer108. In one aspect, the contact pad162may be separate and separated from the gate114, the source110, and/or the drain112.FIG.11further illustrates a gate pad168that is electrically connected to the gate114. It should be noted that the size, arrangement, and configuration of the p-type material contact118, the connection166, the contact pad162, the p+ layer106, the p-type material layer120, and the like illustrated inFIG.11is merely exemplary. Others sizes, arrangements, and configurations are contemplated as well. FIG.12shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.12illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.12may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.12, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.12, the transistor100may be implemented with the p+ layer106and the p-type material layer120(not shown inFIG.12). In one aspect ofFIG.12, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular, the transistor100ofFIG.12illustrates the field plate132connected to the source110through a connection140(source-field plate interconnect). In this aspect, the field plate132may not include a connection to the p-type material layer120. In one aspect, the connection140may be formed on the spacer layer116and/or the spacer layer117to extend between the field plate132and the source110. In one aspect, the connection140may be formed with the field plate132during the same manufacturing step. In one aspect, a plurality of the connections140may be used. In one aspect, a plurality of the field plates132may be used. In one aspect, a plurality of the field plates132may be used and each of the plurality of field plates132may be stacked with a dielectric material therebetween. In some aspects, the connection140may include a conductive material, many different conductive materials, a suitable material being a metal, or combinations of metals, deposited using standard metallization methods. In one aspect, the materials may include one or more of titanium, gold, nickel, or the like. FIG.13shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.13illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.13may include the p+ layer106(not shown inFIG.13) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.13, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.13, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.13, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular, the transistor100ofFIG.13illustrates the field plate132connected to the source110through a connection140.FIG.13further illustrates that the p-type material contact118may be electrically connected to the source110with a connection138. In one aspect, the connection138may be formed on a spacer layer116and/or the spacer layer117to extend between the p-type material contact118and the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. In some aspects, the connection138may include a conductive material, many different conductive materials, a suitable material being a metal or combinations of metals, deposited using standard metallization methods. In one aspect, the materials may include one or more of titanium, gold, nickel, or the like. FIG.14shows a process for making a transistor according to the disclosure. In particular,FIG.14shows an exemplary process500for making the transistor100of the disclosure. It should be noted that the process500is merely exemplary and may be modified consistent with the various aspects disclosed herein. The process500may begin at step502by forming a substrate layer102. The substrate layer102may be made of Silicon Carbide (SiC). In some aspects, the substrate layer102may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and/or the like. In some aspects, the substrate layer102may be very lightly doped. In one aspect, the background impurity levels may be low. In one aspect, the background impurity levels may be 1E15/cm3or less. The substrate layer102may be formed of SiC selected from the group of 6H, 4H, 15R, 3C SiC, or the like. In another aspect, the substrate layer102may be GaAs, GaN, or other material suitable for the applications described herein. In another aspect, the substrate layer102may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting growth of Group III-nitride materials. In a first aspect directed to the transistor100ofFIG.2andFIG.3, the process500may include a step504of implanting Al into the substrate layer102to form the p-type material layer120in the substrate layer102as shown, for example, inFIG.2andFIG.3. The p-type material layer120may be formed by ion implantation of Al and annealing. In one aspect, the p-type material layer120may be formed by implantation and annealing of Al prior to the growth of any GaN layers. In one aspect, the ion implementation may utilize channeling implants. In one aspect, the channeling implants may include aligning the ion beam to the substrate layer102. Alignment of the ion beam may result in increased implantation efficiency. In some aspects, the process500may further include implanting Al into the substrate layer102to form the p+ layer106in the substrate layer102as shown, for example, inFIG.2andFIG.3. Thereafter, the substrate layer102may be annealed as defined herein. In one aspect, the p-type material layer120may be formed by ion implantation of27Al in 4H—SiC implanted with channeling conditions with an implant energy of E1=100 keV with a dose of 1E13 cm2at 25° C. In one aspect, the p-type material layer120may be formed by ion implantation of27Al in 4H—SiC implanted with channeling conditions with an implant energy of E2=300 keV with a dose of 1E13 cm2at 25° C. However, other implant energies and doses are contemplated as well. In the first aspect directed to the transistor100ofFIG.3andFIG.4, the buffer layer104may be formed at step506on the substrate layer102. The buffer layer104may be grown or deposited on the substrate layer102. In one aspect, the buffer layer104may be GaN. In another aspect, the buffer layer104may be formed with LEO. In one aspect, a nucleation layer136may be formed on the substrate layer102and the buffer layer104may be formed at step506on the nucleation layer136. The buffer layer104may be grown or deposited on the nucleation layer136. In one aspect, the buffer layer104may be GaN. In another aspect, the buffer layer104may be formed with LEO. In a second aspect directed to the transistor100ofFIG.4andFIG.5, the process500may include, as a further part of the step504, forming the epitaxial layer202on the substrate layer102. Thereafter, the epitaxial layer202may be removed, etched, damaged, and/or the like to form the p-type material layer120in the epitaxial layer202as shown inFIG.3andFIG.4. Additionally, the p+ layer106may be formed as described herein. In the second aspect directed to the transistor100ofFIG.4andFIG.5, the buffer layer104may be formed at step506on the epitaxial layer202. The buffer layer104may be grown or deposited on the epitaxial layer202. In one aspect, the buffer layer104may be GaN. In another aspect, the buffer layer104may be formed with LEO. At step508, the barrier layer108may be formed on the buffer layer104. The barrier layer108may be an n-type conductivity layer or may be undoped. In one aspect, the barrier layer108may be AlGaN. At step510, the spacer layer116may be formed. The spacer layer116may be a passivation layer, such as SiN, AlO, SiO, SiO2, AlN, or the like, or a combination incorporating multiple layers thereof, which may be deposited over the exposed surface of the barrier layer108. In another aspect of the disclosure, to create a place for contact with the p-type material layer120, a recess may be created by removing at least part of the barrier layer108and at least part of the buffer layer104. The recess119may remove any material above the p-type material layer120within a portion of a region associated with the source110, exposing the p-type material layer120on a side opposite of the substrate layer102. In another aspect of the disclosure, to create a place for contact with the p+ layer106, a recess119may be created by removing at least part of the barrier layer108and at least part of the buffer layer104. The recess formation process may remove any material above the p+ layer106within a portion of a region associated with the source110, exposing the p+ layer106on a side opposite of the substrate layer102. Further during the process500as part of step512, the source110may be arranged on the barrier layer108. The source110may be an ohmic contact of a suitable material that may be annealed. For example, the source110may be annealed at a temperature of from about 500° C. to about 800° C. for about 2 minutes. However, other times and temperatures may also be utilized. Times from about 30 seconds to about 10 minutes may be, for example, acceptable. In some aspects, the source110may include Al, Ti, Si, Ni, and/or Pt. In one aspect, a region164under the source110that is a N+ material may be formed in the barrier layer108. In one aspect, a region164under the drain112may be Si doped. Further during the process500as part of step512, the drain112may be arranged on the barrier layer108. Like the source110, the drain112may be an ohmic contact of Ni or another suitable material, and may also be annealed in a similar fashion. In one aspect, an n+ implant may be used in conjunction with the barrier layer108and the contacts are made to the implant. In one aspect, a region164under the drain112that is a N+ material may be formed in the barrier layer108. In one aspect, a region164under the drain112may be Si doped. Further during the process500as part of step512, the gate114may be arranged on the barrier layer108between the source110and the drain112. A layer of Ni, Pt, AU, or the like may be formed for the gate114by evaporative deposition or another technique. The gate structure may then be completed by deposition of Pt and Au, or other suitable materials. In some aspects, the contacts of the gate114may include Al, Ti, Si, Ni, and/or Pt. Further during the process500as part of step512, the p-type material contact118may be formed. Once the p+ layer106is exposed, nickel or another suitable material may be evaporated to deposit the p-type material contact118. The nickel or another suitable material may be annealed to form an ohmic contact, for example. In some aspects, the contacts of the p-type material contact118may include Al, Ti, Si, Ni, and/or Pt. Such a deposition and annealing process may be carried out utilizing conventional techniques known to those of skill in the art. For example, an ohmic contact for the p-type material contact118may be annealed at a temperature of from about 600° C. to about 1050° C. Once the p-type material contact118has been formed on the p+ layer106, a metal overlayer may electrically couple the p-type material contact118of the p+ layer106to the source110. Doing this may maintain the conductivity of the p+ layer106and the source110at the same potential. The source110and the drain112electrodes may be formed making ohmic contacts such that an electric current flows between the source110and drain112electrodes via a two-dimensional electron gas (2DEG) induced at the hetero interface152between the buffer layer104and barrier layer108when a gate114electrode is biased at an appropriate level. In one aspect, the heterointerface152may be in the range of 0.005 μm to 0.007 μm, 0.007 μm to 0.009 μm, and 0.009 μm to 0.011 μm. The gate114may extend on top of a spacer or the spacer layer116. The spacer layer116may be etched and the gate114deposited such that the bottom of the gate114is on the surface of barrier layer108. The metal forming the gate114may be patterned to extend across spacer layer116so that the top of the gate114forms a field plate132. Further during some aspects of the process500as part of step512, a field plate132may be arranged on top of another spacer layer117and may be separated from the gate114. In one aspect, the field plate132may be deposited on the spacer layer117between the gate114and the drain112. In some aspects, the field plate132may include many different conductive materials with a suitable material being a metal, or combinations of metals, deposited using standard metallization methods. In one aspect, the field plate132may include titanium, gold, nickel, titanium/gold, nickel/gold, or the like. In one aspect, the connection140may be formed with the field plate132during the same manufacturing step (seeFIG.12). In one aspect, a plurality of the field plates132may be used. In one aspect, a plurality of the field plates132may be used and each of the plurality of field plates132may be stacked with a dielectric material therebetween. In one aspect, the field plate132extends toward the edge of gate114towards the drain112. In one aspect, the field plate132extends towards the source110. In one aspect, the field plate132extends towards the drain112and towards the source110. In another aspect, the field plate132does not extend toward the edge of gate114. Finally, the structure may be covered with a dielectric spacer layer such as silicon nitride. The dielectric spacer layer may also be implemented similar to the spacer layer116. Moreover, it should be noted that the cross-sectional shape of the gate114, shown in the Figures is exemplary. For example, the cross-sectional shape of the gate114in some aspects may not include the T-shaped extensions. Other constructions of the gate114may be utilized, for example, the construction of the gate114illustrated inFIG.8orFIG.1. Further during some aspects of the process500as part of step512, the connection154may be formed. In one aspect, the connection154may be formed to extend between the p-type material contact118and the gate114(seeFIG.16). In one aspect, the connection154may be formed on the spacer layer116to extend between the p-type material contact118and the gate114. Further during some aspects of the process500as part of step512, the connection140may be formed (seeFIG.13). In some aspects, the field plate132may be electrically connected to the source110with the connection140. In one aspect, the connection140may be formed on the spacer layer117to extend between the field plate132and the source110. Further during some aspects of the process500as part of step512, the connection166and the contact pad162may be formed (seeFIG.11). In one aspect, the p-type material contact118may be electrically connected to the connection166that may be electrically connected to a contact pad162. Further during some aspects of the process500, the gate pad168may be formed. It should be noted that the steps of process500may be performed in a different order consistent with the aspects described above. Moreover, the process500may be modified to have more or fewer process steps consistent with the various aspects disclosed herein. In one aspect of the process500, the transistor100may be implemented with only the p+ layer106. In one aspect of the process500, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect of the process500, the transistor100may be implemented with only the p-type material layer120. FIG.15illustrates a distribution of Al implanted with channeling conditions according to aspects of the disclosure in comparison to simulations for conventional implant conditions. In particular,FIG.15illustrates a distribution of27Al in 4H-SiC implanted with channeling conditions along C-axis (secondary ion mass spectrometry (SIMS) data) in comparison with simulations for conventional implant conditions (TRIM) off axis. The implant energy utilized was E1=100 keV and E2=300 keV with a dose of 1E13 cm−2at 25° C. In this regard, the p-type material layer120may be implanted consistent with this implant energy and dose. However, other implant energies and doses are contemplated as well as described herein. In one aspect, the p-type material layer120may have a doping concentration less than the p+ layer106. In one aspect, p+ layer106may be doped as highly as possible with minimum achievable sheet resistance. In one aspect, the p-type material layer120may have an implantation concentration less than the p+ layer106. In one aspect, p+ layer106may have an implantation concentration as high as possible with minimum achievable sheet resistance. In one aspect, the p-type material layer120may have an implantation concentration less than 1019. In one aspect, the p-type material layer120may have an implantation concentration less than 1020. In one aspect, the p-type material layer120may have an implantation concentration of 1017-1020, 1019-1020, 1018-1019, or 1017-1018. In one aspect, the p+ layer106may have an implantation concentration 1019or greater. In one aspect, the p+ layer106may have an implantation concentration of 1018-1020, 1018-1019, or 1019-1020. In one aspect, the p-type material layer120doping may be less than 1E17 cm3. In one aspect, the p-type material layer120doping may be less than 2E17 cm3. In one aspect, the p-type material layer120doping may be less than 6E17 cm3. In one aspect, the p-type material layer120doping may be less than 2E18 cm3. In one aspect, the p-type material layer120doping may be in the range of 5E15 to 5E17 per cm3. In these aspects, the p+ layer106doping concentration may be greater than a doping concentration of the p-type material layer120. FIG.16shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.16illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.16may include the p+ layer106(not shown inFIG.16) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.16, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.16, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.16, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.16illustrates a transistor100that may include a gate114as well as a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. In one aspect, the gate114may be a T-shaped gate. In one aspect, the gate114may be a non-T shaped gate. FIG.17shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.17illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.17may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.17, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.17, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.17, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.17illustrates a transistor100that may include a p+ layer106in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102. In one aspect, the transistor100may include a p+ layer106in the epitaxial layer202. In one aspect, the transistor100may include a p-type material layer120in the epitaxial layer202. In one aspect, a transistor100may include a p+ layer106in the substrate layer102, a p-type material layer120in the substrate layer102, a p+ layer106in the epitaxial layer202, and a p-type material layer120in the epitaxial layer202.FIG.17further illustrates that the transistor100may include a field plate132 FIG.18shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.18illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.18may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.18, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.18, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.18, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.18illustrates that the transistor100may include a field plate132. In one aspect, the transistor100may further include a connection140to connect the field plate132to the source110. In one aspect, the transistor100may further include a connection138to connect the field plate132and/or the source110to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. FIG.19shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.19illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.19may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.19, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.19, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.19, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.19illustrates a transistor100that may include a p-type material layer120in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the epitaxial layer202. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102and may include a p-type material layer120in the epitaxial layer202. In one aspect ofFIG.19, the transistor100may include a field plate132. In one aspect, the transistor100may further include a connection140to connect the field plate132to the source110. In one aspect, the transistor100may further include a connection138(source interconnect) to connect the field plate132and/or the source110to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. FIG.20shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.20illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.20may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.20, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.20, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.20, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.20illustrates a transistor100that may include a p+ layer106in an epitaxial layer202.FIG.20further illustrates that the transistor100may include a p-type material layer120in the epitaxial layer202. In one aspect ofFIG.20, the transistor100may include a field plate132. In one aspect, the transistor100may further include a connection140to connect the field plate132to the source110. In one aspect, the transistor100may further include a connection138(source interconnect) to connect the field plate132and/or the source110to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. FIG.21shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.21illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.21may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.21, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.21, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.21, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.21illustrates a transistor100that may include a p-type material layer120in the substrate layer102. In one aspect as illustrated inFIG.21, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the gate114may be a non-T shaped gate. In one aspect ofFIG.21, the transistor100may include a field plate132. In one aspect, the transistor100may further include a connection140to connect the field plate132to the source110. In one aspect, the transistor100may further include a connection138to connect the field plate132and/or the source110to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. FIG.22shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.22illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.22may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.22, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.22, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.22, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.22illustrates a transistor100that may include a p-type material layer120in the substrate layer102. In one aspect as illustrated in FIG.22, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the gate114may be a non-T shaped gate. In one aspect, the transistor100may include a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. FIG.23shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.23illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.23may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.23, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.23, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.23, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.23illustrates a transistor100that may include a p-type material layer120in the epitaxial layer202. In one aspect as illustrated inFIG.23, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the transistor100may include a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. FIG.24shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.24illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.24may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.24, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.24, the transistor100may be implemented with the p+ layer106and the p-type material layer120(not shown). In one aspect ofFIG.24, the transistor100may be implemented with only the p-type material layer120(not shown). In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.24illustrates a transistor100that may include a p+ layer106in the epitaxial layer202. In one aspect as illustrated inFIG.24, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the gate114may be a non-T shaped gate. In one aspect, the transistor100may include a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. FIG.25shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.25illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.25may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.25, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.25, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.25, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.25illustrates a transistor100that may include a p-type material layer120in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the epitaxial layer202. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102and may include a p-type material layer120in the epitaxial layer202. In one aspect as illustrated inFIG.25, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the transistor100may include a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. FIG.26shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.26illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.26may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.26, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.26, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.26, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.26illustrates a transistor100that may include a p+ layer106in an epitaxial layer202.FIG.26further illustrates that the transistor100may include a p-type material layer120in the epitaxial layer202. In one aspect, a transistor100may include a p+ layer106in an epitaxial layer202and may include a p-type material layer120in the epitaxial layer202. In one aspect as illustrated inFIG.26, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the transistor100may include a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. FIG.27shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.27illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.27may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.27, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.27, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.27, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.27illustrates a transistor100that may include a p+ layer106in an epitaxial layer202.FIG.27further illustrates that the transistor100may include a p-type material layer120in the epitaxial layer202. In one aspect, a transistor100may include a p+ layer106in an epitaxial layer202and a p-type material layer120in the epitaxial layer202. In one aspect as illustrated inFIG.27, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the transistor100may include a connection154. In one aspect, the connection154may connect the gate114to the p-type material contact118. In one aspect as illustrated inFIG.27, the transistor100may further include a field plate132. FIG.28shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.28illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.28may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.28, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.28, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.28, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.28illustrates a transistor100that may include a p-type material layer120in the epitaxial layer202. In one aspect as illustrated inFIG.28, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.29shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.29illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.29may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.29, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.29, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.29, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In one aspect as illustrated inFIG.29, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the gate114may be a non-T shaped gate. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.30shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.30illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.30may include the p+ layer106(not shown) as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.30, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.30, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.30, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.30illustrates a transistor100that may include a p-type material layer120in the substrate layer102and may include a p-type material layer120in the epitaxial layer202. In one aspect as illustrated inFIG.30, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.31shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.31illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.31may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.31, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.31, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.31, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.31illustrates a transistor100that may include a p+ layer106in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102. In one aspect, a transistor100may include a p+ layer106in the substrate layer102and may include a p-type material layer120in the substrate layer102. In one aspect as illustrated inFIG.31, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. In one aspect, the p+ layer106may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.32shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.32illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.32may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.32, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.32, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.32, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.32illustrates a transistor100that may include a p+ layer106in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102. In one aspect, a transistor100may include a p+ layer106in the substrate layer102and may include a p-type material layer120in the substrate layer102. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. In one aspect, the transistor100may include a field plate132. In one aspect, the p+ layer106may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.33shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.33illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.33may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.33, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.33, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.33, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.33illustrates a transistor100that may include a p+ layer106in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102. In one aspect, a transistor100may include a p+ layer106in the substrate layer102and may include a p-type material layer120in the substrate layer102. In one aspect, the transistor100may include a field plate132adjacent the gate114. In one aspect, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. In one aspect, the p+ layer106may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.34shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.34illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.34may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.34, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.34, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.34, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.34illustrates a transistor100that may include a p+ layer106in the substrate layer102. In one aspect, the transistor100may include a p-type material layer120in the substrate layer102. In one aspect, a transistor100may include a p+ layer106in the substrate layer102and may include a p-type material layer120in the substrate layer102. In one aspect, the transistor100may include a field plate132. In one aspect, the transistor100may include a gate114having a T-shaped cross section. In one aspect, the gate114may be a non-T shaped gate. In one aspect, the transistor100may further include a connection140to connect the field plate132to the source110. In one aspect, the p-type material layer120may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. In one aspect, the transistor100may further include a connection138to connect the field plate132and/or the source110to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without connecting to the source110. In one aspect, the transistor100may further include a connection138and a connection140configured to connect the field plate132directly to the p-type material contact118without any intervening connections. In one aspect, the p+ layer106may be provided with the p-type material contact118. The p-type material contact118may be electrically connected to a connection166that may be electrically connected to a contact pad162. In this regard, the contact pad162may be used to modulate characteristics of the transistor100. FIG.35shows a cross-sectional view of another aspect of a transistor according to the disclosure. In particular,FIG.35illustrates a transistor100that may include any one or more aspects of the disclosure described herein. In particular, in some aspects the transistor100ofFIG.35may include the p+ layer106as described above. Other aspects may not utilize the p+ layer106. In one aspect ofFIG.35, the transistor100may be implemented with only the p+ layer106. In one aspect ofFIG.35, the transistor100may be implemented with the p+ layer106and the p-type material layer120. In one aspect ofFIG.35, the transistor100may be implemented with only the p-type material layer120. In aspects that utilize the p-type material layer120, the p-type material layer120may be implanted as described herein. In aspects that utilize the p-type material layer120, the p-type material layer120may be formed as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be implanted as described herein. In aspects that utilize the p+ layer106, the p+ layer106may be formed as described herein. In particular,FIG.35illustrates a transistor100that may be implemented without the p-type material contact118. In this regard, the transistor100ofFIG.35together with the p-type material layer120and/or the p+ layer106may also reduce drain lag effect compared to a transistor without such p-layers. Accordingly, the disclosure has set forth a simpler alternative solution to forming p-type layers in HEMTs. The disclosed structure can be readily fabricated with currently available techniques. Moreover, the disclosed use of a high-purity material minimizes drain lag effects. Additionally, the disclosed p-type material layer provides a retarding electric field to obtain good electron confinement with low leakage. Additionally, aspects of this disclosure have described in detail variations of transistors with p-type layers and the ways those p-type layers are formed. The disclosed transistors maximize RF power, allow for efficient discharge, and maximize breakdowns. According to further aspects of this disclosure, transistors, such as GaN HEMTs, fabricated on high resistivity substrates may be utilized for high power RF (radio frequency) amplifiers, for high power radiofrequency (RF) applications, and also for low frequency high power switching applications. The advantageous electronic and thermal properties of GaN HEMTs also make them very attractive for switching high power RF signals. In this regard, the disclosure has described a structure with a buried p-layer under the source region to obtain high breakdown voltage in HEMTs for various applications including power amplifiers while at the same time eliminating drifts in device characteristics arising from trapping in the buffer and/or semi-insulating substrates. Use of buried p-layers may also be important in HEMTs for RF switches to obtain high breakdown voltage and good isolation between the input and output. EXAMPLES Example 1. An apparatus, comprising: a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer. Example 2. The apparatus of Example 1, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 3. The apparatus of Example 2, wherein the p-region is implanted. Example 4. The apparatus of Example 2, wherein the p-region comprises at least two p-regions. Example 5. The apparatus of Example 1, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 6. The apparatus of Example 5, wherein the p-region is implanted. Example 7. The apparatus of Example 5, wherein the p-region comprises at least two p-regions. Example 8. The apparatus of Example 1, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 9. The apparatus of Example 8, wherein the p-region is implanted in the epitaxial layer. Example 10. The apparatus of Example 8, wherein the p-region comprises at least two p-regions in the epitaxial layer. Example 11. The apparatus of Example 8, wherein the epitaxial layer is below the group III-Nitride barrier layer. Example 12. The apparatus of Example 1, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 13. The apparatus of Example 12, wherein at least one of the p-regions in implanted. Example 14. The apparatus of Example 12, wherein the p-region comprises at least two p-regions. Example 15. The apparatus of Example 1, wherein the p-region is on the substrate below said group III-Nitride barrier layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 16. The apparatus of Example 15, wherein at least one of the p-regions is implanted. Example 17. The apparatus of Example 15, wherein the p-region comprises at least two p-regions. Example 18. The apparatus of Example 1, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate. Example 19. The apparatus of Example 18, wherein the field plate is electrically coupled to said p-region. Example 20. The apparatus of Example 18, wherein the field plate is electrically coupled to the source. Example 21. The apparatus of Example 18, wherein the field plate is electrically coupled to the source and said p-region. Example 22. The apparatus of Example 21, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 23. The apparatus of Example 22, wherein the p-region is implanted. Example 24. The apparatus of Example 22, wherein the p-region comprises at least two p-regions. Example 25. The apparatus of Example 21, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 26. The apparatus of Example 25, wherein the p-region is implanted. Example 27. The apparatus of Example 25, wherein the p-region comprises at least two p-regions. Example 28. The apparatus of Example 21, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 29. The apparatus of Example 28, wherein the p-region is implanted in the epitaxial layer. Example 30. The apparatus of Example 28, wherein the p-region comprises at least two p-regions in the epitaxial layer. Example 31. The apparatus of Example 28, wherein the epitaxial layer is below the group III-Nitride barrier layer. Example 32. The apparatus of Example 21, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 33. The apparatus of Example 32, wherein at least one of the p-regions in implanted. Example 34. The apparatus of Example 32, wherein the p-region comprises at least two p-regions. Example 35. The apparatus of Example 21, wherein the p-region is on the substrate below said group III-Nitride barrier layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 36. The apparatus of Example 35, wherein at least one of the p-regions is implanted. Example 37. The apparatus of Example 35, wherein the p-region comprises at least two p-regions. Example 38. The apparatus of Example 1, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate. Example 39. The apparatus of Example 1, wherein the gate comprises a T-shaped cross-section. Example 40. The apparatus of Example 39, wherein the gate is electrically coupled to the p-region. Example 41. The apparatus of Example 39, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 42. The apparatus of Example 41, wherein the p-region is implanted. Example 43. The apparatus of Example 41, wherein the p-region comprises at least two p-regions. Example 44. The apparatus of Example 39, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 45. The apparatus of Example 44, wherein the p-region is implanted. Example 46. The apparatus of Example 44, wherein the p-region comprises at least two p-regions. Example 47. The apparatus of Example 39, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 48. The apparatus of Example 47, wherein the p-region is implanted in the epitaxial layer. Example 49. The apparatus of Example 47, wherein the p-region comprises at least two p-regions in the epitaxial layer. Example 50. The apparatus of Example 47, wherein the epitaxial layer is below the group III-Nitride barrier layer. Example 51. The apparatus of Example 39, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 52. The apparatus of Example 51, wherein at least one of the p-regions in implanted. Example 53. The apparatus of Example 51, wherein the p-region comprises at least two p-regions. Example 54. The apparatus of Example 39, wherein the p-region is on the substrate below said group III-Nitride barrier layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 55. The apparatus of Example 54, wherein at least one of the p-regions is implanted. Example 56. The apparatus of Example 54, wherein the p-region comprises at least two p-regions. Example 57. The apparatus of Example 39, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate. Example 58. The apparatus of Example 1, wherein the source is electrically coupled to said p-region. Example 59. The apparatus of Example 58, further comprising a connection configured to couple the source to said p-region. Example 60. The apparatus of Example 59, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 61. The apparatus of Example 60, wherein the p-region is implanted. Example 62. The apparatus of Example 60, wherein the p-region comprises at least two p-regions. Example 63. The apparatus of Example 59, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 64. The apparatus of Example 63, wherein the p-region is implanted. Example 65. The apparatus of Example 63, wherein the p-region comprises at least two p-regions. Example 66. The apparatus of Example 59, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 67. The apparatus of Example 66, wherein the p-region is implanted in the epitaxial layer. Example 68. The apparatus of Example 66, wherein the p-region comprises at least two p-regions in the epitaxial layer. Example 69. The apparatus of Example 66, wherein the epitaxial layer is below the group III-Nitride barrier layer. Example 70. The apparatus of Example 59, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 71. The apparatus of Example 70, wherein at least one of the p-regions in implanted. Example 72. The apparatus of Example 70, wherein the p-region comprises at least two p-regions. Example 73. The apparatus of Example 59, wherein the p-region is on the substrate below said group III-Nitride barrier layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 74. The apparatus of Example 73, wherein at least one of the p-regions is implanted. Example 75. The apparatus of Example 73, wherein the p-region comprises at least two p-regions. Example 76. The apparatus of Example 59, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate. Example 77. The apparatus of Example 1, further comprising a contact pad electrically coupled to said p-region. Example 78. The apparatus of Example 77, further comprising a connection connecting the contact pad electrically to said p-region. Example 79. The apparatus of Example 77, wherein the contact pad is configured to receive at least one of the following: bias and signals. Example 80. The apparatus of Example 77, wherein the contact pad is configured to receive at least one of the following: bias to modulate characteristics of the apparatus and signals to modulate characteristics of the apparatus. Example 81. The apparatus of Example 80, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 82. The apparatus of Example 81, wherein the p-region is implanted. Example 83. The apparatus of Example 81, wherein the p-region comprises at least two p-regions. Example 84. The apparatus of Example 80, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 85. The apparatus of Example 84, wherein the p-region is implanted. Example 86. The apparatus of Example 84, wherein the p-region comprises at least two p-regions. Example 87. The apparatus of Example 80, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 88. The apparatus of Example 87, wherein the p-region is implanted in the epitaxial layer. Example 89. The apparatus of Example 87, wherein the p-region comprises at least two p-regions in the epitaxial layer. Example 90. The apparatus of Example 87, wherein the epitaxial layer is below the group III-Nitride barrier layer. Example 91. The apparatus of Example 80, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 92. The apparatus of Example 91, wherein at least one of the p-regions in implanted. Example 93. The apparatus of Example 91, wherein the p-region comprises at least two p-regions. Example 94. The apparatus of Example 80, wherein the p-region is on the substrate below said group III-Nitride barrier layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 95. The apparatus of Example 94, wherein at least one of the p-regions is implanted. Example 96. The apparatus of Example 94, wherein the p-region comprises at least two p-regions. Example 97. The apparatus of Example 80, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate. Example 98. The apparatus of Example 1, further comprising a nucleation layer on the substrate, wherein the group III-Nitride buffer layer is on the nucleation layer. Example 99. The apparatus of Example 98, further comprising intervening layers between the nucleation layer and the group III-Nitride buffer layer. Example 100. The apparatus of Example 1, wherein a length of the p-region being less than an entire length of the substrate. Example 101. The apparatus of Example 1, wherein the p-region is provided in the substrate; and wherein the p-region comprises aluminum implanted in the substrate. Example 102. The apparatus of Example 1, wherein the p-region is provided in a layer arranged on the substrate; wherein the layer is an epitaxial layer; and wherein the layer is at least one of the following: GaN or SiC. Example 103. The apparatus of Example 1, wherein a thickness of the group III-Nitride buffer layer defined as a distance between an upper surface of the substrate and a lower surface of the group III-Nitride barrier layer has a range of 0.7 microns to 0.3 microns. Example 104. The apparatus of Example 1, wherein a thickness of one or more layers between an upper surface of the substrate and a lower surface of the group III-Nitride barrier layer has a range of 0.7 microns to 0.3 microns. Example 105. An apparatus, comprising: a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer; and a contact pad electrically coupled to said p-region. Example 106. The apparatus of Example 105, further comprising a connection connecting the contact pad electrically to said p-region. Example 107. The apparatus of Example 105, wherein the contact pad is configured to receive at least one of the following: bias and signals. Example 108. The apparatus of Example 105, wherein the contact pad is configured to receive at least one of the following: bias to modulate characteristics of the apparatus and signals to modulate characteristics of the apparatus. Example 109. The apparatus of Example 105, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 110. The apparatus of Example 109, wherein the p-region is implanted. Example 111. The apparatus of Example 105, wherein the p-region comprises at least two p-regions. Example 112. The apparatus of Example 105, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 113. An apparatus, comprising: a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer, wherein the gate is electrically coupled to the p-region. Example 114. The apparatus of Example 113, further comprising a connection connecting the gate electrically to said p-region. Example 115. The apparatus of Example 113, wherein the p-region is on the substrate below said group III-Nitride barrier layer. Example 116. The apparatus of Example 115, wherein the p-region is implanted. Example 117. The apparatus of Example 113, wherein the p-region comprises at least two p-regions. Example 118. The apparatus of Example 113, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 119. The apparatus of Example 118, wherein the p-region is implanted. Example 120. The apparatus of Example 118, wherein the p-region comprises at least two p-regions. Example 121. The apparatus of Example 113, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 122. A method of making a device comprising: providing a substrate; providing a group III-Nitride buffer layer on the substrate; providing a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer; electrically coupling a source to the group III-Nitride barrier layer; electrically coupling a gate to the group III-Nitride barrier layer; electrically coupling a drain to the group III-Nitride barrier layer; and providing a p-region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer. Example 123. The method of making a device of Example 122, further comprising implanting the p-region. Example 124. The method of making a device of Example 122, wherein the p-region is in the substrate below said group III-Nitride barrier layer. Example 125. The method of making a device of Example 122, further comprising providing an epitaxial layer on the substrate and the p-region is in the epitaxial layer. Example 126. The method of making a device of Example 122, further comprising providing an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group III-Nitride barrier layer. Example 127. The method of making a device of Example 122, further comprising providing a field plate, wherein the field plate is electrically coupled to said p-region. Example 128. The method of making a device of Example 127, further comprising providing a field plate, wherein the field plate is electrically coupled to the source. Example 129. The method of making a device of Example 128, wherein the field plate is electrically coupled to the source and said p-region. While the disclosure has been described in terms of exemplary aspects, those skilled in the art will recognize that the disclosure can be practiced with modifications in the spirit and scope of the appended claims. These examples given above are merely illustrative and are not meant to be an exhaustive list of all possible designs, aspects, applications or modifications of the disclosure. | 151,058 |
11862720 | DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some embodiments, a group III-V device is formed on a silicon substrate because silicon substrates are, among other things, cheap and readily available in a wide variety of sizes. Further, in some embodiments, the group III-V device comprises an aluminum nitride (e.g., AlN) buffer layer and a group III-V heterojunction structure overlying the aluminum nitride buffer layer. The aluminum nitride buffer layer directly contacts the silicon substrate at an interface and serves as a seed for epitaxially forming an overlying layer (e.g., another buffer layer). A challenge with the group III-V device is that the aluminum nitride buffer layer induces band bending at the interface and the band banding results in the formation of a two-dimensional hole gas (2DHG) in the silicon substrate. The 2DHG extends along the interface and has a high concentration of mobile holes. Further, the interface is flat, such that carrier mobility is high at the interface. The 2DHG and the high carrier mobility lead to a low resistance at the interface, such that an average resistance of the silicon substrate is reduced. This leads to substrate losses that reduce the power added efficiency (PAE) of the group III-V device when used for radiofrequency (RF) applications. Various embodiments of the present application are directed towards a group III-V device comprising a rough buffer layer. The rough buffer layer overlies a silicon substrate, a group III-V buffer structure overlies the rough buffer layer, and a group III-V heterojunction structure overlies the group III-V buffer structure. The group III-V buffer structure causes band bending between the silicon substrate and the group III-V buffer structure, and the band bending leads to formation of a 2DHG in the rough buffer layer. The rough buffer layer comprises silicon or some other suitable semiconductor material and, in some embodiments, is doped with carbon, magnesium, zinc, arsenic, phosphorous, some other suitable element(s), or any combination of the foregoing. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility at the 2DHG, which increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which increases a PAE of the group III-V device when used for RF applications. With reference toFIG.1, a cross-sectional view100of some embodiments of a group III-V device comprising a rough buffer layer102is provided. The group III-V device is on a substrate104and may, for example, be a group III-nitride device and/or a depletion mode high electron mobility transistor (D-HEMT). Other device types are, however, amenable. The substrate104is or comprises silicon and, in at least some embodiments, is devoid of group III-V semiconductor materials. For example, the substrate104may be or comprise monocrystalline silicon or some other suitable silicon material. In some embodiments, a top surface of the substrate104is the same or substantially the same as the (111) lattice plane of the substrate104. Substantially the same may, for example, mean that the (111) lattice plane and the top surface of the substrate104intersect at an offset angle of 4 degrees or less in each of the X, Y, and Z dimensions. Other suitable offset angles are, however, amenable in the X, Y, and Z dimensions. In some embodiments, the substrate104is a bulk semiconductor substrate and/or is a semiconductor wafer. The rough buffer layer102overlies and directly contacts the substrate104at a first buffer interface106a. Further, a group III-V buffer structure108overlies and directly contacts the rough buffer layer102at a second buffer interface106b, and a group III-V heterojunction structure110overlies the group III-V buffer structure108. The group III-V buffer structure108and the rough buffer layer102may, for example, compensate for differences in lattice constants, crystalline structures, thermal expansion coefficients, or any combination of the foregoing between the substrate104and the group III-V heterojunction structure110. The group III-V buffer structure108comprises, among other layers, a seed buffer layer112. The seed buffer layer112overlies and directly contacts the rough buffer layer102at the second buffer interface106b. Further, the seed buffer layer112serves as a seed or nucleation layer for growing a group III-V semiconductor layer on the substrate104. The seed buffer layer112may, for example, be or comprise aluminum nitride (e.g., AlN), some other suitable group suitable III nitride, or some other suitable group III-V material. In some embodiments, the seed buffer layer112is a binary group III-V semiconductor material. Further, the seed buffer layer112may, for example, have a thickness of about 100-350 angstroms or some other suitable value. The seed buffer layer112induces band bending in the rough buffer layer102and the substrate104. In at least some embodiments, such as, for example, where the substrate104and the rough buffer layer102are or comprises monocrystalline silicon, the band bending induces formation of a 2DHG114. The 2DHG114extends along the first buffer interface106aand/or the second buffer interface106bat the rough buffer layer102. Further, the 2DHG114has a high concentration of mobile holes and hence has a low resistance. The low resistance of the 2DHG114decreases an overall resistance of the substrate104, which increases substrates losses and decreases PAE when the group III-V device is used for RF applications. The rough buffer layer102counteracts negative effects of the 2DHG114. A top surface of the rough buffer layer102and a bottom surface of the rough buffer layer102are rough so the first and second buffer interfaces106a,106bare rough. The roughness increases carrier scattering at the first and second buffer interfaces106a,106band hence reduces carrier mobility at the 2DHG114. The reduced carrier mobility increases resistance at the 2DHG114and hence increases an overall resistance of the substrate104. The increased overall resistance reduces substrate losses and increases PAE when the group III-V device is used for RF applications. For example, the PAE may be increased from about 54% to about 57% at a frequency of about 6 gigahertz (GHz). Further, the increased overall resistance enhances co-planar waveguide (CPW) performance when the group III-V device is used for RF applications. CPW is a short loop test to measure substrate losses by comparing power out to power in to see how much power loss occurs during signal transfer. CPW may, for example, be enhanced from about −0.51 decibels (dB) to about −0.45 dB at a frequency of about 6 GHz. In some embodiments, the top and bottom surfaces of the rough buffer layer102are “rough” in that the top and bottom surfaces are uneven and have slopes that vary periodically or randomly across the top and bottom surfaces. In some embodiments, the top and bottom surfaces of the rough buffer layer102are “rough” in that the top and bottom surfaces have bumps, hillocks, protrusions, some other suitable features, or any combination of the foregoing arranged periodically or randomly across the top and bottom surfaces. For example, the top and bottom surfaces may have saw toothed profiles. As another example, the top and bottom surfaces may have wavy profiles. Other profiles are, however, amenable. In some embodiments, a thickness Tr of the rough buffer layer102is about 20-200 angstroms, about 20-110 angstroms, about 110-200 angstroms, or some other suitable value. In some embodiments, a total thickness variation (TTV) of the rough buffer layer102is about 1.2-5.0:1, about 1.2-3.1:1, about 3.1-5.0:1, or some other suitable ratio. In some embodiments, TTV is a ratio of the largest thickness value of the rough buffer layer102to the smallest thickness value of the rough buffer layer102. For example, supposing the rough buffer layer102has a maximum thickness value of 68 angstroms and a minimum thickness value of 32 angstroms, the TTV would be about 2.1. If the thickness Tr is too small (e.g., less than about 20 angstroms or some other suitable value) and/or the TTV is too small (e.g., less than about 1.2:1 or some other suitable ratio), the rough buffer layer102may not have sufficient roughness to counteract the negative effects of the 2DHG114. If the thickness Tr is too large (e.g., greater than about 200 angstroms or some other suitable value) and/or the TTV is too large (e.g., greater than about 5.0:1 or some other suitable ratio), crystalline quality of the seed buffer layer112may be poor and may hence lead to leakage current and increased substrate losses. The rough buffer layer102is or comprises a semiconductor material with a narrow band gap, such as, for, example, silicon, germanium, some other suitable semiconductor material(s), or any combination of the foregoing. A narrow band gap may, for example, be a band gap less than that of the seed buffer layer112and/or less than about 1.3 electron volts (eV), 1.0 eV, or some other suitable value. In some embodiments, the band gap of the rough buffer layer102is less than that of a smallest band gap in the group III-V buffer structure108. In some embodiments, a band gap of the rough buffer layer102and a band gap of the substrate104are within about 0.1 eV, 0.5 eV, 0.7 eV, or some other suitable value of each other. In some embodiments, the rough buffer layer102is or comprises a same material as the substrate104. For example, the rough buffer layer102and the substrate104may be or comprise monocrystalline silicon. In at least some embodiments, the rough buffer layer102is devoid of group III-V semiconductor materials. In some embodiments, the rough buffer layer102is a material that may serve as a seed for epitaxially growing the seed buffer layer112. In some embodiments, the rough buffer layer102is doped with a buffer element. As seen hereafter, the buffer element may, for example, aid in formation of the rough buffer layer102, and/or cause the rough buffer layer102to form, with rough surfaces. The buffer element may, for example, be carbon (e.g., C), magnesium (e.g., Mg), zinc (e.g., Zn), arsenic (e.g., Ar), phosphorous (e.g., P), or some other suitable buffer element. In some embodiments, the buffer element is an n-type dopant. For example, where the rough buffer layer102is or comprises silicon, the buffer element may be arsenic, phosphorous, or some other suitable n-type dopant for silicon. The n-type dopant has excess electrons, which counter the mobile holes in the 2DHG114. By countering the mobile holes, the n-type dopant increases a resistance of the 2DHG114. This increased resistance, in turn, reduces substrate losses, increases PAE, and enhances CPW. In alternative embodiments, the buffer element is a p-type dopant. In some embodiments, the rough buffer layer102is doped with multiple buffer elements, each as described above. Referring back to the group III-V buffer structure108, the group III-V buffer structure108further comprises a graded buffer layer116and an isolation buffer layer118stacked upon each other. The graded buffer layer116overlies the seed buffer layer112and is or comprises a group III-V semiconductor material with a first element and a second element respectively having atomic percentages that are graded. For example, the first element may have an atomic percentage increasing from a bottom surface of the graded buffer layer116to a top surface of the graded buffer layer116, whereas the second element may have an atomic percentage decreasing from the bottom surface to the top surface. The graded buffer layer116may, for example, be or comprise aluminum gallium nitride (e.g., AlGaN), some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the graded buffer layer116is or comprises a ternary group III-V material and the first and second elements of the graded buffer layer116are group III elements. For example, the graded buffer layer116may be or comprise aluminum gallium nitride, the first element may be germanium (e.g., Ge), and the second element may be aluminum (e.g., Al). In some embodiments, the seed buffer layer112is or comprises a binary group III-V, the second element of the graded buffer layer116is the group III element of the seed buffer layer112, and a group V element of the graded buffer layer116is the same as that of the seed buffer layer112. For example, the graded buffer layer116may be or comprise aluminum gallium nitride, the seed buffer layer112may be or comprise aluminum nitride, and the second element may be aluminum. In some embodiments, the graded buffer layer116has a thickness of about 0.5-1.5 micrometers or some other suitable value. The isolation buffer layer118overlies the graded buffer layer116and is or comprises a group III-V semiconductor material doped with a buffer element so as to have a high resistance. The high resistance may, for example, be a resistance higher than that of a channel layer120hereafter discussed. The high resistance allows the isolation buffer layer118to act as “back barrier” for the channel layer120to reduce substrate losses and to increase the soft breakdown voltage of the group III-V device. The buffer element may, for example, be carbon, iron (e.g., Fe), some other suitable buffer element(s), or any combination of the foregoing. The isolation buffer layer118may be or comprise, for example, gallium nitride (e.g., GaN), some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the isolation buffer layer118is or comprises a binary group III-V material that comprises a group III element of the graded buffer layer116and that further comprises a group V element of the graded buffer layer116. For example, the isolation buffer layer118may be or comprise gallium nitride and the graded buffer layer116may be or comprise aluminum gallium nitride. In some embodiments, a thickness of the isolation buffer layer118is about 0.5-2.5 micrometers or some other suitable value. The group III-V heterojunction structure110overlies the group III-V buffer structure108and comprises the channel layer120and a barrier layer122. The barrier layer122overlies the channel layer120and is or comprises a group III-V semiconductor material. Further, the barrier layer122is polarized so positive charge is shifted towards a bottom surface of the barrier layer122and negative charge is shifted towards a top surface of the barrier layer122. The polarization may, for example, result from spontaneous polarization effects and/or piezoelectric polarization effects. The barrier layer122may be or comprise, for example, aluminum gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the barrier layer122is or comprises a ternary group III-V material and/or comprises the same elements as the graded buffer layer116. For example, the barrier layer122and the graded buffer layer116may be or comprise aluminum gallium nitride. In some embodiments, the barrier layer122is or comprises AlyGa1-yN, where y is about 0.1-0.2. In some embodiments, the barrier layer122has a thickness of about 5-30 nanometers or some other suitable thickness value. The channel layer120underlies and directly contacts the barrier layer122. Further, the channel layer120is an undoped group III-V semiconductor material with a band gap unequal to that of the barrier layer122. Because of the unequal band gaps, the channel layer120and the barrier layer122define a heterojunction at a heterojunction interface124at which the channel layer120and the barrier layer122directly contact. Further, because the barrier layer122is polarized, a two-dimensional electron gas (2DEG)126forms in the channel layer120. The 2DEG126extends along the heterojunction interface124and has a high concentration of mobile electrons. Because of the high concentration of mobile electrodes, the 2DEG126is conductive. The channel layer120may, for example, be or comprise gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the channel layer120is or comprises a binary group III-V material and/or comprises the same elements as the isolation buffer layer118but without the doping. For example, the channel layer120and the isolation buffer layer118may be or comprise aluminum gallium nitride. In some embodiments, the channel layer120has a thickness of about 0.2-0.6 micrometers or some other suitable thickness value. A first passivation layer128overlies the group III-V heterojunction structure110. A first source/drain electrode130and a second source/drain electrode132are laterally spaced from each other and extend through the first passivation layer128to the group III-V heterojunction structure110. In some embodiments, the first and second source/drain electrodes130,132make ohmic contact with the group III-V heterojunction structure110. Further, a gate electrode134is laterally between the first and second source/drain electrodes130,132and extends through the first passivation layer128to the group III-V heterojunction structure110. The first passivation layer128may be or comprise silicon oxide and/or some other suitable dielectric(s). The first and second source/drain electrodes130,132and/or the gate electrode134may be or comprise metal and/or some other suitable conductive material(s). During use of the group III-V device, the gate electrode134generates an electric field that manipulates the continuity of the 2DEG126from the first source/drain electrode130to the second source/drain electrode132. For example, when the gate electrode134is biased with a voltage that is more than a threshold voltage, the gate electrode134may generate an electric field depleting an underlying portion of the 2DEG126of mobile electrons and breaking the continuity. As another example, when the gate electrode134is biased with a voltage that is less than the threshold voltage, the 2DEG126may be continuous from the first source/drain electrode130to the second source/drain electrode132. In some embodiments, the substrate104is or comprises monocrystalline silicon; the rough buffer layer102is or comprises monocrystalline silicon doped with carbon, magnesium, zinc, phosphorous, or arsenic; the seed buffer layer112is or comprises aluminum nitride; the graded buffer layer116is or comprises aluminum gallium nitride; isolation buffer layer118is or comprises gallium nitride doped with carbon or iron; the channel layer120is or comprises undoped gallium nitride; and the barrier layer122is or comprises aluminum gallium nitride. Other materials are, however, amenable for one or more of the aforementioned layers (e.g., the seed buffer layer112and/or the rough buffer layer102). With reference toFIG.2A, an enlarged cross-sectional view200A of some embodiments of the rough buffer layer102ofFIG.1is provided. The enlarged cross-sectional view200A may, for example, be taken within the circle A inFIG.1. The top and bottom surfaces of the rough buffer layer102have a plurality of features202arranged in periodic patterns across the top and bottom surfaces. Further, the features202are uniform or substantially uniform in shape and size and have a tooth-shaped profile, such that the top and bottom surfaces have saw-toothed profiles. Other shapes, sizes, profiles, or any combination of the foregoing are, however, amenable for the features202. The features202may, for example, be bumps, hillocks, protrusions, some other suitable feature types, or any combination of the foregoing. With reference toFIG.2B, an enlarged cross-sectional view200B of some alternative embodiments of the rough buffer layer102ofFIG.2Ais provided in which the features202are randomly distributed across the top and bottom surfaces of the rough buffer layer102and have random variation in shape and size. With reference toFIG.2C, an enlarged cross-sectional view200C of some alternative embodiments of the rough buffer layer102ofFIG.2Bis provided in which the top and bottom surfaces of the rough buffer layer102are smoother. As such, the top and bottom surfaces of the rough buffer layer102have wavy profiles. With reference toFIGS.2D and2E, enlarged cross-sectional views200D,200E of some alternative embodiments of the rough buffer layer102ofFIG.2Aare provided in which the bottom or top surface of the rough buffer layer102is flat or substantially flat. InFIG.2D, the bottom surface of the rough buffer layer102is flat or substantially flat. InFIG.2E, the top surface of the rough buffer layer102is flat or substantially flat. WhileFIGS.2D and2Eillustrate alternative embodiments of the rough buffer layer102ofFIG.2Ain which the bottom or top surface of the rough buffer layer102is flat or substantially flat, alternative embodiments of the rough buffer layer102ofFIG.2Bmay also have a bottom or top surface that is flat or substantially flat as inFIGS.2D and2E. Similarly, alternative embodiments of the rough buffer layer102ofFIG.2Cmay also have a bottom or top surface that is flat or substantially flat as inFIGS.2D and2E. With reference toFIGS.3A-3C, graphs300A-300C of various embodiments of a curve302describing doping concentration of the buffer element along a thickness Tr of the rough buffer layer102ofFIG.1is provided. As noted above, the buffer element may, for example, be carbon, magnesium, zinc, arsenic, phosphorous, or some other suitable buffer element. The horizontal axis corresponds to doping concentration, and the vertical axis corresponds to location in the rough buffer layer102. The vertical axis may, for example, correspond to line B inFIG.1. In the graph300A ofFIG.3A, the doping concentration of the buffer element is constant or substantially constant from the bottom surface of the rough buffer layer102to the top surface of the rough buffer layer. In the graph300B ofFIG.3B, the doping concentration of the buffer element increases continuously and linearly from the bottom surface of the rough buffer layer102to the top surface of the rough buffer layer102. Gradually varying the doping concentration of the buffer element may help minimize stress and/or lattice mismatch from different crystalline structures of the substrate104and the seed buffer layer112. In the graph300C ofFIG.3C, the doping concentration of the buffer element increases continuously and linearly from the bottom surface of the rough buffer layer102to a midpoint between the top surface of the rough buffer layer102and the bottom surface. Further, the doping concentration of the buffer element is constant or substantially constant from the midpoint to the top surface of the rough buffer layer102. WhileFIGS.3A-3Cillustrate some embodiments of the curve302, other embodiments are amenable. For example, the curve302in any one ofFIGS.3B and3Cmay be inverted. As another example, the curve302ofFIG.3Bmay discretely increase and/or may have a stepped profile from the bottom surface of the rough buffer layer102to top surface of the rough buffer layer102. As yet another example, the curve302ofFIG.3Cmay discretely increase and/or may have a stepped profile from the bottom surface of the rough buffer layer102to the midpoint between the top and bottom surfaces of the rough buffer layer102. With reference toFIG.4A, a cross-sectional view400A of some alternative embodiments of the group III-V device ofFIG.1is provided in which the rough buffer layer102comprises a first rough buffer sublayer102aand a second rough buffer sublayer102boverlying the first rough buffer sublayer102a. The first and second rough buffer sublayers102a,102bare each individually as the rough buffer layer102inFIG.1is illustrated and described. However, the first and second rough buffer sublayers102a,102bhave different buffer elements and/or different doping concentrations for corresponding buffer elements. For example, the first rough buffer sublayer102amay be doped with carbon and the second rough buffer sublayer102bmay be doped with magnesium. As another example, the first and second rough buffer sublayers102a,102bmay be doped with carbon and respectively have different doping concentrations. With reference toFIG.4B, a cross-sectional view400B of some alternative embodiments of the group III-V device ofFIG.4Ais provided in which the first and second rough buffer sublayers102a,102brepeat multiple times to define a periodic pattern. While the first rough buffer sublayer102aofFIGS.4A and4Bis as the rough buffer layer102inFIG.1is illustrated and described, the first rough buffer sublayer102amay alternatively be as the rough buffer layer102in any ofFIGS.2A-2Eis illustrated and described. Similarly, while the second rough buffer sublayer102bofFIGS.4A and4Bis as the rough buffer layer102inFIG.1is illustrated and described, the second rough buffer sublayer102bmay alternatively be as the rough buffer layer102in any ofFIGS.2A-2Eis illustrated and described. In some embodiments, the first and second rough buffer sublayers102a,102bcorrespond to the same embodiments of the rough buffer layer102inFIGS.1and2A-2E. In other embodiments, the first and second rough buffer sublayers102a,102bcorrespond to different embodiments of the rough buffer layer102inFIGS.1and2A-2E. With reference toFIG.5A, a cross-sectional view500A of some alternative embodiments of the group III-V device ofFIG.1is provided in which the first and second source/drain electrodes130,132extend through the barrier layer122to the channel layer120. As a result, the barrier layer122is cleared directly under the first and second source/drain electrodes130,132and the 2DEG126has a break directly under the first and second source/drain electrodes130,132. With reference toFIG.5B, a cross-sectional view500B of some alternative embodiments of the group III-V device ofFIG.1is provided in which a cap layer502is between the group III-V heterojunction structure110and the first passivation layer128. The cap layer502is or comprises an undoped group III-V semiconductor material with a band gap unequal to that of the barrier layer122. The cap layer502may, for example, be or comprise gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the cap layer502is or comprises a binary group III-V material and/or comprises the same elements as the channel layer120. In some embodiments, the cap layer502is or comprises gallium nitride, the barrier layer122is or comprises aluminum gallium nitride, and the cap layer502and the barrier layer122are formed in situ within a common process chamber and/or a common multi-chamber process tool. The cap layer502protects the barrier layer122during formation of the group III-V device so native oxide does not form from the barrier layer122. Instead, native oxide may form from the cap layer502. Native oxide from gallium nitride is more stable and more readily cleaned than native oxide from aluminum gallium nitride. Further, cleaning native oxide from the cap layer502does not risk damaging the barrier layer122. With reference toFIG.5C, a cross-sectional view500C of some alternative embodiments of the group III-V device ofFIG.5Bis provided in which the cap layer502is doped p-type dopants. In alternative embodiments, the cap layer502may be doped with n-type. As a result of the p-type doping of the cap layer502, the mobile electrons at the 2DEG126are dispersed, and the 2DEG126is dissolved, to sides of the first and second source/drain electrodes130,132. Hence, the group III-V device is an enhancement mode high electron mobility transistor (E-HEMT) or some other suitable device type. With reference toFIG.5D, a cross-sectional view500D of some alternative embodiments of the group III-V device ofFIG.5Ais provided in which a gate dielectric layer504separates the gate electrode134from the group III-V heterojunction structure110. As such, the group III-V device is a depletion mode metal-insulator-semiconductor HEMT (MIS-HEMT) or some other suitable device type. The gate dielectric layer504may, for example, be aluminum oxide, silicon oxide, some other suitable dielectric(s), or any combination of the foregoing. With reference toFIG.5E, a cross-sectional view500E of some alternative embodiments of the group III-V device ofFIG.5Dis provided in which the gate electrode134and the gate dielectric layer504further extend through the barrier layer122. As a result, the 2DEG126has a break at the gate electrode134. Further, the group III-V device is an enhancement mode MIS-HEMT or some other suitable device type. While the first and second source/drain electrodes130,132extend to and terminate at a top surface of the barrier layer122inFIGS.5B-5E, the first and second source/drain electrodes130,132may alternatively extend through the barrier layer122to the channel layer120. While the gate electrode134directly contacts combinations of the channel layer120, the barrier layer122, and the cap layer502inFIGS.5A-5C, the gate electrode134may alternatively be separated from the channel layer120, the barrier layer122, and the cap layer502by the gate dielectric layer504ofFIGS.5D and5E. WhileFIGS.5A-5Eillustrate the rough buffer layer102as having a single layer, the rough buffer layer102may alternatively have multiple layers as inFIGS.4A and4B. WhileFIGS.5A-5Eillustrate the rough buffer layer102as having a top surface and a bottom surface as inFIG.1, the rough buffer layer102may alternatively have a top surface and/or a bottom surface as in any one ofFIGS.2A-2E. With reference toFIG.6, a cross-sectional view600of some embodiments of the group III-V device ofFIG.1is provided in which an interconnect structure602covers the gate electrode134and the first and second source/drain electrodes130,132. Further, a second passivation layer604is between the first passivation layer128and the interconnect structure602, and the first passivation layer128comprises a lower dielectric layer128aand an upper dielectric layer128boverlying the lower dielectric layer128a. In some embodiments, the lower dielectric layer128ais or comprises silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the upper dielectric layer128bis or comprises plasma-enhanced silicon oxide and/or some other suitable dielectric(s). In some embodiments, the second passivation layer604is or comprises plasma-enhanced silicon nitride and/or some other suitable dielectric(s). The interconnect structure602comprises an interlayer dielectric (ILD) layer606and an ILD liner608stacked over the gate electrode134. The ILD liner608underlies the ILD layer606and separates the ILD layer606from the gate electrode134and the second passivation layer604. The ILD liner608may be or comprise, for example, plasma-enhanced silicon oxide and/or some other suitable dielectric(s), whereas the ILD layer606may, for example, be or comprise non-plasma-enhanced silicon oxide and/or some other suitable dielectric(s). The interconnect structure602further comprises a field plate610and a plurality of contact vias612. The field plate610wraps around a top corner of the gate electrode134while remaining separated from the gate electrode134by the ILD liner608. The contact vias612extend through the ILD layer606and the ILD liner608respectively to the first and second source/drain electrodes130,132. While not shown, one or more other contact vias extend through the ILD layer606to the gate electrode134and/or the field plate610. Further, while not shown, wires and additional vias are alternatively stacked over and electrically coupled to the contact vias. The field plate610and the contact vias612may, for example, be or comprise metal and/or some other suitable conductive material(s). WhileFIG.6describes alterations to the group III-V device ofFIG.1, the alterations atFIG.6are applicable to the group III-V device in any one ofFIGS.4A,4B, and5A-5E. For example,FIG.5Amay comprise the interconnect structure602ofFIG.6. With reference toFIGS.7-16, a series of cross-sectional views700-1600of some embodiments of a method for forming a group III-V device comprising a rough buffer layer is provided. The method is illustrated using embodiments of the group III-V device inFIG.6but may also form embodiments in any one ofFIGS.1,4A,4B, and5A-5E. As illustrated by the cross-sectional view700ofFIG.7, a substrate104is provided. The substrate104is or comprises silicon and, in at least some embodiments, is devoid of group III-V semiconductor materials. For example, the substrate104may be or comprise monocrystalline silicon or some other suitable silicon material. In some embodiments, the substrate104is a bulk semiconductor substrate and/or a semiconductor wafer. In some embodiments, a top surface104tof the substrate104is flat or substantially flat. Further, in some embodiments, the top surface104tof the substrate104is the same or substantially the same as the (111) lattice plane of the substrate104. Substantially the same may, for example, mean that the (111) lattice plane and the top surface104tof the substrate104intersect at an offset angle of 4 degrees or less in each of the X, Y, and Z dimensions. Other suitable offset angles are, however, amenable in the X, Y, and Z dimensions. In some embodiments, before proceeding to the acts hereafter described with regard toFIG.8, the top surface104tof the substrate104is pre-roughened. Such pre-roughening may, for example, improve the roughness of a rough buffer layer hereafter formed (see, e.g.,FIG.8). The pre-roughening may, for example, be performed by a blanket wet or dry etch into the top surface104tof the substrate104, by a selective etch into the top surface104t, or by some other suitable pre-roughening process. The selective etch may, for example, use photolithography to transfer a rough pattern to the top surface104tof the substrate104. In some embodiments in which the top surface104tof the substrate104is pre-roughened, the top surface104thas the profile illustrated by a dashed line702. Other profiles are, however, amenable. As illustrated by the cross-sectional view800ofFIG.8, a rough buffer layer102is formed overlying and directly contacting the top surface104tof the substrate104at a first buffer interface106a. Further, the rough buffer layer102is formed within a first process chamber802. A bottom surface of the rough buffer layer102is rough so the top surface104tof the substrate104and the first buffer interface106aare rough. Further, a top surface of the rough buffer layer102is rough.FIG.2Aillustrates an enlarged cross-sectional view200A of some embodiments of the rough buffer layer102within circle A, andFIGS.2B-2Dillustrate enlarged cross-sectional views200B-200D of some alternative embodiments of the rough buffer layer102within circle A. As seen hereafter, the roughness increases a resistance at the first buffer interface106ato increase PAE when the group III-V device is used for RF applications. In some embodiments, the top and bottom surfaces of the rough buffer layer102are “rough” in that the top and bottom surfaces are uneven and have slopes that vary periodically or randomly across the top and bottom surfaces. In some embodiments, the top and bottom surfaces of the rough buffer layer102are “rough” in that the top and bottom surfaces have bumps, hillocks, protrusions, some other suitable features, or any combination of the foregoing arranged periodically or randomly across the top and bottom surfaces. In some embodiments, the top and bottom surfaces have saw-toothed profiles, wavy profiles, serpentine profiles, or some other suitable profiles. In some embodiments, a thickness Tr of the rough buffer layer102is about 20-200 angstroms, about 20-110 angstroms, about 110-200 angstroms, or some other suitable value. In some embodiments, a TTV of the rough buffer layer102is about 1.2-5.0, about 1.2-3.1, about 3.1-5.0, or some other suitable value. The rough buffer layer102is or comprises a semiconductor material with a narrow band gap, such as, for, example, silicon, germanium, some other suitable semiconductor material(s), or any combination of the foregoing. A narrow band gap may, for example, be a band gap less than that of the seed buffer layer112and/or less than about 1.3, 1.0, or some other suitable value. In some embodiments, a band gap of the rough buffer layer102and a band gap of the substrate104are within about 0.1 eV, 0.5 eV, 0.7 eV, or some other suitable value of each other. In some embodiments, the rough buffer layer102is or comprises a same material as the substrate104. In at least some embodiments, the rough buffer layer102is devoid of group III-V semiconductor materials. In some embodiments, the rough buffer layer102is a material that may serve as a seed for epitaxially growing a seed buffer layer hereafter discussed. In some embodiments, the rough buffer layer102is doped with a buffer element. The buffer element may, for example, aid in or otherwise cause formation of the rough buffer layer102with top and bottom surfaces that are rough. For example, the buffer element may replace a semiconductor element in the crystalline lattice of the rough buffer layer102to cause the roughness at the top and bottom surfaces of the rough buffer layer102.FIGS.3A-3Cillustrate various embodiments of a curve302describing doping concentration of the buffer element along the thickness Tr of the rough buffer layer102and/or along line B. The buffer element may, for example, be or comprise carbon, magnesium, zinc, arsenic, phosphorous, or some other suitable buffer element. In some embodiments, the buffer element is an n-type dopant. For example, where the rough buffer layer102is or comprises silicon, the buffer element may be arsenic, phosphorous, or some other suitable n-type dopant for silicon. In alternative embodiments, the buffer element is a p-type dopant. In some embodiments, the rough buffer layer102is doped with multiple buffer elements, each as described above. The rough buffer layer102may, for example, be formed by an individual metal organic chemical vapor deposition (MOCVD) process, a shared MOCVD process, a silicon epitaxial deposition process, or some other suitable deposition process. The individual MOCVD process is individual to the rough buffer layer102and is not used to form the rough buffer layer102with a subsequently described seed buffer layer. The shared MOCVD process is shared by the rough buffer layer102and the subsequently described seed buffer layer, such that the rough buffer layer102and the seed buffer layer are formed together. In at least some embodiments in which the buffer element is or comprises arsenic or phosphorus, the rough buffer layer102is formed by the silicon epitaxial deposition process. The silicon epitaxial deposition process may, for example, be or comprise molecular-beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), some other suitable silicon epitaxial deposition process, or any combination of the foregoing. In at least some embodiments in which the buffer element is or comprises magnesium or zinc, the rough buffer layer102is formed by the individual MOCVD process. In at least some embodiments in which the buffer element is or comprises carbon, the rough buffer layer102is formed by the individual or shared MOCVD process or the silicon epitaxial process. In some embodiments, the individual MOCVD process comprises introducing a silicon-containing precursor and a buffer-element-containing precursor into the first process chamber802at a process temperature of about 600-1000 degrees Celsius. Other process temperatures are, however, amenable. The silicon-containing precursor may, for example, be or comprise silane (e.g., SiH4) or some other suitable precursor containing silicon. In embodiments in which the buffer element is or comprises carbon, the buffer-element-containing precursor may, for example, be or comprise cyclohexane (e.g., C6H12), trimethylaluminium (e.g., Al2(CH3)6), or some other suitable precursor containing carbon. In embodiments in which the buffer element is or comprises magnesium, the buffer-element-containing precursor may, for example, be or comprise Bis(cyclopentadienyl)magnesium (e.g., Cp2Mg) or some other suitable precursor containing magnesium. In embodiments in which the buffer element is or comprises zinc, the buffer-element-containing precursor may, for example, be or comprise dimethylzinc (e.g., C2H6Zn) or some other suitable precursor containing zinc. As illustrated by the cross-sectional view900ofFIG.9, a seed buffer layer112is epitaxially formed overlying and directly contacting the rough buffer layer102at a second buffer interface106b. Further, the seed buffer layer112is formed using the rough buffer layer102as a seed or nucleation layer and is formed within a second process chamber902. The seed buffer layer112serves as a seed or nucleation layer for growing a group III-V semiconductor layer hereafter formed on the seed buffer layer112. The seed buffer layer112may, for example, be or comprise aluminum nitride, some other suitable group suitable III nitride, or some other suitable group III-V material. Further, the seed buffer layer112may, for example, have a thickness Ts of about 100-350 angstroms or some other suitable value. The seed buffer layer112may, for example, be formed by an MOCVD process or some other suitable deposition process. In some embodiments, the seed buffer layer112is formed at a process temperature of about 700-1150 degrees Celsius and/or is formed while the second process chamber1102has a chamber pressure of about 50-200 millibars. Other process temperatures and/or chamber pressures are, however, amenable. In some embodiments, the seed buffer layer112and the rough buffer layer102are formed together in a common process chamber by the shared MOCVD process mentioned above with regard to formation of the rough buffer layer102. In such embodiments, the first and second process chambers802,902respectively ofFIGS.8and9are the same. Forming the seed buffer layer112and the rough buffer layer102by the shared MOCVD process may, for example, improve throughput and may, for example, reduce costs. In alternative embodiments, the seed buffer layer112and the rough buffer layer102are formed independently in separate process chambers. In such embodiments, the first and second process chambers802,902respectively ofFIGS.8and9are different. In some embodiments, the shared MOCVD process comprises at least two steps: 1) a first step to form the rough buffer layer102doped with carbon; and 2) a second step to form the seed buffer layer112on the rough buffer layer102. During the first step, a carbon-containing aluminum precursor is introduced into to the common process chamber (e.g., the first and second process chambers802,902respectively ofFIGS.8and9, which are the same in these embodiments). During the second step, a nitrogen precursor is also introduced into the common process chamber. Hence, the carbon-containing aluminum precursor, but not the nitrogen precursor, is introduced into the common process chamber during the first step and both the carbon-containing aluminum precursor and the nitrogen precursor are introduced into the common process chamber during the second step. The carbon-containing aluminum precursor may be or comprise, for example, trimethylaluminium or some other suitable precursor. In some embodiments in which the carbon-containing aluminum precursor is or comprises trimethylaluminium, the carbon-containing aluminum precursor is introduced into the common process chamber at about 90-120 standard cubic centimeters per minute (SCCM) or some other suitable rate. The nitrogen precursor may be or comprise, for example, ammonia (e.g., NH3) or some other suitable precursor. The first step may, for example, persist for about 30-180 seconds or some other suitable amount of time, and/or the second step may, for example, persist for about 3-30 minutes or some other suitable amount of time. Because the seed buffer layer112is a different semiconductor material than the rough buffer layer102and the substrate104, band bending occurs at the rough buffer layer102and the substrate104. In at least some embodiments, the band bending induces formation of a 2DHG114extending along the first and second buffer interfaces106a,106bat the rough buffer layer102. The 2DHG114has a high concentration of mobile holes and hence has a low resistance. The low resistance of the 2DHG114decreases an overall resistance of the substrate104. The decrease in overall resistance increases substrates losses and decreases PAE when the group III-V device is used for RF applications. Further, the decrease in overall resistance degrades CPW when the group III-V device is used for RF applications. However, the rough buffer layer102counteracts the negative effects of the 2DHG114. The roughness at the top and bottom surfaces of the rough buffer layer102increases carrier scattering at the top and bottom surfaces and hence reduces carrier mobility at the 2DHG114. The reduced carrier mobility increases a resistance at the 2DHG114and hence increases an overall resistance of the substrate104. The increased overall resistance reduces substrate losses and increases PAE when the group III-V device is used for RF applications. Further, the increased overall resistance enhances CPW when the group III-V device is used for RF applications. In at least some embodiments in which the rough buffer layer102is doped with n-type dopants, excess electrons of the rough buffer layer102counter mobile holes of the 2DHG114and further increase resistance at the 2DHG114to further reduce substrate losses. As illustrated by the cross-sectional view1000ofFIG.10, a graded buffer layer116is formed on the seed buffer layer112. The graded buffer layer116is or comprises a group III-V semiconductor material with a first element and a second element respectively having atomic percentages that are graded. For example, the first element may have an atomic percentage increasing from a bottom surface of the graded buffer layer116to a top surface of the graded buffer layer116, whereas the second element may have an atomic percentage decreasing from the bottom surface to the top surface. The first and second buffer layers may, for example, be group III elements. The second element may, for example, be a group III element of the seed buffer layer112, and/or the first may, for example, be a group III element found in group III-V layers subsequently formed on the graded buffer layer. The graded buffer layer116may, for example, be or comprise aluminum gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the graded buffer layer116has a thickness Tg of about 0.5-1.5 micrometers or some other suitable value. The graded buffer layer116may, for example, be formed by MOCVD, some other suitable epitaxial process, or some other suitable deposition process. In some embodiments, the graded buffer layer116is formed at a process temperature of about 1000-1150 degrees Celsius and/or within a process chamber having a chamber pressure of about 50-200 millibars. Other process temperatures and/or chamber pressures are, however, amenable. As illustrated by the cross-sectional view1100ofFIG.11, an isolation buffer layer118is formed on the graded buffer layer116. The isolation buffer layer118is or comprises a group III-V semiconductor material doped with a buffer element so as to have a high resistance. The high resistance may, for example, be a resistance higher than that of a channel layer hereafter discussed (see, e.g.,FIG.12). The high resistance allows the isolation buffer layer118to act as “back barrier” for a channel layer hereafter formed so as to reduce substrate losses and to increase the soft breakdown voltage of the group III-V device being formed. The buffer element may, for example, be carbon, iron, or some other suitable buffer element. The isolation buffer layer118may be or comprise, for example, gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the isolation buffer layer118shares a group III element and/or a group V element with the graded buffer layer116and/or the seed buffer layer112. In some embodiments, a thickness of the isolation buffer layer118is about 0.5-2.5 micrometers or some other suitable value. The isolation buffer layer118may, for example, be formed by MOCVD, some other suitable epitaxial process, or some other suitable deposition process. In some embodiments, the isolation buffer layer118is formed at a process temperature of about 900-1050 degrees Celsius and/or within a process chamber having a chamber pressure of about 50-500 millibars. Other process temperatures and/or chamber pressures are, however, amenable. Collectively, the seed buffer layer112, the graded buffer layer116, and the isolation buffer layer118define a group III-V buffer structure108. The group III-V buffer structure108and the rough buffer layer102may, for example, compensate for differences in lattice constants, crystalline structures, thermal expansion coefficients, or any combination of the foregoing between the substrate104and a heterojunction structure hereafter formed on the group III-V buffer structure108. By compensating for these differences, the group III-V buffer structure108and the rough buffer layer102may alleviate stress, which may, for example, reduces leakage current and/or reduce warping of the substrate104. As illustrated by the cross-sectional view1200ofFIG.12, a channel layer120is formed on the isolation buffer layer118. The channel layer120is or comprises an undoped group III-V semiconductor material. In some embodiments, the channel layer120is or comprises the same group III-V semiconductor material as the isolation buffer layer118, except that the channel layer120is undoped whereas the isolation buffer layer118is doped. The channel layer120may, for example, be or comprise gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the channel layer120has a thickness Tc of about 0.2-0.6 micrometers or some other suitable thickness value. The channel layer120may, for example, be formed by MOCVD, some other suitable epitaxial process, some other suitable deposition process. In some embodiments, the channel layer120is formed at a process temperature of about 950-1050 degrees Celsius and/or within a process chamber having a chamber pressure of about 100-650 millibars. Other process temperatures and/or chamber pressures are, however, amenable. As illustrated by the cross-sectional view1300ofFIG.13, a barrier layer122is formed overlying and directly contacting the channel layer120. The barrier layer122is a group III-V semiconductor material with a band gap unequal to that of the channel layer120. Because of the unequal band gaps, the channel layer120and the barrier layer122define a heterojunction at a heterojunction interface124at which the channel layer120and the barrier layer122directly contact. Hence, the channel layer120and the barrier layer122collectively define a group III-V heterojunction structure110. Further, the barrier layer122is polarized so positive charge is shifted towards a bottom surface of the barrier layer122and negative charge is shifted towards a top surface of the barrier layer122. Because the barrier layer122is polarized, a 2DEG126 forms in the channel layer120. The 2DEG126extends along the heterojunction interface124and has a high concentration of mobile electrons. Because of the high concentration of mobile electrodes, the 2DEG126is conductive. The barrier layer122may be or comprise, for example, aluminum gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the barrier layer122is or comprises AlyGa1-yN, where y is about 0.1-0.2. In some embodiments, the barrier layer122has a thickness Tb of about 5-30 nanometers or some other suitable thickness value. The barrier layer122may, for example, be formed by MOCVD, some other suitable epitaxial process, or some other suitable deposition process. In some embodiments, the barrier layer122is formed at a process temperature of about 1000-1100 degrees Celsius and/or within a process chamber having a chamber pressure of about 50-100 millibars. Other process temperatures and/or chamber pressures are, however, amenable. While not shown, a cap layer may be formed on the graded buffer layer116before a first passivation layer is hereafter formed atFIG.14. The cap layer is or comprises a group III-V semiconductor material with a band gap unequal to that of the barrier layer122. The cap layer may, for example, be or comprise gallium nitride, some other suitable group III nitride, or some other suitable group III-V material. In some embodiments, the cap layer502is or comprises a binary group III-V material and/or comprises the same elements as the channel layer120. In some embodiment, the cap layer is undoped, an example of which is described with regard toFIG.5B. In alternative embodiments, the cap layer is doped with p-type or n-type dopants, an example of which is described with regard toFIG.5C. In some embodiments, the cap layer is or comprises gallium nitride, the barrier layer122is or comprises aluminum gallium nitride, and the cap layer and the barrier layer122are formed in situ within a common process chamber and/or a common multi-chamber process tool. The cap layer protects the barrier layer122during formation of the group III-V device so native oxide does not form from the barrier layer122. Instead, native oxide may form from the cap layer. Native oxide from gallium nitride is more stable and more readily cleaned than native oxide from aluminum gallium nitride. Further, cleaning native oxide from the cap layer does not risk damaging the barrier layer122. As illustrated by the cross-sectional view1400ofFIG.14, a first passivation layer128is formed over the group III-V heterojunction structure110. The first passivation layer128comprises a lower dielectric layer128aand an upper dielectric layer128boverlying the lower dielectric layer128a. In alternative embodiments, the lower or upper dielectric layer128a,128bis omitted. The lower dielectric layer may, for example, be or comprise silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. The upper dielectric layer128bmay, for example, be or comprise plasma-enhanced silicon oxide and/or some other suitable dielectric(s). The first passivation layer128may, for example, be formed by plasma-enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric-pressure chemical vapor deposition (APCVD), atomic layer deposition (ALD), some other suitable deposition process(es), or any combination of the foregoing. Also illustrated by the cross-sectional view1400ofFIG.14, a first source/drain electrode130and a second source/drain electrode132are formed overlying the first passivation layer128. Further, the first and second source/drain electrodes protrude through the first passivation layer128and terminate at a top surface of the barrier layer122. In alternative embodiments, the first and second source/drain electrodes130,130protrude through the barrier layer122and terminate at the channel layer120. See, for example,FIG.5A. The first and second source/drain electrodes130,132may, for example, be or comprise metal and/or some other suitable conductive material(s). A process for forming the first and second source/drain electrodes130,132may, for example, comprise: 1) patterning the first passivation layer128to form openings corresponding to the first and second source/drain electrodes130,132; 2) depositing a metal layer covering the first passivation layer and filling the openings; and 3) patterning the metal layer into the first and second source/drain electrodes130,132. Other processes are, however, amenable. The patterning of the first passivation layer128and the metal layer may, for example, each be performed by a photolithography/etching process or some other suitable patterning process. The photolithography/etching process for at least the first passivation layer128may, for example, employ dry etching or some other suitable etching type. The depositing of the metal layer may, for example, be performed by PECVD, LPCVD, APCVD, ALD, some other suitable deposition process(es), or any combination of the foregoing. As illustrated by the cross-sectional view1500ofFIG.15, a second passivation layer604and a gate electrode134are formed over the first and second source/drain electrodes130,132and the first passivation layer128. The gate electrode134overlies the second passivation layer604and protrudes through the first and second passivation layers128,604. Further, the gate electrode134protrudes to and terminates at a top surface of the barrier layer122. The second passivation layer604may, for example, be or comprise plasma-enhanced silicon nitride and/or some other suitable dielectric(s). The second passivation layer604may, for example, be formed as the first passivation layer128is formed. The gate electrode134may, for example, be or comprise metal and/or some other suitable conductive material(s). The gate electrode134may, for example, be formed as the first and second source/drain electrodes130,132are formed. While the first and second source/drain electrodes130,132and the gate electrode134are illustrated as being formed separately, the first and second source/drain electrodes130,132and the gate electrode134may alternatively be formed together. In such embodiments, the second passivation layer604is omitted. Further, the above process for forming the first and second source/drain electrodes130,132forms the gate electrode134in parallel with the first and second source/drain electrodes130,132. While the gate electrode134extends to the group III-V heterojunction structure110, a gate dielectric layer may alternatively be formed separating the gate electrode134from the group III-V heterojunction structure110. Examples of such a gate dielectric layer are inFIGS.5D and5E. As illustrated by the cross-sectional view1600ofFIG.16, an interconnect structure602is formed over the second passivation layer604and the gate electrode134. The interconnect structure602comprises an ILD layer606and an ILD liner608. The ILD liner608underlies the ILD layer606and separates the ILD layer606from the gate electrode134and the second passivation layer604. The interconnect structure602further comprises a field plate610and a plurality of contact vias612in the ILD layer606. The field plate610wraps around a top corner of the gate electrode134while remaining separated from the gate electrode134by the ILD liner608. The contact vias612extend through the ILD layer606and the ILD liner608respectively to the first and second source/drain electrodes130,132. WhileFIGS.7-16are described with reference to a method, it will be appreciated that the structures shown inFIGS.7-16are not limited to the method but rather may stand alone separate of the method. WhileFIGS.7-16are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.7-16illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.17, a block diagram1700of some embodiments of the method ofFIGS.7-16is provided. At1702, a rough buffer layer is deposited on a substrate. See, for example,FIG.8. At1704, a group III-V buffer structure is formed on the rough buffer layer. See, for example,FIGS.9-11. At1704a, the forming of the group III-V buffer structure comprises depositing a seed buffer layer on the rough buffer layer. See, for example,FIG.9. At1704b, the forming of the group III-V buffer structure comprises depositing a graded buffer layer on the seed buffer layer. See, for example,FIG.10. At1704c, the forming of the group III-V buffer structure comprises depositing an isolation buffer layer on the graded buffer layer. See, for example,FIG.11. In alternative embodiments, the group III-V buffer structure is wholly omitted. In alternative embodiments, the group III-V buffer structure is partially omitted, such that the seed buffer layer, the graded buffer layer, the isolation buffer layer, some other buffer layer(s) (not shown inFIGS.7-16), or any combination of the foregoing is/are omitted. The seed buffer layer induces formation of a 2DHG in the rough buffer layer. This, in turn, decreases a resistance of the substrate and increases substrate losses, whereby PAE is reduced when the group III-V device is used for RF applications. The rough surfaces of the rough buffer layer, however, counteract the negative effects of the 2DHG by scattering carriers at the rough surfaces. This reduces carrier mobility at the 2DHG and increases the resistance at the 2DHG. The increased resistance, in turn, decreases substrates losses and increases PAE. At1706, a group III-V heterojunction structure is formed on the group III-V buffer structure. See, for example,FIGS.12and13. At1708, a pair of source/drain electrodes and a gate electrode are formed on the group III-V heterojunction structure. See, for example,FIGS.14and15. While the block diagram1700ofFIG.17is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. In some embodiments, the present disclosure provides a semiconductor device including: a substrate; a group III-V buffer structure overlying the substrate; a group III-V heterojunction structure overlying the group III-V buffer structure; a pair of source/drain electrodes overlying the group III-V heterojunction structure; a gate electrode overlying the group III-V heterojunction structure, laterally between the source/drain electrodes; and a rough buffer layer between the substrate and the group III-V buffer structure, wherein the rough buffer layer directly contacts the substrate and the group III-V buffer structure respectively at a first interface and a second interface, wherein the first interface is rough throughout and/or the second interface is rough throughout, and wherein the rough buffer layer shares a common semiconductor element with the substrate. In some embodiments, the first or second interface has a wavy profile alternating between randomly sized bumps. In some embodiments, a thickness of the rough buffer layer varies throughout the rough buffer layer. In some embodiments, the thickness of the rough buffer layer has a maximum thickness value and a minimum thickness value, wherein the maximum thickness value is about 1.2-5.1 times the minimum thickness value. In some embodiments, the first and second interfaces are rough throughout. In some embodiments, the rough buffer layer includes monocrystalline silicon doped with carbon, magnesium, zinc, arsenic, or phosphorous. In some embodiments, the group III-V buffer structure includes: an aluminum nitride layer overlying and directly contacting the rough buffer layer; and a graded aluminum gallium nitride layer overlying the aluminum nitride layer and having an atomic percentage of aluminum that is graded from top to bottom. In some embodiments, the present disclosure provides another semiconductor device including: a silicon substrate; a group III-V buffer structure overlying the silicon substrate; a group III-V heterojunction structure overlying the group III-V buffer structure; a pair of source/drain electrodes overlying the group III-V heterojunction structure; a gate electrode overlying the group III-V heterojunction structure, laterally between the source/drain electrodes; a buffer layer between the silicon substrate and the group III-V buffer structure; and a 2DHG in the buffer layer, wherein a top surface of the buffer layer and/or a bottom surface of the buffer layer is/are configured to scatter mobile holes in the 2DHG to reduce carrier mobility at the 2DHG. In some embodiments, the top and bottom surfaces of the buffer layer have a plurality of randomly sized bumps arranged throughout. In some embodiments, one of the top and bottom surfaces of the buffer layer is rough compared to another one of the top and bottom surfaces of the buffer layer. In some embodiments, the buffer layer includes silicon doped with an n-type dopant, wherein the silicon substrate is substantially devoid of the n-type dopant. In some embodiments, the group III-V buffer structure includes a group III-V layer consisting essentially of aluminum and nitride, wherein the group III-V layer overlies and directly contacts the buffer layer. In some embodiments, the buffer layer consists essentially of doped silicon. In some embodiments, the present application provides a method for forming a semiconductor device, the method including: depositing a rough buffer layer over and directly contacting a top surface of a substrate, wherein the depositing of the rough buffer layer roughens the top surface of the substrate; depositing a seed buffer layer over and directly contacting the rough buffer layer; forming heterojunction structure overlying the seed buffer layer; forming a pair of source/drain electrodes on the heterojunction structure; and forming a gate electrode on the heterojunction structure, laterally between the source/drain electrodes. In some embodiments, the rough buffer layer is deposited in a first process chamber, wherein the seed buffer layer is deposited in a second process chamber different than the first process chamber. In some embodiments, the depositing of the rough buffer layer includes MOCVD using a first precursor including silicon and a second precursor including carbon, magnesium, or zinc. In some embodiments, the depositing of the rough buffer layer is performed by a silicon epitaxial tool and forms the rough buffer layer including silicon doped with arsenic or phosphorous. In some embodiments, the rough buffer layer and the seed buffer layer are deposited in a common process chamber. In some embodiments, the rough buffer layer and the seed buffer layer are deposited by a shared MOCVD process, wherein the shared MOCVD process includes: introducing a first precursor, but not a second precursor, into the common process chamber to form the rough buffer layer; and after forming the rough buffer layer, introducing both the first and second precursors into the common process chamber to form the seed buffer layer. In some embodiments, the seed buffer layer induces formation of a 2DHG along the top surface of the substrate. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 69,996 |
11862721 | DETAILED DESCRIPTION Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement. In the following description, semiconductor devices/semiconductor die, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation. FIG.1Ais a top view of a semiconductor device100A according to some embodiments of the present disclosure, andFIG.1Bis a cross-sectional view taken along a line1B-1B′ inFIG.1A. The semiconductor device100may be a semiconductor die including a semiconductor substrate102and an integrated circuit package over the semiconductor substrate102. In some embodiments, the semiconductor die may be obtained by dicing/scribing a wafer with layers or components thereon. The semiconductor substrate102has a central area104and a peripheral area106enclosing the central area and defining a boundary of the semiconductor device100A. The central area104can serve as an active area. The active components (e.g. the integrated circuit package or transistors) may be located within the central area104. The exemplary materials of the semiconductor substrate102can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI), or other suitable semiconductor materials. In some embodiments, the semiconductor substrate102can include, for example but are not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the semiconductor substrate102can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxy (epi) layer, or combinations thereof. The semiconductor device100A further includes nitride-based semiconductor layers110and112, a gate structure114, a passivation layer120, a pair of source/drain (S/D) electrodes122and124, a passivation structure126, vias140and142, a patterned conductive layers144and146, and conformal passivation layers148,150, and152. The nitride-based semiconductor layer110is disposed over the semiconductor substrate102. The nitride-based semiconductor layer110is at least disposed within the central area104and the peripheral area106. The exemplary materials of the nitride-based semiconductor layer110can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1−x−y)N where x+y≤1, AlyGa(1−y)N where y≤1. In some embodiments, the semiconductor device100A may further includes a nucleation layer (not illustrated) between the semiconductor substrate102and the nitride-based semiconductor layer110. The exemplary material of the nucleation layer can include, for example but is not limited to AlN. In some embodiments, the semiconductor device100A may further includes a buffer layer (not illustrated) between the semiconductor substrate102and the nitride-based semiconductor layer110. The exemplary materials of the buffer layer can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, GaAs, InN, AlN, InGaN, AlGaN, InAlGaN, or combinations thereof. The buffer layer is provided for reducing lattice and thermal mismatches between the semiconductor substrate102and a layer to be formed above the buffer layer (e.g. epitaxially formed thereon), thereby curing defects due to the mismatches. The nitride-based semiconductor layer112is disposed on the nitride-based semiconductor layer110. The nitride-based semiconductor layer112is disposed within the central area104and the peripheral area106. The exemplary materials of the nitride-based semiconductor layer112can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1−x−y)N where x+y≤1, AlyGa(1−y)N where y≤1. The exemplary materials of the nitride-based semiconductor layers110and112are selected such that the nitride-based semiconductor layer112has a bandgap (i.e. forbidden band width) greater than a bandgap of the nitride-based semiconductor layer110, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer110is an undoped GaN layer having bandgap of approximately 3.4 eV, the nitride-based semiconductor layer112may be an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers110and112serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region113adjacent to the heterojunction. Accordingly, the semiconductor device100A can include the integrated circuit package with at least one GaN-based high-electron-mobility transistor (HEMT). A gate structure114is disposed on the nitride-based semiconductor layer112. The gate structure114is disposed within the central area104. The gate structure114includes a p-type doped III-V compound semiconductor layer116and a conductive gate118. The p-type doped III-V compound semiconductor layer116and the conductive gate118are stacked on the nitride-based semiconductor layer112. The p-type doped III-V compound semiconductor layer116is between the nitride-based semiconductor layer112and the conductive gate118. In some embodiments, the gate structure140may further include a dielectric layer (not illustrated) between the p-type doped III-V compound layer116and the conductive gate118. The semiconductor device100A is an enhancement mode device, which is in a normally-off state when the conductive gate118is at approximately zero bias. Specifically, the p-type doped III-V compound layer116creates a p-n junction with the nitride-based semiconductor layer112to deplete the 2DEG region113, such that a zone of the 2DEG region113corresponding to a position below the gate structure114has different characteristics (e.g. different electron concentrations) than the rest of the 2DEG region113and thus is blocked. Due to such mechanism, the semiconductor device100A has a normally-off characteristic. In other words, when no voltage is applied to the conductive gate118or a voltage applied to the conductive gate118is less than a threshold voltage (i.e. a minimum voltage required to form an inversion layer below the gate structure114), the zone of the 2DEG region113below the gate structure114is kept blocked, and thus no current flows therethrough. Moreover, by providing the p-type doped III-V compound semiconductor layer116, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved. The exemplary materials of the p-type doped III-V compound layer116can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd. In some embodiments, the nitride-based semiconductor layer110includes undoped GaN and the nitride-based semiconductor layer112includes AlGaN, and the p-type doped III-V compound layer116is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region113, so as to place the semiconductor device100A into an off-state condition. In some embodiments, the conductive gate118may include metals or metal compounds. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys thereof, or other metallic compounds. In some embodiments, the exemplary materials of the conductive gate118may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof. In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiOxlayer, a SiNxlayer, a high-k dielectric material (e.g., HfO2, Al2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, etc), or combinations thereof. The passivation layer120is disposed over the nitride-based semiconductor layer112. The passivation layer120is disposed within the central area104and the peripheral area106. The passivation layer120covers the gate structure114for a protection purpose. The passivation layer120is conformal with the gate structure114and thus has a projection profile over the gate structure114. The exemplary materials of the passivation layer120can include, for example but are not limited to, SiNx, SiOx, SiON, SiC, SiBN, SiCBN, oxides, nitrides, or combinations thereof. In some embodiments, the passivation layer120is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof. The S/D electrodes122and124are disposed on the nitride-based semiconductor layer112. The S/D electrodes122and124are disposed within the central area104. The S/D electrodes122and124are located at two opposite sides of the gate structure114(i.e. the gate structure114is located between the S/D electrodes122and124). The gate structure114and the S/D electrodes122and124can collectively act as a GaN-based HEMT with the 2DEG region113. The S/D electrodes122and124have bottom portions penetrating the passivation layer120to form interfaces with the nitride-based semiconductor layer112. The S/D electrodes122and124have top portions wider than the bottom portions thereof. The top portions of the S/D electrodes122and124extend over portions of the passivation layer120. In the exemplary illustration ofFIG.1B, the left and right S/D electrodes122and124serve as source and drain electrodes, respectively. The S/D electrodes122and124may be optionally asymmetrical about the gate structure114. The left S/D electrode122is closer to the gate structure114than the right S/D electrode124. The present disclosure is not limited thereto, and the configuration of the S/D electrodes122and124is adjustable. In some embodiment, each of the S/D electrodes122and124includes one or more conformal conductive layers. In some embodiments, the S/D electrodes122and124can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), other conductor materials, or combinations thereof. The exemplary materials of the S/D electrodes122and124can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. In some embodiments, each of the S/D electrodes122and124forms ohmic contact with the nitride-based semiconductor layer112. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials for the S/D electrodes122and124. In some embodiments, a dielectric layer (not illustrated), such as SiN, can be disposed between the nitride-based semiconductor layer112and the S/D electrodes122and124. The passivation structure126is disposed above the passivation layer120and the S/D electrodes122and124. The passivation structure126is disposed within the central area104and the peripheral area106. The passivation structure126covers the GaN-based HEMT. The passivation structure126includes passivation layers128and130. The passivation layer128covers the S/D electrodes122and124. The passivation layer128forms interfaces with sidewalls and top surfaces of the S/D electrodes122and124. The passivation layer130is disposed on the passivation layer128. The passivation layer128can serve as an inter-layer dielectric (ILD) layer and the passivation layer130can serve as an inter-metal dielectric (IMD) layer, respectively. The passivation layer128may have a flat topmost surface, which is able to act as a flat base for carrying layers formed in a step subsequent to the formation thereof. For example, the passivation layer128may have a flat topmost surface for carrying the passivation layer130. The exemplary materials of the passivation layer128or130can include, for example but are not limited to, SiNx, SiOx, SiON, SiC, SiBN, SiCBN, oxides, nitrides, or combinations thereof. In some embodiments, the passivation layer128or130is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof. In some embodiments, the passivation layer128is thicker than either the passivation120or the nitride-based semiconductor layer112. The vias140at least penetrate the passivation layer128to connect to the S/D electrodes122and124. At least one of the vias140further penetrates the passivation layer120to form an interface with the conductive gate118. The exemplary materials of the vias can include, for example but are not limited to, Cu, Al, or combinations thereof. The patterned conductive layer144is disposed on the passivation layer128and is covered with the passivation layer130. The patterned conductive layer144has a plurality of metal lines over the gate structure114and the S/D electrodes122and124for the purpose of implementing interconnects between circuits. The metal lines are in contact with the vias140, respectively, such that the gate structure114and the S/D electrodes122and124can be arranged into a circuit. For example, the GaN-based HEMT can be electrically connected to other component(s) via the metal lines of the patterned conductive layer144. In other embodiments, the patterned conductive layer144may include pads or traces for the same purpose. The vias142penetrate the passivation layer130to connect to the metal lines of the patterned conductive layer144. Each of the vias142may include a conductive layer142aand a conductive layer142bwrapping the conductive layer142a. The conductive layer142bcan serve as an etching stop layer during the formation of the vias142. The exemplary materials of the conductive layer142acan include, for example but are not limited to, Cu, Al, or combinations thereof. The exemplary materials of the conductive layer142bcan include, for example but are not limited to, Ti, TiN, or combinations thereof. Edges of the nitride-based semiconductor layers110and112, the passivation layer120, and the passivation structure126can collectively form a stepped sidewall160over the semiconductor substrate102. Herein, the phrase “stepped sidewall” may mean that a structure having a stepped profile over the semiconductor substrate102, which includes at least two riser portions162and164with at least one laterally-extending portion166connecting the riser portions162and164. The stepped sidewall160can be called a stepped structure. The stepped sidewall160can be located within the peripheral area106. In the exemplary illustration ofFIG.1B, from the bottom of the stepped sidewall160(i.e. from the interface between the semiconductor substrate102and the nitride-based semiconductor layer110), there are the riser portion164, the laterally-extending portion166, and the riser portion162. The topmost riser portion162connects with the topmost surface of the passivation structure126. In the exemplary illustration ofFIG.1B, the laterally-extending portion166of the stepped sidewall160is formed at the edge of the passivation layer128. The passivation layer128can have a laterally extending region132at its edge to form the two riser portions162and164. In other words, the passivation layer128has an upper side surface134and a lower side surface136which are separated from each other by the laterally extending region132. The upper and lower side surfaces134and136connect to two opposite sides of the laterally extending region132, respectively (e.g. left and right sides of the laterally extending region132inFIG.1B). The upper side surface134of the passivation layer128and a side surface of the passivation layer130form the riser portion162above the laterally extending region132/laterally-extending portion166. The lower side surface136of the passivation layer128, a side surface of the passivation layer120, side surfaces of the nitride-based semiconductor layers110and112, and a side surface of the semiconductor substrate102form the riser portion164below the laterally extending region132/laterally-extending portion166. The profile of the stepped sidewall160enables layers formed after the formation of the passivation structure126to morphologically adapt to the resultant structure, which is able to improve the yield rate of the manufacturing processes for the semiconductor device100A. More details on such issue are provided as follows. The conformal passivation layer148is disposed above/over the passivation structure126. The conformal passivation layer148extends downwardly from a position above the stepped sidewall160to the semiconductor substrate102along the stepped sidewall160. The conformal passivation layer148extends from the central area104to the peripheral area106. The conformal passivation layer148can act as a protection layer for the underlying layers. The conformal passivation layer148include at least one dielectric material. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiOxlayer, a SiNxlayer, a high-k dielectric material (e.g., HfO2, Al2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, etc), or combinations thereof. The conformal passivation layer148covers the stepped sidewall160. The conformal passivation layer148at least covers the edges of the nitride-based semiconductor layers110and112, the passivation layer120, and the passivation structure126. The conformal passivation layer148is conformal with the stepped sidewall160and thus has a stepped profile. The conformal passivation layer148has a laterally extending portion and two riser portions corresponding to those of the stepped sidewall160. The laterally extending portion of the conformal passivation layer148is over the laterally extending portion166of stepped sidewall160. The laterally extending portion of the conformal passivation layer148is over the laterally extending region132of the passivation layer128. The semiconductor substrate102can accommodate the conformal passivation layer148. The semiconductor substrate102has a recess103accommodating the conformal passivation layer148. The recess103of the semiconductor substrate102has a side surface and a bottom surface connected with each other (i.e. sharing the same side/line). The conformal passivation layer extends across an interface formed between the side surface of the nitride-based semiconductor110layer and the recess103and then laterally extends on the bottom surface of the recess103. With respect to the configuration that the conformal passivation layer148extends to the recess103of the semiconductor substrate102, the stepped sidewall160is formed to avoid the low yield rate of the manufacturing processes for the semiconductor device100A. To demonstrate how the configuration ofFIG.1Baffects a yield rate,FIG.2is a cross-sectional view schematically showing a semiconductor device10according to a comparative embodiment. The semiconductor device10incudes a multi-layer stacked structure14with a continuous sidewall (i.e. without any stepped profile) over a substrate12and a deposited layer16above the multi-layer stacked structure14. The substrate12forms a deep corner18with the multi-layer stacked structure14. The deposited layer16can be formed by using a sputtering process. Alternatively, the deposition layer16may be a seed layer for an electroplating process. Since the first step of the electroplating process is formation of a seed layer, no matter which process is applied (i.e. a sputtering process or an electroplating process), a deposition technique is required. However, when the deposition is performed for layer16extending along the continuous sidewall to the substrate12, the deposited layer16contains accumulated stress at a portion near the deep corner18, which is caused by a continuous sidewall that is too high. As such, the portion of the deposited layer16near the deep corner18would have an unpredictable profile. For example, due to the accumulated stress, such portion may become deformed and thus be separated from the deep corner18or from the continuous sidewall, which will decrease the yield rate. The deformed portion of the deposited layer16may be separated from the continuous sidewall by a gap20(e.g. air gap), which will cause the semiconductor device10to fail during subsequent processes. For example, during manufacturing processes for a plurality of semiconductor devices on a wafer, one of the processes is to dice the wafer for separating the semiconductor devices from each other. Once a layer in the semiconductor devices is deformed and thus is separated from the underlying base, it will lead to peeling and damage the resulting semiconductor devices. Referring toFIG.1Bagain, since the stepped sidewall160can provide an additional corner between the riser portion162and the laterally-extending portion166, the distribution of the stress is rearranged, which substantially reduces the accumulated stress at a deep corner (i.e. at a position between the side and bottom surfaces of the recess103). Furthermore, the stepped sidewall160also reduces the average slope for the conformal passivation layer148, so as to avoid excessive stress accumulating in the conformal passivation layer148. Herein, the phrase “average slope” may mean a ratio of a height to an extending length of the conformal passivation layer148. For example, for a fixed height, the stepped sidewall160would make the conformal passivation layer148have a longer extending path, thus reducing the average slope for the conformal passivation layer148. As such, the conformal passivation layer148at the deep corner can morphologically adapt to the profile of the deep corner. For example, the recess103of the semiconductor substrate102can accommodate the conformal passivation layer148in a way such that the conformal passivation layer148covers the side and bottom surfaces of the recess103. In some embodiments, the conformal passivation layer148can entirely cover the side and bottom surfaces of the recess103. Therefore, without undesirable deformation, the conformal passivation layer148can have improved uniformity, thereby avoiding the peeling during dicing and improving the yield rate of the manufacturing processes for the semiconductor device100A. Moreover, at least one of the riser portions162and164can form an obtuse angle with respect to the bottom surface of the recess103, which will be advantageous to reduce the average slope of the conformal passivation layer148. In the exemplary illustration ofFIG.1B, both the riser portions162and164are oblique to the bottom surface of the recess103and form obtuse angles therebetween. In some embodiments, the two obtuse angles formed by the riser portions162and164with respect to the bottom surface of the recess103can be the same. In other embodiments, the two obtuse angles formed by the riser portions162and164with respect to the bottom surface of the recess103can be different. Furthermore, the laterally-extending portion166of the stepped sidewall160is formed at the edge of the passivation layer128so that the passivation layer128is relatively thicker than other adjacent layers. For example, the passivation layer128is relatively thicker than the nitride-based semiconductor layer112and the passivation layer120. Accordingly, the laterally-extending portion166of the stepped sidewall160occurring at an interface between two different layers can be avoided, so as to prevent the yield rate from decreasing. Once the laterally-extending portion166of the stepped sidewall160occurs at an interface between two different layers, the upper layer may easily detach from the lower layer, decreasing the yield rate. The conformal passivation layer150is disposed above/over the conformal passivation layer148. The conformal passivation layer152is disposed above/over the conformal passivation layer150. The conformal passivation layers150and152extend downwardly from a position above the stepped sidewall160toward the recess103of the semiconductor substrate102. The conformal passivation layers150and152extend from the central area104to the peripheral area106. The conformal passivation layers150and152can act as protection layers for the underlying layers. The conformal passivation layer150may include metals or metal compounds. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys thereof, or other metallic compounds. The conformal passivation layer152include at least one dielectric material. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiOxlayer, a SiNxlayer, a high-k dielectric material (e.g., HfO2, Al2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, etc), or combinations thereof. A method for manufacturing the semiconductor device is provided. Different stages of a method for manufacturing the semiconductor device100A are shown inFIGS.3A-3M.FIG.3Ais top view of a wafer with layers thereon,FIG.3Bis a cross-sectional view taken along a line3B-3B′ inFIG.3A, andFIGS.3C-3Mare different stage followingFIG.3B. Referring toFIGS.3A and3B, a wafer can be designed as having a plurality of semiconductor device areas202with active areas204. The semiconductor device areas202may be separated by cutting scribe lines206. In some embodiments, the scribe lines206are achieved by forming trenches, and the cutting is performed along the trenches. The details regarding the trenches are provided as follows. As shown inFIG.3B, a semiconductor substrate102is provided, and nitride-based semiconductor layers110and112are formed above the semiconductor substrate102in sequence. In some embodiments, the nitride-based semiconductor layers110and112can be formed by using deposition techniques. The deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), epitaxial growth, or other suitable processes. A gate structure114is formed above the nitride-based semiconductor layers110and112. The formation of the gate structure114includes forming a p-type doped III-V compound layer116and forming a conductive gate118in sequence. The formation of the gate structure114can be achieved by using deposition techniques and a series of lithographic processes. The deposition techniques can include, for example but are not limited to, ALD, PVD, CVD, MOCVD, epitaxial growth, or other suitable processes. The series of lithographic processes include applying a photoresist layer, etch, development, and/or other suitable processes. A passivation layer120is formed to cover the gate structure114. The formation of the passivation layer120can be achieved by using deposition techniques. The deposition techniques can include, for example but are not limited to, ALD, PVD, CVD, MOCVD, epitaxial growth, or other suitable processes. After the formation of the passivation layer120, at least an etching process is performed to removing portions of the passivation layer120, so as to form openings that can serve as S/D regions. S/D electrodes122and124are formed in the S/D regions and over the passivation layer120. In some embodiments, the formation of the S/D electrodes includes forming more than one layer by using deposition techniques and a series of lithographic processes. The deposition techniques can include, for example but are not limited to, ALD, PVD, CVD, MOCVD, epitaxial growth, or other suitable processes. The series of lithographic processes include applying a photoresist layer, etch, development, and/or other suitable processes, so as to pattern the formed layers as the S/D electrodes122and124. A passivation layer128is formed on the nitride-based semiconductor layer112to cover the gate structure114and the S/D electrodes122and124. In some embodiments, the passivation layer128can be formed by using deposition techniques. The deposition techniques can include, for example but are not limited to, ALD, PVD, CVD, MOCVD, epitaxial growth, or other suitable processes. After the formation of the passivation layer, portions of the passivation layer128are removed for forming vias140within the passivation layer128. The formation of the vias140includes forming a conductive layer within and over the passivation layer128and removing the excess portions of the conductive layer. In some embodiments, a planarization process is performed to remove the excess portions of the conductive layer. In some embodiments, the planarization process includes a chemical mechanical polish (CMP) process. A patterned conductive layer144is formed on the passivation layer128. The formation of the patterned conductive layer144includes forming a blanket conductive layer on the passivation layer128by using deposition techniques. The deposition techniques can include, for example but are not limited to, ALD, PVD, CVD, MOCVD, epitaxial growth, or other suitable processes. A patterning process is performed on the blanket conductive layer to form the patterned conductive layer144including metal lines in contact with the vias140, respectively. The patterning process can be performed by photolithography, exposure and development, etching, other suitable processes, or combinations thereof. A passivation layer130is formed on the passivation layer128to cover the patterned conductive layer144. In some embodiments, the passivation layer130can be formed by using deposition techniques. The deposition techniques can include, for example but are not limited to, ALD, PVD, CVD, MOCVD, epitaxial growth, or other suitable processes. The passivation layers128and130can collectively serve as a passivation structure126. After the formation of the passivation structure126, portions of the passivation layer130are removed for forming conductive layers210and212in and over the passivation layer130. The formation of the conductive layer210is prior to the formation of the conductive layer212. Some portions of the conductive layer210are between the passivation layer130and the conductive layer212. Referring toFIG.3C, a step of etching back the conductive layer212is performed with the conductive layer210acting as an etching stop layer, such that the etching back is performed until the conductive layer210is exposed. After the etching back, portions of the conductive layer210over the passivation layer are removed. The remained portions of the conductive layers210and212serve as vias142in contact with the metal lines of the patterned conductive layer144. Referring toFIG.3D, a photoresist layer220with an opening222is formed on the passivation structure126. The vias142are covered with the photoresist layer220. At least one portion of the passivation structure126is exposed from the opening222of the photoresist layer220. The photoresist layer220with the opening222may be formed by a series of treatments, such as coating (e.g., by spin coating), mask aligning, exposure, developing, and other suitable processes. Referring toFIG.3E, portions of the passivation layers128and130are remove by using the photoresist layer (i.e. the photoresist layer220ofFIG.3D). The portions of the passivation layers128and130are remove to form a trench224. The trench224can be formed by, for example but is not limited to, etching technique (an etching process such as dry etching or wet etching), laser technique (laser drill or laser cutting) or other suitable technique. The trench224is formed under the opening of the photoresist layer (i.e. the opening222of the photoresist layer220ofFIG.3D) by the etching process. The trench224has a bottom226within the passivation layer128. Herein, the phrase “a bottom226within the passivation layer128” may mean the bottom226is under a topmost surface of the passivation layer128and over a bottommost surface of the passivation layer128. The trench224has sidewall228angle forming an obtuse angle with the bottom thereof. The photoresist layer is removed after the etching process. Referring toFIG.3F, a photoresist layer230with an opening232is formed on the passivation structure126. The opening232of the photoresist layer230is wider than the topmost portion of the trench224. The opening232of the photoresist layer230is wider than the opening of the photoresist layer that is applied to the previous etching process (i.e. the opening222of the photoresist layer220ofFIG.3D). Portions of the topmost surface of the passivation structure126are exposed from the opening232of the photoresist layer230. The photoresist layer230with the opening232may be formed by a series of treatments, such as coating (e.g., by spin coating), mask aligning, exposure, developing, and other suitable processes. Referring toFIG.3G, portions of the passivation structure126, portions of the passivation layer120, portions of the nitride-based semiconductor layers110and112, and portions of the semiconductor substrate102are removed by using the photoresist layer (i.e. the photoresist layer230ofFIG.3F). The removal can be achieved by, for example but is not limited to, etching technique (an etching process such as dry etching or wet etching), laser technique (laser drill or laser cutting) or other suitable technique. During the etching process, the trench224is widened and deepened. The etching process is terminated after the semiconductor substrate102is exposed from the trench224. When the etching process is terminated, the semiconductor substrate102has a recess103resulted from the etching process. Since the applied photoresist layer (i.e. the photoresist layer230ofFIG.3F) has the opening wider than the trench (i.e. the trench ofFIG.3F) and exposes the topmost portion of the passivation structure126(as shown inFIG.3F), the trench224can be widened by removing those exposed topmost portion of the passivation structure126and the underlying portions thereof. The trench224can be deepened by at least removing the portions under the bottom of the trench224. As a result, the etching process can make edges of the passivation structure126, the passivation layer120, the nitride-based semiconductor layers110and112, and the semiconductor substrate102become stepped, so as to form a stepped sidewall160for them. As the profile/boundary of the trench224can be defined by the edges of the passivation structure126, the passivation layer120, the nitride-based semiconductor layers110and112, and the semiconductor substrate102, the trench224also has a stepped sidewall over the semiconductor substrate102. The photoresist layer is removed after the etching process. Referring toFIG.3H, a conductive layer146is formed on the passivation structure126. The conductive layer146is blanket formed and accommodated by the recess103of the semiconductor substrate102. The conductive layer146extends from a position higher than the passivation structure126into the trench224to cover the exposed semiconductor substrate102. The conductive layer146can be formed by a deposition process. For example, the deposition process is a PVD process, such as sputtering deposition. In some embodiments, the conductive layer146can serve as a seed layer for an electroplating process. As afore-described, the stepped sidewall160can improve the uniformity of the conductive layer146by distributing the stress of the conductive layer146such that the stress thereof is prevented from accumulating at a deep corner of the recess103of the semiconductor substrate102, thereby avoiding the deformation of the conductive layer146. Referring toFIG.3I, a photoresist layer240with more than one opening is formed on the conductive layer146. The photoresist layer240is free of extending into the trench224. The photoresist layer240is formed for a subsequent patterning process to the conductive layer146. The photoresist layer240can define location and shape of the conductive layer146after the subsequent patterning process. The conductive layer146under the photoresist layer240can be remained after the subsequent patterning process. The photoresist layer240with the openings may be formed by a series of treatments, such as coating (e.g., by spin coating), mask aligning, exposure, developing, and other suitable processes. Referring toFIG.3J, a patterning process is performed on the conductive layer146by using the photoresist layer (i.e. the photoresist layer240ofFIG.3I). As aforementioned, portions of the conductive layer146exposed from the photoresist layer would be removed, and thus the portions of the conductive layer146in the trench246are removed. The remained conductive layer146is called patterned conductive layer146and can serve as metal lines in contact with the vias. Referring toFIG.3K, a conformal passivation layer148is formed above the passivation structure126. The conformal passivation layer148covers the metal lines of the patterned conductive layer146. The conformal passivation layer148extends into the trench224. Similarly, the stepped sidewall160can prevent the stress of the conformal passivation layer148from accumulating at the deep corner of the recess103of the semiconductor substrate102, which will be advantageous to improve the yield rate of the processes. Referring toFIG.3L. Conformal passivation layers150and152are formed above the conformal passivation layer148. With the stepped profile of the conformal passivation layer148, deformation of the conformal passivation layers150and152at the deep corner is prevented. In some embodiments, the conformal passivation layers150and152can be omitted, and thus the protection layer148is the topmost layer for the resulted structure. In some embodiments, at least one conformal passivation layer (not illustrated) is still formed above the conformal passivation layer152. The number of the conformal passivation layers is adjustable. Referring toFIG.3M. The wafer with the layers as set forth above is diced to separate different semiconductor devices. During the dicing, the trench224can serve as a scribe region/line250. In some embodiments, a cutter can be operated to cut the conformal passivation layers148,150, and152and the semiconductor substrate102along the scribe region/line250overlapping the trench224. Since the conformal passivation layers148,150, and152can well adapt to the profile of the trench224, it avoids peeling/separation during the dicing. After the dicing, the resultant structure can be shown asFIGS.1A and1B. Furthermore, because the conformal passivation layers148,150, and152and the semiconductor substrate102are simultaneously cut, they would have distant side surfaces in a continuous profile. In the following, different structures with the stepped sidewalls are provided, demonstration that the semiconductor device with the stepped sidewall of the present disclosure has high adaptability and the manufacturing process thereof is flexible. FIG.4is a cross-sectional view of a semiconductor device100B according to some embodiments of the present disclosure. In this embodiment, the patterned conductive layer146further extends to cover the semiconductor substrate102. More specifically, patterned conductive layer146further extends downwardly from a position above the passivation structure126to the semiconductor substrate102. The patterned conductive layer146directly covers the stepped sidewall160. The recess103of the semiconductor substrate102accommodates the patterned conductive layer146. The conformal passivation layer148is above the patterned conductive layer146. The conformal passivation layer148fills a space between the metal lines of the patterned conductive layer146. In the recess103of the semiconductor substrate102, the conformal passivation layer148is in a position above the patterned conductive layer146. Similarly, the semiconductor device100B is obtained by dicing a wafer, and thus the patterned conductive layer146, the conformal passivation layers148,150, and152, and the semiconductor substrate102can have distant side surfaces with a continuous profile. To manufacture the semiconductor device100B, the processes used may be similar to those used for semiconductor device100A.FIG.5is a stage for manufacturing a semiconductor device100B according to some embodiments of the present disclosure. InFIG.5, a photoresist layer260is modified as further covering the conductive layer146in the trench224. With the photoresist layer260, after performing a patterning process, the patterned conductive layer146directly covers the stepped sidewall160. Thereafter, the conformal passivation layers148,150, and152are formed on the patterned conductive layer146in sequence, and dicing a wafer is performed, thereby obtaining the semiconductor device100B as shown inFIG.4. FIG.6is a cross-sectional view of a semiconductor device100C according to some embodiments of the present disclosure. InFIG.6, the laterally-extending portion166of the stepped sidewall160is formed at the edge of the nitride-based semiconductor layer110. The nitride-based semiconductor layer110can have a laterally extending region111at its edge to form the two riser portions162and164. The nitride-based semiconductor layer110may have an upper side surface110U and a lower side surface110L which are separated from each other by the laterally extending region111. The upper and lower side surfaces110U and110L connect to two opposite sides of the laterally extending region111, respectively (e.g. left and right sides of the laterally extending region111inFIG.6). The upper and lower side surfaces110U and110L are covered with the conformal passivation layer148. The laterally extending region111is under the laterally extending portion of the conformal passivation layer148. In some embodiments, the upper and lower side surfaces110U and110L are entirely covered with the conformal passivation layer148. The upper side surface110U of the nitride-based semiconductor layer110, side surfaces of the nitride-based semiconductor layer112, the passivation layer120, and the passivation structure126form the riser portion162above the laterally extending region111. The lower side surface110L of the nitride-based semiconductor layer110and a side surface of the recess103of the semiconductor substrate102form the riser portion164below the laterally extending region111. The laterally-extending portion166of the stepped sidewall160is formed at the edge of the nitride-based semiconductor layer110because the nitride-based semiconductor layer110is relatively thicker than other adjacent layers. For example, the nitride-based semiconductor layer110is relatively thicker than the nitride-based semiconductor layer112and the passivation layer120. Accordingly, the laterally-extending portion166of the stepped sidewall160occurring at an interface between two different layers may be avoided, so as to prevent the yield rate from decreasing. To manufacture the semiconductor device100C, the processes thereof are similar with that of the semiconductor device100A.FIGS.7A-7Care stages for manufacturing a semiconductor device100C according to some embodiments of the present disclosure. InFIG.7A, the trench224is deeper than the trench224ofFIG.3E. The trench224exposes the nitride-based semiconductor layer110. The etching process is terminated after portions of the nitride-based semiconductor layer110are removed. The trench224is formed by further removing portions of the passivation structure126, the passivation layer120, and the nitride-based semiconductor layers110and112. Referring toFIG.7B, a photoresist layer270with an opening272is formed on the passivation structure126. The opening272of the photoresist layer270is wider than the topmost portion of the trench224. The opening272of the photoresist layer270is wider than the opening of the photoresist layer that is applied to the previous etching process (e.g. the opening222of the photoresist layer220ofFIG.3D). Portions of the topmost surface of the passivation structure126are exposed from the opening272of the photoresist layer270. The photoresist layer270with the opening272may be formed by a series of treatments, such as coating (e.g., by spin coating), mask aligning, exposure, developing, and other suitable processes. Referring toFIG.7C, portions of the passivation structure126, portions of the passivation layer120, portions of the nitride-based semiconductor layers110and112, and portions of the semiconductor substrate102are removed by using the photoresist layer (i.e. the photoresist layer270ofFIG.7A). The removal can be achieved by, for example but is not limited to, etching technique (an etching process such as dry etching or wet etching), laser technique (laser drill or laser cutting) or other suitable technique. During the etching process, the trench224is widened and deepened. The etching process is terminated after the semiconductor substrate102is exposed. When the etching process is terminated, the semiconductor substrate102has a recess103resulted from the etching process. By widening and deepening the trench224, the etching process can make edges of the passivation structure126, the passivation layer120, the nitride-based semiconductor layers110and112, and the semiconductor substrate102become stepped, so as to form a stepped sidewall160over the semiconductor substrate102for them. Thereafter, a patterned conductive layer146and conformal passivation layers148,150, and152are formed on the passivation structure126in sequence, and dicing a wafer is performed, thereby obtaining the semiconductor device100C as shown inFIG.6. FIG.8is a cross-sectional view of a semiconductor device100D according to some embodiments of the present disclosure. In the embodiment ofFIG.8, the patterned conductive layer146extends to cover the semiconductor substrate102. More specifically, the patterned conductive layer146further extends downwardly from a position above the passivation structure126to the semiconductor substrate102. The patterned conductive layer146directly cover the stepped sidewall160. The patterned conductive layer146changes extending directions twice at the nitride-based semiconductor layer110. The recess103of the semiconductor substrate102accommodates the patterned conductive layer146. The conformal passivation layer148is above the patterned conductive layer146. The conformal passivation layer148fills the space between the metal lines of the patterned conductive layer146. In the recess103of the semiconductor substrate102, the conformal passivation layer148is in a position above the patterned conductive layer146. Similarly, the semiconductor device100D is obtained by dicing a wafer, and thus the patterned conductive layer146, the conformal passivation layers148,150, and152, and the semiconductor substrate102can have distant side surfaces in a continuous profile. To manufacture the semiconductor device100D, the processes thereof are similar with that of the semiconductor device100C.FIG.9is a stage for manufacturing a semiconductor device100D according to some embodiments of the present disclosure. InFIG.9, the photoresist layer280is modified as further covering the conductive layer146in the trench224. With the photoresist layer280, after performing a patterning process, the patterned conductive layer146would directly cover the stepped sidewall160. Thereafter, the conformal passivation layers148,150, and152are formed on the patterned conductive layer146in sequence, and dicing a wafer is performed, thereby obtaining the semiconductor device100D as shown inFIG.8. FIG.10is a cross-sectional view of a semiconductor device100E according to some embodiments of the present disclosure. InFIG.10, the stepped sidewall160has three riser portions162,164, and165. The stepped sidewall160further has two laterally-extending portions166and167formed at the edges of the nitride-based semiconductor layer110and the passivation layer128, respectively. The laterally-extending portion166connects the riser portion162and the riser portion164. The laterally-extending portion167connects the riser portion164and the riser portion165. The stepped sidewall160of the semiconductor device100E may have a profile as a combination of stepped sidewalls160of the semiconductor devices100A and100C. The riser portions162,164, and165and the laterally-extending portions166and167collectively form/create plural steps for the stepped sidewall160. A side surface of the passivation layer130, an upper side surface of the passivation layer128forms the riser portion162. A lower side surface of the passivation layer128, side surfaces of the passivation layer120and the nitride-based semiconductor layer112, and an upper side surface of the nitride-based semiconductor layer110forms the riser portion164. A lower side surface of the passivation layer128and a side surface of the recess103of the semiconductor surface102forms the riser portion165. The lower side surface of the passivation layer128and the upper side surface of the nitride-based semiconductor layer110are present between the laterally extending portions166and167. To manufacture the semiconductor device100E, the processes thereof are similar with that of the semiconductor devices100A and100C.FIGS.11A-11Care stages for manufacturing a semiconductor device100E according to some embodiments of the present disclosure. InFIG.11A, the trench224is more shallow than the trench224ofFIG.3G. The trench224has been widened and deepened once. The trench224exposes the nitride-based semiconductor layer110. The etching process is terminated after portions of the nitride-based semiconductor layer110are removed. The trench224is widened and deepened by removing portions of the passivation structure126, the passivation layer120, and the nitride-based semiconductor layers110and112. The bottom of the trench224is separated from the semiconductor substrate102by at least one portion of the nitride-based semiconductor layer110. The semiconductor substrate102is kept the same after the first widening and deepening. Referring toFIG.11B, a photoresist layer290with an opening292is formed on the passivation structure126. The opening292of the photoresist layer290is wider than the topmost portion of the trench224. The opening292of the photoresist layer290is wider than the opening of the photoresist layer that is applied to the previous etching process (e.g. the photoresist layer for forming the trench224at first or for first widening and deepening the trench224). Portions of the topmost surface of the passivation structure126are exposed from the opening292of the photoresist layer290. The photoresist layer290with the opening292may be formed by a series of treatments, such as coating (e.g., by spin coating), mask aligning, exposure, developing, and other suitable processes. Referring toFIG.11C, portions of the passivation structure126, portions of the passivation layer120, portions of the nitride-based semiconductor layers110and112, and portions of the semiconductor substrate102are removed by using the photoresist layer (i.e. the photoresist layer290ofFIG.11B). The removal can be achieved by, for example but is not limited to, etching technique (an etching process such as dry etching or wet etching), laser technique (laser drill or laser cutting) or other suitable technique. During the etching process, the trench224is widened and deepened. The etching process is terminated after the semiconductor substrate102is exposed. When the etching process is terminated, the semiconductor substrate102has a recess103resulted from the etching process. By widening and deepening the trench224, the etching process can make edges of the passivation structure126, the passivation layer120, the nitride-based semiconductor layers110and112, and the semiconductor substrate102have a stepped sidewall160with two steps over the semiconductor substrate102. Thereafter, a patterned conductive layer146and conformal passivation layers148,150, and152are formed on the passivation structure126in sequence, and dicing a wafer is performed, thereby obtaining the semiconductor device100E as shown inFIG.10. FIG.12is a cross-sectional view of a semiconductor device100F according to some embodiments of the present disclosure. At least one difference between the present embodiment and the previous embodiments is that the patterned conductive layer146extends to cover the semiconductor substrate102. More specifically, the patterned conductive layer146further extends downwardly from a position above the passivation structure126to the semiconductor substrate102. The patterned conductive layer146directly cover the stepped sidewall160. The patterned conductive layer146changes extending directions twice at the edge of the passivation structure126and then changes extending directions twice at the nitride-based semiconductor layer110. The recess103of the semiconductor substrate102accommodates the patterned conductive layer146. The conformal passivation layer148is above the patterned conductive layer146. The conformal passivation layer148fills a space between the metal lines of the patterned conductive layer146. In the recess103of the semiconductor substrate102, the conformal passivation layer148is in a position above the patterned conductive layer146. Similarly, the semiconductor device100F is obtained by dicing a wafer, and thus the patterned conductive layer146, the conformal passivation layers148,150, and152, and the semiconductor substrate102can have distant side surfaces in a continuous profile. To manufacture the semiconductor device100F, the processes thereof are similar to that of the semiconductor device100E.FIG.13is a stage for manufacturing a semiconductor device100F according to some embodiments of the present disclosure. InFIG.13, the photoresist layer294is modified as further covering the conductive layer146in the trench224. With the photoresist layer294, after performing a patterning process, the patterned conductive layer146directly covers the stepped sidewall160. Thereafter, the conformal passivation layers148,150, and152are formed on the patterned conductive layer146in sequence, and dicing a wafer is performed, thereby obtaining the semiconductor device100F as shown inFIG.12. FIG.14is a top view of a semiconductor device100G according to some embodiments of the present disclosure. InFIG.14, the stepped sidewalls160L and160R of the semiconductor device100G have different widths W1and W2. The stepped sidewalls160L and160R are located at opposite sides of the central area104and within the same peripheral area106. The different widths W1and W2may result from asymmetrical dicing to a wafer. For example, a distance from a scribe line at the left side of the semiconductor device100G to the center of the semiconductor device100G differs from a distance from a scribe line at the right side of the semiconductor device100G to the center of the semiconductor device100G. The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 within within 20 within 10 or within 1 μm of lying along the same plane. As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component. While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. | 60,552 |
11862722 | Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, reference to the formation or disposal of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Embodiments of the present disclosure are discussed in detail as follows. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure. The present disclosure provides a semiconductor device structure including a barrier layer (or a hole barrier layer) with a bandgap greater than that of AlGaN. The barrier layer may restrain hole(s) being extracted by the gate structure through the depletion layer, and thus the reliability of the semiconductor device structure may be enhanced under high temperature reverse bias (HTRB). The barrier layer may restrain hole(s) accumulating in the depletion layer, and thus the reliability of the semiconductor device structure may be enhanced under high temperature gate bias (HTGB). The semiconductor device structure of the present disclosure can be applied in, without limitation, HEMT devices, especially in low voltage HEMT devices, high voltage HEMT devices and radio frequency (RF) HEMT devices. FIG.1is a cross-sectional view of a semiconductor device structure1ain accordance with some embodiments of the present disclosure. The semiconductor device structure1amay include a substrate10, a buffer layer20, a nitride semiconductor layer30, a nitride semiconductor layer40, an electrode51, an electrode52, a gate structure53, a barrier layer60aand a nitride semiconductor layer70. The substrate10may include, without limitation, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate10may include, without limitation, sapphire, silicon on insulator (SOI), or other suitable materials. The buffer layer20may be disposed on the substrate10. The buffer layer20may be configured to reduce defect due to the dislocation between the substrate10and the nitride semiconductor layer30. The buffer layer20may include, but is not limited to, nitride, such as AlN, AlGaN or the like. The nitride semiconductor layer30may be disposed on the buffer layer20. The nitride semiconductor layer30may include a group III-V layer. The nitride semiconductor layer30may include, but is not limited to, a group III nitride, for example, a compound InaAlbGa1-a-bN, in which a+b≤1. The group III nitride further includes, but is not limited to, for example, a compound AlaGa(1-a)N, in which a≤1. The nitride semiconductor layer30may include a gallium nitride (GaN) layer. GaN has a bandgap of about 3.4 eV. The thickness of the nitride semiconductor layer30may range, but is not limited to, from about 0.5 μm to about 10 μm. The nitride semiconductor layer40may be disposed on the nitride semiconductor layer30. The nitride semiconductor layer40may include a group III-V layer. The nitride semiconductor layer40may include, but is not limited to, a group III nitride, for example, a compound InaAlbGa1-a-bN, in which a+b≤1. The group III nitride may further include, but is not limited to, for example, a compound AlaGa(1-a)N, in which a≤1. The nitride semiconductor layer40may have a greater bandgap than that of the nitride semiconductor layer30. The nitride semiconductor layer40may include an aluminum gallium nitride (AlGaN) layer. AlGaN has a bandgap of about 4.0 eV. The thickness of the nitride semiconductor layer40may range, but is not limited to, from about 10 nm to about 100 nm. A heterojunction is formed between the nitride semiconductor layer40and the nitride semiconductor layer30, and the polarization of the heterojunction forms a two-dimensional electron gas (2DEG) region in the nitride semiconductor layer30. The electrode51(or a source electrode or a source structure) may be disposed on the nitride semiconductor layer40. The electrode51may be in contact with the nitride semiconductor layer40. The electrode51may include, for example, without limitation, a conductive material. The conductive materials may include metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials. The electrode51may be electrically connected to ground. The electrode51may be electrically connected to virtual ground. The electrode51may be electrically connected to real ground. The electrode52(or a drain electrode or a drain structure) may be disposed on the nitride semiconductor layer40. The electrode52may be in contact with the nitride semiconductor layer40. The electrode52may include, for example, without limitation, a conductive material. The conductive materials may include metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials. The nitride semiconductor layer70(or a depletion layer) may be disposed on the nitride semiconductor layer40. The nitride semiconductor layer70may be in direct contact with the nitride semiconductor layer40. The nitride semiconductor layer70may be doped with impurity. The nitride semiconductor layer70may include p-type dopants. It is contemplated that the nitride semiconductor layer70may include a p-doped GaN layer, p-doped AlGaN layer, p-doped AlN layer or other suitable III-V group layers. The p-type dopants may include magnesium (Mg), beryllium (Be), zinc (Zn) and cadmium (Cd). The nitride semiconductor layer70may be configured to control the concentration of the 2DEG in the nitride semiconductor layer30. The nitride semiconductor layer70can be used to deplete the 2DEG directly under the nitride semiconductor layer70. The nitride semiconductor layer70may include a surface701(or an upper surface), a surface702(or a side surface) and a surface703(or a lower surface). The surface701may be opposite the surface703. The surface702may extend from the surface701to the surface702. The surface703may be in contact with the nitride semiconductor layer40. The gate structure53may be disposed on the nitride semiconductor layer70. The gate structure53may include a gate metal. The gate metal may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and compounds thereof (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides, or conductive oxides), metal alloys (such as aluminum-copper alloy (Al—Cu)), or other suitable materials. The electrode51and the electrode52may be disposed on two opposite sides of the gate structure53. Although the electrode51and the electrode52are disposed on two opposite sides of the gate structure53inFIG.1, the electrode51, the electrode52, and the gate structure53may have different configurations in other embodiments of the present disclosure due to the design requirements. Although it is not illustrated inFIG.1, however, it is contemplated that structure of the electrode51can be varied or changed in some other embodiments of the subject application. Although it is not illustrated inFIG.1, however, it is contemplated that structure of the electrode52can be varied or changed in some other embodiments of the subject application. For example, a portion of the electrode51may be located or extended in the nitride semiconductor layer30. A portion of the electrode52may be located or extended in the nitride semiconductor layer30. The electrode51may be disposed on the nitride semiconductor layer30. The electrode52may be disposed on the nitride semiconductor layer30. The electrode51may penetrate the nitride semiconductor layer40to contact the nitride semiconductor layer30. The electrode52may penetrate the nitride semiconductor layer40to contact the nitride semiconductor layer30. The barrier layer60a(or a hole barrier layer) may be disposed between the gate structure53and the nitride semiconductor layer40. The barrier layer60amay be disposed between the gate structure53and the nitride semiconductor layer70. The nitride semiconductor layer70may be separated from the gate structure53by the barrier layer60a. The barrier layer60amay disposed on the nitride semiconductor layer70. The barrier layer60amay be disposed on the surface701of the nitride semiconductor layer70. The barrier layer60amay be in contact with the nitride semiconductor layer70. The barrier layer60amay be in contact with the surface701of the nitride semiconductor layer70. The barrier layer60amay not be in contact with the surface702of the nitride semiconductor layer70. The barrier layer60amay not be in contact with the surface703of the nitride semiconductor layer70. A portion of the nitride semiconductor layer70may be exposed from the barrier layer60a. A portion of the surface701of the nitride semiconductor layer70may be exposed from the barrier layer60a. The gate structure53may be disposed on the barrier layer60a. The gate structure53may be in contact with the barrier layer60a. A surface531(or a lower surface) of the gate structure53may be in contact with the barrier layer60a. The gate structure53may cover the barrier layer60a. The gate structure53may completely cover the barrier layer60a. A surface532(or a side surface) of the gate structure may be coplanar with the side surface of the barrier layer60a. The barrier layer60amay have a bandgap greater than that of the nitride semiconductor layer40. The barrier layer60amay have a band gap of about 4.0 eV to about 4.5 eV. The barrier layer60amay have a band gap of about 4.5 eV to about 5.0 eV. The barrier layer60amay have a band gap of about 5.0 eV to about 5.5 eV. The barrier layer60amay have a band gap of about 5.5 eV to about 6.0 eV. The barrier layer60amay include gallium. The barrier layer60amay include gallium oxide. Gallium oxide may include Ga2O3. The barrier layer60amay include gallium oxynitride. Gallium oxynitride may include GaOxN1-x, wherein 0<x<1. The barrier layer60amay include diamond. The barrier layer60amay include aluminum nitride. The barrier layer60amay include a combination thereof. The bandgap of the barrier layer60amay be greater than that of the nitride semiconductor layer70. The gate structure53, barrier layer60aand nitride semiconductor layer70may form a metal-insulator-semiconductor (MIS) structure. Compared to Schottky contact, MIS structure may assist in reducing leakage current and enhancing breakdown voltage. As a result, the gate voltage swing of the semiconductor device structure1acan be improved. Under high temperature gate bias (HTGB), hole(s) may flow into the nitride semiconductor layer70from the gate structure53. As HTGB is performed on the gate structure, the threshold voltage may shift irreversibly due to accumulation of hole(s) in the depletion layer. As shown inFIG.1, the barrier layer60amay be disposed between the nitride semiconductor layer70and the gate structure53. The barrier layer60ahas a bandgap greater than that of the nitride semiconductor layer40, which restrains hole(s) flowing from the gate structure53to the nitride semiconductor layer70and prevent accumulation of hole(s) in the nitride semiconductor layer70. As a result, the threshold voltage of the semiconductor device structure1amay keep invariable. FIG.2is a cross-sectional view of a semiconductor device structure1bin accordance with some embodiments of the present disclosure. The semiconductor device structure1bmay have a structure similar to the semiconductor device structure1aexcept that the barrier layer60bof the semiconductor device structure1bmay completely cover the surface701of the nitride semiconductor layer70. A portion of the barrier layer60bmay be exposed from the gate structure53. FIG.3is a cross-sectional view of a semiconductor device structure1cin accordance with some embodiments of the present disclosure. The semiconductor device structure1cmay have a structure similar to the semiconductor device structure1aexcept that the barrier layer60cof the semiconductor device structure1cmay enclose the nitride semiconductor layer70. The barrier layer60cmay surround the nitride semiconductor layer70. The barrier layer60cmay be in contact with the surface702of the nitride semiconductor layer70. The barrier layer60cmay be conformally disposed on the nitride semiconductor layer70. FIG.4is a cross-sectional view of a semiconductor device structure1din accordance with some embodiments of the present disclosure. The semiconductor device structure1dmay have a structure similar to the semiconductor device structure1cexcept that the barrier layer60dof the semiconductor device structure1dmay be disposed on the nitride semiconductor layer40. The barrier layer60dmay be in contact with the nitride semiconductor layer40. The barrier layer60dmay be in contact with the a surface401(or an upper surface) of the nitride semiconductor layer40. The barrier layer60dmay be in contact with the electrode51. The barrier layer60dmay be in contact with the electrode52. The barrier layer60dmay be disposed between the nitride semiconductor layer70and the electrode51. The barrier layer60dmay be disposed between the nitride semiconductor layer70and the electrode52. FIG.5is a cross-sectional view of a semiconductor device structure1ein accordance with some embodiments of the present disclosure. The barrier layer60emay be disposed between the nitride semiconductor layer40and the nitride semiconductor layer70. The barrier layer60emay be in contact with the surface703of the nitride semiconductor layer70. The barrier layer60emay not be in contact with the surface701of the nitride semiconductor layer70. The barrier layer60emay not be in contact with the surface702of the nitride semiconductor layer70. The nitride semiconductor layer70may be separated from the nitride semiconductor layer40by the barrier layer60e. The nitride semiconductor layer70may cover the barrier layer60e. The nitride semiconductor layer70may completely cover the barrier layer60e. The surface702of the nitride semiconductor layer70may be coplanar with the side surface of the barrier layer60e. Under high temperature reverse bias (HTRB), an electric field between the gate structure and the drain may incur impact ionization, generating a pair of hole and electron. This hole may be extracted by the gate structure through the depletion layer, which degrade the quality of the depletion layer. As HTRB is performed, the threshold voltage may shift irreversibly due to degradation of the depletion layer. Further, leak current may also be increased. In this embodiment, the barrier layer60eis disposed between the nitride semiconductor layer70and the nitride semiconductor layer40. The barrier layer60ehas a bandgap greater than that of the nitride semiconductor layer40, which restrains hole(s) flowing from the nitride semiconductor layer40to the gate structure53, thereby preventing the nitride semiconductor layer70from degradation. As a result, the threshold voltage of the semiconductor device structure1emay keep invariable. The leak current of the semiconductor device structure1emay keep invariable. FIG.6is a cross-sectional view of a semiconductor device structure1fin accordance with some embodiments of the present disclosure. The semiconductor device structure1fmay have a structure similar to the semiconductor device structure1eexcept that the barrier layer60fof the semiconductor device structure1fmay extend from the electrode51to the electrode52. A portion of the barrier layer60fmay be exposed from the nitride semiconductor layer70. The nitride semiconductor layer70may cover a portion of the barrier layer60f. FIG.7is a cross-sectional view of a semiconductor device structure1gin accordance with some embodiments of the present disclosure. The semiconductor device structure1gmay have a structure similar to the semiconductor device structure1fexcept that the barrier layer60gmay include a portion601and a portion602. The portion601may be separated from the portion602. The portion601may be separated from the portion602by the nitride semiconductor layer70. The portion601may be disposed between the nitride semiconductor layer70and the nitride semiconductor layer40. The portion602may be disposed between the gate structure53and the nitride semiconductor layer70. The portion601may be in contact with the surface703of the nitride semiconductor layer70. The portion602may be in contact with the surface701of the nitride semiconductor layer70. The nitride semiconductor layer70may be disposed between the portion601and the portion602. The surface702of the nitride semiconductor layer70may be coplanar with the side surface of the portion601. The surface532of the gate structure53may be coplanar with the side surface of the portion602. FIG.8is a cross-sectional view of a semiconductor device structure1hin accordance with some embodiments of the present disclosure. The semiconductor device structure1hmay have a structure similar to the semiconductor device structure1gexcept that the barrier layer60hof the semiconductor device structure1hmay be in contact with the surface701, surface702and surface703of the nitride semiconductor layer70. The nitride semiconductor layer70is enclosed by the barrier layer60h. The nitride semiconductor layer70is sealed by the barrier layer60h. FIG.9is a cross-sectional view of a semiconductor device structure1iin accordance with some embodiments of the present disclosure. The semiconductor device structure1imay have a structure similar to the semiconductor device structure1fexcept that the barrier layer60imay be free from in contact with the electrode51. The portion of the nitride semiconductor layer40that is located between the nitride semiconductor layer70and the electrode51may be exposed from the barrier layer60i. The barrier layer60imay cover the portion of the nitride semiconductor layer40that is located between the nitride semiconductor layer70and the electrode52. FIG.10is a waveform schematic of voltage of a comparative semiconductor device structure2under HTGB. Voltage can be switched between VLand VH. When voltage VLis performed, the semiconductor device structure2is at an off state. When voltage VHis performed, the semiconductor device structure2is at an on state. For example, under HTGB, a positive voltage may be imposed on the gate structure53; the substrate10may be connected to ground; the electrode51may be connected to ground; the electrode52may be connected to ground. FIG.10A,FIG.10BandFIG.10Cillustrate accumulation of hole(s) of a comparative semiconductor device structure2at different times, such as times t(1), t(2) and t(3) ofFIG.10, respectively. Referring toFIG.10A, the semiconductor device structure2may include a substrate10′, buffer layer20′, nitride semiconductor layer30′, nitride semiconductor layer40′, electrode51′, electrode52′, gate structure53′ and nitride semiconductor layer70′, which may be the same as or similar to the substrate10, buffer layer20, nitride semiconductor layer30, nitride semiconductor layer40, electrode51, electrode52, gate structure53and nitride semiconductor layer70. The semiconductor device structure2does not include a barrier layer between the nitride semiconductor layer70′ and the gate structure53′. Under HTGB, a mount of hole(s) may be injected into the nitride semiconductor layer70′ from the gate structure53′, and then flow to the interface of the nitride semiconductor layer30and the nitride semiconductor layer40, thereby depleting the 2DEG. At time t(1), almost of hole(s) may be consumed to deplete the 2DEG, and no hole(s) accumulates in the nitride semiconductor layer70′. Referring toFIG.10B, at time t(2), the semiconductor device structure2is switched once after time t(1). Under HTGB, the speed of hole(s) flowing from the gate structure53′ to the nitride semiconductor layer70′ may be greater than the speed of the hole(s) flowing from the nitride semiconductor layer70′ to the nitride semiconductor layer30′. As a result, some hole(s)81may accumulate in the nitride semiconductor layer70′. Referring toFIG.10C, at time t(3), the semiconductor device structure2is switched twice after time t(1). As the number of switch of semiconductor device structure2becomes greater, more hole(s)81may accumulate in the nitride semiconductor layer70′. As a result, the threshold voltage of the semiconductor device structure2may irreversibly shift. FIG.11is a waveform schematic of a comparative semiconductor device structure3under HTRB. Voltage can be switched between VLand VH. When voltage VLis performed, the semiconductor device structure3is at an off state. When voltage VHis performed, the semiconductor device structure3is at an on state. For example, under HTRB, a positive voltage may be imposed on the electrode52; the substrate10may be connected to ground; the gate structure53may be connected to ground; the electrode51may be connected to ground. FIG.11A,FIG.11BandFIG.11Cillustrate accumulation of hole(s) of a comparative semiconductor device structure at different times, such as times t(1), t(2) and t(3) ofFIG.10, respectively. Referring toFIG.11A, the semiconductor device structure3may have a structure similar to or the same as that of the semiconductor device structure2. Under HTRB, hole(s) may be generated due to impact ionization. Hole(s) may be extracted by the gate structure53′. At time (1), since the semiconductor device structure2has not been switched yet, no hole(s) is generated due to impact ionization. Referring toFIG.11B, at time t(2), the semiconductor device structure3is switched once after time t(1). Hole(s) may be generated and then extracted by the gate structure53′. When hole(s)81is extracted by the gate structure53′ through the nitride semiconductor layer70′, defects82may be generated in the nitride semiconductor layer70′, which degrades the nitride semiconductor layer70′. Referring toFIG.11C, at time t(3), the semiconductor device structure3is switched twice after time t(1). As the number of switch of semiconductor device structure3becomes greater, more hole(s)81may be extracted by the gate structure53′ through the nitride semiconductor layer70′, generating more defects82in the nitride semiconductor layer70′. As a result, the threshold voltage of the semiconductor device structure3may irreversibly shift. FIG.12A,FIG.12B,FIG.12CandFIG.12Dillustrate various stages of a method for manufacturing a semiconductor device structure in accordance with some embodiments of the present disclosure. Referring toFIG.12A, the substrate10is provided. The buffer layer20, the nitride semiconductor layer30, the nitride semiconductor layer40and the nitride semiconductor layer70may be formed on the substrate10. The buffer layer20, the nitride semiconductor layer30and the nitride semiconductor layer40, for example, may be formed through metal organic chemical vapor deposition (MOCVD), epitaxial growth or other suitable deposition steps. The nitride semiconductor layer70may be formed through the epitaxy technique. Referring toFIG.12B, a semiconductor material60may be conformally formed on the nitride semiconductor layer40and the nitride semiconductor layer70. The semiconductor material60may be deposited on the nitride semiconductor layer40after forming the nitride semiconductor layer70. The semiconductor material60may be formed by a thermal growth, such as edge-defined film-fed growth (EFG). The semiconductor material60may also be formed by using plasma. For example, a group III semiconductor layer, such as a gallium layer, may be formed first, and then a plasma under oxygen-containing gas may be performed followed by an anneal with nitrogen-containing gas, thereby forming the semiconductor material60. Oxygen-containing gas may include oxygen, ozone or other suitable gas. Nitrogen-containing gas may include nitrogen, ammonia or other suitable gas. Referring toFIG.12C, a portion of the semiconductor material60may be removed to form the barrier layer60a. The semiconductor material60may be removed by, for example, a wet technique, dry technique or other suitable techniques. Referring toFIG.12D, the electrode51, the electrode52and the gate structure53may be formed to form a semiconductor device structure same or similar to the semiconductor device structure1aas described and illustrated inFIG.1. FIG.13A,FIG.13BandFIG.13Cillustrate various stages of a method for manufacturing a semiconductor device structure in accordance with some embodiments of the present disclosure. Referring toFIG.13A, the semiconductor material60may be formed on the nitride semiconductor layer40. The semiconductor material60may be deposited on the nitride semiconductor layer40before forming the nitride semiconductor layer70. Referring toFIG.13B, the semiconductor material60may be patterned to form the barrier layer60e. Referring toFIG.13C, the electrode51, the electrode52, the gate structure53and the nitride semiconductor layer70may be formed to form a semiconductor device structure same or similar to the semiconductor device structure1eas described and illustrated inFIG.5. As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “lower,” “left,” “right” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 80 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present. As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally refers to within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 10 within 5 within 1 or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values. The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. | 29,099 |
11862723 | DETAILED DESCRIPTION For the ease of understanding the disclosure, the disclosure is described more completely with reference to related accompanying drawings. The examples of the disclosure are given in the accompanying drawings. However, the disclosure may be implemented in many different forms and is not limited to the examples described herein. Conversely, these examples are provided to make the disclosures of the disclosure more thorough and complete. Unless otherwise defined, all technical and scientific terms used herein have a same meaning generally understood by those skilled in the art of the disclosure. The terms used in the specification of the disclosure are merely to describe the specific examples, rather than to limit the disclosure. It will be understood that in a case that an element or layer is referred to as being “on”, “adjacent to” and “connected to” other element or layer, it can be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” other element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, and the like may be used herein to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure. For example, the first doping type may be termed the second doping type, and similarly, the second doping type may be termed the first doping type. The first doping type and the second doping type are different doping types, for example, the first doping type may be a P type and the second doping type may be an N type, or the first doping type may be the N type and the second doping type may be the P type. Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “on”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship with another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below other element” or “beneath” or “under” would then be oriented “above” the other element or feature. Thus, the exemplary terms “beneath” and “below” can encompass both an orientation of above and below. In addition, the device may also include other orientation (such as 90° of rotation or other orientation), and the spatial description term used herein is correspondingly explained. As used herein, the singular forms “a”, “an” and “said/the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise/comprising” or “having” specify the presence of stated features, integers, steps, operations, components, portions or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, portions or combinations thereof. Meanwhile, in the specification, the term “and/or” includes any and all combinations of the associated listed items. For the memories (for example, the Dynamic Random-Access Memory (DRAM)), a storage unit includes a storage transistor and a storage capacitor connected thereto, and the storage capacitor is configured to store charges that represent storage information. An active region, a drain region and a gate are formed in the storage transistor, the gate is configured to control current flowing between the source region and the drain region and connected to a word line, the drain region is configured to form a bit line contact region to connect to a bit line, and the source region is configured to form a storage node contact region to connect to the storage capacitor. The source region, channel region and drain region of the storage transistor are horizontally distributed along a direction parallel to a surface of the substrate; and in a case where the storage transistor of the storage unit is conducted normally, a channel current flows along a horizontal direction between the source region and the drain region overall. Hence, when the storage transistor is reduced to a predetermined size, a short-channel effect of the storage transistor tends to occur. The examples of the disclosure are described herein with reference to sectional views that are used as schematic diagrams of ideal examples (intermediate structures) of the disclosure, such that changes in shape may be anticipated due to for example the manufacturing techniques and/or tolerances. Hence, the examples of the disclosure should not be limited to special shapes of the regions shown herein but include shape deviations caused by the manufacturing techniques. For example, the injection region displayed as a rectangle is typically provided with a circular or curved feature at the edge and/or an injection concentration gradient, rather than a binary change from the injection region to the non-injection region. Likewise, the buried region formed by injection may lead to some injection in the buried region and a region between surfaces passed when the injection is performed. Therefore, the regions shown in the figures are substantially schematic, and the shapes thereof neither represent the actual shape of the regions of the device nor limit the scope of the disclosure. FIG.1illustrates a structural schematic diagram of a typical memory. As shown inFIG.1, the memory includes: a substrate, a word line20and a bit line30. Multiple active regions10are defined in the substrate. The active region10is provided with a first doped region and two second doped regions located on two sides of the first doped region. The word line20is formed on the substrate and intersected with the corresponding active region10. The position where the word line20is intersected with the active region10is configured to form a gate of a storage transistor. The bit line30is formed on the substrate and electrically connected to the first doped region of the corresponding active region10, so as to lead out the first doped region. The active region10of the storage transistor is formed by horizontal diffusion, i.e., the first doped region and the second doped region are horizontally distributed in a direction parallel to a surface of the substrate, thereby forming a storage transistor with a horizontal structure. When the size of the storage transistor is reduced, i.e., the size of the corresponding active region10is reduced, the risk of the short-channel effect increases easily. In addition, even though the short-channel effect of the transistor is not taken into account, the size of the storage transistor still cannot be further reduced under the limitation of the resolution of the lithography device. The storage transistor has a width D2of 3F in a direction perpendicular to the word line20, and a width D1of 2F in a direction perpendicular to the bit line30. The area configured for the storage transistor on the substrate is 6F2(3F*2F, i.e., 3*2 buried type word line structure), where, F is the minimum feature size, i.e., the minimum critical dimension size and the minimum critical space size that can be obtained based on the resolution of the lithography device at present. The minimum critical dimension size and the minimum critical space size are equal, i.e., based on the resolution of the existing lithography device, the unit size of the manufactured storage transistor can only reach 6F2, and cannot be reduced any more. In addition, in the memory shown inFIG.1, a bit line contact hole is further additionally manufactured above the second doped region of the active region so as to connect the second doped region and the bit line, and the manufacturing process is relatively complex. Referring toFIG.2, the disclosure provides a manufacturing method of an integrated circuit memory, which may include the following steps. In S102, a substrate is provided. The substrate may be a substrate of a semiconductor material such as silicon, germanium, silicon germanide and gallium arsenide or a Silicon-On-Insulator (SOI) substrate, which is not listed one by one herein. In S104, a bit line is formed on the substrate, with the bit line extending along a first direction. In S106, a word line is formed on the bit line, with the word line extending along a second direction. In S108, a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, with the vertical storage transistor being located in the word line, and connected to the bit line. According to the manufacturing method of the integrated circuit memory, as the formed storage transistor in the memory is the vertical transistor, compared with the storage transistor of the horizontal structure, the disclosure is more beneficial to reducing the size of the single storage transistor, and then may further effectively reduce the size of the whole memory; and meanwhile, as the vertical storage transistor is located in the word line and connected to the bit line, the step of manufacturing the bit line contact hole for connecting the bit line and the drain region of the storage transistor is omitted, and the preparation process is simple. Steps of the manufacturing method in the example will be described below in detail in combination with the accompanying drawings. FIG.3illustrates a top view of an integrated circuit memory after S104is executed according to an example.FIG.4illustrates a sectional view of an integrated circuit memory along an AA′ direction shown inFIG.3. In combination withFIG.3andFIG.4, in an example, the bit line is of a laminated structure. S104includes that: a first isolation layer film, a bit line conductive layer film, a bit line work function film and a bit line contact layer film are sequentially formed on the surface of the substrate, and a first mask pattern is formed on the surface of the substrate by means of photolithography process, with the first mask pattern exposing the bit line contact layer film that needs to be removed. After the first isolation layer film, the bit line conductive layer film, the bit line work function film and a part of the bit line contact layer film in a region exposed by the first mask pattern are removed by means of the etching process, a bit line102and a first opening104located between adjacent bit lines102are formed on the surface of the substrate. The bit line120is sequentially provided with a bit line contact layer202, a bit line work function layer (not shown), a bit line conductive layer204and a bit line isolation layer206from the top surface to the substrate. A distance H1between the top and the bottom of the bit line isolation layer206is greater than or equal to 10 nm and less than or equal to 20 nm. The bit line isolation layer206is formed by etching the first isolation layer film, and the remaining unetched first isolation layer film is formed into a first insulation layer between the bit line and the substrate. The material of the bit line isolation layer206includes for example silicon nitride, the material of the bit line conductive layer204includes for example tungsten (W), the material of the bit line work function layer at least includes for example one of tungsten silicide and titanium nitride (TiN), and the material of the bit line contact layer202includes for example doped polysilicon (Poly). It is to be noted that for the doped polysilicon layer of the bit line contact layer202, the conductive type of the doped ion may be adjusted correspondingly according to the conductive type of the vertical storage transistor. For example, if the conductive type of the vertical storage transistor is the P type, the doped polysilicon layer in the bit line contact layer may also correspondingly be the P-type doped. In an example, the bit line102further includes an adhesion layer (not shown) located between the bit line contact layer202and the bit line work function layer. The material of the adhesion layer includes for example one or more of titanium, titanium nitride and tungsten silicide. In other examples, before S104, a step of forming a stress buffer layer between the substrate and the first insulation layer is further included. The material of the stress buffer layer includes for example an oxidation layer. The oxidation layer may have a thickness of 5 nm, and the material, thickness and process of the stress buffer layer may be selected as required in the actual process. Exemplarily, S104specifically includes that: first step, an oxidation layer (such as 5 nm) for buffering a stress is formed on the surface of the substrate by means of a thermal oxidation process; second step, a layer of silicon nitride film (such as 100 nm) is formed on the oxidation layer by means of a furnace tube process; third step, a layer of tungsten metal film (such as 21 nm) is deposited on the silicon nitride by means of a physical vapor deposition (PVD) process; fourth step, a layer of tungsten silicide film (such as 2.5 nm) is deposited on the tungsten metal film by means of a chemical vapor deposition (CVD) process, and proportions of tungsten and silicon in the tungsten silicide film may be adjusted according to requirements on the bit line resistance; fifth step, a layer of titanium nitride film (such as 8 nm) is deposited on the tungsten silicide film through the CVD process; sixth step, a layer of titanium film (such as 3 nm) is deposited on the titanium nitride film by means of the PVD process; seventh step, a layer of doped polysilicon film (such as 10 nm) is deposited on the titanium film by means of the furnace tube process; and eighth step, the bit line102and the first opening104located between the adjacent bit lines102are formed by means of the photolithography process and the etching process. The etching process is stopped at the silicon nitride film on the oxidation layer film. By means of the etching process, the silicon nitride film is divided into a bit line isolation layer206composed of an etched portion and a first insulation layer composed of an unetched portion. FIG.5illustrates a sectional view of an integrated circuit memory along an AA′ direction before S106is executed correspondingly inFIG.4. In combination withFIG.5, in an example, before the word line is formed on the bit line, the following step is further included. An insulation dielectric layer106is formed on the integrated circuit memory formed with the bit line, the insulation dielectric layer106filling a gap between adjacent bit lines102, and covering the bit line102. By forming the insulation dielectric layer106on the integrated circuit memory formed with the bit line, the bit line102and the bit line102, as well as the bit line102and the subsequently formed word line, is isolated. In addition, the thickness of the insulation dielectric layer106may further be adjusted, to further improve the parasitic capacitance between the bit line200and the subsequently formed word line. In an example, the step that the insulation dielectric layer106is formed on the integrated circuit memory formed with the bit line includes that: a pattern protective layer101and a first filling layer103are sequentially formed on the integrated circuit memory formed with the bit line. The shape of the bit line102formed on the substrate may be protected through the pattern protective layer101, to avoid the influence of the subsequent process on the shape of the bit line, thereby protecting the performance of the memory. Exemplarily, the step that the insulation dielectric layer106is formed on the integrated circuit memory formed with the bit line includes that: first of all, a layer of silicon nitride film (pattern protective layer101) is deposited by means of an atomic layer deposition (ALD) process on the surface of the integrated circuit memory formed with the bit line, the silicon nitride film covering the surface of the integrated circuit memory formed with the bit line, a surface and a sidewall of the bit line, and a bottom of the first opening104, and a thickness of the silicon nitride film being far less than a width of the first opening104(i.e., distance between adjacent bit lines104); then, a silicon oxide film is deposited on the silicon nitride film by means of a CVD process to fill the first opening104between the adjacent bit lines102, a top surface of the silicon oxide film being higher than a top surface of the bit line102; and at last, a planarization process (Chemical Mechanical Polishing (CMP) process) is performed on the surface of the substrate to obtain the insulation dielectric layer106composed of the silicon nitride film and the remaining silicon oxide film, a top surface of the insulation dielectric layer106being higher than the top surface of the bit line102. In combination withFIG.6andFIG.7, in an example, the word line is of a laminated structure, and S106includes that: a word line work function film and a word line conductive layer film are sequentially formed on the surface of the substrate, and a second mask pattern is formed on the surface of the substrate by means of the photolithography process, the second mask pattern exposing a word line conductive layer film that needs to be removed. After the word line conductive layer film and the word line work function film in a region exposed by the second mask pattern are removed by means of the etching process, a word line108and a second opening110located between adjacent word lines108are formed on the surface of the substrate. The word line108is sequentially provided with the word line conductive layer304and the word line work function layer302from the top surface to the top surface of the insulation dielectric layer106. The material of the word line work function layer302at least includes for example one of titanium, titanium nitride and tungsten silicide, and the material of the word line conductive layer304includes for example tungsten (W). In an example, S106further includes that: a word line protective film is formed on the word line conductive layer film; and a word line protective layer306is provided on the word line108which is formed by means of the etching process. In the process of forming the word line108by means of the etching process, the word line protective film takes the effects of keeping the shape of the word line108and adjusting the etching rate of the etching process. The material of the word line protective layer306includes for example silicon nitride. In an example, the etching process for forming the word line108is an over etching process. By means of the over etching process, a first distance between the bottom of the second opening110and the word line work function layer302is greater than a second distance between the top surface of the insulation dielectric layer106and the word line work function layer302. The word line108is formed by means of the over etching process, such that the short-circuit problem arising from the residue of the word line work function film between adjacent word lines108due to a process deviation is avoided, and the word lines108are isolated by the insulation dielectric layer106. Exemplarily, Step S106specifically includes that: first step, a titanium nitride film (such as 3 nm) is formed by means of the CVD process on the surface of the bit line (i.e., surface of the integrated circuit memory formed with the bit line); second step, a tungsten film (such as 20 nm) is deposited on the titanium nitride film by means of the PVD process; third step, a silicon nitride film (such as 50 nm) is deposited on the tungsten film by means of the furnace tube process; and fourth step, the word line108and the second opening110are formed on the surface of the substrate by means of the photolithography process and the etching process, the word line108being isolated through the insulation dielectric layer106below the word line108. A distance H2between the lower surface of the word line108and the bottom of the second opening110is greater than or equal to 5 nm and less than or equal to 10 nm. In an example, a projection of the second direction in which the word line108extends and a projection of the first direction in which the bit line102extends are intersected the substrate with a first included angle φ. The first included angle φ has an angle of greater than or equal to 50° and less than or equal to 90°. For example, the first included angle φ is greater than or equal to 60° and less than or equal to 90°, or the first included angle φ is greater than or equal to 50° and less than or equal to 70°, etc. In an example, a width of the word line108, a width of the bit line102, a spacing between adjacent word lines108and a spacing between adjacent bit lines102are all a preset value, and the preset value is greater than or equal to 30 nm and less than or equal to 60 nm, i.e., the bit line102and the first opening104are equidistantly arranged on the surface of the substrate at a preset value, and the word line108and the second opening110are equidistantly arranged on the surface of the substrate at a preset value. In combination withFIG.8, in an example, after the word line108is formed on the bit line, the following step is further included. A spacing dielectric layer112is formed on the integrated circuit memory with the word line having been formed, in which the spacing dielectric layer112fills a gap between adjacent word lines108, and covering the word line108. That is, the spacing dielectric layer112fills the second opening110between the word lines108, and covers the top surface of the word line108. The spacing dielectric layer112protects the pattern shape of the word line108while isolating the word line108. The material of the spacing dielectric layer112includes for example one or more of silicon nitride, silicon oxide and silicon oxynitride. Exemplarily, the step that the spacing dielectric layer112is formed on the integrated circuit memory with the word line having been formed includes that: a layer of silicon nitride film is deposited on the surface of the integrated circuit memory with the word line having been formed, the silicon nitride film filling the second opening110, and a top surface of the silicon nitride film being higher than the top surface of the word line108; and then, a planarization process (CMP process) is performed to obtain the spacing dielectric layer112composed of the remaining silicon nitride film. The silicon nitride film may be formed by means of the CVD process or the ALD process on the integrated circuit memory with the word line having been formed. The step that the silicon nitride film is formed may also be divided into the following two steps: first step, a first silicon nitride film (such as 5 nm) is deposited by means of the ALD process on the surface of the integrated circuit memory with the word line having been formed, the first silicon nitride film covering the surface of the integrated circuit memory with the formed word line, the surface and the sidewall of the word line, and the bottom of the second opening110, and while protecting the shape of the word line108, the first silicon nitride film avoiding the damage to the word line108on the sidewall of the through hole in the process of subsequently etching to form the through hole when the silicon nitride film is formed only with the CVD process; and second step, a second silicon nitride film (such as 80 nm) is deposited on the first silicon nitride film by means of the CVD process, the second silicon nitride film filling the second opening110, and a top surface of the second silicon nitride film being higher than the top surface of the word line108. The problem of overlong process time when the silicon nitride film is formed only with the ALD process and the silicon nitride film of the same thickness is formed is avoided. In combination withFIG.9, in an example, the step that the vertical storage transistor is formed in the overlapping region where the word line and the bit line are spatially intersected includes the following steps. In S202, a through hole is provided in the overlapping region, the through hole exposing the bit line. Herein, a diameter of the through hole is less than a width of the word line. In combination withFIG.10, in an example, the step that the through hole is provided in the overlapping region includes the following steps. In S302, a first sacrificial layer pattern is formed on the integrated circuit memory with the word line having been formed, in which the first sacrificial layer pattern covers a preset region of the through hole, and exposes a region other than the preset region. FIG.11illustrates a top view of an integrated circuit memory after a transition sacrificial layer pattern along a direction of a word line is obtained in a process of forming a first sacrificial layer pattern through an etching process. FIG.12illustrates a sectional view of an integrated circuit memory along a BB′ direction shown inFIG.11, in which the BB′ is a first direction in which a bit line extends. FIG.13illustrates a top view of an integrated circuit memory with a first sacrificial layer pattern having been formed. FIG.14illustrates a sectional view of an integrated circuit memory along an AA′ direction shown inFIG.13, in which the AA′ is a second direction in which a word line extends. In combination withFIG.11toFIG.14, the step that the first sacrificial layer pattern is formed on the integrated circuit memory (i.e., substrate) with the word line having been formed includes the following steps. At the first step, a first sacrificial layer film is formed on the surface of the integrated circuit memory with the word line having been formed, and the first sacrificial layer film may be a laminated film, for example, including a polysilicon layer (such as 50 nm), an SOC (80 nm) and SION (20 nm) sequentially formed on the surface of the integrated circuit memory with the word line having been formed. At the second step, a part of the first sacrificial layer film is removed by means of the photolithography process and the etching process along the second direction to obtain a transition sacrificial layer pattern402composed of the remaining first sacrificial layer film on the word line108, in which the transition sacrificial layer pattern402extends along the second direction of the word line108, and a width of a projection of the transition sacrificial layer pattern402on the surface of the word line108along the second direction is less than the width of the word line108(as shown inFIG.11). At the third step, a part of the transition sacrificial layer pattern402is removed by the photolithography process and the etching process along the first direction to obtain the first sacrificial layer pattern404composed of the transition sacrificial layer pattern402on the word line108. The etching process in the second step and third step takes the spacing dielectric layer112as the etching stop layer. The first sacrificial layer pattern404is symmetric with respect to a central line of each of the word line and the bit line. A distance CD2between an edge of a projection of the first sacrificial layer pattern404on the substrate and an edge of a projection of the located word line108on the substrate, and a distance CD1between the edge of the projection of the first sacrificial layer pattern404on the substrate and an edge of a projection of the lower bit line102on the substrate are equal, and are greater than or equal to 3 nm and less than or equal to 8 nm. In S304, the through hole is provided in the preset region by means of a pattern transfer process. In combination withFIG.15andFIG.16, S304specifically includes that: first step, an etching protective layer (not shown) is formed on the surface of the integrated circuit memory with the word line having been formed, a top surface of the etching protective layer and a top surface of the first sacrificial layer pattern404being on the same horizontal plane, the material of the etching protective layer including silicon oxide, and the step that the etching protective layer is formed including that: a layer of oxidation layer film (such as 100 nm) filling a gap between the through holes and having a top surface located on the top surface of the first sacrificial layer pattern404is deposited on the surface of the integrated circuit memory with the word line having been formed, and then a planarization process is performed till the top surface of the first sacrificial layer pattern404, and by this time, the remaining oxidation layer film is formed into the etching protective layer; second step, the first sacrificial layer pattern404and the spacing dielectric layer112, the word line108and the insulation dielectric layer106in a preset region thereunder are removed by means of the photolithography process and the etching process till the bit line102, to form the through hole114; and third step, the etching protective layer on the surface of the integrated circuit memory with the word line having been formed is removed. In an example, the etching process for forming the through hole114is the over etching process. By means of the over etching process, there is no residue of the insulation dielectric layer106on the bottom of the through hole114, and the residue of the insulation dielectric layer on the bottom of the through hole114due to the process deviation is avoided affecting the contact between the vertical transistor formed in the through hole114subsequently and the bit line102. In an example, a distance between the bottom of the through hole114and the top (top surface) of the bit line102is greater than or equal to 3 nm and less than or equal to 5 nm. In S204, an active pillar of the vertical storage transistor and a gate dielectric layer surrounding the active pillar are formed in the through hole. In combination withFIG.17toFIG.20, in an example, the step that the active pillar of the vertical storage transistor and the gate dielectric layer surrounding the active pillar are formed in the through hole114includes the following steps. In S402, an annular gate dielectric layer is formed on a sidewall of the through hole. In an example, the step that the annular gate dielectric layer is formed on the sidewall of the through hole includes the following steps. A gate dielectric layer film is formed in the through hole114which covers the sidewall of the through hole and a bottom wall of the through hole. A protective layer film is formed on the gate dielectric layer film. The gate dielectric layer film and the protective layer film on the surface and the bottom wall of the substrate are removed through an etching process, and an opening exposing the bit line is provided in the through hole. A distance between a bottom of the opening and a top of the bit line is greater than or equal to 5 nm and less than or equal to 8 nm, such that the bit line102under the opening is completely exposed, and the residue of the gate oxidation layer or protective layer on the bit line102due to the process deviation is avoided affecting the connection between the drain of the vertical transistor and the bit line; and a distance between a bottom of the through hole and the top of the bit line is greater than or equal to 3 nm and less than or equal to 5 nm. In combination withFIG.17andFIG.18, the step that the annular gate dielectric layer is formed on the sidewall of the through hole114includes the following step. First of all, an oxidation layer film502(such as 8 nm) is formed on the surface of the integrated circuit memory with the word line having been formed by means of the ALD process, in which the oxidation layer film502covers the surface of the integrated circuit memory with the word line having been formed, the surface of the spacing dielectric layer112, and the sidewall and bottom of the through hole114. Then, a silicon film504is deposited on a surface of the oxidation layer film502, the silicon film504taking an effect of protecting the oxidation layer film502on the sidewall of the through hole114, and by this time, a third opening506is formed in the through hole114. Next, the silicon film504and the oxidation layer film502on the surface of the substrate, the surface of the spacing dielectric layer112and the bottom of the through hole114as well as a part of the bit line contact layer202(such as 6 nm) on the surface of the bit line102are removed by means of the etching process to obtain the annular gate dielectric layer116composed of the oxidation layer film502on the sidewall of the through hole114and the fourth opening508in the through hole114. The annular gate dielectric layer116surrounds the sidewall of the through hole114, such that the control of the gate on the formed vertical transistor is improved, and the operation efficiency of the integrated circuit memory is improved. In S404, a drain, a source and a channel region of the vertical storage transistor are formed in the through hole. The active pillar is formed in the through hole, a first doped region118is formed in a lower end portion of the active pillar, the first doped region118is connected to the bit line, a second doped region122is formed in an upper end portion of the active pillar, the second doped region122is configured to connect a storage element (not shown), and a third doped region120is formed between the lower end portion and the upper end portion of the active pillar. The first doped region118, the second doped region122and the third doped region120are respectively constructed to a drain region, a source region and a channel region of the vertical storage transistor. The second doped region122is configured to connect to the storage element (for example, storage capacitor, etc.). The word line108connected to the annular gate dielectric layer116also serves as a metal gate of the vertical storage transistor. In combination withFIG.19, the step that the drain, source and channel regions of the vertical storage transistor are formed in the through hole includes that: 3 times of deposition of silicon with different doping concentrations are sequentially performed in the fourth opening508(other substrate materials such as indium gallium arsenide (InGaAs) and gallium arsenide (GaAs) may also be selected), and thus the first doped region118, the channel region120and the second doped region122from the bit line102up are formed in the fourth opening508. Specifically, for example, the first doped region118, the channel region120and the second doped region122may be formed with an in-situ doping process. In an example, one overlapping region corresponds to one vertical storage transistor, and a unit configuration size of the vertical storage transistor on the substrate is greater than or equal to 4 times of a square of a minimum feature size. In an example, six vertical storage transistors equidistantly adjacent to the same vertical storage transistor in the vertical storage transistors are arranged in hexagonal array. The “unit configuration size” refers to a unit configuration size configured for one storage unit on the substrate, specifically including: a size actually occupied by one storage unit on the substrate, and a spacing size reserved between the storage unit and the adjacent storage unit. For example, if the size occupied by N storage transistors on the substrate is M, the unit configuration size of one storage transistor on the substrate is N/M. For the vertical storage transistor based on the vertical structure, the word line108and the bit line102are spatially intersected with the overlapping region, one overlapping region corresponding to one vertical storage transistor. According to the existing manufacturing process, the bit line102and the word line108having the minimum feature size F can be formed, and the space between the formed adjacent bit lines and adjacent word lines is also greater than or equal to the minimum feature size F; then, the width D1′ of the vertical storage transistor in a direction perpendicular to the bit line is 2F, and the width D2′ in a direction perpendicular to the word line is also 2F; and therefore, the unit configuration size of the corresponding vertical storage transistor may reach 4F2(2F*2F), i.e., the unit configuration size of the vertical storage transistor is greater than or equal to 4 times of the square of the minimum feature size. According to the manufacturing method of the integrated circuit memory, the vertical storage transistor is formed in the overlapping region where the word line and the bit line are spatially intersected, i.e., the source region, the channel region and the drain region are vertically arranged along a height direction, and the vertical storage transistor is located on the bit line and connected to the bit line. In this way, the step of manufacturing the bit line contact hole to connect the bit line and the drain region of the storage transistor is omitted. Moreover, as the unit configuration size of the vertical storage transistor on the substrate is relatively small (for example, the unit configuration size can reach 4F2), the size of the memory may further be correspondingly reduced. Meanwhile, the vertical storage transistor further has the better arrangement flexibility to implement the dense arrangement of the vertical storage transistor. In combination withFIG.19, in an example, an integrated circuit memory is further provided, which includes: a substrate, a bit line102, a word line108and a vertical storage transistor. The bit line102is formed on the substrate and extends along a first direction. The word line108is formed on the bit line and extends along a second direction. The vertical storage transistor is formed in an overlapping region where the word line108and the bit line102are spatially intersected, located on and in the word line102, and connected to the bit line102. In an example, the bit line102is of a laminated structure, for example, the bit line120includes a bit line isolation layer206, a bit line conductive layer204, a bit line work function layer (not shown) and a bit line contact layer202sequentially stacked on the substrate. The material of the bit line isolation layer206includes for example silicon nitride, the material of the bit line conductive layer204includes for example tungsten (W), the material of the bit line work function layer at least includes for example one of tungsten silicide and titanium nitride (TiN), and the material of the bit line contact layer202includes for example doped polysilicon (Poly). It is to be noted that for the doped polysilicon layer of the bit line contact layer202, the conductive type of the doped ion may be adjusted correspondingly according to the conductive type of the vertical storage transistor. For example, if the conductive type of the vertical storage transistor is the P type, the doped polysilicon layer in the bit line contact layer may also correspondingly be the P-type doped. In an example, the bit line102further includes an adhesion layer (not shown) located between the bit line contact layer202and the bit line work function layer. The material of the adhesion layer includes for example one or more of titanium, titanium nitride and tungsten silicide. In an example, the integrated circuit memory further includes an insulation dielectric layer106, which is formed on the integrated circuit memory formed with the bit line (i.e., substrate), in which the insulation dielectric layer106fills a gap between adjacent bit lines102, and covers the bit line102. With the insulation dielectric layer106, a bit line102and another bit line102, as well as a bit line102and a subsequently formed word line, are isolated. In addition, the thickness of the insulation dielectric layer106may be adjusted, to further improve the parasitic capacitance between the bit line200and the subsequently formed word line. In an example, the insulation dielectric layer106includes: a pattern protective layer101and a first filling layer103. The shape of the bit line102formed on the substrate may be protected through the pattern protective layer101, to avoid the influence of the subsequent process on the shape of the bit line, thereby protecting the performance of the memory. In an example, the word line108is of a laminated structure, and includes for example a word line work function layer302and a word line conductive layer304that are sequentially stacked. In an example, the word line108further includes a word line protective layer306located on the word line conductive layer304. In an example, the integrated circuit memory includes: a spacing dielectric layer112. The spacing dielectric layer112fills a gap between adjacent word lines108, and covers the word line108. The spacing dielectric layer112protects the pattern shape of the word line108while isolating the word line108. The material of the spacing dielectric layer112includes for example silicon nitride. In an example, the integrated circuit memory further includes a through hole114, provided in the overlapping region, and exposing the bit line102, an active pillar of the vertical storage transistor and a gate dielectric layer116surrounding the active pillar being arranged in the through hole114. A diameter of the through hole114is less than a width of the word line108. In an example, the vertical storage transistor includes: an annular gate dielectric layer116and the active pillar. The annular gate dielectric layer116is located on a sidewall of the through hole114. The active pillar is located in the through hole114, a first doped region118is formed in a lower end portion of the active pillar and connected to the bit line102(directly contacts the bit line102), a second doped region122is formed in a upper end portion of the active pillar, the second doped region122is configured to connect a storage element (not shown), and a third doped region120is formed between the lower end portion and the upper end portion of the active pillar. The first doped region118, the second doped region122and the third doped region120are respectively constructed to a drain region, a source region and a channel region of the vertical storage transistor. In an example, a width of the word line, a width of the bit line, a spacing between adjacent word lines and a spacing between two adjacent bit lines are all a preset value, and the preset value is greater than or equal to 30 nm and less than or equal to 60 nm, In an example, a projection of the second direction in which the word line108extends and a projection of the first direction in which the bit line102extends on the substrate are intersected with a first angle. The first angle has an angle of greater than or equal to 50° and less than or equal to 90°. For example, the first angle is greater than or equal to 60° and less than or equal to 90°, or the first included angle is greater than or equal to 50° and less than or equal to 70°, etc. One overlapping region corresponds to one vertical storage transistor. A unit configuration size of the vertical storage transistor on the substrate is greater than or equal to 4 times of a square of a minimum feature size. In an example, the integrated circuit memory further includes a storage element (not shown), formed above the vertical storage transistor, and electrically connected to the second doped region122. According to the integrated circuit memory, the vertical storage transistor is formed in the overlapping region where the word line and the bit line are spatially intersected, i.e., the source region, the channel region and the drain region are vertically arranged along a height direction, and the vertical storage transistor is located on the bit line and connected to the bit line. In this way, a bit line contact hole for connecting the bit line and the drain region of the storage transistor is omitted. Moreover, as the unit configuration size of the vertical storage transistor on the substrate is relatively small (for example, the unit configuration size can reach 4F2), the size of the memory may further be correspondingly reduced. Meanwhile, the vertical storage transistor further has the better arrangement flexibility to implement the dense arrangement of the vertical storage transistor. In an example, a semiconductor integrated circuit device is provided, which includes: a substrate, a first conducting line, a second conducting line and a vertical storage transistor. The first conducting line is formed on the substrate and extends along a first direction. The second conducting line is formed on the first conducting line and extends along a second direction. The vertical storage transistor is formed in an overlapping region where the second conducting line and the first conducting line are spatially intersected, located in the second conducting line, and connected to the first conducting line. According to the semiconductor integrated circuit device, the vertical storage transistor is formed in the overlapping region where the second conducting line and the first conducting line are spatially intersected, i.e., the source region, the channel region and the drain region are vertically arranged along a height direction, and the vertical storage transistor is located on the second conducting line and connected to the first conducting line. In this way, a second conducting line contact hole for connecting the first conducting line and the drain region of the storage transistor is omitted. Moreover, as the unit configuration size of the vertical storage transistor on the substrate is relatively small (for example, the unit configuration size can reach 4F2), the size of the memory may further be correspondingly reduced. Meanwhile, the vertical storage transistor further has the better arrangement flexibility to implement the dense arrangement of the vertical storage transistor. Reference in the specification to “some examples”, “other examples”, “ideal example” and the like means that a particular feature, structure, material or feature described in connection with the examples or examples is included in at least one example or example of the disclosure. In the specification, the schematic descriptions on the above terms unnecessarily refer to the same example or example. The technical features of the above examples may be combined freely. In order to describe briefly, the descriptions are not made on all possible combinations of the technical features of the examples. However, the combinations of these technical features should be viewed as a scope of the specification as long as there is no conflict. The above examples only describe several implementation modes of the disclosure. The description is specific and detailed, but cannot be understood as a limit to a scope of the disclosure accordingly. It should be pointed out that those of ordinary skill in the art may further make multiple changes and improvements without departing from a concept of the disclosure and those also belong to the protection scope of the disclosure. Therefore, the protection scope of the disclosure shall be subjected to the appended claims. | 48,166 |
11862724 | DETAILED DESCRIPTION The following Detailed Description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. Embodiments of the present disclosure are generally directed to semiconductor devices and integrated circuits, and methods for fabricating the same. Conventional techniques related to integrated circuit device design and fabrication may not be described in full detail herein, and the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality. In particular, various steps in the manufacture of semiconductor-based integrated circuits are well-known and so, in the interest of brevity, many conventional steps may be mentioned only briefly herein or may be omitted entirely without providing well-known process details. For example, the use of the word “patterned” implies the steps of applying photoresist (resist), exposing the resist to light using a photomask, and developing the resist to create a patterned resist masking layer (note that a layout shape for a mask or reticle is also called a “pattern”), subsequent to which an ion implantation, etching or deposition step may occur through the patterned resist to create a structure having the lateral shape of the exposed and developed resist pattern. Similarly, stripping, removal, ashing, and cleaning steps associated with patterning, deposition, etching, and doping steps that may be required but are well-known are likewise omitted. Although the present invention is described and illustrated herein with reference to a submicron CMOS process using Shallow Trench Isolation (STI) and self-aligned silicide (salicided) polysilicon and diffusions, it will be apparent to those skilled in the art that the illustrated exemplary techniques and structures for device layouts, and the related integrated circuit processing fabrication methods that will be described herein, may have application to a wide variety of NMOS transistor devices, and to different variations of MOS processes using different isolation technologies such as LOCOS. Well known in the art are the designations “P−”, “P”, and “P+” to describe ranges of doping concentrations of p-type dopants, and “N—”, “N”, and “N+” to describe ranges of doping concentrations of n-type dopants, where “P−” and “N—” refer to doping concentrations of 1014-1016cm−3, “P” and “N” refer to concentrations of 1016-1019cm−3, and “P+” and “N+” refer to concentrations of 1019-1021cm−3. These dopant concentrations can be introduced into the substrate by a number of different processes, but ion implantation will be described herein as an example process capable of placing the dopants precisely where they are required. For a given implant energy, peak volumetric concentrations are approximately proportional to the “dose” of the implant, given in units of cm−2, which is a quantity easily specified during processing. Referring now toFIG.2A, a mask layout is shown of a radiation-hardened NMOS transistor200according a first embodiment of the present invention. An active region having the approximate shape of a “plus sign” has a boundary indicated by a solid line ACTIVE pattern202. The active region defined by this boundary has an extent in the length direction with a total length of H, and in the width direction a total width of A+2B, where width A corresponds to a central substantially rectangular region that has a length H, and 2B is the total width of two tabs216. Tabs216are positioned over a GATE pattern206(light long dash line) having length L as shown, and the tabs216both extend outward from the central region by a width B, in the illustrated embodiment. Each tab216has a length t that is less than total length H of the active region, and is offset from each end of ACTIVE202, in this example by distances216a, from bottom edge202aof ACTIVE202to bottom edge of tab216, and216b, from top edge202bof ACTIVE202to top edge of tab216, respectively. Tab length t is typically chosen to be greater than gate length L as shown, so that the structures described herein, when fabricated, will be effective even in the face of misalignments to ensure that the outer edges or side boundaries222aand222bof the tabs extend at least the full length L of gate206. Distances216aand216bneed not be the same, nor do they both need to be nonzero; nor do tab widths B need to be equal. That is, in order to practice the principles of the present invention, a transistor layout need not be symmetrical, although this is common. However, in order to achieve a minimum device size, each feature may be set either to a minimum size dictated by a required function or to a minimum allowed by process design rules, and therefore, like features will in many embodiments have dimensions equal to each other and to such a minimum dimension. An exemplary shape of the NSD diffusion region is shown using heavy short dash lines specifying the outline of an NSDB pattern228. In practice, and as is known to those skilled in the art, N+(NSD) diffusion regions may be defined in a mask layout not by areas defined by where NSD implants will go, as was indicated by rectangle158in FIG.1B, but instead by ACTIVE202and one or more inverted mask layers NSDB (NSD Block)228that indicate where the NSD implant is to be blocked. N+ doping is implanted wherever there is ACTIVE202and an absence of NSDB228, forming self-aligned source/drain regions210aand210bon either side of GATE206in the active region. Segments228a′ and228b′ are analogous to segments158aand158binFIG.1Bin that they are pulled back (i.e., displaced inward toward the center of the active region) from the tab ends defined by first and second side boundaries222aand222bof ACTIVE202, and thus displaced from parasitic edge channels that form along field oxide sidewalls where GATE206crosses over the boundary of ACTIVE202. The distances (gap width g) that segments228a′ and228b′ are displaced inward from side boundaries222aand222bdefine gap regions204(indicated by a sparse random stipple pattern). In the embodiment illustrated, NSDB228is shaped into simple rectangles whose inner edges228a′ and228b′ are positioned so as to define gap widths g that equal the widths B of tabs216. It can be seen that gap regions204(which may be alternatively considered as portions of a single gap region204) are bounded by GATE206, ACTIVE202, and NSDB228, similar to gap regions154inFIG.1B. The same NSDB228pattern may be used to define where implants for LDD structures (in which NLDD is also n-type, but lower concentration than NSD) are to be placed (or blocked). However, different devices might call for different NLDD structures, so a separate mask NLDDB (NLDD Block)218is comprehended in the exemplary layouts herein, and shown coincident with the NSDB228pattern, as is a silicide block pattern SB214, to be described in more detail later. NSDB228and the other blocking patterns214and218are shown oversized from tab216. For example, outer edges228aand228bof the rectangles in the NSDB pattern228are shown as outside tab side boundaries222aand222b, respectively. The blocking patterns may be oversized, as is known in the art, in order to ensure that gap regions204are encompassed by patterns NSDB228, NLDDB218, and SB214(to exclude n-type dopants and silicide formation from the gap regions204) in spite of misalignments during processing. The length of the pulled-back segment of NSDB228is shown as dimension s, which in this example embodiment is also the same length for all three blocking patterns NSDB228, NLDDB218, and SB214. InFIG.2A, not only are the segment lengths s for228a′ and228b′ greater than tab length t, but this example has three of four borders of blocking patterns NSDB228, NLDBB218, and SB214that are oversized beyond the extents of tabs216. Oversizing the rectangular blocking pattern regions on the inner sides (further toward the center of active region202) is unnecessary for alignment purposes, and would unnecessarily increase the size of gap regions204, increase gap width g, and reduce source/drain diffusion region widths W. The purpose of gap regions204is to increase the threshold voltage of parasitic edge transistors that can form along side boundaries222aand222bof ACTIVE202, by removing the n-type doping in diffusion regions210aand210bfrom proximity with the field oxide sidewalls under gate206. With the NSD pull-back, current leaking along the field oxide edge under gate206has to further traverse the gap region, which is lightly-doped p-type and not implanted N+. As described above, the gap regions204are defined by the shape of NSD blocking region NSDB228. Blocking regions using NLDDB218and SB214need not be shaped such that they are exactly coincident with NSDB228, but NLDDB218and SB214are also required to cover gap regions204, in order to keep the moderate n-type doping of LDD structures out, which would increase parasitic edge leakage similar to the NSD doping, and also to prevent silicide from forming in the gap regions204, which would short NSD (especially the drain) to the exposed substrate in the gap regions. Although preferred, not all, nor even any, of these blocking patterns NSDB228, NLDDB218, or SB214need extend all the way across GATE206as shown here (in which they are simple rectangles). Blocking patterns could be laid out in separate portions on either side of GATE206, as long as together they cover gap regions204. In this case, a pulled-back segment (analogous to228a′ or228b′) of NSDB228might consist of two segments separated by at least part of GATE206, with a distance s measured along the length direction between the outer ends of these segments that are closest to the ends202aand202bof active region. However, in small-geometry device layouts, breaking blocking patterns into smaller separated areas can result in yield issues due to the creation of small photoresist particles during lithographic processing; and separated blocking regions on either side of GATE206might trigger design rules requiring gate length L to be longer than its minimum value. Still referring toFIG.2A, blocking regions NSDB228, NLDDB218, and SB214are all drawn having length s, and are thus all oversized in the length direction with respect to tab length t. Thus, the ends of pulled-back segments228a′ and228b′ can be seen to be separated by somewhat smaller distances from their respective nearest ends202aand202bof ACTIVE202than the offset distances216aand216b(which indicate distances separating the active region tabs216from active region ends202aand202b). These somewhat smaller distances from the blocking regions to active region ends are not labeled inFIG.2A, but are indicated inFIG.2Cas distances216a′ and216b′. It is these distances216a′ and216b′ measured to the ends of the blocking regions, which apply either to the notch geometry inFIG.2Cor to the tab geometry inFIG.2A, especially for silicide blocking regions SB214, that are most commonly limited to at least a minimum predetermined nonzero value dictated by process design rules. By making at least one of these distances216a′ and216b′ greater than or equal to the design rule minimum, close placement in the length direction of transistor200to respective neighboring devices or other essential features such as substrate contacts is permitted, as limited only by other design rules governing device spacing. At the same time, designs according to the present invention in which ends of tab216side boundaries222aand222b(as defined by distances216aand216b) are on opposite sides of GATE206(i.e., s>L for the simply-connected blocking regions shown inFIG.2A), enable rad-hard transistors to be laid out having a minimum gate length L according to the design rules, with good high-frequency performance. Thus, high circuit densities and device performances approaching those of non-rad-hard commercial ICs may be achieved using rad-hard transistors designed according to the present invention. As stated earlier, a transistor layout according to the present invention need not be symmetrical in either the length or width direction; for example, the tabs need not be the same size, nor do distances216aand216bneed to be equal. One of offset distances216aor216bmay even be zero, if close spacing to neighboring devices or structures is not required on that respective end of transistor200. A radiation-hardened device may have a single tab216instead of two symmetrical tabs in some embodiments, such as in transistors that may mitigate TID-induced leakage at the other end of the gate using different techniques from the pull-back technique used here to create gap regions204. If no such leakage reduction structure is in place on the other end of the gate, then the use of gap regions204on one end of a transistor gate will at least mitigate leakage on that end, reducing TID-induced leakage by, e.g., a factor of two. Indeed, other completely different shapes of ACTIVE202and NSDB228are possible without departing from the spirit and scope of the present invention, as will be seen later in another embodiment described with reference toFIG.2C. In some embodiments, optional moderately-doped p-type bands212may be formed along the active side boundaries222aand222bunder gate206, to place p-type doping (e.g., boron) along the field oxide sidewalls in order to increase the threshold of the parasitic edge transistors and further reduce TID-induced leakage, as depicted inFIG.2Aby the pattern labeled PWALL212using a regular stipple pattern surrounded by light dashes. This moderate-dose p-type implant is used to further increase radiation hardness, and may not be necessary in cases where a radiation tolerance goal is relatively low. A PWALL implant may be performed along the side boundaries222aand222bafter the patterned field oxide is formed and before gate oxide and gate polysilicon are deposited. The length h of PWALL regions212is preferably at least as long as gate length L in order to cover the entire length of the parasitic edge channel formed under the gate206, to interact with fringing fields from the edges of the gate, and may be longer than L, e.g., extending (for a 180-nm process) perhaps 0.4 micrometers beyond each edge of the gate206such that h=L+0.8 μm. PWALL length h can be as long or longer than tab length t, or equal to the blocking region length s as shown inFIG.2A; but PWALL length h may need to be limited to less than active region length H, as are s and t for NSDB228and SB214and tabs216, or one or both ends of PWALL212similarly offset from at least one end of ACTIVE202in order to avoid triggering design rule violations when used in close proximity to neighboring devices. PWALL212preferably is sized and positioned such that outer edges212aand212bof PWALL212, corresponding the left and right tabs216, respectively, overlap the active region side boundaries222aand222bas shown so as to ensure that the p-type dopant is placed directly along the field oxide sidewalls along boundaries222aand222bwhere parasitic edge transistor channels are formed. The inner edges of PWALL212a′ and212b′ extend into the gap regions204by a distance g′ that is less than the gap width g, such that the implanted region ends a distance d=g−g′ from segments228a′ and228b′ of the n-type diffusion regions210aand210bas defined by the NSD pattern, i.e., by NSDB228. While TID-induced leakage is reduced (i.e., the threshold voltage of parasitic field edge transistors is increased) by the presence of the PWALL implant in regions PWALL212, and may be reduced further by increasing the PWALL doping concentration, increasing the p-type doping concentration of the PWALL implant for a given distance d increases the parasitic threshold voltage at the expense of reducing electrical performance, for example, by decreasing the breakdown voltage of transistor200. To compensate, increasing the distance d between the PWALL implant and NSDB border segments228a′ and228b′ (i.e., increasing the distance between diffusion regions210aand210band the nearest border of PWALL212) can allow the breakdown voltage of transistor200to be maintained for a given p-type concentration level within PWALL212that may be required to meet a predetermined level of TID performance (radiation tolerance level). Therefore, the PWALL parameters distance d and PWALL doping concentration can be selected to achieve a predetermined tradeoff, to improve TID performance while maintaining electrical characteristics such as breakdown voltage of transistor200the same at the expense of transistor area. A schematic cross-section of a compact rad-hard transistor device200is shown inFIG.2B, corresponding to a section indicated by2B-2B through the device as shownFIG.2A. A substrate220that is lightly doped p-type may be a lightly-doped p-type silicon wafer, or an epitaxial layer, or commonly a P-well region within a CMOS wafer. Field oxide222is shown as a shallow trench isolation (STI) structure in which oxide222is embedded into the wafer surface and planarized so that it is substantially level with wafer surface220a. NSD diffusion region210adoped N+ has width W, and can be seen to be pulled back from edges222′ of field oxide222so that its outer edges228a′ and228b′ are separated from field oxide222by a gap width g on both sides, as defined by the NSDB228mask used to exclude the N+ doping from the gap regions204(not labeled inFIG.2B). Also not shown in this section is the placement of NLDD n-type dopants, since the section2B-2B is spaced away from the gate sidewalls. NLDD dopants have a shallower extent than the NSD dopants in diffusion region210a, and have a similar lateral (side-to-side in this view) extent to that of210asince the NLDDB218mask pattern is shown coincident with that of NSDB228inFIG.2A. Optional p-type bands212defined by the PWALL mask pattern are also shown along the edges222′ of the field oxide, and extend a distance g′ into the gap regions, placing their inner edges212a′ and212b′ a distance d from the outer edges of diffusion region210a. The p-type dopants in PWALL212are shown schematically to extend slightly under the field oxide222to outer edges212aand212b, where they can reach by direct ion implantation (e.g., using a tilted/rotation implant), and/or by diffusion in subsequent processing after an untilted implant. This is desirable to improve radiation hardness. For clarity, the depth of the p-type implanted band regions212are shown as deeper than that of trench insulator222and the depth of source/drain implant210b; but in practice, the implant for the p-type bands may extend no deeper, or not much deeper, than the depth of the trench insulator222. A polysilicon gate layer326is shown on top of a thin gate oxide layer322grown on the surface220aof substrate220. The schematic boundary of the gate is shown as a dashed line in this section to indicate that the section2B-2B does not pass directly through gate206, but rather that gate206is seen in a plane behind that of the cross-section shown inFIG.2B. Silicided layers are indicated by reference numeral314in the top surface of the silicon substrate (salicide) and by reference numeral316(polycide) in the polysilicon surface. Metal silicides may be formed using conventional processes and excluded from gap regions using silicide blocking layers patterned using mask layer SB214. It can be seen that for the example layout of transistor200inFIG.2A, as shown in cross-sectionFIG.2B, salicide314is confined to the width W of the diffusion region210a, and polycide316is excluded from regions316′ on the gate layer326. Regions316′ lacking polycide result in high-resistivity segments of gate206, that can be made more conductive using techniques to be discussed later with reference toFIGS.4and7. Referring now toFIG.2C, a layout for an alternative embodiment of a compact rad-hard transistor240is shown. In this embodiment, ACTIVE202is substantially rectangular with total width A and total length H instead of having extending tabs, and side boundaries222aand222brun the full length H of the active region202. Parasitic edge channels can again form along the field oxide under gate206where side boundaries222aand222bcross gate206, and in rad-hard transistor240, a similar strategy is employed to mitigate TID-induced leakage currents. Segments228a′ and228b′ of the border of the NSD diffusion are displaced inward (pulled back) by gap width g from side boundaries222aand222bto form gap regions204, and this placement of the blocking regions NSDB228, NLDDB218, and SB214results in two “notches” into the active region202. These notches have a length s that is less than the total length H of the active region and are separated from nearest ends202aand202bof ACTIVE202by nonzero distances216a′ and216b′ respectively, distances that are analogous to the corresponding distances216aand216bin the previous embodiment200. The cross-section inFIG.2Balso applies to this transistor240, with the section line passing through gap regions204and PWALL implants212. Again, distances216a′ and216b′ need not be the same, nor both nonzero, and in order to practice the principles of the present invention, a transistor layout need not be symmetrical, while to achieve a minimum device size, each feature may be set either to a minimum size dictated by a required function or to a minimum allowed by process design rules. The layout shown inFIG.2Ccan achieve similar density in the length direction as that ofFIG.2A, but for the same electrical width W, as determined by the widths of diffusion regions210aand210badjacent to the gate206, it has a larger area of diffusion regions210aand210band therefore slightly higher capacitance. Alternative embodiments are also possible in which the geometry of blocking regions NSDB228, NLDDB218, and SB214do not cross GATE206, but are divided into separate portions on either side of GATE206, as described earlier for the tab geometry ofFIG.2A, as long as the gap regions204are covered. FIG.3Adepicts a schematic plan view or layout of a region of an integrated circuit according to another embodiment, illustrating close placement of two rad-hard transistors200near to each other with a substrate contact300placed in between. Substrate contact300may be referred to as a guard bar or guard band in some applications, or it may be used as a transistor body connection. Close spacing is made possible using the principles of the present invention, in this case using plus-shaped active regions202, and results in increased circuit density over prior art rad-hard transistor designs. Transistors200are shown having contacts306in the source and drain diffusion regions (not labeled), and for simplicity, p-type bands are omitted, showing only blocking layers NSDB228, NLDDB218, and SB214. Substrate contact300comprises a PSD pattern310(long-short dashed line) that designates an area to be implanted with P+ through an opening in field oxide defined by ACTIVE202as shown, and contacts shown by CONTACT306(heavy solid line) are placed along the substrate contact300, which are connected as needed, typically to VSSor ground, through interconnect lines (not shown) either using either polysilicon or metal interconnect layers. This example demonstrates that the tab geometry shown inFIG.2Afor rad-hard transistors200enables transistors and other essential features such as substrate contacts300to be placed a minimum distance apart from the rad-hard device200. This integrated circuit environment is common, especially in rad-hard or high-voltage circuitry, and the exemplary layout ofFIG.3Ais intended to represent a number of common situations in which a substrate contact300might be employed. As will be seen in other embodiments, a P+ contact to the substrate (or to a P-well) may be used as a body connection for an NMOS transistor, also called a well tap or a back gate. In other situations, NMOS transistors are sometimes completely surrounded with substrate contacts called guard rings, to help prevent heavy ion induced latch-up for rad-hard applications. Guard rings and guard bars are also used to reduce sensitivity to latch-up and electrostatic discharge (ESD) and to block substrate noise currents in sensitive analog inputs and mixed-signal circuit applications. In compact layouts, active regions202can contain multiple rad-hard transistors200or240for improved electrical matching and to implement rad-hard circuit designs that can be used, e.g., in analog circuits such as current mirrors (like that described later in reference toFIG.6D) or differential stages. In a current mirror application, substrate contact300inFIG.3Amay represent a portion of a guard ring structure separating one active region202, containing at least two matched rad-hard transistors, from a second active region202containing a group of at least two cascoded transistors that can be either rad-hard or non-rad-hard. To prevent latch-up, body connections should be provided close to most transistors in an IC. Some CMOS processes allow a body connection to be abutted to a transistor, by permitting a P+ region adjacent to a N+ source/drain within the same active region202, as illustrated in the layout ofFIG.3B, showing a rad-hard NMOS transistor270having an abutting body connection. An abutting body connection permits a particularly compact layout for a transistor, as in this example, and such a device can be placed closer to neighboring transistors using the principles of the present invention. Specifically, in NMOS transistor270, a PSD pattern310is used to create a P+ diffusion region318placed within ACTIVE202, adjacent (abutting) N+ source region210a. The tab geometry, with gap regions204and blocking patterns228,218, and214separated from the end of ACTIVE202that encompasses drain region210b, allows placement of another device, well, or contact close to transistor270on the side neighboring region210b. Diffusion regions210a, and210b, and318may be sized just large enough to permit placement of contacts306. Silicide (not shown) outside silicide block SB214formed on the diffusion regions210a,210b, and318(as well as on top of gate206) may be used to reduce the sheet resistance of those areas, and to form a low-resistance connection between source210aand the body connection formed by diffusion region318. Regions that lack polycide due to the use of continuous silicide block patterns214that cross gate206were mentioned previously in reference toFIG.2B. Referring now toFIG.4, a layout for a radiation-hardened NMOS transistor400is depicted that demonstrates a technique to increase the conductivity of gate regions410that lack polycide because they are covered by silicide block pattern SB214. As explained with respect toFIG.2B, silicide regions will form on silicon and polysilicon surfaces except where blocked using a silicide blocking layer patterned using SB pattern214. During a CMOS fabrication process, the polysilicon layer is conventionally doped N+ or P+ at some point in the process to make it more conductive for interconnect, achieving a resistivity of the doped poly of on the order of a few tens of ohms per square. Later in the process, silicidation of the poly lowers the resistivity to only a few ohms per square. Even short lengths of un-silicided poly in the gate206can have a significant impact on series resistance and thus device performance. To reduce resistivity in such areas, an additional doping step referred to herein as “redoping” may be performed. In this step, a high-dose N+ implant is performed at least in regions containing rad-hard NMOS transistors of the design of the present invention. This implant may be performed before etching the gate, using a REDOPE pattern408to increase the n-type dopant concentration in the polysilicon layer over transistors400. REDOPE pattern408may be used to selectively restrict redoping only to areas418where it is wanted. The polysilicon gate material is doped by this implant, but since it occurs before the poly etch, the redoping implant may be blocked by the continuous polysilicon layer and by photoresist outside the REDOPE408pattern from impinging on areas where N+ doping is unwanted such as P-wells and PMOS transistors. In some fabrication processes, gate regions410would be effectively lightly-doped without this redoping process, due to NSD and PSD mask design requirements, and thus redoping is required. Assuming that there is a single doping step for polysilicon interconnects412outside the REDOPE408region,FIG.4labels areas in order of increasing conductivity after redoping and silicidation: regions410in silicide block areas214are redoped, but have no silicide, so have the lowest conductivity; regions412that receive doped poly from the rest of the IC process as well as silicide have a higher conductivity; and regions414corresponding to gate206regions across most of rad-hard NMOS transistor400that receive all of doping, redoping, and silicide have the highest conductivity (lowest resistivity). REDOPE pattern408can be designed several ways to restrict redoping. The smallest areas that need redoping are at least the gate areas410within the blocking pattern SB214. There is no need to restrict redoping to these small areas, with possibility of alignment problems. The redoping process can be restricted to individual rad-hard NMOS devices using a slightly larger REDOPE408pattern as shown inFIG.4resulting in a redoped region418large enough to encompass the entire NMOS transistor and not encounter any alignment issues. Finally, these redoping patterns might be applied only on certain dice or regions of a wafer (substrate). This strategy allows fabrication of rad-hard ICs on, e.g., a multi-project wafer (MPW) without interfering with the process used on other parts of the wafer by other customers. A schematic plan view of a semiconductor wafer500that may contain rad-hard devices in some IC dice and not others is shown inFIG.5. This drawing depicts a silicon wafer502containing at least two types of IC dice, rad-hard IC dice540and IC dice560that do not contain rad-hard devices. Dice560may belong to other customers of a multi-project wafer run, or may contain different products by the same owner. There may be more types of IC dice than two, having differing levels of radiation tolerance, circuit density, and device performance such as breakdown voltage and capacitance/speed. As discussed with respect to the p-type PWALL structures, tradeoffs between radiation tolerance and these performance parameters may be performed and devices and ICs tailored for these different tradeoffs using the principles taught herein. This may permit a company to optimize profit by customizing their product mix within a wafer, which is particularly important when few expensive wafers are being fabricated. Referring now toFIG.6A, an exemplary layout for a compact series-connected rad-hard NMOS transistor pair600is depicted. Neighboring series-connected transistors may not only touch, but can even share a diffusion210bas shown. Transistor pair600comprises a non-rad-hard NMOS transistor601adjacent to and contiguous with rad-hard NMOS transistor602; the source210bof transistor601overlaps the drain (also210b) in a shared (or merged) diffusion. Contiguous transistors can have larger partially-overlapping sources and drains, but complete overlap or “merging” source and drain into a single minimum-length shared NSD region210bas shown here minimizes device size and thus maximizes circuit density. Contacts306within may be deleted, for further space saving, if a series connection of the source of one transistor to the drain of the next is required without requiring a connection to other parts of a circuit. Transistor601is a conventional NMOS transistor without tabs, having gate206band diffusion region210cacting as a drain. It may be desirable to lay out transistor601non-rad-hard like this in order to optimize performance, since a rad-hard transistor has slightly higher capacitance due to the tab areas; but transistor601could also be a rad-hard transistor like602without increasing the required layout area, as will be discussed later in reference toFIG.6C. For further compactness, P+ body connection318is shown abutting source210aof transistor602, and body connection318can be shared with transistor601for its body connection in the same substrate area or P-well. An example of a circuit for a compact rad-hard CMOS logic gate650is shown inFIG.6B. A series transistor pair600as shown inFIG.6A, comprising transistors601(N1) and 602 (N2), may be used for the A logic input651and B logic input652of a NAND gate, which has a Y logic output655. (A and B label the logic inputs inFIG.6Band are not to be confused with the similarly-named dimensions in earlier figures.) PMOS transistors621(P1) and 622 (P2) are used conventionally, and their body connections are not shown for simplicity. Their sources are connected to positive supply node640(VDD). The source610aof rad-hard transistor602(N2) is connected to node630(VSSor ground) as is the shared body connection610d. The drain610cof transistor601(N1) is connected to transistors621(P1) and 622 (P2) as well as to logic output655(Y). Node610brepresents the internal connection of the drain of transistor602(N2) with the source of transistor601(N1) via the sharing of merged diffusion region210bas shown inFIG.6A. Series-connected NMOS transistors like this can be used in other circuits including analog circuits as will be seen later. It can be seen that the series pair600is rad-hard even though only one of its transistors is rad-hard. This is because in a series connection, only one of the transistors needs to have low radiation-induced leakage currents, since that rad-hard device will block leakage currents that would otherwise flow through the non-rad-hard device. Either transistor (or both) of the pair can be radiation-hardened to make a rad-hard series pair600. Thus, the position of a rad-hard transistor in the pair and the body connection may be selected to result in a minimum-size layout. Note that more than two NMOS transistors may be used in series, e.g., to make multiple-input NAND gates, and laid out using similar principles, and as long as one of a string of series-connected transistors is rad-hard (has low leakage in response to TID), the leakage will be limited for the entire string. Embodiments of the invention result in an improvement in rad-hard circuit density. A common metric for circuit density is the number of NAND gates per square millimeter that can be integrated; a typical benchmark value of the metric for a 180-nm commercial IC process is seventy to eighty thousand NANDs/mm2, and this technology can be used to approach that density. Since there is no connection to node610bwithin the series pair600as used in the NAND gate650, an even more compact layout can be achieved using the series pair design to be described now with reference toFIG.6C, which depicts a schematic plan view or layout of a series transistor pair605comprising two rad-hard transistors606and607sharing a common diffusion region210b. In this embodiment, because there are no contacts306within diffusion210b, the spacing p between gate206aof transistor607and gate206bof transistor606may be minimized as allowed by process design rules, for example, as small as a minimum gate length L as shown. Gates spaced this closely can share tabs216on ACTIVE202that have a width t wide enough to cover both gates. The same strategies as for a single rad-hard NMOS transistor200inFIG.2Aare used to design the blocking regions228,218, and214to create gap regions204by pulling back segments of the border of NSDB228from active region side boundaries222aand222b. These segments are made longer (longer length s) to cover the longer tabs216. Likewise, longer (longer length h) p-type bands PWALL212and similar gap widths and associated dimensions apply to this design. This design for series transistors is more compact than one using separate tabs216for each gate (e.g.,206aand206b), and the design can be extended for use with more than two gates simply by elongating tabs216in the length direction. The overall length H of active region202must just be long enough to accommodate the tabs216and to maintain separations216aand216bof the tabs from active region ends202aand202b, respectively, at least one of which is nonzero and that is equal to or greater than the minimum distance that is allowed by design rules. Referring now toFIG.6D, a schematic circuit diagram of a cascoded rad-hard current mirror670is shown, depicting an example application of rad-hard NMOS transistor series pairs600and605in analog circuitry. In this circuit, radiation-induced leakage is minimized by using the rad-hard transistor pairs600and605. The current mirror functions to generate an output current Ioat node675that mirrors the reference current Irefsupplied by reference current source645and entering node671. The circuit uses two diode-connected NMOS transistors, transistor601(N5) and cascoded transistor602(N6) within series pair600on the left-hand side, whose gates are connected to the gates of series pair605on the right-hand side comprising transistors607(N4) and 606 (N6). Contacts306within shared source/drain210bof transistor pair600are used to make the diode connections between gates and drains. The drain610cof transistor601(N5) is connected to reference current input node671, and drain610cof transistor606(N6) is connected to output current node675. The source nodes610aof both pairs, and all body connections, are connected to node630, shown here as VSSor ground, but may be at any potential sufficiently that is lower than the potential of current terminals671and675. (Note that the labeling of nodes610a,610b,610cand610dsimilarly within each of pairs600and605is not meant to indicate that they are connected to each other, but instead to show correspondence with diffusion regions210a,210b, and210cand body connection318in both.) Although transistor601may be non-rad-hard as discussed previously, and series-connected transistors600and605are referred to herein as “pairs” due to their compact layout, for optimal performance of a current mirror, it may be preferable to match the characteristics of the functional pair602-607(N3-N4), the lower pair in the schematic;601-606(N5-N6), the cascoded upper pair, need not be matched. A layout in which these transistors602and607(N3 and N4) share an active region could lead to better matching in a current mirror than using the pairs as illustrated inFIG.6D. In either case, not all four of the transistors need to be rad-hard, if the rad-hard transistors are judiciously deployed to limit radiation-induced leakage currents. Referring now toFIG.7, a flow chart is shown of a process700for fabricating a rad-hard device or integrated circuit according to the present invention. The process starts in step702by providing a substrate such as a silicon wafer having a P− surface layer. The P− surface layer may be an epitaxial layer, a P-well, or a wafer that is lightly-doped p-type throughout. In step704, a field oxide is formed in the surface of the substrate, which may be a planarized Shallow Trench Isolation field oxide that extends into the surface of the substrate. The field oxide is formed using an ACTIVE pattern that defines active regions within which the field oxide is absent and within which transistors will subsequently be formed. In an optional step706, moderately-doped p-type bands may be implanted using a PWALL pattern that positions p-type dopant along field oxide edges under where NMOS transistor gates will cross. Additional steps known to those with skill in the art may include growing a dummy gate oxide before an implantation step, and any conventionally required steps such as photoresist removal and cleaning steps that are not explicitly enumerated in the flow chart. In step708, a thin gate oxide is grown in the active region, after which a polysilicon (poly) layer is deposited in step710that will be used to form transistor gates and local interconnects. Another optional step712may then be performed before the gate layer is etched, which is to perform an additional N+ doping of the poly over rad-hard NMOS transistors that may later incorporate silicide that is blocked from forming over portions of their gates. This additional doping step712may be performed using a REDOPE pattern that restricts the N+ doping to regions of the substrate that contain at least one radiation-hardened NMOS device. Next, in step714, the poly is patterned and etched to form local interconnects and transistor gates, wherein a rad-hard transistor gate crosses from one edge to an opposite edge of a boundary of the active region defining a radiation-hardened NMOS device. After the gates are etched, steps to form lightly-doped drain (LDD) structures are performed, as represented by step716, in which source/drain extensions (“drain extensions”) on at least one side of a gate are formed using a pattern such as an NLDD Block pattern (NLDDB) that excludes the n-type doping of the LDD structures from within gap regions that will be defined by an NSD (n-type source/drain) implant pattern. Step718then comprises patterning and implanting NSD (N+ dopants) in source/drain diffusion regions of NMOS transistors, using an NSD or NSDB (NSD Block) pattern that excludes N+ doping from gap regions having a gap width g that are positioned adjacent at least one of the edges of the boundary of the active region, as described more fully with reference to the rad-hard NMOS device layouts shown inFIGS.2A and2Cand several other figures above. In some processes, the steps used in formation of LDD structures may exchange the order of steps716and718, but the order given is most commonly used in commercial processes. Then a common but optional step720of forming silicide may be performed, using one of several methods depending on the precise type of metal used to form the silicide. If silicide is formed, it is excluded from forming in the gap regions in the rad-hard NMOS devices within which NSD and NLDD are also excluded, and may use the exemplary salicide process flow that follows, which omits detailed description of some conventional steps such as cleaning processes. Step722in silicide formation process720involves depositing a silicide blocking layer (SBL) such as silicon oxide, silicon nitride, silicon oxynitride, or another material on which silicide will not form. The SBL is next patterned and etched in step724, using a silicide block (SB) pattern that allows the SBL material to remain over the gap regions in order to prevent formation of silicide in the gap regions. Photoresist used to pattern the SBL is removed in step726. Next, in step728, a silicide-forming metal is deposited, which may be one of several refractory metals known in the art such as titanium, cobalt, nickel, platinum, palladium, molybdenum, tungsten, and tantalum. The example process720shown inFIG.7assumes the use of cobalt as the silicide-forming metal. A sintering step730is performed to react metal in contact with silicon or polysilicon that is exposed in areas not covered by SBL in order to form a metal silicide. Unreacted metal is removed in step732using a selective etch, leaving silicided areas in transistor diffusion areas and polysilicon gates and interconnects, and unsilicided areas of silicon and polysilicon where the SB pattern left SBL material in step724. In the case of cobalt or some other metals, an additional anneal step734may be performed to convert the metal silicide from one phase (e.g., CoSi) to a phase (e.g., CoSi2) having lower resistivity, which in the case of cobalt silicides can be lower by a factor of 5-10. Thus, low-resistivity silicide is formed on silicon and polysilicon regions, but excluded from gap regions where silicide would short source-drain diffusions to a grounded substrate. If a silicide block (SB) pattern is used in step724that prevents silicide formation on portions of the gate polysilicon in rad-hard NMOS devices, then the optional redoping step712as described above may have been performed earlier in the process to raise the conductivity (i.e., lower the resistivity) of the unsilicided portions of the gate polysilicon. After the optional metal silicide has been formed and patterned to exclude it from the gap regions, all other remaining steps in device fabrication of the IC are performed in final step736, which may include removing the SBL, depositing and etching interlayer dielectrics and metal interconnect levels, and other conventional steps used to complete a functional integrated circuit. According to embodiments of the present invention, radiation-hardened NMOS transistor devices are provided that have low TID radiation-induced leakage currents and permit high-density circuit layouts. The transistor devices of the present invention are suitable for application individually, or in digital logic or analog circuitry within NMOS, CMOS, BiCMOS, and/or LDMOS integrated circuits, for operation in high-radiation environments. The rad-hard transistor devices provided by this invention may also be used in other applications requiring low leakage and high breakdown voltage, while allowing minimum gate-length designs for high speed. Embodiments of the present invention also provide integrated circuits (ICs) that contain these improved radiation hardened transistor devices, including compact combinations of rad-hard or both rad-hard and non-rad-hard transistors suitable for use in either digital or analog circuits with high circuit density. The Hardness-By-Design concepts presented herein can be applied to commercial IC processes and technologies that are not inherently radiation-hard, and the invention provides radiation hardened devices and circuits exhibiting lower Total Ionizing Dose radiation-induced leakage currents while maintaining high breakdown voltages and circuit densities approaching those in non-rad-hard ICs. The present invention also provides semiconductor wafers containing integrated circuit dice that include at least one radiation-hardened NMOS device, as well as variations in which wafers hold a plurality of IC dice having differing levels of radiation tolerance or having differing predetermined tradeoffs between radiation tolerance and performance. According to yet other embodiments of the present invention, methods for fabricating radiation hardened NMOS devices and ICs are provided that accommodate the improved design and layout techniques also provided herein, while supporting advanced IC processes incorporating lightly-doped drain (LDD) and silicidation techniques. Other applications of these techniques will also be apparent, and therefore the scope of the invention is much broader than the few specific examples described herein. While the present invention has been particularly shown and described in detail with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various modifications can be made in form and details therein without departing from the spirit and scope of the invention as set forth in the appended claims. The invention should therefore not be limited to the particular implementations discussed herein. | 47,576 |
11862725 | DETAILED DESCRIPTION Non-linearities in circuitry may cause harmonic distortion and/or intermodulation distortion that make it a challenge to maintain isolation between multiple signals. Third-order intermodulation distortion (IMD3) is the measure of the third-order distortion products produced by a non-linear device when multiple signals closely spaced in frequency are fed into the device as input. At least some of these distortion products are usually so close to the original (desired) frequencies that it is difficult to filter out the distortion product, and thus creates interference challenges in multichannel communication equipment. This disclosure is directed to, in part, a switching circuit that includes one or more Schottky barrier contacts integrated into a transistor. For example, a switch can include an input node, an output node, and a transistor connected between the input node and the output node. The transistor can control passage of a radio-frequency signal from the input node to the output node. The transistor can include a Schottky barrier contact integrated into a drain of the transistor and/or a Schottky barrier contact integrated into a source of the transistor. A Schottky barrier contact can be integrated at a substrate level into one or more layers of the transistor composition. Each Schottky barrier contact can compensate for a non-linearity effect of other elements of the transistor or switch, resulting in a substantially linear switch. As such, the switch can minimize harmonic and/or intermodulation distortion, such as third-order intermodulation distortion, third-order harmonics, and so on. Further, in examples, integrating a Schottky barrier contact into a transistor at a substrate level can avoid adding other elements to a switch at a circuit level (e.g., a distorter arm, auxiliary arm, etc.) to compensate for a non-linearity effect of components of the switch. FIG.1illustrates an example switch100having a Schottky barrier contact (SBC) transistor102. In particular, the SBC transistor102is electrically connected between an input node104and an output node106. The SBC transistor102can be controlled to allow passage of a signal from the input node104to the output node106. For example, when in an ON state, the SBC transistor102can pass a signal (e.g., a radio-frequency signal) received at the input node104to the output node106. When in an OFF state, the SBC transistor102can prevent passage of a signal from the input node104to the output node106. The input node104, the SBC transistor102, the output node106, and/or conductive material used to connect the components can form a signal path. As shown by a sectional view108, the SBC transistor102can include a substrate110and a P-well or N-well112formed in the substrate110or another layer disposed between the substrate110and the P-well or N-well112. In cases where an additional layer is included, the additional layer can include an insulator layer or another layer, as discussed in reference toFIGS.2A and2B. A source/drain114/116(sometimes referred to as the SBC source/drain114/116) can be formed by (i) doping the P-well or N-well112to form regions118and120and (ii) forming contacts122and124on the regions118and120, respectively. A gate126can also be formed on the P-well or N-well112, so as to be positioned between the source and the drain. In this example, the “N−” and “P−” of the regions118and120indicate that a concentration of a dopant in the regions118and120is classified as low doping or lightly doped, such as below a threshold. For instance, a dopant concentration for the regions118and120can be substantially less (e.g., by less than a threshold amount) than a dopant concentration of a region used for an ohmic contact. An ohmic contact is generally doped with a concentration that is classified as high doping or heavily doped (often represented as N+ or P+). In the example ofFIG.1, the regions118and120and the contacts122and124form Schottky barrier diodes, respectively. That is, the region118and the contact122form a first Schottky barrier diode, while the region120and the contact124form a second Schottky barrier diode. The SBC transistor102can be implemented as a variety of types of transistors. For example, a transistor can include a field-effect transistor (FET) (e.g., N-type or P-type device), such as a junction FET (JFET), insulated gate FET (e.g., a metal-oxide-semiconductor FET (MOSFET), a complementary metal-oxide-semiconductor (CMOS), etc.), a silicon-on-insulator (SOI) FET, and so on. Further, a transistor can include a Bipolar junction transistor (BJT) (e.g., an NPN transistor, a PNP transistor, etc.), such as a heterojunction bipolar transistor (HBT), etc. For ease of illustration, many examples are shown with the SBC transistor102implemented as a FET, such as a p-type or n-type FET. However, other types of transistors can be implemented. In examples, the SBC transistor102is implemented as a transistor stack. A transistor stack can include a plurality of transistors connected in series. A number of transistors in a stack can be scaled based on power requirements of a switch, such as to handle various power capabilities. An example implementation of a transistor stack is shown inFIG.7. For ease of illustration, the SBC transistor102is shown in many figures with a single device. However, it should be understood that the illustrated single device can represent one or more devices. In examples, a transistor of a switch or another component of a device in which the switch is implemented can have non-linear characteristics that contribute to the creation of distortion products. Distortion products can include harmonic distortion (HD) and/or intermodulation distortion (IMD). For instance, assume that an input signal with two frequency components (f1and f2) is provided to a switch. The two frequency components can be separated by each other. Non-linearities in the switch can cause an output signal to include not only the original two frequency components, but additional frequency components at different frequencies, such as second-order harmonic distortion products (e.g., 2f1and 2f2), second-order intermodulation products (e.g., f1+f2and f2-f1), third-order harmonic distortion products (e.g., 3f1and 3f2), third-order intermodulation products (e.g., 2f1-f2and 2f2-f1), and so on. In examples, second-order and third-order distortion products are of particular interest, since these distortion products are often relatively close to the original input frequency components. In general, as power levels decrease, the intermodulation distortion order number increases. To illustrate, when original frequency components f1and f2are relatively near each other in frequency (e.g., within a threshold amount), the third-order intermodulation products are also relatively nearby in frequency. This can make it difficult to filter out the third-order intermodulation products while retaining the original frequency components f1and f2. Accordingly, it is valuable to reduce the generation of third-order harmonic and intermodulation products by reducing non-linearity characteristics of a device or switch rather than by attempting to remove the intermodulation products later. In examples, higher order products, such as fourth-order and fifth-order products, can also be of interest. As such, the switch100discussed herein minimizes or compensates for non-linearities produced by the switch100and/or a device in which the switch100is implemented. For example, the switch100includes the SBC source/drain114/116having Schottky barrier diodes to minimize or compensate for distortion products, such as third-order intermodulation products, third-order harmonics, and so on. FIGS.2A and2Billustrate plan and side sectional views of an example SBC transistor200formed using silicon-on-insulator (SOI) technology. In examples, SOI technology can include a semiconductor substrate having an embedded layer of electrically insulating material, such as a buried oxide layer (also referred to as a BOX) beneath a silicon device layer. For example, a SOI substrate can include an oxide layer embedded below a silicon layer. Other insulating materials can also be used. SOI technology can enable reduced power consumption of device circuitry due to decreased parasitic capacitance of transistors and interconnect metallization to a silicon substrate. Presence of a buried oxide layer can also reduce junction capacitance or use of high resistivity substrate, enabling reduced substrate related RF losses. Electrically isolated SOI transistors can facilitate stacking, contributing to decreased chip size. In this example, the SBC transistor200is configured as a finger-based device where the source and drain are rectangular shaped (in a plan view) and a gate structure extends between the source and the drain like a rectangular shaped finger. Although illustrated as a finger-based device, the SBC transistor200can be configured as other types of devices shaped in different manners. The SBC transistor200can include the substrate110(also referred to as the semiconductor substrate110). The substrate110can include a P-type silicon wafer, an N-type silicon wafer, etc. An insulator layer202(also referred to as the BOX202) can be formed on the semiconductor substrate110. The insulator layer202can be formed from materials including, for example, silicon dioxide, sapphire, etc. A P-well or N-well112can be formed in the insulator layer202such that the exposed surface generally defines a rectangular region. The regions118and120can be N-doped or P-doped and can generally include exposed surfaces that define rectangles. The SBC source/drain114/116can be configured so that source and drain are positioned on either side of the gate126. As shown, the gate126can be formed on the P-well or N-well112so the gate126is positioned between the source and the drain. A gate oxide layer204can be formed between the gate126and the P-well or N-well112. Here, the example gate126is depicted as having a rectangular shape that extends along with the source and the drain. A body contact206(sometimes referred to as the body206) can also be formed by (i) doping the P-well or N-well112to form a region208and (ii) forming a contact210on the region208. In this example, the “P+” and “N+” of the region208indicate that the region208is doped with a concentration that is classified as high doping or heavily doped. The contact122, the contact124, and/or the contact210can be formed of a variety of metals, such as titanium, nickel, platinum, cobalt, any combination thereof, or any other metal. Further, the contact122, the contact124, and/or the contact210can be formed of doped silicon (e.g., highly doped silicon) or another material. The SBC transistor200can be implemented as an N-channel or P-channel device. For example, when implemented as an N-channel device, the regions118and120of the SBC source/drain114/116can be N-regions, the P-well or N-well112can be a P-well, and the region208of the body206can be a P+ region. Alternatively, when implemented as a P-channel device, the regions118and120of the SBC source/drain114/116can be P− regions, the P-well or N-well112can be an N-well, and the region208of the body206can be an N+ region. In some example transistors discussed herein, source and drain regions can be formed adjacent to the ends of their respective upper insulator layers. Further, the junctions between the body and the source/drain regions on the opposing sides of the body can extend substantially all the way down to the top of the buried insulator layer. Such a configuration can provide, for example, reduced source/drain junction capacitance. To form a body contact for such configuration, an additional gate region can be provided on the side so as to allow, for example, an isolated P+ region to contact a P-well. FIG.3illustrates an example process300of forming an SBC transistor. The process300can be part of or include a semiconductor device fabrication process that is performed, at least in part, by one or more systems having one or more hardware components. At302, an insulator layer is formed on a substrate. The substrate can include a P-type silicon wafer, an N-type silicon wafer, another semiconductor substrate, etc. The insulator layer can include silicon dioxide, sapphire, or another insulator. At304, a P-well or N-well is formed in the insulator layer or the substrate. For example, a region within the insulator layer can be P-doped or N-doped to form a P-well or N-well within the insulator layer. At306, a gate dielectric is formed on the P-well or N-well. For example, the gate dielectric can be formed of an insulating layer of silicon dioxide. The gate dielectric can comprise a gate oxide layer that separates a gate contact from the P-well or N-well. At308, a gate contact is formed on the gate dielectric. The gate contact (also referred to as the gate electrode, gate metal, or gate conductor) can be made of a conductive material, such as a highly doped silicon or a metal. The operations306and/or308can form a gate for the SBC transistor. At310, a body portion is formed on the P-well or N-well. For example, the body portion can be formed by P-doping or N-doping the P-well or N-well to form a doped region (e.g., P+ or N+) and forming a conductive layer on the doped region. The conductive layer can be made of a conductive material, such as highly doped silicon, a metal, etc. At312, an SBC source or drain is formed on the P-well or N-well. For example, an SBC source/drain can be formed by N-doping or P-doping the P-well or N-well to form a doped region (e.g., N- or P−) and forming a conductive layer on the doped region. The conductive layer can be made of a conductive material, such as highly doped silicon, a metal, etc. FIG.4illustrates an example frequency spectrum graph400of output signals from different systems. The graph400shows power spectrum density at a load in dBm with respect to frequency in GHz. In this example, an input signal with two frequency components at 1.75 GHz and 2 GHz is provided into a system, and power is detected. The input signal with frequency components is also referred to as fundamental signals. As shown, the power of third-order intermodulation distortion (IMD3)402for an example system that does not include an SBC transistor (e.g., a switch with another type of transistor) is about −86 dBm. Further, the power of IMD3404for an example system that includes an SBC transistor (e.g., a switch with an SBC transistor) is about −95 dBm. As such, the system with the SBC transistor has about a 9 dBm reduction in power for IMD3 in comparison to the system without the SBC transistor. Although not illustrated, other harmonic/intermodulation distortion can also be reduced by implementing the system with the SBC transistor. Further, power for the output signals of the fundamental signals can remain about the same. In examples, the SBC transistors discussed herein can reduce a signal strength of distortion products, such as third-order harmonic/intermodulation distortion products. Improved switching device intermodulation distortion performance can be desirable for wireless communication devices operating in various wireless communication standards, such as the LTE communication standard. In some applications, it can be desirable to improve linearity of switching devices operating in wireless communication devices that enable simultaneous transmission of data and voice communication. For example, improved intermodulation distortion performance in switching devices can be desirable for wireless communication devices operating in the LTE communication standard and performing simultaneous transmission of voice and data communication (e.g., SVLTE). FIG.5Aillustrates an example I-V graph500of signals from different systems. The graph500shows drain-source current with respect to voltage. As shown, a line502indicates the current and voltage for a switch without an SBC transistor. Further, a line504indicates the current and voltage for a switch with an SBC transistor. As illustrated, the switch with the SBC transistor produces substantially more linearity than the switch without the SBC transistor (e.g., the line504is substantially more linear than the line502). FIG.5Billustrates an example graph506of values for the third order derivatives of the I-V curves ofFIG.5Aas a function of drain-source voltage (Vds). The third order derivatives are related to IMD3. In particular, points508represent values for a switch with an SBC transistor, while points510represent values for a switch without an SBC transistor. As shown, the switch with the SBC transistor reduces the magnitude of third derivatives of the IV curve to under 100 dBm, which correlates to a reduction in the IMD3 products. FIG.6illustrates a switch600having multiple switch arms and multiple shunt arms. This example illustrates a single-pole-double-throw (SPDT) switch. However, any number of poles and/or throws can be implemented. As shown, the switch600includes a single pole602, a first throw604, and a second throw606. Each pole or throw can also be referred to as a port or node. The pole602is coupled to the first throw604via a transistor608, while the pole602is coupled to the second throw606via a transistor610. The first throw604is coupled to a ground via a transistor612to provide shunting capability for the first throw604. Similarly, the second throw606is coupled to a ground via a transistor614to provide shunting capability for the second throw606. The arm with the transistor608and the arm with the transistor610can each be referred to as a switch arm or series arm. Meanwhile, the arm with the transistor612and the arm with the transistor614can each be referred to as a shunt arm. Although illustrated with shunt arms, in some examples shunt arms are not included. In examples, the transistors608,610,612, and/or614can be implemented as any of the SBC transistors discussed herein. In an example operation, when the switch600is in a state where a signal is being passed between the pole602and the first throw604, the transistor608can be in an ON state, and the transistor610between the pole602and the second throw606can be in an OFF state. Further, the transistor612can be in an OFF state so that the signal is not shunted to ground as the signal travels from the pole602to the first throw604. The transistor614associated with the second throw606can be in an ON state so that any signals or noise arriving at the switch through the second throw606are shunted to the ground, thus reducing undesirable interference effects. FIG.7illustrates an example transistor stack700. The transistor stack700includes multiple transistors connected in series between a first node702and a second node704. Although twelve transistors are shown inFIG.7, any number of transistors can be used for a transistor stack. In examples, one or more of the SBC transistors discussed herein can be implemented as a transistor stack. For instance, the SBC transistor102ofFIG.1can be implemented as a transistor stack, so that multiple transistors are positioned in series between the input node104and the output node106, with one or more of the transistors being implemented as an SBC transistor. FIG.8illustrates example biasing circuitry800for a transistor802. In this example, a source and/or drain of the transistor802is connected to a source/drain biasing circuit804that applies a biasing voltage to the source and/or drain of the transistor802, a body of the transistor802is connected to a body biasing circuit806that applies a biasing voltage to the body of the transistor802, and a gate of the transistor802is connected to a gate biasing circuit808that applies a biasing voltage to the gate of the transistor802. The source/drain biasing circuit804, the body biasing circuit806, and/or the gate biasing circuit808can apply voltages that are more or less than a value to control the transistor802(e.g., place the transistor an in ON or OFF state). In examples, the transistor802can be representative of any of the transistors discussed herein. That is, any of the transistors discussed herein can be biased in a similar manner as that of the example biasing circuitry800of the transistor802. As such, although not illustrated in some cases, any of the transistors discussed herein can be connected to any number of biasing circuits to control the transistors. FIG.9illustrates an example radio-frequency module900. The radio-frequency module900includes a packaging substrate902, a semiconductor die904mounted on the packaging substrate902, a switch906implemented on the semiconductor die904, and a biasing circuit908implemented on the semiconductor die904. Although illustrated on the semiconductor die904, in some cases the biasing circuit908is implemented as part of the switch906. In some examples, the radio-frequency module900can be a front-end module (FEM). The radio-frequency module900can facilitate, for example, multi-band, multi-mode operation of a radio-frequency device. The switch906can include any of the switches and/or SBC transistors discussed herein. FIG.10illustrates an example radio-frequency device1000. As shown, the radio-frequency device1000can include a baseband sub-system1002, a transceiver1004, a power amplifier (PA) module1006, a duplexer1008, a switch1010, one or more antennas1012, a power management system1014, a battery1016, a memory1018, and a user interface1020. The baseband sub-system1002, the transceiver1004, the PA module1006, the duplexer1008, the switch1010, one or more antennas1012, the power management system1014, the battery1016, the memory1018, and/or the user interface1020can be in communication with each other. The baseband sub-system1002can be connected to the user interface1020to facilitate various input and/or output of voice and/or data provided to and/or received from a user. The baseband sub-system1002can also be connected to the memory1018that is configured to store data and/or instructions to facilitate operation of the radio-frequency device1000and/or to provide storage of information for a user. The transceiver1004can generate radio-frequency (RF) signals for transmission and/or process incoming RF signals received from the one or more antennas1012. The transceiver1004can interact with the baseband sub-system1002that is configured to provide conversion between data and/or voice signals suitable for a user and/or RF signals suitable for the transceiver1004. The transceiver1004can also be connected to the power management system1014. The PA module1006can include a plurality of PAs that can provide an amplified RF signal to the switch1010(e.g., via the duplexer1008). The PA module1006can also receive an unamplified RF signal from the transceiver1004. In examples, the duplexer1008can allow transmit and/or receive operations to be performed simultaneously using a common antenna. InFIG.10, received signals are shown to be routed to “Rx” paths that can include, for example, a low-noise amplifier (LNA). The switch1010can route an RF signal to and/or from the one or more antennas1012. The switch1010can include any number of poles and/or throws. The switch1010can be implemented as any of the switches discussed herein. In examples, the switch1010is implemented on a module1022. The module1022can include a packaging substrate configured to receive a plurality of components. Although one switch1010is illustrated in the example ofFIG.10, any number of switches can be implemented on the radio-frequency device1000. The one or more antennas1012can include antennas for transmitting and/or receiving signals associated with a wide variety of frequencies and communications standards. In examples, the one or more antennas1012support Multiple-Input Multiple-output (MIMO) communications and/or switched diversity communications. For example, MIMO communications use multiple antennas for communicating multiple data streams over a single radio frequency channel. MIMO communications benefit from higher signal to noise ratio, improved coding, and/or reduced signal interference due to spatial multiplexing differences of the radio environment. Switched diversity refers to communications in which a particular antenna is selected for operation at a particular time. For example, a switch can be used to select a particular antenna from a group of antennas based on a variety of factors, such as an observed bit error rate and/or a signal strength indicator. In examples, the one or more antennas1012can include a diversity antenna. The power management system1014can be configured to manage power for operation of the radio-frequency device1000. The power management system1014can provide power to any number of components of the radio-frequency device1000. The power management system1014can receive a battery voltage from the battery1016. The battery1016can be any suitable battery for use in the radio-frequency device1000, including, for example, a lithium-ion battery. The radio-frequency device1000can communicate using a wide variety of communications technologies, including, but not limited to, 2G, 3G, 4G (including Long Term Evolution (LTE), LTE-Advanced, and LTE-Advanced Pro), 5G NR, Wireless Local Area Network (WLAN) (for instance, Wi-Fi), Wireless Personal Area Network (WPAN) (for instance, Bluetooth and ZigBee), Wireless Metropolitan Area Network (WMAN) (for instance, WiMax), and/or satellite-based radio navigation systems (for instance, Global Positioning System (GPS) technologies). The radio-frequency device1000can operate with beamforming in certain implementations. For example, the radio-frequency device1000can include phase shifters having variable phase controlled by the transceiver1004. Additionally, the phase shifters are controlled to provide beam formation and directivity for transmission and/or reception of signals using the one or more antennas1012. For example, in the context of signal transmission, the phases of the transmit signals provided to the one or more antennas1012are controlled such that radiated signals from the one or more antennas1012combine using constructive and destructive interference to generate an aggregate transmit signal exhibiting beam-like qualities with more signal strength propagating in a given direction. In the context of signal reception, the phases are controlled such that more signal energy is received when the signal is arriving to the one or more antennas1012from a particular direction. In certain implementations, the one or more antennas1012include one or more arrays of antenna elements to enhance beamforming. In examples, the radio-frequency device1000supports carrier aggregation, thereby providing flexibility to increase peak data rates. Carrier aggregation can be used for both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD), and can be used to aggregate a plurality of carriers or channels. Carrier aggregation includes contiguous aggregation, in which contiguous carriers within the same operating frequency band are aggregated. Carrier aggregation can also be non-contiguous, and can include carriers separated in frequency within a common band or in different bands. The radio-frequency device1000can include a wide variety of devices that are configured to communicate wirelessly. For example, the radio-frequency device1000can include a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a smart appliance, a smart vehicle, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, an automobile, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wearable device (e.g., a watch), a clock, etc. The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Further, the word “connected” can refer to two or more elements that are either directly connected or connected by way of one or more intermediate elements. Components discussed herein can be coupled or connected in a variety of manners, such as through a conductive material. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The above description of embodiments of the disclosure is not intended to be exhaustive or to limit the disclosure to the precise form disclosed above. While specific embodiments, and examples, are described above for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. For example, while processes or blocks may be presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times. The features described herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. While some embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. Claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. | 31,555 |
11862726 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. FIG.1is a schematic cross-sectional view of an integrated circuit IC in accordance with some embodiments of the disclosure. In some embodiments, the integrated circuit IC includes a substrate20, an interconnect structure30, a passivation layer40, a post-passivation layer50, a plurality of conductive pads60, and a plurality of conductive terminals70. In some embodiments, the substrate20is made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The substrate20may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the substrate20includes various doped regions depending on circuit requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions are doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. In some embodiments, these doped regions serve as source/drain regions of a first transistor T1, which is over the substrate20. Depending on the types of the dopants in the doped regions, the first transistor T1may be referred to as n-type transistor or p-type transistor. In some embodiments, the first transistor T1further includes a metal gate and a channel under the metal gate. The channel is located between the source region and the drain region to serve as a path for electron to travel when the first transistor T1is turned on. On the other hand, the metal gate is located above the substrate20and is embedded in the interconnect structure30. In some embodiments, the first transistor T1is formed using suitable Front-end-of-line (FEOL) process. For simplicity, one first transistor T1is shown inFIG.1. However, it should be understood that more than one first transistors T1may be presented depending on the application of the integrated circuit IC. When multiple first transistors T1are presented, these first transistors T1may be separated by shallow trench isolation (STI; not shown) located between two adjacent first transistors T1. As illustrated inFIG.1, the interconnect structure30is disposed on the substrate20. In some embodiments, the interconnect structure30includes a plurality of conductive vias32, a plurality of conductive patterns34, a plurality of dielectric layers36, and a plurality of second transistors T2. As illustrated inFIG.1, the conductive patterns34and the conductive vias32are embedded in the dielectric layers36. In some embodiments, the conductive patterns34located at different level heights are connected to one another through the conductive vias32. In other words, the conductive patterns34are electrically connected to one another through the conductive vias32. In some embodiments, the bottommost conductive vias32are connected to the first transistor T1. For example, the bottommost conductive vias32are connected to the metal gate, which is embedded in the bottommost dielectric layer36, of the first transistor T1. In other words, the bottommost conductive vias32establish electrical connection between the first transistor T1and the conductive patterns34of the interconnect structure30. As illustrated inFIG.1, the bottommost conductive via32is connected to the metal gate of the first transistor T1. It should be noted that in some alternative cross-sectional views, other bottommost conductive vias32are also connected to source/drain regions of the first transistor T1. That is, in some embodiments, the bottommost conductive vias32may be referred to as “contact structures” of the first transistor T1. In some embodiments, a material of the dielectric layers36includes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, the dielectric layers36may be formed of oxides or nitrides, such as silicon oxide, silicon nitride, or the like. The dielectric layers36may be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, a material of the conductive patterns34and the conductive vias32includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive patterns34and the conductive vias32may be formed by electroplating, deposition, and/or photolithography and etching. In some embodiments, the conductive patterns34and the underlying conductive vias32are formed simultaneously. It should be noted that the number of the dielectric layers36, the number of the conductive patterns34, and the number of the conductive vias32illustrated inFIG.1are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of the dielectric layers36, the conductive patterns34, and/or the conductive vias32may be formed depending on the circuit design. In some embodiments, the second transistors T2are embedded in the interconnection structure30. For example, each second transistor T2is embedded in one of the dielectric layer36. In some embodiments, the second transistors T2are electrically connected to the conductive patterns34through the corresponding conductive vias32. The formation method and the structure of the second transistors T2will be described in detail later. As illustrated inFIG.1, the passivation layer40, the conductive pads60, the post-passivation layer50, and the conductive terminals70are sequentially formed on the interconnect structure30. In some embodiments, the passivation layer40is disposed on the topmost dielectric layer36and the topmost conductive patterns34. In some embodiments, the passivation layer40has a plurality of openings partially exposing each topmost conductive pattern34. In some embodiments, the passivation layer40is a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer formed by other suitable dielectric materials. The passivation layer40may be formed by suitable fabrication techniques such as HDP-CVD, PECVD, or the like. In some embodiments, the conductive pads60are formed over the passivation layer40. In some embodiments, the conductive pads60extend into the openings of the passivation layer40to be in direct contact with the topmost conductive patterns34. That is, the conductive pads60are electrically connected to the interconnect structure30. In some embodiments, the conductive pads60include aluminum pads, copper pads, titanium pads, nickel pads, tungsten pads, or other suitable metal pads. The conductive pads60may be formed by, for example, electroplating, deposition, and/or photolithography and etching. It should be noted that the number and the shape of the conductive pads60illustrated inFIG.1are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, the number and the shape of the conductive pads60may be adjusted based on demand. In some embodiments, the post-passivation layer50is formed over the passivation layer40and the conductive pads60. In some embodiments, the post-passivation layer50is formed on the conductive pads60to protect the conductive pads60. In some embodiments, the post-passivation layer50has a plurality of contact openings partially exposing each conductive pad60. The post-passivation layer50may be a polyimide layer, a PBO layer, or a dielectric layer formed by other suitable polymers. In some embodiments, the post-passivation layer50is formed by suitable fabrication techniques such as HDP-CVD, PECVD, or the like. As illustrated inFIG.1, the conductive terminals70are formed over the post-passivation layer50and the conductive pads60. In some embodiments, the conductive terminals70extend into the contact openings of the post-passivation layer50to be in direct contact with the corresponding conductive pad60. That is, the conductive terminals70are electrically connected to the interconnect structure30through the conductive pads60. In some embodiments, the conductive terminals70are conductive pillars, conductive posts, conductive balls, conductive bumps, or the like. In some embodiments, a material of the conductive terminals70includes a variety of metals, metal alloys, or metals and mixture of other materials. For example, the conductive terminals70may be made of aluminum, titanium, copper, nickel, tungsten, tin, and/or alloys thereof. The conductive terminals70are formed by, for example, deposition, electroplating, screen printing, or other suitable methods. In some embodiments, the conductive terminals70are used to establish electrical connection with other components (not shown) subsequently formed or provided. As mentioned above, the second transistors T2are embedded in the interconnection structure30. Taking the topmost second transistor T2shown inFIG.1as an example, the formation method and the structure of this second transistor T2will be described below in conjunction withFIG.2AtoFIG.2J. FIG.2AtoFIG.2Jare schematic perspective views illustrating various stages of a manufacturing method of the second transistor T2inFIG.1. Referring toFIG.2A, a dielectric layer100is provided. In some embodiments, the dielectric layer100is one of the dielectric layers36of the interconnection structure30ofFIG.1, so the detailed descriptions thereof is omitted herein. Thereafter, an insulating layer200is formed on the dielectric layer100. In some embodiments, the insulating layer200is formed on the dielectric layer100such that a top surface of the dielectric layer100is covered by the insulating layer200. A material of the insulating layer200may be the same as or different from the material of the dielectric layer100. In some embodiments, the insulating layer200is formed of a low-k dielectric material having a dielectric constant (k-value) lower than about 3.0, about 2.5, or even lower. In some embodiments, the insulating layer200is formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), or the like. In some alternative embodiments, the material of the insulating layer200includes polyimide, epoxy resin, acrylic resin, phenol resin, BCB, PBO, or any other suitable polymer-based dielectric material. The insulating layer200may be formed by suitable fabrication techniques such as spin-on coating, CVD, PECVD, or the like. Referring toFIG.2B, a portion of the insulating layer200is removed to partially expose the underlying dielectric layer100. In other words, the insulating layer200partially covers the underlying dielectric layer100. In some embodiments, the insulating layer200is patterned through a photolithography and etching process. For example, a patterned photoresist layer (not shown) is formed on the insulating layer200shown inFIG.1Ato define the shape of the insulating layer200shown inFIG.2B. Thereafter, an etching process is performed to remove the insulating layer200that is not covered by the patterned photoresist layer. The etching process includes, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. Subsequently, the patterned photoresist layer is removed through a stripping process or the like to expose the remaining insulating layer200. Referring toFIG.2C, a source/drain material layer300′ is formed on the dielectric layer100and the insulating layer200. In some embodiments, the source/drain material layer300′ covers the top surface of the dielectric layer100. Meanwhile, the source/drain material layer300′ also covers a top surface and sidewalls of the insulating layer200. For example, the source/drain material layer300′ exhibits an upside down U-shape when viewing from a side. In some embodiments, the source/drain material layer300′ is made of cobalt, tungsten, copper, titanium, tantalum, aluminum, zirconium, hafnium, a combination thereof, or other suitable metallic materials. In some embodiments, the source/drain material layer300′ is formed through CVD, atomic layer deposition (ALD), plating, or other suitable deposition techniques. Referring toFIG.2CandFIG.2D, a portion of the source/drain material layer300′ is removed to form a source region300aand a drain region300b. For example, the source/drain material layer300′ inFIG.2Cis thinned until the underlying insulating layer200is exposed, so as to form the source region300aand the drain region300b. In some embodiments, the source/drain material layer300′ is thinned through a grinding process, such as a mechanical grinding process, a chemical mechanical polishing (CMP) process, or the like. After grinding, a top surface of the source region300a, a top surface of the drain region300b, and a top surface of the insulting layer200are substantially coplanar. In some embodiments, after the insulating layer200is exposed, the source region300a, the drain region300b, and the insulating layer200may be further grinded to reduce the total thickness of the subsequently formed second transistor T2. As illustrated inFIG.2D, the source region300aand the drain region300bare respective formed on two opposite ends of the insulating layer200. For example, the source region300aand the drain300bare respectively in physical contact with opposite sidewalls of the insulating layer200. That is, the insulating layer200is sandwiched between the source region300aand the drain region300bto electrically isolate the source region300aand the drain region300b. In some embodiments, the source region300aextends along a first direction D1. Similarly, the drain region300balso extends along the first direction D1. In other words, the source region300ais parallel to the drain region300b. On the other hand, the insulating layer200extends from the source region300ato the drain region300balong a second direction D2perpendicular to the first direction D1. Referring toFIG.2E, a channel layer400is deposited on the source region300a, the drain region300b, and the insulating layer200. For example, the channel layer400is in physical contact with top surfaces of the source region300a, the drain region300b, and the insulating layer200. In some embodiments, the channel layer400includes metal oxide materials. Examples of the metal oxide materials include ITZOx, IGZOx, TZOx, ATZOx, ZnOx, the like, or a combination thereof. In some embodiments, these metal oxide materials are also being referred to as oxide semiconductor materials. In some embodiments, the channel layer400is made of a single layer having one of the foregoing materials. However, the disclosure is not limited thereto. In some alternative embodiments, the channel layer400may be made of a laminate structure of at least two of the foregoing materials. In some embodiments, the channel layer400is doped with a dopant to achieve extra stability. In some embodiments, the channel layer400is deposited by suitable techniques, such as CVD, ALD, physical vapor deposition (PVD), PECVD, epitaxial growth, or the like. As mentioned above, the channel layer400is formed such that the channel layer400is in physical contact with the top surface of the insulating layer200. However, the disclosure is not limited thereto. In some alternative embodiments, depending on the material of the insulating layer200and the material of the channel layer400, another layer may be generated between the channel layer400and the insulating layer200during the deposition of the channel layer400. Such scenario is shown inFIG.3, which is a schematic perspective view illustrating an intermediate stage of the manufacturing method of the second transistor T2in accordance with some alternative embodiments. Referring toFIG.3, an intermixing layer IM is formed between the overlapping region of the insulating layer200and the channel layer400. For example, during the formation of the channel layer400, the material of the channel layer400would react with the material of the insulating layer200to form the intermixing layer IM. In some embodiments, a portion of the insulating layer200is being consumed during the reaction to form the intermixing layer IM. As such, as illustrated inFIG.3, the top surface of the insulating layer200is located at a level height lower than that of the top surface of the source region300aand the top surface of the drain region300b. On the other hand, a top surface of the intermixing layer IM is located at a level height higher than that of the top surface of the source region300aand the top surface of the drain region300b. As illustrated inFIG.3, the channel layer400is in physical contact with top surfaces of the source region300a, the intermixing layer IM, and the drain region300b. In some embodiments, the material of the intermixing layer IM includes ITZOx, IGZOx, TZOx, ATZOx, ZnOx, a combination thereof, or the like. Referring toFIG.2F, a ferroelectric layer500is formed over the channel layer400. In some embodiments, a material of the ferroelectric layer500includes AlOx, HfOx, HfZrOx, SiOx, a combination thereof, or the like. In some embodiments, the ferroelectric layer500is formed through a non-plasma deposition process. The non-plasma deposition process denotes a deposition process which does not involve the introduction of plasma. The non-plasma deposition process includes, for example, ALD, CVD, or the like. In some embodiments, the ferroelectric layer500is deposited at a temperature ranging from about 200° C. to about 400° C. In some embodiments, since the ferroelectric layer500is formed through the non-plasma deposition process, during the formation of the ferroelectric layer500, the material of the ferroelectric layer500would react with the material of the channel layer400to form an interfacial layer600between the channel layer400and the ferroelectric layer500. In other words, the interfacial layer600is sandwiched between the channel layer400and the ferroelectric layer500. For example, the interfacial layer600is in physical contact with a top surface of the channel layer400and a bottom surface of the ferroelectric layer500. In some embodiments, the interfacial layer600is a byproduct layer generated from the formation of the ferroelectric layer500, so the thickness t600of the interfacial layer600is small. For example, the interfacial layer600is formed to have the thickness t600of about 1 nm to about 5 nm. In some embodiments, a material of the interfacial layer600includes ITOy, ZnOy, HfZrOy, a combination thereof, or the like. In some embodiments, since the interfacial layer600is a product of the reaction between the material of the channel layer400and the material of the ferroelectric layer500, the precursors of the interfacial layer600are originated from the channel layer400and the ferroelectric layer500. That is, the interfacial layer600includes chemical elements that are originated from the chemical elements of the channel layer400and the chemical elements of the ferroelectric layer500. However, since the material of the channel layer400and the material of the ferroelectric layer500undergo a reaction, the resulting material (i.e. the material of the interfacial layer600) is different from the material of the channel layer400and the material of the ferroelectric layer500. In some embodiments, the material of the interfacial layer600includes chemical elements that are different from the chemical elements of the material of channel layer400and the chemical elements of the material of the ferroelectric layer500. For example, when the channel layer400is formed of ITZOx, the resulting interfacial layer600may be made of ITOy, in which the indium atom, the tin atom, and the oxygen atoms are coming from the ITZO of the channel layer400. However, the disclosure is not limited thereto. In some alternative embodiments, the material of the interfacial layer500may include chemical elements that are the same as the chemical elements of the material of the channel layer500or the chemical elements of the material of the ferroelectric layer500, but with different elemental compositions. For example, when the ferroelectric layer500is formed of HfZrOx, the resulting interfacial layer600may be made of HfZrOy, where x is different from y. It should be noted that although the chemical elements in the ferroelectric layer500and the interfacial layer600are the same, due to the difference in elemental compositions, the material of the interfacial layer600is still being considered as different from the material of the ferroelectric layer500. In some embodiments, since the interfacial layer600and the channel layer400are made of different materials, a first interface IF1exists between the interfacial layer600and the channel layer400. Similarly, since the interfacial layer600and the ferroelectric layer500are made of different materials, a second interface IF2exists between the interfacial layer600and the ferroelectric layer500. Conventionally, the ferroelectric layer is formed by a plasma deposition process such as PVD or PECVD. However, with the presence of plasma, the underlying channel layer would be damaged during the formation of the ferroelectric layer. For example, the plasma bombardment on the channel layer during the formation of the ferroelectric layer would damage the channel layer, thereby causing defects. When the channel width is too big, the defects in the channel layer cannot be fully removed/recovered by the subsequent annealing process. The defects in the channel layer would result in gate leakage, which causes degrades in current on/off ratio (Ion/Ioffratio). As a result, the performance of the subsequently formed transistor is compromised. However, as mentioned above, the ferroelectric layer500is formed by a non-plasma deposition process. Therefore, the plasma-induced defect can be reduced significantly or even eliminated. With further annealing in the subsequent processes, the defects coming from other processes can be removed/recovered, thereby rendering a substantially defect-free channel layer400. As a result, the degradation of the Ion/Ioffratio may be prevented, and the performance of the subsequently formed second transistor T2may be ensured. Referring toFIG.2G, a gate electrode700is formed on the ferroelectric layer500. In some embodiments, the gate electrode700is formed on the ferroelectric layer500such that the top surface of the ferroelectric layer500is covered by the gate electrode700. In some embodiments, the gate electrode includes a metallic material. The metallic material of the gate electrode700includes copper, titanium, tantalum, tungsten, aluminum, zirconium, hafnium, cobalt, titanium aluminum, tantalum aluminum, tungsten aluminum, zirconium aluminum, hafnium aluminum, any other suitable metal-containing material, or a combination thereof. In some embodiments, the gate electrode700also includes materials to fine-tune the corresponding work function. For example, the metallic material of the gate electrode700may include p-type work function materials such as Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or combinations thereof, or n-type work function materials such as Ag, TaCN, Mn, or combinations thereof. In some embodiments, the metallic material is deposited through ALD, CVD, PVD, or the like. In some embodiments, a barrier layer (not shown) is optionally formed between the gate electrode700and the ferroelectric layer500, so as to avoid diffusion of atoms between elements. In some embodiments, a material of the barrier layer includes titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or a combination thereof. Referring toFIG.2GandFIG.2H, the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400are patterned to expose at least a portion of the source region300a, at least a portion of the drain region300b, and at least a portion of the insulating layer200. In some embodiments, the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400are patterned through a photolithography and etching process. For example, a patterned photoresist layer (not shown) is formed on the gate electrode700shown inFIG.2Gto define the shape of the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400shown inFIG.2H. Thereafter, an etching process is performed to remove the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400that are not covered by the patterned photoresist layer. The etching process includes, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. Then, the patterned photoresist layer is removed through a stripping process or the like to obtain the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400shown inFIG.2H. In some embodiments, the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400are patterned simultaneously through the same process, so a contour of the channel layer400, a contour of the interfacial layer600, a contour of the ferroelectric layer500, and a contour of the gate electrode700are substantially identical. In other words, sidewalls of the channel layer400, sidewalls of the ferroelectric layer500, sidewalls of the interfacial layer600, and sidewalls of the gate electrode700are aligned. In some embodiments, a width W400of the channel layer400, a width W600of the interfacial layer600, a width W500of the ferroelectric layer500, and a width W700of the gate electrode700are substantially the same. As mentioned above, since the ferroelectric layer500is formed by a non-plasma process, the channel width (i.e. the width W400) can be as large as possible without considering the ability to remove the defects in the subsequent annealing process. For example, the width W400of the channel layer400, the width W600of the interfacial layer600, the width W500of the ferroelectric layer500, and the width W700of the gate electrode700range from about 0.2 μm to about 10 μm. In some embodiments, the channel layer400, the interfacial layer600, the ferroelectric layer500, and the gate electrode700are sequentially stacked on the source region300a, the drain region300b, and the insulating layer200. In some embodiments, since the ferroelectric layer500is disposed between the channel layer400and the gate electrode700, the ferroelectric layer500may serve as a gate dielectric layer in the subsequently formed second transistor T2. As illustrated inFIG.2H, the channel layer400, the interfacial layer600, the ferroelectric layer500, and the gate electrode700extend along a second direction D2perpendicular to the first direction D1. Since the source region300aand the drain region300bextend along the first direction D1, the channel layer400, the interfacial layer600, the ferroelectric layer500, and the gate electrode700are arranged perpendicular to the source region300aand the drain region300b. For example, the channel layer400, the interfacial layer600, the ferroelectric layer500, and the gate electrode700extend from the source region300ato the drain region300b, as illustrated inFIG.2H. In some embodiments, the channel layer400is divided into a first portion400a, a second portion400b, and a third portion400cconnecting the first portion400aand the second portion400b. In some embodiments, the first portion400aof the channel layer400is located directly above the source region300a, the second portion400bof the channel layer400is located directly above the drain region300b, and the third portion400cof the channel layer400is located directly above the insulating layer200. Similarly, the interfacial layer600is also divided into a first portion600a, a second portion600b, and a third portion600cconnecting the first portion600aand the second portion600b. In some embodiments, the source region300aand the first portion400aof the channel layer400are located directly underneath the first portion600aof the interfacial layer600. The drain region300b, the second portion400bof the channel layer400are located directly underneath the second portion600bof the interfacial layer600. Moreover, the insulating layer200and the third portion400cof the channel layer400are located directly underneath the third portion600cof the interfacial layer600. In some embodiments, the ferroelectric layer500is also divided into a first portion500a, a second portion500b, and a third portion500cconnecting the first portion500aand the second portion500b. In some embodiments, the source region300a, the first portion400aof the channel layer400, and the first portion600aof the interfacial layer600are located directly underneath the first portion500aof the ferroelectric layer500. The drain region300b, the second portion400bof the channel layer400, and the second portion600bof the interfacial layer600are located directly underneath the second portion500bof the ferroelectric layer500. Moreover, the insulating layer200, the third portion400cof the channel layer400, and the third portion600cof the interfacial layer600are located directly underneath the third portion500cof the ferroelectric layer500. In some embodiments, the gate electrode700is also divided into a first portion700a, a second portion700b, and a third portion700cconnecting the first portion700aand the second portion700b. In some embodiments, the source region300a, the first portion400aof the channel layer400, the first portion600aof the interfacial layer600, and the first portion of the ferroelectric layer500are located directly underneath the first portion700aof the gate electrode700. The drain region300b, the second portion400bof the channel layer400, the second portion600bof the interfacial layer600, and the second portion500bof the ferroelectric layer500are located directly underneath the second portion700bof the gate electrode700. Moreover, the insulating layer200, the third portion400cof the channel layer400, the third portion600cof the interfacial layer600, and the third portion500cof the ferroelectric layer500are located directly underneath the third portion700cof the gate electrode700. As illustrated inFIG.2H, the first portion400aof the channel layer400, the first portion600aof the interfacial layer600, the first portion500aof the ferroelectric layer500, and the first portion700aof the gate electrode700are located directly above the source region300a. In other words, the first portion400aof the channel layer400, the first portion600aof the interfacial layer600, the first portion500aof the ferroelectric layer500, and the first portion700aof the gate electrode700are sequentially stacked on the source region300a. For example, the source region300a, the first portion400aof the channel layer400, the first portion600aof the interfacial layer600, the first portion500aof the ferroelectric layer500, and the first portion700aof the gate electrode700are vertically overlapped with one another. Similarly, the second portion400bof the channel layer400, the second portion600bof the interfacial layer600, the second portion500bof the ferroelectric layer500, and the second portion700bof the gate electrode700are located directly above the drain region300b. In other words, the second portion400bof the channel layer400, the second portion600bof the interfacial layer600, the second portion500bof the ferroelectric layer500, and the second portion700bof the gate electrode700are sequentially stacked on the drain region300b. For example, the drain region300b, the second portion400bof the channel layer400, the second portion600bof the interfacial layer600, the second portion500bof the ferroelectric layer500, and the second portion700bof the gate electrode700are vertically overlapped with one another. Moreover, the third portion400cof the channel layer400, the third portion600cof the interfacial layer600, the third portion500cof the ferroelectric layer500, and the third portion700cof the gate electrode700are located directly above the insulating layer200. In other words, the third portion400cof the channel layer400, the third portion600cof the interfacial layer600, the third portion500cof the ferroelectric layer500, and the third portion700cof the gate electrode700are sequentially stacked on the insulating layer200. For example, the insulating layer200, the third portion400cof the channel layer400, the third portion600cof the interfacial layer600, the third portion500cof the ferroelectric layer500, and the third portion700cof the gate electrode700are vertically overlapped with one another. In some embodiments, the overlapping of these elements allows the formation of memory cells in the subsequently formed second transistor T2. That is, memory cells are integrated within the second transistor T2. The configurations of these memory cells will be described below. In some embodiments, the source region300a, the first portion400aof the channel layer400, the first portion600aof the interfacial layer600, the first portion500aof the ferroelectric layer500, and the first portion700aof the gate electrode700collectively form a first memory cell MC1. On the other hand, the drain region300b, the second portion400bof the channel layer400, the second portion600bof the interfacial layer600, the second portion500bof the ferroelectric layer500, and the second portion700bof the gate electrode700collectively form a second memory cell MC2that is spatially apart from the first memory cell MC1. In some embodiments, due to its material characteristics, the ferroelectric layer500may be utilized to trap electrons. For example, the ferroelectric layer500may be utilized to store data. As such, in some embodiments, the ferroelectric layer500is referred to as a “storage layer.” In some embodiments, the source region300aand the first portion700aof the gate electrode700respectively serve as a bottom electrode and a top electrode of the first memory cell MC1. Meanwhile, the first portion500aof the ferroelectric layer500may serve as a storage layer of the first memory cell MC1. Similarly, the drain region300band the second portion700bof the gate electrode700respectively serve as a bottom electrode and a top electrode of the second memory cell MC2. Meanwhile, the second portion500bof the ferroelectric layer500may serve as a storage layer of the second memory cell MC2. In some embodiments, since the storage layers of the first memory cell MC1and the second memory cell MC2are made of ferroelectric materials, the first memory cell MC1and the second memory cell MC2may be considered as memory cells for a FeRAM (Ferroelectric Random Access Memory). In some embodiments, after the gate electrode700, the ferroelectric layer500, the interfacial layer600, and the channel layer400are patterned, an annealing process is performed on the structure illustrated inFIG.2Hto remove defects in the channel layer400originated from processes other than the deposition of the ferroelectric layer500. In some embodiments, the annealing process includes a rapid thermal annealing process followed by a laser annealing process. In some embodiments, the annealing process is performed in a chamber filled with O2gas, N2gas, or a combination thereof. In some embodiments, after the annealing process, the channel layer400is substantially defect-free. Referring toFIG.2HandFIG.2I, an interlayer dielectric layer800is formed on the insulating layer200, the source region300a, the drain region300b, the channel layer400, the interfacial layer600, the ferroelectric layer500, and the gate electrode700. For example, the interlayer dielectric layer800covers the exposed top surface of the insulating layer200, the exposed top surface of the source region300a, the exposed top surface of the drain region300, and the top surface of the gate electrode700. Meanwhile, the interlayer dielectric layer800also covers sidewalls of the channel layer400, sidewalls of the interfacial layer600, sidewalls of the ferroelectric layer500, and sidewalls of the gate electrode700. For example, the interlayer dielectric layer800exhibits an upside down U-shape when viewing from a side. In some embodiments, a material and a formation method of the interlayer dielectric layer800are similar to that of the dielectric layer100and/or the insulating layer200, so the detailed descriptions thereof are omitted herein. Referring toFIG.2J, a portion of the interlayer dielectric layer800is removed to obtain the second transistor T2. For example, the interlayer dielectric layer800is thinned until the underlying gate electrode700is exposed. In some embodiments, the interlayer dielectric layer800is thinned through a grinding process, such as a mechanical grinding process, a CMP process, or the like. After grinding, a top surface of the gate electrode700is substantially coplanar with a top surface of the interlayer dielectric layer800. In some embodiments, after the gate electrode700is exposed, the interlayer dielectric layer800and the gate electrode700may be further grinded to reduce the total thickness of the second transistor T2. In some embodiments, since the second transistor T2includes the ferroelectric layer500, the second transistor T2may be referred to as a FeFET (Ferroelectric Field-Effect Transistor). In some embodiments, source/drain contacts (not shown) are formed to penetrate through the interlayer dielectric layer800, so as to connect the source region300a/the drain region300bwith external elements. For example, referring toFIG.2IandFIG.1, some of the conductive vias32shown inFIG.1may serve as source/drain connects to electrically connect the source region300a/the drain region300bwith the conductive patterns34. Similarly, the conductive vias32may also serve as gate contacts that electrically connect the gate electrode700and the conductive patterns34. In other words, the second transistor T2is electrically connected to the first transistor T1and the conductive terminals70through the conductive vias32and the conductive patterns34of the interconnection structure30. In some embodiments, the second transistors T2are embedded in the interconnection structure30, which is being considered as formed during back-end-of-line (BEOL) processes. Please be noted that since the channel layer400, the interfacial layer600, the ferroelectric layer500, and the gate electrode700are located behind the cross-sectional view inFIG.1, these elements are shown by dotted line inFIG.1. As illustrated inFIG.1, each second transistor T2is a standalone transistor. However, the disclosure is not limited thereto. In some alternative embodiments, multiple second transistors T2may be arranged in an array. The configurations of the transistor arrays will be described below in conjunction withFIG.4andFIG.5. FIG.4is a schematic perspective view of a transistor array A1in accordance with some embodiments of the disclosure. Referring toFIG.4, the transistor array A1includes four second transistors T2. In some embodiments, these four second transistors T2are identical. In some embodiments, the source regions300aand the drain regions300bof these second transistors T2are electrically isolated from one another by the insulating layer200. On the other hand, two adjacent second transistors T2arranged along the second direction D2share the same gate electrode700. In other words, the gate electrode700extends continuously from a second transistor T2to an adjacent second transistor T2along the second direction D2. For example, the gate electrodes700of two adjacent second transistors T2arranged along the second direction D2are electrically connected to each other. On the other hand, the gate electrodes700of two adjacent second transistors T2arranged along the first direction D1are electrically isolated from each other. As mentioned above, each second transistor T2includes two memory cells (i.e. the first memory cell MC1and the second memory cell MC2). Therefore, in the transistor array A1ofFIG.4, eight memory cells are presented. As such, the transistor array A1inFIG.4may be referred to as a memory array as well. Please be noted that althoughFIG.4illustrated that the transistor array A1includes four second transistors T2, the disclosure is not limited thereto. In some alternative embodiments, the number of the second transistors T2in the transistor array A1may be adjusted based on demand. FIG.5is a schematic perspective view of a transistor array A2in accordance with some alternative embodiments of the disclosure. Referring toFIG.5, the transistor array A2includes four second transistors T2. In some embodiments, two adjacent second transistors T2arranged along the second direction D2share the same source region300a. That is, two adjacent transistors T2arranged along the second direction D2are electrically connected to each other. Similarly, two adjacent second transistors T2arranged along the second direction D2share the same gate electrode700. In other words, the gate electrode700extends continuously from a second transistor T2to an adjacent second transistor T2along the second direction D2. For example, the gate electrodes700of the two adjacent second transistors T2arranged along the second direction D2are electrically connected to each other. On the other hand, the gate electrodes700of the two adjacent second transistors T2arranged along the first direction D1are electrically isolated from each other. As mentioned above, each second transistor T2includes two memory cells (i.e. the first memory cell MC1and the second memory cell MC2). However, since two adjacent second transistors T2arranged along the second direction D2share the same memory cell, in the transistor array A2ofFIG.5, six memory cells are presented. In some embodiments, the transistor array A2inFIG.5may be referred to as a memory array as well. Please be noted that althoughFIG.5illustrated that the transistor array A2includes four second transistors T2, the disclosure is not limited thereto. In some alternative embodiments, the number of the second transistors T2in the transistor array A2may be adjusted based on demand. In accordance with some embodiments of the disclosure, a transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer. In accordance with some embodiments of the disclosure, an integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate. The interconnect structure includes dielectric layers and at least one second transistor embedded in one of the dielectric layers. The second transistor includes a source region, a drain region, a channel layer, an interfacial layer, a storage layer, and a gate electrode. The source region and the drain region extend along a first direction. The channel layer, the interfacial layer, the storage layer, and the gate electrode are sequentially stacked on the source region and the drain region. The channel layer, the interfacial layer, the storage layer, and the gate electrode extend along a second direction perpendicular to the first direction. In accordance with some embodiments of the disclosure, a manufacturing method of a transistor includes at least the following steps. A dielectric layer is provided. An insulating layer is formed to partially cover the dielectric layer. A source region and a drain region are formed on two opposite ends of the insulating layer. A channel layer is deposited on the insulating layer, the source region, and the drain region. A ferroelectric layer is formed over the channel layer through a non-plasma deposition process such that an interfacial layer is formed between the channel layer and the ferroelectric layer. A gate electrode is formed on the ferroelectric layer. The gate electrode, the ferroelectric layer, the interfacial layer, and the channel layer are patterned to expose at least a portion of the insulating layer, at least a portion of the source region, and at least a portion of the drain region. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 47,660 |
11862727 | DESCRIPTION OF THE EMBODIMENTS The invention provides the manner to fabricate the FinFETm in which the silicon fin may be fabricated by perform partial nitridation treatment on the stress buffer film (SBF) to convert into nitride. The nitride from the stress buffer film may provide a polishing stop, so that some mask layers to protect fin may be omitted. Multiple embodiments are provided for describing the invention but the invention is not just limited to the embodiments. FIGS.1A-1Dare drawings, schematically illustrating a fabrication flow as looking into for forming a fin structure on a substrate in a cross-section view, according to an embodiment of the invention. Referring toFIG.1A, as looked into by the invention, to form the thin fins at the upper portion of the substrate50, multiple dielectric protecting layers, including a pad oxide layer52, a pad nitride layer54and an oxide mask layer56are sequentially formed on the substrate50. The substrate50for forming the fin is silicon in an embodiment. The pad oxide layer52, the pad nitride layer54and the oxide mask layer56in the usual manner are preliminarily formed and would be involved in the mechanism for the subsequent fin polishing and etching processes. Referring toFIG.1B, the pad oxide layer52, the pad nitride layer54, the oxide mask layer56and the substrate50are patterned to form the silicon fins80, on which a residual portion of the pad oxide layer52, the pad nitride layer54, the oxide mask layer56as a stack remain on the top of the silicon fins80. At current stage, the silicon fins80with the stack dielectric at top form as a fin structure. A stress buffer film (SBF)58is then form the formed on the substrate50and is conformally covering over the fin structure. In addition, before forming the SBF58is formed, an atomic layer deposition (ALD) layer57as an option may also be formed conformally covering over the fin structures. A flowable dielectric layer60is formed over the substrate to cover the fin structure, which includes the pad oxide layer52, the pad nitride layer54, the oxide mask layer56and the silicon fin80. The flowable dielectric layer60in an example is formed by flowable chemical vapor deposition (FCVD) process with the suitable material of oxide. The flowable dielectric layer60usually is annealed for curing and increasing density into a hard isolation dielectric with higher density. The SBF58as form of amorphous silicon may protect the silicon fin80from oxidation in an example and also provide the stress buffer effect to the silicon fin80which is thin as viewed in the cross-section structure. Referring toFIG.1C, the flowable dielectric layer60after annealing process for curing and increasing density is polished by chemical mechanical polishing (CMP) process. In this polishing process, the nitride layer54may serve as the polishing stop. Referring toFIG.1D, to expose the silicon fin80, a dielectric etching process is performed to remove the upper portion of the flowable dielectric layer60. Then, the upper portion of the silicon fin80is exposed to provide the fin to form the FinFET in the subsequent processes. Here, the descriptions for the subsequent fabrication processes to form the FinFET are omitted and the invention does not limit the subsequent fabrication processes. As looked into in the invention, the pad oxide layer52, the pad nitride layer54, and the oxide mask layer56are involved, so as to provide the fin polishing stop and resist the dielectric etching process to expose the silicon fin80. As investigated in the invention when looking into the procedure inFIG.1AtoFIG.1D, the pad oxide layer52and the pad nitride layer54may be skipped with slightly modification. As a result, the fabrication may be simplified and the fabrication cost may be reduced. FIGS.2A-2Iare drawings, schematically illustrating a fabrication flow for forming a fin structure on a substrate in a cross-section view, according to an embodiment of the invention. Referring toFIG.2A, a substrate100, such as a silicon wafer or a silicon on insulator (SOI) substrate is provided. The substrate100provide the semiconductor property to form the channel latter for the FinFET. In an embodiment, the mask layer102as a single layer is preliminarily formed on the substrate100. As noted in viewing toFIG.1A, a single mask layer is formed. The mask layer102is an oxide layer in an embodiment. To form the thin fins in an embodiment, a plurality of mandrels104with the intended width is formed on the mask layer102. A spacer106is formed on the sidewall of the mandrels104. There, the thickness of the spacer106is reserved, corresponding to the width of the fin as to be formed form the FinFET. Referring toFIG.2B, the mandrels104are removed while the spacer106remains. At this stage, a portion of the mask layer102as previously cover by the mandrels104is exposed. Referring toFIG.2D, the spacer106is used as the etching mask to etch the substrate100through the mask layer102. Due to the etching selectivity as set, the substrate100in silicon and the spacer106in oxide are etched. After etching process, the silicon fins110are formed at the upper portion of the substrate100. A residual portion of the mask layer102is still disposed on top of the silicon fin110. The gap between the fins form the trench108to expose the substrate100and the sidewall of the silicon fin110. Referring toFIG.2E, a SBF112is formed conformally covering over the fin structure as composed of the silicon fin110and the mask layer102at the top. As also previously stated, an ALD layer111as an option may be formed before forming SBF112. The material of the SBF112is amorphous silicon to protect the silicon fin110in the subsequent annealing process at the high temperature. As noted, the thickness of the SBF112is actually rather thinner than the fin width. The drawing is not at the actual scale as should be noted. In an embodiment of the invention, after the SBF112is formed, a nitridation treatment114is performed on the SBF112. Due to the property of the amorphous silicon of the SBF112, the SBF112may be partially nitridation to partially form nitride in the SBF112. Referring toFIG.2F, here, the SBF112in an embodiment is not in full nitridation to completely convert into silicon nitride. At the stage, the previous SBF112is then changed to the SBF112′, which partially include the nitride portion. This nitride portion may provide as the polishing stop and the silicon material as remined may resist oxidation layer to the silicon fin110for protection effect as to be described. Referring toFIG.2G, a flowable dielectric layer116, such as flowable oxide, is formed over the substrate100to fully fill into the trench108and cover the SBF112′. An annealing process is performed on the flowable dielectric layer116for curing and increasing density. The silicon material in the SBF112′ may provide the stress buffering effect on the silicon fin110. In addition, the annealing process may also cause oxidation on the silicon material. However, the silicon fin110is protected by the SBF112′, which still contains silicon material. The annealing process may be oxidized the SBF112′ but significantly not on the silicon fin110. Referring toFIG.2H, after annealing process for curing and increasing density on the flowable dielectric layer116, the polishing process is performed over the substrate100. It should be noted that the SBF112′ contains nitride portion due to the nitridation treatment114inFIG.2E. The nitride portion may serve as the polishing stop to replace the nitride layer54as stated inFIG.1Calthough the nitride layer54is not actually formed in the embodiment. Referring toFIG.2I, a dielectric etching process is performed to the flowable dielectric layer116to remove its upper portion. Also, the mask layer102and the SBF112′ are also removed in the same etching process. As a result, the upper portion of the silicon fin110is exposed to provide the fin for forming the FinFET in the subsequent fabrication process. As noted in the fabrication procedure, the nitride layer54and the pad oxide layer52, referring toFIG.1A, are saved in the invention. In addition, the nitridation treatment114as referring toFIG.2Eis additionally performed on the SBF112to change into the SBF112′ with nitride portion to provide the polishing stop instead of the nitride layer54. As also noted, the SBF112′ at the lower sidewall of the silicon fin110contains the nitride portion. The top of the silicon fin110in the embodiment just has the single mask layer102, which may be relatively weak to resist the dielectric etching process to expose the silicon fin110. As a result, the top of the silicon fin110is a round-like shape as viewed in cross-section while comparing toFIG.1Din an example. However, the round-like shape at the cross-section view does not significantly affect the channel function for the FinFET when the gate line perpendicularly crossing over the silicon fin110, which is actually a fin line in structure as formed. Although the invention is described with reference to the above embodiments, the embodiments are not intended to limit the invention. A person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention should be subject to the appended claims. | 9,394 |
11862728 | DETAILED DESCRIPTION One or more embodiments or implementations are now described with reference to the enclosed figures. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may also be employed in a variety of other systems and applications other than what is described herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout to indicate corresponding or analogous elements. It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, over, under, and so on, may be used to facilitate the discussion of the drawings and embodiments and are not intended to restrict the application of claimed subject matter. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter defined by the appended claims and their equivalents. In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to “an embodiment” or “one embodiment” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). The term “adjacent” here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it). The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms “over,” “under,” “front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material “over” a second material in the context of a figure provided herein may also be “under” the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies. The term “between” may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material “between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value. Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. The term layer as used herein may include a single material or multiple materials. As used in throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. Semiconductor device structures, devices, apparatuses, computing platforms, and methods are described below related to dual gate thin film transistors. As described above, it may be advantageous to provide improved thin film transistor (TFT) structures. In an embodiment, a TFT structure includes a non-planar semiconductor TFT layer. As used herein, a semiconductor TFT layer or simply semiconductor layer may include any suitable semiconductor thin film such as an amorphous or polycrystalline semiconductor material. A polycrystalline material includes any material having micro-scale or nano-scale crystal grains and include nanocrystalline materials. For example, nanocrystalline materials include materials having crystallites that are not larger than 5 nm (e.g., 0.5 to 5 nm in cross sectional length). An amorphous material may be any material that lacks long range order (e.g., has no structural order) and includes interconnected material blocks. As discussed, the non-planar semiconductor TFT layer is non-planar. As used herein, the term non-planar refers to any layer having one or more non-planar surfaces such that the surface deviates from a particular plane. The term non-planar as used herein indicates one or more portions of the non-planar layer are substantially out of plane with respect to other portions and may be contrasted with substantially planar surfaces that are merely not perfectly planar. For example, a non-planar semiconductor TFT layer may include a first portion over a first gate dielectric layer and a second portion conformal to one or more sidewalls of a trench within a patterned layer such that the patterned layer is adjacent to the first gate dielectric layer and the non-planar layer. For example, a surface of the first gate dielectric layer and the sidewall(s) of the trench may be at an angle with respect to one another such as substantially orthogonal or the like. For example, such a TFT structure may be characterized as a trench-type TFT structure as the non-planar semiconductor layer conforms to a trench. As discussed, a first portion of the non-planar semiconductor TFT layer maybe over a first gate dielectric layer. A first gate electrode structure may be adjacent the first gate dielectric layer and opposite the first portion such that the first gate electrode structure may control (e.g., exert an electric field on) the first portion of the non-planar semiconductor TFT layer. Furthermore, at least a portion of a second gate electrode structure may be in the trench of the patterned layer and adjacent to the first portion of the non-planar semiconductor TFT layer such that a second gate dielectric layer is between the first portion and the second gate electrode structure. Thereby the first gate electrode may also control (e.g., exert an electric field on) the first portion of the non-planar semiconductor TFT layer. As used herein, the term in or within a trench indicates that the structure is at least partially below or within a surface that would define a boundary of the trench. For example, the surface defining a boundary of a trench extends to connect top edges of sidewalls of the trench. A body that is at least partially in a trench has a portion thereof that extends into the trench across that boundary, either partially or entirely (e.g., the body may be partially or entirely within the trench). The TFT structure may further include a source and a drain coupled to the non-planar semiconductor TFT layer. Such TFT structures provide dual gate control via the first and second gate electrode structures. The first and second gate electrode structures may be integrated such that the same control (e.g., control signal, switching signal, bias, etc.) is provided via the two gate electrode structures or they may be separate such that different control is provided by the first gate electrode structure with respect to the second gate electrode structure. Such dual gate architectures provide for advantageous control and operational characteristics of non-planar or trench-type TFT structures. For example, dual gate electrode structures (e.g., dual gates) provide for improved short channel control while maintaining low contact resistance and low parasitic gate to source/drain coupling capacitance. For example, the source to drain pathway for non-planar or trench-type TFT structures is longer to provide improved gate control using a second gate. Furthermore, non-planar or trench-type TFT structures provide improved density with respect to planar TFT structures and improved performance as device density increases. For example, non-planar or trench-type TFT structures provide increased effective gate lengths without increasing the lateral footprint of the TFT. As discussed, a second gate electrode structure extends within a trench and adjacent to a first portion of the non-planar semiconductor TFT layer. For example, the second gate electrode structure extends along the non-planar semiconductor TFT layer on the sidewall of the patterned layer defining the trench. The second gate electrode structure may include a portion of the second gate dielectric layer on a sidewall of the second gate electrode. In some embodiments, a dielectric spacer layer is provided between the non-planar semiconductor TFT layer on the sidewall and the second gate dielectric layer. Such embodiments provide for lower capacitance coupling from the source/drain to the gate. Furthermore, such embodiments may provide doping of the non-planar semiconductor TFT layer via the dielectric spacer layer. In other embodiments, a portion of the source and a portion of the drain are provided between the non-planar semiconductor TFT layer and the second gate dielectric layer. Such embodiments provide for lower contact resistances and maximized overlap for contact area to improve drive current. FIG.1Aillustrates a cross-sectional view of an example thin film transistor structure100andFIG.1Bis a top-down view of thin film transistor structure100, arranged in accordance with at least some implementations of the present disclosure. As shown,FIG.1Aprovides a cross-sectional view along an x-z plane andFIG.1Bprovides a top-down view along the A-plane inFIG.1A(e.g., along an x-y plane). As illustrated, the x-y plane may be in-plane, in-line, or the like with respect to a lateral direction of thin film transistor structure100and the z-direction may be perpendicular with respect to the lateral direction of thin film transistor structure100. As shown, thin film transistor structure100may include a substrate101, a gate electrode structure102, a gate dielectric layer103, a patterned layer104, a non-planar semiconductor layer105, a sidewall spacer106, a gate dielectric layer107, a gate electrode structure108, a source109, and a drain110. Notably, thin film transistor structure100includes a dual gate architecture including gate electrode structure102, gate dielectric layer103, gate dielectric layer107, and gate electrode structure108. For example, a portion of non-planar semiconductor layer105acts as a semiconductor channel for thin film transistor structure100. In some embodiments, gate electrode structure102and gate electrode structure108are the same material or material(s). In other embodiments, gate electrode structure102has a different composition than gate electrode structure108. Similarly, in some embodiments, gate dielectric layer103and gate dielectric layer107are the same material or material(s) while in other embodiments, they have different compositions. Furthermore, gate electrode structure102and gate electrode structure108may be integrated such that the same control (e.g., control signal, switching signal, bias, etc.) is provided via they may be separate such that different control is provided by gate electrode structure102with respect to gate electrode structure108. In an embodiment, gate electrode structure102may provide a body potential to control VTwhile gate electrode structure108switches the on/off state of thin film transistor structure100. In such embodiments, gate dielectric layer103may be advantageously thicker than gate dielectric layer107. For example, gate dielectric layer103may be not less than 30% thicker than gate dielectric layer107. Such integrated or separate control via gate electrode structures102,108may be provided via circuitry (not shown) such as metal interconnect structures. Thin film transistor structure100includes a non-planar or trench-type TFT structure as illustrated with respect to non-planar semiconductor layer105. Such structures provide for provide improved density with respect to planar TFT structures and improved performance as device density increases. As shown, non-planar semiconductor layer105includes a portion121that is immediately adjacent to and conformal to gate dielectric layer103. For example, portion121is co-planar with gate dielectric layer103such that it extends laterally along gate dielectric layer103. Non-planar semiconductor layer105also includes portions122,123that are along sidewalls124,125of a trench (not labeled inFIG.1A) of patterned layer104. As shown, in some embodiments, portions122,123may extend substantially orthogonally with respect to portion121. In some embodiments, portions122,123extend outwardly from portion121such that the trench is at least partially dished. In an embodiment, non-planar semiconductor layer105has, from a cross-sectional perspective, a substantially U-shaped structure. In an embodiment, non-planar semiconductor layer105has a concave shape. For example, non-planar semiconductor layer105and the portions thereof are substantially conformal to a trench defined by a surface128of gate dielectric layer103and sidewalls124,125of patterned layer104and to plateaus129,130of patterned layer104. As used herein, the term conformal indicates a layer conforms to an underling structure although the conformity may be at the same or differing thicknesses of the layer across the conforming are. Although patterned layer104is illustrated with multiple sidewalls124,125, patterned layer104may have a single sidewall around the trench. As shown, gate electrode structure108is partially within a trench formed by non-planar semiconductor layer105and by surface128and sidewalls124,125as discussed above. For example, gate electrode structure108includes a portion131within a trench defined by surface128and sidewalls124,125such that portion131is between sidewalls124,125and below plateaus129,130. Furthermore, at least a portion of gate electrode structure108(including portion131) is laterally between portions126,127and portions122,123of non-planar semiconductor layer105. As shown, gate electrode structure108extends to proximal of portion121of non-planar semiconductor layer105such that gate electrode structure108may apply an electric field to portion121when a bias is applied thereto. Gate dielectric layer107is between gate electrode structure108and portion121and on sidewalls of gate electrode structure108(e.g., between sidewall spacer106and gate electrode structure108). Sidewall spacer106is between various portions of non-planar semiconductor layer105and gate dielectric layer107and between source109and gate dielectric layer107as well as between drain110and gate dielectric layer107. Sidewall spacer106may include any suitable dielectric material and sidewall spacer106reduces capacitance coupling from source109and drain110to gate electrode structure108. As shown, a portion of sidewall spacer106extends over portion126of non-planar semiconductor layer105and another portion of sidewall spacer106extends over portion127of non-planar semiconductor layer105. Furthermore, as shown, a bottom of sidewall spacer106extends to portion121of non-planar semiconductor layer105. In an embodiment, sidewall spacer106is not employed. Source109and drain110are coupled to non-planar semiconductor layer105via portions126,127, respectively. In some embodiments, source109and drain110are on non-planar semiconductor layer105and, in other embodiments, an intervening layer is provided therebetween. Substrate101may be any suitable material or materials. In some embodiments, substrate101includes a semiconductor material such as monocrystalline silicon substrate, a silicon on insulator, or the like. In some embodiments, substrate101include metallization interconnect layers for integrated circuits or electronic devices such as transistors, memories, capacitors, resistors, optoelectronic devices, switches, or any other active or passive electronic devices separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or the like. In an embodiment, substrate101includes underlying layers and devices discussed with respect toFIG.23. In an embodiment, a top surface or layer of substrate101includes a dielectric material for isolation and interconnect (e.g., metallization) routing to gate electrode structure108. Gate electrode structures102,108may be any suitable material or materials. Gate electrode structures102,108may include at least one P-type work function metal or N-type work function metal, depending on whether the thin film transistor structure100is to be included in a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor. For a PMOS transistor, metals that may be used for the gate electrode structures102,108include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). Such materials may be provided individually or in combination. For an NMOS transistor, metals that may be used for the gate electrode structures102,108include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode structures102,108be a stack of two or more metal layers such that one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as to act as a barrier layer. As discussed, in some embodiments, gate electrode structures102,108are the same material(s) while in other embodiments they have different material(s). Furthermore, gate dielectric layers103,107may be any suitable dielectric material or materials. In some embodiments, gate dielectric layers103,107are high-k dielectric material layers having dielectric constants of not less than that of silicon dioxide. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layers103,107include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. Gate dielectric layers103,107may have any suitable thickness such as thicknesses in the range of 0.5 to 5 nm. In some embodiments, gate dielectric layers103,107are the same material(s) while in other embodiments they have different material(s). As discussed, thin film transistor structure100employs non-planar semiconductor layer105. Thin film transistor structure100performance depends on the composition of the semiconductor employed as non-planar semiconductor layer105. Thin film transistor structure100may include any applicable thin film semiconductor material, including traditional group IV semiconductor materials such as silicon (Si), germanium (Ge), and SiGe alloys. In some embodiments, non-planar semiconductor layer105is crystalline (e.g., a single crystal) SI, Ge, or SiGe. In other embodiments, thin film transistor structure100may include III-V semiconductor materials. In some embodiments, non-planar semiconductor layer105is a crystalline (e.g., a single crystal) III-V semiconductor such as gallium nitride (GaN), indium gallium arsenic (InGaAs), etc. Furthermore, thin film transistor structure100may include amorphous (e.g., having no structural order) or polycrystalline (e.g., having micro-scale to nano-scale crystal grains) semiconductor materials including those discussed above. In some embodiments, non-planar semiconductor layer105is amorphous or polycrystalline Si, Ge, SiGe, III-V semiconductor, GaN, or InGaAs. In some embodiments, non-planar semiconductor layer105employs an oxide semiconductor. An oxide semiconductor is a semiconducting oxide, or a semiconductor comprising oxygen. For such embodiments, a wide band gap oxide channel material offers low leakage. Semiconducting properties vary with the oxide semiconductor composition and microstructure. An oxide semiconductor thin film can be amorphous (e.g., having no structural order) or polycrystalline (e.g., having micro-scale to nano-scale crystal grains) Examples of oxide semiconductors for use in non-planar semiconductor layer105include metal oxides with a transition metal (e.g., IUPAC group 4-10) or post-transition metal (e.g., IUPAC groups 11-15). In some embodiments, the metal oxide includes at least one of Mg, Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo. The metal oxides may be suboxides (A2O), monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. Non-planar semiconductor layer105may be a p-type, n-type, or intrinsic material. In some embodiments, non-planar semiconductor layer105is n-type as a number of oxide semiconductors have been found to be capable of significant electron densities. Some oxide semiconductors have also been found to be capable of significant electron hole densities. Many oxide semiconductors have high defect density nearer the valence band but display good n-type electrical properties. Some oxide semiconductors have high defect density in the conduction band but display good p-type electrical properties. In some embodiments, non-planar semiconductor layer105is or includes a tin oxide (SnOx), such as Tin (IV) oxide, or SnO2. In other embodiments, the tin oxide is Tin (II) oxide (SnO) or a mixture of SnO and SnO2, where x may range between 1 and 2. In some embodiments, non-planar semiconductor layer105comprises a zinc oxide (ZnOx), such as Zn(II) oxide, or ZnO. In other embodiments, the zinc oxide is zinc dioxide (ZnO2) or a mixture of ZnO and ZnO2, where x may range between 1 and 2. In some other embodiments, non-planar semiconductor layer105comprises titanium oxide (TiOx), or SnOx. Exemplary oxide semiconductors that may have suitable p-type conductivity include copper oxide (CuOx). In some CuOxembodiments, non-planar semiconductor layer105is Cu(I) oxide, or Cu2O. In other embodiments, non-planar semiconductor layer105is Cu(II) oxide (CuO) or a mixture of CuO and Cu2O, where x may range between 0.5 and 1. Still other exemplary oxide semiconductor compositions include NiOx. Any dopants, such as Al, may also be added to any of these metal oxides, such as ZnO. Non-planar semiconductor layer105, or various portions thereof, may be intentionally doped, or not. Compared to intrinsic oxide semiconductors that are not intentionally doped, n-type and p-type oxide semiconductors may have a higher concentration of impurities, such as, but not limited to, one or more group III element, group V element, and/or elemental hydrogen (H), and/or oxygen vacancies. Dopant levels in non-planar semiconductor layer105may be selected to arrive at an optimal threshold voltage associated with gating the oxide semiconductor within the channel and/or for lowest bulk and/or junction resistance within the source/drain region. In embodiments where non-planar semiconductor layer105comprises ZnOx, the dopants may include In and Ga. In an embodiment, non-planar semiconductor layer105is InGaO3(ZnO)5(e.g., IGZO). Source109and drain110couple to non-planar semiconductor layer105and provide a contact to routing of metallization layers and other circuitry. Source209and drain210may be characterized as a source electrode and a drain electrode, respectively. Source109and drain110may include any suitable material or materials. In some embodiments, source109and drain110includes one or more of a titanium film and an aluminum film. Sidewall spacer106may include any suitable dielectric material. For example, sidewall spacer106may have any composition known to be suitable for electrical isolation, such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates, HSQ, MSQ, etc. Patterned layer104may include any suitable dielectric material. For example, patterned layer104may have any composition known to be suitable for electrical isolation, such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates, HSQ, MSQ, etc. High-k materials (e.g., metal oxides) such as those reference with respect to gate dielectric layers103,107may also be employed as sidewall spacer106and patterned layer104. In an embodiment, thin film transistor structure100is within a field oxide, polymeric sacrificial light absorbing materials, or the like as discussed further herein. As discussed, the architecture of thin film transistor structure100offers the advantages of a trench-type TFT (e.g., improved density with respect to planar TFT structures) and dual gate control (e.g., better short channel control, low contact resistance, and low parasitic gate to source/drain capacitance). In particular, thin film transistor structure100provides reduced capacitance from source/drain to gate due to sidewall spacer106. FIG.2Aillustrates a cross-sectional view of another example thin film transistor structure200andFIG.2Bis a top-down view of thin film transistor structure200, arranged in accordance with at least some implementations of the present disclosure. As shown,FIG.2Aprovides a cross-sectional view along an x-z plane andFIG.2Bprovides a top-down view along the A-plane inFIG.12A(e.g., along an x-y plane). As illustrated, the x-y plane may be in-plane, in-line, or the like with respect to a lateral direction of thin film transistor structure200and the z-direction may be perpendicular with respect to the lateral direction of thin film transistor structure200. As shown, thin film transistor structure200may include substrate101, gate electrode structure102, gate dielectric layer103, patterned layer104, non-planar semiconductor layer105, gate dielectric layer107, gate electrode structure108, a source209, and a drain210. Source209and drain210may be characterized as a source electrode and a drain electrode, respectively. Notably, thin film transistor structure200includes a dual gate architecture similar to that of thin film transistor structure100without sidewall spacer106and having source209and drain210with extended portions203,204respectively. Components of thin film transistor structure200having the same reference numerals may have any of the characteristics (e.g., orientations, materials, etc.) as those illustrated and discussed with respect to thin film transistor structure100. Such characteristics will not be repeated for the sake of brevity and clarity of presentation. Thin film transistor structure200includes a source209and a drain210. As shown, source209includes a portion203between portions122,126of non-planar semiconductor layer105and, similarly, drain210includes a portion204between portions123,127of non-planar semiconductor layer105. Furthermore, portion203of source209extends to contact portion121of non-planar semiconductor layer105and portion204of drain210extends to contact portion121of non-planar semiconductor layer105. Such an architecture provides for source209and drain210(e.g., source and drain metals) adjacent to the portions203,204of non-planar semiconductor layer105(e.g., along sidewalls of non-planar semiconductor layer105), which advantageously reduces contact resistance between source209and non-planar semiconductor layer105and between drain210and non-planar semiconductor layer105. As with source109and drain110, source209and drain210couple to non-planar semiconductor layer105and provide a contact to routing of metallization layers and other circuitry. Source209and drain210may include any suitable material or materials. In some embodiments, source109and drain110includes one or more of a titanium film and an aluminum film. FIG.3illustrates a flow diagram illustrating an example process300for fabricating thin film transistor structures, arranged in accordance with at least some implementations of the present disclosure. For example, process300may be implemented to fabricate thin film transistor structure100or any other thin film transistor structure discussed herein. In the illustrated implementation, process300may include one or more operations as illustrated by operations301-308. However, embodiments herein may include additional operations, certain operations being omitted, or operations being performed out of the order provided. In an embodiment, process300may fabricate thin film transistor structure1700as discussed further herein with respect toFIGS.4-17. Process300may begin at operation301, where a substrate may be received for processing. The substrate may include any suitable substrate such as a silicon wafer or the like. In some embodiments, the substrate includes underlying devices or electrical interconnects or the like. For example, the substrate may include peripheral circuitry, metallization layers, and interlayer dielectric materials as discussed with respect toFIG.23. Processing may continue at operation302, where a bulk gate electrode material, a bulk gate dielectric material, a bulk dielectric material, a thin film transistor semiconductor material, and a source/drain material may be disposed on the substrate. For example, each material may be disposed as a layer on the substrate and then each preceding layer. Such bulk material depositions may be performed using any suitable technique or techniques. The gate electrode material may include any characteristics discussed with respect to gate electrode structure102, the gate dielectric material may include any characteristics discussed with respect to gate dielectric layer103, the dielectric material may include any characteristics discussed with respect to patterned layer104, the thin film transistor semiconductor material may include any characteristics discussed with respect to non-planar semiconductor layer105, and the source/drain material may include any characteristics discussed with respect to gate dielectric layer107. In an embodiment, such bulk materials or material layers may be disposed over substrate101as discussed with respect toFIG.4. As discussed, at operations302, multiple layers are disposed. Such operations may be characterized as disposition or deposition operations, which may be performed separately or together. Processing may continue at operation303, where the material layers disposed at operation302are patterned and isolated. For example, the material layers may be patterned into mesas or the like and isolated for the formation of thin film transistor structures. The material layers may be patterned using any suitable technique or techniques such as lithography and etch techniques. Furthermore, the patterned material layers may be isolated using any suitable technique or techniques such as material deposition and planar techniques. The material used to isolate the patterned material layers (and ultimately the thin film transistor structures) may be any suitable material or material such as polymeric sacrificial light absorbing materials. In an embodiment, the material layers may be patterned and isolated as discussed with respect toFIGS.5,6A, and6B. Processing may continue at operation304, where a trench may be patterned into some the material layers. For example, the isolated material layers may be patterned to form a trench therein such that the trench extends through the source/drain material, the thin film transistor semiconductor material, and the dielectric material (which may be characterized as a patterned layer) but not through the gate dielectric material (nor the gate electrode material) such that the trench provides an opening to the gate dielectric material and has sidewalls including the source/drain material, the thin film transistor semiconductor material, and the dielectric material. The trench may be formed using any suitable technique or techniques such as lithography and etch techniques. In an embodiment, the material layers may be patterned to form a trench or opening as discussed with respect toFIGS.7A,7B,8, and9. Processing may continue at operation305, where a thin film transistor semiconductor material may be grown within the trench and a recess etch may be performed to provide a non-planar thin film transistor semiconductor material layer along sidewalls of the patterned layer (e.g., the patterned dielectric material) and the exposed surface of the gate dielectric material within the trench. The thin film transistor semiconductor material growth may be performed using any suitable technique or techniques such as lateral epitaxial overgrowth (LEO) techniques using the exposed portions of the thin film transistor semiconductor material within the trench as a seed material. Such LEO techniques may provide thin film transistor semiconductor material along sidewalls of the patterned layer and the exposed surface of the gate dielectric material within the trench but also along at least portions of the source/drain material. The thin film transistor semiconductor material on the source/drain material may optionally be removed using recess etch techniques such as providing a fill material such as an oxide and etching the fill material and the thin film transistor semiconductor material and subsequently selectively etching the fill material. In an embodiment, the thin film transistor semiconductor material growth and recess etch may be performed as discussed with respect toFIGS.10,11,12, and13. Processing may continue at operation306, where a conformal dielectric layer may be deposited and directionally etched to form a sidewall spacer along sidewalls of the source/drain materials and the thin film transistor semiconductor material within the trench while exposing a surface of the thin film transistor semiconductor material within the trench. The dielectric spacer layer may be deposited using any suitable technique or techniques such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). Furthermore, the directional etch may be performed using any suitable technique or techniques such as dry etch techniques. In an embodiment, sidewall spacers may be formed as discussed with respect toFIGS.14and15. Processing may continue at operation307, where a gate dielectric material may be conformally disposed over the exposed source and drain material, the sidewall spacer and the exposed thin film transistor semiconductor material within the trench and a gate electrode material may be disposed over the gate dielectric material. The gate dielectric material may be disposed using any suitable technique or techniques such as CVD, PECVD, PVD, electroplating, etc. In an embodiment, the gate dielectric material and the gate electrode material may be disposed over the source and drain material, the sidewall spacer and the thin film transistor semiconductor material as discussed with respect toFIG.16. Processing may continue at operation308, where portions of the gate dielectric material and the gate electrode material may be removed to form a TFT structure. For example, the TFT structure may have a discrete gate electrode structure having an exposed surface (e.g., for contact by a via or other metallization) such that the other surfaces of the gate electrode structure have a gate dielectric layer thereon. The portions of the gate dielectric material and the gate electrode material may be removed using any suitable technique or techniques such as planarization techniques. In an embodiment, the portions of the gate dielectric material and the gate electrode material may be removed as discussed with respect toFIGS.17A and17B. FIGS.4,5,6A,7A,8,9,10,11,12,13,14,15,16, and17Aillustrate cross-sectional side views of example thin film transistor structures as particular fabrication operations are performed, arranged in accordance with at least some implementations of the present disclosure.FIGS.6B,7B, and17Billustrate top-down views of the thin film transistor structures ofFIGS.6A,7A, and17A, respectively. As shown inFIG.4, thin film transistor (TFT) structure400includes substrate101, a gate electrode material layer402, a gate dielectric material layer403, a dielectric layer404, a semiconductor layer405, and a source and drain material layer406. Thin film transistor (TFT) structure400may be fabricated using any suitable technique or techniques. In an embodiment, substrate101is received for processing. Substrate101may include any materials, devices, and characteristics as discussed herein. In an embodiment, substrate101includes peripheral circuitry, metallization layers, and interlayer dielectric materials, etc. as discussed with respect toFIG.23. Gate electrode material layer402may be formed over or on substrate101using any suitable technique or techniques such as CVD, PECVD, PVD, electroplating, etc. Gate electrode material layer402may include any suitable materials and characteristics as discussed with respect to gate electrode structure102. Gate dielectric material layer403may then be formed over or on gate electrode material layer402using any suitable technique or techniques such as CVD, PECVD, PVD, etc. Gate dielectric material layer403may include any suitable materials and characteristics as discussed with respect to gate dielectric layer103. Subsequently, dielectric layer404may be formed over or on gate dielectric material layer403using any suitable technique or techniques such as CVD, PECVD, PVD, etc. Dielectric layer404may include any suitable materials and characteristics as discussed with respect to patterned layer104. Next, semiconductor layer405is formed over or on dielectric layer404using any suitable technique or techniques such as metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), CVD, PECVD, PVD, etc. In some embodiments, layer transfer techniques may be used to form semiconductor layer405of a monocrystalline material. Semiconductor layer405may include any materials and characteristics as discussed with respect to non-planar semiconductor layer105. Finally, source and drain material layer406(e.g., a metal layer) is formed over or on semiconductor layer405using any suitable technique or techniques such as CVD, PECVD, PVD, electroplating, etc. Source and drain material layer406may include any suitable materials and characteristics as discussed with respect to source109and drain110and/or source209and drain210. In an embodiment, the component layers are provided as bulk layers over an entirety (or substantially and entirety) of substrate101. FIG.5illustrates a TFT structure500similar to TFT structure400, after the formation of a patterned layer501on source and drain material layer406and subsequent patterning to form a gate electrode material layer502, a gate dielectric material layer503, a dielectric layer504, a semiconductor layer505, and a source and drain material layer506, which may be characterized as patterned layers or the like. Patterned layer501may be formed using any suitable technique or techniques such as photolithography techniques and gate electrode material layer402, gate dielectric material layer403, dielectric layer404, semiconductor layer405, and source and drain material layer406may be patterned to form gate electrode material layer502, gate dielectric material layer503, dielectric layer504, semiconductor layer505, and source and drain material layer506using any suitable technique or techniques such as etch techniques. FIGS.6A and6Billustrates a TFT structure600similar to TFT structure500, after the removal of patterned layer501via etch techniques or the like and after the formation of a field insulator layer601. Field insulator layer601may be or include any suitable electrically isolating dielectric material such as polymeric sacrificial light absorbing materials. Field insulator layer601may be formed using any suitable technique or techniques such as bulk deposition and planarization techniques. As shown inFIG.6B, which provides a top-down view along the A-plane inFIG.6A, field insulator layer601may surround gate electrode material layer502, gate dielectric material layer503, dielectric layer504, semiconductor layer505, and source and drain material layer506such that the surrounded material layers provide a field or location or the like for the formation of a TFT structure. In the illustrated embodiments, field insulator layer601surrounds each TFT structure. In other embodiments, multiple TFTs may be formed within an insulated region such that the multiple TFTs share non-planar semiconductor layer105. FIGS.7A and7Billustrates a TFT structure700similar to TFT structure600, after the formation of patterned layer701via lithography techniques or the like. As shown, patterned layer701includes an opening702that will define a trench or opening to be formed within source and drain material layer506, semiconductor layer505, and dielectric layer504and stopping at gate dielectric material layer503such that a top surface of gate dielectric material layer503defines a bottom of the trench or opening. As shown inFIG.7B, which provides a top-down view along the A-plane inFIG.7A, patterned layer701may be fully within source and drain material layer506(and the layers below) such that the subsequent trench is isolated within the discussed material layers. FIG.8illustrates a TFT structure800similar to TFT structure600, after the formation of a trench801. Trench801may be formed using any suitable technique or techniques such as selective etch techniques or the like. The formation of trench801further provides for patterned layer104, source109, and drain110as discussed herein. As shown, trench801includes a surface802(or portion) of gate dielectric layer103and sidewall(s)803, which includes a sidewall or sidewalls of patterned layer104, a patterned semiconductor layer805, and source109or drain110. Trench801may have any suitable shape from a top-down perspective such as square or rectangular (please seeFIG.7B). Although illustrated with orthogonal sidewalls(s)803, trench801may have sidewalls that have an obtuse angle (e.g., an angle in the range of >90° to 120°) with respect to the x-y plan, dished or slightly curved (concave) sidewalls, etc. Furthermore, each sidewall portion of patterned layer104, patterned semiconductor layer805, and source109or drain110may have differing characteristics due to differing material choices, etch conditions, etc.FIG.9illustrates a TFT structure900similar to TFT structure800, after the removal of patterned layer701via etch techniques or the like. FIG.10illustrates a TFT structure1000similar to TFT structure900, after the formation of a semiconductor layer structure1005. As shown, semiconductor layer structure1005includes patterned semiconductor layer805and a semiconductor layer portion1006with the separation indicated by hatched vertical lines. Semiconductor layer portion1006may be formed using any suitable technique or techniques such as lateral epitaxial overgrowth techniques. Semiconductor layer portion1006may include the same or different material as patterned semiconductor layer805. For example, semiconductor layer portion1006may include any materials and characteristics as discussed with respect to non-planar semiconductor layer105. As shown, semiconductor layer portion1006may begin growth at locations1009of patterned semiconductor layer805such that semiconductor layer portion1006may be integral with patterned semiconductor layer805. In some embodiments, semiconductor layer portion1006includes a monocrystalline material formed from monocrystalline material seed(s) at location1009. Furthermore, semiconductor layer portion1006may include a portion1008over a sidewall of source109, a portion1007over a sidewall of drain110, a portion1010integral to over sidewall(s) of patterned layer104, and a portion1011on surface128of gate dielectric layer103(please refer toFIGS.1A and2A). In some embodiments, portions1007,1008of semiconductor layer structure1005may be removed as discussed with respect toFIGS.11,12, and13. In other embodiments, portions1007,1008of semiconductor layer structure1005may remain adjacent to drain110and source109, respectively. In yet other embodiments, portions1007,1008may not be formed due to selective growth of semiconductor layer portion1006on surfaces other than the surfaces of source109and drain110. FIG.11illustrates a TFT structure1100similar to TFT structure1000, after the formation of fill material1101. Fill material1101may include any suitable material such as an oxide and may be formed using any suitable technique or techniques such as CVD, PECVD, PVD, etc.FIG.12illustrates a TFT structure1200similar to TFT structure1100, after a recess etch to remove portions of fill material1101and portions1007,1008(please refer toFIG.10) of semiconductor layer structure1005and to provide non-planar semiconductor layer105as discussed herein and a fill material1201. The recess etch may be performed using any suitable technique or techniques such as directional dry etch techniques.FIG.13illustrates a TFT structure1300similar to TFT structure1200, after the removal of fill material1201. Fill material1201may be removed using any suitable technique or techniques such as selective etch techniques. FIG.14illustrates a TFT structure1400similar to TFT structure1300, after the formation of a conformal dielectric layer1401. Conformal dielectric layer1401may include any material or materials discussed herein with respect to sidewall spacer106. Conformal dielectric layer1401may be formed using any suitable conformal deposition technique such as CVD, PECVD, PVD, etc. As shown, conformal dielectric layer1401is conformal to exposed surfaces of field insulator layer601, source109, drain110, and non-planar semiconductor layer105. In an embodiment, conformal dielectric layer1401may be used to dope non-planar semiconductor layer105to reduce resistance in non-planar semiconductor layer105. For example, a dopant may be provided in conformal dielectric layer1401and subsequently driven into non-planar semiconductor layer105via an anneal operation. FIG.15illustrates a TFT structure1500similar to TFT structure1400, after a directional etch of conformal dielectric layer1401to form sidewall spacer106. The directional etch may be performed using any suitable technique or techniques such as dry etch techniques. Sidewall spacer106is on a sidewall1501of source109, a sidewall1502of drain110, and a sidewall1503(or sidewalls) of non-planar semiconductor layer105. Furthermore, the directional etch exposes top surfaces of field insulator layer601, source109, and drain110, and a top surface1505of portion121of non-planar semiconductor layer105. For example, top surface1505may be exposed for the application of gate dielectric and gate electrode (e.g., a gate stack) while sidewall1503may be coated with sidewall spacer106to lower capacitance to the gate electrode. In an embodiment, sidewall spacer106may be used to dope sidewall portions of non-planar semiconductor layer105(e.g., those portions of non-planar semiconductor layer105in contact with sidewall spacer106) to reduce resistance of non-planar semiconductor layer105. For example, a dopant may be provided in conformal dielectric layer1401and, subsequent to performing the directional etch, such dopants may be driven from sidewall spacer106into non-planar semiconductor layer105via an anneal operation. FIG.16illustrates a TFT structure1600similar to TFT structure1500, after the formation of a gate dielectric layer1601and a gate electrode layer1602. Gate dielectric layer1601may include any materials and characteristics discussed herein with respect to gate dielectric layer107. Gate dielectric layer1601may be formed using any suitable technique or techniques such as CVD, PECVD, PVD, etc. As shown, gate dielectric layer1601may be formed conformally to exposed surfaces of field insulator layer601, source109, drain110, sidewall spacer106, and non-planar semiconductor layer105(e.g., the exposed surface of portion121of non-planar semiconductor layer105). Furthermore, gate electrode layer1602may be formed over gate dielectric layer1601using any suitable technique or techniques such as CVD, PECVD, PVD, etc. Gate electrode material layer1602may include any suitable materials and characteristics as discussed with respect to gate electrode structure108. As shown, gate electrode layer1602may fill a trench1604of gate dielectric layer1601as a fill and cover plateaus1603of gate dielectric layer1601extending laterally in the x-y plane. Furthermore, portion1604of gate electrode layer1602is within sidewall spacer106(e.g., between portions of sidewall spacer106), between source109and drain110, and within a trench of non-planar semiconductor layer105. FIGS.17A and17Billustrates a TFT structure1700similar to TFT structure1600, after the removal of portions of gate electrode layer1602and gate dielectric layer1601to form gate dielectric layer107and gate electrode structure108. The portions of gate electrode layer1602and gate dielectric layer1601may be removed using any suitable technique or techniques such as planarization techniques. For example, TFT structure1700substantially matches TFT structure100and illustrates TFT structure100within field insulator layer601. As shown inFIG.17B, which provides a top-down view along the A-plane inFIG.17A, gate electrode structure102, gate dielectric layer103, patterned layer104, non-planar semiconductor layer105, sidewall spacer106, gate dielectric layer107, gate electrode structure108, source109, and drain110may be isolated within field insulator layer601. In the illustrated embodiment, a single TFT is within an opening of field insulator layer601. In other embodiments multiple TFTs may be within an opening. For example, the multiple TFTs may share a common non-planar semiconductor layer105. FIG.18illustrates a flow diagram illustrating an example process1800for fabricating thin film transistor structures, arranged in accordance with at least some implementations of the present disclosure. For example, process1800may be implemented to fabricate thin film transistor structure200or any other thin film transistor structure discussed herein. In the illustrated implementation, process1800may include one or more operations as illustrated by operations301-305and1806-1808. However, embodiments herein may include additional operations, certain operations being omitted, or operations being performed out of the order provided. In an embodiment, process1800may fabricate thin film transistor structure2200as discussed further herein with respect toFIGS.4-13and19-22. Process1800may begin at operations301-305as discussed with respect toFIG.3herein. That is, process1800may include operations301-305. In an embodiment, operations301-305may be performed as illustrated with respect toFIGS.4,5,6A,6B,7A,7B,8,9,10,11,12, and13. Process1800may begin at operation1806, where a conformal source and drain material layer may be deposited and directionally etched to form a source and a drain that each extend along sidewalls of the thin film transistor semiconductor material within the trench while exposing a surface of the thin film transistor semiconductor material within the trench. The source and drain material layer may be deposited using any suitable technique or techniques such CVD, PECVD, PVD, electroplating etc. Furthermore, the directional etch may be performed using any suitable technique or techniques such as dry etch techniques. In an embodiment, extended source and drains may be formed as discussed with respect toFIGS.19and20. Processing may continue at operation1807, where a gate dielectric material may be conformally disposed over the exposed source and drain material and the exposed thin film transistor semiconductor material within the trench and a gate electrode material may be disposed over the gate dielectric material. The gate dielectric material may be disposed using any suitable technique or techniques such as CVD, PECVD, PVD, electroplating, etc. In an embodiment, the gate dielectric material and the gate electrode material may be disposed over the source and drain material, the sidewall spacer and the thin film transistor semiconductor material as discussed with respect toFIG.21. Processing may continue at operation1808, where portions of the gate dielectric material and the gate electrode material may be removed to form a TFT structure. For example, the TFT structure may have a discrete gate electrode structure having an exposed surface (e.g., for contact by a via or other metallization) such that the other surfaces of the gate electrode structure have a gate dielectric layer thereon. The portions of the gate dielectric material and the gate electrode material may be removed using any suitable technique or techniques such as planarization techniques. In an embodiment, the portions of the gate dielectric material and the gate electrode material may be removed as discussed with respect toFIGS.22A and22B. FIGS.19,20,21, and22Aillustrate cross-sectional side views of example thin film transistor structures as particular fabrication operations are performed, arranged in accordance with at least some implementations of the present disclosure.FIG.22Billustrates a top-down view of the thin film transistor structure ofFIG.22A. FIG.19illustrates a TFT structure1900similar to TFT structure1300, after the formation of a conformal source and drain material layer1901. Conformal source and drain material layer1901may include any material or materials discussed herein with respect to source109, drain110, source209, and drain210. Conformal dielectric layer1401may be formed using any suitable conformal deposition technique such as such as CVD, PECVD, PVD, electroplating, etc. As shown, conformal source and drain material layer1901is conformal to exposed surfaces of field insulator layer601, source109, drain110, and non-planar semiconductor layer105. In some embodiments, conformal source and drain material layer1901is the same material as source109and drain110and, in other embodiments, conformal source and drain material layer1901may have a different material. FIG.20illustrates a TFT structure2000similar to TFT structure1900, after a directional etch of source and drain material layer1901to form source209and drain210. The directional etch may be performed using any suitable technique or techniques such as dry etch techniques. For example, the directional etch may be a timed dry etch. Source209has a portion on a top surface2001of non-planar semiconductor layer105(as provided by source109) and a portion on sidewall2003of non-planar semiconductor layer105. Similarly, drain210has a portion on a top surface2002of non-planar semiconductor layer105(as provided by source109) and a portion on sidewall2004of non-planar semiconductor layer105. The portions on sidewalls2003,2004extend to contact portion121of non-planar semiconductor layer105. Furthermore, the directional etch exposes a top surface2005of portion121of non-planar semiconductor layer105. For example, top surface2005may be exposed for the application of gate dielectric and gate electrode (e.g., a gate stack) while sidewalls2003,2004may be coated with portions of source209and drain210, respectively. FIG.21illustrates a TFT structure2100similar to TFT structure2000, after the formation of a gate dielectric layer2101and a gate electrode layer2102. Gate dielectric layer2101may include any materials and characteristics discussed herein with respect to gate dielectric layer107. Gate dielectric layer2101may be formed using any suitable technique or techniques such as CVD, PECVD, PVD, etc. As shown, gate dielectric layer2101may be formed conformally to exposed surfaces of field insulator layer601, source109, drain110, sidewall spacer106, and non-planar semiconductor layer105(e.g., the exposed surface of portion121of non-planar semiconductor layer105). Furthermore, gate electrode layer2102may be formed over gate dielectric layer2101using any suitable technique or techniques such as CVD, PECVD, PVD, etc. Gate electrode material layer2102may include any suitable materials and characteristics as discussed with respect to gate electrode structure108. As shown, gate electrode layer2102may fill a trench2104of gate dielectric layer2101as a fill and cover plateaus2103of gate dielectric layer2101extending laterally in the x-y plane. Furthermore, portion2104of gate electrode layer2102is within sidewall spacer106(e.g., between portions of sidewall spacer106), between source109and drain110, and within a trench of non-planar semiconductor layer105. FIGS.22A and22Billustrates a TFT structure2200similar to TFT structure2100, after the removal of portions of gate electrode layer2102and gate dielectric layer2101to form gate dielectric layer107and gate electrode structure108. The portions of gate electrode layer2102and gate dielectric layer2101may be removed using any suitable technique or techniques such as planarization techniques. For example, TFT structure2200substantially matches TFT structure200and illustrates TFT structure200within field insulator layer601. As shown inFIG.22B, which provides a top-down view along the A-plane inFIG.22A, gate electrode structure102, gate dielectric layer103, patterned layer104, non-planar semiconductor layer105, sidewall spacer106, gate dielectric layer107, gate electrode structure108, source109, and drain110may be isolated within field insulator layer601. In the illustrated embodiment, a single TFT is within an opening of field insulator layer601. In other embodiments multiple TFTs may be within an opening. For example, the multiple TFTs may share a common non-planar semiconductor layer105. FIG.23illustrates a cross-sectional side view of a memory device structure2300, arranged in accordance with at least some implementations of the present disclosure. Memory device structure2300includes an exemplary implementation of a dual gate TFT structure. For example, memory device structure2300provides an implementation of an integrated circuit memory device employing a dual gate TFT structure. Although illustrated with respect to thin film transistor structures100, memory device structure2300may implement thin film transistor structure200, any other thin film transistor structure discussed herein, or combinations thereof. Such thin film transistor structures may be characterized as thin film transistors (TFTs). The cross-sectional view shown inFIG.1is along an A-A′ line that passes through capacitors coupled to one bitline of a memory array. Memory device structure2300further illustrates a portion of an IC that includes peripheral circuitry18over and/or on a substrate2350. Peripheral circuitry18includes a plurality of FETs181that employ a monocrystalline semiconductor for at least the channel semiconductor2321. Peripheral circuitry18may further include one or more levels of interconnect metallization2309embedded within interlayer dielectric (ILD) materials2303. ILDs2303may have any composition known to be suitable for electrical isolation of IC metallization, such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates, HSQ, MSQ, etc. In the exemplary embodiment illustrated, peripheral circuitry18includes metal-one (M1), metal-two (M2) and metal-three (M3) interconnect metallization levels. Thin film transistor structures100are located over peripheral circuitry18. As shown, one or more of thin film transistor structures100employ non-planar semiconductor layers105, dual gates102,108and other features discussed herein, which are not labeled for the sake of clarity of presentation. A memory cell2301is denoted by dot-dashed line. Individual ones of thin film transistor structures100are separated by field insulator layer601as discussed herein. Memory cell2301includes one storage capacitor of capacitor array20. Such storage capacitors or portions thereof may be characterized as capacitor structures. One capacitor terminal that includes metal2310is electrically (e.g., conductively) coupled to a semiconductor terminal (e.g., source) of an individual one of thin film transistor structures100. Individual ones of storage capacitor array20are similarly coupled to a terminal of corresponding individual ones of thin film transistor structures100. In the illustrative embodiment, each of the storage capacitors in array20has another terminal including a metal portion2311connected in parallel through another metal portion2313routed to a shared circuit node25. During memory device operation, circuit node25may be maintained at a reference voltage potential (e.g., ground). Individual ones of thin film transistor structures100have another semiconductor terminal (e.g., drain) electrically connected (e.g., conductively) to bitline metal60. At least one gate electrode structure of thin film transistor structure100is connected to a respective wordline10. For example, one or both of gate electrode structures102,108(please refer toFIGS.1A and2A) are coupled to a respective wordline10. Hence, memory cell2301and the illustrated adjacent memory cells are electrically coupled to one bitline metal60with their respective select thin film transistor structure100further coupled to separate wordlines10. Memory cell2301may be replicated over any given bitline length. Wordlines10may be connected to corresponding wordline drivers (or a similar voltage source) operable to bias the wordlines between a voltage sufficient to turn off a select transistor and a voltage sufficient to turn on a select transistor. For example, wordlines10may be coupled to a wordline driver operable to bias the wordline between a negative voltage (e.g., between 0V and −0.5V) sufficient to turn off an n-type transistor, and a positive voltage (e.g., between 0.5V and 2V) sufficient to turn on an n-type transistor. In some embodiments, bitline metal60comprises an interconnect metallization trace within a metallization level (e.g., M6) immediately above the metallization level (e.g., M5) in which thin film transistor structures100reside. Bitline60is illustrated in dashed line as an indication that bitline60is behind the plane of the cross-sectional view illustrated. Bitline60metallization trace is what might be visible if a portion of dielectric103flush with the plane of the cross-section was milled out (e.g., with a FIB during a deprocessing). As further shown, via148provides electrical connection between bitline60and semiconductor terminals (e.g., drains) of thin film transistor structures100. Source terminals of thin film transistor structures100are electrically connected through local interconnect metallization149. Local interconnect metallization149is within the same metallization level (e.g., M6) as bitline60. Local interconnect metallization149is adjacent to, but electrically insulated, from bitline60. As discussed, local interconnect metallization149electrically interconnects a first storage capacitor terminal including metal2310with a source of thin film transistor structure100. Capacitor metal portion2311is separated from capacitor metal2310by an intervening capacitor insulator2312. Capacitor insulator2312may have any suitable relative permittivity (e.g., high-k such as HfO2, doped high-k material such as Al or Zr doped HfO2, etc.). In an embodiment, capacitor metal portion2311is continuous with routing metal portion2313across at least all capacitors20associated with bitline60. Capacitor metal portion2311may also be continuous across capacitor array20associated multiple bitlines. Capacitor metal portion2311may therefore tie one side of all capacitors of a memory array to a common plate reference potential through circuit node25, implemented for example with another metallization level (e.g., M8). In some embodiments, an intervening metal shield2319separates laterally adjacent capacitors of capacitor array20. Any number of interconnect metallization levels may be employed to route circuit nodes of the memory array to the underlying peripheral circuitry. In an embodiment, the capacitor reference potential at circuit node25is routed down through five metallization levels (e.g., M8-M3) to be in electrical communication with one or more control circuit employing FETs181. Likewise, bitline60is routed down through three metallization levels (e.g., M6-M3) to be in electrical communication with one or more sense amplifier employing FETs181. Wordlines10may also be routed down through one or more metallization levels (e.g., M4-M3) to be in electrical communication with one or more wordline driver employing FETs181. As shown inFIG.23, FETs181include a gate terminal2320separated from channel semiconductor2321by a gate dielectric2302. Channel semiconductor2321separates semiconductor terminals2304(source semiconductor and drain semiconductor). Contact metallization2305lands on semiconductor terminals2304and is separated from gate terminal2320by an intervening dielectric spacer2307. Any materials and techniques known to be suitable for fabricating FETs may be employed for forming FETs181. FETs181may be planar or non-planar devices, for example. In some advantageous embodiments, FETS181are finFETs. One or more semiconductor materials may be employed in FETs181. As one example, FETs181employ a surface layer of a substantially monocrystalline substrate2350. Substrate2350may be any material known to be suitable for the fabrication of MOSFET (CMOS) circuitry, such as, but not limited to, group IV materials (e.g., silicon, germanium, and SiGe). FIG.24illustrates a mobile computing platform and a data server machine employing memory devices including dual gate trench shaped thin film transistors, arranged in accordance with at least some implementations of the present disclosure. For example, memory device2450of server machine2406may employ thin film transistor structure100, thin film transistor structure200, any other thin film transistor structure discussed herein, or combinations thereof. Server machine2406may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic or IC-eDRAM device including dual gate trench shaped thin film transistors. The mobile computing platform2405may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform2405may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system2410, and a battery2415. Disposed within the integrated system2410, a substrate2460includes an eDRAM2430and processor circuitry2440(e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). eDRAM2430includes 1C-1TFT cells, with each cell including a dual gate trench shaped TFT2431(e.g., thin film transistor structure100, thin film transistor structure200, any other thin film transistor structure discussed herein) and a capacitor2432as well as peripheral circuitry2420(e.g., peripheral circuitry18), for example as described elsewhere herein and, in particular, with respect toFIG.23. For monolithic embodiments, substrate2460is a semiconductor chip. For multi-chip module embodiments, substrate2460may be any package substrate, or an interposer. Processor circuitry2440, or a separate RFIC chip, may be further coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 2402.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. FIG.25is a functional block diagram of an electronic computing device2500, arranged in accordance with at least some implementations of the present disclosure. Electronic computing device2500may employ a dual gate trench shaped TFT as discussed herein. Computing device2500may be found inside platform2405or server machine2406, for example. Device2500further includes a motherboard2502hosting a number of components, such as, but not limited to, a processor2504(e.g., an applications processor), which may further incorporate interconnect structures (e.g., line segments with compositional variation) in accordance with embodiments described herein. Processor2504may be physically and/or electrically coupled to motherboard2502. In some examples, processor2504includes an integrated circuit die packaged within the processor2504. In general, the term “processor” or “microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory. In various examples, one or more communication chips2506may also be physically and/or electrically coupled to the motherboard2502. In further implementations, communication chips2506may be part of processor2504. Depending on its applications, computing device2500may include other components that may or may not be physically and electrically coupled to motherboard2502. These other components include, but are not limited to, volatile memory (e.g., MRAM2530, DRAM2532), non-volatile memory (e.g., ROM2535), flash memory, a graphics processor2522, a digital signal processor, a crypto processor, a chipset2512, an antenna2525, touchscreen display2515, touchscreen controller2575, battery2510, audio codec, video codec, power amplifier2521, global positioning system (GPS) device2540, compass2545, accelerometer, gyroscope, audio speaker2520, camera2541, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. Communication chips2506may enable wireless communications for the transfer of data to and from the computing device2500. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips2506may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device2500may include a plurality of communication chips2506. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. As used in any implementation described herein, the term “module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein. The software may be embodied as a software package, code and/or instruction set or instructions, and “hardware”, as used in any implementation described herein, may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), and so forth. While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure. It will be recognized that the invention is not limited to the embodiments so described but can be practiced with modification and alteration without departing from the scope of the appended claims. For example, the above embodiments may include specific combination of features. However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. | 78,385 |
11862729 | DETAILED DESCRIPTION One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents. In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. Vertical thin film transistor (TFTs) structures are described herein. The vertical TFTS include a gate electrode clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C). FIG.1Aillustrates a top-down plan view of a vertical thin film transistor structure101, in accordance with some embodiments.FIG.1Billustrates a cross-sectional view of the vertical thin film transistor structure101along the A-A′ shown inFIG.1A, in accordance with some further embodiments. Vertical gate thin film transistor structure101has a gate electrode110. Gate dielectric115surrounds at least a portion of the sidewall of gate electrode110. A semiconductor layer120surrounds at least a portion of gate dielectric115. Source and drain contact metallization150makes contact with two separate portions of semiconductor layer120, and a field dielectric material180physically and electrically separates contact metallization150. As such, during transistor operation, a gate bias (e.g., 0.5-2.0V) applied to gate electrode110may induce a conductive channel within semiconductor layer120. Majority charge carriers (e.g., electrons) may transit any portion of the channel coupling together the source and drain contact metallization150. When in an “on” state, current may flow through one or more portions of semiconductor layer120, wherever there is sufficient field. In the example shown inFIG.1A, highest current density is found in a first channel131, and a second channel132, which are located on the opposite short ends of gate electrode110. As further shown inFIG.1B, with the vertical orientation, transistor channel width may be proportional to the vertical height (e.g., z-dimension) of the gate electrode and the overlap of the gate electrode with the contact metallization150(e.g., H1). As described further below, channel width may also be proportional to the number of gate electrodes located between source and drain contact metallization150. As the channel width is not dependent on a planar dimension, vertical thin film transistor structure101is more scalable and, as a result well-suited to applications such as an access (select) transistor in memory devices. As shown inFIGS.1A and1B, vertical thin film transistor structure101is located over a substrate105. Substrate105may be any substrate known to be suitable for hosting a thin film transistor, such as, but not limited to, monocrystalline substrates (e.g., silicon, germanium, SiGe, SiC, sapphire), glass substrates (e.g., silica, alumina), or organics (e.g., polyimide, SU-8). In some exemplary embodiments, substrate105includes integrated circuitry, such as, but not limited to, MOSFET (e.g., CMOS) integrated circuitry including a plurality of FETs fabricated in a monocrystalline semiconductor material and one or more levels of conductive interconnect structures (e.g., metallization) embedded in one or more interlevel dielectric (ILD) layers. Gate electrode110is located over an underlying layer of substrate105, for example over an underlying ILD layer. In some embodiments, as described further below, gate electrode110may make contact with an underlying metallization level embedded within the underlying ILD layer. Gate electrode110may have any composition known to be suitable for controlling the channel conductivity of a thin film transistor. Gate electrode110may have any suitable work function and may include a doped semiconductor (e.g., polysilicon), or an elemental metal layer, a metal alloy layer, and/or laminate structure. In some embodiments, the gate electrode110comprises a metal nitride, such as TiN. A gate electrode may also comprise Al (e.g., TiAlN). Other alloy constituents may also be employed, such as, but not limited to, C, Ta, W, Pt, and Sn. One or more dielectric cap layers may be present over a top surface of gate electrode110. A dielectric cap185is shown inFIG.1B. Gate electrode110may have any feature dimensions. As shown inFIG.1A, gate electrode110has a longitudinal length L1and a transverse width L2. In the example illustrated, channel length of transistor structure101is primarily a function of transverse width L2. In some embodiments, transverse width L2is less than 20 nm, and advantageous less than 15 nm. Longitudinal length L1may, in some embodiments, be larger than L2, for example where gate electrode110is patterned as a 2D grating pattern. Gate dielectric115surrounds gate electrode110, forming a cladding around at least a sidewall of gate electrode110. As shown inFIGS.1A and1B, gate dielectric115is absent from the top surface of gate electrode110. However, in some alternative embodiments, gate dielectric115may cover the top surface of gate electrode110. As visible inFIG.1B, gate dielectric115extends over the underlying surface of substrate105and is not confined to sidewalls of gate electrode110. While any gate dielectric materials known to be suitable for gate electrode110and semiconductor layer120may be utilized, in some exemplary embodiments gate dielectric115includes at least one layer of a high-k dielectric material (e.g., having a bulk relative permittivity greater than 9). Exemplary high-k materials include electrically resistive metal oxides, such as, but not limited to, Al2O3, HfO2, and HfAlOx. Semiconductor layer120surrounds gate dielectric115, forming another cladding layer around at least a sidewall of gate electrode110. As shown inFIGS.1A and1B, semiconductor layer120is absent from the top surface of gate electrode110. However, in some alternative embodiments, semiconductor layer120(and gate dielectric115) may cover the top surface of gate electrode110. As shown inFIG.1B, semiconductor layer120is also absent from some regions of the underlying surface so as to be localized to transistor structure101and electrically insulated from any adjacent structures (e.g., other transistors). In some embodiments therefore, semiconductor layer120is present only around the sidewall of gate electrode110(separated by gate dielectric115). In the example shown inFIG.1B, semiconductor layer120has a foot199, which is indicative of the process employed to remove semiconductor layer120. As described further below in the context of transistor fabrication, foot199may extend a few nanometers from the sidewall of gate electrode110as a result of masking by a dielectric spacer160. Dielectric spacer160may have any composition (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC(H)). In some advantageous embodiments, dielectric spacer160has a different composition than dielectric cap185, enabling dielectric spacer160to be etched selectively over dielectric cap185. In some embodiments, dielectric spacer160is a material capable of passivating surfaces of semiconductor layer120. As such, the composition of dielectric spacer160may depend upon the composition of semiconductor layer120. For some exemplary embodiments where semiconductor layer120is an amorphous or polycrystalline oxide semiconductor, dielectric spacer160is an insulative (non-semiconducting) metal oxide. In some such embodiments, dielectric spacer160includes at least one of Al (e.g., AlOx), Ti (e.g., TiOx) or Hf (e.g., HfOx) and may be a suboxide (A2O), monoxide (AO), binary oxide (AO2), ternary oxide (ABO3), or mixture thereof. While transistor structure101may employ any thin film semiconductor material as semiconductor layer120, including traditional group IV semiconductor materials such as silicon (Si), germanium (Ge), and SiGe alloys, TFT performance depends on the composition of the semiconductor employed as the transistor channel material. This may be particularly important where transistor structure101is highly scaled (e.g., L2of 10-15 nm) as some thin film semiconductor materials will suffer exceedingly high leakage current at such dimensions. In some exemplary embodiments, semiconductor layer120is an oxide semiconductor. An oxide semiconductor is a semiconducting oxide, or a semiconductor comprising oxygen. For such embodiments, the wide band gap of oxide semiconductors has the advantage of low leakage. In such materials the minority carrier population is vanishingly small compared to that of materials such as silicon and germanium, making the vertical transistor structure101essentially an exclusively majority carrier device. With virtually no minority carriers, majority-minority carrier recombination is low and off-state leakage current potentially significant. In addition to the low-leakage of oxide semiconductor materials enabling dimensional scaling of transistor structure101, oxide semiconductor materials may enable higher memory cell retention rates at higher memory density. Semiconducting properties vary with the oxide semiconductor composition and microstructure of semiconductor layer120. Semiconductor layer120may be amorphous (i.e., having no structural order), or polycrystalline (e.g., having micro-scale to nano-scale crystal grains). Exemplary oxide semiconductors include metal oxides with a transition metal (e.g., IUPAC group 4-10) or post-transition metal (e.g., IUPAC groups 11-15). In advantageous embodiments, the metal oxide includes at least one of Mg, Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo. The metal oxides may be suboxides (A2O), monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. Semiconductor layer120may be a p-type, n-type, or intrinsic material. In exemplary embodiments, semiconductor layer120is n-type as a number of oxide semiconductors have been found to be capable of significant electron densities. Some oxide semiconductors have also been found to be capable of significant electron hole densities. Many oxide semiconductors have high defect density nearer the valence band, but display good n-type electrical properties. Some oxide semiconductors have high defect density in the conduction band, but display good p-type electrical properties. In some embodiments, semiconductor layer120comprises a tin oxide (SnOx), such as Tin (IV) oxide, or SnO2. In other embodiments, the tin oxide is Tin (II) oxide (SnO) or a mixture of SnO and SnO2, where x may range between 1 and 2. While the range of x may be expanded, semiconducting properties may be lost (e.g., the material becomes a pure conductor if x is to low, and a pure insulator if x is too high). In some other embodiments, semiconductor layer120comprises a zinc oxide (ZnOx), such as Zn(II) oxide, or ZnO. In other embodiments, the zinc oxide is zinc dioxide (ZnO2) or a mixture of ZnO and ZnO2, where x may range between 1 and 2. In some embodiments where semiconductor layer120comprises ZnOx, the dopants may include In and Ga. In some specific examples, semiconductor layer302is InGaO3(ZnO)5, often referred to simply as IGZO. In some other embodiments, semiconductor layer120comprises titanium oxide (TiOx), or SnOx. Exemplary oxide semiconductors that may have suitable p-type conductivity include copper oxide (CuOx). In some CuOxembodiments, semiconductor layer120is Cu(I) oxide, or Cu2O. In other embodiments, semiconductor layer120is Cu(II) oxide (CuO) or a mixture of CuO and Cu2O, where x may range between 0.5 and 1. Still other exemplary oxide semiconductor compositions include NiOx. Although not bound by theory, the basis for semi-conductivity in many oxide semiconductors may be the presence of oxygen vacancies. The presence of other electrically active dopants, such as hydrogen, or one or more metal species, may also serve as a means of tuning the semiconducting properties of the oxide semiconductor. Semiconductor layer120or various portions thereof (e.g., regions contacted by contact metallization150) may be intentionally doped (e.g., through one or more surface treatments). Compared to intrinsic oxide semiconductor that is not intentionally doped, n-type and p-type oxide semiconductors may have a higher concentration of impurities, such as, but not limited to, one or more group III element, group V element, and/or elemental hydrogen (H), and/or oxygen vacancies. Dopant levels in semiconductor layer120may also be selected to arrive at an optimal threshold voltage associated with gating the semiconductor within the channel and/or for lowest bulk and/or junction resistance within the semiconductor source and/or drain junction with contact metallization150. As shown inFIGS.1A and1B, contact metallization150is located within trenches exposing semiconductor layer120along portions of the cladded sidewall of gate electrode110. As for semiconductor layer120, contact metallization150is absent from a top surface of gate electrode110. In the embodiment shown inFIG.1A, contact metallization150is also absent from a top surface of semiconductor layer120, and therefore only makes contact to semiconductor layer120along a sidewall of gate electrode110, as further shown inFIG.1B. As shown, contact metallization150fills a trench of lateral width W1that is at least equal to the thickness of the dielectric spacer160(as measured normal from the sidewall of gate electrode110). In the exemplary embodiment, contact metallization150fills a trench of lateral width W1that is substantially equal to the thickness of the dielectric spacer160and a dielectric liner165. Dielectric liner165may have any composition (e.g., SiO, SiN, SiON, SiCO(H), etc.). In some advantageous embodiments, dielectric liner165has the same composition as dielectric spacer160, facilitating the contact trench etch and/or improving surface passivation of semiconductor layer120. Unlike semiconductor layer120, contact metallization150is discontinuous about the perimeter or periphery of the cladded gate electrode. Rather than a continuous cladding, which would prevent contact metallization150from sustaining a voltage differential across semiconductor layer120, contact metallization150is spaced apart either by portions of semiconductor layer120or dielectric spacer160, and/or165, and/or180. A first contact metallization150may be associated with a first of a source and drain of transistor structure101, while a second contact metallization150may be associated with a second of a source and drain of transistor structure101. Contact metallization150may have any composition known to provide a suitable contact to semiconductor layer120. Contact metallization150may form a schottky or ohmic junction with an interface of semiconductor layer120. Contact metallization150may include, for example, one or more metals or metallic compounds. In some embodiments, contact metallization150includes a metal nitride at the interface of (i.e., in direct contact with) semiconductor layer120. Metal nitrides may offer good stability and do not readily oxidize. Exemplary metal nitrides include TiN, TaN, and WN. In other exemplary embodiments, contact metallization150includes a noble metal (e.g., Pt) at the interface of (i.e., in direct contact with) semiconductor layer120. Isolation dielectric of structure101may include one or more conformal or non-conformal dielectric material layers surrounding semiconductor layer120and contact metallization150. Any dielectric material known to be suitable for electrically insulating adjacent transistors of an IC may be employed as isolation dielectric. In the example shown inFIG.1B, the isolation dielectric includes a dielectric spacer160, a dielectric liner165(both of which are conformal dielectric layers) and field dielectric180(which is non-conformal). In some advantageous embodiments, field dielectric180has a different composition than dielectric spacer160and/or dielectric liner165, facilitating formation of a trench to contain the contact metallization by an etch process that is selective to the spacer and/or liner dielectric over field dielectric180. Field dielectric180is advantageously a material that is flowable or can otherwise planarize structure101with surrounding features. In some embodiments, field dielectric180includes one or more layer of one or more of SiO, SiN, SiON, SiOC(H), polyimide, HSQ, or MSQ. WhileFIGS.1A and1Billustrate an exemplary alignment of contact metallization150to the cladded gate electrode110, the relative alignment and dimensions of structural elements introduced inFIGS.1A and1Bmay deviate without departing from the scope of the present embodiments. For example,FIG.2illustrates a top-down plan view of a vertical thin film transistor structure201, in accordance with some alternative embodiments where the longitudinal lengths of contact metallization150are significantly shorter than shown inFIG.1A. For structure201, contact metallization150have a longitudinal length L3that is significantly less than L1of gate electrode110. As such, the effective lengths of channels131,132are greater than L2, but remain of approximately of equal length. While structure201is a possible variation of the structure101, alternatives where contact metallization150have longitudinal lengths at least equal to that of gate electrode110(e.g., as shown inFIG.1A), or greater than that of gate electrode110(e.g., dashed lines151inFIG.1B), may be more tolerant of potential misalignment of contact metallization (e.g., in the y-dimension). As described further below, contact metallization150can be fabricated in an at least partially self-aligned manner so that variation in the transverse width L2is minimal. As noted above, transistor structures101and201have two channels131,132and may therefore be classified as dual-gate or, more generally, multi-gate transistors. The number of channels may be further increased by increasing the number of gate electrodes spanning the longitudinal length of the contact metallization (e.g., the number of gate electrodes within the length L3).FIG.3illustrates a top-down plan view of a vertical quad-gate thin film transistor structure301, in accordance with some embodiments. Vertical thin film transistor structure301includes a first gate electrode110A laterally spaced apart from a second gate electrode110B. Each of gate electrodes110A and110B may be separate pillars extending from an underlying surface of substrate105. Gate electrodes110A and110B may each have any of the properties described above for gate electrode110. A gate dielectric115A and115B clads at least a sidewall of gate electrode110A and110B, respectively. Gate dielectrics115A,115B may have any of the properties described above in the context of gate dielectric115. At least a sidewall of these dielectric-clad gate electrodes are further surrounded by semiconductor layer120, which may have any of the properties described above. Contact metallization150contacts two separate, discrete regions of semiconductor layer120. As shown, contact metallization150have a longitudinal length L3that exceeds the longitudinal length L4of each gate electrode110A,110B. Contact longitudinal length L3is at least equal to the total longitudinal length of both gate electrodes110A and110B (e.g., twice L4), and as shown, may be equal to (or greater than) the total length of gate electrodes110A,110B added to the spacing between gate electrodes110A,110B (e.g., L1). In the exemplary embodiment shown, the spacing between gate electrodes110A and110B is completely occupied by semiconductor layer120. With sufficient spacing between gate electrodes110A,110B, two distinct semiconductor layers120may be present, and dielectric material may even intervene within the space between gate electrodes110A,110B. Regardless, two additional channels134and135will be operable upon appropriate biasing of gate electrodes110A,110B. Current may be therefore conducted between source and drain contact metallization150by way of the four transistor channels131,132,134, and135. Each of these channels may have substantially the same channel length, which is a function of transverse width L2. Each of these channels may have substantially the same channel width, which is a function of the overlap in the z-dimension between the gate electrodes110A,110B and semiconductor layer(s)120. FIG.4illustrates a top-down plan view of memory device401including a vertical thin film transistor array, in accordance with some embodiments. As shown, memory device401includes a plurality of memory cells, each cell including a vertical thin film transistor structure101and a charge storage capacitor189. Vertical transistor structures101may be arranged in a 2D array, as shown, or in an alternative layout. In some embodiments, vertical transistor structures101are configured as select or access transistors in 1TFT-1C cells of a DRAM. Transistor structures101may be networked with storage capacitors189by conductive traces including wordlines190and bitlines191. Wordlines190may be electrically connected to transistor structures101through a bottom surface of gate electrodes110. Wordlines190may be further electrically connected to row circuitry, such as wordline drivers192. Bitlines191may be electrically coupled to a first (e.g., drain) contact metallization150. Bitlines191may be further electrically connected to column circuitry, such as sense amplifiers193. A second (e.g., source) contact metallization150may be coupled to a terminal of a capacitor189. Transistor structure101may then be operable as a select transistor where wordline drivers192are operable to bias wordlines190between a voltage sufficient to turn off a select transistor and a voltage sufficient to turn on the select transistor. For example, wordlines190may be coupled to a wordline driver192operable to bias the wordline190between a negative voltage (e.g., between 0V and −0.5V) sufficient to turn off an n-type transistor, and a positive voltage (e.g., between 0.5V and 2V) sufficient to turn on an n-type transistor. In some embodiments, memory device401is fabricated in the BEOL interconnect levels of an IC chip. Hence, all of capacitors20, bitlines191, wordlines190, and select transistor structures101are fabricated within, and/or between, various interconnect metallization levels. In further embodiments, peripheral memory circuitry including at least one of column circuitry and row circuitry, is fabricated in a device level that falls within at least some of the footprint of memory device401. For example, bitlines191may be electrically coupled to a sense amplifier193that employs MOSFETs fabricated in a region of a monocrystalline semiconductor device layer (e.g., silicon substrate) that is at least partially underlying memory array100. In further embodiments, wordlines190are electrically coupled to wordline drivers192that employ MOSFETs fabricated in a region of a monocrystalline semiconductor device layer of substrate105that is at least partially underlying the 2D array of transistor structures101. Memory device401may have any storage capacity (i.e., any number of bit cells) and one or more memory device401may be fabricated on a single IC chip. In some embodiments, for example, memory device401includes between 256 and 1024 wordlines and between 1024 and 4096 bitlines. A memory device architecture employing TFTs in the memory array enables vertical integration of the peripheral circuitry. A gain in memory density is then possible where the TFT array has sufficient density. With certain structural features of a vertical TFT and a memory device employing such vertical TFTs described above, the fabrication of such features is further described below. Self-aligned etch processes and/or damascene techniques, which are all highly scalable, may be enlisted to fabricate many vertical thin film transistor structures.FIG.5is a flow diagram illustrating methods501for fabricating an IC device including vertical thin film transistors, in accordance with some embodiments. Methods501begin at operation205where a substrate is received. The substrate advantageously includes a monocrystalline semiconductor layer, such as a silicon layer, upon which FETs may be formed. The FETs may be fabricated using any known technique and interconnected with BEOL metallization levels to form FET circuitry, such a peripheral circuitry of a memory device (e.g., DRAM). In some examples, both n-type and p-type FETs are fabricated upstream of methods501and interconnected into a CMOS peripheral circuit. Methods501continue at operation510where gate features are fabricated, for example within BEOL metallization levels over FET circuitry. Any subtractive or additive fabrication techniques may be employed to fabricate gate features of any shape, such as, but not limited to lines, pillars, or polygonal mesas. Upon completion of operation510, the gate features include a gate electrode covered with a gate dielectric. At operation515, a spacer of semiconductor material is formed around a sidewall of the gate features. Any subtractive or additive fabrication techniques may be employed to fabricate the semiconductor spacer around the gate feature sidewall. In some embodiments, a non-selective semiconductor deposition process is employed at operation515to form a continuous semiconductor layer. A selective etch process may then be employed to remove the semiconductor layer from regions other than the sidewalls of the gate electrode features. The selective etch process may be maskless, for example relying on anisotropy of the etch to impart selectively between portions of the semiconductor layer on a sidewall of the feature and portions that are not on the sidewall. Alternatively, a mask may be employed to protect the portion of the semiconductor layer on the sidewall of the gate features. Upon the completion of operation510, a cladding of semiconductor material is present on a sidewall of the gate feature(s). Methods501continue at operation520where one or more isolation dielectric is deposited around the semiconductor cladded gate features. One or more layers of dielectric may be deposited by a conformal process, such as, but not limited to, chemical vapor deposition (CVD), or atomic layer deposition (ALD), for example. One or more layers of dielectric may be deposited by a non-conformal process, such as, but not limited to, spin-on techniques, and/or flowable CVD techniques, for example. Upon the completion of operation520, semiconductor clad gate features are embedded in isolation dielectric. Methods501continue at operation525where source and drain contact openings are formed. In some embodiments, at least two separate trenches are formed at operation525, for example by etching into one or more of the isolation dielectric material layers. A mask may be employed at operation525to protect portions of the isolation dielectric that are not to be etched. The mask may have one or two openings aligned to the semiconductor clad gate features that define where the trenches are to be located relative to the gate features. Any dielectric etch process, such as an anisotropic dry (plasma) etch may be employed to etch into the isolation dielectric trenches of a predetermined target depth. The trenches formed may advantageously expose separate portions (e.g., two sidewall surfaces) of the semiconductor layer. Methods501continue at operation530where contact metallization is formed. In some embodiments, the contact openings formed at operation525are backfilled with any suitable metal using any damascene techniques known. Methods501complete at operation535where terminals of the TFTs are interconnected into circuitry with one or more BEOL metallization levels using any known techniques. FIG.6is a flow diagram illustrating methods601for fabricating vertical thin film transistor, in accordance with some embodiments of the methods501.FIG.7-17illustrate cross-sectional views of multi-gate thin film transistors of the memory device401(FIG.4) taken along the dashed A-A′ line.FIG.7-17further illustrate certain structural features evolving as operations in the methods601are performed, in accordance with some further embodiments. Methods601begin at operation505where the substrate is received. The substrate may, for example, include peripheral circuitry of a memory device. The substrate received at operation505may have been processed upstream of methods601, for example to fabricate FETs and one or more levels of BEOL interconnect metallization over the FETs. In the example further illustrated inFIG.7, metallization (e.g., wordlines)190are embedded an ILD layer182(e.g., SiO2or a low-k material). Returning toFIG.6, methods601continue at operation610, where a sacrificial material is deposited over the substrate and patterned. The patterned features are then backfilled with gate electrode material at operation615, for example using any known damascene techniques. In the example further illustrated inFIG.8, a sacrificial material layer510(e.g., SiO2) has been deposited over ILD layer182and metallization190. Other sacrificial materials, such as polysilicon, may be employed in a similar fashion. Openings805are etched into sacrificial layer510, for example with an anisotropic etch process. Openings805expose a portion of metallization190. As further shown inFIG.9, gate electrode material110is deposited into openings805. Any overburden may be removed from the top surface of sacrificial material layer810, for example with a chemical-mechanical polish (CMP). Returning toFIG.6, methods601continue at operation620where a dielectric cap is formed over the gate electrode material. Such a cap may be deposited as a top layer of a gate electrode stack where the gate electrode is formed with a subtractive process. In the example shown inFIG.9, a top surface of gate electrode material110is first recessed relative to a top surface of sacrificial material layer810, for example with a selective etch process. A dielectric material layer is then deposited and planarized with the top surface of sacrificial layer810to arrive at the dielectric cap185as shown inFIG.10. Returning toFIG.6, methods601continue at operation625where the sacrificial material is removed to expose sidewalls of the gate electrode material. Once exposed, gate dielectric is deposited over the gate electrode at operation630. A semiconductor layer is then deposited over the insulated gate at operation635. In the example shown inFIG.11, sacrificial material layer810has been removed with an etch process selective over dielectric cap185, gate electrode material110, and metallization190. InFIG.12, gate dielectric115has been deposited over the dielectric cap185, over a sidewall of gate electrode material110, over metallization190, and over ILD layer182. Semiconductor layer120has been further deposited over gate dielectric115. Deposition of semiconductor layer120may entail any deposition process known to be suitable for the semiconductor composition and microstructure desired. For example, any of physical vapor deposition (PVD), chemical vapor deposition (CVD), e-beam deposition (EBD), or pulsed laser deposition (PLD) may be employed to deposit a thin film of semiconductor. In some embodiments where a layer of oxide semiconductor is deposited, any of the materials described above may be deposited as a blanket layer over the substrate. Returning toFIG.6, methods601continue at operation640where a spacer dielectric layer is deposited over the semiconductor layer and anisotropically etched into a self-aligned dielectric spacer. While any dielectric material and etch process known may be employed, in some embodiments the spacer dielectric material is of a composition that provides good surface passivation of the underlying semiconductor layer. Good passivation of the semiconductor layer surface can advantageously reduce transistor leakage current (e.g., source-to-drain leakage). For some embodiments where the semiconductor layer deposited at operation635is an oxide semiconductor, an insulative metal oxide, such as any of those introduced above, is deposited at operation640. In some embodiments, the spacer dielectric layer is deposited with a conformal deposition process (e.g., CVD or ALD). In the example further illustrated inFIG.13, a spacer dielectric layer1310is deposited over semiconductor layer120.FIG.14further illustrates dielectric spacer160following a maskless anisotropic “spacer” etch of dielectric layer1310. As shown, dielectric spacer160remains only adjacent to sidewalls of topographic features, thereby protecting a portion of semiconductor layer120located over a sidewall of the dielectric insulated gate electrode. Returning toFIG.6, methods601continue at operation645where the semiconductor layer is etched through to localize the semiconductor to a finite region surrounding the gate electrode. In some embodiments, the semiconductor layer may be anisotropically etched. If such an etch is performed without a mask, a self-aligned spacer of semiconductor material may be formed around the topography of the gate electrode. In some other embodiments, the semiconductor layer may be isotropically etched and a mask employed to protect the semiconductor material around the gate electrode. In the example illustrated inFIG.15, portions of semiconductor layer120unprotected by dielectric spacer160are removed (e.g., by anisotropic and/or isotropic etch). Notably, no lithographic patterning is required and this self-aligned patterning offers the advantage of scalability. Etching through semiconductor layer120electrically isolates one semiconductor layer120over a first gate electrode from another semiconductor layer120over a second, adjacent, gate electrode. Returning toFIG.6, methods601continue at operation650where a liner dielectric is deposited over the semiconductor clad and insulated gate electrode features. Such a liner dielectric may advantageously passivate portions of semiconductor layer120left exposed after the semiconductor etch process of operation645. The composition of the liner dielectric may therefore advantageously have the same composition as the spacer dielectric formed at operation640. In some advantageous embodiments, the liner dielectric is deposited with a conformal deposition process (e.g., CVD or ALD). The same deposition process employed at operation640may be employed at operation650, for example. Following the liner deposition, a field dielectric is deposited to backfill regions between topographic features with an insulative material. The field dielectric may be deposited with any non-conformal process (e.g., spin-on or other flowable oxide deposition techniques). In some advantageous embodiments, the field dielectric deposited has a different composition than the liner dielectric. A flowable oxide material may be deposited, for example. As further shown in the example ofFIG.16, a dielectric liner165has been conformally deposited and field dielectric180has been non-conformally deposited, substantially backfilling a portion of the space between two adjacent gate electrodes110. The pitch of gate electrodes110is therefore sufficient to ensure a space between adjacent gate electrodes110is large enough for there to be field dielectric180separating the conformal dielectric liner165over each gate electrode110. A planarization (e.g., CMP) process may then remove field dielectric overburden and expose top surfaces of dielectric liner165, and/or gate dielectric115, and/or dielectric cap185. In the example shown inFIG.17, the dielectric is recessed or etched back until dielectric cap185is exposed. One or more selective or non-selective planarization or recess etch processes may be employed to stop upon dielectric cap185and any processes known to be suitable for the chosen material compositions may be employed. Returning toFIG.6, methods601continue at operation660where source and drain contact openings are patterned into one or more of the dielectric material layers surrounding the semiconductor clad insulated gate electrodes. In some embodiments, a lithographic patterning process is performed to define a stripe or other polygonal opening in a masking layer formed over the gate electrode structures. The mask opening may expose only a portion of the surrounding dielectric material. Two discontinuous portions of the dielectric material surrounding any given gate electrode structure may be exposed by a single mask opening as a result of the mask opening's intersection with the semiconductor clad gate electrodes.FIG.18is a top-down plan view of vertical thin film transistor memory device401, in accordance with some embodiments. As shown, a lithographically-defined mask includes mask stripes1515that cross over one or more transistor structures. Each mask stripe1515has an edge that crosses over or overlaps semiconductor layer120, thereby protecting ends of dielectric surrounding each transistor structure. Returning toFIG.6, methods601continue at operation665where the exposed portions of dielectric are recess etched to form trenches that expose a sidewall of the semiconductor layer. In some embodiments, the recess etch is selective to one or more of the dielectric materials exposed within the mask openings. Such an etch process is therefore at least partially self-aligned. The contact etch may be terminated at any time with the depth of the trench determining how much of the semiconductor layer is exposed. The trench depth defines how much overlap there will be between the source/drain contacts and the gate electrode, thereby impacting the effective channel width of the transistor. In some embodiments, the contact etch is landed on a dielectric layer.FIG.19Aillustrates a cross-sectional view of multi-gate thin film transistor memory device401along the A-A′ line shown inFIG.18following an etch process that selectively recesses dielectric spacer160and dielectric liner165relative to a top surface of field dielectric180. In this example, the contact etch has been terminated after a predetermined etch time, so that contact trench1910has a depth less than the height of gate electrode110and dielectrics160and165are present at the bottom of trench1910. The contact etch may alternatively land on gate dielectric115or any other underlying dielectric if there is sufficient etch selectively to ensure metallization190is not exposed.FIG.19Billustrates a cross-sectional view of multi-gate thin film transistor memory device401along the B-B′ line shown inFIG.18following the contact etch process. As shown inFIG.19A, contact trench1910is self-aligned to semiconductor layer120and field dielectric180. As shown inFIG.19B, the mask stripes confine each trench1910to a discrete portion of the dielectric spacer160and/or dielectric liner165. Returning toFIG.6, methods601continue at operation670where the contact trench formed at operation665is backfilled with any suitable contact metallization. Any known damascene technique may be employed at operation670, for example. In the example illustrated byFIG.20A(A-A′ cross-section) andFIG.20B(B-B′ cross-section), source and drain contact metallization150has been deposited and any overburden planarized with a top surface of field dielectric180and/or dielectric cap185. The resulting pairs of contact metallizations contacting the semiconductor layer120surrounding each gate electrode110may then be separately interconnected as distinct nodes of an IC. As shown, contact metallization has a height H2, which is a function of the trench etch depth. Metallization height H2is less than gate electrode height H1and the effective transistor channel width is a function of the overlap of H1and H2. Returning toFIG.6, methods601continue at operation675where the semiconductor layer is recessed relative to surrounding dielectric and/or contact metallization. Although optional, operation675may facilitate subsequent deposition of a passivation layer over the recessed surface of the semiconductor layer, and/or may facilitate subsequent electrical interconnection of the contact metallization. A timed etch selective to the semiconductor layer may be performed at operation675, for example. Backend interconnect levels may then be completed using any known techniques. In the example illustrated inFIG.21A(A-A′ cross-section) andFIG.21B(B-B′ cross-section), ILD1880has been deposited over the transistor structures, backfilling the recessed top surface of semiconductor layer120. In some embodiments ILD1880has the same composition as dielectric spacer160and/or dielectric liner165to passivate the recessed semiconductor layer surface. The transistor structures as shownFIGS.21A and21Bare therefore substantially as introduced inFIGS.1A and1Band are amenable to any further processing suitable for interconnecting transistors into integrated circuitry. FIG.22illustrates a mobile computing platform and a data server machine employing a memory device2250including BEOL TFTs, for example as described elsewhere herein. The server machine2206may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a vertical TFT in accordance with any of the embodiments described above. In some embodiments the vertical TFT is one in a packaged monolithic or MCM IC-eDRAM device. The mobile computing platform2205may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform2205may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system2210, and a battery2215. Disposed within the integrated system2210, a substrate2260includes an eDRAM2230and processor circuitry2240(e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). eDRAM2230includes 1C-1TFT cells, with each cell including a vertical TFT2231and a BEOL capacitor2232, for example having one or more of the features of the transistor structures described elsewhere herein. For monolithic embodiments, substrate2260is a semiconductor chip. For MCM embodiments, substrate2260may be any package substrate, or an interposer. Processor circuitry2240, or a separate RFIC chip may be further coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 1402.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. FIG.23is a functional block diagram of an electronic computing device, in accordance with some embodiments. Computing device2300may be found inside platform2205or server machine2206, for example. Device2300further includes a motherboard2302hosting a number of components, such as, but not limited to, a processor2304(e.g., an applications processor). Processor2304may be physically and/or electrically coupled to motherboard2302. In some examples, processor2304includes an integrated circuit die packaged within the processor2304. In general, the term “processor” or “microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory. In various examples, one or more communication chips2306may also be physically and/or electrically coupled to the motherboard2302. In further implementations, communication chips2306may be part of processor2304. Depending on its applications, computing device2300may include other components that may or may not be physically and electrically coupled to motherboard2302, and/or packaged with processor2304, and/or monolithically integrated with processor2304. These other components include, but are not limited to, volatile memory (e.g., eDRAM that may further incorporate at least one vertical TFT structure as described elsewhere herein), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. Communication chips2306may enable wireless communications for the transfer of data to and from the computing device2300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips2306may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device2300may include a plurality of communication chips2306. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure. It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below. In one or more first examples, a vertical thin film transistor comprises a gate electrode extending from an underlying material surface, a gate dielectric over a sidewall of the gate electrode. A semiconductor layer is over the gate dielectric material, the semiconductor layer separated from the sidewall of the gate electrode by at least the gate dielectric. The transistor comprises one or more isolation dielectric materials surrounding the semiconductor layer, a first contact metallization in contact with a first portion of the semiconductor layer, and a second contact metallization in contact with a second portion of the semiconductor layer. In one or more second examples, for any of the first examples the gate dielectric comprises a cladding surrounding the gate electrode, the semiconductor layer comprises a cladding surrounding the gate dielectric, the one or more isolation dielectric materials comprise a cladding surrounding the semiconductor layer, and a portion of the semiconductor layer between the gate dielectric and the isolation dielectric materials separates the first contact metallization from the second contact metallization. In one or more third examples, for any of the first or second examples the semiconductor layer comprises an oxide, the gate dielectric comprises a metal oxide, and the one or more isolation dielectric materials comprise at least a first dielectric and a second dielectric surrounding the first dielectric. In one or more fourth examples, for any of the first through third examples the first contact metallization is within a first trench in at least the first dielectric layer, a wall of the first trench comprising the second dielectric, and the second contact metallization is within a second trench in at least the first dielectric layer, a wall of the second trench comprising the second dielectric. In one or more fifth examples, for any of the fourth examples the first dielectric is separated from the semiconductor layer by one or more intervening dielectric layers. The first trench is in the first dielectric layer and the one or more intervening dielectric layers. The second trench is in the first dielectric layer and the one or more intervening dielectric layers. In one or more sixth examples, for any of the first examples the gate electrode has a first height as measure from the underlying surface. The first and second contact metallizations contact the semiconductor layer along a top portion of the first height. The isolation dielectric materials contact the semiconductor layer along a bottom portion of the first height, between the top portion and the underlying surface. In one or more seventh examples, for any of the sixth examples a top surface of the semiconductor layer is recessed below a top surface of the first and second contact metallizations. The gate electrode has a first height as measure from the underlying surface. The first and second contact metallizations have a second height, less than the first height. In one or more eighth examples, for any of the seventh examples the semiconductor layer is separated from the underlying surface by the gate dielectric, and a top surface of the gate electrode In one or more ninth examples, for any of the first examples the transistor further comprises a second gate electrode extending from the underlying material surface. The gate dielectric comprises a first cladding surrounding the gate electrode and a second cladding surrounding the second gate electrode. The semiconductor layer surrounds the first cladding and the second cladding. The one or more dielectric materials comprise a cladding surrounding the semiconductor layer. A first portion of the semiconductor layer between the first and second gate electrodes separates the first contact metallization from the second contact metallization. In one or more tenth examples, for any of the ninth examples a longitudinal length of at least one of the contact metallizations is at least equal to that of the first gate electrode summed with that of the second gate electrode. In one or more eleventh examples, a computer platform includes one or more processor, and a memory device coupled to the processor, wherein at least one of the processor and memory device comprises the thin film transistor in any of the first through tenth examples. In one or more twelfth examples, an integrated circuit memory device comprises a memory cell array including a plurality of thin film transistors (TFTs), wherein individual ones of the TFTs comprise a gate electrode extending from an underlying material surface, a gate dielectric over a sidewall of the gate electrode, a semiconductor layer over the gate dielectric, the semiconductor layer separated from the sidewall of the gate electrode by at least the gate dielectric, one or more isolation dielectric materials surrounding the semiconductor layer, a first contact metallization in contact with a first portion of the semiconductor layer, and a second contact metallization in contact with a second portion of the semiconductor layer. In one or more thirteenth examples, for any of the twelfth examples the underlying material surface further comprises an inter-level dielectric (ILD) layer over a substrate including a plurality of metal-oxide-semiconductor field effect transistors (MOSFETs) employing a monocrystalline semiconductor. In one or more fourteenth examples, for any of the thirteenth examples at least the gate electrode is electrically coupled to one of the MOSFETs through a wordline. In one or more fifteenth examples, a method of fabricating a thin film transistor (TFT) comprises forming a gate pillar extending from an underlying material surface, the gate pillar comprising a gate dielectric on a sidewall of a gate electrode material. The method comprises forming a semiconductor layer over a sidewall of the pillar, the semiconductor layer covering the gate dielectric on the sidewall of the pillar. The method comprises forming one or more dielectric materials around the pillar. The method comprises forming a pair of openings in the dielectric materials, each opening exposing a portion of the semiconductor layer. The method comprises forming contact metallization within the openings. In one or more sixteenth examples, for any of the fifteenth examples forming the gate pillar comprises patterning a feature into a sacrificial material layer, backfilling the feature with the gate electrode material, removing the sacrificial material layer to expose the sidewall of the gate electrode material, and depositing the gate dielectric over the exposed sidewall of the gate electrode material. In one or more seventeenth examples, forming the gate pillar comprises recessing a top surface of the gate electrode material from a top surface of the sacrificial material layer, and forming a dielectric cap over the recessed top surface of the gate electrode material, wherein the dielectric cap has a composition distinct from that of the sacrificial material layer. In one or more eighteenth examples, for any of the fifteenth examples forming the semiconductor layer comprises depositing a semiconductor material comprising atomic oxygen. In one or more nineteenth examples, for any of the eighteenth examples forming the semiconductor layer comprises blanket depositing the semiconductor layer over the pillar and the underlying material surface, and removing the semiconductor layer from at least a portion of the underlying material surface adjacent to the pillar. In one or more twentieth examples, for any of the nineteenth examples removing the semiconductor layer from the underlying material surface further comprises depositing a spacer dielectric over the semiconductor layer, anisotropically etching the spacer dielectric to form a dielectric spacer protecting the semiconductor layer covering the gate dielectric material on the sidewall, and removing the semiconductor layer unprotected by the dielectric spacer. In one or more twenty-first examples, for any of the twentieth examples forming one or more dielectric materials around the pillar further comprises depositing a first dielectric layer over the spacer dielectric and depositing a second dielectric layer over the first dielectric layer, and planarizing the first and second dielectric layers with the pillar to expose the dielectric spacer. Forming the pair of openings comprises recessing the first dielectric layer and the dielectric spacer selectively to the second dielectric layer. In one or more twenty-second examples, for any of the twenty-first examples the spacer dielectric comprises a metal oxide. In one or more twenty-third examples, for any of the fifteenth through twenty-second examples forming one or more dielectric materials around the pillar further comprises depositing a first dielectric layer over the pillar and a second dielectric layer over the first dielectric layer, and planarizing the first and second dielectric layers with the pillar to expose the dielectric spacer. Forming the pair of openings comprises recessing the first dielectric layer selectively to the second dielectric layer, the recessing of the first dielectric layer exposing the portion of the semiconductor layer. In one or more twenty-fourth examples, for any of the fifteenth through twenty-second examples the method further includes recessing the semiconductor layer below a top surface of the contact metallization, and depositing a dielectric material over the recessed semiconductor layer. In one or more twenty-fifth examples, for any of the twenty-fourth examples the dielectric material deposited over the recessed semiconductor layer comprises a metal oxide. However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. | 61,943 |
11862730 | DETAILED DESCRIPTION One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents. Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The term “adjacent” here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it). The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.” The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value. The term “scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term “scaling” generally also refers to downsizing layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slowing down or speeding up—i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. The term “between” may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material “between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, the term “backend” generally refers to a section of a die which is opposite of a “frontend” and where an IC (integrated circuit) package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten-metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term “frontend” generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low-level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten-metal stack die example). Here, multiple non-silicon semiconductor material layers may be stacked within a single fin structure. The multiple non-silicon semiconductor material layers may include one or more “P-type” layers that are suitable (e.g., offer higher hole mobility than silicon) for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more “N-type” layers that are suitable (e.g., offer higher electron mobility than silicon) for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors. The multiple non-silicon semiconductor material layers may be fabricated, at least in part, with self-aligned techniques such that a stacked CMOS device may include both a high-mobility N-type and P-type transistor with a footprint of a single finFET. Top-gate thin film transistor (TFTs) structures are described herein. Thin film transistors when in the top-gate configuration suffer from contact resistance. The embodiments of the current invention introduce a sheet of doping on the top surface of TFT channel material. The doping on the top surface of the TFT channel material results in improved contacts resistance. In some embodiments, the top-gate TFT comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer. In some embodiments, the dielectrics material includes one or more of: porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, or spin-on organic polymeric dielectric. In some embodiments, the dielectrics material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the first material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments, the second material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments, the second material is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the second material is doped with one or more of: O, F, H, Br, N, C, Cl, or B. In some embodiments, the second dielectric material is a high-K dielectric material which includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments the spacer includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, the first structure has a thickness in a range of 10-1000 Angstrom. In some embodiments, the second structure has a thickness in a range of 10-400 Angstrom. In some embodiments, the gate has a thickness in a range of 5 nm to 20 nm. In some embodiments, the metal of the gate includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. In some embodiments, the contact includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. In some embodiments, the top-gate TFT comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is partially doped; a second dielectric adjacent to the non-doped portion of the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer. In some embodiments, the dielectric material includes one or more of: porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, spin-on organic polymeric dielectric. In some embodiments, the dielectrics material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the first material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments, the second material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments, the second material is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the second material is doped with one or more of: O, F, H, Br, N, or C, Cl, or B. In some embodiments, the second dielectric material is a high-K dielectric material which includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments the spacer includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, the first structure has a thickness in a range of 10-1000 Angstrom. In some embodiments, the second structure has a thickness in a range of 10-400 Angstrom. In some embodiments, the gate has a thickness in a range of 5 nm to 20 nm. In some embodiments, the metal of the gate includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. In some embodiments, the contact includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. FIG.1Aillustrates a three dimensional (3D) plan view of a top-gate TFT structure100, in accordance with some embodiments.FIG.2Aillustrates a cross-sectional view of the top-gate thin film transistor structure100along the A-A′ shown inFIG.1A, in accordance with some further embodiments. As shown inFIG.1A, device100may include substrate102, channel104, doped channel106, second dielectric107, gate electrode110, and spacer materials114and116. FIG.1Billustrates a 3D plan view of a top-gate TFT structure100, in accordance with some alternative embodiments. As shown inFIG.1B, device100B may include substrate102B, channel104B, doped channel106B, second dielectric107B, gate electrode110B, and spacer materials114B and116B. FIGS.2A and2Billustrate cross-sectional views of top-gate TFT structure100along the A-A′ lines illustrated inFIGS.1A-B, respectively, in accordance with some embodiments. As shown inFIG.2A, device200may include substrate202, channel204, doped channel206, second dielectric207, gate electrode210, contact metals218and220, and spacer materials214and216.FIG.2Billustrates a cross-sectional view of the top-gate thin film transistor structure100B along the A-A′ shown inFIG.1B, in accordance with some further embodiments. In some embodiments, substrate202is a passivation material. In some embodiments, passivation material is an Interlayer Dielectric (ILD). For example, porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, or spin-on organic polymeric dielectric, can be used as ILD. In some embodiments, the ILD material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the thickness of the ILD (shown as Ti inFIG.2A) is less than or equal to 60 nm. ILD are dielectric materials used to electrically separate closely spaced interconnect lines arranged in several levels (multilevel metallization) in an advanced integrated circuit. Typically, ILD features low dielectric constant K (e.g., as close to 1 as possible) to minimize capacitive coupling (“cross talk”) between adjacent metal lines. In some embodiments, the first channel204is formed adjacent to the substrate202. In some embodiments the doped channel206is formed adjacent to the first channel204. In some embodiments the channel204and the doped channel206include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments the channel204and the doped channel206include one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. In some embodiments, the doped channel206is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the doped channel206is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Any suitable doping process may be employed, for example to dope the channel206described here. In some embodiments, the channel to be formed as a bi-layer with a conductive semiconductor layer of any of the listed channel materials, and wherein the conductive layer in direct contact with the second dielectric207, contact metals218and220, and spacer materials214and216. In some embodiments, the channel204has a thickness (shown as Tc inFIG.2A) in a range of 10-1000 Angstrom. In some embodiments, the doped channel206has a thickness (shown as Tdc inFIG.2A) in a range of 10-400 Angstrom. In some embodiments, the doped region has a thickness in a range of 0.5 nm to 5 nm. In some embodiments, second dielectric207is formed adjacent to the doped channel206. In some embodiments, second dielectric207may be a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, SiAlN, HfTiOx, or AlTiOx. In other embodiments the high-K dielectric material includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, the gate electrode210is formed adjacent to the gate dielectric207. In some embodiments, the gate electrode210includes one or more of: Pt, Ir, Ru, Mo, TaN, ITO, IZO, AZO, TiN, W, TiAlC, TaAlC, Al, WC, Cu, Ta, or Au. In some embodiments, the gate electrode210includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact transistor threshold voltage. Although gate electrode210is illustrated as homogeneous, a stack or laminate of metals may also be employed. In some embodiments, the spacers214,216are formed partially adjacent to the gate210and the gate electric207. In some embodiments, the spacers include one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, SiAlN, HfSiOx, or AlTiOx. In some embodiments, the spacers include one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, the contacts218,220are formed adjacent to the spacers214,216. In some embodiments, the contacts218and220include one or more of: Pt, Ir, Ru, Mo, TaN, ITO, IZO, AZO, TiN, W, TiAlC, TaAlC, Al, WC, Cu, Ta, or Au. In some embodiments, the contacts218and220include one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact transistor threshold voltage. Although contacts218and220are illustrated as homogeneous, a stack or laminate of metals may also be employed. As shown inFIG.2B, device200B may represent an alternative embodiment. As shown inFIG.2B, device200B may include substrate202B, channel204B, doped channel206B, second dielectric207B, gate electrode210B, contact metals218B and220B, and spacer materials214B and216B. In some embodiments, substrate202B is a passivation material. In some embodiments, passivation material is an Interlayer Dielectric (ILD). For example, porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, or spin-on organic polymeric dielectric, can be used as ILD. In some embodiments, the ILD material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the thickness of the ILD (shown as Ti inFIG.2B) is less than or equal to 60 nm. In some embodiments, the first channel204B is formed adjacent to the substrate202B. In some embodiments the doped channel206B is partially doped and formed adjacent to the first channel204B. In some embodiments, the channel204B and the partially doped channel206B include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments, the channel204B and the partially doped channel206B include one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. In some embodiments, the partially doped channel206B is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the partially doped channel206B is doped with one or more of: O, F, H, Br, N, C, Cl, or B. In some embodiments, the channel204B has a thickness (shown as Tc inFIG.2B) in a range of 10-1000 Angstrom. In some embodiments, the doped channel206B has a thickness (shown as Tdc inFIG.2B) in a range of 10-400 Angstrom. In some embodiments, the doped region has a thickness in a range of 0.5 nm to 5 nm. In some embodiments, the second dielectric207B is formed adjacent to the non-doped portion of channel206B. In some embodiments, second dielectric207B may be a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, STAIN, HfSiOx, or AlTiOx. In other embodiments the high-K dielectric material includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, the gate electrode210B is formed adjacent to the gate dielectric207B. In some embodiments, the gate electrode210B includes one or more of: Pt, Ir, Ru, Mo, TaN, ITO, IZO, AZO, TiN, W, TiAlC, TaAlC, Al, WC, Cu, Ta, or Au. In some embodiments, the gate electrode210B includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ta, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact transistor threshold voltage. Although gate electrode210B is illustrated as homogeneous, a stack or laminate of metals may also be employed. In some embodiments, the spacers214B,216B are formed partially adjacent to the gate210B and the gate electric207B. In some embodiments, the spacers include one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, SiAlN, HfTiOx, or AlTiOx. In some embodiments, the spacers include one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, the contacts218B,220B are formed adjacent to the spacers214B,216B. In some embodiments, the contacts218B and220B include one or more of: Pt, Ir, Ru, Mo, TaN, ITO, IZO, AZO, TiN, W, TiAlC, TaAlC, Al, WC, Cu, Ta, or Au. In some embodiments, the contacts218B and220B include one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ta, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact transistor threshold voltage. Although contacts218B and220B are illustrated as homogeneous, a stack or laminate of metals may also be employed. FIGS.3A-3Hillustrate cross-sections300,320,330,340,350,360,370, and380, respectively, of materials as a top-gate multilayer TFT is formed, in accordance with some embodiments. Cross-section300illustrates deposition of passivation material302. In some embodiments, passivation material302is an Interlayer Dielectric (ILD). For example, porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, or spin-on organic polymeric dielectric, can be used as ILD. In some embodiments, the ILD material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the thickness of the ILD (shown as Ti inFIG.3A) is less than or equal to 60 nm. Cross-section320illustrates disposition of channels304and306. In some embodiments, the channels (or semiconductor bodies)304and306include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments the channel304and the doped channel306include one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. In some embodiments, the channel306is doped. In some embodiments, channel306is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, channel306is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Any suitable doping process may be employed, for example to dope the channel306described here. In some embodiments, the channel304has a thickness (shown as Tc inFIG.3B) in a range of 10-1000 Angstrom. In some embodiments, the doped channel306has a thickness (shown as Tdc inFIG.3B) in a range of 10-400 Angstrom. Cross-section330illustrates formation of second dielectric307and gate layer310. In various embodiments, TFT formed here is a top-gate TFT where the gate is formed as one of the last structures of the TFT. In some embodiments, the gate comprises a metal. For example, the metal of the gate includes one or more of: Pt, Ir, Ru, Mo, TaN, ITO, IZO, AZO, TiN, W, TiAlC, TaAlC, Al, WC, Cu, Ta, Au. In some embodiments, the metal of the gate includes one or more of: TiN, TaN, Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. In some embodiments, the gate has a thickness (shown as Tg inFIG.3C) in the range of 5 nm (nanometer) to 20 nm. In some embodiments, second dielectric307comprises a dielectric material. In some embodiments, second dielectric307may be a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, SiAlN, HfTiOx, or AlTiOx. In other embodiments the high-K dielectric material includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. In some embodiments, second dielectric has a thickness (shown as Tdi inFIG.3C) in a range of 2 nm to 10 nm. Cross-section340shown inFIG.3Dillustrates etching of the gate layer310and second dielectric307up to layer306, resulting in openings308and309. Any known methods and techniques can be used to etch the gate layer310and second dielectric307. In some embodiments, a plasma etch is utilized. Cross-section350illustrates the structure of cross-section340following a deposition of a dielectric spacer312on uppermost surface of layer306, on sidewalls of gate310and second dielectric307and on the uppermost surface of gate310. In some embodiments, dielectric spacer312is deposited by an atomic layer deposition (ALD) process to ensure conformal deposition on the deposited surfaces. A conformal deposition process, for example, may provide a film with a uniform thickness at an interface with the sidewalls of gate310and second dielectric307. In some embodiments, the material of spacer312includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. The dielectric spacer312may be deposited to a thickness (shown as Ts inFIG.3E) in the range of 2 nm-20 nm. Cross-section360as shown inFIG.3Fillustrates etching of the dielectric spacer312over gate310and over openings308and309, up to layer306, leaving dielectric spacers314and316. Any known methods and techniques can be used to etch the dielectric spacer. In some embodiments, a plasma etch is utilized. Cross-section370as shown inFIG.3Gillustrates the structure of cross-section360following the deposition of a contact318. Any known methods and techniques can be used to deposit the contact318. In an embodiment, the contact318is deposited to a thickness of at least 2.5 times the combined thickness of second dielectric307and gate310to provide sufficient material for a subsequent planarization process. Cross-section380as shown inFIG.311illustrates the structure of Cross-section370following planarization of the contact318, upper portions of the dielectric spacers314and316and upper portions of the gate310. In some embodiments, the planarization process is a chemical mechanical polish (CMP) process. The CMP process is utilized to polish the contact318, the upper portions of the spacers314and316and upper portions of the gate310. Furthermore, in some embodiments, CMP process results in uppermost surfaces of the spacers314and316, gate310and the contact318and320being co-planar or substantially co-planar. FIGS.3I-3Uillustrate cross-sections300B,320B,330B,340B,350B,360B,370B,380B,382B,384B,386B,388B, and390B respectively, of materials as a top-gate multilayer TFT is formed, in accordance with some embodiments. Cross-section300B illustrates deposition of passivation material302. In some embodiments, passivation material302is an Interlayer Dielectric (ILD). For example, porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, spin-on organic polymeric dielectric, can be used as ILD. In some embodiments, the ILD material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the thickness of the ILD (shown as Ti inFIG.3I) is less than or equal to 60 nm. Cross-section320B illustrates disposition of channels304and306. In some embodiments, the channels304and306include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, or Te, Cu, Co, Nb, Ni, or Al. In some embodiments, the channels304and306include one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. In some embodiments, the channel306is doped. In some embodiments, the doped channel306is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the partially doped channel306is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Any suitable doping process may be employed, for example to dope the channel306described here. In some embodiments, the channel304has a thickness (shown as Tc inFIG.3J) in a range of 10-1000 Angstrom. In some embodiments, the doped channel306has a thickness (shown as Tdc inFIG.3J) in a range of 10-400 Angstrom. Cross-section330B as shown inFIG.3Killustrates formation of dummy (or sacrificial) second dielectric307B and dummy gate310B. In some embodiments, the dummy second dielectric includes a layer of material such as but not limited to silicon dioxide or silicon carbide and the dummy gate material includes a layer of material such as a doped polysilicon. In an embodiment, a resist mask is formed on the layer of dummy gate material. Cross-section340B as shown inFIG.3Lillustrates etching of the dummy gate layer310B and second dielectric307B up to layer306to form openings308and309. Any known methods and techniques can be used to etch the gate layer310B and second dielectric307B. In some embodiments, a plasma etch is utilized. Cross-section350B as shown inFIG.3Millustrates the structure of cross-section340following a deposition of a dielectric spacer312on uppermost surface of layer306, on sidewalls of dummy gate310B and dummy second dielectric307B, and on the uppermost surface of dummy gate310B. In some embodiments, dielectric spacer312is deposited by an atomic layer deposition (ALD) process to ensure conformal deposition on the deposited surfaces. A conformal deposition process, for example, may provide a film with a uniform thickness at an interface with the sidewalls of dummy gate310B and dummy second dielectric307B. In some embodiments, the material of spacer312includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. The dielectric spacer312may be deposited to a thickness (shown as Ts inFIG.3M) in the range of 2 nm-20 nm. Cross-section360B as shown inFIG.3Nillustrates etching of the dielectric spacer312over dummy gate310B and over openings308and309, up to layer306, leaving dielectric spacers314and316. Any known methods and techniques can be used to etch the dielectric spacer. In some embodiments, a plasma etch is utilized. Cross-section370B as shown inFIG.3Oillustrates the structure of cross-section360B following the deposition of a contact318. Any known methods and techniques can be used to deposit the contact318. In an embodiment, the contact318is deposited to a thickness of at least 2.5 times the combined thickness of dummy second dielectric307B and dummy gate310B to provide sufficient material for a subsequent planarization process. Cross-section380B as shown inFIG.3Pillustrates the structure of Cross-section370following planarization of the contact318, upper portions of the dielectric spacers314and316and upper portions of the dummy gate310B. In some embodiments, the planarization process is a chemical mechanical polish (CMP) process. The CMP process is utilized to polish the contact318, the upper portions of the dielectric spacers314and316and upper portions of the gate310B. Furthermore, in some embodiments, CMP process results in uppermost surfaces of the dielectric spacers314and316, dummy gate310B and the contact318and320being co-planar or substantially co-planar. Cross-section382B as shown inFIG.3Qillustrates the structure of cross-section380B following removal of the dummy gate310B and dummy second dielectric307B selectively to the dielectric spacers314and316. In some embodiments, dummy gate310B is removed by an etch process and the dummy second dielectric307B is removed by a wet process. Any suitable etch process and wet process may be employed, for example to etch the the dummy gate310B and dummy second dielectric307B described here. As shown, removal of the dummy gate310B and the dummy second dielectric307B creates an opening322. Cross-section384B as shown inFIG.3Rillustrates an embodiment of the structure of cross-section382B following removal of the doped layer306selectively in the opening322. In some embodiments, doped layer306in the opening322is selectively removed by a wet etch process. As shown, removal of the doped layer306creates an opening324. Cross-section386B as shown inFIG.3Sillustrates the structure of cross-section384B following a deposition of a second dielectric, on a top surface of layer304within opening324, on sidewalls of dielectric spacers314and316within opening322, on top surfaces of dielectric spacers314and316, and on top surfaces of the contact layers318and320. In an embodiment, the second dielectric326is deposited by an atomic layer deposition (ALD) process to ensure conformal deposition within openings322and324. A conformal deposition process, for example, may provide a film with a uniform thickness at an interface with layer304. In some embodiments, second dielectric326may be a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, STAIN, HfSiOx, or AlTiOx. In other embodiments the high-K dielectric material includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. The second dielectric326may be deposited to a thickness (shown as Tdi inFIG.3S) in the range of 2 nm-20 nm. A conformal deposition process, such as an ALD process is advantageous when depositing films that are 10 nm or more inside of an opening that ranges between 20 nm-50 nm. In an embodiment, the second dielectric326is doped with Si or Co after the deposition process. The doping process may be carried out ex-situ in an implanter for example. In another embodiment, the second dielectric326is doped with Si or Co during the deposition process. In other embodiments, a physical vapor deposition process is utilized to deposit the second dielectric326. In one such embodiment, the second dielectric326is amorphous as deposited on layer304and becomes crystalline after a thermal anneal process at process temperatures of at least 300 degrees Celsius. In an embodiment, an amorphous hafnium oxide film is deposited to a thickness in the range of 10 nm-15 nm and attains a thickness in the range of 8 nm-13 nm (shown as Tdi inFIG.3S) after a thermal anneal process. Cross-section388B as shown inFIG.3Tillustrates the structure of cross-section386B following a deposition of a gate electrode layer328on the second dielectric326in the opening322. In an embodiment, gate electrode layer328is blanket deposited by an atomic layer deposition process (ALD) process to ensure conformal deposition in opening322and over the second dielectric326. In other embodiments, a physical vapor deposition process is utilized. In an embodiment, a gate electrode layer having a crystalline texture is deposited on an amorphous second dielectric326and the stack is subjected to a thermal anneal at process temperatures above 300 degrees Celsius. In some embodiments, depositing gate electrode layer328may include depositing a stack of two or more conductive layers, where a first conductive layer that is directly on the second dielectric326sets the work function of the gate electrode (to be formed), and the remaining one or more conductive layers include fill layers. The fill layers provide protection to the work function electrode during a subsequent planarization process. Cross-section390B as shown inFIG.3Uillustrates the structure of cross-section388B following a planarization process to form a gate electrode and second dielectric. In some embodiments, the planarization process includes a CMP process. In some embodiments, the uppermost excess portions of gate electrode layer328and second dielectric326are removed leaving the gate electrode330and second dielectric326in the opening322. In some embodiments, uppermost surfaces of gate electrode330and second dielectric326are co-planar or substantially co-planar with the uppermost surface of contact layer318. Co-planarity is advantageous to minimize height variation between transistors and also minimize any potential contact formation issues. FIG.4Aillustrates a flowchart400A illustrating methods for fabricating a top-gated TFT device, in accordance with some embodiments. Flow chart400A begins at block (or operation)402forming a dielectric comprising a dielectric material. In some embodiments, the dielectric is a passivation material. In some embodiments, the passivation material is an Interlayer Dielectric (ILD). For example, porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, or spin-on organic polymeric dielectric, can be used as ILD. In some embodiments, the ILD material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the thickness of the ILD is less than or equal to 60 nm. Flowchart400A continues at operation404, forming a first structure adjacent to the dielectric, the first structure comprising a first material. In some embodiments, the first material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments the first material includes one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. Flowchart400A continues at operation406, forming a second structure adjacent to the first structure, wherein the second structure comprises a second material which is doped. In some embodiments, the second material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments the second material include one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. In some embodiments, the second material is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the second material is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Flowchart400A continues at operation408, forming a second dielectric adjacent to the second structure. In some embodiments, the second dielectric is a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, STAIN, HfTiOx, or AlTiOx. In some embodiments, the second dielectric material is a high-K dielectric material which includes one or more of: Hf, Si, O, Zr, Al, or N. Flowchart400A continues at operation410, forming a gate comprising a metal adjacent to the second dielectric. In some embodiments, the metal of the gate includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Flowchart400A continues at operation412, forming a spacer partially adjacent to the gate and the second dielectric. In some embodiments, the spacer includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Flowchart400A is then completed at operation414, forming a contact adjacent to the spacer. In some embodiments, the contact includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. FIG.4Billustrates a flowchart400B illustrating methods for fabricating a top-gated TFT device, in accordance with some other embodiments. Flow chart400B begins at block (or operation)402B forming a dielectric comprising a dielectric material. In some embodiments, the dielectric is a passivation material. In some embodiments, the passivation material is an Interlayer Dielectric (ILD). For example, porous SiO2, fluorine-doped SiO2, carbon-doped SiO2, porous-doped SiO2, spin-on silicon based polymeric dielectric, spin-on organic polymeric dielectric, can be used as ILD. In some embodiments, the ILD material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. In some embodiments, the thickness of the ILD is less than or equal to 60 nm. Flowchart400B continues at operation404B, forming a first structure adjacent to the dielectric, the first structure comprising a first material. In some embodiments, the first material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments the first material includes one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. Flowchart400B continues at operation406B, forming a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is partially doped. In some embodiments, the second material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. In some embodiments the second material includes one or more of: IGZO, ZnO, Cu2O, CoO, NbO, NiO, SnO, SnO2, Ga2O3, ITO, IZO, AZO, ITZO, ATZO, AIZO, In2O3, MoS2, WSe2, WTe2, MoTe2, black-phosphorus, amorphous/poly/single-crystal Si/Ge/SiGe/III-Vs like-GaN, InGaAs, or InP. In some embodiments, the second material is doped with one or more of: N, CHF3, CH3F, Cl2, Cl, F, F2, O2, N2O, NF3, or BCl3. In some embodiments, the second material is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Flowchart400B continues at operation408B, forming a second dielectric adjacent to the non-doped portion of the second structure. In some embodiments, the second dielectric is a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, SiAlN, HfTiOx, AlTiOx. In some embodiments, the second dielectric material is a high-K dielectric material which includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Flowchart400B continues at operation410B, forming a gate comprising a metal adjacent to the second dielectric. In some embodiments, the metal of the gate include one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Flowchart400B continues at operation412B, forming a spacer partially adjacent to the gate and the second dielectric. In some embodiments, the spacer includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Flowchart400B is then completed at operation414B, forming a contact adjacent to the spacer. In some embodiments, the contact includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. FIG.5illustrates a mobile computing platform500and a data server machine including at least one embedded or integrated top-gated TFT in accordance with some embodiments. In some embodiments, the server machine506may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a circuitry550. The mobile computing platform505may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like, in accordance with some embodiments. For example, the mobile computing platform505may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system510, and a battery515. Whether disposed within the integrated system510illustrated in the expanded view520, or as a stand-alone discrete or packaged multi-chip module within the server machine506, the circuits include at least one top-gate TFT, for example in accordance with some embodiments described elsewhere herein. In some embodiments, disposed within the integrated system510, a substrate560includes a circuitry520and processor circuitry540(e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). In some embodiments, circuitry520includes top-gate TFTs, for example as described elsewhere herein. For monolithic embodiments, substrate560is a semiconductor chip. In some embodiments, processor circuitry540, or a separate RFIC chip may be further coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 1402.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. FIG.6illustrates a smart device or a computer system or a SoC (System-on-Chip)1600including top-gate TFTs, according to some embodiments. For purposes of the embodiments, the transistors for the FEOL in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure. In some embodiments, memory cells are formed using top-gate TFTs. FIG.6illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device1600represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device1600. In some embodiments, one or more blocks (even all blocks) may be powered using the supercapacitor. Any of the blocks ofFIG.6may comprise a top-gate TFT as discussed with reference to various embodiments. In some embodiments, computing device1600includes first processor1610and network interface within1670such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. Any of the various blocks of computing device1600can have or use the super capacitor of various embodiments. In some embodiments, processor1610can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor1610include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device1600to another device. The processing operations may also include operations related to audio I/O and/or display I/O. In some embodiments, computing device1600includes audio subsystem1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device1600, or connected to the computing device1600. In some embodiments, a user interacts with the computing device1600by providing audio commands that are received and processed by processor1610. In some embodiments, computing device1600comprises display subsystem1630. Display subsystem1630represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device1600. Display subsystem1630includes display interface1632, which includes the particular screen or hardware device used to provide a display to a user. In some embodiments, display interface1632includes logic separate from processor1610to perform at least some processing related to the display. In some embodiments, display subsystem1630includes a touch screen (or touch pad) device that provides both output and input to a user. In some embodiments, computing device1600comprises I/O controller1640. I/O controller1640represents hardware devices and software components related to interaction with a user. I/O controller1640is operable to manage hardware that is part of audio subsystem1620and/or display subsystem1630. Additionally, I/O controller1640illustrates a connection point for additional devices that connect to computing device1600through which a user might interact with the system. For example, devices that can be attached to the computing device1600might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices. As mentioned above, I/O controller1640can interact with audio subsystem1620and/or display subsystem1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem1630includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller1640. There can also be additional buttons or switches on the computing device1600to provide I/O functions managed by I/O controller1640. In some embodiments, I/O controller1640manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features). In some embodiments, computing device1600includes power management1650that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem1660includes memory devices for storing information in computing device1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem1660can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device1600. In some embodiments, Memory subsystem1660includes the scheme of analog in-memory pattern matching with the use of resistive memory elements. In some embodiments, memory subsystem includes the 1T-1C memory using TFTs, according to some embodiments. Elements of embodiments are also provided as a machine-readable medium (e.g., memory1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection). In some embodiments, computing device1600comprises connectivity1670. Connectivity1670includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device1600to communicate with external devices. The computing device1600could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. Connectivity1670can include multiple different types of connectivity. To generalize, the computing device1600is illustrated with cellular connectivity1672and wireless connectivity1674. Cellular connectivity1672refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)1674refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication. In some embodiments, computing device1600comprises peripheral connections1680. Peripheral connections1680include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device1600could both be a peripheral device (“to”1682) to other computing devices, as well as have peripheral devices (“from”1684) connected to it. The computing device1600commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device1600. Additionally, a docking connector can allow computing device1600to connect to certain peripherals that allow the computing device1600to control content output, for example, to audiovisual or other systems. In addition to a proprietary docking connector or other proprietary connection hardware, the computing device1600can make peripheral connections1680via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types. Reference in the specification to “an embodiment,” “some embodiments,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “some embodiments,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims. In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting. The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process. Example 1. An apparatus comprising: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer. Example 2. The apparatus of example 1, wherein the dielectric material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. Example 3. The apparatus of examples 1-2, wherein the first material include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. Example 4. The apparatus of examples 1-3, wherein the second material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. Example 5. The apparatus of examples 1-4, wherein the second material is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Example 6. The apparatus of examples 1-5, wherein the second dielectric is a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, STAIN, HfTiOx, or AlTiOx. Example 7. The apparatus of examples 1-6, wherein the second dielectric material is a high-K dielectric material which includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Example 8. The apparatus of examples 1-7, wherein the spacer include one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Example 9. The apparatus of examples 1-8, wherein the first structure has a thickness in a range of 10-1000 Angstrom. Example 10. The apparatus of examples 1-9, wherein the second structure has a thickness in a range of 10-400 Angstrom. Example 11. The apparatus of examples 1-10, wherein the gate has a thickness in a range of 5 nm to 20 nm. Example 12. The apparatus of examples 1-11, wherein the metal of the gate includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Example 13. The apparatus of examples 1-12, wherein the contact include one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Example 14. An apparatus comprising: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is partially doped; a second dielectric adjacent to the non-doped portion of the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer. Example 15. The apparatus of example 14, wherein the dielectric material includes one or more of: Si, O, C, F, Hf, Zr, Al, N, Ta, Ti, Y, or La. Example 16. The apparatus of examples 14-15, wherein the first material include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. Example 17. The apparatus of examples 14-16, wherein the second material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, Mo, Se, W, S, Te, Cu, Co, Nb, Ni, or Al. Example 18. The apparatus of examples 14-17, wherein the second material is doped with one or more of: O, F, H, Br, N, C, Cl, or B. Example 19. The apparatus of examples 14-18, wherein the second dielectric is a high-K dielectric material which includes one or more of: HfO2, Al2O3, Ta2O5, TiO2, SiN, SiON, SiO2, SiAlOx, HfSiOx, HfAlOx, AlN, ZrOx, HfZrOx, ZrAlOx, SiAlOx, Y2O3, La2O3, HfYOx, HfLaOx, SiOC, SiAlC, SiC, STAIN, HfTiOx, or AlTiOx. Example 20. The apparatus of examples 14-19, wherein the second dielectric material is a high-K dielectric material which includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Example 21. The apparatus of examples 14-20, wherein the spacer includes one or more of: Hf, Si, O, Zr, Al, N, Ta, Ti, Y, La, or C. Example 22. The apparatus of examples 14-21, wherein the first structure has a thickness in a range of 10-1000 Angstrom. Example 23. The apparatus of examples 14-22, wherein the second structure has a thickness in a range of 10-400 Angstrom. Example 24. The apparatus of examples 14-23, wherein the gate has a thickness in a range of 5 nm to 20 nm. Example 25. The apparatus of examples 14-24, wherein the metal of the gate includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Example 26. The apparatus of examples 14-25, wherein the contact includes one or more of: Ti, N, Ta, W, C, Pt, Cr, Hf, Ir, Ru, Mo, In, O, Al, Zn, Cu, or Au. Example 27. An electric circuit comprising: one or more transistors; and wherein one or more of the transistors are coupled to a TFT device comprising: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer. Example 28. An electric circuit comprising: one or more transistors; and wherein one or more of the transistors are coupled to a TFT device comprising: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a third material wherein the second material is partially doped; a second dielectric adjacent to the non-doped portion of the second structure; a gate comprising a metal adjacent to the second. dielectric; a spacer adjacent to the gate and the second dielectric; a contact adjacent to the spacer. Example 29. A method comprising: forming a dielectric comprising a dielectric material; forming a first structure adjacent to the dielectric, the first structure comprising a first material; forming a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; forming a second dielectric adjacent to the second structure; forming a gate comprising a metal adjacent to the second dielectric; forming a spacer partially adjacent to the gate and the second dielectric; and forming a contact adjacent to the spacer. Example 30. A method comprising: forming a dielectric comprising a dielectric material; forming a first structure adjacent to the dielectric, the first structure comprising a first material; forming a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is partially doped; forming a second dielectric adjacent to the non-doped portion of the second structure; forming a gate comprising a metal adjacent to the second dielectric; forming a spacer partially adjacent to the gate and the second dielectric; and forming a contact adjacent to the spacer. An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment. | 68,150 |
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