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11862531 | DESCRIPTION OF EMBODIMENTS At present, many industrial-grade energy products and the like require a large number of densely arranged high-power devices, which generate considerable heat. Therefore, such products need to have a good heat dissipation performance. In the packaging of a power device, a soldering process is usually used to implement an electrical connection between the power device and a circuit board. One of the commonly used soldering processes is wave soldering. In wave soldering, molten solder (such as lead-tin alloys) is sprayed by an electric pump or an electromagnetic pump into a solder wave as required by the design. The solder wave may also be formed by injecting nitrogen into a solder pool. A circuit board (which may be referred to as a printed circuit board, a printed board, a plug-in board, a wiring board, or the like) pre-loaded with components is passed through the solder wave, implementing soft soldering for mechanical and electrical connections between welding ends or pins (also referred to as prongs) of the components and pads of the circuit board. Wave soldering includes normal wave soldering and selective wave soldering. Regardless of whether it is normal wave soldering or selective wave soldering, component holes are required on the circuit board. When the power device is electrically connected to the circuit board, pins of the power device are first inserted into the component holes. Then, the pins are soldered into the component holes of the circuit board. After the soldering is completed, if the length of the pins in the direction perpendicular to the board surface is too long, the extra length of the pins further needs to be cut off. It can be learned that many steps are required to implement the electrical connection between the power device and the circuit board through soldering, resulting in a low efficiency and high manufacturing costs. To improve the processing efficiency of a power device assembly and reduce manufacturing costs, SMT (surface-mount technology) may be used to implement an electrical connection between pins of a power device and a circuit board. The power device is usually equipped with a heat sink to dissipate a lot of heat produced when the power device is in operation. Due to factors such as a tolerance in the size of the power device itself and an assembly tolerance thereof, the heat sink is not in close contact with the power device in the SMT, causing a higher thermal resistance and affecting the heat dissipation efficiency of the assembly. To resolve the problem that the heat sink is not in close contact with the power device, a fastener is usually required to fasten a circuit board and a heat sink, so that the power device is sandwiched between the circuit board and the heat sink, and the power device can cling to the heat sink. However, there are still large voids between the power device and the heat sink, resulting in a large thermal resistance of the power device and the assembly thereof, and it is difficult to meet increasingly stringent heat dissipation requirements on power devices. This disclosure provides a power device and a corresponding power device assembly (including a heat sink) thereof, which facilitate the reduction of voids on an interface between the power device and the heat sink, thereby improving the heat dissipation efficiency. The power device and assembly provided in this disclosure can be applied to various electric energy conversion apparatuses that require high-power devices, and the electric energy conversion apparatuses can further be connected to an electric energy conversion device to complete various power functions of the device. For example, the power device assembly of this disclosure can be applied in the field of electric vehicle power systems, that is, the electric energy conversion device may be included in an electric vehicle. The electric energy conversion apparatus may be a motor controller, and the power device may be a power conversion unit assembled in the motor controller. The electric energy conversion apparatus may also be an on-board charger (OBC), and the power device may be an energy conversion unit. The electric energy conversion apparatus may also be a low-voltage control power supply, and the power device may be a DC-DC conversion unit therein, or the like. In addition, the power device assembly of this disclosure is not limited to the field of electric vehicles, but can also be widely used in the field of conventional industrial control, for example, can be applied to an uninterruptible power supply (UPS) in a data center, an inverter of a photovoltaic power generation device, a power supply of a server, and the like. The following further describes in detail this disclosure with reference to the accompanying drawings. Referring toFIG.1, a first implementation provides a power device assembly100, including a power device20, a circuit board (printed circuit board, PCB)40, a heat sink60, and a fastener70. The power device20is electrically connected to the circuit board40, and the power device20is sandwiched between the circuit board40and the heat sink60. The heat sink60dissipates heat for the power device20and the circuit board40. The heat sink60may use a heat dissipation method such as air cooling, water cooling, or the like, which is not limited in this disclosure. The circuit board40is a board-level structure used to provide the power device20, another chip package structure, and the like. The power device20is provided with a through hole21, and the circuit board40is provided with a cutout41. The heat sink60includes an assembling surface62, and the assembling surface62is provided with a connecting hole64. The fastener70passes through the through hole21, the cutout41, and the connecting hole64, so that the power device20and the heat sink60are connected. Because the fastener70directly passes through the power device20and crimps the power device20onto the heat sink60, the power device20closely fits the heat sink60, increasing an area of fitting between the power device20and the heat sink60, and effectively reducing voids on an interface between the power device20and the heat sink60, thereby reducing a thermal resistance of the power device20and the power device assembly100, and improving the heat dissipation efficiency of the power device20and the power device assembly100. The following describes various parts of the foregoing power device assembly100in detail. Referring toFIG.1andFIG.2, the power device20includes a package body201and pins203. The package body201includes a bottom portion2011, a top portion2013, and side portions2015. The top portion2013and the bottom portion2011are disposed opposite each other. The surface of the top portion2013opposed from the bottom portion2011faces the heat sink60. The surface of the bottom portion2011opposed from the top portion2013faces the circuit board40. In this implementation, the pins203may extend in a small outline package (SOP), that is, the pins203extend from the side portions2015of the package body201and have a wing-like structure (for example, an L- or J-shape). A first end of each pin203is connected to the side portion2015, and a second end of each pin203protrudes from the side portion2015. The second end of each pin203includes a mounting surface2031, and the mounting surface2031of the pin203is connected to the circuit board40to form an electrical connection between the power device20and the circuit board40. The mounting surface2031is connected to the circuit board40through a surface-mount technology (SMT). SMT is a circuit assembly technology in which no-pin or short-lead surface assembly devices are connected to the surface of a circuit board or another substrate, and then soldered and assembled by using methods such as reflow soldering or dip soldering. In this implementation, an orientation of the mounting surface2031is the same as an orientation of the bottom portion2011opposed from the top portion2013. In the power device assembly100provided in the first implementation of this disclosure, to form the electrical connection between the power device20and the circuit board40, the mounting surface2031is directly connected to the circuit board40. For example, a reflow soldering process is used in which air or nitrogen is heated to a high enough temperature and then blown to the circuit board onto which the components are already bonded, so that solder on both sides of the components is molten and bonded to the circuit board. There is no need to cut off excessively long pins, which simplifies the steps of assembly between the power device20and the circuit board40, and facilitates reduction of manufacturing costs of the power device assembly100. In addition, the pins203of the power device20may be first soldered to the circuit board40, and then the power device20is crimped onto the circuit board40, which improves the assembling efficiency. With reference toFIG.3, from the top view, the package body201may be roughly square, that is, there are four side portions2015. The plurality of pins203is distributed along the four side portions2015of the package body201so that the plurality of pins203extend from the four side portions2015(that is, toward four directions) of the package body201. It can be understood that this disclosure does not limit the distribution of the plurality of pins203along the four side portions2015of the package body201. In other implementations, the package of the power device20may have the pins extending toward at least two directions, that is, the plurality of pins203is distributed along at least two side portions2015of the package body201. This disclosure does not limit the shape of the package body201either, and the package body201may also be of a circular, triangular, polygonal, or irregular shape, or the like. It can be understood that this disclosure does not limit how the pins203extend, either. The pins203may be configured based on an internal topology and functional requirements of the power device20. The pin spacing and shape can be freely allocated on the premise that a distance between the pins203meets the requirements. For example, the pins203may extend in a heat sink small outline package (small outline package with heat sink, HSOP), and the pins203extend from the side portions2015. The pins203extend from the side portions2015of the package body201, so that the package of the power device20is flexible in the direction and number of the pins. Referring toFIG.4, the package body201includes a substrate structure22, a semiconductor die24, and a molded package26. The semiconductor die24is disposed on the substrate structure22, and the substrate structure22further includes a heat dissipation surface29connectable to the heat sink60. The molded package26covers the semiconductor die24and the substrate structure22excluding the heat dissipation surface29. The through hole21extends through the substrate structure22and the molded package26, and is configured to pass through the fastener70. The inner wall of the through hole21is covered with the molded package26to have insulating properties. The first end of each pin203is connected to the substrate structure22and the second end of each pin203is uncovered from the molded package26to form an electrical connection to the circuit board40. The heat dissipation surface29is uncovered from the molded package26and is configured to conduct heat produced by the power device20to the heat sink60. The through hole21and an electrical structure (not shown) of the substrate structure22are insulated from each other to improve the reliability of the power device20.FIG.1toFIG.4only show one through hole21as an example. It can be understood that the number of through holes21is not limited in this disclosure. In other implementations, there may be two or more through holes21, and the number of the through holes is set based on different requirements of the power device20. The substrate structure22includes a first surface220and a second surface221that are disposed opposite each other. The semiconductor die24is disposed on the first surface220, and the heat dissipation surface29is disposed on the second surface221. More specifically, the substrate structure22includes a metal substrate222and a heat dissipation substrate226that are laminated. The through hole21extends through the metal substrate222and the heat dissipation substrate226. The first surface220is the surface of the bottom layer of the metal substrate222opposed from the heat dissipation substrate226. The second surface221is the surface of the heat dissipation substrate226opposed from the metal substrate222. The heat dissipation surface29is the surface of the heat dissipation substrate226opposed from the metal substrate222, and the molded package26covers the metal substrate222and the remaining surfaces of the heat dissipation substrate226other than the heat dissipation surface29. The metal substrate222includes a thermally conductive insulation layer2222and a metal layer2224that are laminated, and the semiconductor die24is disposed on the surface of the metal layer2224opposed from the thermally conductive insulation layer2222. The through hole21extends through the thermally conductive insulation layer2222and the metal layer2224, and the first end of each pin203is connected to the metal layer2224provided with the semiconductor die24. In this implementation, the metal substrate222is a substrate prepared by using a direct bonded copper (DBC) process, that is, the metal layer2224is a copper layer. DBC refers to a process in which one or both sides of a ceramic substrate is/are clad with copper, and the copper and a ceramic layer are bonded together at high temperature. The metal substrate222may also be prepared by using other processes, for example, a direct plate copper (DPC) process. DPC refers to a method in which a ceramic substrate is plated with a copper layer by vacuum sputtering, and then a development process is used to manufacture electrical circuits. For another example, active metal brazing (AMB) may be used, and AMB refers to a method that relies on active brazing filler metal for high-temperature metallurgical bonding of aluminum nitride and oxygen-free copper. It can be understood that the metal substrate222is not limited to a copper-clad ceramic substrate, but may also be a copper-clad metal substrate, or the like. The copper-clad metal substrate uses metal (such as aluminum, copper, iron, or molybdenum) as a substrate that is covered with a thermally conductive insulation layer, and then a copper layer is covered on the side surface of the thermally conductive insulation layer opposed from the metal substrate. It can be understood that the metal layer2224is not limited to a copper layer, but may alternatively be another metal layer, for example, a gold layer. The thermally conductive insulation layer2222includes aluminum nitride. Alternatively, the thermally conductive insulation layer2222may include another insulating material, such as aluminum oxide. FIG.5is a schematic diagram of a structure in which the metal substrate222is clad with copper on both sides, where there are two metal layers2224. The thermally conductive insulation layer2222includes a first surface2225and a second surface2226that are disposed opposite each other. One metal layer2224is connected to the first surface2225of the thermally conductive insulation layer2222, and the other metal layer2224is connected to the second surface2226of the thermally conductive insulation layer2222. The semiconductor die24is disposed on the side of the metal layer2224on the first surface2225and opposed from the thermally conductive insulation layer2222. That is, the two metal layers2224are respectively disposed on the two opposite surfaces of the thermally conductive insulation layer2222. In other words, the metal substrate222is a double-sided copper-clad metal substrate, and the through hole21extends through the thermally conductive insulation layer2222and the metal layers2224of the metal substrate222. The metal layers2224are made of a copper material with good thermal conductivity, so that the metal substrate222has good thermal conductivity. The double-sided copper-clad metal substrate has two metal layers2224so that the thermal conductivity and reliability of the power device20are improved. The heat dissipation substrate226is connected to the surface of the metal substrate222opposed from the semiconductor die24. In this implementation, the heat dissipation substrate226is connected to the metal layer2224that is not provided with the semiconductor die24to enhance the heat dissipation performance of the power device20and improve the heat dissipation efficiency of the power device20. In this implementation, the heat dissipation substrate226may be connected to the surface of the metal substrate222opposed from the semiconductor die24by using a bonding layer224. The bonding layer224may be a welding layer. The welding layer has a good bonding performance and thermal conductivity, so that the welding layer can not only firmly connect the heat dissipation substrate226and the metal substrate222, but can also well conduct heat produced by the metal substrate222to the heat dissipation substrate226for heat dissipation. It can be understood that this disclosure does not limit the metal substrate222to be a double-sided metal substrate. In other implementations, there may be one metal layer2224in the metal substrate222, that is, the metal substrate222is single-sided.FIG.6is a schematic diagram of a structure when the metal substrate222is clad with copper on a single side. The heat dissipation substrate226is disposed on the side of the thermally conductive insulation layer2222opposed from the metal layer2224. It can be understood that the bonding layer224may alternatively be omitted in the foregoing solution, and the heat dissipation substrate226and the metal substrate222are directly molded together by using the molded package26. The semiconductor die24includes electronic components, such as electronic components having a power conversion function: a high-power transistor, a thyristor, a bidirectional thyristor, a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a diode, a silicon controlled rectifier (SCR), SiC, GaN, and the like. A connection manner of internal devices of the semiconductor die24is not limited. The devices may be connected in series or parallel to form a functional circuit, or the devices may be independent cells. In this way, the number of devices can be effectively reduced, and copper wiring connection forms required for the use of discrete devices on the circuit board can be reduced, optimizing the design of dimensions of the circuit board, thereby reducing the volume of the power device. A topology of the semiconductor die24may be single-tube, half-bridge, H-bridge, three-phase full-bridge, three-level, or the like. For example, the semiconductor die24includes an IGBT (as shown inFIG.7a) half-bridge topology and a MOSFET (as shown inFIG.7b) half-bridge topology. The semiconductor die24may further integrate device drive protection control and junction temperature protection. It can be understood that this disclosure does not limit the type, the topological structure, and the number of semiconductor dies24. The letters inFIG.7aandFIG.7brepresent symbols of the pins. For example, P1, P2, and P3refer to power pin numbers, T1and T2refer to temperature sampling pin numbers, G1and S1refer to switching tube drive pin numbers, Isense1and Isense2refer to current sampling pin numbers, and so on, which are not listed herein. Referring back toFIG.4, the power device20includes a bonding wire27disposed on the molded package26. The bonding wire27is connected between the semiconductor die24and the metal layer2224provided with the semiconductor die24, and is configured to connect the semiconductor die24and an internal electrical structure in the metal substrate222. Referring back toFIG.1, the circuit board40includes a top surface (T surface)43and a bottom surface (B surface)44. The cutout41extends through the top surface43and the bottom surface44of the circuit board40. When the power device20is connected to the circuit board40, the surface of the bottom portion2011opposed from the top portion2013is disposed facing the circuit board40, and the heat dissipation surface29of the power device20is on the side of the top portion2013opposed from the circuit board40. In this implementation, an orientation of the heat dissipation surface29is opposite an orientation of the mounting surface2031, that is, the heat dissipation surface29is disposed on the surface of the top portion2013opposed from the bottom portion2011. The mounting surface2031of the pin203extends from the side to the bottom portion2011of the power device20, and the mounting surface2031of the pin203is connected to the bottom surface44of the circuit board40. The fastener70passes through the cutout41, the through hole21, and the connecting hole64, so that the power device20, the circuit board40, and the heat sink60are connected together. Because the power device20is provided with the through hole21, and the fastener70passes through the through hole21and the connecting hole64to directly crimp the power device20onto the heat sink60, the heat dissipation surface29of the power device20closely fits the assembling surface62of the heat sink60, effectively reducing voids on an interface between the power device20and the heat sink60, thereby reducing a thermal resistance of the power device20and the power device assembly100, and improving the heat dissipation efficiency of the power device20and the power device assembly100. The fastener70includes a rod72and a cap74connected to one end of the rod72. The rod72passes through and is connected to the cutout41, the through hole21, and the connecting hole64, and the circuit board40is sandwiched between the cap74and the surface of the package body201opposed from the heat sink60. The cap74is disposed on the side of the circuit board40opposed from the heat sink60to prevent the fastener70from falling off the circuit board40. This disclosure does not limit a connection manner of the fastener70and the heat sink60. For example, the fastener70may be a screw, an outer wall of the rod72is provided with a thread, the connecting hole64is a screw hole, and the fastener70is connected to the connecting hole64in a screwed manner. Alternatively, the fastener70may be a stud, a pin, a rivet, or the like. The power device assembly100includes a washer80encircled on the rod72. The washer80is sandwiched between the cap74and the circuit board40. The cap74is disposed on the side of the washer80opposed from the circuit board40. A surface area of the washer80is greater than a size of the through hole21, to enlarge a stressed area of the circuit board40and prevent a stress on a local area of the circuit board40from being excessively large and causing damages (for example, a risk of fracture) to the circuit board40. The washer80may be integrated with or provided separately from the fastener70. The power device assembly100includes a thermally conductive interface layer90, and the thermally conductive interface layer90is sandwiched between the power device20and the heat sink60. The thermally conductive interface layer90is configured to conduct heat produced by the power device20to the heat sink60for heat dissipation. The thermally conductive interface layer90is formed with a mounting hole91, and the rod72of the fastener70also passes through the mounting hole91. The thermally conductive interface layer90is sandwiched between the heat dissipation surface29of the power device20and the assembling surface62of the heat sink60. Because the heat dissipation surface29of the power devices20is in direct contact with the assembling surface62of the heat sink60through the thermally conductive interface layer90for heat dissipation, a heat dissipation path is short, which can effectively improve the heat dissipation efficiency of the power device20and the power device assembly100, thereby improving power density of the power device20and the power device assembly100. In this implementation, the thermally conductive interface layer90includes a nano copper hook-and-loop tape. When the power device assembly100is assembled, the assembling surface62of the heat sink60is coated with a film layer (not shown) and deoxidized. The film layer is a metal layer to improve the degree of fitting between the thermally conductive interface layer90and the assembling surface62. The metal layer may include at least one of nickel, copper, silver, gold, and palladium. It can be understood that the material of the metal layer is not limited in this disclosure. Then, the heat dissipation surface29of the power device20is deoxidized to improve the degree of fitting between the thermally conductive interface layer90and the heat dissipation surface29. Next, the nano copper hook-and-loop tape is provided between the heat dissipation surface29of the power device20and the assembling surface62of the heat sink60, and is cured to form the thermally conductive interface layer90after a specific time at a specific temperature and pressure (for example, the pressure is 2 MPa, the temperature is 100° C., and the length of time is 10 min). The fastener70passes through the cutout41of the circuit board40, the through hole21, and the mounting hole91, connectable to the connecting hole64of the heat sink60. It can be understood that the thermally conductive interface layer90is not limited to the nano copper hook-and-loop tape. Alternatively, the thermally conductive interface layer90may be made of another material. For example, the thermally conductive interface layer90may be a graphite thermal pad, a thermal grease, a thermal gel, or the like. In an implementation, when the thermally conductive interface layer90includes a graphite thermal pad, during preparation, a graphite thermal pad is fabricated in advance to form the thermally conductive interface layer90based on the area of the power device20, and the thermally conductive interface layer90is formed with the mounting hole91. When the power device assembly100is assembled, the thermally conductive interface layer90is placed between the heat dissipation surface29and the heat sink60, and the fastener70passes through the cutout41of the circuit board40, the through hole21, the mounting hole91of the thermally conductive interface layer90and is connected to the connecting hole64of the heat sink60. In an implementation, when the thermally conductive interface layer90includes a thermal grease or a thermal gel, during preparation, the assembling surface62of the heat sink60is coated with the thermal grease or the thermal gel to form the thermally conductive interface layer90, and then the fastener70passes through the cutout41of the circuit board40and the through hole21, and is connected to the connecting hole64of the heat sink60. When the power device assembly100is assembled, the circuit board40is soldered to the power device20and then is placed on the heat sink60and positioned, and the fastener70passes through the washer80, the circuit board40, and the through hole21of the package body201of the power device20to be directly into the connecting hole64of the heat sink60. The fastener70applies pressure on the washer80, and the washer80presses the circuit board40as a whole to implement close fitting between the heat dissipation surface29of the power device20, the thermally conductive interface layer90, and the heat sink60, thereby reducing voids between the assembling surface62of the heat sink60and the heat dissipation surface29of the power device20, reducing a thermal resistance of the power device20and the power device assembly100, and improving the heat dissipation performance of the power device20and the heat dissipation efficiency of the power device assembly100. In the power device20and the power device assembly100provided in this disclosure, the mounting surface2031of the pin203directly fits the circuit board40through the surface-mount technology, implementing an electrical connection between the power device20and the circuit board40. Because there is no need to insert the pins into the component holes of the circuit board, steps of assembling the circuit board40with the power device20are simplified, and a process of the power device assembly100is simplified, thereby improving the processing efficiency of the power device assembly100and reducing manufacturing costs of the power device assembly100. In addition to the electrical connection between the power device20and the circuit board40using the surface-mount technology, the power device20is provided with the through hole21extending through the molded package26and the substrate structure22, so that the fastener70can directly pass through the through hole21to assemble the power device20, the circuit board40, and the heat sink60together and directly crimp the power device20onto the heat sink60. In this way, the power device20can closely fit the heat sink60, effectively reducing voids on an interface between the power device20and the heat sink60, thereby reducing a thermal resistance of the power device20and the power device assembly100, and improving the heat dissipation efficiency of the power device20and the power device assembly100. In addition, the power device200uses the surface-mount technology. The pins203of the power device20may be first connected to the circuit board40, and then the power device20and the heat sink60are assembled together. No soldering is required, which helps simplify the assembly process of the power device assembly100and the related apparatus. Referring now toFIG.8, a power device20is provided in a second implementation that is substantially the same as the power device20provided in the first implementation, excluding that a heat dissipation substrate is omitted from a substrate structure. A metal substrate222of the substrate structure includes a thermally conductive insulation layer2222and two metal layers2224. The two metal layers2224are respectively disposed on two opposite sides of the thermally conductive insulation layer2222. A semiconductor die24is disposed on the side of one metal layer2224opposed from the thermally conductive insulation layer2222. A molded package26covers the semiconductor die24and the metal substrate222excluding a heat dissipation surface to form a package body201. The side surface of the other metal layer2224that is not provided with a semiconductor die24and that is opposed from the thermally conductive insulation layer2222is used as the heat dissipation surface of the power device20. In other words, one surface of the metal substrate222can be directly used as the heat dissipation surface, that is, the surface of the metal substrate222provided with the semiconductor die24is a first surface of the substrate structure, and the surface of the metal substrate222opposed from the semiconductor die24is a second surface of the substrate structure. Pins203may extend in SOP. Referring toFIG.9, a power device20provided in a third implementation that is substantially the same as the power device20provided in the first implementation, excluding that pins203may extend in HSOP. A second end of each pin203is uncovered from the surface of a bottom portion2011of a package body201opposed from a top portion2013, and extends in the stacking direction of a thermally conductive insulation layer2222and metal layers2224of a metal substrate222opposed from the power device20, and an orthographic projection of the pin203along the stacking direction is completely disposed on the metal substrate222. Referring toFIG.10, a power device assembly100provided in a fourth implementation that is substantially the same as the power device provided in the first implementation. Compared toFIG.11, a difference is as follows: an orientation of a mounting surface2031of a pin203is the same as an orientation of a bottom portion2011of a package body201opposed from a top portion2013, and a heat dissipation surface29of the power device20is disposed on the surface of the bottom portion2011of the package body201opposed from the top portion2013. A circuit board40is provided with a cutout41extending through a top surface43and a bottom surface44, that is, the circuit board40has an open window design. A mounting surface2031of the pin203is connected to the top surface43together. A heat sink60passes through the cutout41. A rod72of a fastener70passes through the through hole21and a mounting hole91of a thermally conductive interface layer90, and is directly connected to a connecting hole64of the heat sink60together. A cap74is disposed on the surface of the package body201opposed from the heat sink60, that is, the cap74is disposed on the side of the surface of a top portion2013opposed from a bottom portion2011. It can be understood that the heat sink60may be provided with a boss passing through the cutout41of the circuit board40, to implement direct-contact heat dissipation between the heat sink60and the heat dissipation surface29of the power device20. In this implementation, the thermally conductive interface layer90may also be omitted, the fastener70passes through the through hole21and is directly connected to the connecting hole64. The fastener70may be a screw, a pin, a rivet, or the like. With reference to the first and the fourth implementations, depending on a position of the heat dissipation surface disposed on the power device, an assembly manner of the power device, the circuit board, and the heat sink may be selected. For example, when the heat dissipation surface is disposed on the surface of the top portion of the power device opposed from the bottom portion of the power device, the pins may be soldered to the bottom surface of the circuit board by using reflow soldering, and the circuit board does not require an open window design corresponding to the heat sink (that is, the assembly manner exemplified in the first implementation). When the heat dissipation surface is disposed on the surface of the bottom portion of the power device opposed from the top portion of the power device, the circuit board is provided with a cutout, and the pins may be soldered to the top surface of the circuit board by using reflow soldering. In this way, different power devices are packaged together in a variety of forms, which improves the flexibility of device arrangement. Refer toFIG.12. A power device20provided in a fifth implementation of this disclosure differs from the power device20provided in the first implementation in that a heat dissipation surface29includes two heat dissipation surface units290, and a gap2901between adjacent heat dissipation surface units290is filled with a molded package26. For example, when the surface of a heat dissipation substrate226opposed from a metal substrate222is used as the heat dissipation surface29, the heat dissipation substrate may be divided into two independent heat dissipation surface units290, that is, the heat dissipation surface29is divided into two independent heat dissipation surface units290. It can be understood that the number of heat dissipation surface units290is not limited, and there may be two or more heat dissipation surface units290. That is, the heat dissipation surface29includes at least two heat dissipation surface units290, and a gap2901between adjacent heat dissipation surface units290is filled with the molded package26. The heat dissipation surface29includes at least two heat dissipation surface units290, which can effectively reduce a risk that the heat dissipation surface29is easily damaged and fractured by force due to its excessively large area. In an implementation, the substrate structure includes the metal substrate but omits the heat dissipation substrate. The surface of the metal substrate opposed from the semiconductor die provides the heat dissipation surface. The surface of the metal substrate opposed from the semiconductor die may be divided into at least two heat dissipation surface units, to alleviate a risk that the heat dissipation surface is easily fractured by a mechanical stress due to its excessively large area. Refer toFIG.13. A power device provided in a sixth implementation of this disclosure differs from the power device provided in the first implementation in that a metal substrate222includes two mounting units2220, a gap is provided between the two mounting units2220, and the gap may be filled with a molded package26. In this implementation, in each mounting unit2220, there are two metal layers2224, and a thermally conductive insulation layer2222is sandwiched between the two metal layers2224. The surface of one of the metal layers2224in each mounting unit2220opposed from the thermally conductive insulation layer2222is provided with a semiconductor die24. The adjacent mounting units2220are insulated from each other by the molded package26, which helps improve the reliability of the power device. It can be understood that the number of mounting units2220may be set based on a function of the semiconductor die24and the like. The metal substrate222includes at least two mounting units2220and at least two semiconductor dies24, each mounting unit2220being provided with at least one semiconductor die24. This disclosure further provides an assembling method for a power device assembly100described above (in the first to the sixth implementations). The power device assembly100includes a power device20, a circuit board40, and a heat sink60. The power device20includes a package body201and a plurality of pins203. The package body201includes a substrate structure22, a semiconductor die24, and a molded package26. The substrate structure22includes a heat dissipation surface29. The molded package26covers the semiconductor die24and the substrate structure22excluding the heat dissipation surface29. A first end of each pin203is connected to the substrate structure22, a second end of each pin203and the heat dissipation surface29are uncovered from the molded package26. The second end of each pin203includes a mounting surface2031. The package body201is further provided with a through hole21extending through the substrate structure22and the molded package26, and an inner wall of the through hole21is covered with the molded package26. The circuit board40is provided with a cutout41. The heat sink60includes an assembling surface62provided with a connecting hole64. Referring toFIG.14, the assembling method includes the following steps: Step103: The mounting surface2031of the pin203is connected to the circuit board40. In this implementation, the mounting surface2031is connected to the circuit board40by using a reflow soldering process. Step105: The fastener70passes through the through hole21, the cutout41, and the connecting hole64, so that the heat dissipation surface29and the assembling surface62are connected. The package body201includes a bottom portion2011and a top portion2013that are disposed opposite each other, an orientation of the mounting surface2031is the same as an orientation of the bottom portion2011opposed from the top portion2013, and the heat dissipation surface29is disposed on the surface of the top portion2013opposed from the bottom portion2011. The fastener70passes through the through hole21, the cutout41, and the connecting hole64and successively passes through the cutout41, the through hole21, and the connecting hole64so that the circuit board40, the package body201, and the heat sink60are laminated to one another. The fastener70includes a rod72and a cap74connected to one end of the rod72. The fastener70successively passes through the cutout41, the through hole21, and the connecting hole64. The rod72passes through the cutout41, the through hole21, and the connecting hole64so that the circuit board40is sandwiched between the cap74and the surface of the package body201opposed from the heat sink60, and the cap74is disposed on the side of the circuit board40opposed from the package body201. Before the mounting surface2031of the pin203of the power device20is connected to the circuit board40, the assembling method further includes: providing a thermally conductive interface layer90between the heat dissipation surface29and the assembling surface62, where the thermally conductive interface layer90is formed with a mounting hole91extending through the thermally conductive interface layer90. The fastener70passes through the through hole21, the cutout41, and the connecting hole64passes through the mounting hole91. The thermally conductive interface layer90includes one of a nano copper hook-and-loop tape, a graphite thermal pad, a thermal grease layer, or a thermal gel. In an implementation, an orientation of the mounting surface2031is the same as an orientation of the bottom portion2011opposed from the top portion2013, and the heat dissipation surface29is disposed on the surface of the bottom portion2011opposed from the top portion2013. The fastener70passes through the through hole21, the cutout41, and the connecting hole64further includes: the heat sink60passes through the cutout41, and the fastener70successively passes through the through hole21and the connecting hole64, so that the package body201and the heat sink60are laminated. Referring toFIG.15, another assembling method is described for a power device assembly100. The assembling method includes the following steps: Step201: A thermally conductive interface layer90is provided between the heat dissipation surface29and the assembling surface62. Step203: The mounting surface2031of the pin203is connected to the circuit board40. Step205: The fastener70passes through and is connected to a washer80, the cutout41, the through hole21, a mounting hole91, and the connecting hole64successively, so that the washer80, the circuit board40, the package body201, the thermally conductive interface layer90, and the heat sink60are laminated to one another. The package body201includes a bottom portion2011and a top portion2013that are disposed opposite each other, an orientation of the mounting surface2031is the same as an orientation of the bottom portion2011opposed from the top portion2013, and the heat dissipation surface29is disposed on the surface of the top portion2013opposed from the bottom portion2011. The fastener70includes a rod72and a cap74connected to one end of the rod72. The diameter of the cutout41is adapted to the rod72. The washer80is sandwiched between the circuit board40and the cap74, and the cap74is disposed on the side of the washer80opposed from the circuit board40. In an implementation, the cutout41of the circuit board40has a relatively large diameter, the heat sink60passes through the cutout41, an orientation of the mounting surface2031is the same as an orientation of the bottom portion2011opposed from the top portion2013, and the heat dissipation surface29is disposed on the surface of the bottom portion2011opposed from the top portion2013. The washer80is sandwiched between the surface of the package body201opposed from the heat sink60and the cap74, and the cap74is disposed on the side of the washer80opposed from the package body201. The cap74, the washer80, the package body201, the thermally conductive interface layer90, and the heat sink60are laminated to one another. In an implementation, the thermally conductive interface layer90includes a nano copper hook-and-loop tape. Referring toFIG.16, the assembling method for the power device assembly100includes the following steps: Step301: A film layer is plated on the assembling surface62and where the film layer is a metal layer, the film layer is deoxidized. The metal layer includes at least one of nickel, copper, silver, gold, and palladium, and the material of the metal layer is not limited in this implementation of this disclosure. Step303: The heat dissipation surface29is deoxidized. Step305: The thermally conductive interface layer90is provided between the heat dissipation surface29and the assembling surface62, which includes: the nano copper hook-and-loop tape is provided between the heat dissipation surface29and the assembling surface62, and is cured to form the thermally conductive interface layer90, where the thermally conductive interface layer90is provided with a mounting hole91extending through the thermally conductive interface layer90. Step307: The mounting surface2031of the pin203is connected to the circuit board40. Step309: The fastener70passes through and is connected to the through hole21, the cutout41, the mounting hole91, and the connecting hole64, so that the power device20, the circuit board40, and the heat sink60are connected. In an implementation, the thermally conductive interface layer includes a graphite thermal pad. Referring toFIG.17, the assembling method for a power device assembly100includes the following steps: Step401: The graphite thermal pad is fabricated in advance to form the thermally conductive interface layer90, where the thermally conductive interface layer90is formed with a mounting hole91extending through the thermally conductive interface layer90. Step403: The thermally conductive interface layer90is provided between the heat dissipation surface29and the assembling surface62. Step405: The mounting surface2031of the pin203is connected to the circuit board40. Step407: The fastener70passes through and is connected to the through hole21, the cutout41, the mounting hole91, and the connecting hole64, so that the power device20, the circuit board40, and the heat sink60are connected. In an implementation, that the thermally conductive interface layer90is provided between the heat dissipation surface29and the assembling surface62includes: the assembling surface62is coated with a thermal grease or a thermal gel to form the thermally conductive interface layer90. It should be understood that the expressions that can be used in this disclosure, such as “include” and “may include”, indicate the existence of the disclosed functions, operations, or constituent elements, without limiting one or more additional functions, operations, and constituent elements. In this disclosure, the terms such as “include” and/or “have” can be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but cannot be interpreted as excluding the existence of one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof, or a possibility of addition. In addition, in this disclosure, the expression “and/or” includes any and all combinations of the associated terms listed. For example, the expression “A and/or B” may include A, or may include B, or may include both A and B. In this disclosure, the expressions including ordinal numbers such as “first” and “second” may modify various elements. However, the elements are not limited by the expressions. For example, the expressions do not limit the order and/or importance of the elements. The expressions are only used to distinguish an element from another element. For example, first user equipment and second user equipment represent different user equipment, although both the first user equipment and the second user equipment are user equipment. Similarly, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. When a component is described as “connected to” or “access” another component, it should be understood that the component may be directly connected to or access another component, but still another component may exist between the component and the other component. In addition, when a component is described as “directly connected to” or “directly access” another component, it should be understood that no other component exists between them. The foregoing descriptions are merely specific implementations of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this disclosure shall fall within the protection scope of the claims. Therefore, the protection scope of this disclosure shall be subject to the protection scope of the claims. | 48,732 |
11862532 | It will be understood that for clear illustrations,FIGS.1-13may not be drawn to scale. DETAILED DESCRIPTION The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. With the looming shortage of conventional radio frequency silicon on insulator (RFSOI) wafers expected in the coming years, alternative technologies are being devised to get around the need for high resistivity using silicon wafers, the trap rich layer formation, and Smart-Cut SOI wafer process. One of these alternative technologies is based on the use of a silicon germanium (SiGe) interfacial layer instead of a buried oxide layer (BOX) between a silicon substrate and a silicon epitaxial layer, however, which will also suffer from the deleterious distortion effects due to the silicon substrate, similar to what is observed in an RFSOI technology. The present disclosure, which relates to a radio frequency (RF) device with enhanced thermal and electrical performance, and a wafer-level packaging process for making the same, is based on this Si—SiGe—Si structure without deleterious distortion effects from the silicon substrate. FIG.1shows an exemplary RF device10formed from a Si—SiGe—Si wafer (processing details are described in following paragraphs) according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary RF device10includes a device region12, first bump structures14, a first mold compound16, and a second mold compound18. In detail, the device region12includes a front-end-of-line (FEOL) portion20and a back-end-of-line (BEOL) portion22underneath the FEOL portion20. In one embodiment, the FEOL portion20is configured to provide a switch field-effect transistor (FET), and includes an active layer24and a contact layer26. Herein, the active layer24has a source28, a drain30, and a channel32between the source28and the drain30. The source28, the drain30, and the channel32are formed from a same silicon epitaxial layer. The contact layer26is formed underneath the active layer24and includes a gate structure34, a source contact36, a drain contact38, and a gate contact40. The gate structure34may be formed of silicon oxide, and extends horizontally underneath the channel32(from underneath the source28to underneath the drain30). The source contact36is connected to and under the source28, the drain contact38is connected to and under the drain30, and the gate contact40is connected to and under the gate structure34. An insulating material42may be formed around the source contact36, the drain contact38, the gate structure34, and the gate contact40to electrically separate the source28, the drain30, and the gate structure34. In different applications, the FEOL portion20may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. In addition, the FEOL portion20also includes isolation sections44, which reside over the insulating material42of the contact layer26and surround the active layer24. The isolation sections44are configured to electrically separate the RF device10, especially the active layer24, from other devices formed in a common wafer (not shown). Herein, the isolation sections44may extend from a top surface of the contact layer26and vertically beyond a top surface of the active layer24to define an opening46that is within the isolation sections44and over the active layer24. The second mold compound18fills the opening46and may extend over the isolation sections44. The isolation sections44may be formed of silicon dioxide, which may resist etching chemistries such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH). In some applications, the RF device10may further include a passivation layer48, which is formed of silicon dioxide, silicon nitride, or combination of both, directly over the top surface of the active layer24and within the opening46. As such, the second mold compound18is directly over the passivation layer48. The passivation layer48is configured to terminate surface bonds of the active layer24, which may be responsible for unwanted leakage. The passivation layer may also serve as a barrier and is configured to protect the active layer24from moisture or ionic contamination. If the passivation layer48is omitted, the second mold compound18may be in contact with the top surface of the active layer24. In some applications, the RF device10may further include an interfacial layer (described in the following paragraphs and not shown herein), which is formed of SiGe, directly over the top surface of the active layer24and within the opening46. As such, the second mold compound18may be directly over the interfacial layer. The interfacial layer is from the Si—SiGe—Si wafer (processing details are described in following paragraphs), which is used to fabricate the RF device10. If the interfacial layer is omitted, the second mold compound18may be in contact with the top surface of the active layer24. Notice that, regardless of the passivation layer48or the interfacial layer, silicon crystal, which has no germanium content, does not exist between the second mold compound18and the top surface of the active layer24. Both the passivation layer48and the interfacial layer are silicon alloy. Further, in some applications, a top surface of each isolation section44and the top surface of the active layer24are coplanar (not shown), and the opening46is omitted. The second mold compound18resides over both the active layer24and the isolation sections44of the FEOL portion20. Note that the active layer24is never vertically beyond the isolation sections44. The BEOL portion22is underneath the FEOL portion20and includes multiple connecting layers50formed within dielectric layers52. The first bump structures14are formed at a bottom surface of the BEOL portion22, and electrically coupled to the FEOL portion20(the source contact36and the drain contact38in this illustration) via the connecting layers50of the BEOL portion22. The first mold compound16is formed underneath the BEOL portion22and encapsulates sides of each first bump structure14, such that a bottom portion of each first bump structure14is not covered by the first mold compound16. Herein, the first bump structures14do not protrude from a bottom surface of the first mold compound16. In some applications, it would be desirable to have protruding structures at the bottom surface of the RF device10to facilitate and improve the reliability of die attaching (to the printed circuit board) operations. Therefore, the RF device10may further include a number of second bump structures54. Each second bump structure54is in contact with a corresponding first bump structure14, and protrudes from the bottom surface of the first mold compound16. The first bump structures14may be solder balls or copper pillars. The second bump structures54may be formed from solder paste, conductive epoxy, or reflowable metals. The heat generated in the device region12may travel upward to a bottom portion of the second mold compound18, which is over the active layer24, and then will pass downward through the device region12and the first bump structures14, which will dissipate the heat. Further, the heat generated in the device region12may also travel directly through the first mold compound16to be conducted. It is therefore highly desirable to have high thermal conductivities of both the first and second mold compounds16and18. The first mold compound16and the second mold compound18may have a thermal conductivity greater than 1 W/m·K, or greater than 10 W/m·K. In addition, the first mold compound16and the second mold compound18may have a low dielectric constant less than 8, or between 3 and 5 to yield low RF coupling. The first mold compound16may be formed of a same or different material as the second mold compound18. In one embodiment, both the first mold compound16and the second mold compound18may be formed of thermoplastics or thermoset polymer materials, such as PPS (poly phenyl sulfide), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, or diamond-like thermal additives, or the like. Further, the first mold compound16may be transparent, and may have a thickness between 25 μm and 500 μm (based on the size of the first bump structure14). A thickness of the second mold compound18is based on the required thermal performance of the RF device10, the device layout, the distance from the first bump structures14, and as well as the specifics of the package and assembly. The second mold compound18may have a thickness between 200 μm and 500 μm. FIGS.2-13provide an exemplary wafer-level packaging process that illustrates steps to fabricate the exemplary RF device10shown inFIG.1. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated inFIGS.2-13. Initially, a Si—SiGe—Si wafer56is provided as illustrated inFIG.2. The Si—SiGe—Si wafer56includes a common silicon epitaxial layer58, a common interfacial layer60over the common silicon epitaxial layer58, and a silicon handle substrate62over the common interfacial layer60. Herein, the common interfacial layer60, which is formed of SiGe, separates the common silicon epitaxial layer58from the silicon handle substrate62. Herein, the common silicon epitaxial layer58is formed from a device grade silicon material, which has desired silicon epitaxy characteristics to form electronic devices. The common interfacial layer60is formed from an alloy with any molar ratio of Si and Ge. The higher the Ge concentration, the better the etch selectivity between the silicon handle substrate62and the common interfacial layer60, but also the more difficult the epitaxial growth of the common silicon epitaxial layer58becomes. In one embodiment, the common interfacial layer60may have a Ge concentration greater than 15% or greater than 25%. The Ge concentration may be uniform throughout the common interfacial layer60. In some applications, the Ge concentration may be vertically graded (between 1% and 50%) so as to yield the necessary strain relief for the growth of the common silicon epitaxial layer58. The silicon handle substrate62may consist of conventional low cost, low resistivity, and high dielectric constant silicon. The common silicon epitaxial layer58has higher resistivity than the silicon handle substrate62, and the common silicon epitaxial layer58has lower harmonic generation than the silicon handle substrate62. A thickness of the common silicon epitaxial layer58may be between 700 nm and 2000 nm, a thickness of the common interfacial layer60may be between 100 nm and 1000 nm, and a thickness of the silicon handle substrate62may be between 200 μm and 500 μm. Next, a complementary metal-oxide-semiconductor (CMOS) process is performed to the Si—SiGe—Si wafer56to provide a precursor wafer64with a number of device regions12, as illustrated inFIG.3A. For the purpose of this illustration, the FEOL portion20of each device region12is configured to provide a switch FET. In different applications, the FEOL portion20may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. In this embodiment, the isolation sections44of each device region12extend through the common silicon epitaxial layer58and the common interfacial layer60, and extend into the silicon handle substrate62. As such, the common interfacial layer60separates into a number of individual interfacial layers601, and the common silicon epitaxial layer58separates into a number of individual silicon epitaxial layers581, each of which is used to form a corresponding active layer24in one device region12. The top surface of the active layer24is in contact with a corresponding interfacial layer601. The silicon handle substrate62resides over each individual interfacial layer601, and portions of the silicon handle substrate62may reside over the isolation sections44. The BEOL portion22of the device region12, which includes at least the multiple connecting layers50and the dielectric layers52, is formed under the FEOL portion20. Bottom portions of certain connecting layers50are exposed through the dielectric layers52at the bottom surface of the BEOL portion22. In another embodiment, the isolation sections44do not extend into the silicon handle substrate62. Instead, the isolation sections44only extend through the common silicon epitaxial layer58and extend into the common interfacial layer60, as illustrated inFIG.3B. Herein, the common interfacial layer60remains continuous, and the individual interfacial layers601are connected with each other. The common interfacial layer60directly resides over the top surface of each active layer24, and directly resides over a top surface of each isolation section44. The silicon handle substrate62remains over the common interfacial layer60. Further, the isolation sections44may extend through the common silicon epitaxial layer58but do not extend into the common interfacial layer60. The top surface of each isolation section44and the top surface of each active layer24may be coplanar (not shown). The common interfacial layer60is over each isolation section44and each active layer24, and the silicon handle substrate62remains over the common interfacial layer60. The first bump structures14are then formed at the bottom surface of each BEOL portion22to provide a device wafer66, as depicted inFIG.4. A combination of the bottom surface of each BEOL portion22forms a bottom surface of the device wafer66. The device wafer66includes a number of device dies68, each of which further includes the first bump structures14compared to the device region12. Each first bump structure14is in contact with the exposed portion of a corresponding connecting layer50. Herein, the first bump structures14are electrically coupled to the FEOL portion20(the source contact36and the drain contact38in this illustration) via the connecting layers50of the BEOL portion22. The first bump structures14may be formed by a solder ball bumping technology or a copper pillar packaging technology. Each first bump structure14protrudes from the bottom surface of the BEOL portion22between 20 μm and 350 μm. Next, at least one window component70may be formed at the bottom surface of one BEOL portion22where the wafer mark(s) (not shown) is/are located, as illustrated inFIG.5. Herein, the wafer mark indicates the key location(s) of a wafer, which will be utilized for alignment in a following singulation and/or an assembly process. In one embodiment, the at least one window component70is located at the periphery of the bottom surface of the device wafer66. The at least one window component70may be formed of a transparent material (for instance: transparent silicone material), such that the wafer mark will be seen through the at least one window component70. In addition, at least one window component70may be formed of an easily removable material (for instance: acrylic polymer), such that the wafer mark will be seen after an easy removal of the at least one window component70(more details in following discussion). The at least one window component70has a height greater than each first bump structure14and is not connected to any first bump structure14. Notice that the at least one window component70is optional. In some applications, forming the at least one window component70at the bottom surface of one BEOL portion22may be omitted. The first mold compound16is applied over the bottom surface of the device wafer66and encapsulates each first bump structure14and the at least one window component70, as illustrated inFIG.6. The first mold compound16may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, or screen print encapsulation. The first mold compound16may have a superior thermal conductivity greater than 1 W/m·K, or greater than 10 W/m·K, and may have a dielectric constant less than 8, or between 3 and 5. The first mold compound16may have a thickness between 25 μm and 500 μm. The first mold compound16may resist etching chemistries such as KOH, NaOH, and ACH. In some applications, the first mold compound16may be formed of a transparent material. As such, there is no need to form the at least one window component70at the bottom surface of the BEOL portion22, because all locations of a wafer may be seen through the first mold compound16. A curing process (not shown) is then used to harden the first mold compound16. The curing temperature is between 100° C. and 320° C. depending on which material is used as the first mold compound16. After the first mold compound16is formed, the silicon handle substrate62is selectively removed to provide an etched wafer72, where the selective removal is stopped on each interfacial layer601, as illustrated inFIG.7. If the isolation sections44extend vertically beyond the interfacial layers601, the removal of the silicon handle substrate62will provide the opening46over each active layer24and within the isolation sections44. Removing the silicon handle substrate62may be provided by chemical mechanical grinding and an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, NaOH, ACH, or XeF2, or provided by the etching process itself. As an example, the silicon handle substrate62may be ground to a thinner thickness to reduce the following etching time. An etching process is then performed to completely remove the remaining silicon handle substrate62. Since the silicon handle substrate62and the interfacial layers601have different characteristics, they may have different reactions to a same etching technique (for instance: different etching speeds with a same etchant). Consequently, the etching system is capable of identifying the presence of the interfacial layers601, and capable of indicating when to stop the etching process. During the removal process, the isolation sections44are not removed and thus protect each FEOL portion20. The first mold compound16protects the bottom surface of each BEOL portion22. Herein, the top surface of each isolation section44and the top surface of each interfacial layer601are exposed after the removing process. If the isolation sections44extend into the common interfacial layer60(as shown inFIG.3B), or the top surface of each isolation section44and the top surface of each active layer24are coplanar (not shown), only the top surface of the common interfacial layer60will be exposed (not shown). Due to the narrow gap nature of the SiGe material, it is possible that the interfacial layers601(or the common interfacial layer60) may be conducting. The interfacial layer601may cause appreciable leakage between the source28and the drain30of the active layer24. Therefore, in some applications, such as FET applications, it is desired to also remove the interfacial layers601(or the common interfacial layer60), as illustrated inFIG.8. The interfacial layers601may be removed by the same etching process used to remove the silicon handle substrate62, or may be removed by another etching process, such as HCl dry etch systems. If the interfacial layer601is thin enough, it may be completely depleted and may not cause any appreciable leakage between the source28and the drain30of the FEOL portion20. In that case, the interfacial layers601may be left intact. In some applications, the passivation layer48, which may be formed of silicon dioxide, silicon nitride, or combination of both, may be formed directly over the active layer24of each FEOL portion20, as illustrated inFIG.9. If there is one opening46over each active layer24and within the isolation sections44, the passivation layer48is within the opening46. The passivation layer48is configured to terminate the surface bonds at the top surface of the active layer24, which may be responsible for unwanted leakage. The passivation layer48may be formed by CVD dielectric filming or passivating plasma. The second mold compound18is then applied over the etched wafer72as illustrated inFIG.10. Herein, the second mold compound18fills each opening46and is in contact with the passivation layer48within the opening46. In addition, portions of the second mold compound18may extend over the isolation sections44. If there is no passivation layer48formed in each opening46, the second mold compound18is in contact with the top surface of each active layer24(not shown). If the interfacial layer601remains over the top surface of each active layer24, the second mold compound18is in contact with the interfacial layer601(not shown). The second mold compound18always resides over each active layer24. The second mold compound18may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. During the molding process of the second mold compound18, the first mold compound16provides mechanical strength and rigidity to the etched wafer72. A curing process (not shown) is followed to harden the second mold compound18. The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound18. After the curing process, the second mold compound18may be thinned and/or planarized (not shown). Next, the first mold compound16is thinned to provide a mold device wafer74as illustrated inFIG.11. Herein, the first mold compound encapsulates sides of the each first bump structure14and the bottom portion of each first bump structure14is exposed. In addition, since the at least one window component70has a height greater than each first bump structure14, a bottom portion of the at least one window component70is also exposed through the first mold compound16. The thinning procedure may be done with a mechanical grinding process. In one embodiment, the at least one window component70may be formed of a transparent material, such that the wafer mark indicating the key location(s) of a wafer will be seen through the at least one window component70. In another embodiment, the at least one window component70may be formed of an opaque material, such that the wafer mark indicating the key location(s) of a wafer will not be seen through the at least one window component70. An extra step of removing the at least one window component70is needed to expose the wafer mark indicating the key location(s) of a wafer (not shown). Further, in some applications, the second bump structures54may be formed after the first mold compound16is thinned, as illustrated inFIG.12. Each second bump structure54is directly connected to a corresponding first bump structure14, electrically coupled to the corresponding FEOL portion20, and protrudes from the bottom surface of the first mold compound16. Finally, the mold device wafer74is singulated into individual RF devices10, as illustrated inFIG.13. The singulating step may be provided by a probing and dicing process at certain isolation sections44. The individual RF device10may be assembled on the PCB using a number of die attaching methods. Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow. | 27,481 |
11862533 | DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS The illustration in the drawing is schematically. Before describing further exemplary embodiments in further detail, some basic considerations of the present inventors will be summarized based on which exemplary embodiments have been developed which for an efficient cooling of a reliable package. According to an exemplary embodiment of the invention, a package, in particular a molded power module, is provided which is equipped with an efficient heat removal mechanism by direct fluid (in particular liquid) cooling without any risk of undesired penetration of cooling fluid into usually not waterproof encapsulant material. The demand for an increased compactness of packages in combination with the demand for package manufacturability with low effort brings conventional cooling concepts for removing energy generated during operation of a package to the limit. This particularly holds for molded power modules with Direct Copper Bonding (DCB) substrate used for removing heat from the encapsulated chip(s). A severe limitation is the high cost of DCB area of a package. This particularly holds for a double-sided cooling architecture where two such DCB substrates or other heat removal bodies are implemented. An exemplary embodiment of the invention provides a package with a direct cooling configuration using a heat removal body architecture (in particular implementing one or more DCBs), preferably but not necessarily in terms of double-sided cooling, which allows efficient removal of generated heat while safely preventing any undesired intrusion of cooling fluid into a mold-type encapsulant of the package. This can be accomplished by arranging a shielding layer at least on cooling fluid exposed surface portions of the encapsulant, i.e. spatial areas of the package external surface being not formed by the heat removal body or bodies and being in physical contact with the cooling fluid during operation. In order to prevent the cooling medium from diffusing or flowing into an interior of the package or power module, the sealing shielding layer may be arranged directly on the (for instance mold compound type) encapsulant material. Advantageously, the shaping of the encapsulate may be adjusted to provide a flow guidance so as to precisely define fluidic paths along which the cooling fluid can flow. In an embodiment, the shielding layer is a metal layer covering one or more surface portions of the encapsulant for preventing fluid communication of the cooling fluid up to the encapsulant. The shielding layer can be formed by sputtering, vapor deposition (in particular chemical vapor deposition (CVD)), melting at moderate temperature, using a laser, varnishing and/or plasma deposition. The material of the shielding layer may be an organic isolation material (such as parylene), an inorganic isolation material (such as a low-temperature glass) or a metallic layer (for instance titanium, nickel, aluminum, titanium/nickel, titanium/aluminum, titanium/aluminum/nickel, etc.). By taking these measures, the in many cases costly material of a heat removal body (in particular a ceramic material of a DCB) may be reduced in size, since even shielding layer covered surface portions of the encapsulant can be brought in direct contact with a liquid or gaseous cooling fluid. Moreover, one or more structures (such as indentations and/or protrusions) can be formed in the mold tool and can be manufactured without additional effort during encapsulation. Such structures are an indentation for an O-ring sealing, an indentation for cooling fluid flow path definition, etc. According to an exemplary embodiment, a package (in particular a power module) may be provided with a direct heat removal body (in particular DCB) cooling capability, wherein the area enclosed by a cooling body may be larger than the area of the heat removal body (and may be larger than the area of one or more electronic chips and/or of one or more optional spacer bodies). A thin shielding layer may be provided which shields or seals the region of the encapsulant (in particular mold body) exposed outside of the heat removal body with regard to the cooling fluid. Advantageously, the shielding layer may be corrosion resistant and/or waterproof and/or abrasion resistant and/or fissure bridging. The shielding layer may be composed of one or several sub-layers and may enclose cooling structures (such as cooling fins) on the heat removal body. The (preferably mold-type) encapsulant may be simultaneously used for structurally defining sealing areas and/or may provide for flow guidance. FIG.1shows a cross-sectional view of an electronic device150with a double-sided cooling package100according to an exemplary embodiment. The electronic device150is composed of a power package100and a two-piece cooling member152. The cooling member152is configured as a two-piece shell (i.e. comprising an upper shell and a lower shell between which the package100is sandwiched) for being mounted on the package100to thereby delimit, together with the package100, a cooling cavity154for temporarily accommodating flowing cooling fluid for cooling the package100. As can be taken fromFIG.1, the cooling member152is mounted on the package100for double-sided cooling of the package100by cooling fluid being thermally couplable with two opposing main surfaces of the package100. The package100according, toFIG.1comprises two electronic chips102which are here embodied as power semiconductor chips. The electronic chip102shown on the left hand side ofFIG.1may be a diode chip, whereas the electronic chip102shown on the right-hand side ofFIG.1may be an IGBT (Insulated Gate Bipolar Transistor) chip. A first heat removal body108, which is here embodied as Direct Copper Bonding (DCB) substrate, is thermally and mechanically coupled to a first main surface of the electronic chips102and forms part of an exterior surface of the package100. The first heat removal body108is configured for removing thermal energy from the electronic chips102during operation of the package100to cooling liquid (not shown, for instance water and/or an organic solvent such glycol) suppled the cooling cavity154between the package100and the package external cooling member152. The first heat removal body108comprises central electrically insulating and thermally conductive layer112, here made of ceramic material having a first main surface covered by a first electrically conductive layer114which is here embodied as a copper layer, and having an opposing second main surface covered by a second electrically conductive layer116, which is here embodied as a further copper layer. The electronic chips102are mounted and soldered on the first heat removal body108and may be electrically connected with the second electrically conductive layer116by bond wires (not shown). Hence, the first heat removal body108functions as a chip carrier and as a heat sink. The first electrically conductive layer114of the first heat removal body108forms part of an exterior surface of the package100and thereby significantly contributes to the heat removal from toe electronic chips102during operation of the package100. Optional spacer bodies130, which may be embodied as copper blocks, are soldered onto upper main surfaces of the electronic chips102. Moreover, a second heat removal body110is thermally coupled to a second main surface of the electronic chips102via the spacer bodies130. Also the second heat removal body110comprises a central electrically insulating and thermally conductive layer112, which may be made of a ceramic, having a first main surface covered by a first electrically conductive layer114, which is here embodied as a copper layer, and having an opposing second main surface covered by second electrically conductive layer116, which is here embodied as a further copper layer. The second electrically conductive layer116of the second heat removal body110is soldered onto the spacer bodies130. The first electrically conductive layer114of the second heat removal body110forms part of an exterior surface of the package100and thereby significantly contributes to the heat removal from the electronic chips102during operation of the package100. As a whole, the second heat removal body110is configured as a heat sink for removing thermal energy from the electronic chips102. Hence, the heat removal bodies108,110are both partially embedded in the package100and partially exposed. to the cooling cavity154. Furthermore, the heat removal bodies108,110and the cooling member152are free of a direct mutual contact. An electrically conductive contact structure118, here embodied as a leadframe, extends partially within and partially outside of the encapsulant104and may be electrically coupled with the electronic chips102for example via a connection with the second electrically conductive layer115of the first heat removal body108(for example via a solder connection, using bond wires, etc.). Furthermore, the package100comprises a mold-type encapsulate104encapsulating the electronic chips102, the spacer bodies130, only part of the electrically conductive contact structure118, only part of the first heat removal body108and only part of the second heat removal body110. The part of the electrically conductive contact structure118encapsulated by the encapsulant104serves for electrically contacting the electronic chips102, whereas another part of the electrically conductive contact structure118exposed from the encapsulant104provides one or more leads for connection with an electronic periphery device (not shown). Since the electrically conductive contact structure118extends partially within and partially outside of the encapsulant104and is electrically coupled with the electronic chips102, it is capable of providing an electric coupling between an exterior and an interior of the package100. As can be taken fromFIG.1, the package100may comprise one or more shielding lavers106covering several surface portions of the encapsulant101, which surface portions delimit part of the cooling cavity154. The encapsulant101is covered by the shielding layers106also surface regions directly adjacent to the first heat removal body108and to the second heat removal body110. The cooling cavity154can be denoted as the hollow volume through which a liquid cooling fluid can be guided for cooling the package100during operation. Apart from the shielding layers106, the cooling cavity154is also delimited by the cooling member152as well as by the exposed surfaces of the first heat removal body108and the second heat removal body110. The shielding layers106may be made of a metallic material such as nickel which is configured for shielding an interior of the package100with regard to cooling liquid, i.e. to provide a sealing barrier preventing the cooling liquid from ingressing the interior of the package100. In other words, the shielding layers106are impermeable for the cooling liquid such as water and thereby prevent that moisture enters the package100. Thus, undesired effects (such as delamination at package internal material interfaces, reduced electrical reliability, etc.) resulting from liquid entering in particular the encapsulant104can be safely prevented or strongly suppressed. Advantageously, the shielding layers106cover the mold-type encapsulant104which is specifically prone for being soaked with cooling liquid such as water. As a consequence of the provision of the shielding layers106covering the liquid sensitive encapsulant104, the size of the costly heat removal bodies108,110may be kept small, since also the locally shielded encapsulant104may contribute to delimiting of the cooling cavity154. Moreover, portions of the encapsulant104covered with the shielding layers106are provided with a structural feature159contributing to a cooling fluid related function More specifically, this structural feature159is a sealing groove for accommodating a sealing member156, embodied as O-ring, for promoting fluid-tightness of the cooling cavity152. A respective cooling fin body158is arranged on each of the first heat removal body108and the second heat removal bod110. The cooling fin bodies158may be thermally highly conductive structures (for instance made of aluminum) being shaped (for instance with a zig-zag shape as shown inFIG.1) so as to produce turbulent flow or vortex in the cooling liquid flowing along the cooling cavity154. This improves the heat exchange between the package100and the cooling fluid and thereby improves the heat removal capability. As can be taken fromFIG.1, further shielding layers106may cover an external surface of the cooling fin bodies158partly or entirely. This allows to prevent undesired electrochemical effects which may occur for example when the material of the cooling fin bodies158(for instance aluminum) and exposed material of the heat removal bodies108,110(for instance copper) differ. Still referring toFIG.1, additional shielding layers106may be provided to cover portions of a surface of the first heat removal body108and the second heat removal body110. Also this measure contributes to the suppression of undesired electrochemical effects which may occur from different uncovered metallic surfaces within the cooling cavity154. It should be understood that, although some of the shielding layers106only partly cover the respective surfaces (of the heat removal bodies108,110, of the cooling fin bodies158), it is alternatively also possible that their entire surfaces are covered by shielding layers106. Correspondingly, although the entire surfaces of the encapsulant104exposed within the cooling cavity154are covered by corresponding shielding layers106according toFIG.1, it is also possible in other embodiments that these shielding layer106cover the mentioned surfaces only partly. In particular the heat removal bodies108,110may be also completely uncovered from shielding layers106. FIG.2shows a cross-sectional view of an electronic device150with a double-sided cooling package100according to another exemplary embodiment. According toFIG.2, portions of the encapsulant104covered with the shielding layers106are provided with a further structural feature159contributing to a cooling fluid related function. More specifically, this additional structural feature159is a cooling fluid guiding structure or flow guiding structure for guiding the cooling fluid along a defined flow path for keeping the flow resistance small. Correspond the cooling member152comprises cooling medium supply channels160configured for supplying cooling medium to the cooling cavity154, and cooling medium drain channels162configured for draining cooling medium from the cooling cavity154. Arrows inFIG.2indicate the flow direction of cooling liquid. FIG.3shows a three-dimensional view of a preform of a double-sided cooling package100without metallization according to an exemplary embodiment. Thus,FIG.3shows a preform of package100after having partly embedded the heat removal bodies108,110and the electrically conductive contact structure118in the encapsulant104and prior to the formation of the shielding layer(s)106. FIG.4shows a three-dimensional view of double-sided cooling package100with metallization according to an exemplary embodiment. In order to obtain the package100shown inFIG.4from the preform shown inFIG.3, the illustrated metallic shielding layer106has been formed, for instance by chemical vapor deposition (CVD). FIG.5shows a schematic view of a vehicle170with an electronic device150comprising a package100according to an exemplary embodiment. More specifically, the power package100may form part of a control block192controlling operation of engine/battery block194. Hence, a package100or power module according to an exemplary embodiment of the invention may be used for an automotive application. A preferred application of such a power package100is an implementation as an inverter circuit or inverted rectifier for vehicle170which may be an electrically driven vehicle or which may be a hybrid vehicle. Such an inverter may transfer a direct current (DC) of the battery into an alternating current (AC) for driving the electric engine of vehicle170. In a hybrid vehicle, it is also possible to at least partially recover mechanical energy and to transfer it, by the inverter, back into electric energy to recharge the battery. In such an automotive inverter application, extreme amounts of heat are generated during operation of the power package100. This heat can be efficiently removed by the double-sided cooling concept described above. However, it should be said that, in other embodiments, also single-sided cooling may be sufficient. It should be noted that the term “comprising” does not exclude other elements or features and the “a” or “an” does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. | 17,495 |
11862534 | In the drawings: 1. housing; 2. fan assembly;21. fan body;22. fan bracket; 3. heatsink assembly;31. heatsink body;32. heatsink bracket; 4. semiconductor chilling plate; conduction cooling unit;51. main conduction cooling plate;52. conduction cooling fin;511. conduction cooling base;512. conduction cooling sheet;521. connecting shaft;5111. connecting groove;5112. limiting hole;5211. limiting slot;522. first conduction cooling sub-fin;523. second conduction cooling sub-fin;5231. hinge shaft; 6. circuit assembly. DETAILED DESCRIPTION OF THE EMBODIMENTS In order to explain the technical contents, the achieved purposes and effects of the present utility model in detail, the following description is given in conjunction with the embodiments and the accompanying drawings. Referring toFIG.1toFIG.11, the present utility model provides an adjustable heat exchanger, including a fan assembly, a heatsink assembly, a semiconductor chilling plate and a conduction cooling unit that are connected in sequence. The conduction cooling unit includes a main conduction cooling plate and a conduction cooling fin, and the conduction cooling fin includes at least one conduction cooling sub-fin; The main conduction cooling plate is connected to the semiconductor chilling plate, the conduction cooling fin is movably connected to an outer peripheral wall of the main conduction cooling plate, and the conduction cooling fin extends outward along a center of the main conduction cooling plate, and the conduction cooling fin and the main conduction cooling plate jointly form a contact surface for adapting to a heat-dispersing surface. It can be seen from the above description that the advantage of the present utility model is to provide the adjustable heat exchanger. Through adding the conduction cooling fin movably connected on the outer peripheral wall of the main conduction cooling plate, and by adjusting the angle at which the conduction cooling fin is connected to the main conduction cooling plate, the conduction cooling fin and the main conduction cooling plate can jointly form contact surfaces with various radians, as a result, the heat exchanger of the present utility model can adapt to hot surfaces with different curved surface radians, and forms a surrounded fixed structure with the hot surface, thereby arriving at a firm installation. Further, the conduction cooling fin includes over two conduction cooling sub-fins that are hinged end to end in sequence, and the conduction cooling sub-fin located at one end of the conduction cooling fin is movably connected to the outer peripheral wall of the main conduction cooling plate. It can be seen from the above description that the conduction cooling fin can be composed of multiple conduction cooling sub-fins hinged together, so that the overall length of the conduction cooling fin can be extended by increasing the number of the conduction cooling sub-fins, and the mutually hinged conduction cooling sub-fins enable an adjustment of the overall angle of the conduction cooling fin, thus achieving better adaptability. Further, a connecting groove is provided on the outer peripheral wall of the main conduction cooling plate; and one end of the conduction cooling fin is provided with a connecting shaft matching the connecting groove. It can be seen from the above description that the conduction cooling fin is hinged to the main conduction cooling plate by the assembly of the connecting shaft and the connecting groove, so that the conduction cooling fin can move relative to the main conduction cooling plate along the hinge axis direction, forming a surrounded fixation, and improving the stability of installation. Further, a side wall of the connecting groove is provided with a limiting hole, and a side wall of the connecting shaft is provided with a limiting slot matching the limiting hole at a position corresponding to the position of the limiting hole. The main conduction cooling plate is provided with a limiting shaft sequentially passing through the limiting hole and the limiting slot, and the axial direction of the limiting shaft is perpendicular to the axial direction of the connecting shaft. It can be seen from the above description that the connecting shaft can be prevented from moving axially to produce displacement by a limit between the connecting shaft and the connecting groove formed by the limiting shaft, thereby improving the stability of equipment installation. Further, the main conduction cooling plate includes a conduction cooling base and a conduction cooling sheet arranged on the conduction cooling base; The semiconductor chilling plate is connected to the conduction cooling sheet; The connecting groove is arranged on an outer peripheral wall of the conduction cooling base. It can be seen from the above description that the conduction cooling base is used to connect the conduction cooling fin and the hot surface, and the conduction cooling sheet is used to be connected to the semiconductor chilling plate. Further, the heatsink assembly includes a heatsink body and a heatsink bracket, and the heatsink bracket is connected to the conduction cooling base; The heatsink bracket is provided with a through hole matching the semiconductor chilling plate at a position corresponding to the position of the conduction cooling sheet, the semiconductor chilling plate is embedded in the through hole, and two end surfaces of the semiconductor chilling plate contact the heatsink body and the conduction cooling sheet, respectively. It can be seen from the above description that the semiconductor chilling plate is embedded in the through hole, and the two end surfaces of the semiconductor chilling plate respectively extend out of the through hole and are in contact with the heatsink body and the conduction cooling sheet, so as to realize a heat dissipation function. Further, the semiconductor chilling plate is a TEC semiconductor sheet. Referring toFIG.1toFIG.5, the first embodiment of the present utility model is to provide an adjustable heat exchanger, which can be used in electrical equipment, medical equipment, and experimental equipment and on human body surface to achieve functions of temperature control, heat dissipation adjustment and the like. The adjustable heat exchanger is arranged on a mounting surface of a hot surface, and the adjustable heat exchanger includes the housing1, and the fan assembly2, the heatsink assembly3, the semiconductor chilling plate4and the conduction cooling unit5that are respectively covered by and arranged inside the housing. The fan assembly, the heatsink assembly, the semiconductor chilling plate and the conduction cooling unit are connected in sequence from top to bottom. The conduction cooling unit includes the main conduction cooling plate51and any number of conduction cooling fins52, and the conduction cooling fins are movably connected to the outer peripheral wall of the main conduction cooling plate, respectively. Specifically, the main conduction cooling plate includes the conduction cooling base511and the conduction cooling sheet512arranged at the center of an upper end surface of the conduction cooling base, and the conduction cooling base and the conduction cooling sheet are integrally formed and connected. A surface of the conduction cooling base is rectangular. A lower end surface of the conduction cooling base is an arc-shaped surface concave inwardly that matches the mounting surface of the hot surface. Preferably, the lower end surface of the conduction cooling base is an arc-shaped surface having U-shaped cross section, and the concave arc adapts to the arc of the hot surface, so that relatively good assembly accuracy is achieved between the heat exchanger of the present utility model and the hot surface. In other embodiments, the surface of the conduction cooling base can also be rectangular, circular, or have other shapes. Two opposite outer peripheral walls of the conduction cooling base are each provided with the connecting groove5111, and the two connecting grooves are located at two opposite side walls of the U-shaped arc surface of the conduction cooling base. In the present embodiment, the number of the conduction cooling fins52is two, each conduction cooling fin includes one conduction cooling sub-fin, and the two conduction cooling fins are respectively connected to the two connecting grooves. Specifically, the conduction cooling fin is in a shape of an arc hook, one end of the conduction cooling fin is provided with the connecting shaft521matching the connecting groove, and the connecting shaft is inserted in the connecting groove to enable the conduction cooling fin to be movably hinged to the main conduction cooling plate. The axial direction of the connecting shaft is perpendicular to the central axis of the main conduction cooling plate, so that the conduction cooling fin can move in a circular motion along the up-down direction of the main conduction cooling plate around the axial direction of the connecting shaft. By adjusting the angle of each conduction cooling fin relative to the main conduction cooling plate, the two conduction cooling fins and the main conduction cooling plate can jointly form an angle-adjustable arc-shaped contact surface, thus being able to adapt to hot surfaces with different curved surface radians, and forming a surrounded fixed structure with the hot surface to achieve a firm installation. In the present embodiment, the center position of an upper side wall of the connecting groove is further provided with the limiting hole5112, and the limiting hole is preferably a screw hole. A side wall of the connecting shaft of the conduction cooling fin is provided with the limiting slot5211matching the limiting hole at a position corresponding to the position of the limiting hole. The main conduction cooling plate is provided with a limiting shaft sequentially passing through the limiting hole and the limiting slot, and the axial direction of the limiting shaft is perpendicular to the axial direction of the connecting shaft. Preferably, the limiting shaft is a screw, the screw is connected to the screw hole, and the threaded end of the screw is inserted into the limiting slot to form an axial limit, which prevents the conduction cooling fin from moving axially. In the present embodiment, the semiconductor chilling plate is a TEC semiconductor sheet. In the present embodiment, the fan assembly includes the fan body21and the fan bracket22, and the heatsink assembly includes the heatsink body31and the heatsink bracket32. The fan bracket is U-shaped, and the U shape of the fan bracket has an opening facing downward. The fan is arranged on an upper end surface of the fan bracket, and the upper end surface of the fan bracket is provided with vent holes at positions corresponding to the positions of blades of the fan body. A mounting base for mounting the control circuit assembly6is further provided on an outer peripheral side wall of the fan bracket. The central position of the heatsink bracket is provided with a rectangular through hole, and the semiconductor chilling plate is embedded in the through hole. The heatsink is arranged on an upper end surface of the heatsink bracket and contacts an upper end surface of the semiconductor cooling fin, and two side walls of the U shape of the fan bracket are connected to the heatsink bracket to enable the heatsink to be covered by and arranged inside the opening of the U shape of the fan bracket. A lower end surface of the heatsink bracket is connected to the conduction cooling base, and a lower end surface of the semiconductor cooling fin contacts the conduction cooling sheet on the conduction cooling base. In the present embodiment, one end of the housing has an opening, and the opening of the housing faces downward. A top of the housing is provided with a heat dissipation hole, and side walls of the housing corresponding to the opening of the housing are connected to the heatsink bracket. Referring toFIG.6toFIG.7, the second embodiment of the present utility model is as follows. The second embodiment differs from the first embodiment in that the structure of the conduction cooling fin is further improved. Specifically: The conduction cooling fin includes two conduction cooling sub-fins that are hinged end to end in sequence, and the conduction cooling sub-fin at one end of the conduction cooling fin is movably connected to the outer peripheral wall of the main conduction cooling plate. Preferably, each conduction cooling fin of the present embodiment includes two conduction cooling sub-fins hinged to each other, and the conduction cooling fin, from one end to the other end, sequentially includes the first conduction cooling sub-fin522and the second conduction cooling sub-fin523. The connecting shaft is arranged at one end of the first conduction cooling sub-fin and hinged to the connecting groove, the other end of the first conduction cooling sub-fin is provided with a hinge groove, one end of the second conduction cooling sub-fin is provided with the hinge shaft5231matching the hinge groove, and the other end of the second conduction cooling sub-fin is provided with a support foot contacting the hot surface. In other embodiments, the conduction cooling fin may also be composed of multiple conduction cooling sub-fins hinged together, so that the overall length of the conduction cooling fin can be extended by increasing the number of the conduction cooling sub-fins, and the mutually hinged conduction cooling sub-fins make the overall angle of the conduction cooling fin adjustable, resulting in better adaptability. Referring toFIG.8toFIG.9, the third embodiment of the present utility model is as follows. The third embodiment differs from the first embodiment in that the structure of the conduction cooling fin is further improved. Specifically: Only one conduction cooling fin52is provided, and the conduction cooling fin includes only one conduction cooling sub-fin. The single conduction cooling fin52is arranged on one side of the main conduction cooling plate51and is hinged to the main conduction cooling plate. The structure is relatively simple. Referring toFIG.10toFIG.11, the fourth embodiment of the present utility model is as follows. The fourth embodiment differs from the first embodiment in that the structure of the conduction cooling fin is further improved. Specifically: Four conduction cooling fins52are provided, and each of conduction cooling fins includes only one conduction cooling sub-fin. The four conduction cooling fins52are arranged surrounding the main conduction cooling plate51and are hinged to the main conduction cooling plate. The structure can be applied to a convex surface. In summary, the present utility model provides the adjustable heat exchanger. Through adding the conduction cooling fin movably connected on the outer peripheral wall of the main conduction cooling plate, and by adjusting the angle at which the conduction cooling fin is connected to the main conduction cooling plate, the conduction cooling fin and the main conduction cooling plate can jointly form arc-shaped contact surfaces with various radians, as a result, the heat exchanger of the present utility model can adapt to hot surfaces with different curved surface radians, and form a surrounded fixed structure with the hot surface, thereby arriving at a firm installation. The above descriptions are only the embodiments of the present utility model and do not limit the scope of the present utility model. Any equivalent transformation made based on the contents of the specification and drawings of the present utility model, or direct or indirect application in related technical fields, shall be regarded as falling within the protection scope of the present utility model. | 15,946 |
11862535 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Integrated circuits (IC) with image sensors are used in a wide range of modern day electronic devices, such as cell phones and computers, for example. Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) have become popular types of IC image sensors. Compared to charge-coupled devices (CCD), CIS have low power consumption, small size, fast data processing, a direct output of data, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated CMOS image sensors (FSI-CIS) and back-side illuminated CMOS image sensors (BSI-CIS). BSI-CIS comprise a plurality of interconnects arranged within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A plurality of micro-lenses are arranged along an opposing back-side of the substrate, which is configured to receive incident light. A bond pad may also be arranged along the back-side of the substrate. The bond pad is electrically coupled to the plurality of interconnects by way of a conductive through-substrate-via (TSV) that extends through the substrate. The TSV may be formed by performing a first etching process on the back-side of the substrate. The first etching process forms an intermediate TSV hole that extends through the substrate and that is defined by sidewalls of the substrate and a horizontally extending surface of the ILD structure. A dielectric liner is subsequently formed along the sidewalls of the substrate and the horizontally extending surface of the ILD structure. A second etching process is then performed to vertically etch through a horizontally extending surface of the dielectric liner and the ILD structure. The second etching process forms a TSV hole that exposes a first interconnect of the plurality of interconnects. A conductive material is subsequently formed in the TSV hole to define the TSV. It has been appreciated that in addition to etching the horizontally extending surface of the dielectric liner, the second etching process may also etch sidewalls of the dielectric liner, resulting in damage to the dielectric liner and/or sidewalls of the substrate. For example, the second etching process can thin or break-through the dielectric liner, so that the subsequently formed TSV is insufficiently insulated from the substrate, thereby decreasing a reliability of the integrated chip and/or leading to failure of the integrated chip. The present disclosure, in some embodiments, relates to an integrated chip having a through-substrate-via (TSV) with a reentrant profile that is configured to prevent damage to a dielectric liner. In some embodiments, the integrated chip is formed by performing a first etching process on a back-side of a substrate. The first etching process forms an intermediate TSV hole that extends through the substrate and that has a width that increases as a distance from the back-side of the substrate increases. A dielectric liner is formed on sidewalls of the substrate and a horizontally extending surface of an inter-level dielectric (ILD) structure (on a front-side of the substrate) that define the intermediate TSV hole. A second etching process is subsequently performed to form a TSV hole that exposes an interconnect within the ILD structure by etching through a horizontally extending surface of the dielectric liner and the ILD structure. Because a width of the intermediate TSV hole increases as a distance from the back-side of the substrate increases, sidewalls of the dielectric liner are laterally set back from an opening of the intermediate TSV hole along the back-side of the substrate. Laterally separating the sidewalls of the dielectric liner from the opening allows for the sidewall of the dielectric liner to be protected from an etchant of the second etching process and thereby mitigates damage to the dielectric liner and improves a reliability of the integrated chip. FIG.1illustrates a cross-sectional view of some embodiments of an integrated chip100having a through-substrate-via (TSV) with a reentrant profile. The integrated chip100comprises a substrate102having a first side102a(e.g., a front-side) and a second side102b(e.g., a back-side) opposing the first side102a.In some embodiments, one or more semiconductor devices104are disposed along or within the first side102aof the substrate102. In various embodiments, the one or more semiconductor devices104may comprise a transistor device (e.g., a MOSFET, a BJT, a FinFET, or the like), an image sensor device (e.g., a photodiode, a PIN photodiode, or the like), and/or the like. An inter-level dielectric (ILD) structure106is disposed on the first side102aof the substrate102. The ILD structure106surrounds a plurality of interconnects108. In some embodiments, the plurality of interconnects108may be coupled to the one or more semiconductor devices104. A conductive feature114is disposed within a dielectric structure116arranged along the second side102bof the substrate102. In various embodiments, the conductive feature114may comprise an interconnect, a redistribution layer, a bond pad, or the like. A TSV110extends through the substrate102and between one of the plurality of interconnects108and the conductive feature114. The TSV110comprises a conductive material, such as copper, aluminum, or the like. In some embodiments, the TSV110may comprise a back-side through-substrate-via (BTSV), which is formed by etching a TSV hole into the second side102b(e.g., a back-side) of the substrate102. The TSV110has a width that increases as a distance from the second side102bof the substrate102increases. For example, the TSV110may have a first width w1along the second side102bof the substrate102and a second width w2, which is larger than the first width w1, between the first side102aof the substrate102and the second side102bof the substrate102. In some embodiments, the TSV110further comprises a protrusion110pextending outward from a horizontally extending surface110hto one of the plurality of interconnects108. In such embodiments, the horizontally extending surface110his vertically between a first sidewall110s1and a second sidewall110s2of the TSV110. In some embodiments, the protrusion110pphysically contacts one of the plurality of interconnects108. The TSV110is separated from the substrate102by way of a dielectric liner112. The dielectric liner112extends along one or more sidewalls of the substrate102. In some embodiments, the dielectric liner112may continuously extend from the one or more sidewalls of the substrate102to over the second side102bof the substrate102. The dielectric liner112has sidewalls that are angled so that a distance between the sidewalls increases as a distance from the second side102bof the substrate102increases. The angle of the sidewalls causes the sidewalls to be laterally separated from outermost edges of a top surface of the TSV110facing the conductive feature114. For example, in some embodiments, outer edges of the top surface of the TSV110may be laterally separated from the sidewalls of the dielectric liner112by a distance d that is measured along a lateral direction that is parallel to the first side102aof the substrate102. In some embodiments, the distance d is between approximately 10 nm (nanometers) and approximately 200 nm, between approximately 25 nm and approximately 150 nm, or other similar values. Because the sidewalls of the dielectric liner112are separated (e.g., set back) from outermost edges of the top surface of the TSV110, the sidewalls of the dielectric liner112and/or substrate102overhang the TSV110. During fabrication of the integrated chip100, the overhang of the dielectric liner112and/or substrate102limits an amount of etchant that reaches sidewalls of the dielectric liner112. By limiting an amount of etchant that reaches sidewalls of the dielectric liner112, damage to the sidewalls of the dielectric liner112is mitigated and a reliability of the integrated chip100is improved. FIG.2illustrates a cross-sectional view of some additional embodiments of an integrated chip200having a TSV with a reentrant profile. The integrated chip200comprises a substrate102having a first side102aand a second side102bopposing the first side102a.In some embodiments, the substrate102may comprise or be a semiconductor substrate (e.g., a silicon substrate, a silicon wafer, or the like). A contact etch stop layer202is disposed along the first side102aof the substrate102. In some embodiments, an ILD structure106is disposed on the contact etch stop layer202. The ILD structure106may comprise a plurality of stacked ILD layers. A plurality of interconnects108are disposed within the ILD structure106. The plurality of interconnects108may comprise a middle-end-of-the-line (MOL) interconnect, a conductive contact, an interconnect wire, or an interconnect via. A dielectric layer204is disposed on the second side102bof the substrate102. In various embodiments, the dielectric layer204may comprise a nitride (e.g., silicon nitride, silicon oxynitride, etc.), an oxide (e.g., silicon oxide, etc.), or the like A TSV110extends through the substrate102, the dielectric layer204, the contact etch stop layer202, and the ILD structure106. A dielectric liner112is arranged between the TSV110and the substrate102. In some embodiments, the dielectric liner112further extends between the TSV110and the contact etch stop layer202and/or the dielectric layer204. In some embodiments, the dielectric liner112may continuously extend from along one or more sidewalls of the substrate102to over the dielectric layer204. In some embodiments, the dielectric liner112has a substantially constant thickness along the one or more sidewalls of the substrate102, the contact etch stop layer202, and/or the dielectric layer204. In some embodiments, the dielectric liner112may have a thickness in a range of between approximately 50 nanometers (nm) and approximately 150 nm, between approximately 50 nm and approximately 100 nm, between approximately 60 nm and approximately 80 nm, or other similar values. Having a dielectric liner112with a thickness of less than approximately 150 nm provides for the TSV110with a sufficient width to provide for a good electrical connection. The dielectric liner112has a first sidewall112s1and a second sidewall112s2facing the TSV110. A horizontally extending ledge112hprotrudes outward from the first sidewall112s1and towards the second sidewall112s2. The first sidewall112s1is angled so that the first sidewall112s1is separated from the horizontally extending ledge112hby a first angle θ measured through the TSV110. In various embodiments, the first angle θ is between approximately 80° and approximately 90°. In other embodiments, the first angle θ may be between approximately 85° and approximately 88°, between approximately 82° and approximately 86°, or other similar values. In some embodiments, an imaginary vertical line206that is perpendicular to the first side102aand/or the second side102bof the substrate102extends through the TSV110and through the dielectric liner112. The TSV110continuously extends between the first sidewall112s1and the second sidewall112s2of the dielectric liner112. Due to the angled orientation of the first sidewall112s1and the second sidewall112s2, the TSV110has a tapered shape that increases in width as a distance from the second side102bof the substrate102increases. For example, in some embodiments, the TSV110may have a top surface that faces away from the protrusion110pand that has a first width w1. In some embodiments, the TSV110may have a second width w2, which is larger than the first width w1, measured along the horizontally extending surface110h.In various embodiments, the second width w2may be between 120% and approximately 200% of the first width w1, between approximately 140% and approximately 180% of the first width w1, or other similar values. Having the second width w2greater than 120% of the first width w1provides for good protection of sidewalls of the dielectric liner112during fabrication of the integrated chip200. In various embodiments, the first width w1may be in a range of between approximately 1,000 nm and approximately 2,000 nm, between approximately 800 nm and approximately 1,500 nm or other similar values. In some embodiments, the TSV110comprises a first sidewall110s1between sidewalls of the substrate102and a second sidewall110s2between sidewalls of the ILD structure106. In some embodiments, the second sidewall110s2defines a protrusion110pextending outward from a horizontally extending surface110hof the TSV110to one of the plurality of interconnects108. In some embodiments, the first sidewall110s1may be angled so that a width of the TSV110defined by the first sidewall110s1increases as a distance from the horizontally extending surface110hdecreases, while the second sidewall110s2may be angled so that a width of the protrusion110pdecreases as a distance from the horizontally extending surface110hincreases. In some embodiments, the protrusion110pmay have a width wpthat is greater than or equal to the first width w1. In some such embodiments, the TSV110has a top surface and a bottom surface with widths that are smaller than a maximum width of the TSV110that is vertically between the top surface and the bottom surface. FIG.3illustrates a cross-sectional view of some additional embodiments of an integrated chip300having a TSV with a reentrant profile. The integrated chip300comprises a comprises a substrate102having one or more sidewalls extending between a first side102aof the substrate102and a second side102bof the substrate102opposing the first side102a.A dielectric liner112lines the one or more sidewalls of the substrate102. An etch blocking layer302is arranged on one or more sidewalls of the dielectric liner112. A TSV110extends through the substrate102to a plurality of interconnects108disposed within an ILD structure106on the first side102aof the substrate102. In some embodiments, an etch blocking layer remnant304may be disposed along a lower surface of the TSV110. In some embodiments, the etch blocking layer302may continuously extend along a height hBthat is less than a height hDof the dielectric liner112. In some embodiments, the etch blocking layer302has a bottom that is separated from a horizontally extending ledge112hof the dielectric liner112by a non-zero distance. In some embodiments, the etch blocking layer302may have a thickness that is in a range of between approximately 0.1 kÅ (kilo-Angstrom) and 1 kÅ, between approximately 0.5 kÅ (kilo-Angstrom) and 0.7 kÅ, or other similar values. In some embodiments, the etch blocking layer302has a thickness that varies over the height hBof the etch blocking layer302. In some embodiments, the etch blocking layer302may continuously extend from a sidewall of the dielectric liner112to along the second side102bof the substrate102. In some embodiments, the etch blocking layer302may comprise a curved corner facing the TSV110. In various embodiments, the etch blocking layer302may comprise a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), a carbide (e.g., silicon carbide), or the like. The etch blocking layer302is configured to decrease a width of the TSV110along the second side102bof the substrate102. By decreasing a width of the TSV110, the etch blocking layer302is able to further restrict an etchant used to form a TSV hole during fabrication of the integrated chip300. By further restricting an etchant used to form the TSV hole, a distance between a protrusion110pand sidewalls of the TSV110can be increased. For example, in some embodiments a top surface of the TSV110may have a first width w1′ that is in a range of between approximately 400 nm and approximately 600 nm, a horizontally extending surface of the TSV110may have a width whthat is in a range of between approximately 450 nm and approximately 650 nm, and the protrusion110pmay have a width wp′ that is in a range of between approximately 50 nm and approximately 100 nm. In some embodiments, the TSV110may comprise a first segment110adirectly between sidewalls of the etch blocking layer302, a second segment110bdirectly between sidewalls of the dielectric liner112, and a third segment110cdirectly between sidewalls of the ILD structure106. The first segment110amay have a sidewall oriented at a first slope, the second segment110bmay have a sidewall oriented at a second slope that is greater than the first slope, and the third segment110cmay have a third sidewall angled at a third slope that is greater than the second slope. In some embodiments, the first slope may be greater than the second slope. In some additional embodiments, the second slope may be greater than the first slope and/or the second slope. FIG.4illustrates a cross-sectional view of some additional embodiments of an integrated chip400having a TSV with a reentrant profile. The integrated chip400comprises a substrate102having one or more sidewalls extending between a first side102aof the substrate102and a second side102bof the substrate102opposing the first side102a.The one or more sidewalls are respectively defined by one or more curved depressions402(e.g., scallops, arcs) that are vertically separated from one another. A dielectric liner112lines the one or more sidewalls of the substrate102and fills the one or more curved depressions402. The dielectric liner112separates the substrate102from a TSV110extending through the substrate102. In some embodiments, the one or more curved depressions402along a first sidewall of the substrate102and the one or more curved depressions402along a second sidewall of the substrate102are separated by a lateral distance measured along a direction that is parallel to the first side102aor the second side102bof the substrate102. In some embodiments, a first lateral distance L1between a first pair of curved depressions and a second lateral distance L2between a second pair of curved depressions may be substantially equal. In other embodiments, the first lateral distance L1between the first pair of curved depressions may be smaller than the second lateral distance L2between the second pair of curved depressions. In some embodiments, a depth of the one or more curved depressions402may change (e.g., decrease) as a distance from the second side102bof the substrate102increases. In various embodiments, the reentrant profile of the disclosed TSV (e.g., TSV110ofFIG.1) may have different cross-sectional profiles.FIGS.5-6illustrate some non-limiting embodiments of exemplary profiles of a TSV having a reentrant profile. FIG.5illustrates a cross-sectional view of some additional embodiments of an integrated chip500having a TSV110arranged between sidewalls of a substrate102, a contact etch stop layer202, and an ILD structure106. The TSV110has sidewalls that are coupled to a horizontally extending surface110hby way of a curved corner that curves inward, so as to decrease a width of the TSV110along the curve. In some embodiments, the curved corner of the TSV110may be between sidewalls of the substrate102and sidewalls of the contact etch stop layer202. The TSV110has a first width waat a first depth d1below the second side102bof the substrate102, a second width wbat a second depth d2below the second side102b,and a third width wcat a third depth d3below the second side102b.In some embodiments, the second width wbis larger than the first width waand the third width wc. In some embodiments, the first width waand the second width wbmay be directly between sidewalls of the substrate102, while the third width wcmay be directly between sidewalls of the contact etch stop layer202. FIG.6illustrates a cross-sectional view of some additional embodiments of an integrated chip600having a TSV110arranged between sidewalls of a substrate102, a contact etch stop layer202, and an ILD structure106. The TSV110has a first width waat a first depth d1below the second side102bof the substrate102, a second width wbat a second depth d2below the second side102b,and a third width wcat a third depth d3below the second side102b.In some embodiments, the third width wcis larger than the first width waand the second width wb. In some embodiments, the first width waand the second width wbmay be directly between sidewalls of the substrate102, while the third width wcmay be directly between sidewalls of the contact etch stop layer202. FIG.7Aillustrates a cross-sectional view of some additional embodiments of an integrated chip700having a TSV with a reentrant profile. The integrated chip700comprises a transistor gate structure702arranged along a first side102a(e.g., a front-side) of a substrate102. The transistor gate structure702has a gate dielectric layer disposed along the first side102aof the substrate102and a gate electrode arranged on the gate dielectric layer. In some embodiments, sidewall spacers are arranged on opposing sides of the gate electrode. In some embodiments, the transistor gate structure702corresponds to a transfer transistor. In such embodiments, the transistor gate structure702is laterally arranged between a photodiode704and a floating diffusion well706. The photodiode704may comprise a first region within the substrate102having a first doping type (e.g., n-type doping) and an adjoining second region within the substrate102having a second doping type (e.g., p-type doping) that is different than the first doping type. The transistor gate structure702is configured to control a transfer of charge from the photodiode704to the floating diffusion well706. For example, as shown in an exemplary schematic diagram720ofFIG.7B, if a charge level is sufficiently high within the floating diffusion well706, a source-follower transistor722is activated and charges are selectively output according to operation of a row select transistor724used for addressing. A reset transistor726is configured to reset the photodiode704between exposure periods. Referring again toFIG.7A, an ILD structure106is arranged along the first side102aof the substrate102. The ILD structure106comprises a plurality of stacked inter-level dielectric (ILD) layers106a-106c.In various embodiments, the plurality of stacked ILD layers106a-106cmay comprise one or more of silicon dioxide, silicon nitride, carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, or the like. The ILD structure106surrounds a plurality of interconnects108electrically coupled to the transistor gate structure702. In some embodiments, a first passivation layer710is disposed along a second side102b(e.g., a back-side) of the substrate102opposing the first side102a.In some embodiments, one or more redistribution layers (RDLs)712are disposed on the first passivation layer710. The one or more RDLs712may comprise a vertical component (e.g., a redistribution via) that extends through an opening in the first passivation layer710and a lateral component (e.g., a redistribution wire) that extends over the first passivation layer710. The lateral component re-distributes electrical signals to different areas along the second side102bof the substrate102, thereby enabling compatibility with different packaging options. In some embodiments, the one or more RDLs712may be arranged over a bond pad708disposed below the first passivation layer710. A second passivation layer714is arranged over the one or more RDL712. In some embodiments, an under bump metallurgy (UBM) structure716extends through the second passivation layer714to contact the one or more RDLs712. The UBM structure716serves as a solderable interface between the one or more RDLs712and a conductive bump718(e.g., a solder bump). In some embodiments, the UBM structure716comprises a stack of different metal layers,716aand716b,which serve as a diffusion layer, a barrier layer, a wetting layer, and/or an anti-oxidation layer. In various embodiments, the conductive bump718may comprise a solder bump, a copper bump, a metal bump including nickel (Ni) or gold (Au), or combinations thereof. FIGS.8-16illustrate cross-sectional views800-1600of some embodiments of a method of forming an integrated chip having a TSV with a reentrant profile. AlthoughFIGS.8-16are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.8-16are not limited to such a method, but instead may stand alone as structures independent of the method. As shown in cross-sectional view800ofFIG.8, a substrate102is provided. The substrate102comprises a first side102aand a second side102bopposing the first side102a.In some embodiments, one or more semiconductor devices104are formed on or within the first side102aof the substrate102. In various embodiments, the one or more semiconductor devices104may comprise a transistor device, an image sensor device, and/or the like. In some embodiments, a contact etch stop layer202is formed on the first side102aof the substrate102. The contact etch stop layer202may comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. A plurality of interconnects108may be formed within an inter-level dielectric (ILD) structure106formed on the contact etch stop layer202. In some embodiments, the plurality of interconnects108may respectively be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming an ILD layer on the first side102aof the substrate102, etching the ILD layer to form a via hole and/or a trench, and filling the via hole and/or the trench with a conductive material. In some embodiments, the ILD layer may be deposited by a deposition process (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PE-CVD) process, an atomic layer deposition (ALD) process, etc.) and the conductive material (e.g., tungsten, copper, aluminum, or the like) may be formed using a deposition process and/or a plating process (e.g., electroplating, electro-less plating, etc.). As shown in cross-sectional view900ofFIG.9, a dielectric layer204is formed on a second side102bof the substrate102opposing the first side102aof the substrate102. In some embodiments, the dielectric layer204may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like. In some embodiments, the dielectric layer204may be formed by way of a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, an ALD process, etc.). A masking layer902is formed over the dielectric layer204. The masking layer902comprises one or more sidewalls defining an opening904exposing a part of the dielectric layer204. In some embodiments, the masking layer902may comprise a photosensitive material (e.g., a photoresist). In such embodiments, the masking layer902may be formed by way of a spin-on process. As shown in cross-sectional view1000ofFIG.10, a first etching process is performed to pattern the dielectric layer204and the substrate102according to the masking layer902. The first etching process forms sidewalls of the substrate102that extend through the substrate102and that define a first TSV opening1002(i.e., an intermediate TSV hole). In some embodiments, the first TSV opening1002also extends through the contact etch stop layer202to expose the ILD structure106. The sidewalls of the substrate102are angled to give the first TSV opening1002a reentrant profile that increases in width as a distance from the second side102bof the substrate102increases. For example, the first TSV opening1002has an upper width wualong the second side102bof the substrate102and a lower width wL, which is larger than the upper width wu, along the first side102aof the substrate102. In some embodiments, the first etching process is performed by exposing the substrate102to a first etchant1004according to the masking layer902. In some embodiments, the first etchant1004may comprise a plasma etchant having a fluorine based etching chemistry (e.g., a SF6plasma, or the like). In some embodiments, a DC self-bias may be increased as a depth of the first etching process increases. For example, in some embodiments, the DC self-bias may increase from approximately 100V to approximately 150V as a depth of the first etching process increases. Increasing the DC self-bias increases an etching rate of the first etchant1004and a width of the first TSV opening1002. As shown in cross-sectional view1100ofFIG.11, a dielectric liner112is formed along surfaces of the substrate102, the dielectric layer204, and/or the ILD structure106, which define the first TSV opening1002. The dielectric liner112continuously extends from a first sidewall of the substrate102to an opposing second sidewall of the substrate102as viewed along cross-sectional view1100. In some embodiments, the dielectric liner112may comprise an oxide (e.g., silicon oxide), a carbide (e.g., silicon carbide), or the like. In some embodiments, the dielectric liner112may be formed by way of a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, an ALD process, etc.). As shown in cross-sectional view1200ofFIG.12, an etch blocking layer302is formed on the dielectric liner112. The etch blocking layer302may be formed along sidewalls of the dielectric liner112and on an upper surface of the dielectric liner112facing away from the substrate102. The etch blocking layer302has sidewalls that define an opening1202over the first TSV opening1002. In some embodiments, the etch blocking layer302may further be formed on a horizontally extending surface1204of the dielectric liner112that is within the first TSV opening1002. In some embodiments, the etch blocking layer302covers a part, but not all, of the sidewalls of the dielectric liner112. In such embodiments, the etch blocking layer302continuously extends along a smaller height than the dielectric liner112. In some embodiments, the etch blocking layer302may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. In various embodiments, the etch blocking layer302may be formed by way of a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, an ALD process, etc.). In some embodiments, the etch blocking layer302may be formed to a thickness that is in a range of between approximately 1 kÅ and approximately 2 kÅ. As shown in cross-sectional view1300ofFIG.13, the etch blocking layer302is selectively removed from the horizontally extending surface1204of the dielectric liner112within the first TSV opening1002. In some embodiments, the etch blocking layer302may be removed by exposing the etch blocking layer302to a removal etchant1302. In some embodiments, the removal etchant1302may comprise a dry etchant (e.g., having a chlorine based etching chemistry and/or a fluorine based etching chemistry). In some embodiments, a masking layer (not shown) may be formed onto the dielectric liner112in areas outside of the first TSV opening1002prior to exposing the etch blocking layer302to the removal etchant1302. In some embodiments, the masking layer may comprise a photosensitive material (e.g., a photoresist). In some embodiments, the removal etchant1302may reduce a thickness of the etch blocking layer302along sidewalls of the dielectric liner112. For example, in some embodiments, the removal etchant1302may reduce a thickness of the etch blocking layer302by between approximately 50% and approximately 75%. In some embodiments, the etch blocking layer302may have a thickness of between approximately 0.5 kÅ and approximately 0.7 kÅ after being removed from the horizontally extending surface of the dielectric liner112. In some embodiments (not shown), the removal etchant1302may leave remnants of the etch blocking layer302along outer edges of the horizontally extending surface1204of the dielectric liner112. As shown in cross-sectional view1400ofFIG.14, a second etching process is performed to selectively etch the dielectric liner112and the ILD structure106according to the etch blocking layer302. The second etching process defines a TSV hole1406(comprising the first TSV opening (1002ofFIG.13) and a second TSV opening1404) that exposes one of the plurality of interconnects108. In some embodiments, the second etching process exposes the dielectric liner112and the ILD structure106to a second etchant1402according to the opening1202defined by the etch blocking layer302. In some embodiments, the second etchant1402is a different etchant than the first etchant (1004ofFIG.10). In some embodiments, the second etchant1402is an anisotropic etchant (e.g., a dry etchant). Because of the reentrant profile of the first TSV opening (1002ofFIG.13), the dielectric liner112and/or the substrate102overlies a part of the dielectric liner112and thereby mitigates an amount of the second etchant1402that reaches sidewalls of the dielectric liner112. By mitigating an amount of the second etchant1402that reaches sidewalls of the dielectric liner112, damage to the sidewalls of the dielectric liner112can be reduced. Furthermore, because an amount of the second etchant1402that reaches the sidewalls of the dielectric liner112is mitigated, the second etchant1402forms a second TSV opening1404that extends through the dielectric liner112at a position that is separated from the sidewalls of the dielectric liner112by a non-zero distance d. The second TSV opening1404exposes a first interconnect of the plurality of interconnects108. After the second etching process is completed, the dielectric liner112has a horizontally extending ledge112h.In some embodiments, the second TSV opening1404may have a width w2that is greater than or equal to a distance dBbetween sidewalls of the etch blocking layer302defining the opening1202. As shown in cross-sectional view1500ofFIG.15, a conductive material is formed within the TSV hole1406. The conductive material may be formed by way of a deposition process and/or a plating process (e.g., electroplating, electro-less plating, etc.). In various embodiments, the conductive material may comprise copper, aluminum, or the like. After forming the conductive material within the TSV hole1406, a planarization process may be performed (along line1502) to remove excess of the conductive material from over the etch blocking layer302and to define a through-substrate-via (TSV)110extending through the substrate102. In some embodiments (not shown), the planarization process may further remove the etch blocking layer302and/or the dielectric liner112from over the substrate102. In other embodiments, the etch blocking layer302and/or the dielectric liner112may remain over the substrate102after the planarization process is completed. In some embodiments, the planarization process may comprise a chemical mechanical polishing (CMP) process. In other embodiments, the planarization process may comprise an etching process and/or a grinding process, for example. As shown in cross-sectional view1600ofFIG.16, a bond pad708is formed over the TSV110. A first passivation layer710may be formed over the bond pad708. One or more redistribution layers (RDLs)712are formed over the first passivation layer710. In some embodiments, the one or more RDLs712may be formed by etching the first passivation layer710to expose the bond pad708, and forming a second conductive material over the first passivation layer710. A second passivation layer714is formed over the first passivation layer710. The second passivation layer714is subsequently etched to form an under bump metallurgy (UBM) opening1602that exposes the one or more RDLs712. An under bump metallurgy (UBM) structure716is formed within the UBM opening1602. The UBM structure716comprises a stack of different metal layers,716aand716b,which serve as a diffusion layer, a barrier layer, a wetting layer, and/or an anti-oxidation layer. The UBM structure716may be formed by successive deposition processes. A conductive bump718is formed on the UBM structure716. In various embodiments, the conductive bump718may comprise a solder bump, a copper bump, a metal bump including nickel (Ni) or gold (Au), or combinations thereof. FIGS.17-24illustrate cross-sectional views1700-2400of some additional embodiments of a method of forming an integrated chip having a TSV with a reentrant profile. AlthoughFIGS.17-24are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.17-24are not limited to such a method, but instead may stand alone as structures independent of the method. As shown in cross-sectional view1700ofFIG.17, one or more semiconductor devices104(e.g., a transistor device, an image sensor device, and/or the like) are formed on and/or within a first side102aof a substrate102. In some embodiments, a contact etch stop layer202is formed on the first side102aof the substrate102. A plurality of interconnects108may be formed within an ILD structure106formed on the contact etch stop layer202. As shown in cross-sectional view1800ofFIG.18, a dielectric layer204is formed on a second side102bof the substrate102opposing the first side102aof the substrate102. A masking layer902is formed over the dielectric layer204. The masking layer902comprises one or more sidewalls defining an opening904exposing a part of the dielectric layer204. As shown in cross-sectional views1900-1912ofFIGS.19A-19E, a first etching process is performed to pattern the dielectric layer204and the substrate102according to the masking layer902. The first etching process forms sidewalls defining a first TSV opening1916(i.e., an intermediate TSV hole) extending through the substrate102. In some embodiments, the first TSV opening1916also extends through the contact etch stop layer202to expose the ILD structure106arranged along the first side102aof the substrate102. The sidewalls are angled to give the first TSV opening1916a reentrant profile that increases in width as a distance from the second side102bof the substrate102increases. In some embodiments, the first etching process may comprise a multi-step dry etch process (e.g., a Bosch etch process). The multi-step dry etch process comprises a plurality of cycles that respectively perform steps of exposing the substrate102to a first etchant1902to form a curved depression402within the substrate102and then subsequently forming a protective layer1908on the substrate102. Each of the plurality of cycles forms a curved depression402within a sidewall of the substrate102. In some embodiments, within a cycle a first gas may be introduced into a processing chamber to perform an etch during a first time period, the processing chamber may be purged, and then a second gas species may be in-situ (i.e., without breaking a vacuum) introduced into the process chamber to form the protective layer1908during a subsequent time period. For example, during a first cycle, shown in cross-sectional view1900ofFIG.19A, a first etchant1902is brought into contact with the substrate102to form a cavity1904having a first pair of curved depressions402awithin opposing sidewalls of the substrate102. In some embodiments, the first pair of curved depressions402aare separated by a first lateral distance L1. After forming the first pair of curved depressions402a,a protective layer1908is formed onto interior surfaces of the substrate102defining the cavity1904, as shown in cross-sectional view1906ofFIG.19B. During a second cycle, shown in cross-sectional view1910ofFIG.19C, the first etchant1902is re-introduced into the cavity1904to form a second pair of curved depressions402bwithin opposing sidewalls of the substrate102. In some embodiments, the second pair of curved depressions402bare separated by a second lateral distance L2. After forming the second pair of curved depressions402b,the protective layer1908is formed onto interior surfaces of the substrate102defining the cavity1904, as shown in cross-sectional view1912ofFIG.19D. Cross-sectional view1914ofFIG.19Eillustrates the first TSV opening1916after the first etching process is complete. The first TSV opening1916extends through the substrate102and the contact etch stop layer202to expose the ILD structure106. In some embodiments, the first etchant1902may comprise a dry etchant having an etching chemistry comprising tetrafluoromethane (CF4), sulfur hexafluoride (SF6), and/or nitrogen trifluoride (NF3), for example. In some embodiments, the protective layer1908may be formed by exposing the substrate102to a polymer gas (e.g., C4F8). In some embodiments, respective cycles of the first etching process may last for a time of between 0.05 seconds and 0.3 seconds. In some embodiments, a ratio between a time of an etch and a time of a deposition of the protective layer1908within a cycle may be between approximately 2 and approximately 3 to form the first TSV opening1916with the reentrant profile. For example, in some embodiments, an etch portion of a cycle may last for approximately 0.2 second and a deposition portion of the cycle may last for approximately 0.1 second. In some embodiments, a DC self-bias of the first etching process may be increased as a depth of the etch increases. For example, in some embodiments, the DC self-bias may increase from approximately 100V to approximately 150V as a depth of the first etching process increases. In some embodiments, once the first etching process is completed, the protective layer1908is removed from within the first TSV opening1916. In some embodiments, the protective layer1908may be removed by exposing the protective layer1908to a wet etchant. In some embodiments, the wet etchant may comprise a diluted hydrofluoric acid, potassium hydroxide, or the like. As shown in cross-sectional view2000ofFIG.20, a dielectric liner112is formed along surfaces defining the first TSV opening1916. For example, the dielectric liner112may be formed along sidewalls of the substrate102, the dielectric layer204, and/or on the ILD structure106. As shown in cross-sectional view2100ofFIG.21, an etch blocking layer302is formed on the dielectric liner112. The etch blocking layer302may be formed along sidewalls of the dielectric liner112and on an upper surface of the dielectric liner112facing away from the substrate102. The etch blocking layer302has sidewalls that define an opening2102over the first TSV opening1916. In some embodiments (not shown), the etch blocking layer302may further be formed on a horizontally extending surface2104of the dielectric liner112that is within the first TSV opening1916. In such embodiments, the etch blocking layer302is subsequently removed from the horizontally extending surface2104of the dielectric liner112within the first TSV opening1916. As shown in cross-sectional view2200ofFIG.22, a second etching process is performed to selectively etch the dielectric liner112and the ILD structure106according to the opening2102defined by the sidewalls of the etch blocking layer302. The second etching process defines a TSV hole2206(comprising the first TSV opening (1916ofFIG.21) and a second TSV opening2204) that exposes one of the plurality of interconnects108. In some embodiments, the second etching process exposes the dielectric liner112and the ILD structure106to a second etchant2202according to the opening2102defined by the etch blocking layer302. Because of the reentrant profile of the first TSV opening (1916ofFIG.21), the dielectric liner112and/or the substrate102overlies a part of the dielectric liner112and thereby mitigates an amount of the second etchant2202that reaches and damages sidewalls of the dielectric liner112. Furthermore, because an amount of the second etchant2202that reaches sidewalls of the dielectric liner112is mitigated, the second etchant2202forms a second TSV opening2204that extends through the dielectric liner112at a position that is separated from the sidewalls of the dielectric liner112by a non-zero distance d. The second TSV opening2204exposes a first interconnect of the plurality of interconnects108. As shown in cross-sectional view2300ofFIG.23, a conductive material is formed within the TSV hole2206. After forming the conductive material, a planarization process may be performed (along line1502) to remove excess of the conductive material from over the etch blocking layer302and to define a through-substrate-via (TSV)110extending through the substrate102. As shown in cross-sectional view2400ofFIG.24, a bond pad708is formed over the TSV110. A first passivation layer710may be formed over the bond pad708. One or more RDLs712are formed over the first passivation layer710. In some embodiments, the one or more RDLs712may be formed by etching the first passivation layer710to expose the bond pad708, and forming a second conductive material over the first passivation layer710. A second passivation layer714is formed over the first passivation layer710. The second passivation layer714is subsequently etched to form an UBM opening1602that exposes the one or more RDLs712. An UBM structure716is formed within the UBM opening1602. FIGS.25-32illustrate cross-sectional views2500-3200of some additional embodiments of a method of forming an integrated chip having a TSV with a reentrant profile. AlthoughFIGS.25-32are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.25-32are not limited to such a method, but instead may stand alone as structures independent of the method. As shown in cross-sectional view2500ofFIG.25, one or more semiconductor devices104(e.g., a transistor device, an image sensor device, and/or the like) are formed on and/or within a first side102aof a substrate102. In some embodiments, a contact etch stop layer202is formed on the first side102aof the substrate102. A plurality of interconnects108may be formed within an ILD structure106formed on the contact etch stop layer202. As shown in cross-sectional view2600ofFIG.26, a dielectric layer204is formed on a second side102bof the substrate102opposing the first side102aof the substrate102. A masking layer902is formed over the dielectric layer204. The masking layer902comprises one or more sidewalls defining an opening904exposing a part of the dielectric layer204. As shown in cross-sectional view2700ofFIG.27, a first etching process is performed to pattern the dielectric layer204and the substrate102according to the masking layer902. The first etching process forms sidewalls of the substrate102that extend through the substrate and that define a first TSV opening2702(i.e., an intermediate TSV hole) extending through the substrate102. In some embodiments, the first TSV opening2702also extends through the contact etch stop layer202to expose the ILD structure106arranged along the first side102aof the substrate102. The sidewalls are angled to give the first TSV opening2702a reentrant profile that increases in width as a distance from the second side102bof the substrate102increases. In some embodiments, the first etching process is performed by exposing the substrate102to a first etchant2704according to the masking layer902. As shown in cross-sectional view2800ofFIG.28, a dielectric liner112is formed along surfaces defining the first TSV opening2702. For example, the dielectric liner112may be formed along sidewalls of the substrate102, the dielectric layer204, and/or the ILD structure106. As shown in cross-sectional view2900ofFIG.29, an etch blocking layer2902is formed on the dielectric liner112. The etch blocking layer2902may be formed along sidewalls of the dielectric liner112and on an upper surface of the dielectric liner112facing away from the substrate102. In some embodiments, the etch blocking layer2902may comprise a photosensitive material. In some embodiments, the photosensitive material may be selectively patterned to define an opening2904that exposes a horizontally extending surface of the dielectric liner112that is within the first TSV opening2702. As shown in cross-sectional view3000ofFIG.30, a second etching process is performed to selectively etch the dielectric liner112and the ILD structure106according to the etch blocking layer2902. The second etching process defines a TSV hole3006(comprising the first TSV opening (2702ofFIG.29) and a second TSV opening3004) that exposes one of the plurality of interconnects108. In some embodiments, the second etching process exposes the dielectric liner112and the ILD structure106to a second etchant3002according to the etch blocking layer2902. The etch blocking layer2902is removed after the second etching process is completed. In some embodiments, the etch blocking layer2902may be removed by a plasma ashing process. Because of the reentrant profile of the first TSV opening (2702ofFIG.29), the dielectric liner112and/or the substrate102overlies a part of the dielectric liner112and thereby prevent the second etchant3002from reaching the dielectric liner112. Because the second etchant3002is not able to reach sidewall of the dielectric liner112, the second etchant3002forms a second TSV opening3004that extends through the dielectric liner112at a position that is separated from sidewalls of the dielectric liner112by a non-zero distance d. The second TSV opening3004exposes a first interconnect of the plurality of interconnects108. As shown in cross-sectional view3100ofFIG.31, a conductive material is formed within the TSV hole3006. After forming the conductive material, a planarization process may be performed (along line1502) to remove excess of the conductive material from over the dielectric liner112and to define a through-substrate-via (TSV)110extending through the substrate102. As shown in cross-sectional view3200ofFIG.32, a bond pad708is formed over the TSV110. A first passivation layer710may be formed over the bond pad708. One or more RDLs712are formed over the first passivation layer710. In some embodiments, the one or more RDLs712may be formed by etching the first passivation layer710to expose the bond pad708, and forming a second conductive material over the first passivation layer710. A second passivation layer714is formed over the first passivation layer710. The second passivation layer714is subsequently etched to form an UBM opening1602that exposes the one or more RDLs712. An UBM structure716is formed within the UBM opening1602. FIG.33illustrates a flow diagram of some embodiments of a method3300of forming an integrated chip having a TSV with a reentrant profile. While the disclosed method3300is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At act3302, one or more semiconductor devices are formed on or within a first side of a substrate.FIG.8illustrates a cross-sectional view800of some embodiments corresponding to act3302.FIG.17illustrates a cross-sectional view1700of some alternative embodiments corresponding to act3302.FIG.25illustrates a cross-sectional view2500of some alternative embodiments corresponding to act3302. At act3304, a plurality of interconnects are formed within an inter-level dielectric (ILD) structure formed on the first side of the substrate.FIG.8illustrates a cross-sectional view800of some embodiments corresponding to act3304.FIG.17illustrates a cross-sectional view1700of some alternative embodiments corresponding to act3304.FIG.25illustrates a cross-sectional view2500of some alternative embodiments corresponding to act3304. At act3306, a masking layer is formed on a second side of the substrate.FIG.9illustrates a cross-sectional view900of some embodiments corresponding to act3306.FIG.18illustrates a cross-sectional view1800of some alternative embodiments corresponding to act3306.FIG.26illustrates a cross-sectional view2600of some alternative embodiments corresponding to act3306. At act3308, a first etching process is performed to etch the substrate according to the masking layer to define a first TSV opening having a width that increases as a distance from the masking layer increases.FIG.10illustrates a cross-sectional view1000of some embodiments corresponding to act3308.FIGS.19A-19Eillustrate cross-sectional views1900of some alternative embodiments corresponding to act3308.FIG.27illustrates a cross-sectional view2700of some alternative embodiments corresponding to act3308. At act3310, a dielectric liner is formed on sidewalls of the substrate defining the first TSV opening.FIG.11illustrates a cross-sectional view1100of some embodiments corresponding to act3310.FIG.20illustrates a cross-sectional view2000of some alternative embodiments corresponding to act3310.FIG.28illustrates a cross-sectional view2800of some alternative embodiments corresponding to act3310. At act3312, an etch blocking layer is formed on sidewalls of the dielectric liner in some embodiments.FIG.12illustrates a cross-sectional view1200of some embodiments corresponding to act3312.FIG.21illustrates a cross-sectional view2100of some alternative embodiments corresponding to act3312.FIG.29illustrates a cross-sectional view2900of some alternative embodiments corresponding to act3312. At act3314, a second etching process is performed to etch the dielectric liner and the ILD structure according to the etch blocking layer and/or the dielectric liner to define a second TSV opening exposing a first interconnect of the plurality of interconnects.FIG.13illustrates a cross-sectional view1300of some embodiments corresponding to act3314.FIG.22illustrates a cross-sectional view2200of some alternative embodiments corresponding to act3314.FIG.30illustrates a cross-sectional view3000of some alternative embodiments corresponding to act3314. At act3316, the etch blocking layer may be removed in some embodiments.FIG.31illustrates a cross-sectional view3100of some embodiments corresponding to act3316. At act3318, a conductive material is formed within the first TSV opening and the second TSV opening.FIG.14illustrates a cross-sectional view1400of some embodiments corresponding to act3318.FIG.23illustrates a cross-sectional view2300of some alternative embodiments corresponding to act3318.FIG.31illustrates a cross-sectional view3100of some alternative embodiments corresponding to act3318. At act3320, a planarization process is performed to remove excess of the conductive material.FIG.15illustrates a cross-sectional view1500of some embodiments corresponding to act3320.FIG.23illustrates a cross-sectional view2300of some alternative embodiments corresponding to act3320.FIG.31illustrates a cross-sectional view3100of some alternative embodiments corresponding to act3320. Accordingly, in some embodiments, the present disclosure relates to an integrated chip having a through-substrate-via (TSV) (e.g., a back-side through substrate via (BTSV)) with a reentrant profile that is configured to prevent damage to a dielectric liner. In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate, the semiconductor substrate including one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate; a dielectric liner lining the one or more sidewalls of the semiconductor substrate; a through-substrate-via (TSV) arranged between the one or more sidewalls and separated from the semiconductor substrate by the dielectric liner; and the TSV having a first width at a first distance from the second side and a second width at a second distance from the second side, the first width smaller than the second width and the first distance smaller than the second distance. In some embodiments, the dielectric liner continuously extends from along the one or more sidewalls of the semiconductor substrate to along the second side of the semiconductor substrate. In some embodiments, the dielectric liner includes a first sidewall and a second sidewall facing opposing sides of the TSV and a horizontally extending ledge protruding outward from the first sidewall and towards the second sidewall. In some embodiments, the integrated chip further includes an etch blocking layer arranged between the dielectric liner and sidewalls of the TSV, the etch blocking layer having a bottom that is separated from the horizontally extending ledge of the dielectric liner. In some embodiments, the etch blocking layer has a thickness that varies over a height of the etch blocking layer. In some embodiments, the etch blocking layer continuously extends from a sidewall of the dielectric liner to along the second side of the semiconductor substrate. In some embodiments, the TSV includes a horizontally extending surface facing away from the semiconductor substrate and a protrusion extending outward from the horizontally extending surface. In some embodiments, the integrated chip further includes a plurality of interconnects disposed within an inter-level dielectric (ILD) structure arranged along the first side of the semiconductor substrate, the protrusion extending through the ILD structure to contact one of the plurality of interconnects. In some embodiments, the one or more sidewalls of the semiconductor substrate are respectively defined by a plurality of curved depressions. In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnects disposed within an inter-level dielectric (ILD) structure arranged along a first side of a substrate; a through-substrate-via (TSV) extending through the substrate; a dielectric liner separating the TSV from the substrate, the dielectric liner including a first sidewall and a second sidewall facing opposing sides of the TSV and a horizontally extending ledge protruding outward from the first sidewall and towards the second sidewall; and the TSV including a horizontally extending surface disposed on the horizontally extending ledge of the dielectric liner and a protrusion extending outward from the horizontally extending surface to one of the plurality of interconnects. In some embodiments, the dielectric liner continuously extends from along sidewalls of the substrate to along a second side of the substrate opposing the first side of the substrate. In some embodiments, the integrated chip further includes an etch blocking layer arranged between the dielectric liner and sidewalls of the TSV, the etch blocking layer vertically separated from the horizontally extending ledge of the dielectric liner by a non-zero distance. In some embodiments, the etch blocking layer includes an oxide or a nitride. In some embodiments, the etch blocking layer has sidewalls facing the TSV; and the sidewalls of the etch blocking layer are separated by a first distance and the protrusion has a width that is greater than or equal to the first distance. In some embodiments, the TSV has a top surface having a first width and a bottom surface having a second width; and the TSV has a maximum width that is vertically disposed between the top surface and the bottom surface, the maximum width being larger than the first width and the second width. In some embodiments, the first sidewall of the dielectric liner is separated from the horizontally extending ledge of the dielectric liner by an angle of between approximately 80° and approximately 90°. In some embodiments, the TSV has a first sidewall that is directly between sidewalls of the substrate and that has a first slope; and the TSV has a second sidewall that is directly between sidewalls of the ILD structure and that has a second slope that is larger than the first slope. In some embodiments, an imaginary vertical line that is perpendicular to the first side of the substrate extends through the TSV and through the dielectric liner. In other embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of interconnects within an inter-level dielectric (ILD) structure along a first side of a substrate; forming a masking layer on a second side of the substrate opposing the first side; performing a first etching process to etch the substrate according to the masking layer and to form sidewalls of the substrate that define a first through-substrate-via (TSV) opening extending through the substrate, the first TSV opening having a width that increases as a distance from the masking layer increases; forming a dielectric liner along the sidewalls of the substrate and on the ILD structure; performing a second etching process on the dielectric liner and the ILD structure to form a second TSV opening exposing one of the plurality of interconnects, the second TSV opening being separated from a sidewall of the dielectric liner by a non-zero distance; and forming a conductive material within the first TSV opening and the second TSV opening. In some embodiments, the method further includes forming an etch blocking layer on sidewalls of the dielectric liner, the second etching process etching the dielectric liner and the ILD structure according to the etch blocking layer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 64,137 |
11862536 | Features and advantages of the illustrated embodiments will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. DETAILED DESCRIPTION As described above, transistors comprising gallium nitride (GaN) material are useful for high speed, high voltage, and high power applications because of the favorable material properties of GaN. Some applications relating to radio-frequency (RF) communications can place demanding performance requirements on devices that include GaN transistors. For example, some applications may require GaN transistors with a power rating of between approximately 250 Watts and approximately 1000 Watts. High power transistors may be constructed by, for example, forming a plurality of transistors on a die. Each of these transistors on the die may include gate, source, and drain contacts. The plurality of transistors on the die may be electrically coupled together by electrically coupling like contacts together. For example, the gate contacts may be electrically coupled together. Similarly, the drain contacts may be electrically coupled together and the source contacts may be electrically coupled together. The power rating of a high power transistor may increase as the total gate width of the high power transistor increases. The total gate width may be equal to the sum of the gate widths of each gate contact in the high power transistor. Thereby, the power rating of a transistor may be increased by adding gate contacts and/or by increasing the width of the gate contacts. Increasing the gate width of individual gate contacts, however, may undesirably decrease the gain of the high power transistor. Conventional transistors arrange a plurality of gate, source, and drain contacts in a single linear array. These conventional transistors achieve higher power ratings by elongating the die and adding additional contacts (including gate contacts) to the single linear array. Thereby, the power rating may be increased without changing the width of the gate contacts or reducing the gain. The inventors have appreciated that the conventional construction of high power transistors using a single linear array of contacts forms a rectangular die with a length that is substantially longer than its width and only uses a fraction of the space available in a given circuit package. Further, the inventors have appreciated that the heat dissipation through the circuit package may increase as the contact area between the die and the circuit package increases. Accordingly, the inventors have conceived and designed high power transistors that include multiple linear arrays of contacts arranged in parallel to increase the total gate width of a high power transistor without elongating the die. Thereby, a greater portion of the space in a given circuit package may be used and the power rating of the high power transistor may be increased. Further, the increased surface area between the high power transistor and the circuit package allows the additional heat generated by the extra linear array(s) of contacts to be dissipated through the circuit package. Example Transistors By way of introductory explanation, a transistor may be formed by a set of contacts above a semiconductor material, such as GaN, on a substrate. An example of such a transistor is shown inFIGS.1A and1Bby transistor100. As shown, the transistor100includes a substrate102, a transition layer104, a GaN layer106, an aluminum gallium nitride (AlGaN) layer107, a passivation layer114, a source contact108, a gate contact110, and a drain contact112. The gate contact110may have a width shown as Wgand a length shown as Lg. The substrate102may be a semiconductor or an electric insulator that forms the base of the transistor100. The substrate102may comprise, for example, bulk GaN, silicon, silicon carbide, and/or sapphire. The transistor layer104may be formed on the substrate102to, for example, facilitate the bonding of the GaN layer106to the transistor100. The transition layer104may include a buffer layer (e.g., aluminum nitride) deposited directly on or above the substrate102. The GaN layer106may include source, channel, and drain regions below the source, gate, and drain contacts108,110, and112, respectively. Carrier transport between the source and drain regions in the GaN layer106may be controlled by a voltage applied to the gate contact110. In some embodiments, the GaN layer106may have a low defect density because the GaN layer114includes the active region of the device. For example the defect density may be less than approximately 108cm−2. The GaN layer106may include GaN material in any of a variety of forms. For example, the GaN layer106may include AlGaN, indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), gallium arsenide phosphide nitride (GaAsPN), and/or aluminum indium gallium arsenide phosphide nitride (AlInGaAsPN). The contacts108,110, and112may be formed above the AlGaN layer107to isolate the contacts108,110, and112from the GaN layer106. As shown inFIG.1A, the transistor100may include a passivation layer114that covers the AlGaN layer107while still leaving the contacts108,110, and112exposed. It should be appreciated that the transistor100may be formed in any of a variety of architectures. For example, the transistor100may formed as a depletion-mode, high-electron-mobility transistor (HEMT), a junction field-effect transistor (JFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a bipolar junction transistor (BJT). Further, the transistor100does not need to be a GaN transistor. For example, the transistor100may have an active region that comprises silicon and may omit the GaN layer106and/or the AlGaN layer107. Example Power Transistors A power transistor may be constructed by forming a plurality of transistors, each like transistor100shown inFIGS.1A and1B, on a die. As discussed above, the plurality of transistors may be arranged in multiple linear arrays to increase the total gate width of a given power transistor while still allowing the power transistor to be mounted within the same circuit package. A plan view of an example of such a power transistor is shown inFIG.2Aby power transistor200A. As shown, the power transistor200A includes linear arrays of contacts202, gate pads204, drain pads206, interconnects208, and vias210. The power transistor200A includes two linear arrays of contacts202that are arranged in parallel. Each of the linear arrays of contacts202includes source, gate, and drain contacts108,110, and112, respectively, that are arranged to form a plurality of transistors. For example, each linear array of contacts202in the power transistor200A includes ten sets of source, gate, and drain contacts108,110, and112, respectively, that form ten transistors. The gate, drain, and source contacts108,110, and112, respectively, may have a similar (or same) width as shown inFIG.2A. It should be appreciated that the particular dimension of each contact and the number of contacts in the power transistor200A may vary based on the particular implementation. For example, the number of contacts in each linear array of contacts202and/or the number of linear arrays of contacts202may be adjusted to change the total gate width of the power transistor200A and, thereby, change the power rating of the power transistor200A. In addition (or alternatively), the width of each of the gate contacts110may be adjusted to change a gain and power rating of the power transistor200A. In some embodiments, contacts of the same type in each linear array of contacts202and/or in the entire power transistor200A may be electrically coupled together. For example, the gate contacts110may be electrically coupled together by the interconnects208. Similarly, the drain contacts112may be electrically coupled together by the interconnects208. The source contacts108may be electrically coupled together through a conductive surface of a circuit package when the power transistor200A is packaged. For example, the source contacts108may be electrically coupled to vias210that pass through a substrate (e.g., through the substrate102) of the power transistor200A. In this example, the substrate of the power transistor200A may be mounted on a conductive surface of the circuit package. Thereby, the source contacts108may be electrically coupled to each other through the interconnects208, the vias210, and the conductive surface of the circuit package. The pads204and206may facilitate the electrical connection between terminals of a circuit package and the contacts within the power transistor200A. For example, the gate pad204may be electrically coupled to the gate contacts108through interconnects208. In turn, the gate pad204may be electrically coupled to a gate terminal of a circuit package by a bonding wire. Similarly, the drain pad206may be electrically coupled to the drain contacts112by interconnects208and electrically coupled to a drain terminal of a circuit package by bonding wires. The particular size and location of the pads204and206may vary based on the particular implementation of the power transistor200A and/or the circuit package that the power transistor200A will be mounted in. For example, the drain pad206may be larger than the gate pads204(e.g., as shown inFIG.2A) to enable additional bonding wires to connect the drain terminal to the drain pad206. In some embodiments, the source contacts108of the power transistor200A may be electrically coupled to a source terminal of a circuit package without a pad or bonding wires. For example, the source contacts108may be electrically coupled by interconnects208to vias210that pass through the substrate of the power transistor200A. In this example, the substrate of the power transistor200A may be mounted to a conductive surface of a circuit package that is electrically coupled to the source terminal. Thereby, the vias210(in combination with the metal interconnects208) may electrically the source contacts108to the conductive surface and the source terminal. It should be appreciated that source contacts108may be electrically coupled to a source terminal of a circuit package in a similar fashion as the gate and drain contacts110and112, respectively, in some embodiments. For example, the transistor200A may further include a source pad that is electrically coupled to the source contacts108by interconnects208. The source pads may be employed to provide an additional connection point to the source contacts108or used in-place of the vias210. As discussed above, the interconnects208may electrically couple various elements within the power transistor200A. The interconnects208may be constructed in a variety of ways and may be formed on any of the layers in the power transistor200A. For example, the interconnects208may be metal interconnects patterned over a substrate (e.g., substrate102) of the power transistor200A. Various alterations may be made to the power transistor200A without departing from the scope of the present disclosure. For example, each of the two large linear arrays of contacts202shown inFIG.2Amay each be divided into two smaller linear arrays of contacts that are in line with each other. Dividing up the large linear arrays of contacts may, for example, improve heat dissipation by spreading out the linear arrays of contacts that generate heat. An example of such a power transistor is shown inFIG.2Bby power transistor200B. The power transistor200B divides each of the two linear arrays of contacts202shown inFIG.2Ainto two smaller linear arrays of contacts202that are in-line with each other. Thereby, the power transistor200B includes four linear arrays of contacts202. Further, the power transistor200B divides the single drain pad206inFIG.2Ainto two smaller drain pads206and adds an additional gate pad204between the two drain pads206. Each of the drain pads206in power transistor200B may be electrically coupled to the drain contacts112in two of the four linear arrays of contacts202. As shown inFIGS.2A and2B, the pads204and/or206may be placed between linear arrays of contacts202. In some embodiments, the pads204and206may be placed, instead, on opposing sides of the linear arrays of contacts202as shown inFIG.2Cby power transistor200C. As shown, the gate pad204is on a first side of the linear arrays of contacts202and the drain pad206is on a second side of the linear arrays of contacts202that is opposite the first side. As described above, the source contacts108may be electrically coupled to a source terminal of a circuit package through vias210. InFIG.2C, the vias210are placed in the source contacts108to electrically couple the source contacts108to a conductive surface in the circuit package. Thereby, the interconnects208between the source contacts108and the vias210may be omitted. In some embodiments, the drain contact112may have a different width than the source contacts108or the gate contacts110. For example, the drain contact112may have a width that is at least two times larger than the width of the gate contacts110. As shown inFIG.2C, employing a longer drain contact112may allow a single drain contact112to be shared across multiple linear arrays of contacts. Further, the shared drain contact112allows the drain pad206to be electrically coupled to the drain contact112with a direct interconnect208. The gate pad204inFIG.2Cmay be coupled to the gate contacts110by interconnects208and/or nodes212. As shown, interconnects208may be placed directly between the gate contacts110in the linear array of contacts202that is proximate the gate pad204. The interconnects208may electrically couple the gate contacts110that are in the linear array of contacts202that is distal from the gate pad204through a node212. For example, one interconnect208may be formed over the source contact108(without making an electrical connection to the source contact108) and electrically couple the node212to the gate pad204. Additional interconnects208may electrically couple the node212to gate contacts110in the linear array of contacts that is distal from the gate pad204. As shown, the node212may be placed between the linear arrays of contacts202and be electrically coupled to a pair of gate contacts110. It should be appreciated that the interconnects208may be arranged in any suitable way to couple the gate pad204to the source contacts108. For example, the interconnects208may be routed under or around the source contacts108to reach the node212. Further, the direct interconnects208between the gate pad204and the gate contacts110in the linear array of contacts202that is proximate the gate pad204may be replaced with interconnects208between those gate contacts110and the node212. An example of such a power transistor is shown inFIG.2Dby power transistor200D. As shown, the gate pads204are electrically coupled to all of the gate contacts110through the nodes212. In particular, each node212is now electrically coupled to four gate contacts110including two gate contacts110from each of the two linear arrays of contacts202. In some embodiments, a power transistor may be constructed with more than two linear arrays of contacts in parallel. For example, the power transistor200C may be extended to include three or more linear arrays of contacts. An example of such a power transistor is shown inFIG.3by power transistor300. As shown, the power transistor300includes three linear arrays of contacts202arranged in parallel between the gate pad204and the drain pad206. The gate pad204may be electrically coupled to the gate contacts110in the first linear array of contacts202that is proximate the gate pad204by direct interconnects208. The gate contacts110in the second linear array of contacts202in the middle of the three linear arrays of contacts202may be electrically coupled by interconnects208to a first node212that is between the first and second linear arrays of contacts202. The first node212may be, in turn, electrically coupled to the gate pad204by interconnects208. The gate contacts110in the third linear array of contacts202that is distal from the gate pad204may be electrically coupled by interconnects208to a second node212that is between the second and third linear arrays of contacts202. The second node212may be, in turn, electrically coupled to the first node212and the gate pad204by interconnects208. Having described various possible implementations of a power transistor with multiple linear arrays of contacts, it should be appreciated that still yet more implementations may be constructed. For example, the power transistor may include additional pads, different pad locations, different arrangements of interconnects, and/or additional linear arrays of contacts. Example Packaged Power Transistors The power transistors described above with reference toFIGS.2A-3may be mounted in a circuit package to, for example, protect the power transistor from the environment and/or dissipate heat from the power transistor during operation. An example of such a packaged power transistor is shown inFIGS.4A and4Bby packaged power transistor400.FIG.4Ashows the underside of the packaged power transistor400andFIG.4Bshows the topside of the packaged power transistor400. As shown, the packaged power transistor400includes a power transistor402mounted to a conductive surface407in an enclosure408. The packaged power transistor further includes a gate terminal412, a drain terminal414, and a source terminal416that may be attached to the enclosure408. The power transistor402may include gate pads404coupled to the gate terminal412by bonding wires410in addition to drain pads406coupled to the drain terminal414by bonding wires410. The power transistor402may include a plurality of transistors arranged in multiple linear arrays, such as power transistors200A,200B,200C,200D, and300described above. The gate contacts of these transistors may be electrically coupled to the gate pad404. Similarly, the drain contacts of these transistors may be electrically coupled to the drain pad406. The source contacts of these transistors may be electrically coupled to the conductive surface407through vias, such as vias210shown inFIGS.2A-3. It should be appreciated that the particular location, number, and type of pads on the power transistor402may vary based on the particular implementation. For example, the power transistor402may include a source pad and/or include a different number of drain pads. The power transistor402may be electrically coupled to the gate, drain, and source terminals412,414, and416, respectively. For example, the gate pads404on the power transistor402may be electrically coupled the gate terminal412by bonding wires410. Similarly, the drain pads408may be electrically coupled to the drain terminal414by bonding wires410. As discussed above, the source contacts in the power transistor402may be electrically coupled to the conductive surface407through vias in the power transistor402. The conductive surface407may be, in turn, electrically coupled to the source terminal416. For example, the conductive surface407may be integral with the source terminal416. Thereby, the source contacts may be electrically coupled to the source terminal416without the use of bonding wires and/or a source pad. It should be appreciated that additional components may be placed in the enclosure408and/or be included in the packaged power transistor400that are not shown. For example, the packaged power transistor may further include a matching network with various capacitive elements to improve the performance of the packaged power transistor400in a device, such as an RF amplifier. CONCLUSION The terms “approximately” and “about” may be used to mean within ±20% of a target dimension in some embodiments, within ±10% of a target dimension in some embodiments, within ±5% of a target dimension in some embodiments, and yet within ±2% of a target dimension in some embodiments. The terms “approximately” and “about” may include the target dimension. When using the terms “on,” “adjacent,” or “over” in to describe the locations of layers or structures, there may or may not be one or more layers of material between the described layer and an underlying layer that the layer is described as being on, adjacent to, or over. When a layer is described as being “directly” or “immediately” on, adjacent to, or over another layer, no intervening layer is present. When a layer is described as being “on” or “over” another layer or substrate, it may cover the entire layer or substrate, or a portion of the layer or substrate. The terms “on” and “over” are used for ease of explanation relative to the illustrations, and are not intended as absolute directional references. A device may be manufactured and implemented in other orientations than shown in the drawing (for example, rotated about a horizontal axis by more than 90 degrees). The technology described herein may be embodied as a method, of which at least some acts have been described. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than described, which may include performing some acts simultaneously, even though described as sequential acts in illustrative embodiments. Additionally, a method may include more acts than those described, in some embodiments, and fewer acts than those described in other embodiments. Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto. | 22,087 |
11862537 | It may be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of the present invention. The specific design features of the present invention as included herein, including, for example, specific dimensions, orientations, locations, and shapes will be determined in part by the particularly intended application and use environment. In the figures, reference numbers refer to the same or equivalent portions of the present invention throughout the several figures of the drawing. DETAILED DESCRIPTION Reference will now be made in detail to various embodiments of the present invention(s), examples of which are illustrated in the accompanying drawings and described below. While the present invention(s) will be described in conjunction with exemplary embodiments of the present invention, it will be understood that the present description is not intended to limit the present invention(s) to those exemplary embodiments. On the other hand, the present invention(s) is/are intended to cover not only the exemplary embodiments of the present invention, but also various alternatives, modifications, equivalents and other embodiments, which may be included within the spirit and scope of the present invention as defined by the appended claims. Hereinafter, a soldering structure and a power module according to various embodiments of the present invention are described in detail with reference to the accompanying drawings. FIG.1is a cross-sectional view showing a power module using a soldering structure according to various exemplary embodiments of the present invention. As shown inFIG.1, a power module1may be a double-sided cooling type power module having substrates10and20on its upper and lower portions. The upper substrate10may include a first metal layer11, a dielectric layer12bonded to an upper surface of the first metal layer11, and a second metal layer13bonded to an upper surface of the dielectric layer12. Although not shown, a cooling channel may be disposed on the upper surface of the second metal layer13by having a thermal interface material (TIM) interposed therebetween. Like the upper substrate10, the lower substrate20may include a first metal layer21, a dielectric layer22bonded to a lower surface of the first metal layer21and a second metal layer23bonded to a lower surface of the dielectric layer22. Although not shown, the other cooling channel may be disposed on the lower surface of the second metal layer23by having a thermal interface material (TIM) interposed therebetween. The dielectric layers12and22respectively included in the upper substrate10and the lower substrate20may each have a large thickness tolerance due to characteristics of its manufacturing process. Therefore, for the entire power module1to have a constant height by compensating for each thickness tolerance of the dielectric layers12and22respectively included in the upper substrate10and the lower substrate20, the height depending on melting of solders51to53may be adjusted by increasing each amount of the solders51to53that physically/electrically bond components in the power module1to each other. For example, a large amount of solder may be used to compensate for the height of the power module1having a value lower than a set value, and in a case where the height has a value higher than the set value and thus needs to be lowered, the height may be lowered by widely spreading the molten solders51to53. The solders51to53for adjusting the height may be used to directly or indirectly bond components to each other between the upper and lower substrates. The solder for adjusting the height is used for a component, which is bonded to each of the metal layers11and21of the substrates10and20by solder and not affecting the operation or durability of the power module. For example, as shown inFIG.1, the solders51to53may be suitable for adjusting the height as the solders used for respectively bonding spacers31and32and the metal layers11and21of the substrates10and20to each other. Solders54and55may be used to bond a power semiconductor chip40to another component, may affect an operation of the power semiconductor chip40due to solder overflow, and thus may not be suitable for adjusting the height. Furthermore, a solder56may bond a lead61to the metal layer21of the substrate20, may not be directly or indirectly connected to the upper substrate10, and thus may not be suitable for adjusting the height. The soldering structure according to various exemplary embodiments of the present invention may be used for portions respectively marked by reference numerals ‘A1’ and ‘A2’ shown inFIG.1. The soldering structure may include: the component31or32to be soldered; and the metal layer11or21having a bonding area, to which the component31or32to be soldered is bonded by solder, and a groove portion D formed around the bonding area. In the power module1using the soldering structure according to various exemplary embodiments of the present invention, the components to be soldered may be the spacers31and32, and the metal layers may be the metal layers11and21included in the substrates10and20, respectively. An upper end portion of the via spacer31may be bonded to the first metal layer11of the upper substrate10by the solder51, and a lower end portion of the via spacer31may be bonded to the first metal layer21of the lower substrate20by the solder52, without having any component interposed therebetween, and the groove portion D may be formed on each of the metal layers11and21respectively bonded to both the end portions of the via spacer31. One end portion of the spacer32may be bonded to the power semiconductor chip40by the solder54and the other end portion of the spacer32may be bonded to the first metal layer11of the first substrate10by the solder53, and the groove portion D may be formed only on the first metal layer11of the first substrate10. FIG.2is a further enlarged cross-sectional view showing the soldering structure of the exemplary embodiment shown inFIG.1; andFIG.3is a plan view showing a surface of a metal layer of the soldering structure according to various exemplary embodiments of the present invention.FIG.2is a view showing the area marked by the ‘A1’ inFIG.1; andFIG.3is a plan view showing that the spacer31or32and the metal layer11or21are bonded to each other in the area marked by ‘A1’ or ‘A2’ ofFIG.1. Referring toFIG.2andFIG.3, in the soldering structure according to various exemplary embodiments of the present invention, the metal layers11and21may each include: a bonding area R to which one surface of a component to be soldered, such as the spacer31or32, is bonded; and the groove portion D formed around the bonding area R. The groove portion D may block the solders in a molten state used to bond the spacers31and32and the metal layers11and21to each other, respectively, from being moved along the surfaces of the metal layers11and21. Instead, the molten solders may be moved vertically along side surfaces of the spacers31and32, respectively. Here, the side surfaces of the spacers31and32may refer to surfaces formed in a direction perpendicular to one surfaces of the spacers31and32facing the metal layers11and21, respectively, and may refer to surfaces corresponding to the left and right of the spacers31and32shown inFIG.1or2, respectively. For the molten solders51and52not to be diffused along the surfaces of the metal layers11and21and to be moved along the side surfaces of the spacers31and32as described above, the surfaces of the spacers31and32need to have excellent solder wettability. The solder wettability may refer to a property that the molten solder spreads over a base metal, e.g., the surfaces of the spacers31and32. In various embodiments of the present invention, an a metal having excellent solder wettability needs to be employed on the surfaces of the spacers31and32to prevent the solders from being moved to the surfaces of the metal layers11and21to affect patterns of the metal layers, respectively. To the present end, each of the spacers31and32is made of a metal having excellent solder wettability due to its low contact angle formed by the molten solder (for example, a contact angle of about 40 degrees or less), such as copper (Cu), gold (Au), silver (Ag) or nickel (Ni), or each of the spacers31and32is manufactured to have its surface plated with the above metal. As described above, according to the various embodiments of the present invention, it is possible to prevent the molten solders from being moved along the surfaces of the metal layers11and21and allow the solders51,52and53to be moved to the side surfaces of the spacers31and32, preventing the solders from affecting patterns formed by the metal layers11and21due to the solder overflow even though the large amount of solder is used to adjust the height of the power module. In various exemplary embodiments of the present invention, the groove portion D may have a shape in which a plurality of dimples is arranged to surround the bonding area R around the bonding area R. The inventors of the present invention most effectively tested whether deformation occurs in a pattern of a metal layer due to the solder overflow by variously changing a shape of a groove portion.FIG.4,FIG.5,FIG.6,FIG.7andFIG.8show the results of the present test. FIG.4,FIG.5,FIG.6andFIG.7are views showing various shapes of groove portions and patterns of metal layers based thereon as comparative examples of the present invention; andFIG.8is a view showing a shape of a groove portion and a pattern state of a metal layer of the soldering structure according to various exemplary embodiments of the present invention. FIG.4shows an example in which a groove portion D′ is formed in a shape of a groove disposed along a direction in which each side of a bonding area R′ having a rectangular planar shape is disposed;FIG.5shows an example in which the groove portion D′ is formed to have L-shaped grooves near respective vertices of the bonding area R′ having the rectangular planar shape;FIG.6shows an example of reducing a space between the groove portion and the bonding area of the comparative example shown inFIG.4; andFIG.7shows an example of increasing the space between the groove portion and the bonding area of the comparative example shown inFIG.4. As shown in photos disposed in respective lower portions ofFIG.4,FIG.5,FIG.6, andFIG.7, it may be seen that in all of the comparative examples, deformation E occurs in the patterns of the metal layers due to the solder overflow. In a case where the solder causes deformation in the pattern of the metal layer as above, damage to the substrate may occur due to thermal shock. On the other hand, it may be seen that the soldering structure according to various exemplary embodiments of the present invention shown inFIG.8does not affect the pattern of the metal layer. These results are because the solder may be easily flowed into and fill each groove portion D′ of the comparative examples, which is formed in a shape of a groove, and thus may not be effectively confined therein. Furthermore, in a case where the dielectric layers12and22are exposed, such an exposure may not only change an electrical path formed by the metal layers11and21but also be disadvantageous to distribution of stress. It is thus necessary to form a groove portion by removing only some of the metal layers11and21without exposing the insulating layers12and22. However, when taking into account precision of an etching process used for forming the groove-shaped groove portion D′ of each of the comparative examples as shown inFIG.4,FIG.5,FIG.6, andFIG.7, it is very difficult to remove some of the metal layers11and21without exposing the insulating layers12and22of the substrates10and20. As described above, it is very advantageous to form the dimple-shaped groove portion as in various exemplary embodiments of the present invention when taking into account both the prevention of the solder overflow and the difficulty of the process. FIG.9is a view showing an example of increasing a space between a plurality of dimples configuring a groove portion as another comparative example of the present invention. As seen from the comparison betweenFIG.8andFIG.9, in a case where the space between the dimples is large, the deformation E occurs in a pattern of a metal layer due to the solder overflow. According to various exemplary embodiments of the present invention, it is possible to prevent the solder overflow by allowing the solder to flow upward along a side surface of the chip between the dimple D and the component to be soldered. That is, the solder confinement in various exemplary embodiments of the present invention may be achieved by confining the solder between the dimple D and the component to be soldered, rather than confining the solder in the dimple D. The solder confinement using these dimples may be achieved more easily if the space between the dimples is small, and the space between each of the plurality of dimples D may preferably be smaller than a diameter of each of the plurality of dimples. The space between each of the plurality of dimples D may more preferably be smaller than or equal to half the diameter of each of the plurality of dimples. Furthermore, in a case where there is a limitation on the number of dimples D to be formed, the dimples D are formed mainly at the vertices of the area to be soldered. In a case where the solder is molten and compressed during the soldering, the component to be soldered may be deviated from the soldering area or rotated along a portion where the solder is wetted. However, when the dimple D is formed adjacent to the vertices of the area to be soldered, the solder may be confined near the vertices of the component to be soldered, preventing the component to be soldered from being deviated or rotated. As described above, according to the soldering structure and the power module including the same according to the various embodiments of the present invention, it is possible to minimize the solder overflow to a boundary of the pattern formed on the metal layer of the substrate even though the large amount of solder is provided to control the height of the power module in the manufacturing process of the power module. Accordingly, it is also possible to prevent the damage to the substrate due to the thermal shock by preventing the stress from being added to the substrate due to the solder overflow. For convenience in explanation and accurate definition in the appended claims, the terms “upper”, “lower”, “inner”, “outer”, “up”, “down”, “upwards”, “downwards”, “front”, “rear”, “back”, “inside”, “outside”, “inwardly”, “outwardly”, “interior”, “exterior”, “internal”, “external”, “forwards”, and “backwards” are used to describe features of the exemplary embodiments with reference to the positions of such features as displayed in the figures. It will be further understood that the term “connect” or its derivatives refer both to direct and indirect connection. The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teachings. The exemplary embodiments were chosen and described to explain certain principles of the present invention and their practical application, to enable others skilled in the art to make and utilize various exemplary embodiments of the present invention, as well as various alternatives and modifications thereof. It is intended that the scope of the present invention be defined by the Claims appended hereto and their equivalents. | 15,966 |
11862538 | DETAILED DESCRIPTION A semiconductor die may be mounted to a die pad within a semiconductor package. In some cases, the semiconductor die may be attached to the die pad using a solder paste. During a reflow process, heat is applied (e.g., via convection, radiation) to the solder paste so as to melt and fuse the solder paste to the die pad and the semiconductor die. Unbalanced wetting forces (e.g., caused by non-uniform heat transfer) may lead to undesired lateral rotation, translation, or other movement of the semiconductor die on the die pad during the reflow process, which may result in misalignment or misplacement of the semiconductor die on the die pad. Ultimately, this unwanted movement of the semiconductor die may frustrate subsequent operations for electrically coupling the semiconductor die to other electrical components (e.g., conductive terminals). Accordingly, examples disclosed herein include die pads that are configured to prevent excessive movement (e.g., rotation) of a semiconductor die during a reflow process. For instance, in some examples, the example die pads may include a recess that is sized and shaped to constrain movement of the semiconductor die during a reflow process, even if the solder paste experiences unbalanced wetting forces. Thus, through use of the example die pads disclosed herein, a desired position and alignment of semiconductor die may be maintained on a die pad during a reflow process, so that instances of die misalignment may be reduced in a semiconductor package manufacturing process. Referring now toFIG.1, a block diagram of an electronic device10including semiconductor chip package100(or more simply “package100”) having a recess120in a die pad110for receiving a semiconductor die150(or more simply “die150”) therein according to some examples is shown. In particular, the electronic device10may be a laptop computer, a notebook computer, a desktop computer, a smartphone, an appliance (e.g., a refrigerator, a laundry machine, an oven, a toaster), a television, an automobile or a component within an automobile, an aircraft or a component within an aircraft, a water vehicle or a component within a water vehicle, or any other type of device containing one or more electronic components. In some examples, the electronic device10includes a PCB12. The package100is coupled to the PCB12. During use of the electronic device10, the package100may receive power and/or data signals and may perform a function or functions that contribute to the overall use and functionality of the electronic device10. Other components (e.g., such as other semiconductor packages and/or other electronic devices) may be coupled to PCB12and potentially coupled to the package100. However, these possible additional components are not shown inFIG.1so as to simplify the drawing. Referring now toFIGS.2A and2B, a perspective view and top view, respectively, of the PCB12and the package100are shown according to some examples. As previously described, the package100comprises a die150mounted within a recess120formed in a die pad110. In addition, the die150may be coupled to a plurality of conductive terminals112(or more simply “terminals112”) via wire bonds16. The terminals112are also coupled (e.g., with solder15shown inFIG.2C) to a plurality of traces14(or any suitable conductive surfaces) formed on PCB12. Further, a pair of tie bars113may be coupled to and may extend from die pad110(e.g., at about a 45° angle from the horizontal direction). The die pad110, die150, a portion of the terminals112, and the tie bars113are all covered in a dielectric mold compound102(or more simply “mold compound102”) to shield the die150and the other electrical components (e.g., terminals112, wire bonds16) of package100from moisture, debris, contaminants, etc. Referring now toFIG.2C, a cross-sectional view of the package100and PCB12taken along section A-A inFIG.2Bis shown. Die pad110includes a first or top side110aand a second or bottom side110bopposite top side110a. Top side110amay comprise a planar surface. Recess120extends into die pad from top side110a(e.g., from the planar surface of top side110a). In particular, recess120includes a terminal surface122(which may be referred to herein as a “floor” of recess120) and a plurality of side walls124extending (e.g., perpendicularly to the plane of top side110a) between top side110aand terminal surface122. The terminal surface122may comprise a planar surface that is parallel to and offset (e.g., by the side walls124) from top side110a(e.g., from the plane of top side110a). Die150includes a first or device side152and a second or non-device side154opposite device side152. A plurality of side walls156extend between the device side152and non-device side154to thereby define an outer perimeter158of die150. The device side154may include circuitry (not shown) that is coupled to the terminals112via wire bonds16as previously described. Specifically, the wire bonds16may be coupled to the device side154and to uppermost surfaces112aof the conductive terminals112. As shown inFIG.2C, a solder member160fixes and secures the die150within the recess120. More specifically, solder member160may be engaged along both the non-device side154of die150and terminal surface122of recess120. In addition, solder member160may also be engaged along outer perimeter158(including one or more or all of the side surfaces156) of die150and/or along one or more of the side walls124of recess120. Thus, rotation and lateral movement (e.g., movement toward or away from side walls124) of die150is constrained by solder member160within recess120. The non-device side154of die150may be positioned within the recess120, and therefore, spaced between the terminal surface122and top side110aof die pad110along the depth of recess120. Further details of examples of die pad110and die150are described in more detail below. As is also shown inFIG.2C, the die pad110is downset relative to the conductive terminals112. That is, the top side110aof the die pad110is positioned lower than the uppermost surfaces112aof the conductive terminals112within mold compound102. The bottom side110bof die pad110may be aligned with a bottom side of the mold compound102, or (as is shown inFIG.2C) may be spaced from the bottom side of the mold compound102(e.g., so that die pad110is fully contained within mold compound102). Without being limited to this or any other theory, the combination of a downset die pad110and a recess120in die pad110for receiving die150allows for a more even distribution of components within the mold compound102. Specifically, the conductive terminals112, wire bonds16, die150, and downset, recessed die pad110may be more evenly distributed across a thickness (e.g., a vertical thickness) within the mold compound102. As a result, the molding operations for forming mold compound102may be more efficient and reliable, because a more even distribution of components (e.g., conductive terminals112, wire bonds16, die150, and die pad110) may allow for a more even and uniform distribution and flow of liquid (or semi-liquid) mold compound102, so that instances of voids within mold compound102are reduced. The tie bars113may extend outward from die pad110(e.g., at about a 45° in some examples) so that the outer ends (e.g., extended away from the die pad110) of tie bars113are co-planar with the uppermost surfaces112aof conductive terminals112. In addition, as best shown inFIG.2B, the outer ends of tie bars113are co-planar or flush with the outer surface of mold compound102such that the outer ends of tie bars113are exposed. Referring now toFIGS.3A-3C, die pad110and die150are shown according to some examples.FIG.3Ashows a perspective view of die pad110and die150,FIG.3Bshows a top view of die pad110and die150, andFIG.3Cshows a cross-sectional view of die pad110and die150along section B-B inFIG.3B. As shown inFIG.3B, recess120is generally rectangular in the top view (e.g., viewed normally to top side110aof die pad110) such that recess120includes a total of four side walls124that define a length L120and a width Win of recess120. The length L120ranges from 972 micrometers (μm) to 2676 μm and the width W120ranges from 1534 μm to 4846 μm such that recess120accommodates a semiconductor die (e.g., die150) as described herein. In addition, as shown inFIG.3C, the recess120extends to a depth Duo measured from top side110ato terminal surface122that is between 50 μm and 100 μm, such as about 75 μm. As shown inFIG.3C, solder member160may form a solder fillet162that extends about the outer perimeter158of die150. In particular, solder fillet162may engage along both the side surfaces156of die150and the side walls124of recess120to secure and align die150within recess120. Solder member160may have a dry bond line thickness T extending upward from terminal surface122that represents the overall thickness of the solder member160after the solder member160has been reflowed within the recess120. The dry bond line thickness T may be measured vertically (e.g., in a direction perpendicular to top side110aand a parallel to the side walls124) from the terminal surface122to the point that solder fillet162extends to along the side walls156of die150. The dry bond line thickness T is less than 2.5 millimeters (mm), such as from 1 mm to 2 mm to ensure that die150is secured within recess120. The dry bond line thickness T may also incorporate a thickness of the solder member160extending between non-device side154of die150and terminal surface122that ranges from 50 μm to 115 μm (such as from 50.8 μm to 114.3 μm in some examples). Without being limited to this or any other theory, a dry bond line thickness T below 1 mm provides an insufficient coverage of solder member160between the die150and recess120such that die150is not adequately secured within recess120. Conversely, if the dry bond line thickness T of solder member160is above 2.5 mm, the initial thickness of the solder paste that forms the solder member160(e.g., before the reflow process) would be greater than the depth (Dian) of recess120(e.g., above top side110a), so that during a reflow process in which the solder paste is melted to form solder member160, the die150may become misaligned (e.g., via rotation and/or translation) with the recess120. In addition, a dry bond line thickness over 2.5 mm would also cause overflow of the solder out of the recess120during reflowing thereby resulting in an uncontrolled movement of the solder on die pad110. The length L120and width Win of the recess120are selected within the ranges provided above to provide a corresponding spacing X between the side surfaces156and side walls124that, along with the above-noted depth Duo, ultimately provides a suitable bond line thickness T within the range described herein (e.g., from 1 mm to 2.5 mm). In some examples, the depth Duo ranges from 430 μm to 500 μm, such as, for instance from 432.8 μm to 495.3 μm. In some examples, the spacing X ranges from 124 to 300 μm, such as, for instance from 240 μm to 300 μm, or about 270 μm. In addition to providing the desired dry bond line thickness T as previously described, limiting the spacing X under 300 μm facilitates formation of wire bonds16. Specifically, a spacing X that is greater than 300 μm is not suitable for forming the wire bonds16so that subsequent coupling of the die150to terminals112is not possible. FIGS.4A-4Eillustrate a process for manufacturing a semiconductor chip package (e.g., package100) that may include a semiconductor die (e.g., die150) within a recess formed in a die pad (e.g., recess120in die pad110) according to some examples. In addition,FIG.5is a flow diagram of a method200for manufacturing a semiconductor chip package that may include a semiconductor die within a recess formed in a die pad according to some examples. Accordingly,FIGS.4A-4E and5are described in parallel. Method200begins by receiving a die pad having a recess at block202. As shown inFIG.4A, the die pad110may include a recess120extending from a top side110ato a terminal surface122as previously described. The die pad110may be coupled to a plurality of conductive terminals112via a lead frame (not specifically shown). A pair of tie bars113may be coupled to and may extend from die pad110(not shown inFIG.4A, but tie bars113are illustrated inFIGS.2A and2B). Next, method200includes aligning a semiconductor die with the recess at block204. As shown inFIG.4B, the die150is aligned with recess120on die pad110by placing the die150on top of a volume of solder paste164that is positioned on terminal surface122within recess120. The non-device side154of the die150may be engaged with the solder paste164such that the device side152faces outward and away from recess120. In addition, in some examples, the thickness of the solder paste164when initially aligning the die150with recess120may be large enough so that the non-device side154is aligned with or is below the top side110awithin recess120. Method200also includes reflowing a solder paste positioned between the semiconductor die and a terminal surface of the recess at block206, and lowering the semiconductor die into the recess at block208. Referring now toFIGS.4B and4C(and particularly the progression fromFIG.4BtoFIG.4C), reflowing the solder paste may comprise applying heat (e.g., convective heat, radiative heat, conductive heat) to the solder paste164, die pad110, and die150so that the solder paste164liquifies before again solidifying as solder member160having fillets162to secure die150within recess120as previously described. In some examples, the die pad110, die150, and solder paste160may be placed within an oven which may apply radiative and/or convective heat thereto. During the reflow process, the liquified solder paste164may flow outward toward side walls124of recess120so that the thickness of solder is reduced and die150is lowered into recess120, toward terminal surface122(e.g., under the force of gravity). In addition, the liquified solder paste164may flow up the side surfaces154along outer perimeter158of die150and/or up the side walls124of recess120so as to form the solder fillet162and to achieve a desired bond line thickness (e.g., bond line thickness T shown inFIG.3C) as previously described. In some examples, the initial thickness of the solder paste160, prior to the reflow process, may be twice the dry bond line thickness T (FIG.3C) of the solder paste160after the reflow process. As previously described, the initial thickness of the solder paste164(that is, before the reflow process) is such that the non-device side154of die150is aligned with or below the top side110aof die pad110. Thus, as the solder paste164liquifies and flows outward toward side walls124during the reflow process as previously described, the non-device side154is placed below the top side110a, within recess120, so that lateral movement and/or rotation of die150is constrained by the side walls124of recess120. As a result, even if there are unbalanced wetting forces within the solder paste160during the reflow process (e.g., such as due to uneven heat transfer), the desired position and alignment of die150is maintained by the recess120. Method200also includes coupling the semiconductor die to a plurality of conductive terminals at block210. As shown inFIG.4D, the terminals112may be coupled to the device side152of die150via wire bonds16. In some examples, the device side152may include a plurality of conductive bond pads (not shown) that couple to the wire bonds16and that define connection terminals or locations for the circuit (not shown) of die150. Finally, method200includes covering the die pad and the semiconductor die with a mold compound at block212. As shown inFIG.4E, the mold compound102may cover the die pad110, die150, and wire bonds16. In addition, the mold compound102may also cover a portion of the terminals112, particularly the portion of the terminals112that are coupled to wire bonds16(e.g., the uppermost surfaces112a). A remaining portion of the terminals112may extend outward from the mold compound102such that they may be coupled (e.g., soldered) to corresponding traces on a PCB (e.g., traces14shown on PCB12inFIGS.2A-2C). The mold compound102may be formed about the die150, die pad110, wire bonds16, and terminals112via a molding process (e.g., injection molding, press molding, vacuum molding). Moreover, the mold compound102may comprise a dielectric material so that mold compound102may insulate die150, die pad110, wire bonds16, and terminals112from one another, and generally from the outside environment, during operations. In addition, mold compound102may also protect die150, die pad110, wire bonds16and terminals112(at least the portion positioned within the mold compound102) from moisture, ultraviolet (UV) radiation, debris, contaminants, etc. during operations. Covering the die150, die pad110, wire bonds16, and terminals112with mold compound102may complete the package100, such that package100may then be coupled within an electronic device (e.g., such as by coupling the package100to PCB12of electronic device10as shown inFIGS.2A-2C). Referring now toFIGS.6A-6Ca semiconductor package300(or more simply “package300”) having a recess120in a die pad110for receiving die150(or more simply “die150”) therein according to some examples is shown.FIG.6Ais a perspective view of the package300mounted to PCB12,FIG.6Bis a top view of the package300and PCB12, andFIG.6Cis a cross-sectional view of package300and PCB12taken along section C-C inFIG.6B. Package300includes die pad110having recess120for receiving die150as previously described for package100. In addition, the die150may be secured within recess120via solder member160. Thus, the position of the die150may be maintained on die pad110during a reflow process, even if the die150experiences un-balanced wetting forces as previously described. However, in contrast to package100, package300is configured as a quad flat no-lead (QFN) package that includes a plurality of conductive terminals312exposed along a lower surface302aof mold compound302(which may be similar to mold compound102previously described). In addition, the die pad110is also aligned with and is exposed along the lower surface302a. The conductive terminals312may be coupled to the die150via wire bonds16as previously described for package100. Further, the package300may be secured to PCB12by coupling the plurality of conductive terminals312to the plurality of traces14with solder15. The examples disclosed herein include die pads that are configured to prevent excessive movement of a semiconductor die during a reflow process. For instance, in some examples, the example die pads may include a recess that is sized and shaped to constrain movement of the semiconductor die during a reflow process, even if the solder paste experiences unbalanced wetting forces. Thus, through use of the example die pads disclosed herein, a desired position and alignment of semiconductor die may be maintained on a die pad during a reflow process, so that instances of die misalignment may be reduced in a semiconductor package manufacturing process. The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A. A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims. | 21,429 |
11862539 | For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art, in one or more embodiments. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein. DETAILED DESCRIPTION OF THE DRAWINGS FIG.1illustrates a cross-sectional view of a packaged electronic device10, such as a packaged semiconductor device10in accordance with a first embodiment. In accordance with the present embodiment, packaged semiconductor device10includes a pad11, flag11, die attach pad11, die pad11, or support pad11and leads12or terminals12disposed proximate to, but separated from, pad11. In one embodiment, an electronic device16, electronic component16, or electronic die16, such as a semiconductor device16or semiconductor die16is connected to or attached to pad11using an attach material17. In some embodiments, semiconductor device16is an integrated circuit device, a power semiconductor device, an optical device, a sensor device, or other devices as known to those skilled in the art. By way of example, attach material17can be a solder paste, a conductive epoxy, conductive adhesives, conductive films, non-conductive epoxy, non-conductive adhesives, non-conductive films, or other suitable attach materials as known to those skilled in the art. In some embodiments, non-conductive refers to electrically insulating and it is understood that such materials may still be thermally conductive. Those skilled in the art will appreciate that electronic device16is illustrated in simplified form, and may further include multiple diffused regions, multiple conductive layers, and multiple dielectric layers. In accordance with the present embodiment, leads12comprise a unique shape compared to related devices. As illustrated inFIG.1, one or more leads12include a thick terminal portion120or thick lead portion120, and a thin terminal portion121or thin lead portion121. Stated differently, thick terminal portion120has a greater thickness or height compared to thin terminal portion121in cross-sectional view to provide a shelf portion122or step portion122. In accordance with the present embodiment, thick terminal portion120is disposed distal to pad11and thin terminal portion121is disposed proximate to pad11. In one embodiment, thick terminal portion120laterally abuts thin terminal portion121, with thin terminal portion121interposed between thick terminal portion120and pad11. In the present embodiment, thick terminal portion120includes an outward facing side surface126, conductive side surface126, outward facing flank surface126, or flank surface126that is configured for receiving a conductive layer26. In some embodiments, flank surface126is laterally recessed inward as generally illustrated inFIG.1and can be described as outward facing recessed side surface126. In this embodiment, conductive layer26includes a vertical portion260and a horizontal portion261. Horizontal portion261can be at least partially arcuate instead of straight or linear, such as in cases where etching is used instead of sawing to form outward facing flank surface126. In most embodiments, conductive layer26is further disposed adjacent a bottom facing surface125or lower surface125of leads12. In accordance with the present embodiment, thick terminal portion120includes a portion1200or outward facing portion1200that does not include conductive layer26. In accordance with the present embodiment, portions1200are absent conductive material26because portions1200are exposed or formed after conductive layer26is formed. In some embodiments, thin terminal portion121includes an inward facing side surface128that laterally opposes outward facing side surface126in cross-sectional view. In some embodiments, inward facing side surface128is laterally recessed inward as generally illustrated inFIG.1and can be described as inward facing recessed side surface128. By way of example, inward facing side surface128and outward facing side surface126can be laterally recessed up to about 60 microns. In other embodiments, inward facing side surface128is not recessed. In accordance with the present embodiment, inward facing side surface128has a height129or thickness129that is less than a height131or thickness131of outward facing side surface126. In some embodiments, height131is greater than about 140 microns and height129is less than about 130 microns. By way of example, height131is in a range from about 140 microns through about 200 microns or more. In the same or other embodiments, height131can be at least approximately 10% greater than height129or more, such as approximately 50% greater than height129. In accordance with the present embodiment, the total height133or thickness133of thick terminal portion120can be up to about 250 microns or more, which is different from previous devices that have leads with a standard full thickness of less than 200 microns. This difference provides flank surface126with a taller surface or increased surface area compared to prior devices having flank surfaces less than 130 microns in height. In accordance with the present embodiment, the taller flank surface126provides more solderable surface area for attaching packaged electronic device10to a next level of assembly, which improves bond integrity and reliability. In addition, this enhances the ability to perform any necessary visual inspections of the bonded surfaces. Packaged electronic device10further includes conductive connective structures19attached to a major surface of semiconductor device16and further connected to one or more leads12. In some embodiments, one or more or all of conductive connective structures19are attached to top surfaces123of thin terminal portion121. In other embodiments, one or more or all of conductive connective structures19are attached to top surfaces124of thick terminal portion120. In some embodiments, it is preferred to attach conductive connective structures19to top surfaces124because top surfaces124are not etched surfaces, which can provide a more reliable surface for attaching conductive connective structures19. In other embodiments, it is preferred to attach conductive connective structures19to top surfaces123of thin terminal portions121to support a thinner package body. By way of example, conductive connective structures19comprise gold or copper wires or other materials as known to those skilled in the art. It is understood that other conductive connective structures, such as clips, ribbon bonds, or other structures known to those skilled in the art can be used instead of, or in addition to, the conductive wires. In addition, direct chip attachment methods can be used, which will be illustrated, for example, withFIG.3. Packaged electronic device10further includes a package body36that covers or encapsulates conductive connective structures19, semiconductor die16, at least portions of leads12, and at least portions of pad11while, in some embodiments, leaving lower or bottom surfaces125of leads12, flank surfaces126of leads12, and lower surface110of pad11exposed to the outside of packaged electronic device10as generally illustrated inFIG.1. In some embodiments, package body36can be polymer based composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Package body36comprises a non-conductive and environmentally protective material that protects electronic device16from external elements and contaminants. Package body36may be formed using paste printing, compressive molding, transfer molding, over-molding, liquid encapsulant molding, vacuum lamination, other suitable applicator, or other processes as known to those of skill in the art. In some embodiments, package body36is an epoxy mold compound (“EMC”) and can be formed using transfer or injection molding techniques. In accordance with the present embodiment, conductive side surfaces126or outward facing flank surfaces126are exposed through side surfaces360of package body36, and are further covered by conductive layer26, which can be a solderable layer26. By way of example, conductive layer26comprises tin (Sn) and can be formed using plating techniques. In some embodiments, conductive layer26is further disposed on lower surfaces125of leads12and on lower surface110of pad11as generally illustrated in FIG.1. In other embodiments, lower surface110may not be exposed to the outside of packaged electronic device10. FIG.2illustrates a partial cross-sectional view of a portion of packaged electronic device10attached to a next level of assembly200, such as a printed circuit board200having conductive traces201and202disposed proximate to a first surface203. In accordance with the present embodiment, outward facing flank surface126of lead12has about 55% more surface area for conductive layer26compared to related devices, which provides about a 55% increase in wettable flank surface area for solder attach material24. In accordance with the present embodiment, this improves the solder joint strength and the reliability of the assembled component compared to related devices. In addition, this enhances the ability to perform any necessary visual inspections of the bonded surfaces. FIG.3illustrates a cross-sectional view of a packaged electronic device30, such as a packaged semiconductor device30in accordance with another embodiment. Packaged electronic device30is similar to packaged electronic device10and only the differences will be described hereinafter. In packaged electronic device30, electronic device16, such as semiconductor device16is directly attached to leads12and pad11in a flip-chip configuration. In some embodiments, conductive bumps31are used to attach electronic device16to leads12and pad11. In some embodiments, conductive bumps31comprise temperature reflowed solder bumps and/or pillar bumps (e.g., copper pillar bumps that can have corresponding solder tips), thermosonic or thermocompression bonded bumps (e.g., gold bumps), adhesively bonded bumps, or other bump materials known to those skilled in the art. In some embodiments, conductive bumps31are first applied to bond pads32on electronic device16while in wafer form. In one embodiment, electronic device16is directly attached to top surfaces123of thin terminal portions121. In other embodiments, electronic device16can be directly attached to top surfaces124of thick terminal portions120. In some embodiments, package body36provides an underfill structure for electronic device16. In additional embodiments, a separate underfill material can be used and formed prior to forming package body36. FIG.4illustrates a partial cross-sectional view of a packaged electronic device40, such as a packaged semiconductor device40in accordance with a further embodiment. Packaged electronic device40is similar to packaged electronic device10and only the differences will be described hereinafter. In packaged electronic device40, a different configuration of lead12is provided. In packaged electronic device40lead12does not have a thin terminal portion121, but instead consists of a thick terminal portion120only. In this configuration, lead12still includes outward facing recessed flank surface126and inward facing recessed side surface128that laterally opposes outward facing flank surface126in cross-sectional view. In accordance with the present embodiment, outward facing flank surface126has height131greater than the height129of inward facing side surface128as described with packaged electronic device10. In the present embodiment, conductive connective structures19are attached to top surface124of thick terminal portion120as generally illustrated inFIG.4. FIG.5is a flow chart of a method of manufacturing a packaged electronic device, such as packaged electronic device10in accordance with one embodiment. The method includes a step510of providing a conductive substrate having thick and thin terminal features. By way example, this can include thick terminal portions120and thin terminal portions121illustrated inFIG.1. Stated a different way, step510can include providing a conductive substrate having an outward facing recessed side surface and an opposing inward facing recessed side surface that has a smaller height than the outward facing recessed side surface, such as in the embodiment illustrated inFIG.4. The method includes a step520of electrically connecting electronic components to the conductive substrate. In some embodiments, the electronic components can include one or more electronic devices16, such as semiconductor devices16. The method includes a step530of forming a package body to encapsulate the electronic components and portions of the conductive substrate to provide an encapsulated subassembly. In some embodiments, the package body can include package body36. The method includes a step540of exposing portions of the thick terminal features including side portions of the thick terminal features. By way of example, the side portions can include outward facing side surfaces126. Step550includes forming a solderable material on portions of the conductive substrate including exposed portions of the thick terminal features. In some embodiments, the solderable material can be conductive layer26and the exposed portions of the conductive substrate include outward facing side surfaces126, and can also include one or more of lower surfaces125of leads12and lower surface110of pad11. Step560includes singulating the encapsulated subassembly to provide package electronic devices having thick terminal features with enhanced wettable flanks. In accordance with the present embodiment, the wettable flanks comprise outward facing side surfaces126having conductive layer26disposed thereon, which have an increased height and thus an increased surface area for bonding compared to related devices. Turning now toFIGS.6-13, which illustrate cross-sectional views of packaged electronic devices at various stages of fabrication, the method ofFIG.5will be further described in accordance with a first embodiment. In the present embodiment, step510ofFIG.5is illustrated inFIGS.6-9. InFIG.6a substrate61, such as a conductive substrate61is provided. In some embodiments, substrate61comprises a generally flat plate of copper, a copper alloy, nickel-iron-cobalt alloys, iron-nickel alloys (e.g., Alloy42), plated materials, or other materials known to those skilled in the art. In accordance with the present embodiment, substrate61has thickness611that is greater than substrates used for related devices to provide outward facing side surfaces126with increased height for enhanced wettable flank surfaces. In accordance with the present embodiment, thickness61can be 225 microns or more, such as about 250 microns, compared to related devices where the substrate thickness is less than 200 microns. In one embodiment, a masking layer62is provided on a major surface63of substrate61, and a masking layer64is provided on a major surface66of substrate61. Masking layer62includes openings67that expose portions of major surface63for additional processing. In some embodiments, masking layer64is provided without openings. Masking layers62and64can comprise photosensitive materials, such as photoresist materials, polymer materials, dielectric materials, or other masking materials known to those skilled in the art. FIG.7illustrates substrate61after additional processing. In one embodiment, portions of substrate61are removed extending inward from major surface63through openings67to provide recessed surfaces630. In some embodiments, a heated spray etch apparatus is used to form recessed surfaces630. In some embodiments, masking layers62and64are the removed and substrate61is rinsed and dried for further processing. FIG.8illustrates substrate61after masking layers82and84are disposed on major surfaces63,630, and66of substrate61. Masking layers82and84can be photoresist layers patterned to provide openings87and88that expose portions of major surface66and recessed surface630respectively as generally illustrated inFIG.8. In accordance with the present embodiment, openings87are wider than openings88. In a subsequent step, exposed portions of substrate61are then removed to provide leads12and pads11as generally illustrated inFIG.9. In accordance with the present embodiment, leads12are provided with thick terminal portions120and thin terminal portions121. Further, this step provides thin terminal portions121with inward facing recessed surfaces128. In some embodiments, an etching process is used to remove the exposed portions of substrate61in openings87and88. Masking layers82and84can then be removed and substrate62can be rinsed and dried for additional processing. Those skilled in the art will appreciate that the edges of the etched features of substrate61may not be straight lines, but can be rounded or scalloped in cross-sectional view. In other embodiments, the features of substrate61can be formed using stamping techniques, chemical stamping techniques, laser cutting techniques, grinding techniques or other techniques as known to those skilled in the art including in combination with chemical etching. Although not shown, the elements of substrate61are typically held together using tie bars and surrounding frame structures for additional processing. In accordance with the present embodiment, substrate61is configured as a conductive leadframe substrate. FIG.10illustrates substrate61after electronic devices16, such as semiconductor devices16, are electrically connected to portions of substrate61in accordance with step520ofFIG.5. In one embodiment, electronic devices16are attached to pads11using attach material17described previously. Conductive connective structures19can then be attached to electronic devices16and leads12. As set forth previously, conductive connective structures19can be attached to either top surface124of thick terminal portions120, or to top surface123of thin terminal portion121, or combinations thereof can be used. It is understood that other types of conductive connective structures19can be used, such as clips and/or ribbon bonds in any combination including combinations with conductive wire bonds. In addition, in step520electronic devices16can be attached to pads11and leads12in a flip-chip configuration as described inFIG.3. FIG.11illustrates substrate61after forming package body36in accordance with step530ofFIG.5. In one embodiment, package body36is provided to encapsulate electronic devices16, conductive connective structures19, portions of leads12, and portions of die pads11to provide an encapsulated subassembly531. In the present embodiment, lower surfaces110of die pads11and lower surfaces125of leads12are exposed to the outside of package body36. As set forth previously, package body36can be polymer based composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Package body36comprises a non-conductive and environmentally protective material that protects electronic device16from external elements and contaminants. Package body36may be formed using paste printing, compressive molding, transfer molding, over-molding, liquid encapsulant molding, vacuum lamination, other suitable applicator, or other processes as known to those of skill in the art. In some embodiments, package body36is an EMC, and can be formed using transfer or injection molding techniques. FIG.12illustrates encapsulated subassembly531after exposing portions of thick terminal portions120of leads12including outward facing side surfaces126in accordance with step540ofFIG.5. In one embodiment, a partial sawing process is used to remove a portion of thick terminal portions120of leads12extending inward from lower surfaces125. In one embodiment, the sawing process does not extend all the way through thick terminal portions120so that adjoining thick terminal portions120in adjacent units remain physically connected as illustrated inFIG.12by element1201. This physical connection facilitates electrical communication for an electroplating process to form conductive layer26on outward facing side surfaces126. In other embodiments, other removal techniques are used instead of or in combination with the sawing process. By way of example, etching, grinding, and/or laser removal processes can be used as well as other removal processes known to those skilled in the art. Next, in some embodiments encapsulated subassembly531can be attached to a belt finger portion of an electroplating apparatus, which suspends the subassembly within a plating solution to form conductive layers26on exposed portions of substrate61, including outward facing side surfaces126of thick terminal portions120, lower surfaces125of leads12, and lower surfaces110of pads11in accordance with step550ofFIG.5. In accordance with the present embodiment, conductive layer26includes vertical portions260and horizontal portions261on thick terminal portions120. Conductive layer26can be solderable materials, such as tin, cadmium, gold, silver, palladium, rhodium, copper, copper alloys, combinations thereof, or similar materials known to those skilled in the art. In some embodiments, a nickel barrier layer can be used before plating the solderable materials. In some embodiments, conductive layer26can have a thickness in a range from about 2 microns to about 20 microns. FIG.13illustrates encapsulated subassembly531after a singulation step to separate the subassembly into individual packaged electronic devices10in accordance with step560ofFIG.5. In some embodiments, a sawing process can be used to singulate the individual devices along singulation line561, which forms side surfaces360of package bodies36and portions1200of leads12that are absent conductive layer26. This step provides individual packaged electronic devices10each having outward facing side surfaces126that are recessed and provided with conductive layers126configured to provide increased surface area or enhanced wettable flanks for attaching packaged electronic devices10to a next level of assembly, such as a printed circuit board200as illustrated inFIG.2. Turning now toFIGS.14-20, which illustrate cross-sectional views of packaged electronic devices at various stages of fabrication, the method ofFIG.5will be further described in accordance with another embodiment. In the present embodiment, step510ofFIG.5of providing a conductive substrate is illustrated inFIGS.14-15. InFIG.14, a conductive pattern411is formed on a first surface418of a carrier400. Carrier400further includes a second surface419that is opposite to the first surface418. In one embodiment, carrier400has a thickness in a range from approximately 3 microns through 300 microns. In some embodiments, carrier400may be formed of one or more of a metal, silicon, glass, an epoxy resin or other materials known to those skilled in the art. At least the first surface418is prepared and cleaned for receiving the first conductive pattern411. In one embodiment, conductive pattern411may be made of a conductive material comprising copper (Cu), gold (Au), silver (Ag), aluminum (Al) or other materials as known to those skilled in the art. In addition, conductive pattern411may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal sputtering, metal evaporation, electrolytic or electroless plating or other formation techniques known to those skilled in the art. In some embodiments, conductive pattern411has a thickness in a range from approximately 3 microns through 50 microns. After deposition, the conductive material may be patterned by physical etching or chemical etching, or other techniques known to those skilled in the art. In other embodiments, a masking layer (not shown) may be first deposited on the first major surface418and the conductive material subsequently deposited. The masking layer may or may not be removed after the conductive pattern is formed depending on the application. In accordance with the present embodiment, conductive pattern411forms portions of leads12and pads11for a substrate611. In some embodiments, portions of conductive pattern411can be referred to as conductive traces411or traces411. Next, referring toFIG.15, conductive pillars412are provided on portions of conductive pattern411that will be used as leads12of substrate611. Conductive pillars412are formed to extend away or outward from conductive pattern411and away from first surface418of carrier400. In one embodiment, conductive pillars412are preferably formed of a material having good electrical, thermal conductivity, such as copper (Cu), a copper alloy or similar materials as known to those skilled in the art. In some embodiments, conductive pillars412have a thickness in a range from approximately 30 microns through 300 microns. In addition, conductive pillars412may be formed using PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating or other formation techniques as known to those of skill in the art. Photomasking and etch techniques can be used to form conductive pillars412in desired shapes, such as cuboid shapes. In one embodiment, electrolytic or electroless plating techniques are used with a masking layer provided over the first major surface418and having a preselected pattern for forming the first conductive pillars412in desired locations on conductive pattern411. In accordance with the present embodiment, conductive pillars412have a narrower width than conductive pattern411where conductive pillars412are formed. In accordance with the present embodiment, conductive pillars412(and those portions of conductive pattern411disposed below conductive pillars412) are configured to provide thick terminal portions120of leads12, and those portions of conductive pattern411adjacent to, but not covered by, conductive pillars412are configured to provide thin terminal portions121of leads12. Those portions of conductive pattern411not provided with conductive pillars are configured to provide pads11. In accordance with the present embodiment, substrate611is configured as a build-up substrate. From this point forward in the description ofFIGS.16-20, leads12and pads11designations will be used with substrate611. FIG.16illustrates substrate611after electronic devices16are electrically connected to portions of substrate611in accordance with step520ofFIG.5. In one embodiment, electronic devices16are attached to pads11using attach material17described previously. Conductive connective structures19can then be attached to electronic devices16and leads12. As set forth previously, conductive connective structures19can be attached to either top surface124of thick terminal portions120, or to top surface123of thin terminal portion121, or combinations thereof can be used. It is understood that other types of conductive connective structures19can be used, such as clips and/or ribbon bonds in any combination including combinations with conductive wires. In addition, in step520electronic devices16can be attached to pads11and leads12in a flip-chip configuration as described inFIG.3. FIG.17illustrates substrate611after forming package body36in accordance with step530ofFIG.5. In one embodiment, package body36is provided to encapsulate electronic devices16, conductive connective structures19, portions of leads12, and portions of die pads11to provide an encapsulated subassembly531. In the present embodiment, lower surfaces110of die pads11and lower surfaces125of leads12are exposed to the outside of package body36adjoining major surface418of carrier400. Package body36can be the same materials and can formed using the same processes as described previously and the description will not be repeated again here. Carrier400can then be removed to provide an encapsulated subassembly631as illustrated inFIG.18. FIG.19illustrates encapsulated subassembly631after exposing portions of thick terminal portions120of leads12including outward facing side surfaces126in accordance with step540ofFIG.5. In one embodiment, a partial sawing process is used to remove a portion of thick terminal portions120of leads12extending inward from lower surfaces125. In one embodiment, the sawing process does not extend all the way through thick terminal portions120so that adjoining thick terminal portions120in adjacent units remain physically connected as illustrated inFIG.19by element1201. This physical connection facilitates electrical communication for an electroplating process to form conductive layer26on outward facing side surfaces126. In other embodiments, other removal techniques are used instead of or in combination with the sawing process. By way of example, etching, grinding, and/or laser removal processes can be used as well as other removal processes known to those skilled in the art. Next, in some embodiments encapsulated subassembly631can be attached to a belt finger portion of an electroplating apparatus, which suspends the subassembly within a plating solution to form conductive layers26on exposed portions of substrate61, including outward facing side surfaces126of thick terminal portions120, lower surfaces125of leads12, and lower surfaces110of pads11in accordance with step550ofFIG.5. In accordance with the present embodiment, conductive layer26includes vertical portions260and horizontal portions261on thick terminal portions120. Conductive layer26can be the same materials as described previously and the description will not repeated again here. FIG.20illustrates encapsulated subassembly631after a singulation step to separate the subassembly into individual packaged electronic devices101in accordance with step560ofFIG.5. In some embodiments, a sawing process can be used to singulate the individual devices along singulation lines661, which forms side surfaces360of package bodies36and portions1200of leads12that are absent conductive layer26. This step provides individual packaged electronic devices101each having outward facing side surfaces126that are recessed and provided with conductive layers126configured to provide increased surface area or enhanced wettable flanks for attaching packaged electronic devices101to a next level of assembly, such as a printed circuit board200as illustrated inFIG.2. Turning now toFIGS.21-28, which illustrate cross-sectional views of packaged electronic devices at various stages of fabrication, the method ofFIG.5will be further described in accordance with a further embodiment. In the present embodiment, step510ofFIG.5of providing a conductive substrate is illustrated inFIGS.21-25. InFIG.21, a conductive pattern711is formed on a first surface718of a carrier700. Carrier700further includes a second surface719that is opposite to the first surface718. In one embodiment, carrier700has a thickness in a range from approximately 3 microns through 300 microns. In some embodiments, carrier700may be formed of one or more of a metal, silicon, glass, an epoxy resin or other materials known to those skilled in the art. At least the first surface718is prepared and cleaned for receiving the first conductive pattern711. In one embodiment, conductive pattern711may be made of a conductive material comprising copper (Cu), gold (Au), silver (Ag), aluminum (Al) or other materials as known to those skilled in the art. In addition, conductive pattern711may be formed by PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating or other formation techniques known to those skilled in the art. In some embodiments, conductive pattern711has a thickness in a range from approximately 3 microns through 50 microns. After deposition, the conductive material may be patterned by physical etching or chemical etching, or other techniques known to those skilled in the art. In other embodiments, a masking layer (not shown) may be first deposited on the first major surface718and the conductive material subsequently deposited. The masking layer may or may not be removed after the conductive pattern is formed depending on the application. In accordance with the present embodiment, conductive pattern711forms portions of leads12and traces714for a substrate612. Next, referring toFIG.22, a conductive pillar712is provided on a portion of conductive pattern711that will be used for leads12of substrate612. Conductive pillar712is formed to extend away or outward from conductive pattern711and away from first surface718of the carrier700. In one embodiment, conductive pillar712is preferably formed of a material having good electrical, thermal conductivity, such as copper (Cu), a copper alloy or similar materials as known to those skilled in the art. In one embodiment, conductive pillars712have a thickness in a range from approximately 30 microns through 300 microns. In addition, conductive pillars712may be formed using PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating or other formation techniques as known to those of skill in the art. Photomasking and etch techniques can be used to form conductive pillars712in desired shapes, such as cuboid shapes. In one embodiment, electrolytic or electroless plating techniques are used with a masking layer provided over the first major surface718and having a preselected pattern for forming the first conductive pillars712in desired locations on conductive pattern711. In accordance with the present embodiment, conductive pillar712has a narrower width than conductive pattern711where conductive pillar712is formed. In accordance with the present embodiment, conductive pillar712(and that portion of conductive pattern711disposed below conductive pillar712) is configured to provide thick terminal portions120of leads12, and those portions of conductive pattern711adjacent to, but not covered by, conductive pillar712are configured to provide thin terminal portions121of leads12. In accordance with the present embodiment, substrate612is configured as a molded substrate. From this point forward in the description ofFIGS.23-28, lead12and traces714designations will be used with substrate612. FIG.23illustrates substrate612after additional processing. In one embodiment, substrate612is encapsulated with a molded layer736that covers or encapsulates lead12, traces714, and exposed portions of carrier700. Molded layer736can be polymer based composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Molded layer736may be formed using paste printing, compressive molding, transfer molding, over-molding, liquid encapsulant molding, vacuum lamination, other suitable applicator, or other processes as known to those of skill in the art. In some embodiments, molded layer736is an EMC, and can be formed using transfer or injection molding techniques. In one embodiment, molded layer736is provided to extend over the top of thick terminal portion120of lead12. In a subsequent step, a portion of molded layer736can be removed to expose an outer surface1240of thick terminal portion120of lead12as illustrated inFIG.24. In some embodiments, portions of molded layer736can be removed using grinding techniques, etching techniques, combination thereof, or other removal techniques known to those skilled in the art. In other embodiments, molded layer736can be as-formed with the top surface of thick terminal portion120exposed by placing an upper mold plate adjacent to thick terminal portion120during the molding process. In the alternative, film-assisted molding can be used. FIG.25illustrates substrate612after carrier700is removed to expose traces714and leads12to the outside for further processing. In accordance with the present embodiment, substrate612is configured as a molded substrate and has been flipped or rotated 180 degrees fromFIG.24. FIG.26illustrates substrate612after electronic devices16are electrically connected to portions of substrate612in accordance with step520ofFIG.5. In one embodiment, electronic devices16are attached in a flip-chip configuration to traces714and leads12using conductive bumps31. In some embodiments, conductive bumps31temperature reflowed solder bumps, thermosonic or thermocompression bonded bumps (e.g., gold bumps), adhesively bonded bumps, or other bump materials as known to those skilled in the art. In some embodiments, conductive bumps are first applied to bond pads (not shown) on electronic devices16while in wafer form. In one embodiment, electronic device16is attached to lead12such that a peripheral edge160of electronic die16extends to only overlap thin terminal portion121. In other embodiments, electronic device16is attached to lead12such that peripheral edge160of electronic die16extends to overlap at least a portion of thick terminal portion120. In some embodiments, package body36provides an underfill structure for electronic device16. In additional embodiments, a separate underfill material can be used and can be formed prior to forming package body36. FIG.26further illustrates substrate612after forming package body36in accordance with step530ofFIG.5. In one embodiment, package body36is provided to encapsulate electronic devices16, portions of leads12, and portions of traces714provide an encapsulated subassembly731. Package body36can be the same materials and can formed using the same processes as described previously and the description will not be repeated again here. FIG.27illustrates encapsulated subassembly731after exposing portions of thick terminal portions120of leads12including outward facing side surfaces126in accordance with step540ofFIG.5. In one embodiment, a partial sawing process is used to remove a portion of thick terminal portions120of leads12extending inward from outer surface1240of thick terminal portions120. In one embodiment, the sawing process does not extend all the way through thick terminal portions120so that adjoining thick terminal portions120in adjacent units remain physically connected as illustrated inFIG.27by element1201. This physical connection facilitates electrical communication for the electroplating process to form conductive layer26on outward facing side surfaces126. In another embodiment, the removal process completely separates the conductive pillar712portion of lead12, but terminates proximate to underlying conductive pattern711so that conductive pattern711remains intact (i.e., conductive pattern711provides element1201) to facilitate electrical communication for the electroplating process to form conductive layer26. In other embodiments, other removal techniques are used instead of or in combination with the sawing process. By way of example, etching, grinding, and/or laser removal processes can be used as well as other removal processes known to those skilled in the art. Next, in some embodiments encapsulated subassembly731can be attached to a belt finger portion of an electroplating apparatus, which suspends the subassembly within a plating solution to form conductive layers26on exposed portions of thick terminal portions120in accordance with step550ofFIG.5. In accordance with the present embodiment, conductive layer26includes vertical portions260and horizontal portions261on thick terminal portions120. Conductive layer26can be the same materials as described previously and the description will not repeated again here. FIG.28illustrates encapsulated subassembly731after a singulation step to separate the subassembly into individual packaged electronic devices102in accordance with step560ofFIG.5. In some embodiments, a sawing process can be used to singulate the individual devices along singulation lines761, which forms side surfaces360of package bodies36and portions1200of leads12that are absent conductive layer26. This step provides individual packaged electronic devices102each having outward facing side surfaces126that are recessed and provided with conductive layers126configured to provide increased surface area or wettable flanks for attaching packaged electronic devices102to a next level of assembly, such as a printed circuit board200as illustrated inFIG.2. FIG.29illustrates a partial cross-sectional view of substrate612in accordance with an alternative embodiment. In the present embodiment, conductive pattern711is recessed below a major surface737of molded layer736. The recessed surfaces can be formed using, for example, masking and etching techniques. One advantage of providing conductive pattern711as recessed is that it can facilitate alignment of electronic device16to substrate612. In view of all of the above, it is evident that a novel structure and method of providing the structure has been disclosed that includes a lead structure having an outwardly facing side surface with enhanced surface area for providing a wettable flank. More particularly, the outward facing side surface has an increased height for receiving a solderable layer compared to related devices. In some embodiments the lead structure includes a thick terminal portion that has the outwardly facing side surface and a thin terminal portion having an inwardly facing side surface that is absent the solderable layer. An electronic device can be electrically connected to either the thick terminal portion or the thin terminal portion. The lead structure can be provided as part of, for example, a lead frame structure, a build-up substrate structure, or a molded substrate structure. The exposed side surface provides an enhanced wettable flank surface that improves the bond integrity when the packaged electronic device is attached to a next level of assembly, such as a printed circuit board. In addition, the increased height enhances optical inspection of solder joints formed between the packaged electronic device and the next level of assembly. The structure and method provide for improved reliability by facilitating stronger solder joints compared to previous approaches. While the subject matter of the invention is described with specific preferred embodiments and example embodiments, the foregoing drawings and descriptions thereof depict only typical embodiments of the subject matter, and are not therefore to be considered limiting of its scope. It is evident that many alternatives and variations will be apparent to those skilled in the art. By way of example, multiple electronic devices can be attached to a substrate in side-by-side configurations, in stacked configurations, combinations thereof, or other configurations known to those skilled in the art. In addition, the packaged electronic device can leads on less than all sides of the package body. As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Detailed Description of the Drawings, with each claim standing on its own as a separate embodiment of the invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and meant to form different embodiments as would be understood by those skilled in the art. | 46,186 |
11862540 | DETAILED DESCRIPTION Reference is made toFIG.4which shows a top view of a quad flat packaging (QFP) type leadframe110. The leadframe110is made from a sheet of metal material, for example a copper or a copper alloy material, having a thickness of, for example, 100-300 μm. The leadframe110is fabricated to include a number of structures, with the fabrication generally comprising some form of stamping or etching operation to define the size and shape of the structures. The included structures of the leadframe110comprise a die pad112that generally has the shape of quadrilateral, such as a rectangular shape or a square shape (as shown), in top view. The area of the die pad112is sized to receive and support an integrated circuit (IC) chip (not shown; seeFIGS.5A-5B) which is mounted to the upper surface of the die pad. The leadframe110structures further comprise a plurality of tie bars114which are connected to the die pad112and extend away from the die pad. The tie bars114primarily function to support the die pad112, and the mounted IC chip, within the mold cavity during the transfer molding process. In the illustrated example ofFIG.4, the tie bars114radially extend away from the die pad112from the four corners of the quadrilaterally-shaped die pad. In an alternative embodiment, the tie bars114may extend perpendicularly from the four side edges of the quadrilaterally-shaped die pad. The tie bars114include an internal tie bar portion104and an external tie bar portion108. The internal tie bar portion104provides the portion of each tie bar114which will be encapsulated by the molding material within the resulting IC package. The external tie bar portion108will be outside the resulting IC package and is typically discarded. The leadframe110structures further comprise a plurality of leads116which extend from, but are not directly connected to, the four side edges of the die pad112. The leads116include an internal lead portion118and an external lead portion120. The internal lead portion118provides the portion of each lead116which will be encapsulated by the molding material within the resulting IC package and to which the mounted IC chip is electrically connected. The external lead portion120provides the portion of each lead116which will extend externally from the resulting IC package. The leads116are connected to each other and to the tie bars114using a dam bar124structure of the leadframe110which extends parallel to, and is spaced apart from, each side edge of the die pad112. The dash-dotted outline indicates the general extent of the mold cavity152for the transfer molding process (the extent of the mold cavity generally coinciding with (adjacent to) the inside edge of the dam bar124). The dashed outline indicates the extent of a leadframe unit which may be replicated and tiled to form a frame which includes a plurality of leadframe units arranged in a matrix format. The internal tie bar portion104extends between the die pad and the dam bar, and the external tie bar portion108extends from the dam bar to the perimeter edge of the leadframe unit (for example, at a perimeter corner thereof). Similarly, the internal lead portion118extends between adjacent the die pad and the dam bar, and the external lead portion120extends from the dam bar to the perimeter edge of the leadframe unit (for example, at a perimeter side edge thereof). FIG.5Aillustrates a cross-section of the leadframe110taken along line A-A inFIG.4. Although the upper surface of the die pad14is illustrated in this cross-section to be co-planar with the upper surface of the leads16, it will be understood that this is just an example and that some leadframe configurations utilize a sunken die pad which is positioned below the leads.FIG.5Billustrates a cross-section of the leadframe110taken along line B-B inFIG.4. The IC chip is mounted to the die pad112and bonding wires130electrically connect pads on the upper surface of the IC chip to a proximal end of the internal lead portion118of each lead116. The assembly of the leadframe110with the attached and wirebonded IC chip is clamped between an upper half150aand lower half150bof a two part mold150used in a transfer molding process to encapsulate the IC chip and produce a packaged IC device. The mold150defines a cavity152within which the die pad112, internal tie bar portions104of the tie bars114and internal lead portions118of the leads116are located. The external lead portion120of each lead116extends beyond the cavity152and is clamped by the mold150. Likewise, the external tie bar portion108of each tie bar114extends beyond the cavity and is clamped by the mold150. The mold cavity152is connected through a gate156to a mold runner158that is filled with an encapsulation material (generally, a mold compound such as a resin or epoxy-based material). In response to an applied force, the encapsulation material is delivered by the mold runner158and injected into the cavity152through the gate156. The flow rate of the encapsulation material is controlled by the applied force, the lengths and cross-sections of the mold runner158, the cross-section of the gate156, the temperature, and the viscosity and flow characteristics of the encapsulation material. Following injection, the encapsulation material solidifies to form a package which encapsulates the IC chip. The resulting structure is then ejected from the mold150and the external lead portions120are severed and the dam bar124is cut to separate the leads116from each other. Furthermore, the external tie bar portions108the tie bars114located outside the package are removed (with the internal tie bar portions104ending at an outer surface of the package). The external lead portion120of each lead116is then bent to shape as needed. To address concerns with controlling the flow of encapsulation material into the mold cavity152during the transfer molding process, at least one of the tie bars114is configured to provide a mold flow control structure102within the mold cavity152. In particular, the internal tie bar portion104of the tie bar114corresponding to the location of the gate156is cut (reference106; using the stamping or etching operation) adjacent to the dam bar124. The part of the internal tie bar portion104of the tie bar114which remains connected to the die pad112is further bent out of a plane (reference101) coinciding with an upper surface of the tie bars in the direction of which is perpendicular to the plane defined by the top surface of the die pad112to form the mold flow control structure102. The bent portion of the part of the internal tie bar portion104of the tie bar114forms an acute angle Θ relative to the plane101for the top surface of the external tie bar portion108the tie bar114(and a corresponding obtuse angle Φ relative to the top surface of the die pad, where Θ=180°−Φ). WhileFIG.5Bshows a case where the cut internal tie bar portion104of the tie bar114has been bent in the direction of the upper half150aof the two part mold150, it will be understood that this is by example only and that the bend can instead be made in the direction of the lower half150bof the two part mold150. The location of the bend may, for example, coincide with the corner (or side edge) of the die pad112. Alternatively, the location of the bend may be positioned at a location along the length of the cut internal tie bar portion4of the tie bar114between the corner (or side edge) of the die pad112and the cut end of the tie bar. In the implementation shown byFIG.5B, the gate156is located at a corner of the mold cavity512corresponding to the location of one of the tie bars114. In an alternative implementation, the gate156may instead be located at a side edge of the mold cavity152, and again would correspond to the location of one of the tie bars114. It is common for a frame to be used which includes a plurality of leadframe units arranged in a matrix format. As noted above in connection withFIG.4, the dashed outline indicates the extent of each leadframe unit.FIG.6illustrates a portion of a frame where the matrix includes plural leadframe units arranged with one column and three rows. As an example, the frame may comprise a 3×10 matrix of leadframe units (three columns, ten rows) or a 4×15 matrix of leadframe units (four columns, fifteen rows). FIG.6further shows, in a schematic way, additional detail concerning the runner system158and gates156for a given column of leadframe units. Again, the dash-dotted outline indicates the general extent of each mold cavity152and each gate156from the mold runner158is positioned at a corner of the mold cavity where a tie bar114is located. The mold runner158extends parallel to the column and delivers the encapsulation material to each mold cavity152along that column. This system is replicated for each column of the plural columns included in the matrix. The flow of encapsulation material that is simultaneously injected into each mold cavity152along the column can be adjusted by changing the shape of the mold flow control structure102. This adjustment is effectuated in one way by controlled setting of the acute angle Θ. For example, each mold flow control structure102along the length of a given column can have an individually selected acute angle Θ. Indeed, in a preferred implementation, the acute angle Θ gradually changes (increasing or decreasing) from mold cavity152to mold cavity along the length of the column. Thus, the mold flow control structure102provided by the leadframe unit for a first cavity152(1) connected to the mold runner158along the length of the column can have an acute angle Θ(1), the mold flow control structure102provided by the leadframe unit for a second cavity152(2) connected to the mold runner158along the length of the column can have an acute angle Θ(2), and the mold flow control structure102provided by the leadframe unit for a third cavity152(1) connected to the mold runner158along the length of the column can have an acute angle Θ(3), where Θ(1)≠Θ(2)≠Θ(3) and, more specifically, Θ(1)<Θ(2)<Θ(3) as an example. In addition, a length L of the bent part of the internal tie bar portion104of the tie bar114forming the mold flow control structure102can be individually selected for each mold cavity along the length of the column. This is accomplished by selecting the location for making the cut106along the length of the cut106made to internal tie bar portion104of the tie bar114. Alternatively, this is accomplished by selecting the location for the making of the bend. Thus, the bent part of the internal tie bar portion104of the mold flow control structure102provided by the leadframe unit for a first cavity152(1) connected to the mold runner158along the length of the column can have a length L(1), the bent part of the internal tie bar portion104of the mold flow control structure102provided by the leadframe unit for a second cavity152(2) connected to the mold runner158along the length of the column can have a length L(2), and the bent part of the internal tie bar portion104of the mold flow control structure102provided by the leadframe unit for a third cavity152(1) connected to the mold runner158along the length of the column can have a length L(3), where L(1) L(2) L(3) and, more specifically, L(1)<L(2)<L(3) as an example. The provision of the mold flow control structure102in general, and the controlled selection of angle Θ and length L for the bent part of the internal tie bar portion104in particular, assists in balancing the flow of encapsulation material to each mold cavity152along the column of the matrix so as to reduce the likelihood of a wire sweep and/or mold void occurrence. While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. | 12,145 |
11862541 | DETAILED DESCRIPTION The embodiments described herein provide a molded semiconductor package that has a negative standoff between the leads and the bottom main surface of the mold compound. That is, each lead of the package terminates outside the mold compound in a plane coplanar with the bottom main surface of the mold compound or in a plane above the bottom main surface of the mold compound. This way, the total height tolerance of the molded semiconductor package includes the height tolerance of the mold compound but not the height tolerance of the leads. Other tolerances which contribute to the total height tolerance of the molded semiconductor package may include solder tolerance, in the case of the leads being attached to a circuit board by solder, and a cooling structure tolerance, in the case of a cooling structure being used to cool the package. Since the leads of the molded semiconductor package have a negative standoff, the height tolerance of the leads is not a factor in determining the thickness of a thermal interface material which thermally contacts the topside of the molded package body to the bottom side of the housing or other type of cooling structure, thereby lowering the overall height tolerance of the package. FIG.1illustrates a cross-sectional view of an embodiment of a molded semiconductor package100of the leaded type. The molded semiconductor package100includes a mold compound102, leads104and at least one semiconductor die (chip)106embedded in the mold compound102. The mold compound102has a top main surface108, a bottom main surface110opposite the top main surface108and side faces112extending between the top main surface108and the bottom main surface110. Any typical molding process such as injection molding, compression molding, film-assisted molding (FAM), reaction injection molding (RIM), resin transfer molding (RTM), map molding, blow molding, etc. may be used to embed the semiconductor die106in the mold compound102. Common mold compounds and resins include, but are not limited to, thermoset resins, gel elastomers, encapsulants, potting compounds, composites, optical grade materials, etc. Each lead104of the molded semiconductor package100has a first end114embedded in the mold compound102and a second end116protruding from a side face112of the mold compound102. Depending on the type of leaded package, the molded semiconductor package100may have leads104protruding from two, three or all four side faces112of the mold compound102. For example, in the case of a dual row leaded flat package such as SOP like SSO8 or TSOP, a first subset104′ of the leads104protrudes from a first side face112′ of the mold compound102and a second subset104″ of the leads104protrudes from a second side face112″ of the mold compound102opposite the first side face112′. In the case of a quad row leaded flat package such as QFP, the package would further include a third subset (out of view/not shown) of the leads104protruding from a third side face (out of view/not shown) of the mold compound102and a fourth subset (out of view/not shown) of the leads104protruding from a fourth side face (out of view/not shown) of the mold compound102. Regardless of the type of leaded package, the semiconductor die (chip)106embedded in the mold compound102is electrically connected, within the mold compound102, to the leads104. The electrical connections are illustrated as bond wires118. In general, any type of electrical conductor may be used to electrically connect the semiconductor die106to the leads104of the package100. For example, instead of or in addition to bond wires118, metal clips, metal ribbons, etc. may be used. The semiconductor die106embedded in the mold compound102may be attached to a die pad120of a lead frame or similar type of structure for supporting the die106. The leads104and the die pad120may be formed from the same lead frame, e.g., by stamping or etching. The die pad120is the region of a lead frame to which the semiconductor die106is attached. More than one semiconductor die106may be attached to the same die pad120and/or the molded semiconductor package100may include more than one lead frame with one or more semiconductor dies106attached to each corresponding die pad120. In each case, the second end116of each lead104of the molded semiconductor package100has a bottom surface122facing in the same direction as the bottom main surface110of the mold compound102. The bottom surface122of each lead104is coplanar with the bottom main surface110of the mold compound102, or disposed in a plane (‘Plane A’) above the bottom main surface110of the mold compound102. That is, the molded semiconductor package100has a negative standoff between the leads104and the bottom main surface110of the mold compound102. The term “negative standoff” as used herein means that no lead104of the molded semiconductor package100extends below the bottom main surface110of the mold compound102. In one embodiment, each lead104of the molded semiconductor package100is bent downward in a direction away from the top main surface108of the mold compound102and toward the bottom main surface110of the mold compound102, e.g., in a gull-wing like configuration, and terminates outside the mold compound102in a plane (‘Plane B’) coplanar with the bottom main surface110of the mold compound102or in a plane (‘Plane A’) above the bottom main surface110of the mold compound102, so that a total height tolerance (T_pkg) of the molded semiconductor package100includes a height tolerance (T_mc) of the mold compound102between the top and bottom main surfaces108,110but not a height tolerance (T_Id) of the leads104. The height tolerance T_mc of the mold compound102can be controlled precisely, e.g., to 100 μm. The molded semiconductor package embodiments described herein differ from conventional molded semiconductor packages with a positive lead standoff and which typically have a height tolerance of up to 300 μm. FIG.1shows each lead104of the molded semiconductor package100terminating outside the mold compound102in a first plane (‘Plane A’) which is above a second plane (‘Plane B’) in which the bottom main surface110of the mold compound102lies. The leads104themselves may terminate in different planes with respect to each other, depending on the way in which the leads104are bent, but in each case the bottom surface122of no lead104terminates outside the mold compound102in a plane below the bottom main surface110of the mold compound102. This way, the height tolerance T_Id of the leads104has no impact on the overall height tolerance T_pkg of the molded semiconductor package100. According to the embodiment shown inFIG.1, the bottom surface122of each lead104of the molded semiconductor package100is vertically offset from the bottom main surface110of the mold compound102by a distance d>0. In an embodiment, d ranges from 0.01 μm to 0.16 μm. According to the embodiment with the vertical offset, the bottom surface122of each package lead104is disposed in a plane (‘Plane A’) above the bottom main surface110of the mold compound102, e.g., as shown inFIG.1. FIG.2illustrates another embodiment of a molded semiconductor package200having a negative standoff between the leads104and the bottom main surface110of the mold compound102. The embodiment illustrated inFIG.2is similar to the embodiment illustrated inFIG.1. Different, however, each lead104of the molded semiconductor package200illustrated inFIG.2terminates outside the mold compound102in the same plane (‘Plane A’=‘Plane B’) in which the bottom main surface110of the mold compound102lies. Hence, there is no vertical offset (d=0) between the bottom surface122of each lead104of the molded semiconductor package200and the bottom main surface110of the mold compound102according to this embodiment. FIG.3illustrates another embodiment of a molded semiconductor package300having a negative standoff between the leads104and the bottom main surface110of the mold compound102. The embodiment illustrated inFIG.3is similar to the embodiment illustrated inFIG.1. Different, however, the top main surface108of the mold compound102of the molded semiconductor package300illustrated inFIG.3is initially formed or later thinned so that the die pad120or similar structure to which the semiconductor die106is attached is exposed at the top side of the molded semiconductor package300. If the semiconductor die106is not attached to a die pad of a lead frame or similar structure, the side of the semiconductor die106opposite the bottom main surface110of the mold compound102may be directly exposed at the top main surface110of the mold compound102. In each case, a primary thermal path of the molded semiconductor package300may include the exposed die pad120at the top main surface108of the mold compound102. As such, the embodiment illustrated inFIG.3reduces the thermal resistance of the primary thermal path of the molded semiconductor package300by exposing the die pad120or similar structure, or if a die pad/similar structure is not used, the side of the semiconductor die106opposite the bottom main surface110of the mold compound102. FIG.4illustrates a perspective view of an embodiment of a molded semiconductor package400having a negative standoff between the leads104and the bottom main surface110of the mold compound102. The mold compound102is not visible inFIG.4so that the internal components of the package400are visible. According to this embodiment, the molded semiconductor package400is a dual row leaded flat package in which a first subset104′ of the leads104protrudes from a first side face of the mold compound (not shown inFIG.4) and a second subset104″ of the leads104protrudes from a second side face of the mold compound opposite the first side face. In one embodiment, the semiconductor die106embedded in the mold compound is a power semiconductor device such as a power MOSFET (metal-oxide-semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), HEMT (high-electron mobility transistor), etc. In the case of a vertical power semiconductor device, the main current path is between the top and bottom sides of the die106. In this case, a first load terminal (e.g. source or drain of a power MOSFET or HEMT; or emitter or collector of an IGBT) of the semiconductor die106is attached to the die pad of the lead frame102and out of view inFIG.4, a second load terminal (e.g. drain or source of a power MOSFET or HEMT; or collector or emitter of an IGBT)402is disposed at the opposite side of the die106. The first subset104′ of leads104may be integrally formed with the die pad120or may be separate. In either case, the first subset104′ of leads104is electrically connected to the first load terminal of the semiconductor die106. The second subset104″ of leads104is electrically connected to the second load terminal402of the semiconductor die106, e.g., using a structured metal clip404as shown inFIG.4. A third type of lead406is electrically connected to a gate terminal408of the semiconductor die106which is disposed at the same side of the die106as the second load terminal402. The third type of lead406may be electrically connected to the gate terminal408of the semiconductor die106by a bond wire, metal clip or other type of electrical conductor410. The semiconductor die106may instead be a lateral device in that the main current path is along the top side of the die106. In this case, all power terminals of the semiconductor die106are disposed at the same side of the die which faces the bottom main surface110of the mold compound (not shown inFIG.4). FIG.5illustrates a cross-sectional view of an embodiment of a semiconductor assembly500that includes a molded semiconductor package300of the kind described herein. The semiconductor assembly500may include any of the molded semiconductor packages100/200/300/400shown inFIGS.1through4. For ease of explanation only, the semiconductor assembly500is shown inFIG.5with the molded semiconductor package300illustrated inFIG.3. The semiconductor assembly500also includes a circuit board502such as a PCB (printed circuit board) to which the molded semiconductor package300is mounted. The bottom main surface110of the package mold compound102faces the circuit board502, and the top main surface108of the package mold compound102faces away from the circuit board502. The second end116of the package leads104which protrude from one or more side faces of the mold compound102are attached to a first main surface504of the circuit board502, e.g., by solder506. The second end116of each lead104has a bottom surface122which faces the circuit board502. The bottom surface122of each package lead104is coplanar with the bottom main surface110of the mold compound102or disposed in a plane above which the bottom main surface110of the mold compound102lies as previously explained herein, so that no lead104of the molded semiconductor package300is positioned closer to the circuit board502than the mold compound102. As previously described herein, the bottom surface122of each package lead104may be vertically offset from the bottom main surface110of the mold compound102by a distance ranging from 0.01 μm to 0.16 μm so that the bottom surface122of each package lead104is disposed in a plane above the bottom main surface110of the mold compound102. Separately or in combination, each package lead104may be bent downward outside the mold compound102in a direction of the circuit board502. In one embodiment, the bottom main surface110of the mold compound102contacts the first main surface504of the circuit board502, e.g., as shown inFIG.5. In each case, the semiconductor assembly500also includes a cooling structure508disposed over the top main surface108of the package mold compound102and a thermal interface material (TIM)510such as TiN filling a gap between the top main surface108of the package mold compound102and the cooling structure508. In the case of the second end122of each package lead104being attached to the first main surface504of the circuit board502by solder506, the total height tolerance (T_sa) of the semiconductor assembly500includes the height tolerance (T_mc) of the package mold compound102between the top and bottom main surfaces108,110of the mold compound102, plus the height tolerance (T_s) of the solder506, plus the height tolerance (T_cs) of the cooling structure508, plus the height tolerance (T_tim) of the thermal interface material510, but not the height tolerance (T_Id) of the package leads104. FIG.6plots the thermal resistance (Rth) of the same thermal interface material (TIM) in ° C./W over time (t) for different material thicknesses ranging from 50 μm to 500 μm. Once the semiconductor assembly500reaches a thermal steady-state, the advantage of a thinner thermal interface material510becomes readily apparent. In one embodiment, the thermal interface material510has a thickness of 100 um or less since the height tolerance T_Id of the package leads104is not a factor in determining the total height tolerance T_sa of the semiconductor assembly500. Also, the robustness of the semiconductor assembly500is improved because any force acting on the semiconductor assembly500, e.g., by the cooling structure508, acts on the mold compound102of the molded semiconductor package300and not the package leads104, the mold compound102being more robust than the package leads104. The height tolerance T_Id of the package leads104is not a factor in determining the total height tolerance T_sa of the semiconductor assembly500because the molded semiconductor package300has a negative standoff between the package leads104and the bottom main surface110of the mold compound102, as explained above. The package leads104may still have some height tolerance, but the lead height tolerance does not contribute to the total height tolerance T_sa of the semiconductor assembly500because of the negative lead standoff. Hence, there may be a gap between the bottom surface122of some or all of the package leads104and the bottom main surface110of the mold compound102, e.g., as shown inFIGS.1and3. The solder506fills the gap between the circuit board02and the package leads104, but the solder506does not affect the primary thermal path of the semiconductor assembly500which includes the exposed die pad120at the top main surface108of the mold compound102, the thermal interface material510and the cooling structure508. The primary thermal path of the semiconductor assembly500is indicated by the higher density of curvilinear lines at the top side of the cooling structure508inFIG.5. The cooling structure508of the semiconductor assembly500may include one or more water pipes or similar structures512for added cooling along the primary thermal path. In one embodiment, the cooling structure508is a housing attached to the first main surface504of the circuit board502and which encloses the molded semiconductor package300on the circuit board502. In another embodiment, the cooling structure508is a heat slug, metal block or similar structure interposed between the top main surface108of the package mold compound102and another structure such as another circuit board, another semiconductor assembly, another semiconductor module, etc. Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description. As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof. | 18,523 |
11862542 | The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. DETAILED DESCRIPTION The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses. It should be understood that throughout the drawings, corresponding reference numerals indicate like or corresponding parts and features. However, it should be understood that the present disclosure is not limited to the forms described below and may be implemented in various different forms, and the following forms are provided to fully convey the scope of the present disclosure to those skilled in the art. In addition, for convenience of description, sizes of the components in the figures may be exaggerated or reduced. First,FIG.14is a cross-sectional view schematically illustrating a dual side cooling power module according to a comparative example of the present disclosure. The dual side cooling power module2000may include a lower substrate100, a semiconductor chip200, lead frames300, a spacer400, an upper substrate500, and a molding portion600. For example, an active metal brazed copper (AMC) substrate or a direct bonded copper (DBC) substrate is used for the lower substrate100and the upper substrate500. The semiconductor chip200for driving a motor of a hybrid vehicle is first bonded by soldering to the lower substrate100using a first solder preform802. Here, the semiconductor chip200has an upper surface as an emitter and a lower surface as a collector, and is operated such that current flows from the collector to the emitter. A diode also works in a similar way. Thereafter, the lead frames300are formed on the lower substrate100, and the semiconductor chip200and any one of the lead frames300are connected by wire-bonding to each other. Subsequently, the spacer400is bonded by soldering on the semiconductor chip200using a second solder preform804, and the upper substrate500is bonded by soldering on the spacer400using a third solder preform806, which is then encapsulated by the molding portion600so as to form an overall structure. On the other hand, for example, a metal having excellent conductivity such as copper (Cu) may be used for the spacer400, and the spacer400has a function of maintaining a gap between the lower substrate100and the upper substrate500in order to protect a wire900electrically connecting the semiconductor chip200and a first external lead310. The aforementioned structure causes the following problems. A plurality of semiconductor chips200use, for example, SiC elements and are mounted using a wire bonding method. In this case, each semiconductor chip200has a length of a wire different from each other, which causes a problem with parasitic inductance. In addition, chip performance is maintained at a junction temperature (Tj) of a SiC element, approximately 200° C. or higher, of which requires module technology to take advantage. Conventionally, the semiconductor chip200is bonded by soldering. However, in the case of the soldering method, since solder has a melting point ranging from 180° C. to 220° C., premature deterioration occurs when it is used at a high temperature. In addition, since the dual side cooling power module2000is manufactured by soldering, warpage occurs due to a difference in coefficient of thermal expansion (CTE) between materials therein, thereby resulting in a high failure rate of the module. Since a module to which SiC elements are applied has small chip sizes, there is a problem that it has an area for transmitting heat to an upper substrate of a chip smaller than that of an insulated gate bipolar transistor (IGBT) having larger chip sizes, thereby increasing thermal resistance. In order to solve the problems, the present disclosure provides a dual side cooling power module in which an internal structure of the module is simplified, performance of the module is improved due to a robust structure, a structure in which cooling is possible on both sides of the module is provided, a heat dissipating surface is designed to be insulated, and a bonding contact is provided so that a power terminal and a signal terminal of a chip can be bonded to an external control board of the module, thereby providing excellent cooling efficiency, and a manufacturing method thereof. FIGS.1to13are cross-sectional views schematically illustrating a manufacturing method of a dual side cooling power module according to one form of the present disclosure in the order of a process sequence thereof. First, referring toFIG.13, the dual side cooling power module1000according to one form of the present disclosure may include a lower substrate100having a recessed portion110on at least one surface thereof, a semiconductor chip200formed in the recessed portion110, lead frames300formed at both ends of the lower substrate100, and an upper substrate500formed on the semiconductor chip200, at least a portion of the lead frames300, and the lower substrate100. Here, the recessed portion110may be formed by processing at least a portion of the upper surface of the lower substrate100to be stepped such that the semiconductor chip200does not protrude to the upper surface of the lower substrate100. Cu wirings may be formed on upper surfaces of the recessed portion110and the lower substrate100. In this step, the semiconductor chip200may be formed not to protrude to the upper surface of the lower substrate100. In one form, bonded portions of the semiconductor chip200are formed not to protrude over the lower substrate100. In this case, an upper surface of the semiconductor chip200may be formed higher than the upper surface of the lower substrate100in accordance with heights of Cu bumps. On the other hand, the semiconductor chip200may include, for example, SiC MOSFET elements. In the semiconductor chip200, Cu bumps220may be formed on gates and source electrode pads210, and first conductive adhesives810may be laminated and bonded thereon. For example, an Ag film or paste may be used for the first conductive adhesive810. At this time, an internal space between the recessed portion110and the semiconductor chip200is filled with an underfill120. For example, a resin such as epoxy or the like may be used for a material of the underfill120. In addition, both ends of the lower substrate100may be processed to be stepped such that the lead frames300do not protrude to the upper surface of the lower substrate100. The lead frames300are formed at both stepped ends to function as a power terminal and a signal terminal. After the lead frames300are formed, a nonconductive adhesive may be applied to a region requiring insulation (at both ends of the lower substrate100), a nonconductive adhesive may be applied to both ends of a lower surface of the upper substrate500corresponding to the region, and then they may bonded to face each other. In another form, both ends of the lower surface of the upper substrate500may be bonded in a stepped form to increase bonding with the semiconductor chip200, and a conductive adhesive is applied to the upper surface of the semiconductor chip200to bond the lower substrate100and the upper substrate500to each other. In this case, the upper surface of the semiconductor chip200is directly bonded to the lower surface of the upper substrate500using a second conductive adhesive820so that a conventionally used spacer may be omitted. In other form, a molding portion600surrounding outer peripheral surfaces of the lower substrate100, the lead frames300, and the upper substrate500is provided, and at least a portion of the lead frames300may protrude outside the molding portion600. Hereinafter, a manufacturing method of the dual side cooling power module1000according to one form of the present disclosure will be described in detail with reference toFIGS.1to13. Referring toFIGS.1and2, in the manufacturing method of the dual side cooling power module1000according to one form of the present disclosure, the recessed portion110may be formed on at least one surface of the lower substrate100. Here, the lower substrate100includes a direct bonded copper (DBC) substrate, and the DBC substrate includes a ceramic layer104between a first metal layer102and a second metal layer106. The recessed portion110is formed on at least one surface of the prepared lower substrate100, for example, the upper surface of the lower substrate100. The recessed portion110has been processed to be stepped so that the semiconductor chip (200shown inFIG.3) which will be bonded later does not protrude to the upper surface of the lower substrate100. However, in accordance with a thickness of the lower substrate100or a thickness of the second metal layer106, the recessed portion110may be processed to be stepped to have a height at which bonded portions of the semiconductor chip200shown inFIG.3do not protrude thereto. Thereafter, as shown inFIG.3, the semiconductor chip200may be formed in the recessed portion110. The semiconductor chip200has a structure in which the bumps220are formed on the pads210and are bonded by flip chip bonding to the recessed portion110. In this case, bonding surfaces of the bumps220are bonded using a conductive paste or a film. After the bonding is completed, the underfill120is filled in the internal space between the recessed portion110and the semiconductor chip200as shown inFIG.4. As shown inFIG.5, first steps130are formed at positions where the lead frames300shown inFIG.6will be formed. The first steps130may be processed to be stepped on both ends of the lower substrate100such that the lead frames300shown inFIG.6do not protrude to the upper surface of the lower substrate100. Thereafter, as shown inFIG.6, the lead frames300may be bonded to the first steps130using a sintering method or an ultrasonic welding method. Referring toFIG.7, after the lead frames300are bonded, the second conductive adhesive820may be applied to the upper surface of the semiconductor chip200, and a first nonconductive adhesive830may be applied to insulate the upper surface of the lower substrate100to which the second conductive adhesive820is not applied and at least a portion of the lead frames300. On the other hand, referring toFIGS.8to10, the upper substrate500may use the same type of substrate as that of the lower substrate100and may be provided with a ceramic layer504between a first metal layer502and a second metal layer506. A second nonconductive adhesive840may be applied to the lower surface of the prepared upper substrate500, that is, both ends of the first metal layer502so that it can correspond to the first nonconductive adhesive830applied to both ends of the lower substrate100in the same region. Here, the first nonconductive adhesive830and the second nonconductive adhesive840may be the same. In another form, before applying the second nonconductive adhesive840to both ends of the lower surface of the upper substrate500, second steps530may be formed on both ends of the first metal layer502of the upper substrate500. The second steps530are not necessarily formed, but it can be understood that partial processing for forming the steps is performed to enhance bonding characteristics of portions bonded to the semiconductor chip200. Next, referring toFIGS.11and12, the lower substrate100to which the first nonconductive adhesive830is applied and the upper substrate500to which the second nonconductive adhesive840is applied may be disposed to face each other, and then the lower substrate100and the upper substrate500may be bonded to each other. In this case, heater blocks700are disposed on a lower surface of the first metal layer102of the lower substrate100and an upper surface of the second metal layer506of the upper substrate500, and then thermally compressed by applying a force in the arrow direction, the upper substrate500may be thermally compressed and bonded to the semiconductor chip200, at least a portion of the lead frames300, and the lower substrate100. Here, the semiconductor chip200is bonded by sintering via the second conductive adhesive820, and curing reaction of adhesive occurs in the insulated region where the first nonconductive adhesive830and the second nonconductive adhesive840are applied, whereby the upper surface of the semiconductor chip200is directly bonded to the lower surface of the upper substrate500via the second conductive adhesive820, so that a conventionally used spacer may be omitted. As shown inFIG.13, after the upper substrate500is bonded, the molding portion600is formed to surround the outer peripheral surfaces of the lower substrate100, the lead frames300, and the upper substrate500so that at least a portion of the lead frames300protrudes outside the molding portion600, whereby the dual side cooling power module1000having a simplified internal structure to be applicable to an inverter for an eco-friendly vehicle may be manufactured. Here, for example, a polymer material having excellent insulation and protection properties such as epoxy molding compound (EMC) or polyimide-based material may be used for the molding portion600. The molding portion600may encapsulate all regions except for regions where the lead frames300are exposed, the lower surface of the lower substrate100and the upper surface of the upper substrate500. Since the above structure does not use a spacer, regions between edges of the module and power terminals and signal terminals may be easily insulated and fixed without filling gaps formed between the lower substrate100and the upper substrate500with the molding portion600. Although not shown in the figures, finally, after the molding portion600is formed, at least a portion of the lead frames300may be trimmed. After unnecessary portions of the lead frames300are trimmed, the module may have a form in which only the signal terminals and the power terminals protrude outside the molding portion600. As described above, in the dual side cooling power module according to the form of the present disclosure, the spacer may be omitted by flip-chip bonding SiC elements using Ag bumps and Cu patterns instead of Al wire bonding, and the molding portion between the lower DBC substrate and the upper DBC substrate can be reduced or eliminated, thereby providing excellent heat dissipation characteristics. In addition, a resistive-capacitive (RC) delay due to wire bonding can be reduced, chip performance is maintained even at a high temperature of 200° C. or higher, and warpage of the substrates during the molding process can be controlled. Since the inside of the module is entirely filled with materials, even if thermal pressure is applied to the module from above and below, temperature and pressure distributions evenly influence the entire area without concentrating on the chip, and thus the molding process can be performed smoothly. Further, conventionally, the module is bonded by soldering with a spacer metal disposed therein. Accordingly, solder layers having large thermal resistances are applied thereto, which results in a limit to reducing a thickness thereof. However, according to the present disclosure, since the Cu layers can be formed relatively thicker than those in the IGBT module while reducing the thickness, efficient cooling is possible by increasing a diffusion rate of heat in a lateral direction of the chip. While the present disclosure has been described with reference to the forms shown in the figures, it should be understood that these are merely exemplary and those skilled in the art can make various modifications and other forms equivalent thereto on the basis of the above. EXPLANATION OF REFERENCES 100Lower substrate110Recessed portion120Underfill130First step102,502First metal layer104,504Ceramic layer106,506Second metal layer200Semiconductor chip210Pad220Cu bump300Lead frame400Spacer500Upper substrate530Second step600Molding portion700Heater block802First Solder Preform804Second Solder Preform806Third solder preform810First Conductive Adhesive820Second conductive adhesive830First nonconductive adhesive840Second nonconductive adhesive900Wire1000,2000Dual side Cooling Power Module | 16,213 |
11862543 | Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION With reference toFIGS.1and2, an exemplary electric drive module constructed in accordance with the teachings of the present disclosure is generally indicated by reference numeral10. The electric drive module10includes a housing assembly12, an electric motor14, a control unit16, a transmission18, a differential assembly20, a pair of output shafts22aand22b, a pump24, a heat exchanger26(FIG.5) and a filter28. The housing assembly12can house the electric motor14, the control unit16, the transmission and the differential assembly20. The electric motor14can be any type of electric motor and can have a stator32and a rotor34. The stator32can include field windings36, whereas the rotor34can include a rotor shaft38that can be disposed within the stator32for rotation about a first rotational axis40. The transmission18can include a planetary reduction42, a shaft44and a transmission output gear46. The planetary reduction can have a sun gear, which can be unitarily and integrally formed with the rotor shaft38to keep pitch line velocity as low as possible, a ring gear, which can be grounded to or non-rotatably coupled to the housing assembly12, a planet carrier and a plurality of planet gears that can be journally supported by the planet carrier and which can be meshingly engaged with both the sun gear and the ring gear. The sun gear, the ring gear and the planet gears can be helical gears. The shaft44can be mounted to a set of bearings60that support the shaft for rotation about the first rotational axis40relative to the housing assembly12. The transmission output gear46can be coupled to (e.g., unitarily and integrally formed with) the shaft44for rotation therewith about the first rotational axis40. The differential assembly20can include a final drive or differential input gear70and a differential. The differential input gear70can be rotatable about a second rotational axis80and can be meshingly engaged to the transmission output gear46. In the example provided, the transmission output gear46and the differential input gear70are helical gears. The differential can be any type of differential mechanism that can provide rotary power to the output shafts22aand22bwhile permitting (at least in one mode of operation) speed differentiation between the output shafts22aand22b. In the example provided, the differential includes a differential case, which is coupled to the differential input gear70for rotation therewith, and a differential gearset having a plurality of differential pinions, which are coupled to the differential case and rotatable (relative to the differential case) about one or more pinion axes that are perpendicular to the second rotational axis80, and a pair of side gears that are meshingly engaged with the differential pinions and rotatable about the second rotational axis80. Each of the output shafts22aand22bcan be coupled to an associated one of the side gears for rotation therewith. In the example provided, the output shaft22bis formed as two distinct components: a stub shaft90and half-shaft92. The stub shaft90is drivingly coupled to an associated one of the side gears and extends between an associated gear and the half-shaft92and is supported by a bearing94in the housing assembly12for rotation about the second rotational axis80. Each of the output shaft22aand the half-shaft92has a constant velocity joint100with a splined male stem. The splined male stem of the constant velocity joint on the output shaft22ais received into and non-rotatably coupled to an associated one of the side gears. The splined male stem of the constant velocity joint on the half-shaft92is received into and non-rotatably coupled to the stub shaft90. InFIGS.3through6, the control unit16includes a power terminal200, one or more field capacitor202, an inverter204and a controller206. The power terminal200can be mounted to the housing assembly12and can have contacts or terminals (not shown) that can be fixedly coupled to a respective power lead210to electrically couple the power lead210to the control unit16. It will be appreciated that the electric motor14can be powered by multi-phase electric AC power and as such, the power terminal200can have multiple contacts or terminals to permit the several power leads210to be coupled to the control unit16. Each field capacitor202electrically couples an associated one of the power leads210to the inverter204. In the example provided, each field capacitor202is relatively small and is disposed in an annular space between the inverter204and the housing assembly12. The annular space can be disposed adjacent to an end of a body of the stator32from which the field windings36extend. Each field capacitor202can be mounted to the inverter204. With reference toFIGS.3,4and7through10, the inverter204can be an annular structure that can be mounted about the field windings36that extend from the body of the stator32. In the example provided the inverter204includes a transistor assembly250and a circuit board assembly252. The transistor assembly250can comprise a plurality of surface mount MOSFET's260, a plurality of heat sinks262, and a retaining member264. With reference toFIGS.11through14, each of the MOSFET's260can include a plurality of device or pin terminals270a,270band270cand a surface-mount power terminal (not specifically shown). The surface-mount power terminal of each MOSFET260can be soldered to an associated one of the heat sinks262. In the example provided, each heat sink262has a base280and a plurality of fins282that extend from the base280. The base280can optionally define a pocket288that is configured to receive the MOSFET260. The pocket288has a bottom surface288a. A riser288b, which is a tapered surface of the pocket that provides clearance between the heat sink262and the MOSFET260, can be provided to permit air to vent from/prevent air entrapment in the pocket288when the MOSFET260is received into the pocket288and soldered to the bottom surface288a. The solder can be placed into the pocket288prior to inserting the MOSFET260into the pocket288. The solder can optionally be in the form of a metal foil. The retaining member264can be a suitable electrically insulating plastic material that can be overmolded onto the MOSFET's260and heat sinks262. The plastic of the retaining member264can cohesively bond to the MOSFET's260and the heat sinks262to thereby fixedly couple the MOSFET's and heat sinks262to one another. Configuration in this manner eliminates relative motion between the MOSFET's260and between each of the MOSFET's260and its associated heat sink262, as well as creates a fluid-tight seal that inhibits fluid migration from the interior of the transistor assembly250in a radially outward direction. The retaining member264can carry a seal that can form a seal between the retaining member264and the housing assembly12. If desired, the solder can be a relatively low temperature solder that has a melting point that is below a predetermined target temperature. The target temperature can be a temperature that is below a maximum operating temperature of the transistor assembly250. For example, the target temperature can be the expected temperature of the transistor assembly250when the electric motor14(FIG.1) was powered at approximately 30%, 50%, or 80% of maximum power for a predetermined time interval, such as three hours. In such situation, the solder between the surface-mount power terminal and the heat sink262would be expected to melt from time to time during the operation of the electric drive module10(FIG.1). The melted solder would remain conductive and the retaining member264would both inhibit relative movement between the MOSFET's260and the heat sinks262but also inhibit migration of the liquid solder out of the pocket288and away from the interface between the surface-mount power terminal and the bottom surface288aof the pocket288. As such, the melting of the solder would not impair operation of the electric motor14(FIG.1). Furthermore, the solder would eventually cool and re-bond the surface-mount power terminal to the bottom surface288aof the pocket288. It will be appreciated that different alloys could be employed to tune the melt point of the solder to a desired temperature or temperature range. With reference toFIG.15, an annular end plate290can be fixedly and sealingly coupled to the retaining member264. The end plate290can include a plurality of phase lead bosses292, which can accept phase leads294(FIG.3) of the field windings36(FIG.3) therethrough, as well as an oil inlet port296. InFIGS.3and4, the circuit board assembly252can comprise a plurality of printed circuit boards that can be stacked against one another and electrically coupled to the pin terminals of the MOSFET's260as well as to the phase leads294of the field windings36of the stator32. The quantity of printed circuit boards is dependent upon the thickness of the electrical traces or conductors on each of the printed circuit boards and the amount of current that is to pass through between each MOSFET260and an associated one of the field windings36. With reference toFIG.16, the controller206is configured to sense a rotational position of the rotor34relative to the stator32(FIG.1) and responsively control the flow of electric power from the inverter204(FIG.3) to the field windings36(FIG.3) to rotate the magnetic field that is produced by the field windings36(FIG.3). The controller206can include a second circuit board assembly that can comprise a plurality of stacked printed circuit boards. The second circuit board assembly can have conventional hardware and control programming for operating the electric motor14(FIG.1) and a TMR sensor300that is configured to sense a rotational position of a magnetic field of a magnet302that is fixedly coupled to the rotor34. The TMR sensor300and the magnet302can optionally be used in place of a conventional encoder or resolver. Significantly, the controller206uses direct voltage traces on the various printed circuit boards and/or the pins of the MOSFETS instead of resistors to determine current flow. InFIG.17, the housing assembly12is shown to have a pump mount310, a heat exchanger mount312and a filter mount314. The pump24can be mounted to the pump mount310and can circulate an appropriate fluid about the electric drive module10to both lubricate and/or cool various components. In the example provided the fluid is a suitable dielectric fluid, such as automatic transmission fluid. The heat exchanger26can be mounted to the heat exchanger mount312and can be configured to receive a pressurized cooling fluid, such as a water-glycol mixture, from an external source and to facilitate the transfer of heat from the dielectric fluid circulated in the electric drive module10to the pressurized cooling fluid. The filter28can be any suitable filter, such as a spin-on oil filter, can be mounted to the filter mount314, and can filter the dielectric fluid that is circulated within the electric drive module. With reference toFIGS.18through20, an intake filter or screen400can be disposed in a portion of the housing assembly12that houses the differential input gear70. The intake filter400can receive dielectric fluid that can be returned to the low-pressure side of the pump24. A windage dam402can be integrated into a cover404and a main housing portion406of the housing assembly12to shield the dielectric fluid that is being returned to the intake filter400from the differential input gear70. More specifically, the windage dam402can cause dielectric fluid to accumulate in the vicinity of the intake filter400and segregate the accumulated fluid from the (rotating) differential input gear70. It will be appreciated that without the windage dam402, the rotating differential input gear70would tend to pull dielectric fluid away from the intake filter400, which could prevent sufficient dielectric fluid from being returned to the low pressure (intake) side of the pump24. It will also be appreciated that segregating the dielectric fluid from the rotating differential input gear70can reduce drag losses that would otherwise be incurred from the rotation of the differential input gear70through the dielectric fluid. The cover404can also include a tubular feed pipe410. With reference toFIGS.21and22, a deflector420can be mounted to the planet carrier PC and can shield the planetary reduction42from dielectric fluid that is slung from other rotating components and/or cause dielectric fluid to drain from the planetary reduction42in a desired manner. InFIGS.23and24, dielectric fluid is received into the intake filter400and transmitting to the low pressure (inlet) side of the pump24. High pressure dielectric fluid exits the pump24and travels through an internal gallery430in the housing assembly12to an inlet passage of the heat exchanger mount312, through the heat exchanger26, into an outlet passage of the heat exchanger mount312, into an inlet passage of the filter base314, through the filter28, into an outlet passage in the filter mount314and to another internal gallery432in the housing assembly12. InFIGS.25and26, dielectric fluid exiting the internal gallery432can travel through a transfer tube434through the oil inlet port296in the end plate290and can enter an annular cavity440that is located radially between a tubular central projection442on the end plate290and the field windings36. The central projection442can carry a seal that can be sealingly engaged to the central projection442and to the field windings36. An annular gap448is formed between an axial end of the field windings36and an annular portion of the end plate290. As noted previously, the end plate290is fixedly and sealingly coupled to the retaining member264of the transistor assembly250. InFIG.27, the dielectric fluid is shown to flow through the annular gap448, through the fins282in the heat sinks262and into passages450formed axially through the stator32. While the fins282have been depicted herein as perpendicular projections, it will be appreciated that the fins282could be shaped differently (for example, as diamond shaped projections) to cause the flow of dielectric fluid passing through the fins282to move in both tangential and axial directions. Flow in this manner may be beneficial for rejecting more heat from the heat sinks262into the dielectric fluid and/or to produce a desired flow restriction that can aid in the pressure balancing of the cooling flow to the rotor. Accordingly, it will be appreciated that dielectric fluid is introduced to the inverter204, passes through fins282on heat sinks262that are electrically conductively coupled to power terminals of the MOSFET's260to thereby cool the inverter204, and thereafter enters the passages450in the stator32to cool the stator32as is shown inFIG.28. InFIGS.29and30, dielectric fluid exiting the stator32is collected in an annular cavity460on an opposite end of the stator32that permits the velocity of the dielectric fluid to slow. A portion of the dielectric fluid is returned to a sump (not shown) in the housing assembly12, while other portions of the flow are directed to lubricate various other components. For example, the annular cavity460can be in fluid communication with a worm track464. With reference toFIGS.31through33, the worm track464can have an outlet that can discharge the dielectric fluid into a bearing470, which can support the differential case472for rotation relative to the housing assembly12, and/or onto the stub shaft90, where the dielectric fluid can migrate to the opposite axial ends of the stub shaft90to lubricate the differential gearing and the bearing94. Thereafter, the dielectric fluid can drain to the sump where it can flow into the intake filter400(FIG.23). InFIGS.34and35, the annular cavity460can be in fluid communication with a passage480that provides a flow of the dielectric fluid to a bearing482that supports the rotor shaft38relative to the housing assembly12. Dielectric fluid that is discharged from the bearing482can seep between the housing assembly12and the rotor shaft38and can drain to the sump in the housing assembly12. With reference toFIGS.26,27and36, a portion of the dielectric fluid in the annular cavity440can be discharged into a bypass tube500. The amount of fluid that is discharged into the bypass tube500is based on pressure balancing between the flow that is directed through the bypass tube500and the portion of the flow that travels through the inverter204and the stator32. FIG.37depicts the dielectric fluid as it is discharged from the annular cavity440and transferred via the bypass tube500to the feed pipe410in the cover404. FIG.38depicts the bypass flow exiting the bypass tube500, traveling through the feed pipe410in the cover404and being fed into a heat exchanger506that is mounted within the rotor shaft38. The heat exchanger506receives the flow (inflow) of dielectric fluid along its rotational axis, and then turns the flow at the opposite end of the rotor34so that the flow of dielectric fluid flows concentrically about the inflow toward the end of the rotor34that received the inflow of the dielectric fluid. InFIGS.39and40, the outflow of the dielectric fluid that exits the heat exchanger506in the rotor shaft38can be at least partly employed to lubricate the various components (i.e., bearings, shafts, gear teeth) of the planetary reduction42, as well as the bearings60that support the shaft44of the transmission. Note that the feed pipe410in the cover404is received through a bore in the shaft44. In the example provided, the feed pipe410is a discrete component that is assembled to the cover404. FIGS.41through44show various flows of dielectric fluid being used to lubricate various other components within the electric drive module. With reference toFIGS.45through72, another inverter constructed in accordance with the teachings of the present disclosure is generally indicated by reference numeral204a. Unless expressly described herein, the inverter204acan be generally similar to the inverter204(FIG.3) described in detail above. InFIG.46, the transistor assembly250ahas a retaining member264athat is formed as a discrete component and thereafter various other components, including the surface mount MOSFET's260, can be assembled to the retaining member264a. The retaining member264adefines a plurality of phase lead bosses292a, a plurality of current sensor lamination mounts600and a plurality of sensor mounts602. Each of the phase lead bosses292acan be disposed axially through the retaining member264aand can be disposed within an associated one of the current sensor lamination mounts600. Each of the phase lead bosses292ais sized to receive portion of a corresponding phase lead (not shown) that supplies electric power to the electric motor. Each of the current sensor lamination mounts600is a generally oval-shaped structure that projects axially from the bottom surface290aof the retaining member264a. Each of the sensor mounts602is disposed proximate an associated one of the current sensor lamination mounts600and defines a hollow, oval-shaped guide tube604that projects axially away from the bottom surface290aof the retaining member264a. In this example, the retaining member264adefines a plurality of insulating shields608that are spaced about the circumference of the retaining member264aand which extend axially from the bottom surface290aof the retaining member264a. With additional reference toFIG.47, each of the insulating shields608is disposed about (e.g., concentrically about) a corresponding aperture610that is sized to receive a corresponding terminal from one of the MOSFET's260. The insulating shields608help to electrically insulate the terminals of the MOSFET's260from one another. FIG.47shows a portion of the transistor assembly250aand depicts the presence of an annular seal ring groove612about the perimeter of the retaining member264a. The seal ring groove612is configured to receive an appropriate elastomeric seal (e.g., an O-ring) therein that sealingly engages the retaining member264aand the housing assembly12(FIG.1). With reference toFIGS.48and49, a plurality of current sensor laminations620are stacked onto each of the current sensor lamination mounts600. The current sensor laminations620are formed of steel and are generally C-shaped so as to define a pair of end faces622that are disposed on opposite sides of an associated guide tube604. The current sensor laminations620can be configured with locating features that nest into or with locating features on adjacent ones of the current sensor laminations620to help secure the current sensor laminations620to one another. A generally C-shaped insulating member624can be disposed on each stack of current sensor laminations620on an axial side of the stack that is opposite the bottom surface290a. InFIG.50, a Hall sensor630is disposed in an associated one of the sensor mounts602. A proximal end of the Hall sensor630is mounted to the circuit board so that the sensor portion630aof the Hall sensor630is disposed parallel to end faces622of the current sensor laminations620at a desired location along a sensing axis relative to the stack of current sensor laminations620. Because the sensor portion630aof the Hall sensor630is disposed at some distance from the proximal end of the Hall sensor630, it will be appreciated that it would be relatively easy to bend the terminals630bof the Hall sensor630, which would affect the positing of the sensor portion630aof the Hall sensor630. The guide tube604, however, is sized and located relative to an associated one of the current sensor lamination mounts600to receive the sensor portion630aof the Hall sensor630as the circuit board is mounted to the retaining member264aand the MOSFET's260and guide the sensor portion630ainto a desired location between the end faces622. With reference toFIGS.51and52, each of the phase leads294acan include a conductor plate640and a receiver642. The conductor plate640can be formed of a suitable electrically-conductive material, such as copper. Each conductor plate640can have a body644and a plurality of protrusions646that extend radially outwardly from the body644. The body644can overlie an associated one of the stacks of current sensor laminations620and can define a receiver aperture648that can be disposed in-line with a corresponding one of the phase lead bosses292a. It will be appreciated that the insulating member624can inhibit the transmission of electricity between the conductor plate640and the current sensor laminations620. Each of the protrusions646can define an aperture that is sized to receive a device terminal270of an associated one of the MOSFET's260. The receiver642is formed of a plurality of individually bident-shaped members650that are linearly arranged (i.e., stacked back-to-front) and permanently affixed to the conductor plate640. Each bident-shaped member650can be formed of an appropriate electrically conductive material, such as copper, and can have body652and a base654. The body652can define a pair of tines and a generally U-shaped opening. Each of the tines can have a protrusion or barb that is fixedly coupled to a distal end of the tine and which extends inwardly therefrom so as to narrow the portion of the generally U-shaped opening that is opposite the base654. The base654is received into the receiver aperture648in an associated one of the conductor plates640. In the example shown, the receiver apertures648are formed along a straight line and as such, the bident-shaped members650that form the receiver642are arranged along the straight line. It will be appreciated, however, that one or more of the receiver apertures648could be arranged along a line that is shaped differently (e.g., an arcuate line) and that the associated set of bident-shaped members650are similarly arranged along a differently shaped (i.e., non-straight) line. It will be appreciated that each phase of electric power supplied to the inverter204acan be electrically coupled to a blade terminal (not shown) that is received into the generally U-shaped openings in the bident-shaped members650and electrically coupled to the receiver642. The individual bident-shaped members650permit flexing of the tines relative to one another and ensure that the blade terminal electrically contacts multiple ones of the tines (preferably all or substantially all of the tines) to transmit an associated phase of electric power through the receiver642and into the conductor plate640, which transmits the associated phase of electric power to a set of the MOSFET's260. InFIGS.53and54, a first insulator660is abutted against the phase leads294aon a side of the phase leads that is opposite the generally C-shaped insulating members624. The first insulator660can define a first bus bar recess662and a plurality of first insulating collars664. The first bus bar recess662is disposed on an axial side of the first insulator660that is opposite the side that abuts the phase leads294a. Each of the first insulating collars664is disposed about a device terminal270of a respective one of the MOSFET's260. Each first insulating collars664can having a first end, which can be received into a mating recess that is formed in the retaining member264a. It will be appreciated that the first insulating collars664are disposed about the device terminals270of the MOSFET's260that need be electrically separated from a first bus bar670that is received into the first bus bar recess662. Holes are formed through the first insulator660to receive therethrough any electric terminals (e.g., the device terminals270of the MOSFET's260) that need extend through the first insulator660. Each of the first insulating collars664can be disposed concentrically about a respective one of the holes. In the example shown the retaining member264adefines a flange672, which is disposed circumferentially about the device terminals270of the MOSFET's260. With reference toFIGS.53,55and56, the first bus bar670is abutted to the first insulator660and received into the first bus bar recess662. The first bus bar670has an annular bar body676, a plurality of protrusions678that extend radially outwardly from the annular bar body676, and a power input portion680. Each of the protrusions678is sized to be received between the first insulating collars664of the first insulator660and to be electrically coupled to a respective one of the device terminals270of the MOSFET's260. Holes are formed through the protrusions and the power input portion680to receive device terminals270from the MOSFET's260and from the terminals684of a pair of capacitors686, respectively. A first slotted aperture690is formed in the power input portion680to receive a blade terminal692that electrically couples the first bus bar670to a source of electrical power (not shown). With reference toFIGS.53and57, a second insulator700can be mounted to the first bus bar670on a side opposite the first insulator660. Like the first insulator660, the second insulator700can extend over the power input portion680, can have a plurality of holes for receipt of various device terminals270and terminals684therethrough and can define a plurality of (second) insulating collars706that can be disposed about the device terminals270of the MOSFET's260to electrically separate those device terminals270of the MOSFET's260that will not be electrically coupled a second bus bar710. Each of the second insulating collars706can define a pair of hollow, tubular projections that can project in opposite axial directions. The tubular projections on the side of the second insulator700that face toward the first insulator660can be matingly received into recesses that are defined by the first insulating collars664. With reference toFIGS.53and58, the second bus bar710is abutted to the second insulator700. The second bus bar710has an annular bar body712, a plurality of protrusions714that extend radially outwardly from the annular bar body712and a power input portion716. Each of the protrusions714is sized to be received between the second insulating collars706of the second insulator700and to be electrically coupled to a respective one of the device terminals270of the MOSFET's260. Holes are formed through the protrusions714and the power input portion716to receive the device terminals270from the MOSFET's260and from the terminals720of the pair of capacitors686, respectively. A second slotted aperture722is formed in the power input portion716to receive a blade terminal724that electrically couples the second bus bar710to a source of electrical power (not shown) With reference toFIGS.53and59, a third insulator730is mounted to the retaining member264aand abuts the second bus bar710on a side opposite the second insulator700. The third insulator730defines a second bus bar recess732into which the second bus bar710is received. The third insulator730also defines a plurality of third insulating collars734and a plurality of holes. Each of the third insulating collars734can define a recess that can receive a tubular projection from an associated one of the second insulating collars706of the second insulator700. The holes can extend through the third insulator730to receive there through various terminals, such as the device terminals270of the MOSFET's260, so that those terminals can be electrically coupled to the circuit board740. The third insulator730can define first and second flange members742and744, respectively, that can extend axially from a central body of the third insulator730in opposite axial directions. Each of the first and second flange members742and744is disposed about the perimeter of the central body of the third insulator730. The flange672of the retaining member264acan be received within (and optionally can abut) the second flange member742to form a labyrinth about a cavity that is defined by the retaining member264aand the third insulator730. InFIGS.53and60, the circuit board740can be abutted to the third insulator730on a side opposite the second bus bar710and can be electrically coupled to the various terminals that extend through the third insulator730. InFIGS.61through63a control board750is plugged into the circuit board740and is fixedly coupled thereto via a plurality of threaded fasteners752. The control board750is disposed about the transfer tube434that is mounted to a bearing support754that holds a bearing756that supports a rotor shaft38of the electric motor relative to the housing of the electric motor. The transfer tube434is sealingly engaged to the oil inlet port296that is unitarily and integrally formed with the retaining member264a(FIG.46). Coolant received by the oil inlet port296in the retaining member is employed to route cooling liquid to the inverter204aand to the electric motor. InFIGS.64through67, a portion of the flow of the filtered coolant that is discharged from the heat exchanger26is routed to the capacitors686to cool the capacitors686. Coolant discharged from the capacitors686is routed to join the flow of cooling liquid enters the stator32to cool the electric motor. The capacitors686are illustrated inFIG.68as being mounted to a tray780that holds a seal member782. Optional crush limiters784can be mounted to the tray780to limit the amount by which the seal member782is compressed.FIG.69depicts the reverse side of the tray780and the terminals684,720of the capacitors686. The capacitors686can be potted to the tray780with a suitable compound to form a seal between the capacitors686and the tray780. FIG.70depicts a recess790in the housing that is configured to receive the tray780(FIG.68) and the capacitors686(FIG.68). A gallery792that is integrally formed with the housing permits cooling fluid in the recess790to be discharged through a housing wall796to the stator32(FIG.64) of the electric motor. FIG.71depicts the tray780being mounted to the housing via a plurality of threaded fasteners. FIG.72depicts a fourth insulator800that is disposed between the circuit board740and the bearing support754. The fourth insulator800can have a flange810about its perimeter that can be received into the first flange742on the third insulator730to form a labyrinth between the third and fourth insulators730and800. The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. | 33,040 |
11862544 | Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION The following disclosure provides for many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, a reference to the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure. FIG.1Aillustrates a cross sectional view of an exemplary electronic assembly1in accordance with some embodiments of the present disclosure. The electronic assembly1may include a substrate10, a semiconductor device package1s, and a conductive element14. The substrate10may include, for example, a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper foil laminate, a polymer-impregnated glass-fiber-based copper foil laminate, or so on. In some embodiments, the substrate10may include a flexible PCB. The substrate10may include one or more interconnection structures, such as a redistribution layer (RDL) or a grounding element. The interconnection structures may include, for example, one or more conductive pads10pproximate to, adjacent to, or embedded in and exposed from a surface101of the substrate10facing the semiconductor device package1s. The semiconductor device package1s(which may be abbreviated as a package) may include a substrate11, an electronic component12, and an encapsulant13. The details of the substrate11may refer to the substrate10, and will thus not be repeated hereafter. The substrate11may have a surface111, a surface112opposite to the surface111, and a surface113(which can also be referred to as a lateral surface of the substrate11) extending between the surface111and the surface112. The surface113may face the substrate10. The substrate11may include an electrical contact11p1proximate to, adjacent to, or embedded in and exposed from the surface111of the substrate11. In some embodiments, the electrical contact11p1may include a conductive pad. In some embodiments, the electrical contact11p1may be adjacent to the surface113of the substrate11. The electronic component12may be disposed on the surface111of the substrate11. The electronic component12may include, for example, a chip or a die. The chip or die may include a semiconductor substrate (e.g., silicon substrate), one or more integrated circuit (IC) devices, and one or more interconnection structures therein. In some examples, the IC devices may include an active component, such as an IC chip or a die. In some examples, the IC devices may include a passive electronic component, such as a capacitor, a resistor, or an inductor. In some embodiments, the electronic component12may be electrically connected to the substrate11by, for example, flip-chip or wire-bonding. The encapsulant13(which may be referred to as a protection layer) may be disposed on the surface111of the substrate11. The encapsulant13may cover or encapsulate the electronic component12. The electronic component12may be covered or encapsulated in the encapsulant13. In some embodiments, the encapsulant13may include, for example, an epoxy resin having fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof. The encapsulant13may have a surface131(which can also be referred to as a top surface of the encapsulant13) facing away from the substrate11and an edge133(which can also be referred to as a lateral surface of the encapsulant13). In some embodiments, the edge133may be substantially coplanar with the surface113of the substrate11. The encapsulant13may have a dimension d1(e.g., a thickness or a height) measured between the surface111of the substrate11and the surface131of the encapsulant13. The encapsulant13may have a dimension d2(e.g., a length or a width) measured between two edges of the encapsulant13from a side view as shown inFIG.1A. In some embodiments, the dimension d2may be greater than the dimension d1. In other words, the dimension d1may be smaller than the dimension d2. The shorter side of the encapsulant13may face the substrate10. The encapsulant13may define or have a cavity or a recessed portion (not annotated inFIG.1A, such as the cavity13h1inFIG.1B) recessed from the edge133of the encapsulant13. As a result, the cavity may face the surface101of the substrate10. The electrical contact11p1may be exposed from the encapsulant13through the cavity to provide electrical interconnection or signal transmission between the substrate10and the semiconductor device package1s. The conductive element14may be disposed on the surface101of the substrate10and electrically connected to the substrate10through the conductive pad10p. The conductive element14may be accommodated in (such as partially accommodated in) the cavity. The conductive element14may be surrounded by (such as partially accommodated by) the encapsulant13. The conductive element14may be pluggable with respect to the encapsulant13through the cavity defined by the encapsulant13. In other words, the substrate10may be pluggable with respect to the encapsulant13through the cavity. In some embodiments, the conductive element14may be in contact with (such as in direct contact with) the encapsulant13. The conductive element14may press against the encapsulant13. The conductive element14may have a pressing force on the encapsulant13. In some embodiments, the conductive element14may be in contact with (such as in direct contact with) the electrical contact11p1in the cavity. The conductive element14may press against the electrical contact11p1in the cavity. The conductive element14may have a pressing force on the electrical contact11p1in the cavity. The conductive element14may supported in the cavity. The conductive element14may supported by the encapsulant13. For example, the conductive element14may be directly supported by the encapsulant13. For example, the conductive element14may be indirectly supported by the encapsulant13, such as supported by the electrical contact11p1. In some embodiments, the conductive element14may include, for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), palladium (Pd), another metal(s) or alloy(s), or a combination of two or more thereof. In some embodiments, the conductive element14may include a conductive pin. For example, the conductive element14may extend from the surface101of the substrate10into the cavity. For example, the conductive element14may have an elongation direction, an extending direction, or a longer side in a direction from the surface101of the substrate10into the cavity. For example, the conductive element14may pass through the edge133of the encapsulant13. The conductive element14may provide electrical interconnection or signal transmission between the substrate10and the semiconductor device package1s. For example, the conductive element14may be electrically connected between the electrical contact11p1and the conductive pad10p. For example, the conductive element14may be electrically connected with the electronic component12through the electrical contact11p1. In some embodiments, the signal transmission path between the electrical contact11p1and the conductive pad10pmay be in the extending direction of the conductive element14. For example, the signal transmission path may extend from the surface101of the substrate10into the cavity. For example, the signal transmission path may be along a direction substantially perpendicular to the surface101of the substrate10. For example, the signal transmission path may be along a direction substantially in parallel with the surface111of the substrate11. FIG.1Billustrates a cross sectional view of the semiconductor device package1sin accordance with some embodiments of the present disclosure. The semiconductor device package1sinFIG.1Bis similar to the semiconductor device package1sinFIG.1A, with more details described below. The cavity13h1may be recessed from the short side (with the dimension d1) of the encapsulant13. The cavity13h1may be recessed from the edge133of the encapsulant13along the surface101of the substrate10. The cavity13h1may be not formed on the surface131of the encapsulant13. In other words, the cavity13h1may be not recessed from the surface131of the encapsulant13. In some embodiments, the cavity13h1may be spaced apart from the surface131of the encapsulant13. For example, a sidewall134of the cavity13h1may be opposite to the surface131of the encapsulant13. In some embodiments, the sidewall134of the cavity13h1may provide a support for the conductive element14inFIG.1Ato be able to press against and increase the contact area between the conductive element14and the encapsulant13. Therefore, the conductive element14can be secured in the cavity13h1by the compression force. In some embodiments, the cavity13h1may have the sidewall134defined by the encapsulant13, an opposite sidewall136defined by the surface111of the substrate11, and a bottom surface135defined by the encapsulant13. The bottom surface135may be located between the sidewall134and the sidewall136. In some embodiments, the electrical contact11p1may be spaced apart from the encapsulant13. For example, the electrical contact11p1may be spaced apart from the bottom surface135of the encapsulant13by a distance w1. For example, the electrical contact11p1may be not in contact with the encapsulant13. In some embodiments, the electrical contact11p1may be spaced apart from the surface113of the substrate11by a distance w2. In some embodiments, the distance w1and the distance w2may each be greater than zero. FIG.1Cillustrates a cross sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device package is inFIG.1AandFIG.1Bmay have a cross sectional view as shown inFIG.1C. The encapsulant13may have a plurality of cavities (including the cavity13h1and the cavity13h2). The cavity13h2may be spaced apart from the cavity13h1. An electrical contact11p2may be exposed from the encapsulant13through the cavity13h2. In some embodiments, with more electrical contacts to provide electrical interconnection or signal transmission between the substrate10and the semiconductor device package1s, I/O numbers can be increased and electrical performance of the electronic assembly1can be improved. In some other embodiments, the encapsulant13may have any number of cavities. In addition, there may be one or more electrical contacts exposed from each of the cavities. FIG.1Dillustrates a cross sectional view of a part of an exemplary semiconductor device package in accordance with some embodiments of the present disclosure.FIG.1Donly illustrates a part of the substrate11, a part of the encapsulant13, and the electrical contact11p1. In some embodiments, the semiconductor device package is inFIG.1A, andFIG.1Bmay have a cross sectional view as shown inFIG.1C. The bottom surface135of the encapsulant13may have a hole as illustrated in the dotted circle13a. For example, the bottom surface135of the encapsulant13may be non-planar. Residue of the encapsulant13as illustrated in the dotted circle13bmay remain on the substrate11. The residue of the encapsulant13may be not connected with the main portion of the encapsulant13. In some embodiments, the residue of the encapsulant13may be adjacent to the surface113of the substrate11. In some embodiments, the residue of the encapsulant13may have a surface substantially coplanar with the surface113of the substrate11. In some embodiments, the electrical interconnection or signal transmission in two directions or bending directions may be obtained by bonding a connector (such as an FPC or a flexible foil) to the conductive pads on the substrates10and11through soldering. Joint areas for placing the soldering materials may be required on the substrates10and11, which may increase the package size. In addition, warpage of the FPC should be well-controlled to prevent low yield issues. As shown inFIG.1AandFIG.1B, by providing the cavity13h1, which is recessed from the edge133of the encapsulant13for accommodating the conductive element14, electrical interconnection or signal transmission between the substrate10and the semiconductor device package1scan be obtained through the conductive element14. Since no joint area is required to solder the conductive element14, the layout design flexibility can be increased, and more electronic components can be incorporated into the package. In addition, warpage issues that may be caused by the FPC may be alleviated or eliminated, which would in turn improve the electrical performance and reliability of the electronic assembly1. FIG.2Aillustrates a cross sectional view of an exemplary electronic assembly2in accordance with some embodiments of the present disclosure. The electronic assembly2inFIG.2Ais similar to the electronic assembly1inFIG.1Aexcept for the differences described below. The electronic assembly2may further include an electrical contact20covering the electrical contact11p1. In some embodiments, the electrical contact20may be exposed from the encapsulant13through the cavity. In some embodiments, the electrical contact20may be in contact with the conductive element14to provide electrical interconnection or signal transmission between the substrate10and the semiconductor device package1s. In some embodiments, the electrical contact20may include a flowable conductive material. In some embodiments, the electrical contact20may include a soldering material. In some embodiments, the electrical contact20may include, for example, eutectic Sn/Pb, high-lead solder, lead-free solder, pure tin solder, or other types of solders. In some embodiments, since the electrical contact20covers the electrical contact11p1, the electrical contact11p1may be not exposed through the cavity of the encapsulant13. In an operation to remove the encapsulant13to form the cavity, the electrical contact20may protect the solder mask on the substrate11from being removed or etched away. In some embodiments, the substrate11may be not exposed from the encapsulant13through the cavity. FIG.2Billustrates a cross sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.FIG.2Bonly illustrates a part of the substrate11, a part of the encapsulant13, and electrical contacts20,21. In some embodiments, the semiconductor device package1sinFIG.2Amay have a cross sectional view as shown inFIG.2B. The encapsulant13may have a plurality of cavities (including the cavity13h1and the cavity13h2). The cavity13h2may be spaced apart from the cavity13h1. The electrical contact21may be exposed from the encapsulant13through the cavity13h2. In some embodiments, with more electrical contacts to provide electrical interconnection or signal transmission between the substrate10and the semiconductor device package1s, I/O numbers can be increased and electrical performance of the electronic assembly1can be improved. In some other embodiments, the encapsulant13may have any number of cavities. In addition, there may be one or more electrical contacts exposed from each of the cavities. FIG.2Cillustrates a cross sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.FIG.2Conly illustrates a part of the substrate11, a part of the encapsulant13, and electrical contacts20,21. In some embodiments, the semiconductor device package1sinFIG.2Amay have a cross sectional view as shown inFIG.2C. Similar toFIG.2B, the encapsulant13may have a plurality of cavities (including the cavity13h1and the cavity13h2) except that the electrical contacts may not be equally spaced. For example, the electrical contact21may be closer to the electrical contact20than to the other electrical contacts. FIG.3illustrates a cross sectional view of an exemplary electronic assembly3in accordance with some embodiments of the present disclosure. The electronic assembly3inFIG.3is similar to the electronic assembly2inFIG.2Aexcept that the conductive element14in the electronic assembly2is replaced with conductive materials30,31and that the electronic assembly2further includes an underfill32. The conductive material30may be exposed from the surface133of the encapsulant13. The conductive material30may be in contact with the electrical contact20on the electrical contact11p1. In some embodiments, the conductive material30may be formed by filling the conductive material30in the cavity of the encapsulant13. In some embodiments, the conductive material30and the conductive material31may each have a material (as listed above) for the electrical contact20. In some embodiments, the conductive material30may be well combined or have a standard wetting balance with the electrical contact20. In some embodiments, the underfill32may be formed to encapsulate the conductive material31. In some embodiments, the underfill32includes an epoxy resin, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof. FIG.4Aillustrates a cross sectional view of an exemplary electronic assembly4in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device package1sinFIG.4Amay have a cross sectional view as shown inFIG.4B. The electronic assembly4inFIG.4Ais similar to the electronic assembly1inFIG.1Aexcept that the conductive element14in the electronic assembly1is replaced with a conductive frame40. In addition, the substrate10may have a cavity10rrecessed from the surface101. The conductive frame40may extend into the cavity10rof the substrate10and contact the conductive pad10p. In some embodiments, as shown in the enlarged view, the conductive frame40may have a plurality of pins exposed from the encapsulant13. FIG.5Aillustrates a cross sectional view of an exemplary electronic assembly5in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device package1sinFIG.5Amay have a cross sectional view as shown inFIG.5B. The electronic assembly5inFIG.5is similar to the electronic assembly1inFIG.1Aexcept that the conductive element14in the electronic assembly1is replaced with a conductive wire50, a wire end pad51, and a conductive material52, and that the electronic assembly5further includes an underfill53. In some embodiments, the wire end pad51may be a conductive thin film. In some embodiments, as shown in the enlarged view, there may be a plurality of wire end pads51on the encapsulant13. In some embodiments, the conductive material52may have a material as listed above for the electrical contact20. In some embodiments, the underfill53may be formed to encapsulate the wire end pad51and the conductive material52. In some embodiments, the underfill53may have a material as listed above for the underfill32. FIG.6illustrates a cross sectional view of an exemplary electronic assembly6in accordance with some embodiments of the present disclosure. The electronic assembly6inFIG.6is similar to the electronic assembly1inFIG.1Aexcept for the differences described below. The electronic assembly6may include a substrate60and a semiconductor device package6s. An electronic component61may be disposed on a surface601of the substrate60. An encapsulant62(which may be referred to as a protection layer) may be disposed on the surface601of the substrate60to cover or encapsulate the electronic component61. In some embodiments, the substrate60, the electronic component61, and the encapsulant62may be collectively referred to as a semiconductor device package or a package. The encapsulant62may have a surface621facing away from the substrate60. The encapsulant62may have a dimension d3(e.g., a thickness or a height) measured between the surface601of the substrate60and the surface621of the encapsulant62. The encapsulant13may have a dimension d4(e.g., a length or a width) measured between two edges of the encapsulant62from a side view as shown inFIG.6A. In some embodiments, the dimension d4may be greater than the dimension d3. In other words, the dimension d3may be smaller than the dimension d4. The longer or greater side of the encapsulant62may face the semiconductor device package6s. The encapsulant62may define or have a cavity62hrecessed from the surface621. The cavity62hmay be recessed from the longer or greater side (with the dimension d4) of the encapsulant62. In some embodiments, the cavity62hmay penetrates through the encapsulant62. For example, a part of the surface601of the substrate60may be exposed from the encapsulant62through the cavity62h. For example, the cavity62hmay penetrates from the surface621to the surface601. In some embodiments, the cavity62hmay be inclined to a periphery of the encapsulant62. For example, the cavity62hmay be closer to a side of the encapsulant62than the opposite side of the encapsulant62. For example, the cavity62hmay be spaced apart from a central portion of the encapsulant62. For example, the cavity62hmay be spaced apart from a central line of the encapsulant62. In some embodiments, the cavity62hmay be spaced apart from the circuit area of the substrate60. For example, the circuit area of the substrate60is not exposed from the encapsulant62. The substrate60may include, for example, one or more electrical contacts63proximate to, adjacent to, or embedded in and exposed from the surface601of the substrate60. In some embodiments, as shown inFIG.6A, the electrical contact63may include a soldering material63aon a conductive pad63b. In some embodiments, the electrical contact63may include other types of connecting elements described above (such as the electrical contact11p1, the conductive element14, the conductive material30, the conductive frame40, the conductive wire50, etc.). In some embodiments, the electrical contact63may be exposed from the encapsulant62through the cavity62h. For example, the electrical contact63may be partially exposed from the encapsulant62through the cavity62h. Elastic elements64and65may be provided on a sidewall of the cavity62h. In some embodiments, a flexibility of the elastic element64may be greater than a flexibility of the encapsulant62. In some embodiments, a flexibility of the elastic element64may be greater than a flexibility of the electrical contact63. In some embodiments, a distance between the elastic element64and the surface601may be greater than a distance between the electrical contact63and the surface601. For example, in the normal direction of the surface601, the electrical contact63is located between the surface601and the elastic element64. The semiconductor device package6s(which may be abbreviated as a package) may be accommodated in (such as partially accommodated in) the cavity62h. The package6smay include substrates6s1and6s3, and a molding material6s2(or an encapsulant) disposed between the substrates6s1and6s3. In some embodiments, the package6smay include one or more electronic components on the substrate6s1and/or the substrate6s3. The one or more electronic components may disposed between the substrates6s1and6s3. The one or more electronic components may be covered or encapsulated by the molding material6s2(or an encapsulant). In some embodiments, the package6smay include one substrate and a molding material (or an encapsulant) disposed on the substrate. In some embodiments, the package6smay be or may include a conductive element. The package6smay include, for example, one or more conductive pads6scproximate to, adjacent to, or embedded in and exposed from the substrate6s1and/or the substrate6s3. In some embodiments, the package6smay have a portion physically connecting to the electrical contact63. For example, the package6smay have a portion directly contacting the electrical contact63. In some embodiments, the conductive pad6scmay have a portion physically connecting to the electrical contact63. For example, the conductive pad6scmay have a portion directly contacting the electrical contact63. In some embodiments, the package6smay have a portion physically disconnected from the electrical contact63. For example, the package6smay have a portion spaced apart from the electrical contact63. In some embodiments, the conductive pad6scmay have a portion physically disconnected from the electrical contact63. For example, the conductive pad6scmay have a portion spaced apart from the electrical contact63. The package6smay be pluggable with respect to the cavity62hof the encapsulant62through the encapsulant62. The package6smay be supported by the encapsulant62. For example, the package6smay be directly supported by the encapsulant62. For example, the package6smay be indirectly supported by the encapsulant62, such as through the elastic element64and the electrical contact63. The package6smay be surrounded by (such as partially accommodated by) the encapsulant61. The package6smay be mounted in the cavity62h. The electrical contact63and the conductive pad6scmay provide electrical interconnection or signal transmission between the substrate60and the package6s. The package6smay be supported by the elastic element64and the electrical contact63. In some embodiments, the elastic element64and the electrical contact63may functioned as location-limiting elements for the package6s. For example, the elastic element64and the electrical contact63may fix the package6s. For example, the elastic element64and the electrical contact63may press against the package6s. In some embodiments, the elastic element64may be a non-conductive location-limiting element. In some embodiments, the elastic element64may correspond to a non-conductive area (or a non-circuitry area) of the package6s. In some embodiments, the elastic element64may be physically connected with a non-conductive area (or a non-circuitry area) of the package6s. In some embodiments, the electrical contact63may be a conductive location-limiting element. In some embodiments, the electrical contact63may correspond to a conductive area (or a circuitry area) of the package6s. In some embodiments, the electrical contact63may be physically connected with a conductive area (or a circuitry area) of the package6s. FIG.6Billustrates a top view of a semiconductor device package in accordance with some embodiments of the present disclosure.FIG.6Bonly illustrates a part of the encapsulant62and the elastic elements64,65. In some embodiments, the electronic assembly6inFIG.6Amay have a top view as shown inFIG.6B. The elastic elements64and65may have a triangular shape. In some other embodiments, the elastic elements can have any shape. In some other embodiments, at least two elastic elements64and65are provided on the opposite sidewalls of the cavity62hto prevent the semiconductor device package6sfrom shifting or rotating. In some other embodiments, the elastic elements64and65may be provided symmetrically. In some other embodiments, the elastic elements64and65may face each other. In some other embodiments, there may be any number of elastic elements provided on a sidewall of the cavity62h. FIG.7illustrates a cross sectional view of an exemplary electronic assembly7in accordance with some embodiments of the present disclosure. The electronic assembly7inFIG.7is similar to the electronic assembly1inFIG.1Aexcept for the differences described below. The electronic assembly7may include a substrate70, and a semiconductor device package7s. The substrate70may include, for example, one or more conductive pads70pproximate to, adjacent to, or embedded in and exposed from a surface of the substrate70facing the semiconductor device package7s. A socket71may be provided on the substrate70and connected to the conductive pad70p. The socket71may have a cavity71h. In some embodiments, the electrical contact72may be provided on a sidewall of the cavity71h. The semiconductor device package7smay be accommodated in (such as partially accommodated in) the cavity71h. The socket71and the electrical contact72may provide electrical interconnection or signal transmission between the substrate70and the semiconductor device package7s. FIG.8A,FIG.8B,FIG.8C,FIG.8D, andFIG.8Eillustrate one or more stages of a method of manufacturing an exemplary semiconductor device package in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. Referring toFIG.8A, a substrate11having an electrical contact11p1on a surface101of the substrate11may be provided. Referring toFIG.8B, a protection layer80may be formed on the surface101of the substrate11to cover the electrical contact11p1. In some embodiments, the protection layer80may include an adhesive such as a hot melt adhesive (HMA). In some embodiments, the protection layer80may include Ethylene-vinyl acetate (EVA), polyolefins (PO), polypropylene (PP), polyamides (PA), other feasible materials or two or more combinations thereof. In some embodiments, the protection layer80may be formed by using paste printing, compression molding, transfer molding selective molding, liquid glue molding, vacuum lamination, spin coating, or other suitable operations. Referring toFIG.8C, an encapsulant13may be formed on the surface101of the substrate11to cover the protection layer80. In some embodiments, the encapsulant13may formed by using paste printing, compression molding, transfer molding selective molding, liquid glue molding, vacuum lamination, spin coating, or other suitable operations. Referring toFIG.8D, a singulation may be performed through the encapsulant13and the substrate11. The singulation may be performed, for example, by using a dicing saw, laser, or other appropriate cutting techniques. After the singulation, a part of the protection layer80may be exposed. The exposed protection layer80may be substantially coplanar with the surface133of the encapsulant13and the surface113of the substrate11. Referring toFIG.8E, the protection layer80may be removed to form the cavity13h1in the encapsulant13. The structure manufactured through the operations illustrated inFIG.8A,FIG.8B,FIG.8C,FIG.8D, andFIG.8Emay be similar to the semiconductor device package is inFIG.1AandFIG.1B. FIG.9A,FIG.9B,FIG.9C, andFIG.9Dillustrate one or more stages of a method of manufacturing an exemplary semiconductor device package in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. Referring toFIG.9A, a substrate11having an electrical contact11p1on a surface101of the substrate11may be provided. A protection layer90may be formed on the surface101of the substrate11to cover the electrical contact11p1. The protection layer90may be thinner than the protection layer80inFIG.8B. The protection layer90may have an irregular shape. Referring toFIG.9B, an encapsulant13may be formed on the surface101of the substrate11to cover the protection layer90. Optionally, a singulation may be performed through the encapsulant13and the substrate11. After the singulation, the electrical contact11p1may be closer to the edge of the encapsulant13. Referring toFIG.9C, a cavity13h1may be formed by performing laser drilling. Then, a part of the protection layer90may be exposed. In some embodiments, residue of the encapsulant13as illustrated in the dotted circle13bmay remain on the substrate11. Referring toFIG.9D, the protection layer90may be removed to expose the electrical contact11p1in cavity13h1. In some embodiments, since the protection layer90is removed after the laser drilling inFIG.9Cto form the cavity13h1, the bottom surface135of the encapsulant13may be non-planar. The bottom surface135of the encapsulant13may have a hole as illustrated in the dotted circle13a. The structure manufactured through the operations illustrated inFIG.9A,FIG.9B,FIG.9C, andFIG.9Dmay be similar to the structure inFIG.1D. FIG.10A,FIG.10B,FIG.10C,FIG.10D,FIG.10E, andFIG.10Fillustrate one or more stages of a method of manufacturing an exemplary semiconductor device package in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. Referring toFIG.10A, a substrate11having an electrical contact11p1on a surface101of the substrate11may be provided. Referring toFIG.10B, a conductive wire50may be formed on the electrical contact11p1through a wire bonding operation. Referring toFIG.10C, an encapsulant13may be formed on the surface101of the substrate11to cover the conductive wire50. Referring toFIG.10D, a singulation may be performed through the encapsulant13and the substrate11. After the singulation operation, a part of the conductive wire50may be exposed from the encapsulant13. The exposed part of the conductive wire50may be substantially coplanar with the surface133of the encapsulant13and the surface113of the substrate11. Referring toFIG.10E, a conductive layer51′ may be disposed on an external surface of the encapsulant13. The conductive layer51′ may cover the exposed part of the conductive wire50. In some embodiments, the conductive layer51′ may be a conductive thin film. The conductive layer51′ may be formed by, for example, a plating process. Referring toFIG.10F, the conductive layer51′ may be patterned to form a wire end pad51. The structure manufactured through the operations illustrated inFIG.10A,FIG.10B,FIG.10C,FIG.10D,FIG.10E, andFIG.10Fmay be similar to the semiconductor device package inFIG.5. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “left,” “right” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present. As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along the same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values. The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. | 37,644 |
11862545 | DESCRIPTION OF THE EMBODIMENTS Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. FIG.1is a schematic cross-sectional view of an integrated substrate structure in accordance with some embodiments. Referring toFIG.1, an integrated substrate structure10includes a plurality of fine redistribution segments110mounted on a coarse redistribution structure120. The size of the integrated substrate structure10may be large enough so that many chips (not shown) may be integrated simultaneously on the integrated substrate structure10through the fine redistribution segments110. In some embodiments, the size of the integrated substrate structure10is about 80 mm×80 mm, 100 mm×100 mm, or even beyond this. Compared to a conventional substrate, the integrated substrate structure10is provided with a larger format for connecting various chips thereon. It should be noted that the configuration of the fine redistribution segments110and the coarse redistribution structure120are illustrated as an example, the layers of the respective fine redistribution segment and the coarse redistribution structure may be adjusted depending on product requirements. The fine redistribution segments110may be spatially separated from one another, and the fine redistribution segments110may be electrically coupled to each other through the coarse redistribution structure120. The spatial separation of the segments has the benefit of the heat generated from the chips on one segment is thermally decoupled from the chips on the other segments. The thermal decouple among chips has the benefit of reducing thermal stresses of the chips. This benefit can enhance the reliability of overall packaging system. In addition, the gaps between the segments can be useful for the process of filling underfill materials. The structure inFIG.1is a die last solution for system integration. Hence, the overall system integration yield can be increased by known good substrate and known good dies. The respective fine redistribution segment110may include a fine circuitry112embedded in a fine dielectric layer114. The respective fine redistribution segment110may include a top surface110a, a bottom surface110bopposite to the top surface110a, and a sidewall110cconnected to the top surface110aand the bottom surface110b. For example, at least one chip (not shown) is mounted on the top surface110a, the bottom surface110bfaces the coarse redistribution structure120, and the sidewall110cis substantially vertical. The topmost portion of the fine circuitry112at the top surface110amay be accessibly revealed by the fine dielectric layer114for the chips mounted thereon. In some embodiments, the sidewall110cincludes a sidewall of the fine circuitry112and a sidewall of the fine dielectric layer114aligned with each other. The pitch of the fine circuitry112may match the fine-pitch requirements of chips that will be mounted on the fine redistribution segments110. In some embodiments, the fine circuitry112includes fine conductive patterns FP and fine conductive vias FV vertically connecting adjacent levels of the fine conductive patterns FP. The materials of the fine conductive patterns FP and the fine conductive vias FV may be or may include copper, gold, nickel, aluminium, platinum, tin, combinations thereof, an alloy thereof, or any suitable conductive material. In some embodiments, the fine dielectric layer114includes a plurality of sublayers stacked upon one another, and the respective sublayer may include the same material or different materials. The material of the fine dielectric layer114may be or may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), inorganic dielectric material (e.g., silicon oxide, silicon nitride, or the like), or other suitable electrically insulating materials. The respective coarse redistribution structure120may include a coarse circuitry122embedded in a coarse dielectric layer124. In some embodiments, the coarse circuitry122includes coarse conductive patterns CP and coarse conductive vias CV connected to the adjacent levels of the coarse conductive patterns CP. The material of the coarse circuitry122may be similar to that of the fine circuitry112. In some embodiments, the coarse dielectric layer124includes a plurality of sublayers stacked upon one another, and the respective sublayer may include the same material or different materials. For example, the coarse dielectric layers124are formed by lamination or other suitable deposition process and may include material such as ceramic (e.g., titanium oxide or the like), organic dielectric, or other suitable electrically insulating materials. The respective coarse conductive pattern CP and the respective coarse conductive via CV may be coarser and thicker than the fine conductive pattern FP and the fine conductive via FV. The layout density per unit area of the fine circuitry112may be much finer than that of the coarse circuitry122. The fine redistribution segments110may be viewed as thin film segments with high density wiring area relative to the coarse redistribution structure120. For example, the fine conductive pattern FP has line-spacing (L/S) pitches finer than the L/S pitches of the coarse conductive pattern CP. In some embodiments, a dimension (e.g., height, depth, width, outer diameter, etc.) of the respective coarse conductive via CV is greater than that of the fine conductive via FV. The coarse dielectric layer124at each level may also be thicker and more rigid than the fine dielectric layer114. In some embodiments, the fine circuitry112of the respective fine redistribution segment110is connected to the coarse circuitry122through conductive connectors130. For example, the conductive connectors130are solder joints coupling the fine redistribution segments110and the coarse redistribution structure120. In some embodiments, underfill layers140are formed on the coarse redistribution structure120and each of the underfill layers140may fills a gap between the respective fine redistribution segment110and the underlying coarse redistribution structure120. The conductive connectors130may be surrounded by the underfill layers140for protection. In some embodiments, the sidewall110cof the respective fine redistribution segment110is partially covered by the underfill layer140. For example, the underfill layer140is in direct contact with the sidewall of the fine dielectric layer114. In some embodiments, the sidewall of the fine circuitry112is also in direct contact with the underfill layer140. Alternatively, the underfill layer140is omitted. In some embodiments, the fine redistribution segments110are mounted on one side of the coarse redistribution structure120and a plurality of external terminals150are mounted on the opposing side of the coarse redistribution structure120. In some embodiments, the coarse redistribution structure120includes a mask layer124A underlying the bottommost portion of the coarse dielectric layer124. For example, the bottommost portion of the coarse conductive pattern CP may be accessibly exposed by the mask layer124A, and the external terminals150are physically connected to the bottommost portion of the coarse conductive pattern CP. In some embodiments, the external terminals150are solder balls and the mask layer124A is a solder mask. The external terminals150may be electrically coupled to the fine redistribution segments110through the coarse redistribution structure120and the conductive connectors130. Alternatively, the mask layer124A is omitted. FIGS.2A-2Eare schematic cross-sectional views illustrating a manufacturing method of an integrated substrate structure according to some embodiments. It is noted that the resulting the integrated substrate structure described herein is similar to the integrated substrate structure10described inFIG.1, and thus the same reference numbers are used in the drawings and the description to refer to the same or like parts. Referring toFIGS.2A-2B, a release layer6may be formed on a temporary carrier5, where the release layer6may enhance the releasibility of the subsequently formed structure from the temporary carrier5in a subsequent de-bonding process. Next, a fine redistribution structure1100including a fine dielectric layer1140and a fine circuitry1120is formed over the temporary carrier5with the release layer6interposed therebetween. For example, the fine circuitry1120includes fine conductive patterns FP and fine conductive vias FV collectively viewed as the fine redistribution circuitry that is embedded in the fine dielectric layer1140. Referring toFIG.2Cand with reference toFIG.2B, the fine redistribution structure1100is segmented by removing portions of the fine redistribution structure1100to form a plurality of trenches TR. For example, the trenches TR spatially separate the fine redistribution segments110from one another. In some embodiments, the trenches TR are formed at intended locations to meet the chip placement requirements. For example, laser energy (e.g., excimer laser) is applied to the fine redistribution structure1100to form the trenches TR. In some embodiments, the respective fine redistribution segment has a substantially vertical sidewall110c. Other suitable removal techniques (e.g., chemical etching, lithography and etching, etc.) may be used depending on the materials of the fine redistribution structure1100. In some embodiments, during the removal of the portions of the fine redistribution structure1100, portions of the release layer6corresponding to those portions of the fine redistribution structure1100are also be removed. Alternatively, the temporary carrier5is exposed by the trenches TR. Referring toFIG.2D, the fine redistribution segments110and the coarse redistribution structure120may be bonded together. The coarse redistribution structure120may include the coarse circuitry122and the coarse dielectric layer124as mentioned above. The coarse redistribution structure120may be much larger and wider than the temporary carrier5and the structure thereon. For example, a circuit-board formation process is applied to form the coarse redistribution structure120, although other semiconductor processes may be used. In some embodiments, the fine redistribution segments110carried by the temporary carrier5are attached to the coarse redistribution structure120via the conductive connectors130. In some embodiments, the conductive connectors130include solder material, and a reflow process may be performed to bond the coarse circuitry122of the coarse redistribution structure120to the fine circuitry112of the fine redistribution segments110. Although the conductive connectors130may be made of other suitable bonding material(s), and other bonding techniques may also be used to mount the coarse redistribution structure120on the fine redistribution segments110. Referring toFIG.2Eand with reference toFIG.2D, the temporary carrier5may be removed to expose the top surface110aof the respective fine redistribution segment110. In some embodiments, the underfill layers140may be formed between the respective fine redistribution segment110and the coarse redistribution structure120to surround the conductive connectors130. Alternatively, the underfill layer is omitted. The external terminals150may be formed on the coarse circuitry122of the coarse redistribution structure120for further electrical connection (e.g., a system board, a mother board, a printed circuit board, etc.). Up to here, the fabrication of the integrated substrate structure10is complete. The integrated substrate structure10includes fine redistribution segments110which may provide a localized high density routing. In this manner, after chips (not shown) mounted on the top surfaces110aof the fine redistribution segments110, the fine redistribution segments110permits high bandwidth (e.g., density) chip-to-chip interconnects to be created. In addition, the aforementioned process is compatible with current processing facilities, so that the integrated substrate structure110may be fabricated without requiring major changes to the fabrication process. Moreover, the fine redistribution segments110and the coarse redistribution structure120are separately fabricated. In this manner, significant warpage of the integrated substrate structure10is avoided. The fine redistribution segments110may remain their geometrical planarity which permits reliable connections between the integrated substrate structure10and the subsequently-mounted chips. FIG.3Ais a schematic cross-sectional view of an integrated substrate structure in accordance with some embodiments, andFIG.3Bis a schematic plan view of an integrated substrate structure and various devices mounted thereon in accordance with some embodiments. It is noted that elements of the integrated substrate structure20illustrated inFIG.3Asame as/similar to the elements of the integrated substrate structure10illustrated inFIG.1are not described again for brevity. Referring toFIG.3A, the integrated substrate structure20includes the fine redistribution segments110disposed over the coarse redistribution structure120, and the external terminals150and the fine redistribution segments110are disposed at two opposing sides of the coarse redistribution structure120. The difference between the integrated substrate structure20shown inFIG.3Aand the integrated substrate structure10shown inFIG.1includes that the respective fine redistribution segment110is coupled to the coarse redistribution structure120through a plurality of conductive connectors130A, and embedded chip(s)/embedded device(s) may be interposed between the fine redistribution segment110and the coarse redistribution structure120. The integrated substrate structure20may also include mounted devices disposed on the periphery of the coarse redistribution structure120and next to the conductive connectors130A. In some embodiments, the respective conductive connector130A includes a conductive pillar132and a conductive joint134connected to the conductive pillar132, where the conductive pillar132is physically and electrically connected to the fine circuitry112of the fine redistribution segment110, and the conductive joint134is physically and electrically connected to the conductive pillar132and the coarse circuitry122of the coarse redistribution structure120. For example, the conductive pillar132and the conductive joint134are of different conductive materials. The material of the conductive pillar may include copper, gold, nickel, aluminium, platinum, tin, combinations thereof, an alloy thereof, etc. The material of the conductive joint may include solder or the like. The conductive joint134may be formed by initially forming a solder cap on the conductive pillar132, attaching the solder cap to the solder material (if any) on the coarse circuitry122, and reflowing the solder to form the conductive joints134. The fine redistribution segments110may be mounted on the coarse redistribution structure120after the reflow process performed on the conductive joints134. In some embodiments, the mask layer124B, similar to the mask layer124A, is formed on the coarse dielectric layer124and at least laterally covers the conductive joints134for protection, where the underfill layers140may be formed on the mask layer124B. Alternatively, the mask layer124B is omitted. In some embodiments, an embedded chip210is coupled to at least one of the fine redistribution segments110through chip connectors212. For example, the embedded chip210includes an active side210acoupled to the fine redistribution segment110, a back side210bfacing the coarse redistribution structure120, and a sidewall210cconnected to the active side210aand the back side210b. The chip connectors212at the active side210amay be or may include C4bumps, micro-bumps, etc., and may be physically and electrically connected to the bottom portion of the fine circuitry122. The embedded chip210may be surrounded by the conductive connectors130. In some embodiments, the sidewall of the conductive connector130A may be substantially parallel to the sidewall210cof the embedded chip210. The embedded chip210may include active circuits (e.g., logic circuits, memory circuits, processor circuits, a combination thereof), passive circuits, or other types of circuits. In some embodiments, the underfill layer140is formed between the coarse redistribution structure120and the fine redistribution segment110to cover the embedded chip210and the conductive connector130A for protection. The underfill layer140may cover the active side210ato surround the chip connectors212and may also cover the back side210band the sidewall210c. That is, the back side210bof the embedded chip210may be spatially apart from the coarse redistribution structure120through the underfill layer140. Alternatively, the back side210bof the embedded chip210is abutted against the coarse redistribution structure120. In some embodiments, an embedded device220, similar to the embedded chip210, is mounted on another one of the fine redistribution segment110and electrically connected to the fin circuitry112of the fine redistribution segment110. The embedded device220may be surrounded by the conductive connectors130A and embedded in the underfill layer140. The embedded device220may be or may include passive device such as resistor, capacitor, and/or inductor, etc. In some embodiments, at least one mounted device230is mounted on the coarse redistribution structure120and located on the periphery of the coarse redistribution structure120that surrounds an array of the fine redistribution segments110. The mounted device230may be or may include active/passive device(s), surface mounted device(s), etc. A plurality of the mounted devices230may be provided and may perform the same/similar function as the embedded device220, in accordance with some embodiments. The embedded chip210, the embedded device220, and the mounted device230are optionally integrated in the integrated substrate structure20to perform various functions depending on the product requirements. Referring toFIG.3Band with reference toFIG.3A, an electronic assembly200includes the integrated substrate structure20and a plurality of chips/devices mounted on the integrated substrate structure20. it is also noted that the plan view of the integrated substrate structure20labelled inFIG.3Bis drawn in a simplified manner to show the layout configuration of chips/devices, and the integrated substrate structure20may have a cross sectional view similar to the structure shown inFIG.3A. In some embodiments a plurality of chips (C1, C2, and C3) is mounted onto the integrated substrate structure20. For example, the fine redistribution segments110labelled inFIG.3Aof the integrated substrate structure20may interconnect between the chips C1and C2(and/or C3) to provide better electrical performance. In some embodiments, the chip C1is surrounded by the chips C2, where the chip C1may be any type of IC chip or logic chip, and the chips C2may be memory chips. Other types of chips may be used. In some embodiments, the chip C3may be also mounted on the integrated substrate structure20and disposed aside the array of the chips C1and C2, where the chip C3may be I/O chips. Although chip3may be other type of chip or may be omitted. In some embodiments, multiple passive components D1are mounted onto the integrated substrate structure20and disposed next to the array of the chips C1and C2. In some embodiments, an optical device D2is mounted on the integrated substrate structure20and disposed next to the chip C3and the array of the chips C1and C2. The optical device D2may be or may include an optical transceiver converting and coupling an information-containing electrical signal with an optical fiber (not shown). Other types of optical device may be used. It is understood that the layout configuration shown inFIG.3is only for illustrative purpose, and the number and configuration of devices construe no limitation in the disclosure. FIGS.4A-4Gare schematic cross-sectional views illustrating a manufacturing method of an integrated substrate structure with embedded chips/devices according to some embodiments. It is noted that the resulting the integrated substrate structure30described herein is similar to the integrated substrate structure20described inFIG.3A, and thus the detailed descriptions are simplified. Referring toFIGS.4A-4B, the fine redistribution structure110including a fine dielectric layer114and the fine circuitry112is formed over the temporary carrier5with the release layer6interposed therebetween. Next, a plurality of conductive pillars132may be formed on the fine circuitry112of the fine redistribution structure1100. The conductive pillars132may be plated or may be pre-formed and disposed on the fine circuitry112. Subsequently, the fine redistribution structure110is segmented by removing portions of the fine redistribution structure1100to form a plurality of first trenches TR1. The formation of the trenches TR1may be similar to the process described inFIG.2C. Referring toFIGS.4C-4D, a plurality of chips and devices may be disposed on the fine redistribution segments110. Each of the chips and devices may be surrounded by the conductive pillars132. Next, an insulating layer3100may be formed over the temporary carrier5to cover the fine redistribution segments110, the conductive pillars132, the chips210, and the devices220. Since the chips and devices are embedded in the insulating layer3100, the chips may be viewed as the embedded chips210and the devices may be viewed as the embedded devices220. In some embodiments, the insulating layer3100also fills the first trenches TR1. The insulating layer3100may be or may include molding compound, molding film, or liquid molding compound, and may be formed by a molding process or other suitable process. Other types of insulating material may be used. In some embodiments, a grinding process is performed on the insulating layer3100to expose at least the top surfaces132aof the conductive pillars132for further electrical connection. In some embodiments, a surface finishing process is performed on the top surfaces of the conductive pillars for the subsequently mounting process. Referring toFIG.4Eand with reference toFIG.4D, the insulating layer3100is segmented by removing portions of the insulating layer3100to form a plurality of second trenches TR2, where the locations of the second trenches TR2correspond to the location of the first trenches TR1. The width of the respective second trench TR2may be less than that of the corresponding first trench TR1. For example, the laser energy is applied to the insulating layer3100to form the second trenches TR2. Other suitable removal techniques (e.g., mechanical removal, etching, etc.) may be used depending on the material of the insulating layer3100. The second trenches TR2may spatially separate the insulating segments310from one another. The width of the respective second trench TR2may be controlled so that the respective insulating segment310laterally covers the fine redistribution segment110. For example, at least one side of the sidewall110cof the respective fine redistribution segment110is covered by the corresponding insulating segment310, and the sidewall110cand the sidewall310cmay be substantially aligned with each other. Alternatively, the fine redistribution segment110is fully wrapped by the insulating segment310. For example, the insulating segment310covers the sidewall110cand the top surface110aof the fine redistribution segment110, where the insulating segment310may be in direct contact with the fine circuitry112exposed by the fine dielectric layer114at the sidewall110c. Referring toFIG.4F, the coarse redistribution structure120is then mounted onto the resulting structure shown inFIG.4E. In some embodiments, the coarse circuitry122of the coarse redistribution structure120is coupled to the conductive pillars132through the conductive joints134′. For example, the solder bumps are initially formed on the topmost portion of the coarse circuitry122, and then the solder bumps are disposed on the conductive pillars132and reflowed to form the conductive joints134′. The conductive pillar132and the conductive joint134′ overlying the conductive pillar132may be collectively viewed as the conductive connector130B. Compared to the conductive connector130A shown inFIG.3A, the conductive pillar132of the conductive connector130B is laterally covered by the insulating segment310and the conductive joint134′ is exposed by the insulating segment310. For example, the contact interface between the conductive joint134′ and the coarse circuitry122is greater than the contact interface between the conductive joint134′ and the conductive pillar132. Referring toFIG.4Gand with reference toFIG.4F, the temporary carrier5may be removed to expose the fine circuitry112and the fine dielectric layer114of the respective fine redistribution segment110. The removal of the temporary carrier5may be similar to the process described previously, and thus the details thereof are omitted. In some embodiments, the underfill layers140may be formed between the insulating segments310and the coarse redistribution structure120to surround the conductive joints134′ for protection. For example, the underfill layer140may extend to cover the bottom of the sidewall310cof the insulating segment310. Alternatively, the underfill layers140may be omitted. The external terminals150are optionally formed on coarse circuitry122of the coarse redistribution structure120for further electrical connection. Up to here, the fabrication of the integrated substrate structure30with the embedded chips210and the embedded devices220is complete. Since the respective fine redistribution segment110is covered by the corresponding insulating segment310, the insulating segment310may provide rigid protection to the fine redistribution segment110so as to enhance the reliability. FIGS.5A-5Bare schematic cross-sectional views of an application of an integrated substrate structure in accordance with some embodiments. The integrated substrate structure20shown inFIGS.5A-5Bis similar to the integrated substrate structure20shown inFIG.3A, so the detailed descriptions are not repeated. It should be understood that the integrated substrate structure20may be replaced with the integrated substrate structure10shown inFIG.1, the integrated substrate structure30shown inFIG.4G, or other integrated substrate structure described elsewhere in the disclosure, in accordance with some embodiments. Referring toFIG.5A, various components may be mounted onto the integrated substrate structure20to form an electronic assembly300A depending on product requirements. For example, an IC chip C1′ is disposed on and electrically connected to one of the fine redistribution segments110, where the chip connectors322are physically and electrically connected to the fine circuitry112. In some embodiments, one or more than one 3D-IC chip stack C2′ may be disposed on the fine redistribution segment110, where the chip connectors332are physically and electrically connected to the fine circuitry112. For example, one of the 3D-IC chip stacks C2′ is disposed on one of the fine redistribution segments110and next to the IC chip C1′, and the one of the fine redistribution segments110interconnects the one of the 3D-IC chip stacks C2′ and the IC chip C1′. For example, the embedded chips210may interact with the one of the 3D-IC chip stacks C2′ and the IC chip C1′ through the fine circuitry112. Another one of the 3D-IC chip stacks C2′ may be disposed on and electrically connected to another one of the fine redistribution segments110, and the embedded device220may interact with the another one of the 3D-IC chip stacks C2′ through the fine circuitry112of the another one of the fine redistribution segments110. It should be noted that various 3D-IC chip stacks may be employed. For example, the other one of the 3D-IC chip stacks C2″ may be disposed on and electrically connected to the other one of the fine redistribution segments110, and the embedded device220may interact with the other one of the 3D-IC chip stacks C2″ through the fine circuitry112of the other one of the fine redistribution segments110. In some embodiments, a heat sink H1may be disposed on the one of the 3D-IC chip stacks C2′ and the IC chip C1′ for thermal management. It is noted that the type of the heat sink illustrated inFIG.5Ais an example and construes no limitation in the disclosure. In some embodiments, a power supply module P1is coupled to the coarse redistribution structure120through the external terminals150. For example, the IC chip C1′ and the 3D-IC chip stacks (C2′ and C2″) are disposed at one side of the integrated substrate structure20, and the power supply module P1is disposed at the opposing side of the integrated substrate structure20. The IC chip C1′ and the 3D-IC chip stacks (C2′ and C2″) may be electrically coupled to the power supply module P1through the integrated substrate structure20. A semiconductor device P2is optionally disposed next to the power supply module P1and also electrically coupled to the coarse redistribution structure120through the external terminals150. The semiconductor device P2may be (or include) active/passive component(s), optical component(s), or various mounted devices depending on product requirements. It is understood that the configuration shown inFIG.5Ais only for illustrative purpose, and the number and configuration of devices mounted onto the integrated substrate construe no limitation in the disclosure. Referring toFIG.5B, an electronic assembly300B is similar to the electronic assembly300A, and the difference therebetween includes that the external terminals may be provided with different sizes. For example, a plurality of external terminals150A are connected to the power supply module P1and/or the semiconductor device P2, and the external terminals150are to be connected to other electrical component (not shown). In some embodiments, during the formation of the external terminals (150and150A), a greater amount of solder material are applied to those locations for the external terminals150, and a less amount of solder material are applied to those locations for the external terminals150A. The external terminals150A may have the size (and/or the spacing) less than the size (and/or the spacing) of the external terminals150. FIG.6Ais a schematic plane view of a substrate layer including heat-dissipating features in accordance with some embodiments, andFIG.6Bis a schematic cross-sectional view of the substrate layer ofFIG.6A. Referring toFIGS.6A-6B, a substrate layer1200includes at least one heat-dissipating feature HF embedded in a dielectric layer1240. The dielectric layer1240may be a firm polymer layer, such as polypropylene or the like. The dielectric layer1240may include a composite material, such as a ceramic mixture. For example, the heat-dissipating features HF include ceramic (e.g., alumina, alumina nitride, etc.), glass, and/or other heat-dissipating material(s) such as isolated copper slug. In some embodiments, a plurality of the substrate layers1200may be stacked upon one another to form a coarse dielectric layer of a coarse redistribution structure (e.g., “120” described above). The heat-dissipating features HF fully embedded in the dielectric layer1240may enhance the mechanical strength of the substrate layer1200and also improve the capability of heat dissipation. The greater details will be discussed below. FIG.7is a schematic cross-sectional view of an integrated substrate structure including a substrate layer in accordance with some embodiments. The integrated substrate structure40shown inFIG.7is similar to the integrated substrate structure10shown inFIG.1, except for the coarse redistribution structure120A. Therefore, the details of the integrated substrate structure are simplified herein. Referring toFIG.7, the coarse redistribution structure120A of the integrated substrate structure40includes at least one heat-dissipating feature HF embedded inside the coarse dielectric layer124. It is noted that the number and configuration of the heat-dissipating features HF are shown only for illustrative purpose and construe no limitation in the disclosure. In some embodiments, the coarse circuitry122A of the coarse redistribution structure120A includes conductive through vias CT penetrating through the heat-dissipating feature HF for vertically connection between the coarse conductive patterns CP. In some embodiments, the top surface and the bottom surface of the heat-dissipating feature HF are in direct contact with the coarse conductive patterns CP, and the sidewall of the heat-dissipating feature HF is covered by the sublayer(s) of the coarse dielectric layer124. In some embodiments, the respective conductive through via CT extends longer than the respective coarse conductive via CV. Alternatively, the conductive through via CT may have similar height to the height of the coarse conductive via CV, depending on the thickness of the heat-dissipating feature HF. It is also noted that the coarse redistribution structure120A shown inFIG.7may be employed to other variations of integrated substrate structure discussed herein. FIGS.8-9are schematic cross-sectional views of a double-sided integrated substrate structure in accordance with some embodiments. Referring toFIG.8, a double-sided integrated substrate structure50is similar to the integrated substrate structure10shown inFIG.1, except that the double-sided integrated substrate structure50includes the fine redistribution segments110disposed on two opposing sides of the coarse redistribution structure120. The respective fine redistribution segment is electrically coupled to the coarse redistribution structure120through the conductive connectors130. It should be noted that the conductive connectors130may be replaced with other type of conductive connectors described elsewhere in the disclosure. The external terminals150shown inFIG.1may be thus omitted. The double-sided integrated substrate structure50may be configured to be coupled to various chips/devices/components to perform various functions depending on product requirements. Referring toFIG.9, a double-sided integrated substrate structure60is similar to the integrated substrate structure20shown inFIG.3A, so the details thereof are omitted. The difference between the double-sided integrated substrate structure60and the integrated substrate structure20includes that the fine redistribution segments110are disposed at two opposing sides of the coarse redistribution structure120. The external terminals150shown inFIG.3Amay be omitted. For example, the fine redistribution segments110, and the embedded chips210and the embedded device220interposed between the fine redistribution segments110and the coarse redistribution structure120may be formed at the bottom side of the coarse redistribution structure120. In some embodiments, the embedded chip/device may not be interposed between the fine redistribution segment110and the coarse redistribution structure120. In some embodiments, the mounted devices230may be provided at the bottom side of the coarse redistribution structure120. Based on the above, the integrated substrate structure including the coarse redistribution structure and the fine redistribution segments mounted thereon may be electrically coupled to various components (e.g., IC chips, passive devices, optical devices, etc.). The fine redistribution segments may be formed to have fine pitches so as to meet the I/O pitch requirements of various chips. The fine redistribution segments may be located at the intended locations on the coarse redistribution structure for interconnecting the chips/devices on the corresponding fine redistribution segments, thereby shortening the signal transmission path between the chips/devices. The coarse redistribution structure may be rigid enough to provide the mechanical support of the integrated substrate structure. In addition, the respective fine redistribution segment may be encapsulated by the insulating segment to enhance the overall mechanical strength. Moreover, the chips/devices may be interposed between the fine redistribution segment and the coarse redistribution structure and embedded inside the underfill layer or the insulating segment to form the embedded chips/devices that may enhance the functionality of the integrated substrate structure. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. | 37,242 |
11862546 | To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the Figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like. The methods and apparatus disclosed herein include novel thin-form-factor semiconductor core structures intended to replace more conventional semiconductor package, PCB, and chip carrier structures utilizing glass fiber-filled epoxy frames. Generally, the scalability of current semiconductor packages, PCBs, spacers, and chip carriers is limited by the rigidity and lack of planarity of the materials typically utilized to form these various structures (e.g., epoxy molding compound, FR-4 and FR-5 grade woven fiberglass cloth with epoxy resin binders, and the like). The intrinsic properties of these materials cause difficulty in patterning and utilizing fine (e.g., micron scale) features formed therein. Furthermore, as a result of the properties (e.g., insulativity) of currently-utilized materials, coefficient of thermal expansion (CTE) mismatch may occur between fiberglass frames, boards, molding compounds, and any chips disposed adjacent thereto. Therefore, current package, PCB, spacer, and carrier structures necessitate larger solder bumps with greater spacing to mitigate the effect of any warpage caused by CTE mismatch. Accordingly, conventional semiconductor package, PCB, spacer, and carrier frames are characterized by low through-structure electrical bandwidths, resulting in decreased overall power efficiency. The methods and apparatus disclosed herein provide semiconductor core structures that overcome many of the disadvantages associated with conventional semiconductor package, PCB, spacer, and carrier structures described above. FIGS.1A and1Billustrate cross-sectional views of a thin-form-factor semiconductor core assembly100according to some embodiments. The semiconductor core assembly100may be utilized for structural support and electrical interconnection of semiconductor packages mounted thereon. In further examples, the semiconductor core assembly100may be utilized as a carrier structure for a surface-mounted device, such as a chip or graphics card. The semiconductor core assembly100generally includes a core structure102, an optional passivating layer104, and an insulating layer118. In one embodiment, the core structure102includes a patterned (e.g., structured) substrate formed of any suitable substrate material. For example, the core structure102includes a substrate formed from a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, glass (e.g., borosilicate glass), sapphire, alumina, and/or ceramic materials. In one embodiment, the core structure102includes a monocrystalline p-type or n-type silicon substrate. In one embodiment, the core structure102includes a polycrystalline p-type or n-type silicon substrate. In another embodiment, the core structure102includes a p-type or an n-type silicon solar substrate. The substrate utilized to form the core structure102may further have a polygonal or circular shape. For example, the core structure102may include a substantially square silicon substrate having lateral dimensions between about 120 mm and about 180 mm, with or without chamfered edges. In another example, the core structure102may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 50 mm, for example about 300 mm. The core structure102has a thickness T1between about 50 μm and about 1000 μm, such as a thickness T1between about 70 μm and about 800 μm. For example, the core structure102has a thickness T1between about 80 μm and about 400 μm, such as a thickness T1between about 100 μm and about 200 μm. In another example, the core structure102has a thickness T1between about 70 μm and about 150 μm, such as a thickness T1between about 100 μm and about 130 μm. In another example, the core structure102has a thickness T1between about 700 μm and about 800 μm, such as a thickness T1between about 725 μm and about 775 μm. The core structure102further includes one or more holes or core vias103(hereinafter referred to as “core vias”) formed therein to enable conductive electrical interconnections to be routed through the core structure102. Generally, the one or more core vias103are substantially cylindrical in shape. However, other suitable morphologies for the core vias103are also contemplated. The core vias103may be formed as singular and isolated core vias103through the core structure102or in one or more groupings or arrays. In one embodiment, a minimum pitch Pi between each core via103is less than about 1000 μm, such as between about 25 μm and about 200 μm. For example, the pitch Pi is between about 40 μm and about 150 μm. In one embodiment, the one or more core vias103have a diameter V1less than about 500 μm, such as a diameter V1less than about 250 μm. For example, the core vias103have a diameter V1between about 25 μm and about 100 μm, such as a diameter V1between about 30 μm and about 60 μm. In one embodiment, the core vias103have a diameter V1of about 40 μm. The optional passivating layer104may be formed on one or more surfaces of the core structure102, including a first surface106, a second surface108, and one or more sidewalls of the core vias103. In one embodiment, the passivating layer104is formed on substantially all exterior surfaces of the core structure102such that the passivating layer104substantially surrounds the core structure102. Thus, the passivating layer104provides a protective outer barrier for the core structure102against corrosion and other forms of damage. In one embodiment, the passivating layer104is formed of an oxide film or layer, such as a thermal oxide layer. In some examples, the passivating layer104has a thickness between about 100 nm and about 3 μm, such as a thickness between about 200 nm and about 2.5 μm. In one example, the passivating layer104has a thickness between about 300 nm and about 2 μm, such as a thickness of about 1.5 μm. The insulating layer118is formed on one or more surfaces of the core structure102or the passivating layer104and may substantially encase the passivating layer104and/or the core structure102. Thus, the insulating layer118may extend into the core vias103and coat the passivating layer104formed on the sidewalls thereof or directly coat the core structure102, thus defining the diameter V2as depicted inFIG.1A. In one embodiment, the insulating layer118has a thickness T2from an outer surface of the core structure102or the passivating layer104to an adjacent outer surface of the insulating layer118(e.g., major surfaces105,107) that is less than about 50 μm, such as a thickness T2less than about 20 μm. For example, the insulating layer118has thickness T2between about 5 μm and about 10 μm. In one embodiment, the insulating layer118is formed of polymer-based dielectric materials. For example, the insulating layer118is formed from a flowable build-up material. Accordingly, although hereinafter referred to as an “insulating layer,” the insulating layer118may also be described as a dielectric layer. In a further embodiment, the insulating layer118is formed of an epoxy resin material having a ceramic filler, such as silica (SiO2) particles. Other examples of ceramic fillers that may be utilized to form the insulating layer118include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4, Sr2Ce2Ti5O16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO) and the like. In some examples, the ceramic fillers utilized to form the insulating layer118have particles ranging in size between about 40 nm and about 1.5 μm, such as between about 80 nm and about 1 μm. For example, the ceramic fillers have particles ranging in size between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the ceramic fillers include particles having a size less than about 10% of the width or diameter of adjacent core vias103in the core structure102, such as a size less than about 5% of the width or diameter of the core vias103. One or more through-assembly holes or vias113(hereinafter referred to as “through-assembly vias”) are formed through the insulating layer118where the insulating layer118extends into the core vias103. For example, the through-assembly vias113may be centrally formed within the core vias103having the insulating layer118disposed therein. Accordingly, the insulating layer118forms one or more sidewalls of the through-assembly vias113, wherein the through-assembly vias113have a diameter V2lesser than the diameter V1of the core vias103. In one embodiment, the through-assembly vias113have a diameter V2less than about 100 μm, such as less than about 75 μm. For example, the through-assembly vias113have a diameter V2less than about 50 μm, such as less than about 35 μm. In one embodiment, the through-assembly vias113have a diameter of between about 25 μm and about 50 μm, such as a diameter of between about 35 μm and about 40 μm. The through-assembly vias113provide channels through which one or more electrical interconnections144are formed in the semiconductor core assembly100. In one embodiment, the electrical interconnections144are formed through the entire thickness of the semiconductor core assembly100(i.e. from a first major surface105to a second major surface107of the semiconductor core assembly100). For example, the electrical interconnections144may have a longitudinal length corresponding to a total thickness of the semiconductor core assembly100between about 50 μm and about 1000 μm, such as a longitudinal length between about 200 μm and about 800 μm. In one example, the electrical interconnections144have a longitudinal length of between about 400 μm and about 600 μm, such as longitudinal length of about 500 μm. In another embodiment, the electrical interconnections144are only formed through a portion of the thickness of the semiconductor core assembly100. In further embodiments, the electrical interconnections144may protrude from a major surface of the semiconductor core assembly100, such as the major surfaces105,107as depicted inFIG.1A. The electrical interconnections144may be formed of any conductive materials used in the field of integrated circuits, circuit boards, chip carriers, and the like. For example, the electrical interconnections144are formed of a metallic material, such as copper, aluminum, gold, nickel, silver, palladium, tin, or the like. In the embodiment depicted inFIG.1A, the electrical interconnections144have a lateral thickness equal to the diameter V2of the through-assembly vias113in which they are formed. In another embodiment, such as depicted inFIG.1B, the semiconductor core assembly100further includes an adhesion layer140and/or a seed layer142formed thereon for electrical isolation of the electrical interconnections144. In one embodiment, the adhesion layer140is formed on surfaces of the insulating layer118adjacent to the electrical interconnections144, including the sidewalls of the through-assembly vias113. Thus, as depicted inFIG.1B, the electrical interconnections144have a lateral thickness less than the diameter V2of the through-assembly vias113in which they are formed. In yet another embodiment, the electrical interconnections144only cover the surfaces of the sidewalls of the through-assembly vias113, and thus may have a hollow core therethrough. The adhesion layer140may be formed of any suitable materials, including but not limited to titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, and the like. In one embodiment, the adhesion layer140has a thickness Bi between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesion layer140has a thickness Bi between about 75 nm and about 125 nm, such as about 100 nm. The optional seed layer142comprises a conductive material, including but not limited to copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. The seed layer142may be formed on the adhesion layer140or directly on the sidewalls of the through-assembly vias113(e.g., on the insulating layer118without an adhesion layer therebetween). In one embodiment, the seed layer142has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer142has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In some embodiments, such as depicted inFIG.1B, the semiconductor core assembly100further includes one or more redistribution layers150formed on a first side175and/or a second side177of the semiconductor core assembly100(the redistribution layer150is depicted as being formed on the second side177inFIG.1B). In one embodiment, the redistribution layer150is formed of substantially the same materials as the insulating layer118(e.g., polymer-based dielectric materials), and thus forms an extension thereof. In other embodiments, the redistribution layer150is formed of a different material than the insulating layer118. For example, the redistribution layer150may be formed of a photodefinable polyimide material, a non-photosensitive polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicon dioxide, and/or silicon nitride. In another example, the redistribution layer150is formed from a different inorganic dielectric material than the insulating layer118. In one embodiment, the redistribution layer150has a thickness between about 5 μm and about 50 μm, such as a thickness between about 10 μm and about 40 μm. For example, the redistribution layer150has a thickness between about 20 μm and about 30 μm, such as about 25 μm. The redistribution layer150may include one or more redistribution connections154formed through redistribution vias153for relocating contact points of the electrical interconnections144to desired locations on the surfaces of the semiconductor core assembly100, such as the major surfaces105,107. In some embodiments, the redistribution layer150may further include one or more external electrical connections (not shown) formed on the major surfaces105,107, such as a ball grid array or solder balls. Generally, the redistribution vias153and the redistribution connections154have substantially similar or smaller lateral dimensions relative to the through-assembly vias113and the electrical interconnections144, respectively. For example, the redistribution vias153have a diameter V3between about 2 μm and about 50 μm, such as a diameter V3between about 10 μm and about 40 μm, such as a diameter V3between about 20 μm and about 30 μm. Furthermore, the redistribution layer150may include the adhesion layer140and the seed layer142formed on surfaces adjacent to the redistribution connections154, including sidewalls of the redistribution vias153. FIG.2illustrates a flow diagram of a representative method200of forming a semiconductor core assembly. The method200has multiple operations210,220,230, and240. Each operation is described in greater detail with reference toFIGS.3-12L. The method may include one or more additional operations which are carried out before any of the defined operations, between two of the define operations, or after all the defined operations (except where the context excludes the possibility). In general, the method200includes structuring a substrate to be utilized as a core structure (e.g., frame) at operation210, further described in greater detail with reference toFIGS.3and4A-4D. At operation220, an insulating layer is formed on the core structure102, further described in greater detail with reference toFIGS.5,6A-6I,7, and8A-8E. At operation230, one or more interconnections are formed through the core structure102and the insulating layer, further described in greater detail with reference toFIGS.9and10A-10H. At operation240, a redistribution layer is formed on the insulating layer to relocate contact points of the interconnections to desired locations on a surface of an assembled core assembly and the core assembly is thereafter singulated. In some embodiments, one or more additional redistribution layers may be formed in addition to the first redistribution layer, described in greater detail with reference toFIGS.11and12A-12L. FIG.3illustrates a flow diagram of a representative method300for structuring a substrate400to be utilized as a core structure.FIGS.4A-4Dschematically illustrate cross-sectional views of a substrate400at various stages of the substrate structuring process300represented inFIG.3. Therefore,FIG.3andFIGS.4A-4Dare herein described together for clarity. The method300begins at operation310and correspondingFIG.4A. As described with reference to the core structure102above, the substrate400is formed of any suitable substrate material including but not limited to a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, glass material (e.g., borosilicate glass), sapphire, alumina, and/or ceramic material. In one embodiment, the substrate400is a monocrystalline p-type or n-type silicon substrate. In one embodiment, the substrate400is a multicrystalline p-type or n-type silicon substrate. In another embodiment, the substrate400is a p-type or an n-type silicon solar substrate. The substrate400may further have a polygonal or circular shape. For example, the substrate400may include a substantially square silicon substrate having lateral dimensions between about 140 mm and about 180 mm, with or without chamfered edges. In another example, the substrate400may include a circular silicon containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 300 mm. Unless otherwise noted, embodiments and examples described herein are conducted on substrates having a thickness between about 50 μm and about 1000 μm, such as a thickness between about 90 μm and about 780 μm. For example, the substrate400has a thickness between about 100 μm and about 300 μm, such as a thickness between about 110 μm and about 200 μm. Prior to operation310, the substrate400may be sliced and separated from a bulk material by wire sawing, scribing and breaking, mechanical abrasive sawing, or laser cutting. Slicing typically causes mechanical defects or deformities in substrate surfaces formed therefrom, such as scratches, micro-cracking, chipping, and other mechanical defects. Thus, the substrate400is exposed to a first damage removal process at operation310to smoothen and planarize surfaces thereof and remove mechanical defects in preparation for later structuring operations. In some embodiments, the substrate400may further be thinned by adjusting the process parameters of the first damage process. For example, a thickness of the substrate400may be decreased with increased exposure to the first damage removal process. The first damage removal process at operation310includes exposing the substrate400to a substrate polishing process and/or an etch process followed by rinsing and drying processes. In some embodiments, operation310includes a chemical mechanical polishing (CMP) process. In one embodiment, the etch process is a wet etch process including a buffered etch process that is selective for the removal of a desired material (e.g., contaminants and other undesirable compounds). In other embodiments, the etch process is a wet etch process utilizing an isotropic aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the wet etch process. In one embodiment, the substrate400is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate400is immersed in an aqueous KOH etching solution for etching. In some embodiments, the etching solution is heated to a temperature between about 30° C. and about 100° C. during the etch process, such as between about 40° C. and 90° C. For example, the etching solution is heated to a temperature of about 70° C. In still other embodiments, the etch process at operation310is a dry etch process. An example of a dry etch process includes a plasma-based dry etch process. The thickness of the substrate400is modulated by controlling the time of exposure of the substrate400to the etchants (e.g., etching solution) utilized during the etch process. For example, a final thickness of the substrate400is reduced with increased exposure to the etchants. Alternatively, the substrate400may have a greater final thickness with decreased exposure to the etchants. At operation320, the now planarized and substantially defect-free substrate400is patterned to form one or more core vias403therein (four core vias403are depicted in the cross-section of substrate400inFIG.4B). The core vias403are utilized to form direct-contact electrical interconnections through the substrate400. Generally, the one or more core vias403may be formed by laser ablation (e.g. direct laser patterning). Any suitable laser ablation system may be utilized to form the one or more core vias403. In some examples, the laser ablation system utilizes an infrared (IR) laser source. In some examples, the laser source is a picosecond ultraviolet (UV) laser. In other examples, the laser is a femtosecond UV laser. In still other examples, the laser source is a femtosecond green laser. The laser source of the laser ablation system generates a continuous or pulsed laser beam for patterning of the substrate400. For example, the laser source may generate a pulsed laser beam having a frequency between 5 kHz and 500 kHz, such as between 10 kHz and about 200 kHz. In one example, the laser source is configured to deliver a pulsed laser beam at a wavelength between about 200 nm and about 1200 nm and a pulse duration between about 10 ns and about 5000 ns with an output power between about 10 Watts and about 100 Watts. The laser source is configured to form any desired pattern of features in the substrate400, including the core vias403. In some embodiments, the substrate400is optionally coupled to a carrier plate (not shown) before being patterned. The optional carrier plate may provide mechanical support for the substrate400during patterning thereof and may prevent the substrate400from breaking. The carrier plate may be formed of any suitable chemically- and thermally-stable rigid material including but not limited to glass, ceramic, metal, or the like. In some examples, the carrier plate has a thickness between about 1 mm and about 10 mm, such as between about 2 mm and about 5 mm. In one embodiment, the carrier plate has a textured surface. In other embodiments, the carrier plate has a polished or smoothened surface. The substrate400may be coupled to the carrier plate utilizing any suitable temporary bonding material, including but not limited to wax, glue, or similar bonding material. In some embodiments, patterning the substrate400may cause unwanted mechanical defects in the surfaces of the substrate400, including chipping, cracking, and/or warping. Thus, after performing operation320to form the core vias403in the substrate400, the substrate400is exposed to a second damage removal and cleaning process at operation330substantially similar to the first damage removal process at operation310to smoothen the surfaces of the substrate400and remove unwanted debris. As described above, the second damage removal process includes exposing the substrate400to a wet or dry etch process, followed by rinsing and drying thereof. The etch process proceeds for a predetermined duration to smoothen the surfaces of the substrate400, and particularly the surfaces exposed to laser patterning operations. In another aspect, the etch process is utilized to remove any undesired debris remaining on the substrate400from the patterning process. After removal of mechanical defects in the substrate400at operation330, the substrate400is exposed to a passivation process at operation340andFIG.4Dto grow or deposit a passivating film or layer, such as oxide layer404, on desired surfaces thereof (e.g., all surfaces of the substrate400). In one embodiment, the passivation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature between about 800° C. and about 1200° C., such as between about 850° C. and about 1150° C. For example, the thermal oxidation process is performed at a temperature between about 900° C. and about 1100° C., such as a temperature between about 950° C. and about 1050° C. In one embodiment, the thermal oxidation process is a wet oxidation process utilizing water vapor as an oxidant. In one embodiment, the thermal oxidation process is a dry oxidation process utilizing molecular oxygen as the oxidant. It is contemplated that the substrate400may be exposed to any suitable passivation process at operation340to form the oxide layer404or any other suitable passivating layer thereon. The resulting oxide layer404generally has a thickness between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. For example, the oxide layer404has a thickness between about 300 nm and about 2 μm, such as about 1.5 μm Upon passivation, the substrate400is ready to be utilized as a core structure402for the formation of a core assembly, such as the semiconductor core assembly100.FIGS.5and7illustrate flow diagrams of representative methods500and700, respectively, for forming an insulating layer618on the core structure402.FIGS.6A-6Ischematically illustrate cross-sectional views of the core structure402at different stages of the method500depicted inFIG.5, andFIGS.8A-8Eschematically illustrate cross-sectional views of the core structure402at different stages of the method700depicted inFIG.7. For clarity,FIG.5andFIGS.6A-6Iare herein described together andFIG.7andFIGS.8A-8Eare herein described together. Generally, the method500begins at operation502andFIG.6Awherein a first surface406of the core structure402at a first side475, now having the core vias403formed therein and the oxide layer404formed thereon, is placed on and affixed to a first insulating film616a. In one embodiment, the first insulating film616aincludes one or more layers formed of polymer-based dielectric materials. For example, the first insulating film616aincludes one or more layers formed of flowable build-up materials. In one embodiment, the first insulating film616aincludes a flowable epoxy resin layer618a. Generally, the epoxy resin layer618ahas a thickness less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the epoxy resin layer618ahas a thickness between about 10 μm and about 25 μm. The epoxy resin layer618amay be formed of a ceramic-filler-containing epoxy resin, such as an epoxy resin filled with (e.g., containing) silica (SiO2) particles. Other examples of ceramic fillers that may be used to form the epoxy resin layer618aand other layers of the insulating film616ainclude aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO) and the like. In some examples, the ceramic fillers utilized to form the epoxy resin layer618ahave particles ranging in size between about 40 nm and about 1.5 μm, such as between about 80 nm and about 1 μm. For example, the ceramic fillers utilized to form the epoxy resin layer618ahave particles ranging in size between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the first insulating film616afurther includes one or more protective layers. For example, the first insulating film616aincludes a polyethylene terephthalate (PET) protective layer622a, such as a biaxial PET protective layer622a. However, any suitable number and combination of layers and materials is contemplated for the first insulating film616a. In some embodiments, the entire insulating film616ahas a thickness less than about 120 μm, such as a thickness less than about 90 μm. In some embodiments, after affixing the core structure402to the first insulating film616a, the core structure402may then be placed on a carrier624adjacent the first side475thereof for additional mechanical stabilization during later processing operations. Generally, the carrier624is formed of any suitable mechanically and thermally stable material capable of withstanding temperatures above 100° C. For example, in one embodiment the carrier624comprises polytetrafluoroethylene (PTFE). In another example, the carrier624is formed of polyethylene terephthalate (PET). At operation504andFIG.6B, a first protective film660is affixed to a second surface408on a second side477of the core structure402. The protective film660is coupled to the core structure402on the second side477and opposite of the first insulating film616asuch that it covers the core vias403. In one embodiment, the protective film660is formed of a material similar to that of the protective layer622a. For example, the protective film660is formed of PET, such as biaxial PET. However, the protective film660may be formed of any suitable protective materials. In some embodiments, the protective film660has a thickness between about 50 μm and about 150 μm. The core structure402, now affixed to the insulating film616aat the first side475and the protective film660at the second side477, is exposed to a first lamination process at operation506. During the lamination process, the core structure402is exposed to elevated temperatures, causing the epoxy resin layer618aof the insulating film616ato soften and flow into the open voids or volumes between the insulating film616aand the protective film660, such as into the core vias403. Accordingly, the core vias403become at least partially filled (e.g., occupied) with the insulating material of the epoxy resin layer618a, as depicted inFIG.6C. Further, the core structure402becomes partially surrounded by the insulating material of the epoxy resin layer618a. In one embodiment, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed by use of a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 psig and about 150 psig while a temperature between about 80° C. and about 140° C. is applied to core structure402and insulating film616afor a period between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 psig and about 100 psig, and a temperature between about 100° C. and about 120° C. for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes. At operation508, the protective film660is removed and the core structure402, now having the laminated insulating material of the epoxy resin layer618aat least partially surrounding the core structure402and partially filling the core vias403, is placed on a second protective film662. As depicted inFIG.6D, the second protective film662is coupled to the core structure402adjacent the first side475such that the second protective film662is disposed against (e.g., adjacent) the protective layer622aof the insulating film616a. In some embodiments, the core structure402, now coupled to the protective film662, may be optionally placed on the carrier624for additional mechanical support on the first side475. In some embodiments, the protective film662is placed on the carrier624prior to coupling the protective film662with the core structure402. Generally, the protective film662is substantially similar in composition to the protective film660. For example, the protective film662may be formed of PET, such as biaxial PET. However, the protective film662may be formed of any suitable protective materials. In some embodiments, the protective film662has a thickness between about 50 μm and about 150 μm. Upon coupling the core structure402to the second protective film662, a second insulating film616bsubstantially similar to the first insulating film616ais placed over the second side477at operation510andFIG.6E, thus replacing the protective film660. In one embodiment, the second insulating film616bis positioned on the second side477of the core structure402such that an epoxy resin layer618bof the second insulating film616bcovers the core vias403. In one embodiment, the placement of the second insulating film616bon the core structure402may form one or more voids between the insulating film616band the already-laminated insulating material of the epoxy resin layer618athat partially surrounds the core structure402and partially fills the core vias403. The second insulating film616bmay include one or more layers formed of polymer-based dielectric materials similar to the insulating film616a. As depicted inFIG.6E, the second insulating film616bincludes an epoxy resin layer618bsubstantially similar to the epoxy resin layer618adescribed above. The second insulating film616bmay further include a protective layer622bformed of similar materials to the protective layer622a, such as PET. At operation512, a third protective film664is placed over the second insulating film616b, as depicted inFIG.6F. Generally, the protective film664is substantially similar in composition to the protective films660,662. For example, the protective film664is formed of PET, such as biaxial PET. However, the protective film664may be formed of any suitable protective materials. In some embodiments, the protective film664has a thickness between about 50 μm and about 150 μm. The core structure402, now affixed to the insulating film616band the protective film664on the second side477and the protective film662and the optional carrier624on the first side475, is exposed to a second lamination process at operation514andFIG.6G. Similar to the lamination process at operation504, the core structure402is exposed to elevated temperatures, causing the epoxy resin layer618bof the insulating film616bto soften and flow into any open voids or volumes between the insulating film616band the already-laminated insulating material of the epoxy resin layer618a, thus integrating itself with the insulating material of the epoxy resin layer618a. Accordingly, the core vias403become completely filled (e.g. packed, sealed) with insulating material of both epoxy resin layers618a,618b. In one embodiment, the second lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed by use of a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 psig and about 150 psig while a temperature between about 80° C. and about 140° C. is applied to the core structure402and the insulating film616afor a period between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 psig and about 100 psig, and a temperature between about 100° C. and about 120° C. for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes. After lamination, the core structure402is disengaged from the carrier624at operation516and the protective films662,664are removed, resulting in a laminated intermediate core assembly602. As depicted inFIG.6H, the intermediate core assembly602includes the core structure402having one or more core vias403formed therethrough and filled with the insulating dielectric material of the insulating films616a,616b. The insulating dielectric material of the epoxy resin layers618a,618bfurther encases the core structure402having the oxide layer404formed thereon such that the insulating material covers at least two surfaces or sides of the core structure402(e.g., surfaces406,408). In some examples, the protective layers622a,622bare also removed from the intermediate core assembly602at operation516. Generally, the protective layers622aand622b, the carrier624, and the protective films662and664are removed from the intermediate core assembly602by any suitable mechanical processes such as peeling therefrom. Upon removal of the protective layers622a,622band the protective films662,664, the intermediate core assembly602is exposed to a cure process to fully cure (i.e. harden through chemical reactions and cross-linking) the insulating dielectric material of the epoxy resin layers618a,618b, thus forming an insulating layer618. The insulating layer618substantially surrounds the core structure402and fills the core vias403. For example, the insulating layer618contacts or encapsulates at least the107,477of the core structure402(including surfaces406,408). In one embodiment, the cure process is performed at high temperatures to fully cure the intermediate core assembly602. For example, the cure process is performed at a temperature between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation516is performed at or near ambient (e.g. atmospheric) pressure conditions. After curing, one or more through-assembly vias613are drilled through the intermediate core assembly602at operation518, forming channels through the entire thickness of the intermediate core assembly602for subsequent interconnection formation. In some embodiments, the intermediate core assembly602may be placed on a carrier, such as the carrier624, for mechanical support during the formation of the through-assembly vias613. The through-assembly vias613are drilled through the core vias403that were formed in the core structure402and subsequently filled with the insulating layer618. Thus, the through-assembly vias613may be circumferentially surrounded by the insulating layer618filled within the core vias403. By having the ceramic-filler-containing epoxy resin material of the insulating layer618line the walls of the core vias403, capacitive coupling between the conductive silicon-based core structure402and interconnections1044(described with reference toFIG.9andFIGS.10A-10H) in the completed (e.g., final) semiconductor core assembly1270(described with reference toFIG.11andFIGS.12K and12L) is significantly reduced as compared to other conventional interconnecting structures that utilize conventional via-insulating liners or films. Furthermore, the flowable nature of the epoxy resin material of the insulating layer618enables more consistent and reliable encapsulation and insulation, thus enhancing electrical performance by minimizing leakage current of the completed semiconductor core assembly1270. In one embodiment, the through-assembly vias613have a diameter less than about 100 μm, such as less than about 75 μm. For example, the through-assembly vias613have a diameter less than about 50 μm, such as less than about 35 μm. In some embodiments, the through-assembly vias613have a diameter between about 25 μm and about 50 μm, such as a diameter between about 35 μm and about 40 μm. In one embodiment, the through assembly vias613are formed using any suitable mechanical process. For example, the through-assembly vias613are formed using a mechanical drilling process. In one embodiment, through-assembly vias613are formed through the intermediate core assembly602by laser ablation. For example, the through-assembly vias613are formed using an ultraviolet laser. In one embodiment, the laser source utilized for laser ablation has a frequency between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam at a pulse duration between about 10 ns and about 100 ns with a pulse energy between about 50 microjoules (μJ) and about 500 μJ. Utilizing an epoxy resin material containing small ceramic filler particles further promotes more precise and accurate laser patterning of small-diameter vias, such as the through-assembly vias613, as the small ceramic filler particles therein exhibit reduced laser light reflection, scattering, diffraction, and transmission of the laser light away from the area in which the via is to be formed during the laser ablation process. In some embodiments, the through-assembly vias613are formed within (e.g., through) the core vias403in such a way that the remaining ceramic-filler-containing epoxy resin material (e.g., dielectric insulating material) on the sidewalls of the core vias403has an average thickness between about 1 μm and about 50 μm. For example, the remaining ceramic-filler-containing epoxy resin material on the sidewalls of the core vias403has an average thickness between about 5 μm and about 40 μm, such as between about 10 μm and about 30 μm. Accordingly, the resulting structure after formation of the through-assembly vias613may be described as a “via-in-via” (e.g., a via centrally formed in a dielectric material within a via of the core structure). The via-in-via structure includes a dielectric sidewall passivation consisting of a ceramic-particle-filled epoxy material and disposed on a thin layer of thermal oxide formed on the sidewalls of the core vias403. After formation of the through-assembly vias613, the intermediate core assembly602is exposed to a de-smear process. During the de-smear process, any unwanted residues and/or debris caused by laser ablation during the formation of the through-assembly vias613are removed therefrom. The de-smear process thus cleans the through-assembly vias613for subsequent metallization. In one embodiment, the de-smear process is a wet de-smear process. Any suitable solvents, etchants, and/or combinations thereof may be utilized for the wet de-smear process. In one example, methanol may be utilized as a solvent and copper (II) chloride dihydrate (CuCl2·H2O) as an etchant. Depending on the residue thickness, exposure duration of the intermediate core assembly602to the wet de-smear process may be varied. In another embodiment, the de-smear process is a dry de-smear process. For example, the de-smear process may be a plasma de-smear process with an O2/CF4mixture gas. The plasma de-smear process may include generating a plasma by applying a power of about 700 W and flowing O2:CF4at a ratio of about 10:1 (e.g., 100:10 sccm) for a time period between about 60 seconds and about 120 seconds. In further embodiments, the de-smear process is a combination of wet and dry processes. Following the de-smear process at operation518, the intermediate core assembly602is ready for formation of interconnection paths therein, described below with reference toFIG.9andFIGS.10A-10H. As discussed above,FIG.5andFIGS.6A-6Iillustrate a representative method500for forming the intermediate core assembly602.FIG.7andFIGS.8A-8Eillustrate an alternative method700substantially similar to the method500but with fewer operations. The method700generally includes five operations710-750. However, operations710,740, and750of the method700are substantially similar to the operations502,516, and518of the method500, respectively. Thus, only operations720,730, and740, depicted inFIGS.8B,8C, and8D, respectively, are herein described for clarity. After fixing the first insulating film616ato the first surface406on the first side475of the core structure402, a second insulating film616bis coupled to the second surface408on the opposing side477at operation720andFIG.8B. In some embodiments, the second insulating film616bis positioned on the surface408of the core structure402such that the epoxy resin layer618bof the second insulating film616bcovers all of the core vias403. As depicted inFIG.8B, the core vias403form one or more voids or gaps between the insulating films616aand616b. In some embodiments, a second carrier625is affixed to the protective layer622bof the second insulating film616bfor additional mechanical support during later processing operations. At operation730andFIG.8C, the core structure402, now affixed to the insulating films616aand616bon opposing sides thereof, is exposed to a single lamination process. During the single lamination process, the core structure402is exposed to elevated temperatures, causing the epoxy resin layers618aand618bof both insulating films616a,616bto soften and flow into the open voids or volumes created by the core vias403between the insulating films616a,616b. Accordingly, the core vias403become filled with the insulating material of the epoxy resin layers618aand618b. Similar to the lamination processes described with reference toFIG.5andFIGS.6A-6I, the lamination process at operation730may be a vacuum lamination process that may be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed by use of a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 psig and about 150 psig while a temperature between about 80° C. and about 140° C. is applied to core structure402and the insulating films616a,616bfor a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psig and about 100 psig, a temperature between about 100° C. and about 120° C., and for a period between about 2 minutes and 10 minutes. For example, the lamination process at operation730is performed at a temperature of about 110° C. for a period of about 5 minutes. At operation740, the one or more protective layers of the insulating films616a,616bare removed from the core structure402, resulting in the laminated intermediate core assembly602. In one example, the protective layers622a,622bare removed from the core structure402, and thus the intermediate core assembly602is also disengaged from the first and second carriers624,625. Generally, the protective layers622a,622band the carriers624,625are removed by any suitable mechanical processes such as peeling therefrom. As depicted inFIG.8D, the intermediate core assembly602includes the core structure402having one or more core vias403formed therein and filled with the insulating dielectric material of the epoxy resin layers618a,618b. The insulating material further encases the core structure402such that the insulating material covers at least two surfaces or sides of the core structure402, for example, the surfaces406,408. Upon removal of the protective layers622a,622b, the intermediate core assembly602is exposed to a cure process to fully cure the insulating dielectric material of the epoxy resin layers618a,618b. Curing of the insulating material results in the formation of the insulating layer618. As depicted inFIG.8Dand similar to operation516corresponding withFIG.6H, the insulating layer618substantially surrounds the core structure402and fills the core vias403. In one embodiment, the cure process is performed at high temperatures to fully cure the intermediate core assembly602. For example, the cure process is performed at a temperature between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation740is performed at or near ambient (e.g. atmospheric) pressure conditions. After curing at operation740, the method700is substantially similar to operation520of the method500. Accordingly, one or more through-assembly vias613are drilled through the intermediate core assembly602, followed by exposing the intermediate core assembly602to a de-smear process. Upon completion of the de-smear process, the intermediate core assembly602is ready for formation of interconnection paths therein, as described below. FIG.9illustrates a flow diagram of a representative method900for forming electrical interconnections through the intermediate core assembly602.FIGS.10A-10Hschematically illustrate cross-sectional views of the intermediate core assembly602at different stages of the process of the method900depicted inFIG.9. Thus,FIG.9andFIGS.10A-10Hare herein described together for clarity. In one embodiment, the electrical interconnections formed through the intermediate core assembly602are formed of copper. Thus, the method900generally begins at operation910andFIG.10Awherein the intermediate core assembly602, having through-assembly vias613formed therein, has a barrier or adhesion layer1040and/or a seed layer1042formed thereon. An enlarged partial view of the adhesion layer1040and the seed layer1042formed on the intermediate core assembly602is depicted inFIG.10Hfor reference. The adhesion layer1040may be formed on desired surfaces of the insulating layer618, such as surfaces corresponding with the major surfaces1005,1007of the intermediate core assembly602as well as sidewalls of the through-assembly vias613, to assist in promoting adhesion and blocking diffusion of the subsequently formed seed layer1042and electrical interconnections1044. Thus, in one embodiment, the adhesion layer1040acts as an adhesion layer; in another embodiment, the adhesion layer1040acts as a barrier layer. In both embodiments, however, the adhesion layer1040will be hereinafter described as an “adhesion layer.” In one embodiment, the adhesion layer1040is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable materials or combinations thereof. In one embodiment, the adhesion layer1040has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesion layer1040has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer1040is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. The seed layer1042may be formed on the adhesion layer1040or directly on the insulating layer618(e.g., without the formation of the adhesion layer1040). In some embodiments, the seed layer1042is formed on all surfaces of the insulating layer618while the adhesion layer1040is only formed on desired surfaces or desired portions of surfaces of the insulating layer618. For example, the adhesion layer1040may be formed on the major surfaces1005,1007and not on the sidewalls of the through-assembly vias613while the seed layer1042is formed on the major surfaces1005,1007as well as sidewalls of the through-assembly vias613. The seed layer1042is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. In one embodiment, the seed layer1042has a thickness between about 0.05 μm and about 0.5 μm, such as a thickness between about 0.1 μm and about 0.3 μm. For example, the seed layer1042has a thickness between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. In one embodiment, the seed layer1042has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer1040, the seed layer1042is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry processes, wet electroless plating processes, or the like. In one embodiment, a copper seed layer1042may be formed on a molybdenum adhesion layer1040on the intermediate core assembly602. The molybdenum adhesion and copper seed layer combination enables improved adhesion with the surfaces of the insulating layer618and reduces undercut of conductive interconnect lines during a subsequent seed layer etch process at operation970. At operations920and930, corresponding toFIGS.10B and10C, respectively, a spin-on/spray-on or dry resist film1050, such as a photoresist, is applied to both major surfaces1005,1007of the intermediate core assembly602and subsequently patterned. In one embodiment, the resist film1050is patterned via selective exposure to UV radiation. In one embodiment, an adhesion promoter (not shown) is applied to the intermediate core assembly602prior to formation of the resist film1050. The adhesion promoter improves adhesion of the resist film1050to the intermediate core assembly602by producing an interfacial bonding layer for the resist film1050and by removing any moisture from the surface of the intermediate core assembly602. In some embodiments, the adhesion promoter is formed of bis(trimethylsilyl)amine or hexamethyldisilizane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA). At operation940, the intermediate core assembly602is exposed to a resist film development process. As depicted inFIG.10D, development of the resist film1050results in exposure of the through-assembly vias613, which may now have an adhesion layer1040and/or a seed layer1042formed thereon. In one embodiment, the film development process is a wet process, such as a wet process that includes exposing the resist film1050to a solvent. In one embodiment, the film development process is a wet etch process utilizing an aqueous etch process. For example, the film development process is a wet etch process utilizing a buffered etch process selective for a desired material. Any suitable wet solvents or combination of wet etchants may be used for the resist film development process. At operations950and960, corresponding toFIGS.10E and10Frespectively, electrical interconnections1044are formed through the exposed through-assembly vias613and the resist film1050is thereafter removed. The interconnections1044are formed by any suitable methods, including electroplating and electroless plating. In one embodiment, the resist film1050is removed via a wet process. As depicted inFIGS.10E and10F, the electrical interconnections1044may completely fill the through-assembly vias613and protrude from the surfaces1005,1007of the intermediate core assembly602upon removal of the resist film1050. In some embodiments, the electrical interconnections1044may only line the sidewalls of the through-assembly vias613without completely filling the through-assembly vias613. In one embodiment, the electrical interconnections1044are formed of copper. In other embodiments, the electrical interconnections1044may be formed of any suitable conductive material including but not limited to aluminum, gold, nickel, silver, palladium, tin, or the like. At operation970andFIG.10G, the intermediate core assembly602having electrical interconnections1044formed therein is exposed to a seed layer etch process to remove the exposed adhesion layer1040and seed layer1042on external surfaces thereof (e.g., surfaces1005,1007). In some embodiments, the adhesion layer1040and/or seed layer1042formed between the electrical interconnections1044and the sidewalls of the through-assembly vias613may remain after the seed layer etch process. In one embodiment, the seed layer etch is a wet etch process including a rinse and drying of the intermediate core assembly602. In one embodiment, the seed layer etch process is a buffered etch process selective for a desired material such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etch process is an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process. Following the seed layer etch process at operation970, one or more semiconductor core assemblies may be singulated from the intermediate core assembly602and utilized as a fully-functional electronic mounting or package structure. For example, the one or more semiconductor core assemblies may be singulated and utilized as circuit board structures, chip carrier structures, integrated circuit packages, and the like. Alternatively, the intermediate core assembly602may have one or more redistribution layers1260(shown inFIGS.12J and12K) formed thereon to reroute external contact points of the electrical interconnections1044to desired locations on the surfaces of the final semiconductor core assemblies. FIG.11illustrates a flow diagram of a representative method1100of forming a redistribution layer1260on the intermediate core assembly602.FIGS.12A-12Kschematically illustrate cross-sectional views of the intermediate core assembly602at different stages of the method1100depicted inFIG.11. Thus,FIG.11andFIGS.12A-12Kare herein described together for clarity. The method1100is substantially similar to the methods500,700, and900described above. Generally, the method1100begins at operation1102andFIG.12A, wherein an insulating film1216is affixed to the intermediate core assembly602and is thereafter laminated. The insulating film1216is substantially similar to the insulating films616a,616b. In one embodiment, as depicted inFIG.12A, the insulating film1216includes an epoxy resin layer1218and one or more protective layers. For example, the insulating film1216may include a protective layer1222. Any suitable combination of layers and insulating materials is contemplated for the insulating film1216. In some embodiments, an optional carrier1224is coupled to the insulating film1216for added support. In some embodiments, a protective film (not shown) may be coupled to the insulating film1216. Generally, the epoxy resin layer1218has a thickness of less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the epoxy resin layer1218has a thickness of between about 10 μm and about 25 μm. In one embodiment, the epoxy resin layer1218and the PET protective layer1222have a combined thickness of less than about 120 μm, such as a thickness of less than about 90 μm. The insulating film1216, and specifically the epoxy resin layer1218, is affixed to a surface of the intermediate core assembly602having exposed electrical interconnections1044, such as the major surface1005. After placement of the insulating film1216, the intermediate core assembly602is exposed to a lamination process substantially similar to the lamination process described with regard to operations506,514, and730. The intermediate core assembly602is exposed to elevated temperatures to soften the epoxy resin layer1218of the insulating film1216, which subsequently bonds to the insulating layer618. Thus, the epoxy resin layer1218becomes integrated with the insulating layer618and forms an extension thereof, and will thus be described hereinafter as a singular insulating layer618. The integration of the epoxy resin layer1218and the insulating layer618further results in an enlarged insulating layer618enveloping the previously exposed electrical interconnections1044. At operation1104andFIG.12B, the protective layer1222and the carrier1224are removed from the intermediate core assembly602by mechanical means, and the intermediate core assembly602is exposed to a cure process to fully harden the newly expanded insulating layer618. In one embodiment, the cure process is substantially similar to the cure process described with reference to operations516and740. For example, the cure process is performed at a temperature between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes. The intermediate core assembly602is then selectively patterned by laser ablation at operation1106andFIG.12C. The laser ablation process at operation1106forms one or more redistribution vias1253in the newly expanded insulating layer618and exposes desired electrical interconnections1044for redistribution of contact points thereof. In one embodiment, the redistribution vias1253have a diameter substantially similar to or smaller than the diameter of the through-assembly vias613. For example, the redistribution vias1253have a diameter between about 5 μm and about 600 μm, such as a diameter of between about 10 μm and about 50 μm, such as between about 20 μm and about 30 μm. In one embodiment, the laser ablation process at operation1106is performed utilizing a CO2laser. In one embodiment, the laser ablation process at operation1106is performed utilizing a UV laser. In another embodiment, the laser ablation process at operation1106is performed utilizing a green laser. In one example, the laser source may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam at a wavelength of between about 100 nm and about 2000 nm, at a pulse duration between about 10E-4 ns and about 10E-2 ns, and with a pulse energy of between about 10 μJ and about 300 μJ. At operation1108andFIG.12D, an adhesion layer1240and/or a seed layer1242are optionally formed on one or more surfaces of the insulating layer618. In one embodiment, the adhesion layer1240and the seed layer1242are substantially similar to the adhesion layer1040and the seed layer1042, respectively. For example, the adhesion layer1240is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable materials or combinations thereof. In one embodiment, the adhesion layer1240has a thickness between about 10 nm and about 300 nm, such as a thickness between about 50 nm and about 150 nm. For example, the adhesion layer1240has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer1240may be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, or the like. The seed layer1242is formed from a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. In one embodiment, the seed layer1242has a thickness between about 0.05 μm and about 0.5 μm, such as between about 0.1 μm and about 0.3 μm. For example, the seed layer1242has a thickness between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. Similar to the adhesion layer1240, the seed layer1242may be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry processes, wet electroless plating processes, or the like. In one embodiment, a molybdenum adhesion layer1240and a copper seed layer1242are formed on the intermediate core assembly602to reduce the formation of undercut during a subsequent seed layer etch process at operation1122. At operations1110,1112, and1114, corresponding toFIGS.12E,12F, and12G, respectively, a spin-on/spray-on or dry resist film1250, such as a photoresist, is applied over the seeded surfaces of the intermediate core assembly602and subsequently patterned and developed. In one embodiment, an adhesion promoter (not shown) is applied to the intermediate core assembly602prior to placement of the resist film1250. The exposure and development of the resist film1250results in opening of the redistribution vias1253. Thus, patterning of the resist film1250may be performed by selectively exposing portions of the resist film1250to UV radiation, and subsequent development of the resist film1250by a wet process, such as a wet etch process. In one embodiment, the resist film development process is a wet etch process utilizing a buffered etch process selective for a desired material. In other embodiments, the resist film development process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the resist film development process. At operations1116and1118, corresponding toFIGS.12H and121, respectively, redistribution connections1244are formed through the exposed redistribution vias1253and the resist film1250is thereafter removed. In one embodiment, the resist film1250is removed via a wet process. As depicted inFIGS.12H and121, the redistribution connections1244fill the redistribution vias1253and protrude from the surfaces of the intermediate core assembly602upon removal of the resist film1250. In one embodiment, the redistribution connections1244are formed of copper. In other embodiments, the redistribution connections1244are formed of any suitable conductive material including but not limited to aluminum, gold, nickel, silver, palladium, tin, or the like. Any suitable methods may be utilized to form the redistribution connections1244, including electroplating and electroless deposition. At operation1120andFIG.12J, the intermediate core assembly602having the redistribution connections1244formed thereon is exposed to a seed layer etch process substantially similar to that of operation970. In one embodiment, the seed layer etch is a wet etch process including a rinse and drying of the intermediate core assembly602. In one embodiment, the seed layer etch process is a wet etch process utilizing a buffered etch process selective for a desired material of the seed layer1242. In other embodiments, the etch process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process. Upon completion of the seed layer etch process at operation1120, one or more additional redistribution layers1260may be formed on the intermediate core assembly602utilizing the sequences and processed described above. For example, one or more additional redistribution layers1260may be formed on the first redistribution layer1260and/or an opposing surface of the intermediate core assembly602, such as major surface1007. In one embodiment, the one or more additional redistribution layers1260may be formed of polymer-based dielectric materials, such as a flowable build-up materials, that are different from the material of the first redistribution layer1260and/or the insulating layer618. For example, in some embodiments, the insulating layer618may be formed of an epoxy filled with ceramic fibers, while the first and/or any additional redistribution layers1260are formed of polyimide, BCB, and/or PBO. Alternatively, at operation1122andFIG.12K, one or more completed semiconductor core assemblies1270may be singulated from the intermediate core assembly602after a desired number of redistribution layers1260is formed. The completed semiconductor core assemblies1270formed at operation1120may be utilized in any suitable package assembly, PCB assembly, PCB spacer assembly, chip carrier assembly, intermediate carrier assembly, and the like. In one exemplary embodiment depicted inFIG.13A, a single semiconductor core assembly1270is utilized as a carrier for a chip1360in a chip carrier assembly1300. The chip1360may be any suitable type of chip, including a memory chip, a microprocessor, a complex system-on-a-chip (SoC), or a standard chip. Suitable types of memory chips include DRAM chips or NAND flash chips. In some further examples, the chip1360is a digital chip, an analog chip, or a mixed chip. The chip1360is disposed adjacent to one of the major surfaces1005,1007of the semiconductor core assembly1270. In some embodiments, two or more chips1360may be disposed adjacent to a single major surface1005,1007. In another embodiment, one or additional devices and/or structures may be disposed adjacent to the chip1360, such as one or more components of a PCB or a package substrate. For example, one or more passives may be disposed adjacent to the chip1360, such as capacitors, resistors, inductors and the like. In another example, one or more connectors may be disposed adjacent to the chip1360. The chip1360includes one or more contacts1348formed on an active surface1352thereof. As depicted, the contacts1348are conductively coupled to one or more redistribution connections1244of the semiconductor core assembly1270by one of more solder bumps1346disposed between the active surface1352and the major surface1005. In some embodiments, the contacts1348may be conductively coupled to the one or more interconnections1044by the one or more solder bumps1346. In one embodiment, the contacts1348and/or the solder bumps1346are formed of a substantially similar material to that of the interconnections1044and the redistribution connections1244. For example, the contacts1348and the solder bumps1346may be formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. In one embodiment, the solder bumps1346include C4 solder bumps. In one embodiment, the solder bumps1346include C2 (Cu-pillar with a solder cap) solder bumps. Utilization of C2 solder bumps may enable smaller pitch lengths and improved thermal and/or electrical properties for the chip carrier assembly1300. The solder bumps1346may be formed by any suitable wafer bumping processes, including but not limited to electrochemical deposition (ECD) and electroplating. In another exemplary embodiment depicted inFIG.13B, a semiconductor core assembly1270is utilized in a PCB assembly1302. Accordingly, the semiconductor core assembly1270is configured to function as a PCB structure for supporting (e.g., carrying) a package assembly1310. The package assembly1310may be substantially similar in structure and material to the semiconductor core assembly1270, but includes an embedded die1326disposed within a cavity1320formed within the core structure402that is substantially surrounded by the insulating layer618. The embedded die1326may further include an active surface1328having one or more contacts1330formed thereon and coupled with interconnections1342and/or redistribution connections1344of the package assembly1310. Similar to the chip carrier assembly1300inFIG.13A, the contacts1330and/or interconnections1342and/or redistribution connections1344of the package assembly1310are conductively coupled to the one or more redistribution connections1244of the semiconductor core assembly1270by the one of more solder bumps1346disposed between the active surface1328and the major surface1005. In some embodiments, the contacts1330may be conductively coupled to the one or more interconnections1044by the one or more solder bumps1346. FIG.13Cdepicts yet another exemplary embodiment utilizing the semiconductor core assembly1270as a PCB spacer structure in a PCB assembly1304. As shown, the semiconductor core assembly1270is disposed between two PCB's1362a,1362band configured to position the first PCB1362arelative to the second PCB1362bsuch that a physical space remains between the first PCB1362aand the second PCB1362bwhile they are conductively connected. Accordingly, the PCB's1362a,1362binclude one or more electrically conductive pads1368formed on major surfaces1364a,1364bthereof, respectively. The one or more conductive pads1368are conductively coupled to the redistribution connections1244and/or interconnections1044of the semiconductor core assembly1270via the one or more solder bumps1346. Similar the contacts1330,1348, the conductive pads1368are formed of a substantially similar material to that of the solder bumps1346, interconnections1044, and the redistribution connections1244to enable electrical conductivity therethrough. For example, the conductive pads1368may be formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. The utilization of the semiconductor core assembly1270in the embodiments shown above provides multiple advantages over conventional package, PCB, PCB spacer, and chip carrier structures. Such benefits include a thin-form-factor and high chip or die-to-package volume ratio, which enables greater I/O scaling to meet the ever-increasing bandwidth and power efficiency demands of artificial intelligence (AI) and high performance computing (HPC). The utilization of a structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability of 3-dimensional integrated circuit (3D IC) architecture. Furthermore, the fabrication methods for through-assembly vias and via-in-via structures described herein provide high performance and flexibility for 3D integration with relatively low manufacturing costs as compared to conventional TSV technologies. By utilizing the methods described above, high aspect ratio features may be formed on glass and/or silicon core structures, thus enabling the economical formation of thinner and narrower circuit boards, chip carriers, integrated circuit packages, and the like. The semiconductor core assemblies fabricated utilizing the methods described above provide the benefits of not only high I/O density and improved bandwidth and power, but also greater reliability with low stress attributed to the reduced weight/inertia and assembly architecture allowing flexible solder ball distribution. Further merits of the methods described above include economical manufacturing with dual-sided metallization capability and high production yield. Additionally, the utilization of a silicon core reduces or eliminates mismatch of the coefficient of thermal expansion (CTE) between the core assembly and any chips connected thereto, enabling the smaller soldering pitches and increased device density. While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. | 76,074 |
11862547 | DETAILED DESCRIPTION Described herein are semiconductor devices with stacked structures having swapped vertical conductive pins and interconnects that may be used for differential crosstalk self-cancelation. The embodiments of the stacked structures described below may be implemented in one or more assemblies comprising of integrated circuit (IC) dies, sockets, substrates (e.g., a high-density interconnect (HDI) substrate, a low-density interconnect (LDI) substrates, interposers, etc.), and package substrates (e.g., a printed circuit board (PCB), a motherboard, an electronic package substrate such as a central processing unit (CPU) package substrate, etc.). According to these embodiments, the assemblies may be comprised of a substrate having a first interconnect and a second interconnect, and a socket having a first pin, a second pin, and a base layer, where the socket may be disposed over the substrate. In one embodiment, the first interconnect of the substrate has a first conductive pad and a second conductive pad, and the second interconnect of the substrate has a third conductive pad and a fourth conductive pad. In some embodiments, the first interconnect may also have a first via, a second via, a first conductive line, and a second conductive line, while the second interconnect has a third via, a fourth via, a third conductive line, and a fourth conductive line (e.g., as shown below with the components of the first and second interconnects103a-bofFIGS.1A-1B). For one embodiment, the base layer of the socket includes a first pad and a second pad. As shown in the embodiments below, the socket may have the first pin disposed directly on the first pad of the base layer, and the second pin disposed directly on the second pad of the base layer. In one embodiment, the first pad of the base layer of the socket may be disposed (or positioned) at least partially within a footprint of the third conductive pad of the second interconnect of the substrate; and the second pad of the base layer of the socket may be disposed at least partially within a footprint of the first conductive pad of the first interconnect of the substrate. In these embodiments, the first pin of the socket may be conductively coupled to the first interconnect of the substrate, and the second pin of the socket may be conductively coupled to the second interconnect of the substrate. Accordingly, as shown below inFIGS.1A-1B,2, and3A-3B, the first and second pins of the socket may be respectively stacked (or coupled) on the first and second interconnects of the substrate to implement the stacked structure of the assembly, where the stacked structure may be implemented (or designed/patterned) with a polarity swapped configuration. As described above, existing approaches to mitigate differential crosstalk in socket assemblies has led to increased technical challenges and costs that are associated with socket height reduction, complex pin maps, form-factor reduction, and increased number of total pins. Accordingly, in the embodiments described herein, the stacked structures have been implemented to achieve crosstalk self-cancelation (and/or substantially reduced crosstalk) (e.g., crosstalk may be substantially reduced by at least an average of 20 dB below a typical differential signal at a frequency of roughly 20 GHz), and overcome these existing technical challenges and costs. That is, in such embodiments, the stacked structure may be positioned in the assembly in a polarity swapped configuration to thereby effectively (i) reduce the crosstalk in the differential vertical pins and/or interconnects, and (ii) optimize the speed scaling in the peripheral component interconnect express (PCIe) channels, the high-speed serializer/deserializer (serdes) channels, and so on. As described herein, a “polarity swapped configuration” may refer to a polarity swapping scheme (or a swapped routing structure) comprised of a first interconnect, a second interconnect, a first pin may have a first polarity (e.g., a positive polarity), and a second pin may have a second polarity (e.g., a negative polarity), where the first and second pins are concentrically swapped with the respective first and second interconnects to eliminate (or substantially reduce/mitigate) signal crosstalk such as differential crosstalk. For example, the polarity swapped configuration may be implemented as a swapped structure in the assembly, where the first and second interconnects are part of the swapped structure that may be positioned and patterned directly into the substrate. In particular, in one example, the swapped structure may be patterned directly between a top conductive layer and an intermediate conductive layer in the substrate (e.g., the intermediate conductive layer may be positioned proximately below the top conductive layer), where the swapped structure may be comprised of (i) the second via, the first and second conductive lines, and the second conductive pad of the first interconnect, and (ii) the fourth via, the third and fourth conductive lines, and the fourth conductive pad of the second interconnect. Accordingly, the stacked structures of the assembly with the swapped structures of the interconnects may therefore provide improvements to the existing packaging solutions by (i) enabling differential crosstalk self-cancelation within the vertical structure boundaries of the stacked pins and interconnects using the polarity swapped configuration, (ii) avoiding an increased number of total pins and a socket height reduction, and (iii) implementing low-cost substrate design rules. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as microelectromechanical systems (MEMS) based electrical systems, gyroscopes, advanced driving assistance systems (ADAS), 5G communication systems, cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary. In some embodiments, the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices, including electronic devices with assemblies comprised of IC dies, sockets, HDI/LDI substrates, package substrates, swapped structures, and stacked structures, as described herein. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present embodiments, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. As used herein the terms “top,” “bottom,” “upper,” “lower,” “lowermost,” and “uppermost” when used in relationship to one or more elements are intended to convey a relative rather than absolute physical configuration. Thus, an element described as an “uppermost element” or a “top element” in a device may instead form the “lowermost element” or “bottom element” in the device when the device is inverted. Similarly, an element described as the “lowermost element” or “bottom element” in the device may instead form the “uppermost element” or “top element” in the device when the device is inverted. Referring now toFIG.1A, a cross-sectional illustration of an assembly100is shown, in accordance with an embodiment. Additionally, inFIG.1B, a plan illustration of the respective assembly100is shown, in accordance with an embodiment. For some embodiments, the assembly100may include a socket150disposed on and coupled to a substrate102. In particular, the socket150may have a plurality of pins132a-bthat are respectively disposed on a plurality of interconnects103a-bof the substrate102. As shown inFIG.1A, the assembly100may have a first stacked structure and a second stacked structure with a swapped170. For example, the stacked structures may include the first stacked structure comprised of pin132aand interconnect103a, and the second stacked structure comprised of pin132band interconnect103b. In these embodiments, the first/second stacked structure may be implemented as an overall vertical transmission line that is divided into two (or more) swapped pins/interconnects—instead of a conventional single pin/interconnect structure. Additionally, in these embodiments, the first/second stacked structures may be implemented as a differential pair of vertical transmission lines having a pin/interconnect polarity that can be swapped in between the pins and interconnects through one or more conductive routing structures (e.g., metal vias, pads, lines, etc.). For example, to implement the swapped polarity of the pins/interconnects, the pins132a-band interconnects103a-bmay be positioned to have a polarity swapped configuration in the respective socket150and substrate102. Accordingly, as shown inFIGS.1A-1B, the polarity swapped configuration may be implemented by having the pins132a-bof the socket102stacked on the respective interconnects103a-bof the substrate102, and by swapping the pins132a-bwith the respective interconnects103a-bat the swapped structure170(or a substantially concentric location between the pins132a-band the interconnects103a-b). In some embodiments, the socket150may be a CPU socket, a connecting device, or the like with one or more mechanical components that may provide mechanical and electrical connections between a CPU (or the like) and a PCB (or the like). For one embodiment, the socket150may be, but is not limited to, a pin grid array (PGA) socket, a land grid array (LGA) socket, and a ball grid array (BGA) socket. Additionally, in one embodiment, the socket150may include a housing body (or the like) having a top conductive layer (or surface) and a bottom conductive layer that is opposite from the top conductive layer. Accordingly, in these embodiments, the pins132a-bof the socket150may be disposed in the housing body in the polarity swapped configuration to enable the crosstalk cancellation, improve the signal integrity, and increase the speed scaling in PCIe and high-speed serdes devices for the assembly100. In some embodiments, the socket150may have a thickness (T1) of approximately 0.50 mm to 2 mm. In other embodiments, the socket150may have a thickness (T1) of approximately 0.50 mm to 15 mm. In one embodiment, the thickness (T1) of the socket150may be substantially similar or equal to the thickness (T2) of the substrate102. While, in another embodiment, the thickness (T1) of the socket150may be greater or less than the thickness (T2) of the substrate102. Additionally, as shown inFIGS.1A-1B, the socket150may have the pin132a(or a first pin), the pin132b(or a second pin), and a base layer108. In some embodiments, the base layer108may be a bottommost conductive layer (or the bottom conductive layer) of the socket150. The base layer108may be comprised of a plurality of pads130a-b(e.g., a first pad130aand a second pad130b) and a plurality of respective pad openings (e.g., as shown with the pad openings305ofFIGS.3A-3B), where the pad openings may surround (or house) the respective pads130a-b. Note that, in these embodiments, the socket150may have a plurality of signal, ground, and/or miscellaneous pins, but for illustrative simplicity, only the first and second pins132a-bof the stacked structures of the assembly100are shown. In some embodiments, the first and second pins132a-bmay be an interconnect, a transmission line, and/or the like. Additionally, in one embodiment, the first and second pins132a-bmay be implemented as a portion of the overall differential pair of transmission lines (e.g., the upper portions of the differential pair of transmission lines of the stacked structures). In one embodiment, the first pin132amay be a negative polarity pin, and the second pin132bmay be a positive polarity pin (or vice-versa), where the first and second pins132a-bmay extend in the housing body of the socket150from or near the top conductive layer to the base layer108. The base layer108with the first and second pads130a-bmay be positioned over/above the substrate102. Accordingly, as shown inFIGS.1A-1B, the first pin132amay be directly disposed on the first pad130a, and the second pin132bmay be directly disposed on the second pad130b. In particular, the first pad130a(and/or the first pin132a) of the socket150may be positioned at least partially within a footprint of a third conductive pad120bof the second interconnect103bof the substrate102, while the second pad130b(and/or the second pin132b) of the socket150may be positioned at least partially within a footprint of the first conductive pad120aof the first interconnect103aof the substrate102, according to some embodiments. In some embodiments, the substrate102may be, but is not limited to, an HDI substrate, a LDI substrate, a multi-layer interposer (e.g., a hybrid interposer comprised of silicon and/or glass (or the like)), and/or a package substrate. For example, the substrate102may have a multi-layer, high-density (or low-density) circuitry with fine line/space (l/s) (or an ultra-fine l/s) patterns that increase the functionality of the substrate102using less area, where the multi-layer circuitry may include a plurality of conductive layers with metal (e.g., copper) filled microvias that create vertical interconnect structures. The substrate102may be a silicon substrate having increased (or high) input/output (I/O) density and bandwidth for the communication with the socket150and any other microelectronic devices of the assembly100. In one embodiment, the substrate102may have a thickness (T2) of approximately 10 um or greater. In another embodiment, the substrate102may have a thickness (T2) of approximately 0.50 mm to 2.5 mm. In other embodiments, the substrate102may have a thickness (T2) of approximately 0.50 mm to 15 mm. Also, as described above, the thickness (T2) of the substrate102may be substantially similar or equal to the thickness (T1) of the socket150, according to some embodiments. For one embodiment, the substrate102may include a plurality of redistribution layers (RDLs) comprised of dielectric layers and conductive layers (e.g., metals such as copper (or the like), alloys, etc.). The conductive layers of the substrate102may be comprised of conductive pads123a-b,121a-b, and120a-b, conductive lines111a-band112a-b(or conductive traces/planes), and/or conductive vias110a-b(e.g., through silicon vias (TSVs), through glass vias (TGVs), or the like). Additionally, as described above, the first and second interconnects103a-bmay be implemented as a portion of the overall differential pair of transmission lines (e.g., the lower portions of the differential pair of transmission lines of the stacked structures). In one embodiment, the first interconnect103amay be a negative polarity interconnect, and the second interconnect103bmay be a positive polarity interconnect (or vice-versa). In some embodiments, the first interconnect103amay have the first conductive pad120aand a second conductive pad123a, and the second interconnect103bmay have the third conductive pad120band a fourth conductive pad123b. Accordingly, the first interconnect103amay be coupled to the first pin132aof the socket150by directly coupling the second conductive pad123aof the first interconnect103ato the first pad130aof the socket150. Likewise, the second interconnect103bmay be coupled to the second pin132bof the socket150by directly coupling the fourth conductive pad123bof the second interconnect103bto the second pad130bof the socket150. As shown inFIGS.1A-1B, the substrate102may be conductively coupled to the socket150with the swap structure170of the first and second interconnects103a-b. In one embodiment, the substrate102may have a body104comprised of one or more dielectric layers149a-band conductive routing layers139a-c, where the body104has a top surface104aand a bottom surface104bthat is opposite from the top surface104a. In some embodiment, the top surface104ahas a first conductive layer139aand a first dielectric layer149a, and the bottom surface104bhas a second conductive layer139band a second dielectric layer149b. In one embodiment, the first conductive layer139amay be comprised of, but is not limited to, the second and fourth conductive pads123a-b, the second and fourth conductive lines112a-b, and/or the top ends of the second and fourth vias122a-b. Likewise, in one embodiment, the second conductive layer139bmay be comprised of, but is not limited to, the first and third conductive pads120a-band/or the bottom ends of the first and third vias110a-b. In one embodiment, the first and second dielectric layers149a-bmay be a photosensitive dielectric layer, a solder resist layer, a solder mask, or the like. Accordingly, as described above, the first and second interconnects103a-bmay be positioned with the swapped structure170in the body104of the substrate102. Furthermore, as shown inFIGS.1A-1B, the second conductive pad123aof the first interconnects103amay be positioned at least partially within the respective footprint of the third conductive pad120bof the second interconnect103b, while the fourth conductive pad123bof the second interconnect103bmay be positioned at least partially within the respective footprint of the first conductive pad120aof the first interconnect103a. In addition, according to some embodiments, a third conductive layer339cmay be disposed between the first and second conductive layers139a-bin the body104of the substrate102. The third conductive layer139cmay be positioned directly below (or proximately below) the first conductive layer139a, where the third conductive layer139cmay be comprised of, but is not limited to, the first and third conductive lines111a-b, the intermediate conductive pads121a-b(and/or the top ends of the first and third vias110a-b), and the bottom ends (or pads) of the second and fourth vias122a-b. As such, the polarity swapped configuration of the first and second interconnects103a-bmay be implemented with the swapped structure170that is directly positioned and patterned between the first conductive layer139aand the third conductive layer139c, where the swapped structure170may be implemented with the second and fourth vias122a-b, the first and third conductive lines111a-b, the second and fourth conductive lines112a-b, and/or the second and fourth conductive pads123a-bof the respective first and second interconnects103a-b. Accordingly, to implement the polarity swamp inFIGS.1A-1B, a short dogbone routing scheme (or the like) may be implemented on the first conductive layer139a(or a top surface layer) of the substrate102to offset the second and fourth conductive pads123a-b(i.e., the respective negative and positive polarities of the top conductive pads). The second and fourth conductive pads123a-bmay be respectively coupled to the second via122aand the fourth via122bwith the second conductive line112aand the fourth conductive line112b. The second and fourth vias122a-bmay be routed from the first conductive layer139asubsequently downward to the third conductive layer139c(or an intermediate layer) at an offset routing location of the swapped structure170. Additionally, the second and fourth vias122a-bmay be respectively coupled to the first and third vias110a-bwith the first and third conductive lines111a-b, where the first and third vias110a-bmay be positioned at an original routing location of the swapped structure170that may be used for the polarity swapping scheme (i.e., by routing the positive link under/below the original positive pad, and the negative link under/below the original negative pad). Lastly, the first and third vias111a-bmay be respectively coupled down to the first and third conductive pads120a-bin the second conductive layer139b(or a bottom surface layer) (e.g., the respective negative and positive polarities of the bottom conductive pads). In an embodiment, the first and third vias111a-bmay have a thickness that is greater than a thickness of the second and fourth vias112a-b. Also, in one embodiment, the first conductive line111amay have a length (or a width) that is different or substantially equal to a length of the third conductive line111b. Likewise, in one embodiment, the second conductive line112amay have a length that is different or substantially equal to a length of the fourth conductive line112b. Lastly, for some embodiments, the first pad130aof the socket150may have a footprint that may be directly positioned over a footprint of the third via110band/or a footprint of the third conductive pad120bof the second interconnect103bof the substrate102. Likewise, for some embodiments, the second pad130bof the socket150may have a footprint that may be directly positioned over a footprint of the first via110aand/or a footprint of the first conductive pad120aof the first interconnect103aof the substrate102. In alternative embodiments, the first pad130aof the socket150may have a footprint that may be positioned at least partially within a footprint of the third via110band/or a footprint of the third conductive pad120bof the second interconnect103bof the substrate102, while the second pad130bof the socket150may have a footprint that may be positioned at least partially within a footprint of the first via110aand/or a footprint of the first conductive pad120aof the first interconnect103aof the substrate102. That is, in these other embodiments, a portion of the footprint(s) of the first/second pads130a-bof the socket150may overlap a portion of the footprint(s) of the first/third conductive pads120a-band/or a portion of the footprint(s) of the first/third vias110a-bof the substrate102. Note that the assembly100ofFIGS.1A-1Bmay include fewer or additional packaging components based on the desired packaging design. Referring now toFIG.2, a three-dimensional (3D) perspective illustration of an assembly200is shown, in accordance with an embodiment. In particular,FIG.2is a detailed 3D perspective illustration of a polarity swap configuration (or a swap configuration) of a stacked structure in the assembly200. For some embodiments, the assembly200may be substantially similar to the assembly100described above inFIGS.1A-1B. Likewise, the components of the assembly200may be substantially similar to the components of the assembly100described above inFIGS.1A-1B. Accordingly, the socket250, the substrate202, the pins232a-b, the interconnects203a-b, the conductive lines211a-band212a-b, the pads230a-b, the conductive pads223a-b,221a-b, and220a-b, and the vias210a-band222a-bmay be substantially similar to the socket150, the substrate102, the pins132a-b, the interconnects103a-b, the conductive lines111a-band112a-b, the pads130a-b, the conductive pads123a-b,121a-b, and120a-b, and the vias110a-band122a-bdescribed above inFIGS.1A-1B. Note that, inFIG.2, only the pins232a-band the interconnects203a-bare shown, while the housing bodies of the respective socket250and substrate202are omitted, for simplicity. According to some embodiments, the assembly200may dispose the socket250over the substrate202. The socket250may have a first pin232a, a second pin232b, and a base layer, where the base layer may further include a first pad230aand a second pad230b. In these embodiments, the first pin232amay be directly disposed on the first pad230a, and the second pin232bmay be directly disposed on the second pad230b. Furthermore, the substrate202may have a first interconnect203aand a second interconnect203b. The first interconnect203amay further include a first conductive pad220aand a second conductive pad223a, and the second interconnect203bmay further include a third conductive pad220band a fourth conductive pad223b. Accordingly, in these embodiments, the first pad230aof the socket250may be positioned at least partially within a footprint of the third conductive pad220bof the second interconnect203bof the substrate202, while the second pad230bof the socket250may be positioned at least partially within a footprint of the first conductive pad220aof the first interconnect203aof the substrate202. In these embodiments, the first pin232aof the socket250may be communicatively coupled to the first interconnect203aof the substrate202, and the second pin232bof the socket250may be communicatively coupled to the second interconnect203bof the substrate202. Furthermore, in some embodiments, the first interconnect203amay have a first via210a, a second via222a, a first conductive line211a, and a second conductive line212a, while the second interconnect203bmay have a third via210b, a fourth via222b, a third conductive line211b, and a fourth conductive line212b. The first via210amay conductively couple the first conductive pad220a(in/on a bottom conductive layer) to the first conductive line211aat the conductive pad221a(or the top end of the first via210a). The second via222amay conductively couple the first conductive line211a(in an intermediate conductive layer) to the second conductive line212a(in a top conductive layer). The second conductive line212amay conductively couple the second via222ato the second conductive pad223a, where the second conductive pad223aof the substrate202may be directly coupled to the first pad230aof the socket250. Respectively, the third via210bmay conductively couple the third conductive pad220b(in the bottom conductive layer) to the third conductive line211bat the conductive pad221b(or the top end of the third via210b). The fourth via222bmay conductively couple the third conductive line211b(in the intermediate conductive layer) to the fourth conductive line212b(in the top conductive layer). The fourth conductive line212bmay conductively couple the fourth via222bto the fourth conductive pad223b, where the fourth conductive pad223bof the substrate202may be directly coupled to the second pad230bof the socket250. Also note that, as shown inFIG.2, the conductive routing components of the first interconnect203amay have one or more size dimensions (e.g., widths, lengths, and/or thicknesses) that are substantially symmetical to one or more size dimensions of the conductive routing components of the second interconnect203b. That is, in some embodiments, the first via210amay have a thickness that is substantially equal to a thickness of the third via210b, while the second via222amay have a thickness that is substantially equal to a thickness of the fourth via222b. While, in an alternate embodiment, the first via210amay have a thickness that is different from a thickness of the third via210b, while the second via222amay have a thickness that different from a thickness of the fourth via222b. Likewise, in some embodiments, the first conductive line211amay have a length (or a width) that is substantially equal to a length of the third conductive line211b, while the second conductive line212amay have a length that is substantially equal to a length of the fourth conductive line212b. While, in an alternate embodiment, the first conductive line211amay have a length that is different from a length of the third conductive line211b, while the second conductive line212amay have a length that is different from a length of the fourth conductive line212b. Note that the assembly200may include fewer or additional packaging components based on the desired packaging design. Referring now toFIGS.3A-3B, a 3D perspective illustration and a respective plan illustration of an assembly300are shown, in accordance with some embodiments. For some embodiments, the assembly300may be substantially similar to the assembly100described above inFIGS.1A-1B, with the exception that the interconnects303and303a-bof the substrate302are coupled to the conductive pads352of the package substrate351with a plurality of solder balls333, that only the interconnects303a-bare in the polarity swapped configurations in the substrate302, and that the remaining interconnects303of the substrate302are not swapped and thus extend vertically from the bottom conductive layer304ato the top conductive layer304b—without the conductive routing structures used for the polarity swapped configurations. That is, in these embodiments, the assembly300may implement the stacked structures of pins323a-band interconnects303a-bin the polarity swapped configurations for only a desired number of differential pairs of stacked structures (e.g., for the most dominant aggressor-victim differential pairs to thereby ensure the largest benefit for the most dominant crosstalk aggressor pairs). In addition, the components of the assembly300may be substantially similar to the components of the assembly100described above inFIGS.1A-1B. Accordingly, the socket350, the substrate302, the pins332a-b, the interconnects303a-b, the conductive lines311a-band312a-b, the pads330a-b, the conductive pads323a-b,321a-b, and320a-b, and the vias310a-band322a-bmay be substantially similar to the socket150, the substrate102, the pins132a-b, the interconnects103a-b, the conductive lines111a-band112a-b, the pads130a-b, the conductive pads123a-b,121a-b, and120a-b, and the vias110a-band122a-bdescribed above inFIGS.1A-1B. Also, as described above, the assembly300may further include the pins332, the interconnects303, the vias310, and the conductive pads320and323. As shown inFIGS.3A-3B, the assembly300may have the socket350disposed over the substrate302, while the substrate302may be disposed over the package substrate351. The substrate302may conductively couple the socket350to the package substrate351. The substrate302may have a body304comprised of multiple dielectric layers349a-band conductive routing layers339a-c, where the body304has a top surface304aand a bottom surface304bthat is opposite from the top surface304a. In some embodiment, the top surface304ahas a first conductive layer339aand a first dielectric layer349a, and the bottom surface304bhas a second conductive layer339band a second dielectric layer349b. In one embodiment, the first conductive layer339amay be comprised of, but is not limited to, the conductive pads323(or the plurality of first conductive pads), the conductive pads323a-b(or the second and fourth conductive pads), the conductive lines312a-b(or the second and fourth conductive lines), and/or the top ends of the vias322a-b. Likewise, in one embodiment, the second conductive layer339bmay be comprised of, but is not limited to, the conductive pads320(or the plurality of second conductive pads) and the conductive pads320a-b(or the second and fourth conductive pads). In one embodiment, the first and second dielectric layers349a-bmay be a photosensitive dielectric layer, a solder resist layer, a solder mask, or the like. The substrate302may have the interconnects303disposed in the body304, where the interconnects303may vertically extend from the top surface304ato the bottom surface304band conductively couple the conductive pads323to the conductive pads320. In addition, the substrate302may have the interconnects303a-b(or the first and second interconnects) disposed in the body304, where one of the pairs of the interconnects303a-bmay be positioned adjacent to each other and positioned between the interconnects303. Also, the pairs of interconnects303a-bmay be positioned in the body304in the polarity swapped configurations described herein. Furthermore, as shown inFIGS.3A-3B, the conductive pads323aof the first interconnects303amay be positioned at least partially within the respective footprints of the conductive pads320bof the second interconnects303b, while the conductive pads323bof the second interconnects303bmay be positioned at least partially within the respective footprints of the conductive pads320aof the first interconnects303a. In addition, the substrate302may have a third conductive layer339cdisposed between the first and second conductive layers339a-bin the body304. The third conductive layer339cmay be positioned directly below (or proximately below) the first conductive layer339a, where the third conductive layer339cmay be comprised of, but is not limited to, the conductive lines311a-b, the top ends (or pads) of the vias310a-b, and the bottom ends of the vias322a-b. Additionally, as shown in these embodiments, the polarity swapped configurations of the interconnects303a-bmay be implemented as a swapped structure370(or a swapped routing structure) that is directly positioned and patterned between the first conductive layer339aand the third conductive layer339c. In these embodiments, the swapped structure370may be implemented with the via322a, the conductive lines311aand312a, and the second conductive pads323aof the first interconnects303a, and with the via322b, the conductive lines311band312b, and the conductive pads323bof the second interconnects303b. Furthermore, as shown inFIG.3A, the vias310aof the interconnects303avertically extend from the second conductive layer339bto the third conductive layer339c, where the vias310aconductively couple the conductive pads320ato the conductive lines311ain the third conductive layer339c. The vias322aof the interconnects303avertically extend from the third conductive layer339cto the first conductive layer339a, where the vias322aconductively couple the conductive lines311ato the conductive lines312ain the first conductive layer339a. As such, the conductive lines312aconductively couple the vias322ato the conductive pads323aof the interconnects303aon the top surface304aof the body304of the substrate302. Respectively, as shown inFIG.3A, the vias310bof the interconnects303bvertically extend from the second conductive layer339bto the third conductive layer339c, where the vias310bconductively couple the conductive pads320bto the conductive lines311bin the third conductive layer339c. The vias322bof the interconnects303bvertically extend from the third conductive layer339cto the first conductive layer339a, where the vias322bconductively couple the conductive lines311bto the conductive lines312bin the first conductive layer339a. As such, the conductive lines312bconductively couple the vias322bto the conductive pads323bof the interconnects303bon the top surface304bof the body304of the substrate302. In addition, the socket350may have the base layer308disposed over the top conductive layer304aof the substrate302, while the substrate302may have the bottom conductive layer304bdisposed over a top conductive layer316of the package substrate351. According to these embodiments, the base layer308may have a plurality of openings305surrounding the respective pads330and330a-bwith gaps309in between; while the top and bottom conductive layers304a-bmay have a plurality of via openings306-307surrounding the respective pads323and323a-band/or the respective interconnects303and303a-b. In one embodiment, the top and bottom ends of the interconnects303and303a-bmay extend through the respective via openings306-307of the substrate302to thereby couple the socket350to the package substrate351. While, in another embodiment, the top and bottom ends of the interconnects303and303a-bmay be substantially coplanar to the respective top and bottom surfaces304a-bof the substrate302, where the respective conductive pads323and323a-band320and320a-bmay be coupled to the respective top and bottom ends of the interconnects303and303a-b, and may be positioned over the respective openings306-307of the substrate302. Note that, even if via openings306-307are shown inFIGS.3A-3B, such via openings306-307may be shown for illustrative purposes as the respective pads323and323a-band vias310and310a-bmay occupy such openings. In some embodiments, the bottom ends of the interconnects303and303a-bmay be coupled to the respective conductive pads320and320a-bthat are positioned directly below the via openings307of the bottom conductive layer304bof the substrate302. These conductive pads320and320a-bof the substrate302may thus be coupled to the conductive pads352of the package substrate351with the solder balls333. Likewise, in another example, the top ends of the interconnects303and303a-bmay be coupled to the respective conductive pads323and323a-bthat are positioned directly above the via openings306of the top conductive layer340aof the substrate302. These conductive pads323and323a-bof the substrate302may thus be directly coupled to the respective pads330and330a-bof the socket350. In addition, the pins332, the interconnects303, the vias310, and the conductive pads320and323may be similar to the pins332a-b, the interconnects303a-b, the vias310a-b, and the conductive pads320a-band323a-b. Also, as shown inFIG.3A, the vias310may have a thickness that is substantially equal to a total thickness of one of the vias310a-band one of the vias322a-b(i.e., the total thickness may be the combined sum of the thickness of the via310aand the thickness of the via322a). Furthermore, as shown inFIG.3B, the pins332a-band interconnects303a-bmay be positioned in between and separated by the pins332and interconnects303, where, for example, the vias322a-bmay be positioned vertically in line with (and/or adjacent to) some of the interconnects303. Note that the assembly300ofFIGS.3A-3Bmay include fewer or additional packaging components based on the desired packaging design. Referring now toFIG.4, a plan illustration of a pin map of an assembly400is shown, in accordance with an embodiment. The pin map of the assembly400may include a plurality of interconnects403a-dand404a-b(or a plurality of pins). The assembly400may be substantially similar to the assembly100described above inFIGS.1A-1B. Likewise, the components of the assembly400may be substantially similar to the assembly400described above inFIGS.1A-1B. As such, in some embodiments, the interconnects403a-dand404a-bof the pin map may be used to pattern (or position/map) the respective interconnects of a substrate (e.g., the substrate102ofFIGS.1A-1B) and/or the respective pins of a socket (e.g., the socket150ofFIGS.1A-1B), where the interconnects403a-dand404a-bmay be substantially similar to the interconnects103a-band/or the pins123a-bdescribed above inFIGS.1A-1B. In some embodiments, the interconnects403a-band404a-bmay be a plurality of signal interconnects (i.e., the signal interconnect/pin groups shown with “(1,2)—(15,16)”), the interconnects403cmay be a plurality of ground interconnects (i.e., the ground interconnects shown with “G”), and the interconnects403dmay be a plurality of miscellaneous interconnects and/or interconnects (or pins) that may be implemented for any desired purpose (i.e., the miscellaneous interconnects shown with “T”). For some embodiments, the interconnects403a-band/or404a-bmay be distinctly positioned in a polarity swapped configuration in the assembly400. Moreover, a first signal interconnect group of interconnects403a-band404a-b(as shown with “(1,2)-(7,8)”) may be separated from a second signal interconnect group of interconnects403a-band404a-b(as shown with “(9,10)-(15,16)”) by the interconnects403c. As shown inFIG.4, within one signal interconnect group, the polarity swap configuration may be casted either on the interconnects403a-b(as shown with “(1,2) and (5,6)”) or the interconnects404a-b(as shown with “(3,4) and (7,8)”), which may be the same case for the other signal interconnect groups, according to one embodiment. Also note, as described above, the polarity swap configuration may be casted on the most dominant aggressor-victim pairs, where, for example, only the interconnects403a-bmay have to be swapped as the other interconnects404a-bmay not have to be swapped, and where the interconnects403a-b(or interconnects404a-b) may thus be selected to implement the largest crosstalk cancellation benefit for the most dominant crosstalk aggressors in the assembly. Note that the assembly400may include fewer or additional packaging components based on the desired packaging design. Referring now toFIG.5, a cross-sectional illustration of a semiconductor packaged assembly500(or an electronic packaged assembly) is shown, in accordance with an embodiment. For some embodiments, the semiconductor packaged assembly500may include a die514, a first substrate513, a first package substrate540, a socket550, a second substrate502, and a second package substrate551, according to one embodiment. As shown inFIG.5, in one embodiment, the semiconductor packaged assembly500may include the die514disposed on the first substrate513(or an interposer), and the stack of die514and first substrate513respectively disposed on the first package substrate540. In addition, for some embodiments, the semiconductor packaged assembly500may include the first package substrate540disposed on the socket550, and the stack of first package substrate540and socket550respectively disposed on the second substrate502. The socket550may couple the first package substrate540(e.g., a CPU package substrate) to the second substrate502(e.g., an HDI substrate, a LDI substrate, a multi-layer interposer with a low-profile, etc.) with a plurality of solder balls534and a plurality of pins532and532a-b. For example, the socket550may have a top conductive layer538with a plurality of conductive pads560, and a base layer508with a plurality of conductive pads530and530a-b. As such, the first package substrate540may be coupled to the conductive pads560on the top conductive layer538of the socket550; the pins532and532a-bmay be respectively coupled to the conductive pads530and530a-bon the base layer508of the socket550; and the respective pins532and532a-band conductive pads530and530a-bmay be coupled to a plurality of conductive pads523and523a-bof a plurality of interconnects503and503a-bof the second substrate502. Furthermore, in an embodiment, the semiconductor packaged assembly500may include the stack of socket550and second substrate502disposed on the second package substrate551. The second substrate502may couple the socket550to the second package substrate551(e.g., a motherboard) with a plurality of solder balls533and the interconnects503and503a-b. In these embodiments, the socket550and the second substrate502of the semiconductor packaged assembly500may be substantially similar to the socket150and the substrate102of the assembly100described above inFIGS.1A-1B. Likewise, the components of the socket550and the second substrate502may be substantially similar to the components of the sockets150and350and the substrates102and302described above inFIGS.1A-1BandFIGS.3A-3B. As such, the pins532and532a-b, the pads530and530a-b, the interconnects503and503a-b, the conductive lines511a-band512a-b, the conductive pads520and520a-b,521a-b, and523a-b, the vias510a-band522a-b, the surfaces504a-bof the body504, the conductive layers539a-c, and the dielectric layer549a-bmay be substantially similar to the pins332and332a-b, the pads330and330a-b, the interconnects303and303a-b, the conductive lines311a-band312a-b, the conductive pads320and320a-b,321a-b, and323a-b, the vias310a-band322a-b, the surfaces304a-bof the body304, the conductive layers339a-c, and the dielectric layer349a-bdescribed above inFIGS.3A-3B. For example, as described herein, the pins532a-bof the socket550may be disposed on the respective interconnects503a-bof the second substrate502, and the stacked structures of pins532a-band503a-bmay be positioned with the swapped structures570to implement the polarity swap configurations of the semiconductor packaged assembly500. Note that, in one embodiment, the stacked structures of pins/interconnects in the polarity swap configuration, as described herein, may be implemented in the other microelectronic devices of the semiconductor packaged assembly500based on the desired packaging design (e.g., the die514, the first substrate513, and the first/second package substrates540and551). Also note that the semiconductor packaged assembly500is not limited to the illustrated semiconductor packaged system, and thus may be designed/formed with fewer, alternate, or additional packaging components and/or with different interconnecting structures. According to one embodiment, the semiconductor packaged assembly500is merely one example of an embodiment of a semiconductor packaged system. For one embodiment, the semiconductor packaged assembly500may include a BGA package, a LGA package, and/or a PGA package. For one embodiment, the die514is coupled to the first substrate513(e.g., an interposer) via one or more solder balls518(or bumps/joints) formed from respective microbumps, and the first substrate513is coupled to the first substrate540via one or more solder balls516formed from respective microbumps. As described above, a solder ball formed by soldering of a microbump according to an embodiment may itself be referred to as a “bump” and/or a “microbump.” Additionally, one or more of the die514, the first substrate513, and the first/second package substrates540and551may be coupled using an anisotropic conductive film (ACF) or the like. For one embodiment, the first substrate512may be, but is not limited to, a silicon interposer and/or a die with through silicon vias (TSVs). For an alternate embodiment, the semiconductor packaged assembly500may omit the first interposer/substrate513. The first package substrate540and/or the second package substrate551may include a variety of electronic structures formed thereon or therein. In certain embodiments, the first and/or second package substrates540and551may be an organic substrate made up of one or more layers of polymer base materials or ceramic base materials, with conducting regions for transmitting signals. For some embodiments, the first/second package substrates540and551may include, but is not limited to, a package, a substrate, a PCB, a CPU package substrate, and a motherboard. In one embodiment, the first package substrate540is a CPU package substrate (or an electronic package substrate) and/or a PCB, while the second package substrate551is a motherboard. For one embodiment, the first/second package substrates540and551are made of an FR-4 glass epoxy base with thin copper foil laminated on both sides. For certain embodiments, a multilayer first/second package substrates540and551can be used, with pre-preg and copper foil used to make additional layers. For example, the multilayer first/second package substrates540and551may include one or more dielectric layers, where the dielectric layers may be a photosensitive dielectric layer. For one embodiment, the first/second package substrates540and551may also include one or more conductive layers, which may further include copper (or metallic) traces, lines, pads, vias, holes, and/or planes. For one embodiment, the die514may be comprised, but are not limited to, a semiconductor die, an electronic device (e.g., a wireless device), an IC, a CPU, a graphic processing unit (GPU), a microprocessor, a platform controller hub (PCH), a memory (e.g., a high bandwidth memory (HBM)), and/or a field-programmable gate array (FPGA). Additionally, in other embodiments, the die514, the first substrate513, and/or the second substrate502may be comprised of one or more materials, including glass, crystal, diamond, low thermal conductive materials, high thermal conductive materials (e.g., gallium nitride (GaN) or the like), silicon, glass-based materials, and/or silicon-based materials (e.g., silicon carbide (SiC) or the like). Also, in other embodiments, the die514may be a plurality of chiplet dies. The die514, the first substrate513, and/or the second substrate502may be formed from a material such as silicon and have circuitry thereon that is to be coupled to the other devices, such as the socket550and the first/second package substrates540and551. Although some embodiments are not limited in this regard, the second substrate502may in turn be coupled to another body, for example, the second package substrate551such as a computer motherboard. One or more connections between one or more of the die514, the first/second substrates513and502, the socket550, and the first/second package substrates540and551—e.g., including some or all of bumps516,518, and533-534—may include one or more interconnect structures and underfill layers526and528. In some embodiments, these interconnect structures (or connections) may variously comprise an alloy of nickel, palladium, and tin (and, in some embodiments, copper). Connections between one or more of the die514, the first/second substrates513and502, the socket550, and the first/second package substrates540and551may be made using any suitable structure, such as the illustrative bumps516,518, and533-534shown. Although some embodiments are not limited in this regard, the semiconductor packaged assembly500may include gap control structures580—e.g., positioned between the first substrate513and the first package substrate540. Such gap control structures580may mitigate a change in the height of the gap between the first substrate and the first package substrate513and540. Note that the semiconductor packaged assembly500includes the underfill material528between the first substrate513and the die514, and the underflow material526between the first package substrate540and the first substrate513. Also note that the underfill material may be disposed between the second substrate502and the second package substrate551if desired. For one embodiment, the underfill materials (or layers)526and528may be one or more polymers that are injected between the layers. For other embodiments, the underfill materials may be MUF. Note that the semiconductor packaged assembly500may include fewer or additional packaging components based on the desired packaging design. FIG.6is an illustration of a schematic block diagram illustrating a computer system600that utilizes a device package610(or a semiconductor packaged assembly) having a stacked structure comprised of pins and interconnects that are respectively positioned in a polarity swapped configuration, according to one embodiment.FIG.6illustrates an example of computing device600. Computing device600houses a motherboard602. Motherboard602may include a number of components, including but not limited to processor604, device package610(or semiconductor package), and at least one communication chip606. Processor604is physically and electrically coupled to motherboard602. For some embodiments, at least one communication chip606is also physically and electrically coupled to motherboard602. For other embodiments, at least one communication chip606is part of processor604. Depending on its applications, computing device600may include other components that may or may not be physically and electrically coupled to motherboard602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). At least one communication chip606enables wireless communications for the transfer of data to and from computing device600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. At least one communication chip606may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.112 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device600may include a plurality of communication chips606. For instance, a first communication chip606may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip606may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. Processor604of computing device600includes an integrated circuit die packaged within processor604. Device package610may be a semiconductor packaged assembly that may include, but is not limited to, dies, package substrates, sockets, and/or substrates (e.g., an HDI substrate, a LDI substrate, and/or an interposer). In one embodiment, device package610may include an assembly that is substantially similar to the assembly100ofFIGS.1A-1Bdescribed herein. Device package610may include an assembly having a socket and a substrate, where one or more stacked structures comprised of pins and interconnects are respectively positioned in a polarity swapped configuration in the respective socket and substrate as described herein (e.g., as illustrated and described above with the assemblies ofFIGS.1A-1B,2,3A-3B and4-5)—or any other components from the figures described herein. Note that device package610may be a single component/device, a subset of components, and/or an entire system, as the materials, features, and components may be limited to device package610and/or any other component of the computing device600that may need the assembly with the stacked and swapped structures as described herein (e.g., the motherboard602, the processor604, and/or any other component of the computing device600that may need the embodiments of the assemblies described herein). For certain embodiments, the integrated circuit die may be packaged with one or more devices on a package substrate that includes a thermally stable RFIC and antenna for use with wireless communications and the device package, as described herein, to reduce the z-height of the computing device. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. At least one communication chip606also includes an integrated circuit die packaged within the communication chip606. For some embodiments, the integrated circuit die of the communication chip606may be packaged with one or more devices on a package substrate that includes one or more device packages, as described herein. In the foregoing specification, embodiments have been described with reference to specific exemplary embodiments thereof. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications. The following examples pertain to further embodiments: Example 1: an assembly, comprising: a substrate having a first interconnect and a second interconnect, wherein the first interconnect has a first conductive pad and a second conductive pad, and wherein the second interconnect has a third conductive pad and a fourth conductive pad; and a socket over the substrate, wherein the socket has a first pin, a second pin, and a base layer, wherein the base layer includes a first pad and a second pad, wherein the first pin is vertically over the first interconnect, wherein the second pin is vertically over the second interconnect, wherein the first pad is directly coupled to the first pin and the fourth conductive pad of the second interconnect, and wherein the second pad is directly coupled to the second pin and the second conductive pad of the first interconnect. Example 2: the assembly of Example 1, wherein the first pad of the socket is at least partially within a footprint of the third conductive pad of the second interconnect of the substrate, and wherein the second pad of the socket is at least partially within a footprint of the first conductive pad of the first interconnect of the substrate. Example 3: the assembly of Examples 1-2, wherein the first pin is on the first pad, wherein the second pin is on the second pad, wherein the first pin of the socket is conductively coupled to the first interconnect of the substrate, and wherein the second pin of the socket is conductively coupled to the second interconnect of the substrate. Example 4: the assembly of Examples 1-3, wherein the substrate is comprised of a high-density interconnect substrate, a low-density interconnect substrate, or an interposer. Example 5: the assembly of Example 1-4, wherein the first interconnect has a first via, a second via, a first conductive line, and a second conductive line, and wherein the second interconnect has a third via, a fourth via, a third conductive line, and a fourth conductive line. Example 6: the assembly of Example 1-5, wherein the first via conductively couples the first conductive pad to the first conductive line, wherein the second via conductively couples the first conductive line to the second conductive line, and wherein the second conductive line conductively couples the second via to the second conductive pad. Example 7: the assembly of Examples 1-6, wherein the third via conductively couples the third conductive pad to the third conductive line, wherein the fourth via conductively couples the third conductive line to the fourth conductive line, and wherein the fourth conductive line conductively couples the fourth via to the fourth conductive pad. Example 8: the assembly of Examples 1-7, wherein the first via of the first interconnect has a thickness that is substantially equal to a thickness of the third via of the second interconnect. Example 9: the assembly of Examples 1-8, wherein the second via of the first interconnect has a thickness that is substantially equal to a thickness of the fourth via of the second interconnect. Example 10: a substrate, comprising: a body having a top surface and a bottom surface that is opposite from the top surface, wherein the top surface has a first conductive layer and a first dielectric layer, and wherein the bottom surface has a second conductive layer and a second dielectric layer; a plurality of interconnects in the body, wherein the plurality of interconnects have a plurality of first conductive pads on the top surface of the body, and a plurality of second conductive pads on the bottom surface of the body, wherein the plurality of interconnects vertically extend from the plurality of first conductive pads to the plurality of second conductive pads, and wherein the plurality of interconnects conductively couple the plurality of first conductive pads to the plurality of second conductive pads; and a first interconnect and a second interconnect in the body, wherein the first interconnect has a first conductive pad on the bottom surface of the body, and a second conductive pad on the top surface of the body, wherein the second interconnect has a third conductive pad on the bottom surface of the body, and a fourth conductive pad on the top surface of the body, wherein the first interconnect is directly adjacent to the second interconnect, wherein the first and second interconnects are in between the plurality of interconnects, wherein the first and second interconnects are part of a swapped structure in the body, wherein the second conductive pad of the first interconnect is at least partially within a footprint of the third conductive pad of the second interconnect, and wherein the fourth conductive pad of the second interconnect is at least partially within a footprint of the first conductive pad of the first interconnect. Example 11: the substrate of Example 10, further comprising a third conductive layer in the body, wherein the third conductive layer is between the first and second conductive layers, wherein the third conductive layer is proximately below the first conductive layer, wherein the first interconnect has a first via, a second via, a first conductive line, and a second conductive line, wherein the second interconnect has a third via, a fourth via, a third conductive line, and a fourth conductive line, wherein the swapped structure is directly between the first conductive layer and the third conductive layer, and wherein the swapped structure is comprised of the second via, the first and second conductive lines, and the second conductive pad of the first interconnect, and comprised of the fourth via, the third and fourth conductive lines, and the fourth conductive pad of the second interconnect. Example 12: the substrate of Examples 10-11, wherein the first conductive pad is below the second dielectric layer, wherein the first via vertically extends from the first conductive pad to the third conductive layer, wherein the first via conductively couples the first conductive pad to the first conductive line in the third conductive layer, wherein the second via vertically extends from the third conductive layer to the first conductive layer, wherein the second via conductively couples the first conductive line to the second conductive line in the first conductive layer, wherein the second conductive line conductively couples the second via to the second conductive pad, wherein the second conductive pad is on the second conductive line and the first dielectric layer, and wherein the first dielectric layer is over the second conductive line of the first conductive layer. Example 13: the substrate of Examples 10-12, wherein the third conductive pad is below the second dielectric layer, wherein the third via vertically extends from the third conductive pad to the third conductive layer, wherein the third via conductively couples the third conductive pad to the third conductive line in the third conductive layer, wherein the fourth via vertically extends from the third conductive layer to the first conductive layer, wherein the fourth via conductively couples the third conductive line to the fourth conductive line in the first conductive layer, wherein the fourth conductive line conductively couples the fourth via to the fourth conductive pad, wherein the fourth conductive pad is on the fourth conductive line and the second dielectric layer, and wherein the first dielectric layer is over the second conductive line of the first conductive layer. Example 14: the substrate of Example 10-13, further comprising a socket over the top surface of the body, wherein the socket has a first pin, a second pin, and a base layer, wherein the base layer includes a first pad and a second pad, wherein the base layer is directly above and parallel to the first conductive layer, wherein the first pin is vertically over the first interconnect, wherein the second pin is vertically over the second interconnect, wherein the first pad is directly coupled to the first pin and the fourth conductive pad of the second interconnect, and wherein the second pad is directly coupled to the second pin and the second conductive pad of the first interconnect. Example 15: the substrate of Examples 10-14, wherein the first pin is on the first pad, wherein the second pin is on the second pad, wherein the first pin of the socket is conductively coupled to the first interconnect, and wherein the second pin of the socket is conductively coupled to the second interconnect. Example 16: the substrate of Examples 10-15, wherein the first pad of the socket is at least partially within the footprint of the third conductive pad of the second interconnect, and wherein the second pad of the socket is at least partially within the footprint of the first conductive pad of the first interconnect. Example 17: the substrate of Examples 10-16, wherein the first via of the first interconnect has a thickness that is substantially equal to a thickness of the third via of the second interconnect. Example 18: the substrate of Examples 10-17, wherein the second via of the first interconnect has a thickness that is substantially equal to a thickness of the fourth via of the second interconnect. Example 19: an electronic packaged assembly, comprising: a substrate on a first package substrate, wherein the substrate has a first interconnect and a second interconnect, wherein the first interconnect has a first conductive pad and a second conductive pad, and wherein the second interconnect has a third conductive pad and a fourth conductive pad; a socket over the substrate, wherein the substrate conductively couples the socket to the first package substrate, wherein the socket has a first pin, a second pin, and a base layer, wherein the base layer includes a first pad and a second pad, wherein the first pin is vertically over the first interconnect, wherein the second pin is vertically over the second interconnect, wherein the first pad is directly coupled to the first pin and the fourth conductive pad of the second interconnect, and wherein the second pad is directly coupled to the second pin and the second conductive pad of the first interconnect; a second package substrate over the socket, wherein the socket conductively couples the second package substrate to the substrate; and a die over the second package substrate. Example 20: the electronic packaged assembly of Example 19, wherein the first pad of the socket is at least partially within a footprint of the third conductive pad of the second interconnect of the substrate, wherein the second pad of the socket is at least partially within a footprint of the first conductive pad of the first interconnect of the substrate, wherein the first pin is on the first pad, wherein the second pin is on the second pad, wherein the first pin of the socket is conductively coupled to the first interconnect of the substrate, and wherein the second pin of the socket is conductively coupled to the second interconnect of the substrate. Example 21: the electronic packaged assembly of Examples 19-20, wherein the substrate is comprised of a high-density interconnect substrate, a low-density interconnect substrate, or an interposer, wherein the first package substrate is a board, and wherein the second package substrate is an electronic package substrate. Example 22: the electronic packaged assembly of Examples 19-21, wherein the first interconnect has a first via, a second via, a first conductive line, and a second conductive line, and wherein the second interconnect has a third via, a fourth via, a third conductive line, and a fourth conductive line. Example 23: the electronic packaged assembly of Examples 19-22, wherein the first via conductively couples the first conductive pad to the first conductive line, wherein the second via conductively couples the first conductive line to the second conductive line, and wherein the second conductive line conductively couples the second via to the second conductive pad. Example 24: the electronic packaged assembly of Examples 19-23, wherein the third via conductively couples the third conductive pad to the third conductive line, wherein the fourth via conductively couples the third conductive line to the fourth conductive line, and wherein the fourth conductive line conductively couples the fourth via to the fourth conductive pad. Example 25: the electronic packaged assembly of Examples 19-24, wherein the first via of the first interconnect has a thickness that is substantially equal to a thickness of the third via of the second interconnect, and wherein the second via of the first interconnect has a thickness that is substantially equal to a thickness of the fourth via of the second interconnect. In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. | 70,277 |
11862548 | DETAILED DESCRIPTION FIG.1is a cross-sectional view of a package substrate film10, according to an embodiment. The package substrate film10according to an embodiment may include a film constituting a chip-on-film (COF) package. In an implementation, the package substrate film10may include a film configured to mount or accommodate a semiconductor chip20. Referring toFIG.1, the package substrate film10according to an embodiment may include a film substrate110, a redistribution pattern120, an input pad130, an output pad140, a chip bonding pad150, a passivation layer160, a test pattern220, a test pad230, or the like. The film substrate110of the package substrate film10may include a film for mounting the semiconductor chip20. In an implementation, the film substrate110may include an insulating material. In an implementation, the film substrate110may include a material of polyimide or epoxy resin. In an implementation, the film substrate110may include a flexible film. In an implementation, the film substrate110may include an upper surface110aand a lower surface110b. The upper surface110aof the film substrate110may be one surface of the film substrate110, on which the semiconductor chip20is mounted or mountable and the test pad230is arranged. In an implementation, the lower surface110bof the film substrate110may be one surface of the film substrate110opposite to the upper surface110a. In an implementation, the film substrate110may include a chip section CS, an input section IS, an output section OS, and a test section TS. The chip section CS may be one section of the film substrate110on which the semiconductor chip20is to be mounted. In an implementation, the chip section CS may be on or at the center portion of the film substrate110. The input section IS may be on or at one side of the chip section CS, and may be a section of the film substrate110for signal input. In an implementation, the input section IS of the film substrate110may be connected to a printed circuit board (PCB), and may be one section of the film substrate110that receives a signal from the PCB. The output section OS may be on or at the other side of the chip section CS, and may be a section of the film substrate110for signal input. In an implementation, the output section OS of the film substrate110may be connected to a display panel, and may be a section of the film substrate110that transmits a signal to the display panel. The test section TS may be on or at an (e.g., outer) edge portion of the film substrate110. In an implementation, the test section TS may be outside the output section OS. In an implementation, the test section TS may be a section of the film substrate110for testing a signal flow of the package substrate film10. In an implementation, the test section TS may be a section of the film substrate110that is removed during the operation of individualization of the film substrate110. The redistribution pattern120of the package substrate film10may extend on the film substrate110, and may include a pattern of a conductive material that electrically connects the semiconductor chip20, the input pad130, the output pad140, and the chip bonding pad150to each other. In an implementation, the material of the redistribution pattern120may include a metal, e.g., copper (Cu), nickel (Ni), aluminum (Al), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B. In an implementation, the redistribution pattern120may include an upper redistribution line pattern123, a lower redistribution line pattern125, and a redistribution via pattern127. In an implementation, the upper redistribution line pattern123may include a pattern extending in a horizontal direction (e.g., X direction) on the upper surface110aof the film substrate110. In an implementation, the upper redistribution line pattern123may be in or on the chip section CS, the input section IS, and the output section OS of the film substrate110. In an implementation, the upper redistribution line pattern123may include a pattern connected to the input pad130, the output pad140, and the chip bonding pad150. In an implementation, the lower redistribution line pattern125may include a pattern extending in the horizontal direction (e.g., X direction) on the lower surface110bof the film substrate110. In an implementation, the lower redistribution line pattern125may be in or on the chip section CS, the input section IS, and the output section OS of the film substrate110. In an implementation, the lower redistribution line pattern125may include a pattern connected to the input pad130, the output pad140, and the chip bonding pad150. In an implementation, the redistribution via pattern127may include a pattern that penetrates the film substrate110in a vertical direction (e.g., Z direction), and connects the upper redistribution line pattern123to the lower redistribution line pattern125. In an implementation, the redistribution via pattern127may penetrate at least one of the chip section CS, the input section IS, and the output section OS of the film substrate110, and may connect the upper redistribution line pattern123to the lower redistribution line pattern125. The input pad130of the package substrate film10may be on the upper surface110aof the film substrate110. The input pad130may be on the input section IS of the film substrate110. In an implementation, the input pad130may include a pad for the signal input of the package substrate film10. In an implementation, the input pad130may be connected to a portion of a PCB, such as a flexible PCB (FPCB), and may include a pad for receiving an electrical signal from the PCB. In an implementation, the input pad130may be electrically connected to the chip bonding pad150via the upper redistribution line pattern123, the lower redistribution line pattern125, and the redistribution via pattern127. In an implementation, one side of the input pad130may be connected to the upper redistribution line pattern123. In an implementation, an area of the input pad130may be greater than that of the upper redistribution line pattern123. In an implementation, a material of the input pad130may include a metal, e.g., copper (Cu), nickel (Ni), aluminum (Al), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. The output pad140of the package substrate film10may be on the upper surface110aof the film substrate110. The output pad140may be on the output section OS of the film substrate110. In an implementation, the output pad140may include a pad for the signal output of the package substrate film10. In an implementation, the output pad140may be connected to a portion of the display panel, and may include a pad for transmitting an electrical signal to the display panel. In an implementation, the output pad140may be electrically connected to the chip bonding pad150via the upper redistribution line pattern123, the lower redistribution line pattern125, and the redistribution via pattern127. In an implementation, one side of the output pad140may be connected to the upper redistribution line pattern123. In an implementation, an area of the output pad140may be greater than that of the upper redistribution line pattern123. In an implementation, the material of the output pad140may include a metal, e.g., copper (Cu), nickel (Ni), aluminum (Al), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. The chip bonding pad150of the package substrate film10may be on the upper surface110aof the film substrate110. The chip bonding pad150may be on the chip section CS (e.g., between the input section IS and the output section OS). In an implementation, the chip bonding pad150may include a pad for electrical connection to the semiconductor chip20. In an implementation, the chip bonding pad150may be connected to the chip connection terminal310of the semiconductor chip20, and may include a pad for signal transfer of the semiconductor chip20. In an implementation, the chip bonding pad150may be electrically connected to the input pad130and the output pad140via the upper redistribution line pattern123, the lower redistribution line pattern125, and the redistribution via pattern127. In an implementation, one side of the chip bonding pad150may be connected to the upper redistribution line pattern123. In an implementation, an area of the chip bonding pad150may be greater than that of the upper redistribution line pattern123. In an implementation, the material of the chip bonding pad150may include a metal, e.g., copper (Cu), nickel (Ni), aluminum (Al), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. The passivation layer160of the package substrate film10may include a layer extending conformally along the upper surface110aand the lower surface110bof the film substrate110. In an implementation, the passivation layer160may cover the upper redistribution line pattern123on the upper surface110aof the film substrate110. In an implementation, the passivation layer160may expose the input pad130, the output pad140, the chip bonding pad150, and the test pad230, which are on the upper surface110aof the film substrate110. In an implementation, the passivation layer160may cover the lower redistribution line pattern125on the lower surface110bof the film substrate110. In an implementation, the passivation layer160may include an insulating material. In an implementation, a material of the passivation layer160may include, e.g., silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonate (SiOCN), silicon carbon nitride (SiCN), or a combination thereof. The test pattern220of the package substrate film10may extend on the film substrate110, and may include a pattern of a conductive material for testing a signal flow of the package substrate film10. In an implementation, the material of the test pattern220may include a metal, e.g., copper (Cu), nickel (Ni), aluminum (Al), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. In an implementation, the test pattern220may include an upper test line pattern223, a lower test line pattern225, a first test via pattern227a, and a second test via pattern227b. In an implementation, the upper test line pattern223may include a pattern extending in the horizontal direction (e.g., X direction) on the upper surface110aof the film substrate110. In an implementation, the upper test line pattern223may extend on the chip section CS, the input section IS, the output section OS, and the test section TS of the film substrate110. In an implementation, the upper test line pattern223may include a test pattern connected to the input pad130, the output pad140, and the chip bonding pad150. In an implementation, the lower test line pattern225may include a pattern extending in the horizontal direction (e.g., X direction) on the lower surface110bof the film substrate110. In an implementation, the lower test line pattern225may extend on the chip section CS, the input section IS, the output section OS, and the test section TS of the film substrate110. In an implementation, the lower test line pattern225may include a test pattern connected to the input pad130, the output pad140, and the chip bonding pad150. In an implementation, the first test via pattern227aand the second test via pattern227bmay include patterns that penetrate the film substrate110in the vertical direction (e.g., Z direction), and connect the upper test line pattern223to the lower test line pattern225. In an implementation, the first test via pattern227amay be inside the second test via pattern227b. In an implementation, the first test via pattern227amay be closer to the chip section CS than the second test via pattern227bis to the chip section CS (e.g., in the X direction). In an implementation, the first test via pattern227amay pass through at least one of the chip section CS, the input section IS, and the output section OS of the film substrate110. In an implementation, when the package substrate film10is individualized, the first test via pattern227amay not be removed but may remain. In an implementation, the first test via pattern227amay pass through the test section TS of the film substrate110. In an implementation, when the package substrate film10is individualized, the first test via pattern227amay be removed. In an implementation, a portion of the first test via pattern227amay pass through at least one of the chip section CS, the input section IS, and the output section OS of the film substrate110, and the other portion thereof may pass through the test section TS of the film substrate110. In an implementation, when the package substrate film10is individualized, a portion of the first test via pattern227amay be removed, and the other portion thereof may remain. In an implementation, the second test via pattern227bmay pass through the test section TS among the sections of the film substrate110. In an implementation, when the package substrate film10is individualized, the second test via pattern227bmay be removed. In an implementation, the upper test line pattern223may include a first upper test line pattern223aand a second upper test line pattern223b. In an implementation, the first upper test line pattern223amay include a pattern for connecting the first test via pattern227ato a first test pad230a. In an implementation, the second upper test line pattern223bmay include a pattern for connecting the second test via pattern227bto a second test pad230b. In an implementation, the first upper test line pattern223amay be connected to the first test via pattern227a, and may extend outwardly (e.g., in the X direction) from the first test via pattern227a. In an implementation, the first upper test line pattern223amay be connected to the first test via pattern227a, and may extend in a direction toward the test section TS from the output section OS of the film substrate110. In an implementation, the second upper test line pattern223bmay be connected to the second test via pattern227b, and may extend inwardly from the second test via pattern227b(e.g., in the X direction). In an implementation, the second upper test line pattern223bmay be connected to the second test via pattern227b, and may extend in a direction toward the output section OS from the test section TS of the film substrate110. In an implementation, a signal flow direction of the first upper test line pattern223amay be different from (e.g., opposite to) that of the second upper test line pattern223b. In an implementation, the signal flow direction of the first upper test line pattern223amay be a direction from the output section OS to the test section TS, and the signal flow direction of the second upper test line pattern223bmay be a direction from the test section TS to the output section OS. The test pad230of the package substrate film10may be on the upper surface110aof the film substrate110. The test pad230may be on the test section TS of the film substrate110. In an implementation, the test pad230may be between the first test via pattern227aand the second test via pattern227b. In an implementation, the first test pad230aand the second test pad230bmay be between the first test via pattern227aand the second test via pattern227b, and may face each other. In an implementation, the test pad230may be used in a test process of the package substrate film10, and may be a pad to be removed in an individualization process of the package substrate film10. In an implementation, the material of the test pad230may include a metal, e.g., copper (Cu), nickel (Ni), aluminum (Al), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. In an implementation, the test pad230may include the first test pad230aand the second test pad230b. In an implementation, the first test pad230aand the second test pad230bmay be on the test section TS of the film substrate110. In an implementation, the first test pad230amay include a test pad connected to the first test via pattern227aand the first upper test line pattern223a. One side of the first test pad230amay be connected to a first upper test line pattern223a. In an implementation, an area of the first test pad230amay be greater than that of the first upper test line pattern223a. In an implementation, the second upper test line pattern223bmay include a test pad connected to the second test via pattern227band the second upper test line pattern223b. One side of the second test pad230bmay be connected to a second upper test line pattern223b. In an implementation, an area of the second upper test pad230bmay be greater than that of the second upper test line pattern223b. FIG.2is a plan view of a test section TS1of the package substrate film10, according to an embodiment.FIG.3is an enlarged view of a region A inFIG.2. Referring toFIGS.2and3together, the test section TS1of the package substrate film10may be distinguished into or include a first test section TS_a and a second test section TS_b, e.g., by or about a central axis C. The central axis C may extend in a direction (e.g., Y direction) vertical or orthogonal to a direction (e.g., X direction) in which the film substrate110extends, and may include an axis that crosses between the first test pad230aand the second test pad230b. In an implementation, the first test section TS_a may be inside or at one side of the central axis C, and may include a section in which the first upper test line pattern223aand the first test pad230aare arranged. In an implementation, the second test section TS_b may be outside or at another side of the central axis C, and may include a section in which the second upper test line pattern223band the second test pad230bare arranged. In an implementation, the first upper test line pattern223aand the first test pad230amay be in the first test section TS_a, and the first test section TS_a may be a portion of the test section TS in which the second upper test line pattern223band the second test pad230bare not arranged. In an implementation, the second upper test line pattern223band the second test pad230bmay be in the second test section TS_b, and the second test section TS_b may include a section in which the first upper test line pattern223aand the first test pad230aare not arranged. In an implementation, in the first test section TS_a and the second test section TS_b, the first upper test line pattern223aand the second upper test line pattern223bmay cross or face each other, and may not be arranged (e.g., cross arranged). In an implementation, the first test section TS_a may include only the first upper test line pattern223a(e.g., and not the second upper test line pattern223b) and the second test section TS_b may include only the second upper test line pattern223b(e.g., and not the first upper test line pattern223a). In an implementation, a width w (e.g., in the Y direction) of each of the first upper test line pattern223aand the second upper test line pattern223bmay increase (e.g., relative to other devices). When the test section TS of the film substrate110is viewed in a plan view, the width w of each of the first upper test line pattern223aand the second upper test line pattern223bmay be defined as a thickness of each of the first upper test line pattern223aand the second upper test line pattern223b, respectively (e.g., in the Y direction). In an implementation, the widths w of the first upper test line pattern223aand the second upper test line pattern223bmay exceed about 8 micrometers. In an implementation, the widths w of the first upper test line pattern223aand the second upper test line pattern223bmay each be about 10 micrometers to about 20 micrometers. In an implementation, a pitch p1between the first upper test line patterns223aand a pitch p2between the second upper test line patterns223bmay increase (e.g., relative to other devices). When the test section TS of the film substrate110is viewed in a plan view, the pitch p1between the first upper test line patterns223aand the pitch p2between the second upper test line patterns223bmay be defined as a distance between the centers of adjacent first upper test line patterns223aand a distance between the centers of adjacent second upper test line patterns223b, respectively (e.g., along the Y direction). In an implementation, the pitch p1between the first upper test line patterns223aand the pitch p2between the second upper test line patterns223b(e.g., as measured at ends thereof) may not exceed about 15 micrometers. In an implementation, the pitch p1between the first upper test line patterns223aand the second pitch p2between the second upper test line patterns223bmay be about 20 micrometers to about 40 micrometers. The widths w and the pitches p1and p2of a plurality of first test pads230aand a plurality of second test pads230bof the package substrate film10according to an embodiment may increase, respectively, short defects of the package substrate film10may be reduced, and an electrical connection path of the package substrate film10may be improved. In an implementation, each of the first test pad230aand the second test pad230bmay be provided in a plurality. In an implementation, the first test pad230amay be inside the central axis C (e.g., in the first test section TS_a) in a plurality. In an implementation, the second test pad230bmay be provided outside the central axis C (e.g., in the second test section TS_b) in a plurality. In an implementation, the plurality of first test pads230aand the plurality of second test pads230bmay each have, e.g., a rectangular shape or other shape. In an implementation, distances or widths d1and d2in a direction (e.g., Y direction) of the plurality of first test pads230aand the plurality of second test pads230bmay not exceed about 130 micrometers, respectively. In an implementation, the widths d1and d2in the Y direction of the plurality of first test pads230aand the plurality of second test pads230bmay each be about 140 micrometers to about 300 micrometers, respectively. In an implementation, the widths d1and d2of the plurality of first test pads230aand the plurality of second test pads230bof the package substrate film10may each be about 140 micrometers to about 300 micrometers, respectively, and contact defects of the plurality of first test pads230aand the plurality of second test pads230bof a test pin (710inFIG.15) of a test device (700inFIG.15) for testing the package substrate film10may be reduced. In an implementation, the plurality of first test pads230aand the plurality of second test pads230bmay be arranged to be symmetrical based on or about the central axis C. In an implementation, if the first test section TS_a (in which the plurality of first test pads230aare formed) were to be folded about the central axis C, the plurality of first test pads230amay be (e.g., vertically) superimposed with the plurality of second test pads230b. The plurality of first test pads230aand the plurality of second test pads230bmay be symmetrically arranged about the central axis C, and accordingly, a movement of the test device (e.g., a probe card) in the test operation of the package substrate film10may be regular. In an implementation, a test yield of the package substrate film10by using the test device may be improved. In an implementation, the plurality of first test pads230aand the plurality of second test pads230bmay be arranged asymmetrically about the central axis C. In an implementation, the first test pads230aand the second test pads230bmay include the plurality of first test pads230aand the plurality of second test pads230bof substantially the same size, respectively. In an implementation, the first test pad230aand the second test pad230bmay include the plurality of first test pads230aand the plurality of second test pads230bof different sizes, respectively. In an implementation, a scribe lane SL for the individualization of the package substrate film10according to the embodiment may be in the first test section TS_a. In an implementation, when the package substrate film10is individualized at the scribe lane SL, portions of the first test pad230aand the first upper test line pattern223ain the first test section TS_a may be removed, and the second test pad230b, the second upper test line pattern223b, and the second test via pattern227bof the second test section TS_b may also be removed. In an implementation, when the package substrate film10is individualized at the scribe lane SL, portions of the first test via pattern227aand the first upper test line pattern223amay remain. FIG.4is a plan view of a test section TS2of the package substrate film10, according to an embodiment. In an implementation, the test section TS2of the package substrate film10may be distinguished into or include the first test section TS_a and a second test section TS_b, e.g., at sides of the central axis C. The central axis C may extend in the direction (e.g., Y direction) orthogonal to the direction (e.g., X direction) in which the film substrate110extends, and may include an axis that crosses between the first test pad230aand the second test pad230b. In an implementation, the first test section TS_a may be inside (e.g., at one side of) the central axis C, and may include a section in which the first upper test line pattern223aand the first test pad230aare arranged. In an implementation, the second test section TS_b may be outside (e.g., at another side of) the central axis C, and may include a section in which the second upper test line pattern223band the second test pad230bare arranged. In an implementation, the plurality of first test pads230aand the plurality of second test pads230bmay be arranged to be symmetrical based on or about the central axis C. In an implementation, if the first test section TS_a (in which the plurality of first test pads230aare formed) were to be folded at the central axis C, the plurality of first test pads230amay be (e.g., vertically) superimposed with or on the plurality of second test pads230b. In an implementation, the plurality of first test pads230aand the plurality of second test pads230bmay be arranged asymmetrically about the central axis C. In an implementation, the first test pad230aand the second test pad230bmay include the plurality of first test pads230aand the plurality of second test pads230bof different sizes, respectively. In an implementation, lengths in the X direction (e.g., parallel with a direction in which the film substrate110extends) of the plurality of first test pads230aand the plurality of second test pads230bmay be defined as first lengths t1and t2, respectively, and lengths in the Y direction (e.g., orthogonal to the X direction) of first test pads230aand the plurality of second test pads230bmay be defined as second lengths d1and d2, respectively. The first length t1of each first test pad230amay be less than the second length d1of each first test pad230aand the first length t2of each second test pad230bmay be less than the second length d2of each second test pad230b. In an implementation, the second lengths d1and d2of each first test pad230aand each second test pad230bmay exceed about 130 micrometers, respectively. In an implementation, the second lengths d1and d2of each first test pad230aand each second test pad230bmay exceed about 140 micrometers to about 300 micrometers, respectively. In an implementation, when the first test pad230aand the second test pad230binclude the plurality of first test pads230aand the plurality of second test pads230b, which are provided in different sizes, respectively, the second lengths d1and d2of the first test pad230aand second test pad230b, which have smallest sizes among the plurality of first test pads230aand second test pads230b, may be about 140 micrometers to about 160 micrometers, respectively. In an implementation, the second lengths d1and d2of the first test pad230aand second test pad230b, which have smallest sizes among the plurality of first test pads230aand second test pads230b, may be about 156 micrometers, respectively. In an implementation, when the first test pad230aand the second test pad230binclude the plurality of first test pads230aand the plurality of second test pads230b, which are provided in different sizes, respectively, the second lengths d1and d2of the first test pad230aand second test pad230b, which have largest sizes among the plurality of first test pads230aand second test pads230b, may be about 250 micrometers to about 300 micrometers, respectively. In an implementation, the second lengths d1and d2of the first test pad230aand second test pad230b, which have largest sizes among the plurality of first test pads230aand second test pads230b, may be about 279 micrometers, respectively. The first test pad230aand the second test pad230bof the package substrate film10according to an embodiment may be between the first test via pattern227aand the second test via pattern227b, and accordingly, spatial utilization on the film substrate110of the first test pad230aand the second test pad230bmay be improved. Accordingly, a size of the package substrate film10according to an embodiment may be reduced. In an implementation, areas of the first test pad230aand the second test pad230bmay be increased, and accordingly, the yield of the test process by using the first test pad230aand the second test pad230bmay be improved. FIG.5is a cross-sectional view of a semiconductor package1according to an embodiment. The semiconductor package1according to an embodiment may include the package substrate film10and the semiconductor chip20mounted on the package substrate film10. The semiconductor package1according to an embodiment may include the COF package. In an implementation, the semiconductor package1may include a semiconductor package for performing a function of implementing colors by controlling pixels of a display panel. The package substrate film10of the semiconductor package1may be the same as that described with reference toFIG.1throughFIG.4, and repeated detailed descriptions thereof may be omitted. In an implementation, the package substrate film10of the semiconductor package1may be in made individualized by performing a cutting process at the scribe lane SL. In an implementation, the scribe lane SL may pass through the test section TS of the package substrate film10. In an implementation, when the first test via pattern227apasses through at least one of the chip section CS, the input section IS, and the output section OS of the film substrate110, the first test via pattern227amay not be removed and may remain in the package substrate film10. In an implementation, when the first test via pattern227apasses through the test section TS of the film substrate110, the first test via pattern227amay be removed. In an implementation, when a portion of the first test via pattern227apasses through at least one of the chip section CS, the input section IS, and the output section OS, and the other portion thereof passes through the test section TS of the film substrate110, a portion of the first test via pattern227amay be removed, and the other portion thereof may remain in the package substrate film10. In an implementation, the second test via pattern227bmay pass through the test section TS. Accordingly, when the package substrate film10is individualized, the second test via pattern227bmay be removed. In an implementation, when the first upper test line pattern223ais on the output section OS and the test section TS of the film substrate110, and the package substrate film10is individualized, a portion of the first upper test line pattern223amay remain in the package substrate film10. The semiconductor chip20of the semiconductor package1may be on the chip section CS of the film substrate110. The semiconductor chip20may include a semiconductor chip that performs a function of, e.g., implementing colors by controlling pixels of the display panel. In an implementation, the semiconductor chip20may include a display driver (DD) integrated circuit (IC) (DDI). In an implementation, the semiconductor chip20may include first and second semiconductor chips20aand20b. As illustrated inFIG.5, the semiconductor chip20may include the first semiconductor chip20aand the second semiconductor chip20b. In an implementation, the first semiconductor chip20aand the second semiconductor chip20bmay include semiconductor chips of different types. Accordingly, the semiconductor package1may include a system in package (SIP) in which the first and second semiconductor chips20aand20bof different types are electrically connected to each other and operate as one system. In an implementation, the first and second semiconductor chips20aand20bmay include semiconductor chips of the same type. In an implementation, the first and second semiconductor chips20aand20bmay include active layers at portions adjacent to lower surfaces thereof. In an implementation, each of the first and second semiconductor chips20aand20bmay include an active layer at a portion thereof adjacent to one surface facing the upper surface110aof the film substrate110. In an implementation, the active layers of the first and second semiconductor chips20aand20bmay include a plurality of individual devices of various types. In an implementation, the plurality of individual devices may include various micro-electronic devices, e.g., a complementary metal-oxide-semiconductor (CMOS) transistor, a metal-oxide-semiconductor field effect transistor (MOSFET), large scale integration (LSI), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, etc. In an implementation, the first semiconductor chip20aand the second semiconductor chip20bmay include the chip connection terminal310. The first semiconductor chip20aand the second semiconductor chip20bmay be flip-chip bonded to the film substrate110via the chip connection terminal310. The chip connection terminal310of the first semiconductor chip20aand the second semiconductor chip20bmay contact the chip bonding pad150in the chip section CS on the upper surface110aof the film substrate110. FIG.6is a plan view of a test section TS' of a package substrate film10′, according to a comparative example.FIG.7is an enlarged view of a region B inFIG.6. In addition,FIG.8is an image showing the test section TS' after a test on the package substrate film10′ according to the comparative example was performed. Referring toFIGS.6through8together, a first test pad230a′ and a second test pad230b′ of the package substrate film10′ according to the comparative example may be on the outermost boundary of the package substrate film10′. In other words, both the first test pad230a′ and a second test pad230b′ of the package substrate film10′ according to the comparative example may be outside a first test via pattern227a′ and a second test via pattern227b′. As both the first test pad230a′ and the second test pad230b′ are arranged outside the first test via pattern227a′ and the second test via pattern227b′, sizes of the first test pad230a′ and the second test pad230b′ may be reduced due to a limited space of the film substrate110. For example, second lengths (e.g., lengths along the Y direction) of the first test pad230a′ and a second test pad230b′ of the package substrate film10′ may be less than about 130 micrometers, respectively. Referring toFIG.8, due to relatively small sizes of the first test pad230a′ and a second test pad230b′ of the package substrate film10′, contact defects of the first test pad230a′ and a second test pad230b′ of a probe device may occur. In addition, as both the first test pad230a′ and the second test pad230b′ are arranged outside the first test via pattern227a′ and the second test via pattern227b′, signal flow directions of a first upper test line pattern223a′ connecting the first test via pattern227a′ to the first test pad230a′ and a second upper test line pattern223b′ connecting the second test via pattern227b′ to the second test pad230b′ may be substantially the same. In addition, the second upper test line pattern223b′ may be between a plurality of first upper test line patterns223a′, and the first upper test line pattern223a′ may be between a plurality of second upper test line patterns223b′. Accordingly, widths w′ (in the Y direction) of the first upper test line pattern223a′ and the second upper test line pattern223b′ may be relatively small. For example, the widths w′ of the first upper test line pattern223a′ and the second upper test line pattern223b′ may be less than about 8 micrometers. In addition, a pitch p′, which is a separation distance (e.g., in the Y direction) between the first upper test line pattern223a′ and the second upper test line pattern223b′, may be relatively small. For example, the pitch p′ between the first upper test line pattern223a′ and the second upper test line pattern223b′ may be less than about 15 micrometers. As the width w′ of the first upper test line pattern223a′ and the second upper test line pattern223b′ is relatively small, and the pitch p′ between the first upper test line pattern223a′ and the second upper test line pattern223b′ is also relatively small, short defects between the first upper test line pattern223a′ and the second upper test line pattern223b′ may occur. In addition, the reliability of an electrical connection structure of the package substrate film10′ may be reduced. The package substrate film10and the semiconductor package1including the same according to an embodiment may include the first test pad230aand the second test pad230bbetween the first test via pattern227aand the second test via pattern227b. In an implementation, areas of the first test pad230aand the second test pad230bincluded in the package substrate film10may be increased (e.g., as compared with other devices), and the yield of the test process by using the first test pad230aand the second test pad230bmay be improved. In an implementation, the size of the package substrate film10according to an embodiment may be reduced. In an implementation, the package substrate film10may have the structure described above, and the width w and the first and second pitches p1and p2of the plurality of first test pads230aand the plurality of second test pads230bmay increase (e.g., may be relatively greater than those of other types of devices), respectively. Accordingly, short defects of the package substrate film10according to an embodiment may be reduced, and the electrical connection path of the package substrate film10may be improved. In an implementation, the plurality of first test pads230aand the plurality of second test pads230bof the package substrate film10may be arranged symmetrical with respect to or about the central axis C, and the movement of the test device (e.g., a probe card) in the test operation of the package substrate film10may be regular. Accordingly, the test yield of the package substrate film10by using the test device may be improved. In an implementation, the test speed of the package substrate film10by using the test device may be improved. FIG.9is a flowchart of a flow of methods of fabrication, testing, and individualization (S10) of the semiconductor package1, according to an embodiment.FIG.9is a flowchart of the flow of the methods of fabrication, testing, and individualization (S10) of the semiconductor package1including the COF. FIG.10is a flowchart of a flow of a method of fabrication (S100) of the semiconductor package1, according to an embodiment.FIG.10is a flowchart of the flow of the method of fabrication (S100) of the semiconductor package1including the COF before individualization. In addition,FIGS.11through16are stages in the method of fabrication, testing, and individualization (S10) of the semiconductor package1, according to embodiments. Referring toFIGS.9and10together, the method of fabrication, testing, and individualization (S10) of the semiconductor package1according to embodiments may include fabricating the semiconductor package1including the COF (S100), testing the signal flow of the semiconductor package1including the COF (S200), and individualizing the semiconductor package1including the COF (S300). In an implementation, the method of fabrication of the semiconductor package1including the COF (S100) according to an embodiment may include forming a via hole H in the film substrate110(S1100), forming the redistribution pattern120, the input pad130, the output pad140, the chip bonding pad150, the test pattern220, and the test pad230(S1200), forming the passivation layer160(S1300), and mounting the semiconductor chip20(S1400). Referring toFIGS.9,10, and11together, operation S1100may include an operation of forming the via hole H in the film substrate110. The via hole H of the film substrate110may be filled with a conductive material in operation S1200, and the via hole H filled with the conductive material may function as the redistribution via pattern127, the first test via pattern227a, and the second test via pattern227b. In an implementation, operation S1100may include an operation of forming the via hole H that penetrates the film substrate110in the vertical direction by using a laser drilling process or an etching process. Referring toFIGS.9,10, and12together, operation S1100may include an operation of forming the redistribution pattern120, the input pad130, the output pad140, the chip bonding pad150, the test pattern220, and the test pad230by using a photolithography process, a plating process, and an etching process, or the like on the upper surface110aand the lower surface110bof the film substrate110. In an implementation, an operation of forming the redistribution pattern120may include operations of forming the redistribution via pattern127by filling the via hole H of the film substrate110with a conductive material, forming of the upper redistribution line pattern123extending on the upper surface110aof the film substrate110and being connected to the redistribution via pattern127, and forming the lower redistribution line pattern125extending on the lower surface110bof the film substrate110and being connected to the redistribution via pattern127. In an implementation, an operation of forming the input pad130may include an operation of forming the input pad130connected to the upper redistribution line pattern123in the input section IS on the upper surface110aof the film substrate110. In an implementation, an operation of forming the output pad140may include an operation of forming the output pad140connected to the upper redistribution line pattern123on the output section OS on the upper surface110aof the film substrate110. In an implementation, an operation of forming the chip bonding pad150may include an operation of forming the chip bonding pad150connected to the upper redistribution line pattern123on the chip section CS on the upper surface110aof the film substrate110. In an implementation, an operation of forming the test pattern220may include operations of forming the first test via pattern227aand the second test via pattern227bby filling the via hole H of the film substrate110with a conductive material, forming the lower test line pattern225extending on the lower surface110bof the film substrate110and being connected to the first test via pattern227aand the second test via pattern227b, and forming the first upper test line pattern223aextending on the upper surface110aof the film substrate110and being connected to the first test via pattern227a, and the second upper test line pattern223bextending on the upper surface110aof the film substrate110and being connected to the second test via pattern227b. In an implementation, an operation of forming the test pad230may include operations of forming the first test pad230aconnected to the first upper test line pattern223a, and forming the second test pad230bconnected to the second upper test line pattern223b. In an implementation, the first test pad230amay be formed outside the first test via pattern227a, and the second test pad230bmay be formed inside the second test via pattern227b. In an implementation, each of the first test pad230aand the second test pad230bmay be formed between the first test via pattern227aand the second test via pattern227b. In an implementation, the first test pad230aand the second test pad230bmay be formed on the test section TS of the film substrate110to face each other. Referring toFIGS.9,10, and13together, operation S1300may include an operation of forming the passivation layer160by applying a coating process, a photolithography process, an etching process, etc. In an implementation, the passivation layer160may be formed to extend on the upper surface110aof the film substrate110, and cover the upper redistribution line pattern123, the first upper test line pattern223a, and the second upper test line pattern223b. In an implementation, the passivation layer160may expose the input pad130, the output pad140, and the chip bonding pad150, which are arranged on the upper surface110aof the film substrate110, without covering them. In an implementation, the passivation layer160may be formed to extend on the lower surface110bof the film substrate110and cover the lower redistribution line pattern125and the lower test line pattern225. Referring toFIGS.9,10, and14together, operation S1400may include an operation of mounting the semiconductor chip20on the chip section CS of the film substrate110by applying a flip chip bonding. In an implementation, the semiconductor chip20may be mounted in the chip section CS of the film substrate110so that the chip connection terminal310of the semiconductor chip20contacts the chip bonding pad150on the chip section CS of the film substrate110(S1400). In an implementation, the plurality of first and second semiconductor chips20aand20bmay be mounted on the chip section CS of the film substrate110(S1400). In an implementation, the plurality of first and second semiconductor chips20aand20bmay include semiconductor chips of different types from each other. Accordingly, the semiconductor package1fabricated in operation S1400may include a system in package (SIP) in which the plurality of first and second semiconductor chips20aand20bof different types from each other are electrically connected to each other, and operate as one system. By performing operations S1100through S1400, the semiconductor package1before being individualized according to an embodiment may be fabricated. Referring toFIGS.9and15together, operation S200may include an operation of testing the electrical signal flow of the semiconductor package1including the COF that has been fabricated by performing operation S100by using a test device700. The test device700that includes a test pin710for the electrical signal flow test of the semiconductor package1may be used (S200). In an implementation, the test device700may include the probe card. In an implementation, operation S200may include operations of contacting the test pin710of the test device700to the first test pad230aand the second test pad230bof the semiconductor package1, applying an electrical signal to the first test pad230aand the second test pad230bvia the test pin710of the test device700, and determining defects of the semiconductor package1by using a signal to be identified from the applied electrical signal. In an implementation, the first test pad230aand the second test pad230bof the semiconductor package1may be on the test section TS of the film substrate110. In an implementation, the first test pad230aand the second test pad230bof the semiconductor package1may be between the first test via pattern227aand the second test via pattern227b, and may face each other. Accordingly, the sizes of the first test pad230aand the second test pad230bmay be increased (e.g., relative to other types of devices). In an implementation, the dimensions (e.g., second lengths) d1and d2extending in a direction (e.g., Y direction) vertical to a direction in which the film substrate110extends (e.g., X direction) among dimensions of the plurality of first test pads230aand the plurality of second test pads230bmay be about 140 micrometers to about 300 micrometers, respectively. In an implementation, the dimensions d1and d2extending in the Y direction vertical to the direction in which the film substrate110extends among the dimensions of the plurality of first test pads230aand the plurality of second test pads230bof the semiconductor package1according to an embodiment may be about 140 micrometers to about 300 micrometers, respectively, and contact defects of the plurality of first test pads230aand the plurality of second test pads230bof the test pin710of the test device700for testing the package substrate film10may be reduced. In an implementation, the yield of the electrical signal flow test of the semiconductor package1by using the test device700may be improved. Referring toFIGS.9and16together, operation S300may include an operation of individualization of the semiconductor package1including the COF in which operation S200has been completed. Operation S300may include an operation of individualization of the semiconductor package1by cutting at the scribe lane SL of the semiconductor package1. In an implementation, operation S300may include an operation of cutting at the scribe lane SL by using a blade wheel. In an implementation, the operation S300may include an operation of cutting the scribe lane SL by using a laser. In an implementation, the scribe lane SL of the semiconductor package1may be on the test section TS. Accordingly, when the scribe lane SL of the semiconductor package1is cut, the first test pad230a, the second test pad230b, the second test via pattern227b, and the second upper test line pattern223bmay be removed. In an implementation, when the scribe lane SL of the semiconductor package1is cut, portions of the first test via pattern227aand the first upper test line pattern223amay remain. One or more embodiments may provide a test device in a test process of a semiconductor package, and a semiconductor package including a package substrate film capable of reducing contact defects between test pads. One or more embodiments may provide a semiconductor package of a reduced size by increasing the spatial utilization degree of test pads on a film substrate. One or more embodiments may provide a semiconductor package that reduces short defects between test line patterns, and includes a package substrate film in which electrical connection paths are improved. A package substrate film according to an embodiment may include a plurality of test pads arranged between a first via pattern and a second test via pattern. Due to a structure of a package substrate film according to an embodiment, an area of the plurality of test pads increases. Accordingly, in a test process of a semiconductor package, contact defects between a test device and a test pad are reduced, a yield of the test process may be increased. In addition, due to a structure of a package substrate film according to an embodiment, a size of a semiconductor package may be reduced, and short defects between test line patterns may be reduced. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 53,341 |
11862549 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “top,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIG.1AtoFIG.1Eare schematic cross-sectional views illustrating a manufacturing process of a semiconductor package in accordance with some embodiments of the disclosure. Referring toFIG.1A, a carrier102having a de-bonding layer104thereon is provided. In some embodiments, the de-bonding layer104is formed on a top surface of the carrier102. For example, the carrier102is a glass substrate and the de-bonding layer104is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. However, the disclosure is not limited thereto, and other suitable materials may be adapted for the carrier102and the de-bonding layer104. In alternative embodiments, a buffer layer (not shown) is coated on the de-bonding layer104, where the de-bonding layer104is sandwiched between the buffer layer and the carrier102, and a top surface of the buffer layer further provides a high degree of coplanarity. The buffer layer may be a dielectric material layer or a polymer layer which is made of polyimide, BCB, PBO, or any other suitable polymer-based dielectric material. Then, a redistribution structure110is formed over the carrier102. In some embodiments, first, a passivation layer112is formed on the de-bonding layer104. A material of the passivation layer112may include polyimide, polyimide derivative, polybenzoxazole (PBO), or any other suitable dielectric material. The passivation layer112may be formed by spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. The passivation layer112is a single layer or multiple layers. After forming the passivation layer112, a plurality of conductive vias114are formed in the passivation layer112, and a plurality of conductive patterns116are formed on the conductive vias114to electrically connect to the conductive vias114respectively. In some embodiments, a plurality of openings (not shown) are formed in the passivation layer112, and the conductive vias114are formed in the openings. The conductive patterns116are then formed on the conductive vias114respectively. In some embodiments, the conductive vias114and the conductive patterns116are formed integrally by a dual damascene process. In alternative embodiments, the conductive vias114and the conductive patterns116are formed separately by a single damascene process or any other suitable process. The conductive vias114and the conductive patterns116may each include a diffusion barrier layer and a conductive material thereon. The diffusion barrier layer may include one or more layers of TaN, Ta, TiN, Ti, CoW, or the like and be formed by ALD, or the like, and the conductive material may include copper, aluminum, tungsten, silver, combinations thereof, or the like and be formed by CVD, PVD, a plating process, or the like. The number of the conductive vias114and the conductive patterns116is not limited in the disclosure. After forming the conductive patterns116, a plurality of dielectric layers122and a plurality of conductive patterns124are alternately formed over the conductive patterns116, to complete the formation of the redistribution structure110. The conductive patterns124may include vias and/or traces to interconnect any devices and/or to an external device. The dielectric layers122may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layers122may be formed by spin-on coating, CVD, PECVD, HDP-CVD, or the like. The conductive patterns124are formed in/on the dielectric layers122. The conductive patterns124may include a diffusion barrier layer and a conductive material thereon. The diffusion barrier layer may include one or more layers of TaN, Ta, TiN, Ti, CoW, or the like and be formed by ALD, or the like, and the conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, or the like and be formed by CVD, PVD, a plating process, or the like. The number of the dielectric layers122and the conductive patterns124is not limited in the disclosure. Referring toFIG.1B, at least one die130,140is bonded to the redistribution structure110. The dies130,140may each have a single function (e.g., a logic device, memory die, etc.), or may have multiple functions (e.g., a system on a chip (SoC), an application-specific integrated circuit (ASIC), etc.). In some embodiments, the die130is a SoC, and the die140is a memory device. The memory device may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In an embodiment, the die140is an HBM module. In some embodiments, the dies130,140are bonded to the redistribution structure110with die connectors134,144. The die connectors134,144may be electrically connected to bond pads132,142of the dies130,140. In some embodiments, the dies130,140are placed on the redistribution structure110using a pick-and-place tool. The die connectors134,144may be formed from a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the die connectors134,144are formed by initially forming a layer of solder through methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the die connectors134,144into desired bump shapes. The die connectors134,144form joints between corresponding conductive patterns124(i.e., the outermost conductive patterns124) on the redistribution structure110and the dies130,140, and electrically connect the redistribution structure110to the dies130,140. Then, an underfill150may be formed between the dies130,140and the redistribution structure110, surrounding the die connectors134,144. The underfill150may be formed by a capillary flow process after the dies130,140are attached, or may be formed by a suitable deposition method before the dies130,140are attached. After forming the underfill150, an encapsulant152is formed over the dies130,140and the underfill150. The encapsulant152may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The encapsulant152may be formed over the redistribution structure110such that the dies130,140are buried or covered. The encapsulant152is then cured. Referring toFIG.1C, a plurality of under-ball metallurgy (UBM) patterns160and a plurality of conductive terminals162are sequentially formed on the conductive vias114. In some embodiments, the carrier102is de-bonded and is separated from the passivation layer112. In some embodiments, the de-bonding process includes projecting a light such as a laser light or an UV light on the de-bonding layer104(e.g., the LTHC release layer) so that the carrier102can be easily removed along with the de-bonding layer104. During the de-bonding step, a tape (not shown) may be used to secure the structure before de-bonding the carrier102and the de-bonding layer104. After removing the carrier102and the de-bonding layer104, the UBM patterns160are formed on the conductive vias114respectively. The UBM patterns160may be formed for ball mount. The UBM patterns160include aluminum, copper, nickel, or an alloy thereof. The removal of the carrier102and the de-bonding layer104and/or formation of the UBM patterns160and the conductive terminals162may be performed while the encapsulant152is on a tape. Then, the conductive terminals162are placed on the UBM patterns160. The conductive terminals162may be controlled collapse chip connection (C4) bumps, solder balls such as a ball grid array (BGA), metal pillars, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive terminals162include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In an embodiment in which the conductive terminals162are solder bumps, the conductive terminals162are formed by initially forming a layer of solder through various methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. In this embodiment, once a layer of solder has been formed, a reflow is performed to shape the material into the desired bump shape. Referring toFIG.1D, the encapsulant152is thinned to expose surfaces of the dies130,140. The thinning may be accomplished by a CMP, a grinding process, or the like. After the thinning, surfaces (e.g., top surfaces) of the encapsulant152and dies130,140are level. In some embodiments, the redistribution structure110and the encapsulant152are singulated (not shown) by a singulation process, thereby forming a semiconductor package100. The singulation may be performed while the redistribution structure110is on a tape. Singulation is performed along scribe line regions. In some embodiments, the singulation process includes a sawing process, a laser process, or combinations thereof. As shown inFIG.1D, as a result of the singulation process, sidewalls of the redistribution structure110and the encapsulant152are substantially flush with each other. The semiconductor package100may integrate homogeneous or heterogeneous components. In some embodiments, the semiconductor package100is formed by forming the redistribution structure first, which is also referred to a redistribution layer (RDL) first process. However, the disclosure is not limited thereto. Referring toFIG.1E, the semiconductor package100may be mounted onto a package substrate202, to form a semiconductor package200. In some embodiments, the package substrate202is an interposer such as an organic interposer. The package substrate202may include a redistribution structure. For example, the redistribution structure includes alternating dielectric layers (not shown) and conductive patterns (not shown) and a plurality of bond pads204over the dielectric layers and the conductive patterns. The conductive patterns may include vias and/or traces. The dielectric layers may include organic material, and the conductive patterns and the bond pads204may include conductive material such as copper. The conductive patterns and the bond pads204may be formed through any suitable process such as deposition, single damascene, dual damascene, or the like. In some embodiments, the package substrate202is substantially free of active and passive devices. However, the disclosure is not limited thereto. In alternative embodiments, the package substrate202is made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like, may also be used. Additionally, the package substrate202may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate202may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the semiconductor package200. The devices may be formed using any suitable methods. The package substrate202may include the redistribution structure. The redistribution structure includes alternating dielectric layers (not shown) and conductive patterns (not shown) and a plurality of bond pads204over the dielectric layers and the conductive patterns. The conductive patterns and the bond pads204are formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The dielectric layers may include low-k dielectric material and the conductive patterns and the bond pads204may include conductive material such as copper. In alternative embodiments, the package substrate202is a printed circuit board such as a laminate substrate formed as a stack of multiple thin layers (or laminates) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, or the like. However, any other suitable substrate, such as an organic substrate, a ceramic substrate, or the like, may alternatively be utilized, and all such redistributive substrates that provide support and connectivity to the semiconductor package100are fully intended to be included in some embodiments. In some embodiments, the conductive terminals162are reflowed to attach the semiconductor package100to the bond pads204, thereby bonding the semiconductor package100to the package substrate202. The conductive terminals162electrically and/or physically couple the package substrate202to the semiconductor package100. In alternative embodiments, passive devices (e.g., surface mount devices (SMDs), not illustrated) may be attached to the package substrate202(e.g., bonded to the bond pads204) prior to mounting the semiconductor package100on the package substrate202. In such embodiments, the passive devices may be bonded to a same surface of the package substrate202as the conductive terminals162. In some embodiments, after bonding the semiconductor package100onto the package substrate202, an underfill210is formed between the semiconductor package100and the package substrate202, surrounding the conductive terminals162. The underfill210may be formed by a capillary flow process. In some embodiments, the geometry and the arrangement of the conductive patterns116with respect to the die (e.g., the die130) play significant roles in ensuring the reliability of the formed semiconductor package100. The configuration of the conductive patterns116will be described in detail below in conjunction withFIG.2AandFIG.2B. FIG.2AandFIG.2Bare simplified top views illustrating various arrangements of the conductive patterns116inFIG.1E. Referring toFIG.1E, in some embodiments, the conductive patterns116are disposed directly under the die130. For example, the conductive patterns116are disposed under the die130within a periphery130pof the die130. The conductive patterns116may be arranged to surround a center axis CA of the die130(also referred to as an extending line of the center axis CA). Herein, the center axis is a line passing through a center of an object, and the object is substantially symmetric with respect to the center axis. The conductive patterns116may be arranged in an array. As illustrated inFIG.2A, a top view of the conductive pattern116has an ellipse-like shape. In other words, a cross-section of the conductive pattern116substantially parallel to a surface130aof the die130ahas an ellipse-like shape. The surface130amay be an active surface or a rear surface opposite to the active surface. Herein, the term “ellipse” refers to a symmetric shape having two mutually perpendicular axes which intersect at the center thereof due to its symmetry. Similarly, the term “ellipse-like” refers to a shape like an ellipse and having two mutually perpendicular axes which intersect at the center thereof. The ellipse-like shape may not be provided with a smooth periphery or contour and may not be as symmetric as an ellipse due to the process variation and tolerance. However, viewing the shape as the whole, the ellipse-like can be interpreted as an ellipse to some extent. The ellipse-like shape may be an ellipse (as shown inFIG.4AandFIG.4B), an oval (as shown inFIG.2AandFIG.2B), an oblong (as shown inFIG.2AandFIG.2B) or the like. The oblong is a shape having two long sides and two short sides, does not have right angles, and the short sides may be curved in some embodiments. As illustrated inFIG.2A, the oval (the cross-section of the conductive patterns116) has a long-axis118aand a short-axis118bperpendicular to the long-axis118a. The long-axis118aof the conductive pattern116is aligned with the center axis CA of the die130. That is, the long-axis118apoints toward the center axis CA of the die130, and the long-axis118a(also referred to as an extending line of the long-axis118a) intersects with the center axis CA of the die130. In some embodiments, the long-axis118aof each conductive pattern116intersects with the center axis CA of the die130. A length Laof the long-axis118ais larger than a length Lbof the short-axis118b. In other words, the conductive pattern116has a longer length Lb. In some embodiments, a ratio of the length Laof the long-axis118ato the length Lbof the short-axis118bis greater than 1 and less than 8. In some embodiments, the length Laof the long-axis118aranges from 60 μm to 110 μm. The length Laof the long-axis118amay be larger than a maximum length of the UBM pattern160. For example, the UBM pattern160has a circular shape and has a diameter t1. In some embodiments, the length Laof the long-axis118aof the conductive pattern116is larger than the diameter t1of the UBM pattern160, and the diameter t1of the UBM pattern160is larger than or substantially equal to the length Lbof the short-axis118bof the conductive pattern116. In alternative embodiments, the UBM pattern160is octagonal shaped. In some embodiments, a center axis CA1of the conductive pattern116is substantially collinear with a center axis CA2of the conductive via114. That is, the center axis CA1is entirely overlapping with the center axis CA2. For example, a distance (i.e., the shortest distance) d1between the center axis CA1of the conductive pattern116to the center axis CA of the die130is the same as a distance (i.e., the shortest distance) d2between the center axis CA2of the conductive via114to the center axis CA of the die130. In some embodiments, the center axis CA1of the conductive pattern116is substantially collinear with a center axis CA3of the UBM pattern160and a center axis (not shown) of the conductive terminal162. However, the disclosure is not limited thereto. In some embodiments, the conductive patterns116are also referred to as cap patterns since the conductive patterns116cover tops of the conductive terminals162. In some embodiments, the conductive patterns116are arranged to be tilted with respect to extending directions of sidewalls of the die130. For example, as illustrated inFIG.2A, the die130is a parallelogram having four sides S1-S4connected to each other. The side S1and the side S3may extend along a first direction D1while the side S2and the side S4may extend along a second direction D2. The first direction D1is perpendicular to the second direction D2, for example. In some embodiments, the long-axis118aof the oval (the cross-section of the conductive patterns116) forms an included angle θ a with the first direction D1, and the included angle θ a is larger than 0° and smaller than 90°. In some embodiments, the long-axis118aof the oval (the cross-section of the conductive patterns116) forms an included angle θb with the second direction D2, and the included angle θb is larger than 0° and smaller than 90°. FIG.2Aalso shows a projection of the die130, the conductive patterns116, the conductive vias114and the UBM patterns160onto a surface such as a front or rear surface of the die130and a front or rear surface of the package substrate202. For example,FIG.2Aillustrates a projection of the die130, the conductive patterns116, the conductive vias114and the UBM patterns160onto the surface130aof the die130or a surface202aof the package substrate202. As shown inFIG.2A, in some embodiments, in the projection onto the surface130aor202a, a center C1of the conductive pattern116is overlapped with a center C2of the conductive via114and a center C3of the UBM pattern160. The long-axis118aof the conductive pattern116is in a direction D from the center C1of the conductive pattern116to a center C of the die130. In other words, the conductive pattern116is enlarged/extended along the direction D and thus has a larger length Lain the direction D. In some embodiments, at the cooling stage, a coefficient of thermal expansion (CTE) mismatch is present between the package substrate202and the die130, which may induce stress concentration at an outer edge of the conductive pattern116and lead to a crack of the passivation layer112aside the conductive pattern116. In some embodiments, by extending the conductive pattern116along the direction D from the center C1of the conductive pattern116to the center C of the die130, the conductive pattern116has an ellipse-like shape, and the stress is reduced. Referring toFIG.2B, an alternative configuration of the conductive patterns116is provided. As illustrated inFIG.2B, the conductive patterns116directly under the die130may be constituted by a plurality of first conductive patterns116aand a plurality of second conductive patterns116b. As illustrated inFIG.2B, a top view of the first conductive pattern116ahas an ellipse-like shape while a top view of the second conductive pattern116bhas a circular shape. In other words, a cross-section of the first conductive pattern116asubstantially parallel to the surface130aof the die130has an ellipse-like shape, and a cross-section of the second conductive pattern116bparallel to the surface130aof the die130has a circular shape. The first conductive patterns116aand the UBM patterns160are similar to the conductive patterns116and the UBM patterns160ofFIG.2Aexcept that the first conductive patterns116aare arranged at regions corresponding to corners130cof the die130. For example, as illustrated inFIG.2B, the second conductive patterns116bare sandwiched between the first conductive patterns116a. The long-axis118aof the first conductive pattern116aintersects with the center axis CA of the die130. In some embodiments, the long-axis118aof each conductive pattern116aintersects with the center axis CA of the die130. In some embodiments, the length Laof the long-axis118aof the first conductive pattern116ais larger than the diameter t1of the UBM pattern160, and the diameter t1of the UBM pattern160is larger than or substantially equal to the length Lbof the short-axis118bof the first conductive pattern116a. A diameter t2of the second conductive pattern116bis smaller than the diameter t1of the UBM pattern160, for example. In some embodiments, the center axis CA1of the first conductive pattern116ais substantially collinear with the center axis CA2of the conductive via114. In some embodiments, the center axis CA1of the first conductive pattern116ais substantially collinear with the center axis CA3of the UBM pattern160and the center axis (not shown) of the conductive terminal162. Similarly, in some embodiments, the center axes (not shown) of the second conductive pattern116b, the conductive via114, the UBM pattern160and the conductive terminal162are substantially collinear with one another. However, the disclosure is not limited thereto. In addition, in alternative embodiments, the second conductive patterns116bdisposed between the first conductive patterns116ahave other suitable shape. In an embodiment in which the second conductive pattern116bhas the same shape as the first conductive pattern116a, the long-axis of the second conductive pattern116bmay or may not intersect with the center axis CA of the die130. Similar toFIG.2A,FIG.2Balso shows a projection of the die130, the conductive patterns116, the conductive vias114and the UBM patterns160onto the surface130aof the die130or the surface202aof the package substrate202. As shown inFIG.2B, in some embodiments, in the projection onto the surface130aor202a, a center C1of the conductive pattern116ais overlapped with a center C2of the conductive via114and a center C3of the UBM pattern160. Similarly, centers (not shown) of the conductive pattern116b, the conductive via114and the UBM pattern160are overlapped. The long-axis118aof the conductive pattern116ais in a direction D from the center C1of the conductive pattern116ato a center C of the die130. In other words, the conductive pattern116ais enlarged/extended along the direction D and thus has a larger length Lain the direction D. In some embodiments, since the stress mentioned above is larger at regions corresponding to the corners130cof the die130than other sites, the conductive patterns116aat these regions are designed to have an ellipse-like shape. In other words, the conductive patterns116ain the regions corresponding to the corners130cof the die130are configured to have a larger size than the UBM patterns160therebeneath while the conductive patterns116bin other regions may remain to have a size smaller than the UBM patterns160therebeneath. In alternative embodiments, as shown inFIGS.3A and3B, the configuration of the conductive structures200is similar to that ofFIG.1EandFIG.2A, and the main difference lies the center axis CA2of the conductive via114is not collinear with the center axis CA1of the conductive pattern116. For example, as shown inFIGS.3A and3B, the center axis CA2of the conductive via114is shifted with respect to the center axis CA1of the conductive pattern116, so as to be farther away from the center axis CA of the die130than the center axis CA1of the conductive pattern116. In some embodiments, the center axis (not shown) of the conductive terminal162is collinear with the center axis CA1of the conductive pattern116. In some embodiments, a distance d1(i.e., the shortest distance) between the center axis CA1of the conductive pattern116to the center axis CA of the die130is smaller than a distance d2(i.e., the shortest distance) between the center axis CA2of the conductive via114to the center axis CA of the die130. In some embodiments, a distance d3between the center axis CA2of the conductive via114and the center axis CA1of the conductive pattern116ranges from 3 μm to 30 μm. FIG.3Balso shows a projection of the die130, the conductive patterns116, the conductive vias114and the UBM patterns160onto a surface such as a front or rear surface of the die130and a front or rear surface of the package substrate202. For example,FIG.3Billustrates a projection of the die130, the conductive patterns116, the conductive vias114and the UBM patterns160onto the surface130aof the die130or the surface202aof the package substrate202. As shown inFIG.3B, in some embodiments, in the projection onto the surface130aor202a, the center C1of the conductive pattern116is overlapped with the center C3of the UBM pattern160. In some embodiments, the center C2of the conductive via114is shifted with respect to the centers C1, C3of the conductive pattern116and the UBM pattern160. The center C2of the conductive via114may be shifted outward along the direction D from the center C1of the conductive pattern116to the center C of the die130with respect to the center C1of the conductive pattern116. A distance d4between the center C2of the conductive via114to an inner edge of the UBM pattern160along the direction D is larger than a distance d5between the center C2of the conductive via114to an outer edge of the UBM pattern160along the direction D. A difference between the distance d4and the distance d5is equal to the distance d3and ranges from 3 μm to 30 μm. The conductive pattern116has a larger length Lain the direction D from the center C1of the conductive pattern116to the center C of the die130. In other words, the conductive pattern116is enlarged along the direction D. In some embodiments, by shifting the conductive vias114outward along the direction D from the center C1of the conductive pattern116to the center C of the die130, the stress is further reduced. In above embodiments, the conductive patterns116disposed directly under the die130are configured asFIG.2A,FIG.2B,FIG.3Bor other similar arrangement, and the conductive patterns116disposed directly under the die140may have other arrangement. For example, each of the conductive patterns116disposed directly under the die140has a circular shape, and each of these conductive patterns116has a smaller diameter than the UBM patterns160or substantially the same diameter as the UBM patterns160. However, the disclosure is not limited thereto. In alternative embodiments, the conductive patterns116disposed directly under the die140are also configured as the conductive patterns116ofFIG.2A,FIG.2BandFIG.3Bor other similar arrangement. In other words, according to the design, the conductive patterns116and/or the conductive vias114may be configured corresponding to one or more dies of the semiconductor package. In some embodiments, by extending the conductive pattern of the redistribution structure along the direction toward to the center axis of the die, the conductive pattern has an ellipse-like shape. In addition, in some embodiments, the conductive via is shifted outward along the direction with respect to the center of the conductive pattern. Accordingly, the stress due to the CTE mismatch between the package substrate and the die may be reduced. Therefore, the performance of the formed semiconductor package may be improved. In accordance with some embodiments of the disclosure, a semiconductor package includes a die, a redistribution structure and a plurality of conductive terminals. The redistribution structure is disposed below and electrically connected to the die. The redistribution structure includes a plurality of conductive patterns, and at least one of the plurality of conductive patterns has a cross-section substantially parallel to the surface of the die. The cross-section has a long-axis and a short-axis, and the long-axis intersects with a center axis of the die. The conductive terminals are disposed below and electrically connected to the redistribution structure. In accordance with some embodiments of the disclosure, a semiconductor package includes a redistribution structure, a die, an underfill and an encapsulant. The redistribution structure includes a plurality of first conductive patterns and a plurality of second conductive patterns. The plurality of first conductive patterns have an ellipse-like shape respectively, and the plurality of second conductive patterns have a circular shape respectively. The die is disposed over and electrically connected to the redistribution structure. The underfill is disposed between the die and the redistribution structure. The encapsulant encapsulates the die over the redistribution structure. In accordance with some embodiments of the disclosure, a semiconductor package includes a die, a redistribution structure and a plurality of under-ball metallurgy (UBM) patterns. The die has a first center axis. The redistribution structure is disposed below and electrically connected to the die, and includes a plurality of conductive patterns and a plurality of conductive vias. The plurality of conductive vias are disposed between and in direct with the plurality of conductive patterns and the plurality of UBM patterns. One of the plurality of conductive vias has a second center axis, a respective one of the plurality of UBM patterns under the one of the plurality of conductive vias has a third center axis, and a distance between the second center axis and the first center axis is larger than a distance between the third center axis and the first center axis. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure. | 34,587 |
11862550 | Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION FIG.1illustrates a cross-sectional view of an electronic package structure in accordance with some embodiments of the present disclosure. The electronic package structure1includes a substrate10, a conductive element20, a support structure30, electrical contacts40, electronic components51and52, an encapsulant60, and a protection layer70. The substrate10may have a surface101(also referred to as “a bottom surface”), a surface102(also referred to as “an upper surface”) opposite to the surface101, and a lateral surface103angled or non-parallel with the surface101. The substrate10may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The substrate10may include an interconnection structure, such as a plurality of conductive traces and/or conductive through vias. The substrate10may include an organic substrate or a leadframe. The substrate10may include a ceramic material or a metal plate. The substrate10may include an interposer. In some embodiments, the substrate10includes a core layer11, dielectric layers13and15on opposite surfaces11aand11bof the core layer11, at least one interconnection via17passing through the core layer11, at least one conductive via12passing through the dielectric layer13, at least one conductive via14passing through the dielectric layer15, at least one conductive layer16connected to the conductive via12, and at least one conductive layer18connected to the conductive via14. In some embodiments, the substrate10may include one or more conductive pads110in proximity to, adjacent to, or embedded in and exposed at the surface101of the substrate10. The conductive pad110may be electrically connected to the conductive via12. In some embodiments, the substrate10may include one or more conductive pads112in proximity to, adjacent to, or embedded in and exposed at the surface102of the substrate10. The conductive pad112may be electrically connected to the conductive via14. The conductive element20may be disposed on the lateral surface103of the substrate10. In some embodiments, the surface101of the substrate10is free of the conductive element20. In some embodiments, the conductive element20is disposed over the surface102of the substrate10. In some embodiments, the conductive element20includes a plurality of portions (e.g., portions21,22and23, which will be discussed in details hereinafter). In some embodiments, the portion21of the conductive element20is on the lateral surface103of the substrate10. In some embodiments, the portion23of the conductive element20is disposed over the surface102of the substrate10. In some embodiments, the portion23of the conductive element20has a thickness T2a. In some embodiments, the portion21of the conductive element20has a thickness T2bsmaller than the thickness T2aof the portion23of the conductive element20. In some embodiments, the thickness T2ais from about 2 μm to about 6 μm, or from about 3 μm to about 5 μm. In some embodiments, the thickness T2bis from about 1 μm to about 3 μm, or from about 1.5 μm to about 2.5 μm. In some embodiments, the conductive element20may be or include a shielding element or a shielding layer configured to provide an electromagnetic interference (EMI) protection for the electronic components51and52, The conductive element20may include a conductive material, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof. The support structure30(also referred to as “a spacing element”) may be on the surface101of the substrate10. In some embodiments, the support structure30is configured to space the surface101(or the bottom surface) of the substrate from an external carrier. In some embodiments, the support structure30provides a predetermined gap configured to space the surface101(or the bottom surface) of the substrate from an external carrier to prevent continuously disposing a shielding layer (e.g., the conductive element20) between the lateral surface103of the substrate and the external carrier. The external carrier may be an adhesive tape or a substrate (e.g., a carrier800, which will be illustrated inFIGS.5E-5G). In some embodiments, a lateral surface303of the support structure30is spaced apart from the lateral surface103of the substrate10by a distance D1. In some embodiments, the lateral surface303of the support structure30is indented from the lateral surface103of the substrate10by the distance D1. In some embodiments, the conductive element20is further disposed on a portion of the surface101of the substrate defined by the distance D1. In some embodiments, the lateral surface303is the outermost lateral surface of the support structure30. In some embodiments, the distance D1is greater than the thickness T2bof the portion21of the conductive element20. In some embodiments, the distance D1is greater than about 20 In some embodiments, the distance D1is from about 100 μm to about 300 In some embodiments, the support structure30defines a plurality of openings310. In some embodiments, the openings310of the support structure30expose the conductive pads110of the substrate10. In some embodiments, the lateral surface303of the support structure30and the conductive element20collectively define a recess R1. In some embodiments, the lateral surface303of the support structure30and an edge portion101eof the surface101of the substrate10exposed from the support structure30define the recess R1. In some embodiments, the edge portion101eof the surface101is connected to the lateral surface103of the substrate10. In some embodiments, a thickness T1of the support structure30is greater than the thickness T2aof the portion23of the conductive element20. In some embodiments, a difference between the thickness T1of the support structure30and the thickness T2aof the portion23of the conductive element20is greater than about 2 μm. In some embodiments, the thickness T1of the support structure30is equal to or less than about 50 μm. In some embodiments, the thickness T1of the support structure30is equal to or greater than about 10 μm. In some embodiments, the thickness T1of the support structure30is from about 20 μm to about 35 μm. In some embodiments, the support structure30includes at least one portion of a solder mask. The electrical contact40may be disposed on the surface101of the substrate10. In some embodiments, the electrical contact40is disposed on the conductive pad110. In some embodiments, a portion of the electrical contact40is disposed within the opening310of the support structure30and electrically connected to the conductive pad110. In some embodiments, the recess R1defined by the support structure30and the substrate10is spaced apart from the electrical contact40. The electronic components51and52may be disposed over the surface102of the substrate10. The electronic components51and52may each be a chip or a die, one or more integrated circuit (IC) devices, and one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof. In some embodiments, the electronic component51may be an active component, such as an integrated circuit chip or a die. In some embodiments, the electrical component52may be a passive electrical component, such as a capacitor, a resistor, or an inductor. Each electronic component51,52may be electrically connected to one or more of another electronic components51,52and to the substrate10(e.g., to the conductive pads112), and the electrical connection may be attained by way of flip-chip or wire-bond techniques. The encapsulant60may be disposed over the surface102of the substrate10and encapsulate the electronic components51and52. In some embodiments, the portion23of the conductive element20directly or physically contacts a surface602(also referred to as “an upper surface”) of the encapsulant60. In some embodiments, the portion21of the conductive element20directly or physically contacts a lateral surface603of the encapsulant60. In some embodiments, the lateral surface603of the encapsulant60is substantially coplanar with the lateral surface103of the substrate10. In some embodiments, the encapsulant60may include an epoxy resin having fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof. The protection layer70may be disposed on the surface102of the substrate10. In some embodiments, the protection layer70defines a plurality of openings710. In some embodiments, the openings710of the protection layer70expose the conductive pads112of the substrate10. In some embodiments, a lateral surface703of the protection layer70is substantially coplanar with the lateral surface103of the substrate10. In some embodiments, the lateral surface703of the protection layer70is substantially coplanar with the lateral surface603of the encapsulant60. In some embodiments, the encapsulant60directly or physically contacts the protection layer70. In some embodiments, the protection layer70includes a patterned solder mask. According to some embodiments of the present disclosure, the arrangement of the lateral surface103of the substrate10and the lateral surface303of the support structure30(e.g., the recess R1) can produce a discontinuous formation surface for the conductive element20in the manufacturing process, and thus it can prevent the conductive material (i.e., the material for forming the conductive element20) from forming a continuous layer along the lateral surface103of the substrate10towards the carrier on which the substrate10is disposed. In other words, the portion of the as-formed conductive element20on the lateral surface103of the substrate10can be spaced apart from the portion of the conductive material formed on the upper surface of the carrier because of lacking of a continuous formation surface. Therefore, it can prevent the formation of metal burrs which could have been formed by pulling off a continuous layer of the conductive material when detaching the substrate10from the carrier. Accordingly, the prevention of formation of metal burrs can reduce the probability of occurrences of short circuits (i.e., between the electrical contacts40and the metal burrs that fall off when performing a deburring operation), which can increase the yields of the electronic package structure1. Moreover, according to some embodiments of the present disclosure, the recess R1is defined by the substrate10and the support structure30, and the formation of the recess R1and the openings310for exposing the conductive pads110can be performed in the same operation. In other words, the openings310for the electrical contacts40and the recess R1which benefits the prevention of metal burrs can be formed in the same operation. Therefore, additional operations are not required, and thus the process can be simplified. In addition, according to some embodiments of the present disclosure, the support structure30including at least one portion of a solder mask can be formed by lithography operation, a screen printing operation, an inkjet printing operation, or a combination thereof, and therefore the recess R1can be formed of a relatively high precision and having a relatively refined structure. Furthermore, the formation of cutting burrs resulting from mechanical cutting operations can be avoided, and thus the yields of the electronic package structure1can be increased. FIG.1Aillustrates a bottom view of an electronic package structure1in accordance with some embodiments of the present disclosure. In some embodiments,FIG.1Aillustrates a top view of the electronic package structure1as viewed from the surface101of the substrate10. In some embodiments,FIG.1illustrates a cross-sectional view along the cross-sectional line1-1′ inFIG.1A. In some embodiments, a plurality of the electrical contacts40are disposed on the surface101of the substrate10. In some embodiments, the electrical contacts40may be separated into two or more groups, and a pitch of a first group of the electrical contacts40may be different from a pitch of a second group of the electrical contacts40. In some embodiments, the portion22of the conductive element20partially covers the edge portion101eof the surface101of the substrate10. In some embodiments, a peripheral region101pof the surface101of the substrate10is exposed from the portion22of the conductive element20. In some embodiments, the peripheral region101pis within the edge portion101eof the surface101of the substrate10. In some embodiments, the edge portion101eof the surface101includes the peripheral region101p. In some embodiments, the peripheral region101p(which is within the edge portion101e) of the surface101of the substrate10is exposed from the support structure30. In some embodiments, the edge portion101eof the surface101of the substrate10surrounds the support structure30. In some embodiments, the portion22of the conductive element20surrounds the support structure30. In some embodiments, the portion22of the conductive element20surrounds the peripheral region101pof the surface101of the substrate10. In some embodiments, the peripheral region101pof the surface101of the substrate10surrounds the support structure30. FIG.2Aillustrates a cross-sectional view of a portion of an electronic package structure1in accordance with some embodiments of the present disclosure. In some embodiments,FIG.2Aillustrates a cross-sectional view of the structure in the dashed box1A ofFIG.1. In some embodiments, the conductive element20further covers (or partially covers) the edge portion101eof the surface101of the substrate10. In some embodiments, the portion22of the conductive element20is on the edge portion101eof the surface101of the substrate10. In some embodiments, the portion22of the conductive element20is connected to the portion21of the conductive element20on the lateral surface103of the substrate10. In some embodiments, a thickness T2cof the portion22of the conductive element20is less than the thickness T2bof the portion21of the conductive element20. In some embodiments, the portion22of the conductive element20is disposed in the recess R1. In some embodiments, the lateral surface303of the support structure30is spaced apart from the portion22of the conductive element20by a distance D2, and the distance D2is less than the distance D1. In some embodiments, the portion101pof the surface101of the substrate10is exposed from a space between the lateral surface303of the support structure30and the portion22of the conductive element20. In some embodiments, the support structure30includes a portion30A immediately adjacent to the lateral surface103of the substrate10. In some embodiments, the recess R1is spaced apart from the opening310by the portion30A of the support structure30. In some embodiments, the recess R1is spaced apart from the electrical contact40by the portion30A of the support structure30. FIG.2Billustrates a cross-sectional view of a portion of an electronic package structure1in accordance with some embodiments of the present disclosure. In some embodiments,FIG.2Billustrates a cross-sectional view of the structure in the dashed box1A ofFIG.1. In some embodiments, the portion30A of the support structure30has a lateral surface303with a non-vertical or a curved profile. In some embodiments, the portion30A of the support structure30has a surface301(also referred to as “a bottom surface”) with a non-vertical or a rounded profile. In some embodiments, a portion of the lateral surface303and a portion of the surface301form a curved edge30E of the portion30A of the support structure30. FIG.2Cillustrates a cross-sectional view of a portion of an electronic package structure1in accordance with some embodiments of the present disclosure. In some embodiments,FIG.2Cillustrates a cross-sectional view of the structure in the dashed box1C ofFIG.1. In some embodiments, the support structure30further includes a portion30B in contact with the electrical contact40. In some embodiments, the portion30B is embedded in the electrical contact40. In some embodiments, a portion40pof the electrical contact40is between the conductive pad110and the portion30B of the support structure30. In some embodiments, a surface40p1and a surface40p2of the portion40pof the electrical contact40define an acute angle. In some embodiments, the conductive pad110has a thickness T3from about 10 μm to about 30 μm. In some embodiments, the portion30B of the support structure30over the conductive pad110has a thickness T1afrom about 10 μm to about 30 μm. FIG.3illustrates a cross-sectional view of an electronic package structure in accordance with some embodiments of the present disclosure. The electronic package structure2is similar to the electronic package structure1inFIG.1, and the differences therebetween are described as follows. In some embodiments, the electronic package structure2further includes a protection layer50between the support structure30and the surface101of the substrate10. In some embodiments, the protection layer50defines or has a plurality of openings510, and the electrical contacts40are disposed within the openings510of the protection layer50. In some embodiments, the protection layer50includes a patterned solder mask. In some embodiments, the conductive element20further covers a portion of the protection layer50. In some embodiments, the conductive element20further covers a lateral surface503of the protection layer50. In some embodiments, the lateral surface303of the support structure30is spaced apart from the lateral surface503of the protection layer50by the distance D1. In some embodiments, the lateral surface303of the support structure30and an edge portion501eof a surface501(also referred to as “a bottom surface”) of the protection layer50exposed from the support structure30define the recess R1. In some embodiments, the edge portion501eof the surface501is connected to the lateral surface503of the protection layer50. FIG.3Aillustrates a top view of an electronic package structure2in accordance with some embodiments of the present disclosure. In some embodiments,FIG.3Aillustrates a bottom view of the electronic package structure2as viewed from the surface101of the substrate10. In some embodiments,FIG.3illustrates a cross-sectional view along the cross-sectional line3-3′ inFIG.3A. In some embodiments, the portion22of the conductive element20partially covers the edge portion501eof the surface501of the protection layer50. In some embodiments, a peripheral region501pof the surface501of the protection layer50is exposed from the portion22of the conductive element20. In some embodiments, the peripheral region501pis within the edge portion501eof the surface501of the protection layer50. In some embodiments, the peripheral region501p(which is within the edge portion501e) of the surface501of the protection layer50is exposed from the support structure30. In some embodiments, the peripheral region501pof the surface501of the protection layer50is exposed from a space between the lateral surface303of the support structure30and the conductive element20. In some embodiments, the edge portion501eof the surface501of the protection layer50surrounds the support structure30. In some embodiments, the peripheral region501pof the surface501of the protection layer50surrounds the support structure30. FIG.4Aillustrates a cross-sectional view of a portion of an electronic package structure2in accordance with some embodiments of the present disclosure. In some embodiments,FIG.4Aillustrates a cross-sectional view of the structure in the dashed box4A ofFIG.3. In some embodiments, the conductive element20further covers (or partially covers) the edge portion501eof the surface501of the protection layer50. In some embodiments, the portion22of the conductive element20is on the edge portion501eof the surface501of the protection layer50. In some embodiments, the portion22of the conductive element20is connected to the portion21of the conductive element20on the lateral surface503of the protection layer50. In some embodiments, the portion22of the conductive element20is in the recess R1defined by the protection layer50and the support structure30. In some embodiments, the support structure30is immediately adjacent to the lateral surface503of the protection layer50. In some embodiments, the recess R1is spaced apart from the opening510by the support structure30. In some embodiments, the recess R1is spaced apart from the electrical contact40by the support structure30. In some embodiments, the electrical contact40directly or physically contacts the support structure30and the protection layer50. FIG.4Billustrates a cross-sectional view of a portion of an electronic package structure2in accordance with some embodiments of the present disclosure. In some embodiments,FIG.4Billustrates a cross-sectional view of the structure in the dashed box4A ofFIG.3. In some embodiments, the support structure30has a lateral surface303with a non-vertical or a rounded profile. In some embodiments, the support structure30further has a lateral surface303′ opposite to the lateral surface303, and the lateral surface303′ has a non-vertical or a rounded profile. In some embodiments, the lateral surface303′ directly or physically contacts the electrical contact40. In some embodiments, a portion of the lateral surface303and a portion of the surface301form a curved edge30E of the support structure30. In some embodiments, a portion of the lateral surface303′ and a portion of the surface301form a curved edge30E′ of the support structure30. In some embodiments, the cured edge30E′ of the support structure30directly or physically contacts the electrical contact40. FIG.5A,FIG.5B,FIG.5C, FIG.5C1, FIG.5C2,FIG.5D, FIG.5D1,FIG.5E, FIG.5E1,FIG.5F, andFIG.5Gillustrate various operations in a method of manufacturing an electronic package structure1in accordance with some embodiments of the present disclosure. Referring toFIG.5A, a substrate layer10A may be provided. In some embodiments, the substrate layer10A has at least two device regions10R1and10R2and a predetermined cutting line region S1between the device region10R1and the device region10R2. In some embodiments, the substrate layer10A has a surface101and a surface102opposite to the surface101. In some embodiments, the substrate layer10A includes a core layer11, dielectric layers13and15on opposite surfaces11aand11bof the core layer11, at least one interconnection via17passing through the core layer11, at least one conductive via12passing through the dielectric layer13, at least one conductive via14passing through the dielectric layer15, at least one conductive layer16connected to the conductive via12, at least one conductive layer18connected to the conductive via14, one or more conductive pads110exposed at the surface101of the substrate10, and one or more conductive pads112exposed at the surface102of the substrate10. Referring toFIG.5B, an insulating layer300may be formed on the surface101of the substrate10. In some embodiments, the insulating layer300is formed on the device regions10R1and10R2and the predetermined cutting line region S1of the substrate10. In some embodiments, an insulating layer700is formed on the surface102of the substrate10. In some embodiments, the insulating layers300and700may include the same or different materials. In some embodiments, the insulating layers300and700include a solder resist material. Referring toFIG.5C, a portion (also referred to as “a first portion”) of the insulating layer300may be removed to expose the predetermined cutting line region S1of the substrate layer10A to form a support structure30on the surface101of the substrate layer10A. In some embodiments, a portion (or a first portion) of the insulating layer300is removed to form an opening320to expose the predetermined cutting line region S1of the substrate layer10A. In some embodiments, still referring toFIG.5C, another portion (also referred to as “a second portion”) of the insulating layer300is further removed to form openings310to expose the conductive pads110of the substrate10. In some embodiments, removing the first portion of the insulating layer300to expose the predetermined cutting line region S1and removing the second portion of the insulating layer300to form the openings310are performed in the same operation. In some embodiments, a portion of the insulating layer700is removed to form openings710to expose the conductive pads120of the substrate layer10A, so as to form a protection layer70. Referring to FIG.5C1, which illustrates a cross-sectional view of the structure in the dashed box5C1ofFIG.5Cin accordance with some embodiments of the present disclosure, a portion of the surface101of the substrate layer10A corresponding to the predetermined cutting line region S1may be exposed from the support structure30(e.g., the opening320of the support structure30). In some embodiments, a width W1of the opening320of the support structure30is greater than a width W2of the predetermined cutting line region S1. In some embodiments, a portion of the surface102of the substrate layer10A corresponding to the predetermined cutting line region S1is covered by the protection layer70. Referring to FIG.5C2, which illustrates a top view of the structure shown inFIG.5Cas viewed from the surface101of the substrate layer10A in accordance with some embodiments of the present disclosure, the predetermined cutting line region S1of the surface101may be exposed from the support structure30. In some embodiments, the conductive pads110may be exposed from the openings310of the support structure30. In some embodiments, the support structure30may be formed by a lithography operation, a screen printing operation, an inkjet printing operation, or a combination thereof. For example, in the embodiments illustrated inFIGS.5B-5C2, the support structure30is formed by a lithography operation. In some other embodiments, the support structure30may be formed by a mask-less operation (e.g., a screen printing operation or an inkjet printing operation). For example, referring toFIG.5A, forming the support structure30may include applying an insulating material on the device regions10R1and10R2of the substrate layer10A with a predetermined pattern to form the support structure30. In some embodiments, the insulating material is applied on the device regions10R1and10R2of the surface101of the substrate layer10A with the predetermined pattern. In some embodiments, the predetermined pattern of the insulating material exposes the predetermined cutting line region S1of the substrate layer10A. Referring toFIG.5D, electronic components51and52may be disposed over the surface102of the substrate layer10A, an encapsulant60may be disposed over the surface102of the substrate layer10A to encapsulate the electronic components51and52, electrical contacts40may be disposed on the surface101of the substrate layer10A, and a singulation operation may be performed along the predetermined cutting line region S1. In some embodiments, forming the support structure30is prior to performing the singulation operation. In some embodiments, referring to FIG.5D1, which illustrates a cross-sectional view of the structure in the dashed box5D1ofFIG.5Din accordance with some embodiments of the present disclosure, each of the singulated structures1A includes a substrate10having the surface101, the surface102opposite to the surface101, and a lateral surface103angled with the surface101, and a lateral surface303of the support structure30is spaced apart from the lateral surface103of the substrate10by a distance D1. In some embodiments, the distance D1in defined by the width W1of the opening320and the width W2of the predetermined cutting line region S1. In some embodiments, the lateral surface303recessed from the lateral surface103defines a recess R1. In some embodiments, the lateral surface303of the support structure30and an edge portion101eof the surface101of the substrate define the recess R1. Referring toFIG.5Eand FIG.5E1, which illustrates a cross-sectional view of the structure in the dashed box5E1ofFIG.5Ein accordance with some embodiments of the present disclosure, the singulated structure1A may be disposed on a carrier800. In some embodiments, the carrier800may be a tape. In some embodiments, the support structure30contacts an upper surface801of the carrier800. In some embodiments, the upper surface801of the carrier800, the lateral surface303of the support structure30, and the edge portion101eof the surface101of the substrate10define the recess R1. In some embodiments, the thickness T1of the support structure30defines the height of the recess R1. Referring toFIG.5F, a conductive element20may be formed over the substrate10. In some embodiments, forming the conductive element20is after performing the singulation operation. In some embodiments, forming the conductive element20includes performing a physical vapor deposition (PVD) operation with a conductive material20A over the substrate10. In some embodiments, the PVD operation is performed along a direction DR1from the surface102towards the surface101of the substrate10. That is, in some embodiments, atoms of the conductive material20A move along the direction DR1(e.g., the direction of the electric field in the PVD operation) substantially in parallel to the lateral surface103of the substrate10. In some embodiments, atoms of the conductive material20A move along the direction DR1towards the surfaces602and603of the encapsulant60, the lateral surface103of the substrate10, and the upper surface801of the carrier800. In some embodiments, the conductive material20A is formed on the surfaces602and603of the encapsulant60, the lateral surface103of the substrate10, and the upper surface801of the carrier800by PVD. Referring toFIG.5G, the conductive element20may be formed on the surfaces602and603of the encapsulant60and the lateral surface103of the substrate10. A layer of the conductive material20A may be formed on the upper surface801of the carrier800. In some embodiments, the conductive element20is spaced apart from the layer of the conductive material20A on the carrier800. Next, the carrier800may be removed. As such, the electronic package structure1illustrated inFIG.1is formed. According to some embodiments of the present disclosure, the arrangement of the lateral surface103of the substrate10and the lateral surface303of the support structure30(e.g., the recess R1) can produce a discontinuous deposition surface for the PVD operation, and thus it can prevent the conductive material20A from forming a continuous layer along the lateral surface103of the substrate10towards the upper surface801of the carrier800. In other words, the portion of the conductive material20A on the lateral surface103of the substrate10is spaced apart from the portion of the conductive material20A on the upper surface801of the carrier800because of lacking of a continuous deposition surface. Therefore, it can prevent the formation of metal burrs which could have been formed by pulling off a continuous layer of the conductive material20A when detaching the singulated structure1A from the carrier800. Accordingly, the prevention of formation of metal burrs can reduce the probability of occurrences of short circuits, which can increase the yields of the electronic package structure1. In addition, according to some embodiments of the present disclosure, atoms of the conductive material20A move along the direction DR1(which is the direction of the electric field in the PVD operation) substantially in parallel to the lateral surface103of the substrate10. Therefore, since the PVD operation is highly directional, the probability of the atoms entering the recess R1which is recessed from the lateral surface103of the substrate10can be significantly reduced. Accordingly, the design of the recess R1can prevent the conductive material20A from forming a continuous layer along the lateral surface103of the substrate10towards the upper surface801of the carrier800, the formation of metal burrs can be reduced, and thus the probability of occurrences of short circuits can be reduced, which can increase the yields of the electronic package structure1. Moreover, according to some embodiments of the present disclosure, the formation of the openings310and320of the support structure30can be performed in the same operation. In other words, the openings310for the electrical contacts40and the opening320for forming the recess R1which benefits the prevention of metal burrs can be formed in the same operation. Therefore, additional operations are not required, and thus the process can be simplified. Furthermore, compared to the cases when a substrate has a recess proximal to a bottom surface and a lateral surface of the substrate, the formation of a recess of a substrate requires a mechanical pre-cutting operation followed by a singulation, and thus the formation of a recess of a substrate requires additional manufacturing operations, not to mention that the relatively low precision provided by the mechanical pre-cutting operation, which may decrease the effects of preventing the formation of metal burrs as well as the yields of the electronic package structure. In contrast, according to some embodiments of the present disclosure, the recess R1is defined by the support structure30and the substrate10. Since the support structure30may be formed by a lithography operation, a screen printing operation, an inkjet printing operation, or a combination thereof, the recess R1can be formed of a relatively high precision and having a relatively refined structure, the formation of cutting burrs can be avoided, and thus the yields of the electronic package structure1can be increased. FIG.6A,FIG.6B, andFIG.6Cillustrate various operations in a method of manufacturing an electronic package structure2in accordance with some embodiments of the present disclosure. Referring toFIG.6A, a protection layer50may be formed on the surface101of the substrate layer10A. In some embodiments, operations similar to those illustrated inFIGS.5A-5Cfor forming the protection layer70are performed to form the protection layer50on the surface101of the substrate layer10A. In some embodiments, operations similar to those illustrated inFIGS.5A-5Cfor forming the protection layer70are performed to form a protection layer70on the surface102of the substrate layer10A. In some embodiments, a portion of the surface101of the substrate layer10A corresponding to the predetermined cutting line region S1is covered by the protection layer50. In some embodiments, a portion of the surface102of the substrate layer10A corresponding to the predetermined cutting line region S1is covered by the protection layer70. Referring toFIG.6B, an insulating layer300may be formed on the protection layer50. In some embodiments, the insulating layer300is filled in the openings510of the protection layer50. Referring toFIG.6C, a portion of the insulating layer300may be removed to expose a portion of the protection layer50to form the support structure30. In some embodiments, the openings510of the protection layer50are exposed from the support structure30. In some embodiments, the protection layer50is formed prior to forming the support structure30. In some embodiments, a portion of the protection layer50corresponding to the predetermined cutting line region S1is exposed from the support structure30. Next, operations similar to those illustrated inFIG.5Dmay be performed to dispose electronic components51and52over the surface102of the substrate layer10A, dispose an encapsulant60over the surface102of the substrate layer10A to encapsulate the electronic components51and52, dispose electrical contacts40on the surface101of the substrate layer10A, and perform a singulation operation along the predetermined cutting line region S1. Next, operations similar to those illustrated inFIGS.5E-5Gmay be performed to form a conductive element20on the surfaces602and603of the encapsulant60and the lateral surface103of the substrate10. As such, the electronic package structure2illustrated inFIG.3is formed. As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of said numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” or “about” the same if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature. As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component. While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent components may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and the like. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure. | 41,708 |
11862551 | DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS The detailed features and advantages of the disclosure are described in detail in the following embodiments. The content is sufficient for persons skilled in the art to understand the technical content of the disclosure to be implemented accordingly. Also, according to the content, claims, and drawings disclosed in the specification, persons skilled in the art may easily understand the relevant objectives and advantages of the disclosure. The following embodiments further illustrate in detail the viewpoints of the disclosure, but do not limit the scope of the disclosure by any viewpoint. The element sizes in the drawings in the specification are drawn for convenience of description and do not represent the actual ratios of the element sizes. In the description of the following embodiments, it should be understood that when it is pointed out that a layer (or film) or a structure is disposed “on” or “under” another substrate, another layer (or film), or another structure, the former may be “directly” located on the another substrate, the another layer (or film), or the another structure, or there may be more than one intermediate layer between the two, which are disposed in an “indirect” manner. In the detailed description of each embodiment, terms such as “first”, “second”, and “third” may be used to describe different elements. The terms are only used to distinguish between the elements, but in terms of structure, the elements should not be limited by the terms. For example, a first element may be referred to as a second element, and similarly, the second element may be referred to as the first element without departing from the protection scope of the disclosure. In addition, in a manufacturing method, in addition to a specific manufacturing process, the order of forming the elements or components should also not be limited by the terms. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Alternatively, the first element and the second element may be formed in the same manufacturing process or step. FIG.1Ais a partial cross-sectional schematic view of an interposer according to an embodiment of the disclosure.FIG.1Bis a partial top schematic view ofFIG.1A. Please refer toFIG.1AandFIG.1B. In the embodiment, an interposer100includes a redistribution layer (RDL) structure110, multiple first conductive terminals120, and multiple second conductive terminals130, wherein the redistribution layer structure110includes a circuit range outline112(as shown inFIG.1B) and has a first surface110aand a second surface110bopposite to the first surface110a. Furthermore, the first conductive terminals120are disposed on the first surface110a, and the second conductive terminals130are disposed on the second surface110b. An orthographic projection area of the first conductive terminals120on the redistribution layer structure110is inside the circuit range outline112, an orthographic projection area of a first part of the second conductive terminals130on the redistribution layer structure110is inside the circuit range outline112, and an orthographic projection area of a second part of the second conductive terminals130on the redistribution layer structure110is outside the circuit range outline112, as shown inFIG.1B. In addition, the first conductive terminals120are electrically connected to the second conductive terminals130. There is a first pitch122between the adjacent first conductive terminals120, there is a second pitch132between the adjacent second conductive terminals130, and the second pitch132is greater than the first pitch122, as shown inFIG.1A. Therefore, the first conductive terminals120may be configured to be bonded with a component with a fine pitch, and the second conductive terminals130may be configured to be bonded with a component with a thick pitch. Here, the fine pitch is, for example, less than 135 microns, and the thick pitch is, for example, greater than 150 microns, but the disclosure is not limited thereto. The fine pitch and the thick pitch may be determined according to actual design requirements. Accordingly, with the pitch design of the interposer100and the layout of the circuit range outline, the second pitch132between the adjacent second conductive terminals130on the second surface110bof the redistribution layer structure110in the interposer100is greater than the first pitch122between the adjacent first conductive terminals120on the first surface110aof the redistribution layer structure110in the interposer100. In this way, the interposer110may be used in a subsequent package structure to become a pitch converting medium between the semiconductor chip and the package substrate, so as to improve the issue of pitch mismatch in the subsequent package structure. Here, the pitch may be defined as a distance between center points of adjacent conductive terminals, and the pitch may be the smallest pitch between the adjacent conductive terminals. For example, as shown inFIG.1B, the first pitch122is the smallest pitch between the adjacent first conductive terminals120, the second pitch132is the smallest pitch between the adjacent second conductive terminals130, a third pitch124is another pitch (greater than the first pitch122) between the adjacent first conductive terminals120, and a fourth pitch134is another pitch (greater than the second pitch132) between the adjacent second conductive terminals130, but the disclosure is not limited thereto. In addition, the implementation of the semiconductor package will be further described inFIG.2below. In some embodiments, the orthographic projection area of the first conductive terminals120on the redistribution layer structure110being inside the circuit range outline112may be that center points120P of the first conductive terminals120are all inside the circuit range outline112, but the disclosure is not limited thereto. In some embodiments, in order to reduce the presence of blank regions on the redistribution layer structure110, improve space utilization, and reduce manufacturing costs, the circuit range outline112includes a first direction D1and a second direction D2perpendicular to each other, and the second part of the second conductive terminals130is outside the circuit range outline112in the first direction D1or the second direction D2, that is, a center point130P of the second part of the second conductive terminals130is outside the circuit range outline112in the first direction D1or the second direction D2, but the disclosure is not limited thereto. It should be noted that the redistribution layer structure110may include multiple other circuit range outlines (not shown) similar to the circuit range outline112, and the circuit range outline112and the other circuit range outlines may be connected in series, so as to improve the flexibility of circuit layout. In some embodiments, the first conductive terminals120are in the form of micro bumps, so the first conductive terminals120may be bonded with a chip with micro bumps, and the second conductive terminals130are in the form of C4 bumps, so the second conductive terminals130may be bonded with a package substrate with C4 bumps, but the disclosure is not limited thereto. In the embodiment, the first conductive terminals120may be electrically connected to the second conductive terminals130by a conductive pattern in the redistribution layer structure110(as shown by oblique line parts of the redistribution layer structure110inFIG.1A). For example, the redistribution layer structure110is formed with a semiconductor material as a base, and the redistribution layer structure110may include the conductive pattern (as shown by the oblique line parts of the redistribution layer structure110inFIG.1A) and a base part (as shown by blank parts of the redistribution layer structure110inFIG.1A, wherein the semiconductor material may include silicon, and the material of the conductive pattern may include copper, gold, nickel, aluminum, platinum, tin, a combination thereof, an alloy thereof, or other suitable conductive materials, but the disclosure is not limited thereto. In an embodiment not shown, the redistribution layer structure110is formed with an organic material as the base. For example, the redistribution layer structure110may include the conductive pattern and a dielectric layer, wherein the material of the dielectric layer may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other suitable organic dielectric materials, and the material of the conductive pattern may include copper, gold, nickel, aluminum, platinum, tin, a combination thereof, an alloy thereof, or other suitable conductive materials, but the disclosure is not limited thereto. It should be noted that the disclosure does not limit the implementation of the redistribution layer structure110, as long as the first conductive terminals120may be electrically connected to the second conductive terminals130by the redistribution layer structure110, the redistribution layer structure110belongs to the protection scope of the disclosure. In addition, the conductive pattern of the redistribution layer structure110inFIG.1Ais only schematically drawn and is not an actual electrical connection manner of the disclosure. The actual electrical connection manner of the disclosure may be determined according to design requirements. It must be noted here that the following embodiment continues to use the reference numerals and some content of the above embodiment, wherein the same or similar reference numerals are adopted to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the above embodiment, which will not be repeated in the following embodiment. FIG.2is a partial cross-sectional schematic view of a semiconductor package according to an embodiment of the disclosure. Please refer toFIG.2. A semiconductor package10of the embodiment may be a chip on wafer on substrate (CoWoS), but the disclosure is not limited thereto. In an embodiment not shown, the semiconductor package may also be an integrated fan-out (InFO) package. In the embodiment, the semiconductor package10includes a package substrate12, an interposer100, and at least one chip14(schematically shown as three). Here, the package substrate12may be a printed circuit board (PCB) or other suitable substrate types, and the chip14may be a system on chip (SoC) or other suitable chip types, which are not limited in the disclosure. Furthermore, the package substrate12has a bearing surface12a. The interposer100is disposed on the bearing surface12awith the second surface110bfacing the package substrate12. The chip14is disposed on the first surface110awith an active surface14a, and multiple chips14may be arranged side by side on the interposer100. In addition, the chip14is electrically connected to the package substrate12by the interposer100. Accordingly, the embodiment enables the second pitch132between the adjacent second conductive terminals130(close to the package substrate12) on the second surface110bof the redistribution layer structure110in the interposer100to be greater than the first pitch122between the adjacent first conductive terminals120(close to the chip14) on the first surface110aof the redistribution layer structure110in the interposer100by the pitch design of the interposer100and the layout of the circuit range outline. In this way, the issue of mismatch between the chip14and the package substrate12may be improved through converting the pitch of the redistribution layer structure110. Contact points with fine pitch configuration on the chip14may be converted to contact points with thick pitch configuration on the package substrate12, so that a signal of the semiconductor package10can be effectively transmitted. Here, the circuit range outline112on the redistribution layer structure110shown inFIG.1Bmay correspond to an element functional block (IP macro) range on the chip14, that is, multiple element functional block ranges on the chip14may respectively correspond to multiple circuit range outlines112, but the disclosure is not limited thereto. In some embodiments, since a high-speed signal transmission chip end has higher requirements for input/output terminals to transmit more signals, but requirements for a ground signal, etc. at a package substrate end are still limited by the manufacturing process, the semiconductor package10of the embodiment may be used for high-speed signal transmission, and the design of the interposer100enables the semiconductor package to meet different requirements at the two ends at the same time, but the disclosure is not limited thereto. Here, the first conductive terminals120and the second conductive terminals130in the interposer100may be designed into any suitable terminals, such as power ground terminals, according to actual design requirements, and the number ratio may also be adjusted according to actual design requirements. In some embodiments, multiple third conductive terminals16may be optionally disposed on the surface of the package substrate12opposite to the interposer100, so that the semiconductor package10may be further connected to other components, but the disclosure is not limited thereto. In summary, the embodiment enables the second pitch between the adjacent second conductive terminals (close to the package substrate) on the second surface of the redistribution layer structure in the interposer to be greater than the first pitch between the adjacent first conductive terminals (close to the chip) on the first surface of the redistribution layer structure in the interposer by the pitch design of the interposer and the layout of the circuit range outline. In this way, the issue of mismatch between the chip and the package substrate may be improved through converting the pitch of the redistribution layer structure. Contact points with fine pitch configuration on the chip may be converted to contact points with thick pitch configuration on the package substrate, so that the signal of the semiconductor package can be effectively transmitted. Although the disclosure has been disclosed in the above embodiments, the embodiments are not intended to limit the disclosure. Persons skilled in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. The protection scope of the disclosure shall be defined by the appended claims. | 14,685 |
11862552 | DETAILED DESCRIPTION One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents. In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. Embodiments of methods of forming embedded inductor structures comprising selectively located magnetic material, are described herein. In embodiments, the embedded inductor structures may be formed by using magnetic materials and their alloys, that may be selectively formed within particular locations of microelectronic package structures. The selective formation of magnetic material may be incorporated within both cored and coreless packages. The magnetic material of the embedded inductor structures of the embodiments herein may be selectively formed around and disposed on various conductive structures, such as via and pad structures for example. Methods of forming magnetic material for embedded inductor structure fabrication described herein may include forming a cavity and utilizing stencil printing processing to form a magnetic material, such as a magnetic paste, within selective locations of a package substrate/structure. Other methods may include selectively forming a magnetic paste in desired locations within a package build up layer, and then grinding the dielectric build up material to further pattern an inductor structure. Another embodiment includes utilizing a plasma etching process to pattern the embedded magnetic material. Various implementations of the embodiments herein may be formed or carried out on a substrate, such as a package substrate. A package substrate may comprise any suitable type of substrate capable of providing electrical communications between a die, such as an integrated circuit (IC) die, and a next-level component to which an microelectronic package may be coupled (e.g., a circuit board). In another embodiment, the substrate may comprise any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled with a lower IC/die package, and in a further embodiment a substrate may comprise any suitable type of substrate capable of providing electrical communication between an upper IC package and a next-level component to which an IC package is coupled. FIG.1is a cross-sectional view of a package structure100, wherein the package structure100may include a portion of a microelectronic package, and may include an embedded package inductor structure. The embedded inductor structure includes a magnetic material110, that has been selectively formed, and is embedded within a substrate102of the package structure100, the fabrication process of said embedded inductor to be described further herein. The substrate102may comprise a portion of a package substrate102, in an embodiment. The substrate102may comprise a coreless substrate, in an embodiment, and in other embodiments, may comprise a cored substrate. By way of example, in one embodiment, the substrate102may comprise a multi-layer substrate—including alternating layers of a dielectric/electrically insulating material101and conductive interconnect structures106,107, wherein the interconnect structures107may comprise a via, in an embodiment, and wherein interconnect structure106may comprise a pad, in an embodiment. The electrically insulating material may comprise such materials as an epoxy laminate, in an embodiment. For example, the substrate102may include electrically insulating layers composed of materials such as, phenolic cotton paper materials (e.g., FR-1), cotton paper and epoxy materials (e.g., FR-3), woven glass materials that are laminated together using an epoxy resin (FR-4), glass/paper with epoxy resin (e.g., CEM-1), glass composite with epoxy resin, woven glass cloth with polytetrafluoroethylene (e.g., PTFE CCL), or other polytetrafluoroethylene-based prepreg material. Other types of substrates and substrate materials may also find use with the disclosed embodiments (e.g., ceramics, sapphire, glass, etc.). Further, according to one embodiment, a substrate may comprise alternating layers of dielectric material and metal that are built-up over a die itself—this process is sometimes referred to as a “bumpless build-up process.” Where such an approach is utilized, conductive interconnects may or may not be needed (as the build-up layers may be disposed directly over a die, in some cases). The substrate102may provide structural support for a die/device, such as device130, for example. Solder structures120may be disposed on a first surface103and/or a second surface105of the substrate102, and may be disposed adjacent a solder resist material113, in an embodiment. The solder structures120may be electrically coupled to the die130and/or a PCB/motherboard, in an embodiment. In an embodiment, the die130, may be electrically and physically coupled to the package substrate102through the solder structures120. The die/device130may comprise any type of integrated circuit device. In one embodiment, the die130may include a processing system (either single core or multi-core). For example, the die130may comprise a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, etc. In one embodiment, the die130may comprise a system-on-chip (SoC) having multiple functional units (e.g., one or more processing units, one or more graphics units, one or more communications units, one or more signal processing units, one or more security units, etc.). However, it should be understood that the disclosed embodiments are not limited to any particular type or class of devices/die. In an embodiment, the substrate may comprise any number of die coupled thereto. Conductive interconnect structures may be disposed on a side(s) of the die/device130(not shown) and may comprise any type of structure and materials capable of providing electrical communication between a die/device and a substrate, or another die/device, for example. In an embodiment, conductive interconnect structures may comprise an electrically conductive terminal on a die (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures) and a corresponding electrically conductive terminal on a substrate (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures). Solder structures120(e.g., in the form of balls or bumps) may be disposed on the terminals109of the substrate102and/or die/device, and these terminals may then be joined using a solder reflow process. Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wirebonds extending between a die and a substrate). The terminals on the die130may comprise any suitable material or any suitable combination of materials, whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds. For example, the terminals on the die may include copper, aluminum, gold, silver, nickel, titanium, tungsten, as well as any combination of these and/or other metals. In other embodiments, a terminal may comprise one or more non-metallic materials (e.g., a conductive polymer). The terminals109on a surface of the substrate102may also comprise any suitable material or any suitable combination of materials, whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds. A surface finish111, may be disposed on terminals/copper pads109on a surface of conductive structure106, in an embodiment, wherein the surface finish111may comprise such materials as an electroplated nickel/gold (ENIG) finish, and other similar finish materials. The conductive interconnect structures106,107may be disposed within dielectric portions101of the substrate102in any pattern as required by the particular application, according to embodiments. Any number of build-up layers may be disposed within the substrate102, wherein the conductive interconnect structures106,107may comprise via structures, such as microvias, for example within build up layers. The substrate102may comprise any number of dielectric layers101, which may include any number of conductive interconnect structures106,107as appropriate for a particular application. Individual ones of the conductive interconnect structures106,107may comprise traces, trenches, routing layers, ground planes, power planes, re-distribution layers (RDLs), and/or any other appropriate electrical routing features. Although specific patterns of the conductive interconnect structures106,107are illustrated inFIG.1, such patterns are merely exemplary, and may vary according to the particular application. The magnetic material110may comprise a portion of an embedded inductor structure, wherein conductive material may be patterned around the magnetic material to form embedded inductor structures of any desired geometry, which will be described further herein. In an embodiment, the magnetic material110incorporated in the embedded inductor structure may comprise at least a portion of a power distribution system that may supply power to the die130and/or to other components, devices, or systems coupled to the substrate102/package structure100. For example, an embedded magnetic inductor incorporating the magnetic material110may form a portion of a voltage regulator coupled to a power supply for the die130. Integrating the embedded magnetic inductor structures into the semiconductor substrate102may eliminate the need for an external inductor. The magnetic material110, may comprise a magnetic film, and in other embodiments, may comprise a magnetic paste and/or a magnetic ink. The magnetic material110may include one or more metallic magnetic materials or one or more soft ferrite magnetic materials. Example metallic magnetic materials include, but are not limited to: iron (Fe); oriented iron silicide (FeSi); unoriented iron silicide (FeSi); iron-nickel (FeNi) and iron nickel containing alloys; iron-cobalt (FeCo) and iron-cobalt containing alloys; FeSiBNbCu and FeSiBNbCu containing alloys; and CoZrTa and CoZrTa containing alloys. Example soft ferrite magnetic materials include, but are not limited to: manganese-zinc ferrite (MnZn); nickel-zinc ferrite (NiZn); and ferric oxide (Fe2O3). Soft ferrites have a relatively low coercivity which permits the magnetic field produced by a soft ferrite to easily reverse without hysteresis losses (i.e., energy dissipation). The relatively low losses of soft ferrite materials at high frequencies provides an advantage in both radio frequency (RF) applications and switched-mode power supplies. In an embodiment, the magnetic paste and/or magnetic ink may comprise a carrier material, which may comprise one or more of thermosetting resins, such as epoxies; inter-penetrating polymer networks; liquid crystalline polymers (LCP); fluoropolymers, such as polytetrafluoroethylene (PTFE); and silicones. In one embodiment, the carrier that may be included in the magnetic material110may include bis-benzocyclobutene (BCB, for example bis-benzocyclobutene offered under the commercial name CYCLOTENE™ 3022 by Dow Chemical Co., MIDLAND, MI). In some embodiments, a liquid crystalline polymer may include one or more polymers dissolved in one or more solvents (e.g., lyotropic liquid-crystal polymers). In some embodiments, a liquid crystalline polymer may include one or more polymers or polymer mixtures heated above its glass or melting transition point (e.g., thermotropic liquid-crystal polymers). The magnetic material110may be applied, deposited, or otherwise formed using any number and/or combination of currently available and/or future developed liquid application techniques including spray deposition, spin coating, printing, and similar. In an embodiment, the magnetic material110may be disposed on surfaces, and in some embodiment, directly disposed on surfaces of the interconnect structures106,107. For example, a magnetic material110may be disposed on conductive structures106,107, and may be embedded within the substrate102, and may be disposed on the dielectric material101of the package substrate102, and may not be disposed on the first surfaces103, nor on the second surface105of the substrate102. That is, the magnetic material110may be completely embedded within the substrate102. The magnetic material110may comprise a selectively formed magnetic material, which may be formed according to particular design requirements in any suitable location/locations within the substrate102, as will be further described herein. In some embodiments, the magnetic material110may be formed on a conductive seed layer (not shown), such as on a copper seed layer, for example. The seed layer may be disposed between the conductive interconnect structures106,107and the magnetic material110, in an embodiment. The seed layer may comprise a thickness of about 50 nm to about 5 microns, and may be formed by an electroplating process, in an embodiment. In other embodiments, the seed layer may be formed by any suitable formation process, such as by a physical vapor deposition process, for example. The seed layer may comprise such materials as copper, titanium and/or nickel, for example. The magnetic material110may comprise such materials as iron, nickel, cobalt, molybdenum, and combinations thereof, in an embodiment. The magnetic material110may comprise magnetic materials possessing a high permeability and a low coercivity, and may comprise those materials that are suitable for use as an efficient in-package/embedded inductor, to be described further herein. In some embodiments, the magnetic material110may comprise a permeability of between about 2 and about 50, and in other embodiments, the permeability may be greater than about 2. In some embodiments, the magnetic material110may comprise a thickness of between about 10 microns to about 1000 microns, but in other embodiments the magnetic material110thickness may vary according to the particular application. In an embodiment, the magnetic material110may optionally include conductive structures, such as rectangular copper structures125disposed within the magnetic material110and adjacent the dielectric material101. FIGS.2a-2mdepict embodiments of forming an embedded magnetic inductor structure, wherein the magnetic material may be formed in a cavity within a dielectric material, for example.FIG.2adepicts a cross sectional view of a portion of a package structure200, wherein a core221, may comprise conductive interconnect structures, such as pads206disposed on surfaces, such as a first surface203, and on a second surface205of the core221. A plated through hole204, may extend through the core221, in an embodiment. The core221may comprise an organic core, in an embodiment, and may comprise any suitable organic materials, in an embodiment, and may comprise other suitable materials, such as ceramic and/or glass. In other embodiments, the package structure200may comprise a coreless package structure200. In an embodiment, build up layers may subsequently be formed on the surfaces203,205of the core. The package structure200may be a portion of a PCB, an interposer, or the like. In some exemplary embodiments, the package structure200may comprise a PCB in a multi-level board including a plurality of conductive trace levels laminated with glass-reinforced epoxy sheets (e.g., FR-4). InFIGS.2b-2c, build up layers211may be formed on the surfaces203,205of the core221, to build up a substrate202such as a package substrate202, for example. The substrate202may comprise any number of build up layers comprising conductive layers and dielectric layers. In an embodiment, the build up layers211may be formed by laminating and patterning a dielectric material, such as any suitable build up dielectric material for example, and forming and patterning a conductive material, such as a copper material for example, to form conductive traces within the dielectric material. Interconnect structures206,207comprising conductive material may be formed within the dielectric material201. In an embodiment, the interconnect structures206may comprise pads, and the interconnect structures207may comprise vias. In an embodiment, a dry film resist (DFR) patterning process may be utilized to form the conductive structures206,207, in an embodiment. InFIG.2d, an opening208may be formed within the dielectric material201, wherein a surface of a conductive interconnect structure, such as the conductive interconnect structure206, may be exposed. The opening208may be formed utilizing a laser drilling and de-smear processing, in an embodiment. The opening208may be formed in locations where an embedded package inductor is to be formed within the substrate202, such that an embedded inductor may be selectively formed within a package substrate. The opening208may comprise a rectangular structure, and may comprise linear sidewalls213, in an embodiment. In an embodiment, a seed layer (not shown) may optionally be formed on the conductive structure206, and on the sidewalls of the opening208. The seed layer may comprise a thickness of about 50 nm to about 5 microns, in an embodiment, and may be formed by an electroplating process, in an embodiment. In other embodiments, the seed layer may be formed by any suitable formation process, such as by a physical vapor deposition process, for example. The seed layer may comprise such materials as copper, titanium and nickel, for example. InFIG.2e, a magnetic material210may be formed in the opening208, wherein the magnetic material210may comprise a magnetic paste and/or a magnetic ink, and may comprise similar properties to the magnetic material ofFIG.1. In an embodiment, the magnetic material210may be formed on the sidewalls213of the opening and on the exposed surface of the conductive interconnect structure206, by utilizing a stencil printing process. The magnetic material210is formed such that the magnetic material210may comprise a first side215and a second side217, wherein the second side217of the magnetic material is coplanar (within about 1-2 degrees) with an adjacent surface219of the dielectric material201. In an embodiment, a length251of at least one of the first side215or the second side217of the magnetic material210may be less than about 2 times a length250of the interconnect structure206, and may be less than about 1.5 times a length250of the interconnect structure250. In other embodiments, a length of one of the first side215or the second side217may be less than a length of the interconnect structure206. By utilizing stencil printing techniques, the magnetic material210may be selectively formed within portions/locations of the package substrate202, according to particular design requirements, wherein in-package/embedded inductor structures are desired to be located. Any number of openings and magnetic materials may be placed in selected locations within the substrate. Subsequent to the formation of the magnetic material210in the opening208, a magnetic opening212may be formed in the magnetic material210itself (FIG.2f). The magnetic opening212may expose a surface223, such as a first surface, of the conductive interconnect structure206, that is disposed at least partially on the first side215of the magnetic material210. The magnetic opening212may comprise linear sidewalls, in an embodiment. A seed layer209, such as a copper electroplated seed layer, for example, may be formed on the first side203and the second side205of the substrate202, and may be formed within the magnetic opening212and on a portion of the surface223of the conductive interconnect structure206(FIG.2g). Sidewalls of the magnetic opening212may be lined with the seed layer209, but the seed layer209does not completely fill the opening208. The seed layer209may comprise a thickness of between about 50 nm to about 5 microns, in an embodiment. A patterning material240, such as a dry film resist, for example, may be formed/laminated onto the first and second sides203,205of the substrate202(FIG.2h), and an opening225may be formed in the patterning material240(FIG.2i). The opening225may expose a portion of the seed layer209that is disposed within the magnetic opening212, and may expose a portion of the seed layer209that is disposed on the second side217of the magnetic material210. A conductive trace/interconnect structure237may be formed on the seed layer209(FIG.2j), within the magnetic opening and also on the exposed portion of the seed layer209on the second side217of the magnetic material210. The conductive interconnect structure237may comprise any shape according to the particular design requirements, but is dependent on the size of the magnetic opening212and the seed layer209location. In an embodiment, a first side of the interconnect structure237may be disposed on the first side of the interconnect structure206, and a second side of the second interconnect structure, opposite the first side of the interconnect structure237, may be coplanar with the second side of the magnetic material. The patterning material240may be removed from the substrate202(FIG.2k), and the remaining seed layer209may be removed from the first and second sides203,205of the substrate202by utilizing a flash etch process, in an embodiment. InFIG.2l, solder resist242may be formed on the first and second sides203,205of the substrate202, and openings may be patterned to reveal/expose the conductive structures206and to reveal the conductive structure137. Pads244, such as copper pads, may be formed on the conductive structures206,237, and solder interconnect structures, such as solder balls may be formed on the pads244. A device, such as the device130ofFIG.1, for example, or a board (not shown), such as a motherboard for example, may be coupled with the first side203or the second side205of the substrate202by via solder structures coupled to the pads244. AlthoughFIGS.2a-2ldepict the formation of the magnetic material on a core of a cored substrate, a stencil process may be employed to form an embedded inductor structure in a prepeg-based substrate, such as in an interposer, for example. The stencil process described herein may also be employed with a coreless substrate, wherein two coreless panels may be attached to either side of a temporary core, and cavities may be drilled into both panels above and below the temporary core (not shown). A magnetic material may be drilled and plated on both sides of such as temporary core while the temporary core protects the front sides of each substrate. The magnetic material210disposed on the conductive structures may comprise any suitable geometric structure, depending upon the particular design requirements for an embedded inductor. For example, an inductor250geometry may comprise a serpentine structure (FIG.2m, side perspective view) wherein conductive structures206,207are disposed on the selectively formed magnetic material210, in an embodiment. In another embodiment, an inductor250geometry may comprise a conductive material206that may be disposed in a rectangular shape on the selectively formed magnetic material, adjacent the dielectric material201within the substrateFIG.2n(top view). In another embodiment, a magnetic material may be selectively formed within portions of a substrate by utilizing a grinding process with which to reveal a magnetic material, such as a magnetic paste and/or a magnetic ink, for example (FIGS.3a-3l). InFIG.3a, a cross sectional view of a portion of a package structure300, is depicted, wherein a core321may comprise conductive interconnect structures, such as pads306disposed on surfaces, such as a first surface303, and on a second surface305of the core321. A plated through hole304, may extend through the core321, in an embodiment. The plated through holes304may be plated on sidewalls with a conductive layer305, which may comprise a copper layer305. The core321may comprise an organic core, in an embodiment, and may comprise any suitable organic materials, in an embodiment, and may comprise other suitable materials, such as ceramic and/or glass. In other embodiments, the package structure300may comprise a coreless package structure300. In an embodiment, a dielectric material301may be formed/laminated onto the first side and the second side of the core321(FIG.3b), and conductive structures307, such as conductive via structures307may be formed within the dielectric material by utilizing plating and drilling process, for example (FIG.3c). Conductive pads306may be formed on the conductive vias307(FIG.3d). A patterning material308, such as a dry film resist for example, may be formed on the dielectric material301(FIG.3e), and a magnetic material310may be formed on the conductive interconnect structure306, between the patterning material308. In an embodiment, the magnetic material may be selectively formed wherein a sidewall of the magnetic material may be formed adjacent a sidewall of the first conductive via307. The magnetic material310may comprise a magnetic paste or a magnetic ink, and may comprise one or more of the magnetic materials described inFIG.1, for example. The patterning material310may be removed (FIG.3f), and a dielectric layer301may be formed/laminated over the magnetic material310(FIG.3g). A planarizing process320, such as a grinding process320, may be performed wherein the dielectric layer301and the magnetic material310may be coplanar (FIG.3h). Conductive structures307may be formed in the magnetic material310, utilizing laser drilling and copper plating processes, for example (FIG.3i). Conductive structures306, such as conductive pads, may be formed on the conductive structures307, patterning material may be placed in desired locations adjacent the conductive pads, and additional magnetic material310may be formed on the conductive pads306between the patterning material308(FIG.3j). Conductive structures307may be formed within the magnetic material310(FIG.3k). The process of forming magnetic material310within the substrate302and revealing the magnetic material310by utilizing a grinding process may be repeated for as many desired locations for inductor placement within the substrate302. In an embodiment, a solder resist material342may be placed on the final build up layer of the substrate302, and pads344may be formed on conductive interconnect structures306(FIG.3l). Solder structures (not shown) may be formed on the pads, wherein the solder structures may be coupled to a board or a device. Inductor structures may comprise any suitable geometries, and may include structures such as those depicted inFIGS.2m-2n, for example. In yet another embodiment, the magnetic material of the embodiments herein may be formed within a substrate, such as a package substrate, by using a plasma etch process. A substrate400, such as a package substrate, may comprise conductive structures406disposed thereon. A conductive layer409, such as an electroless copper layer409, may be formed on the conductive structures406and on the substrate402(FIG.4b). The conductive layer409may comprise a thickness between about 50 nm to about 5 microns, in an embodiment. A patterning material408may be formed on the conductive layer409, and may be patterned (FIG.4c). An exposed portion of the conductive layer409may be removed from the substrate and from an exposed conductive structure406by using a flash etch process, for example (FIG.4d), and the patterning material408may then be removed (FIG.4e). A magnetic material410may be formed on the conductive layer409, on the conductive interconnect structure406, and on exposed substrate402portions (FIG.4f). The magnetic material410may comprise similar elements as the magnetic materials ofFIG.1, for example, and may comprise a magnetic film, in an embodiment. A second conductive layer409′ may be formed on the magnetic material410, and a patterning material408, such as a dry film resist, may be formed on a portion of the second conductive layer409′ (FIG.4g). The second conductive layer409′ may be removed from the magnetic material410, by using a flash etch process, for example (FIG.4h). In an embodiment, a plasma etch process may be utilized to remove the magnetic material410from the first conductive layer409(FIG.4i). The plasma process may comprise a fluorine based chemistry, in an embodiment. The first conductive material409may be removed from the conductive interconnect structures406, wherein conductive structures425may remain within the magnetic material410(FIG.4j). The conductive structures425may comprise a rectangular shape, and may be disposed between a sidewall of the magnetic material and the conductive structure406. A dielectric layer401may be formed/laminated onto the magnetic material410, and onto the conductive structures406(FIG.4k). A grinding process421may then be employed, wherein the surface of the dielectric material401may be planarized to be coplanar with the surface of the magnetic material410(FIG.4l). Conductive structures407may be formed within the magnetic material410and within the dielectric layer401(FIG.4m), and conductive structures406may then be formed on the conductive structures407. Further build up layers may be formed on the substrate402, wherein any number of build up layers may be formed, wherein magnetic material may be selectively formed within the dielectric material401of the substrate402. Solder material442, solder pads444and surface finish446may be formed on the substrate402, wherein solder structures may be formed (not shown) which may be coupled to a board or a device, in embodiments. The number of levels of conductive traces/metallization levels that may be built up within the package structures described herein may vary according to the particular design requirements. Additional magnetic material may be formed on the initially formed magnetic material, and may be patterned according to design requirements. Various embodiments herein enable the selective embedding of magnetic material in substrates, such as package substrates. Magnetic films, magnetic paste, and/or magnetic ink may be selectively formed within the substrate, according to embodiments herein. Selective formation of the magnetic material is advantageous since the material does not cover substantially large areas of the substrate, and avoids placement of inductors on surfaces of substrates. Covering large areas of a substrate with a magnetic material may interfere with signal integrity. The embodiments enable the selective placement of magnetic material only in certain locations within build up layers. The embodiments utilize processing techniques such as stencil printing, grinding, and plasma etching. The embodiments can be employed with both cored or coreless substrates, dielectric laminates or prepeg materials. FIG.5adepicts a flow chart of a method500of forming an in-package/embedded inductor structure, wherein a magnetic material is selectively electroplated to form a portion of the embedded inductor structure. At operation502, a first interconnect structure is formed on a dielectric material of a substrate. The first interconnect structure may comprise any suitable conductive interconnect structure, such as a conductive trace, a via structure, a pad structure, for example. The substrate may comprise a package substrate, in an embodiment, or may comprise any other type of substrate, such as an interposer, for example. The substrate may comprise a cored package substrate, and may comprise an organic substrate in an embodiment, or may comprise a substrate without a core, such as a core-less substrate, for example. At operation504, a magnetic material may be selectively formed on a surface of the first interconnect structure. The magnetic material may comprise any of the magnetic materials described herein, such as those materials described inFIG.1, for example. In an embodiment, the magnetic material may be formed by utilizing a stencil printing process, wherein the magnetic material may be formed within an opening within the dielectric material, wherein the opening is formed to reveal a surface of the first conductive structure. In an embodiment, the opening may comprise a cavity, such as a rectangular cavity. The opening may comprise linear sidewalls, in an embodiment. The magnetic material may comprise a first side and a second side, wherein the first side of the magnetic material may be formed on the surface of the first interconnect structure. In an embodiment, a seed layer, such as the seed layer ofFIG.2g, for example, may be formed on the first interconnect structure prior to the formation of the magnetic material. Sidewalls of the magnetic material, which may comprise linear sidewalls in an embodiment, may be in direct contact with adjacent dielectric material within the substrate, in an embodiment. The magnetic material may be selectively formed within the substrate, such that it forms a portion of an embedded inductor within the substrate; that is the magnetic material may not be disposed on a surface of the substrate, in an embodiment. In an embodiment, the magnetic material may be revealed and patterned by using a grinding process, and in another embodiment, the magnetic material may be patterned by using a plasma etching process, such as by utilizing a fluorine based chemistry. At operation506, an opening may be formed in the magnetic material. The opening may be formed utilizing laser drilling, for example, and may expose/reveal a surface of the first interconnect structure. At operation508, a second interconnect structure may be formed in the opening. In an embodiment, the second interconnect structure may comprise a via, but in other embodiments, the second interconnect structure may comprise any suitable interconnect structure/trace. In an embodiment, the second interconnect structure may be formed directly on the first interconnect structure, and may be formed by an electroplating process, and may comprise a copper material, for example. In other embodiments, the second interconnect structure may be formed on a seed layer disposed between the first interconnect structure and the second interconnect structure. By selecting the locations of the openings and/or the seed layer formation, magnetic material portions of an inductor structure may be placed at desired locations within a package substrate. The embedded inductor structures may comprise any suitable geometry within specific locations of the substrate, and may comprise structures such as those described inFIGS.2m-2n, for example. At least one build-up layer and/or dielectric layer may be formed on the embedded inductor structure, so that the embedded inductor structure may be fully embedded within the package substrate. FIG.5bdepicts a flow chart of a method520of forming an embedded package inductor structure within a substrate, such as within a package substrate, wherein a magnetic material is selectively formed within the substrate. At operation522, a first interconnect structure may be formed on a dielectric material of a substrate. The first interconnect structure may be formed utilizing a plating process, for example, and may comprise a copper material, in an embodiment. The dielectric material may comprise a build up material of either a cored or a coreless package, for example. At operation524, a magnetic material may be selectively formed on a surface of the first interconnect structure, wherein a sidewall of the formed magnetic material is linear, and wherein the sidewall is adjacent the dielectric material. In an embodiment, the magnetic material may be formed within an opening formed within the dielectric material. In an embodiment, the magnetic material may be formed such that the sidewalls of the magnetic material are directly adjacent the dielectric material of the substrate, and wherein a length of a first side or a length of a second side of the magnetic material is disposed between dielectric material portions of the substrate. In an embodiment, a length of either a first side or a second side of the magnetic material may be less than about 1.5 times a length of the first interconnect structure. In other embodiments, a length of a first or second side of the magnetic material may be less than a length of the first interconnect structure. At operation526, an opening may be formed in the magnetic material, utilizing any of the process described herein. In an embodiment, the opening may comprise a via opening. At operation528, a second interconnect structure may be formed in the opening. The second interconnect structure may comprise a via structure, and may be formed by electroplating a conductive material within the opening, in an embodiment. In an embodiment, a seed layer may be formed within the opening prior to the formation of the magnetic material. In an embodiment, a third interconnect structure may be formed on the second interconnect structure, and an additional magnetic material may be formed on the third conductive interconnect structure. The embedded inductor structure may comprise a any suitable geometries, including those described inFIGS.2m-2n, for example. Any number of additional build up layers may be formed on the embedded inductor structures, according to design requirements. The package structures of the embodiments herein may be coupled with any suitable type of structures capable of providing electrical communications between a microelectronic device, such as a die, disposed in package structures, and a next-level component to which the package structures herein may be coupled (e.g., a circuit board). The device/package structures, and the components thereof, of the embodiments herein may comprise circuitry elements such as logic circuitry for use in a processor die, for example. Metallization layers and insulating material may be included in the structures herein, as well as conductive contacts/bumps that may couple metal layers/interconnects to external devices/layers. In some embodiments, the structures may further comprise a plurality of dies, which may be stacked upon one another, depending upon the particular embodiment. In an embodiment, a die(s) may be partially or fully embedded in a package structure of the embodiments herein. The various embodiments of the device/package structures included herein may be used for system on chip (SOC) products, and may find application in such devices as smart phones, notebooks, tablets, wearable devices and other electronic mobile devices. In various implementations, the package structures herein may be included in a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, and wearable devices. In further implementations, the package devices herein may be included in any other electronic devices that process data. Turning now toFIG.6, illustrated is a cross sectional view of an embodiment of a computing system600. The system600includes a mainboard602or other circuit board. Mainboard602includes a first side601and an opposing second side603, and various components may be disposed on either one or both of the first and second sides601,603. In the illustrated embodiment, the computing system600includes at least one die620, disposed on a surface (such as on a top or bottom or side surface) of a substrate604, such as a package substrate comprising at least one of the embedded inductor structures according to any of the various embodiments herein. The substrate604may comprise an interposer604, for example, or any other type of substrate, such as a cored substrate or a coreless substrate, for example. The substrate604may comprise various conductive layers608, for example, which may be electrically and physically connected to each other by via structures607. The conductive layers608may comprise conductive traces in an embodiment. The substrate604may further comprise through substrate vias612, which may comprise the magnetic material on sidewalls, such as inFIG.3g, for example. Dielectric material605may separate/isolate conductive layers from each other within the substrate604. Joint structures606may electrically and physically couple the substrate604to the board602. The computing system600may comprise any of the embodiments of the embedded inductor structures described herein. System600may comprise any type of computing system, such as, for example, a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a net top computer, etc.). However, the disclosed embodiments are not limited to hand-held and other mobile computing devices and these embodiments may find application in other types of computing systems, such as desk-top computers and servers. Mainboard602may comprise any suitable type of circuit board or other substrate capable of providing electrical communication between one or more of the various components disposed on the board. In one embodiment, for example, the mainboard602comprises a printed circuit board (PCB) comprising multiple metal layers separated from one another by a layer of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route—perhaps in conjunction with other metal layers—electrical signals between the components coupled with the board601. However, it should be understood that the disclosed embodiments are not limited to the above-described PCB and, further, that mainboard602may comprise any other suitable substrate. FIG.7is a schematic of a computing device700that may be implemented incorporating embodiments of the package structures described herein. For example, any suitable ones of the components of the computing device700may include, or be included in, package structures comprising the embedded inductor structures of the various embodiments disclosed herein. In an embodiment, the computing device700houses a board702, such as a motherboard702for example. The board702may include a number of components, including but not limited to a processor704, an on-die memory706, and at least one communication chip708. The processor704may be physically and electrically coupled to the board702. In some implementations the at least one communication chip708may be physically and electrically coupled to the board702. In further implementations, the communication chip708is part of the processor704. Depending on its applications, computing device700may include other components that may or may not be physically and electrically coupled to the board702, and may or may not be communicatively coupled to each other. These other components include, but are not limited to, volatile memory (e.g., DRAM)709, non-volatile memory (e.g., ROM)710, flash memory (not shown), a graphics processor unit (GPU)712, a chipset714, an antenna716, a display718such as a touchscreen display, a touchscreen controller720, a battery722, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device726, an integrated sensor728, a speaker730, a camera732, an amplifier (not shown), compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth). These components may be connected to the system board702, mounted to the system board, or combined with any of the other components. The communication chip708enables wireless and/or wired communications for the transfer of data to and from the computing device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip708may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond. The computing device700may include a plurality of communication chips608. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. In various implementations, the computing device700may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a wearable device, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device500may be any other electronic device that processes data. Embodiments of the package structures described herein may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure. It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features as further provided below: Example 1 is a microelectronic package structure, comprising: a substrate comprising a dielectric material, a first interconnect structure within the dielectric material; magnetic material, wherein a first side of the magnetic material is on a first side of the first interconnect structure; and second interconnect structure within the magnetic material, wherein; first side of the second interconnect structure is on the first side of the first interconnect structure; and second side of the second interconnect structure is coplanar with a second side of the magnetic material. Example 2 includes the microelectronic package structure of example 1, wherein the magnetic material comprises a rectangular shape, and wherein a sidewall of the first interconnect structure is linear. Example 3 includes the microelectronic package structure of example 1, wherein a seed layer is between the magnetic material and a sidewall of the second interconnect structure. Example 4 includes the microelectronic package structure of example 1, wherein the first side of the second interconnect structure is directly on the first side of the first interconnect structure, and wherein the second side of the magnetic material is on the dielectric material. Example 5 includes the microelectronic package structure of example 1, wherein the magnetic material comprises a magnetic paste, and wherein the magnetic paste comprises a carrier, and a magnetic material. Example 6 includes the microelectronic package structure as in of any one of the preceding examples, wherein the magnetic material comprises a portion of an embedded inductor structure. Example 7 includes the microelectronic package structure as in of any one of the preceding examples, wherein the magnetic material comprises one or more of iron, nickel, cobalt or molybdenum, their alloys, and combinations thereof. Example 8 includes the microelectronic package structure as in of any one of the preceding examples, wherein the substrate comprises a die electrically coupled thereto. Example 9 includes the microelectronic package structure as in of any one of the preceding examples, wherein a build-up layer is on the magnetic material. Example 10 is a microelectronic package structure comprising: a substrate comprising a dielectric material; a magnetic material within the dielectric material, the magnetic material comprising a first side and a second side; a first interconnect structure on a first side of the magnetic material, wherein a first side of the first interconnect structure is within the magnetic material, and wherein a second side of the first interconnect structure is on the dielectric material; and a second interconnect structure on the first the side of first interconnect structure, wherein the second interconnect structure is at least partially embedded within the magnetic material. Example 11 includes the microelectronic package structure of example 10, wherein the magnetic material comprises a magnetic paste, wherein the magnetic paste comprises iron, nickel and alloys of iron and nickel, and a carrier. Example 12 includes the microelectronic package structure of example 10 wherein the first interconnect structure comprises a pad, and the second interconnect structure comprises a via. Example 13 includes the microelectronic package structure of example 10, wherein the second side of the first interconnect structure is coplanar with the dielectric material. Example 14 is the microelectronic package structure of example 10, wherein a first sidewall of the magnetic material is directly on the dielectric material, and a second sidewall of the magnetic material is directly on the dielectric material. Example 15 includes the microelectronic package structure of example 10 wherein the substrate comprises a core, and wherein the magnetic material is above the core. Example 16 includes the microelectronic package structure of claim12, wherein a first side of a rectangular copper structure is on a sidewall of the magnetic material and is adjacent the first interconnect structure. Example 17 includes the microelectronic package structure as in any one of the preceding examples, further comprising: a microprocessor; a memory; and a battery, wherein at least the microprocessor is electrically coupled to the substrate. Example 18 is a method of forming a microelectronic package structure, the method comprising: forming a first interconnect structure on a dielectric material of a substrate; selectively forming a magnetic material on a surface of the first interconnect structure; forming an opening in the magnetic material; and forming a second interconnect structure in the opening. Example 19 includes the method of forming the microelectronic package structure of example 18, wherein selectively forming the magnetic material comprises forming a sidewall of the magnetic material adjacent a sidewall of the first conductive material. Example 20 includes the method of forming the microelectronic package structure of any one of the preceding examples, wherein selectively forming the magnetic material comprises: forming a dielectric layer on the first conductive interconnect structure; forming a cavity in the dielectric layer, wherein a surface of the first interconnect structure is exposed; and forming the magnetic material in the cavity, and on the surface of the first interconnect structure. Example 21 includes the method of forming the microelectronic package structure of any of the preceding examples, wherein selectively forming the magnetic material comprises: forming the magnetic material on the surface of the first conductive interconnect structure, wherein the magnetic material is formed on the dielectric material adjacent the first conductive interconnect structure; forming a mask on the surface of the first conductive interconnect structure; and plasma etching the magnetic material adjacent the mask. Example 22 includes the method of forming the microelectronic package structure of example 21, wherein forming the magnetic material comprises forming a magnetic film. Example 23 incudes the method forming the microelectronic package structure of example 18, wherein forming the opening comprises: forming a dielectric layer on the magnetic material; grinding a first surface of the dielectric layer to be coplanar with a first surface of the magnetic material; and forming an opening in the magnetic material. Example 24 includes the method of forming the microelectronic package structure as in any one of the preceding examples, wherein forming the first conductive interconnect structure comprises forming a conductive pad, and wherein forming the second conductive interconnect structure comprises forming a via. Example 25 includes the method of forming the microelectronic package as in any one of the preceding examples wherein the magnetic material comprises nickel, iron (please add any other materials), and alloys thereof. However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. | 58,676 |
11862553 | DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment 1 is described hereinafter using the drawings.FIG.1is a top view of a semiconductor device100according to the embodiment 1.FIG.2is a side view of the semiconductor device100. InFIG.1andFIG.2, an illustration of an insulating material as a sealing material is omitted to make an inner structure of the semiconductor device100visible. As illustrated inFIG.1, the semiconductor device100includes an insulating substrate1, a circuit pattern5, a plurality of (twelve, for example) semiconductor chips6, a low potential terminal7, a high potential terminal8, and an output terminal9. The semiconductor device100further includes an insulating material (illustration is omitted) such as gel sealing the insulating substrate1, the circuit pattern5, the plurality of semiconductor chips6, a part of the low potential terminal7, a part of the high potential terminal8, and a part of the output terminal9. The insulating substrate1is made of ceramic, for example, and formed into a rectangular shape in a top view. The circuit pattern5is provided on an upper surface of the insulating substrate1. The circuit pattern5includes a low potential circuit pattern2as the circuit pattern on the low potential side, a high potential circuit pattern3as the circuit pattern on the high potential side, and an output circuit pattern4as the circuit pattern on an output side. The low potential circuit pattern2is provided in a range from a position closer to the other end of the upper surface of the insulating substrate1in a longitudinal direction in relation to a center portion thereof to one end portion thereof. The high potential circuit pattern3is provided in a region adjacent to the low potential circuit pattern2. Specifically, the high potential circuit pattern3is provided in a range from a position closer to the other end of the upper surface of the insulating substrate1in the longitudinal direction in relation to the center portion thereof to the other end portion thereof. Herein, the high potential circuit pattern3has a shape of surrounding an outer peripheral side of the low potential circuit pattern2so that the low potential circuit pattern2and the high potential circuit pattern3do not have contact with each other in the position closer to the other end of the upper surface of the insulating substrate1in the longitudinal direction in relation to the center portion thereof. The output circuit pattern4is provided on an outer peripheral side of the low potential circuit pattern2and the high potential circuit pattern3on the upper surface of the insulating substrate1. Specifically, the output circuit pattern4is provided along two sides of the upper surface of the insulating substrate1in the longitudinal direction. As illustrated inFIG.1, the plurality of semiconductor chips6are metal oxide semiconductor field effect transistors (MOSFET), for example, and mounted on the circuit pattern5. Specifically, the twelve semiconductor chips6are SiC-MOSFETs. The six semiconductor chips6in the twelve semiconductor chips6are disposed to face each other to form three pairs on the high potential circuit pattern3, and connected to a position located on a side of the high potential circuit pattern3in the output circuit pattern4using a plurality of aluminum wires6a. The remaining six semiconductor chips6are disposed to face each other to form three pairs in a position located on a side of the low potential circuit pattern2in the output circuit pattern4, and connected to the low potential circuit pattern2using the plurality of aluminum wires6a. The twelve semiconductor chips6are mounted inFIG.1, however, the configuration is not limited thereto. It is sufficient that at least two semiconductor chips6are mounted. Herein, “the side of the low potential circuit pattern2” indicates a region17extending from the center portion of the upper surface of the insulting substrate1to one end portion in the longitudinal direction. “The side of the high potential circuit pattern3” indicates a region18extending from the center portion of the upper surface of the insulting substrate1to the other end portion in the longitudinal direction. As illustrated inFIG.1andFIG.2, the low potential terminal7and the high potential terminal8constitute parallel flat plates vertically disposed via an insulating paper11. The low potential terminal7includes a connection part7aas one end portion connected to the low potential circuit pattern2, a flat plate part7bas a midway portion constituting the parallel flat plates with the high potential terminal8, and an electrode part7cas the other end portion protruding from the insulating substrate1. The flat plate part7bis disposed in parallel to the insulating substrate1on an upper side of the insulating substrate1. The flat plate part7bextends to the side of the low potential circuit pattern2of the insulating substrate1, and covers an upper surface of the low potential circuit pattern2and an upper surface of a part of the output circuit pattern4. The connection part7aextends in an up-down direction, and one end portion thereof is connected to a position in the low potential circuit pattern2located on the side of the high potential circuit pattern3, and the other end portion thereof is connected to one end portion of the flat plate part7b. The electrode part7chas a width smaller than the flat plate part7bin a top view, and is formed into an L-like shape in a side view. One end portion of the electrode part7cis connected to the other end portion of the flat plate part7b, and the electrode part7cis bended to an upper side to extend to an outer side of the insulating substrate1in parallel to the flat plate part7b. That is to say, the electrode part7cprotrudes from one end of the insulating substrate1in the longitudinal direction. As illustrated inFIG.1andFIG.2, the high potential terminal8includes a connection part8aas one end portion connected to the high potential circuit pattern3, a flat plate part8bas a midway portion constituting the parallel flat plate with the low potential terminal7, and an electrode part8cas the other end portion protruding from the insulating substrate1. The flat plate part8bis disposed in parallel to the insulating substrate1on the upper side of the insulating substrate1, and located on an upper side of the flat plate part7bof the low potential terminal7. In other words, the flat plate part7bof the low potential terminal7is disposed on a lower side of the flat plate part8bof the high potential terminal8. The flat plate part8bextends to the side of the low potential circuit pattern2of the insulating substrate1, and covers the upper surface of the low potential circuit pattern2and the upper surface of the part of the output circuit pattern4. The connection part8aextends in the up-down direction, and one end portion thereof is connected to a position of the high potential circuit pattern3adjacent to the connection part7aof the low potential terminal7, and the other end portion thereof is connected to one end portion of the flat plate part8b. The electrode part8chas a width smaller than the flat plate part8bin a top view. One end portion of the electrode part8cis connected to the other end portion of the flat plate part8b, and the electrode part8cextends to an outer side of the insulating substrate1. That is to say, the electrode part8cprotrudes from one end of the insulating substrate1in the longitudinal direction. The electrode part7cof the low potential terminal7and the electrode part8cof the high potential terminal8are located in the same height position. As illustrated inFIG.1andFIG.2, the output terminal9is a terminal to which output of the semiconductor chip6is given, and includes two connection parts9aas one end portions connected to a position in the output circuit pattern4located on the side of the high potential circuit pattern3, a plate-like part9bconnecting the two connection parts9a, and two electrode parts9cas the other end portion protruding from the insulating substrate1. The two connection parts9aextend in the up-down direction, and face each other with the high potential circuit pattern3therebetween. One end portion of the two connection parts9ais connected to a position in the output circuit pattern4located on the side of the high potential circuit pattern3. The plate-like part9bis disposed in parallel to the insulating substrate1on the upper side of the insulating substrate1. The two electrode parts9care formed to have the same width as the plate-like part9b, and formed in the same height position as the plate-like part9b. The two electrode parts9cprotrude from the other end of the insulating substrate1in the longitudinal direction on a side opposite to a direction in which the electrode part7cof the low potential terminal7and the electrode part8cof the high potential terminal8protrude. If the output terminal9is provided on the side of the low potential circuit pattern2of the output circuit pattern4, that is to say, if the two connection parts9aare connected to positions in the output circuit pattern4located on the side of the low potential circuit pattern2and the two electrode parts9cprotrude from one end of the insulating substrate1in the longitudinal direction, parasitic resistance between the semiconductor chip6disposed on the side of the high potential circuit pattern3and the output terminal9increases and an electrical loss of an electrical circuit made up of the plurality of semiconductor chips6increases. If the two electrode parts9care connected to positions in the output circuit pattern4located on the side of the high potential circuit pattern3and the two electrode parts9cprotrude from one end of the insulating substrate1in the longitudinal direction, a length Lb from the connection part9ato the electrode part9cof the output terminal9(refer toFIG.2) increases, thus inductance of the output terminal9increases. In the embodiment 1, the output terminal9is provided on the side of the high potential circuit pattern3in the output circuit pattern4to solve such a problem. That is to say, the two connection parts9aare connected to the positions in the output circuit pattern4on the side of the high potential circuit pattern3, and the two connection parts9cprotrude from the other end of the insulating substrate1in the longitudinal direction. Main electrode attaching parts10are provided in the electrode part7cof the low potential terminal7, the electrode part8cof the high potential terminal8, and the electrode part9cof the output terminal9. FIG.3is a circuit diagram illustrating an equivalent circuit of the semiconductor device100. As illustrated inFIG.3, in the semiconductor device100, the six parallel semiconductor chips6are disposed on a side of an upper arm between a P electrode (corresponding to the high potential terminal8) and an AC electrode (corresponding to the output terminal9), and the six parallel semiconductor chips6are disposed on a side of a lower arm between an AC electrode (corresponding to the output terminal9) and an N electrode (corresponding to the low potential terminal7). Herein, a P electrode side and an N electrode side are referred to as the upper arm and the lower arm, respectively. In the above description, the semiconductor chip6is the SiC-MOSFET, but is not limited thereto. The semiconductor chip6may be made up of a switching element such as reverse conductive insulated gate bipolar transistor (RC-IGBT) and a reflux element formed as one chip. As described above, the semiconductor device100is sealed by an insulating material not shown in the drawings, and the electrode part7cof the low potential terminal7, the electrode part8cof the high potential terminal8, and the electrode part9cof the output terminal9are exposed from the insulating material. As described above, the semiconductor device100according to the embodiment 1 includes: the insulating substrate1; the circuit pattern5including the low potential circuit pattern2provided on the insulating substrate1and the high potential circuit pattern3provided on the region adjacent to the low potential circuit pattern2on the insulating substrate1; the plurality of semiconductor chips6mounted on the circuit pattern5; the low potential terminal7having one end portion connected to the low potential circuit pattern2; and the high potential terminal8having one end portion connected to the high potential circuit pattern3, wherein the high potential terminal8and the low potential terminal7include the flat plate parts8band7bconstituting the parallel flat plates vertically disposed in parallel to each other and extending on the side of the low potential circuit pattern2and the electrode parts8cand7cprotruding from the insulating substrate1. The high potential circuit pattern3is formed in the position adjacent to the low potential circuit pattern2, thus when the connection part8aof the high potential terminal8and the connection part7aof the low potential terminal7are disposed in the positions adjacent to each other, the length from the connection part8aof the high potential terminal8to the connection part7aof the low potential terminal7can be reduced, and the length La of the parallel flat plate made up of each of the flat plate parts8band7bof the high potential terminal8and the low potential terminal7(refer toFIG.2) can be increased. This configuration can lead to increase in the area of the parallel flat plate. As described above, the length from the connection part8aof the high potential terminal8to the connection part7aof the low potential terminal7is reduced and the area of the parallel flat plate is increased, thus inductance between the high potential terminal8and the low potential terminal7can be reduced in the semiconductor device100while achieving downsizing of the semiconductor device100. The six semiconductor chips6in the twelve semiconductor chips6are disposed to face each other to form three pairs on the high potential circuit pattern3, and connected to the position located on the side of the high potential circuit pattern3in the output circuit pattern4using the plurality of aluminum wires6a. The remaining six semiconductor chips6are disposed to face each other to form three pairs in the position located on the side of the low potential circuit pattern2in the output circuit pattern4, and connected to the low potential circuit pattern2using the plurality of aluminum wires6a. The semiconductor chips6are disposed in this manner, thus a degree of freedom in arranging the aluminum wires6ais increased. Accordingly, the number of aluminum wires6acan be increased to reduce a current density for one aluminum wire6a. Accordingly, inductance between the plurality of aluminum wires6acan be reduced. The semiconductor device100further includes the output terminal9to which output of the semiconductor chip6is given. The circuit pattern5further includes the output circuit pattern4provided on the outer peripheral side of the low potential circuit pattern2and the high potential circuit pattern3on the insulating substrate1. The output terminal9includes the connection part9aconnected to the position in the output circuit pattern4located on the side of the high potential circuit pattern3and the electrode part9cprotruding from the insulating substrate1. Accordingly, the length Lb from the connection part9ato the electrode part9cof the output terminal9(refer toFIG.2) can be reduced, thus parasitic resistance between the semiconductor chip6disposed on the side of the high potential circuit pattern3and the output terminal9can be reduced. The semiconductor chip6is the SiC-MOSFET, thus high-speed interruption of current can be performed at a time of an off operation of the semiconductor chip6. Accordingly, an electrical loss occurring at the time of interruption of the current can be reduced in the semiconductor chip6. The semiconductor chip6is made up of the switching element and the reflux element formed as one chip, thus density of the semiconductor device100can be increased, and the semiconductor device100can be further downsized. The flat plate part7bof the low potential terminal7is disposed on the lower side of the flat plate part8bof the high potential terminal8, thus the flat plate part7bof the low potential terminal7constituting a lower part of the parallel flat plates and the low potential circuit pattern2and the aluminum wire6alocated on the lower side of the parallel flat plates have the same potential, and a height position of the parallel flat plates can be reduced. Accordingly, the semiconductor device100can be further downsized. Embodiment 2 A semiconductor device100A according to an embodiment 2 is described next.FIG.4is a top view of the semiconductor device100A according to the embodiment 2.FIG.5is a side view of the semiconductor device100A. In the description in the embodiment 2, the same reference numerals are assigned to the same constituent elements as those described in the embodiment 1, and the description thereof will be omitted. As illustrated inFIG.4andFIG.5, in the embodiment 2, a region where the output circuit pattern4is provided is different from that in the embodiment 1, and in accordance with this, the semiconductor device100A includes, in place of the output terminal9, an output terminal19having a shape and a position where the output terminal19is connected to the output circuit pattern4different from the output terminal9. The output circuit pattern4is provided along the two sides of the upper surface of the insulating substrate1in the longitudinal direction, and also provided in a side on the other end side of the upper surface of the insulating substrate1in the longitudinal direction. The output terminal19includes a connection part19aas one end portion connected to the side on the other end side in the output circuit pattern4in the longitudinal direction on the upper surface of the insulating substrate1and an electrode part19bas the other end portion protruding from the insulating substrate1. The connection part19ais provided along the side on the other end side on the upper surface of the insulating substrate1in the longitudinal direction, and extends in the up-down direction. One end portion of the connection part19ais connected to a position in the output circuit pattern4located in the side on the other end side of the upper surface of the insulating substrate1in the longitudinal direction. The electrode part19bis formed into a U-like shape in a top view, and disposed in parallel to the insulating substrate1on the upper side of the insulating substrate1. The electrode part19bextends from the other end portion of the connection part19ain a direction opposite to a direction in which the electrode part7cof the low potential terminal7and the electrode part8cof the high potential terminal8protrude. Two tip end portions having a U-like shape in the electrode part19bprotrude from the other end of the insulating substrate1in the longitudinal direction, and the main electrode attaching parts10are provided in the two tip end portion having the U-like shape in the electrode part19b. As described above, in the semiconductor device100A according to the embodiment 2, the connection part19aof the output terminal19is connected to the position located in the end portion on the insulating substrate1on the side opposite to the direction in which the electrode parts8cand7cof the high potential terminal8and the low potential terminal7protrude in the output circuit pattern4. Accordingly, the length Lb from the connection part19ato the two tip end portions having the U-like shape of the electrode part19bin the output terminal19can be reduced compared with the case in the embodiment 1. The output circuit pattern4is provided in the side on the other end side of the upper surface of the insulating substrate1in the longitudinal direction, and the connection part19aof the output terminal19is connected thereto. The high potential terminal8and the low potential terminal7are not disposed in the side on the other end side of the upper surface of the insulating substrate1in the longitudinal direction, thus an area of the position where the output terminal19is connected to the output circuit pattern4can be increased. Accordingly, contact resistance in the position where the output terminal19is connected to the output circuit pattern4can be reduced. Each embodiment can be arbitrarily combined, or each embodiment can be appropriately varied or omitted. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention. | 20,883 |
11862554 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects in which embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of present disclosure. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. Embodiments of the present disclosure will be described with reference toFIG.1toFIG.8. The following description uses a dynamic random-access memory (DRAM) as an illustrative example of a semiconductor memory device. FIG.1is a vertical cross-sectional view of a structure of a memory device100including a memory cell region104and a peripheral region114in accordance with one embodiment of the present disclosure. The memory device100may be an apparatus including a portion fabricated in a FBOL above a substrate102. The portion fabricated in the FEOL includes a memory cell106in the memory cell region104. The memory cell106may be disposed on a substrate102. The memory cell106may include a transistor108on the substrate102and a capacitor110coupled to the transistor108. An insulating film112may be disposed on the substrate102, above the capacitor110. In the peripheral region114, the portion fabricated in the FEOL includes a transistor116that may be disposed on the substrate102. An insulating film118may be disposed above the substrate102in the peripheral region114. The insulating film118may be disposed above the transistor116. A via120coupled to the transistor116may be disposed within the insulating film118. In some embodiments, the insulating films112and118may be continuous. In some embodiments, the insulating films112and118may include the same material, for example, silicon dioxide (SiO2). The memory device100may include a portion fabricated in a BEOL above the portion fabricated in the FEOL. The portion fabricated in the BEOL includes a portion122including insulating films above the insulating films112and118. The portion122may also include interconnects124,126and128disposed above the insulating films112and118. While the portion122inFIG.1includes the interconnects124,126and128, a number of interconnects may not be limited to three. In some embodiments, the interconnect124may be disposed on the insulating films112and118. The interconnect126may be disposed on one or more insulating layers of the portion122that is on the interconnect124. The interconnect128may be disposed on portion122that is on the interconnect128. In some embodiments, there may be one or more interconnects130and132that couple the interconnects124,126and128to one another. In some embodiments, the interconnects130and132may include the same material as the interconnects124,126and128. (n some embodiments, one or more insulating layers of the portion122may be disposed on the interconnect128. In some embodiments, the interconnects124,126and128may be conductive layers. In some embodiments, the interconnects124,126and128may be a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3) including metal, respectively. For example, the interconnects124,126and128may include copper (Cu). In some embodiments, the portion122may include material having a lower dielectric constant (k) (low-k material) than silicon dioxide (SiO2) that exhibits weak electric polarization between conductive layers. The low-k material may be included to prevent diffusion of a conductive material, such as copper (Cu), and to reduce parasitic capacitance between the interconnects. Using the low-k material may help to achieve high speed operations of electronic circuits in the semiconductor devices. In some embodiment, the low-k material may include silicon oxycarbide (SiOC) or silicon carbonitride (SiCN). In some embodiments, the interconnects124,126,128,130and132may include coating on surfaces in contact with the low-k material. An insulating film134may be disposed on the portion122. In some embodiments, the insulating film134may include silicon dioxide (SiO2). Within the insulating film134, a capacitor136may be disposed. In some embodiments, the capacitor136may be a metal-insulator-metal (MIM) capacitor. Above the insulating film134and the capacitor136, another interconnect138may be disposed. In some embodiments, the interconnect138may be a conductive layer. In some embodiments, the interconnect138may include metal. For example, the interconnect138may include aluminum (Al). In some embodiments, there may be another insulating film above or below the insulating film134and one or more interconnects above the other insulating film may be disposed inFIG.1. The capacitor136may be coupled to the interconnect138. Another insulating layer140may be disposed on the interconnect138. The insulating film140may include silicon dioxide (SiO2). The insulating layer140may have an opening148. A conductive layer142may be disposed above the insulating layer140. The conductive layer142may have a portion covering the insulating film140along a side of the opening148and a portion that is a bottom of the opening148where a pad may be disposed to be coupled to the interconnect138In some embodiment, the conductive layer142may be an integrated redistribution layer. In some embodiments, the conductive layer142may include aluminum (Al). The conductive layer142may be covered by a passivation film144. In some embodiments, the passivation film144may include silicon nitride (Si3N4). In some embodiments, a polyimide film146may be disposed above the passivation film144. In some embodiments, the polyimide film146may include photopolymer material. FIG.2is a vertical cross-sectional view of a structure of a portion200of the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion200may include the via120in the insulating film118and the portion122ofFIG.1above the insulating film118and the via120. The portion122may include an insulating film208, an interconnect124disposed in the insulating film202, an insulating film204above the interconnect124and the insulating film202, a portion206above the insulating film204, and a portion212above the portion206. The portion206may include an insulating film208, an interconnect126above the insulating film208and an insulating film210above the interconnect126. The portion206may also include an interconnect130through the insulating films204and208that couples the interconnect126to the interconnect124. The portion212may include an insulating film214, an interconnect128above the insulating film214, a hydrogen supply film216above the interconnect128, an insulating film218above the hydrogen supply film216, and a hydrogen barrier film220above the insulating film218. The portion212may also include an interconnect132through the insulating films210and214that couples the interconnect128to the interconnect126. In some embodiments, the insulating films202,204,208,210,214and218may include material that has a lower dielectric constant (k) (low-k material) than silicon dioxide (SiO2) that exhibits weak electric polarization between conductive materials. The insulating films204,210and218may include so-called barrier low-k (BLOk) films to prevent diffusion of conductive material, such as copper (Cu). By including the BLOk films, parasitic capacitance between the interconnects may be reduced and high speed operations of electronic circuits in semiconductor devices may be achieved. The low-k material in the insulating films202,204,208,210,214and218may include, for example, carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The hydrogen supply film216may release hydrogen and/or hydrogen ions during subsequent thermal processes. For example, the hydrogen supply film216may include a passivation plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si3N4) film that may release hydrogen and/or hydrogen ions during subsequent thermal processes at relatively lower temperatures, compared to temperatures for forming layers in the FEOL. For example, the passivation PECVD silicon nitride film may have at least one of higher concentration of Si—H bonds, a low concentration of N—H bonds, or a high Si/N composition. The released hydrogen and/or the hydrogen ions may reach the capacitor110and transistors108and116inFIG.1. The hydrogen and/or hydrogen ions provided by the hydrogen supply film216may reduce leakage currents of the capacitor110and the transistors108and116. Including the hydrogen supply film216may improve data reliability and refresh rates of the memory cell106inFIG.1. The hydrogen barrier film220may be disposed above the hydrogen supply film216. The hydrogen barrier film220may be disposed between the hydrogen supply film216and the capacitor136(shown inFIG.1). For example, the hydrogen barrier film220may block hydrogen and hydrogen ions and limit migration of the hydrogen and hydrogen ions from one side of the hydrogen barrier film220to the other. In some embodiments, the hydrogen barrier film220may be used to prevent hydrogen and hydrogen ions from migrating to other films and/or semiconductor structures. For example, preventing hydrogen and hydrogen ions from the hydrogen supply film216positioned below the hydrogen barrier film220migrating to films and/or structures positioned above the hydrogen barrier film220. The hydrogen barrier film220may be hydrogen-impermeable, for example, include hydrogen-impermeable material that may not permeate hydrogen and hydrogen ions. The hydrogen barrier film220may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) disposed by atomic layer deposition (ALD). In some embodiments, the hydrogen barrier film220may be formed around or under 400° C. Including the hydrogen barrier film220may prevent the hydrogen and hydrogen ions released from the hydrogen supply film216from reaching the capacitor136inFIG.1. FIG.3Ais a vertical cross-sectional view of a structure of a portion300aof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion300amay be included in the portion206. The portion300amay include an insulating film302a, an interconnect304aabove the insulating film302aand an insulating film306aabove the interconnect304a. The insulating films302aand306amay include low-k material. The low-k material in the insulating films302aand306amay include, for example, carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The interconnect304amay correspond to the interconnect126that may include copper (Cu). The insulating film306amay include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu) from the interconnect304a. In some embodiments, the portion206ofFIG.2may include a hydrogen supply film.FIG.3Bis a vertical cross-sectional view of a structure of a portion300bof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion300bmay be included in the portion206. The portion300bincludes an insulating film302b, an interconnect304babove the insulating film302band an insulating film306babove the interconnect304b, which are similar to the insulating film302a, the interconnect304aand the insulating film306a. Thus, a detailed description of the insulating film302b, the interconnect304band the insulating film306bis omitted in the interest of brevity. The portion300bmay include a hydrogen supply film308above the insulating film306b. The hydrogen supply film308may release hydrogen and/or hydrogen ions during subsequent thermal processes to treat the transistors108and116and the capacitor110inFIG.1. FIG.30is a vertical cross-sectional view of a structure of a portion300cof the memory device in accordance with one embodiment of the present disclosure. In some embodiments, the portion300cmay be included in the portion206. The portion300cincludes an insulating film302c, an interconnect304cabove the insulating film302cand an insulating film306cabove the interconnect304c, which are similar to the insulating film302a, the interconnect304aand the insulating film306a. Thus, a detailed description of the insulating film302c, the interconnect304cand the insulating film306cis omitted in the interest of brevity. The portion300cmay include a hydrogen supply film310disposed between the interconnect304cand the insulating film306c. The hydrogen supply film310may release hydrogen and/or hydrogen ions during subsequent thermal processes to treat the transistors108and116inFIG.1. FIG.3Dis a vertical cross-sectional view of a structure of a portion300dof the memory device in accordance with one embodiment of the present disclosure. In some embodiments, the portion300dmay be included in the portion206, The portion300dincludes an insulating film302d, an interconnect304dabove the insulating film302dand an insulating film306dabove the interconnect304d, which are similar to the insulating film302a, the interconnect304aand the insulating film306a. Thus, a detailed description of the insulating film302d, the interconnect304dand the insulating film306dis omitted in the interest of brevity. The portion300dmay further include hydrogen supply films312and314. The hydrogen supply film312may be disposed above the insulating film306d. The hydrogen supply film314may be disposed between the interconnect304dand the insulating film306d. The hydrogen supply films312and314may release hydrogen and/or hydrogen ions during subsequent thermal processes to treat the transistors108and116inFIG.1. In some embodiments, the portion212ofFIG.2may include a hydrogen barrier film.FIG.4Ais a vertical cross-sectional view of a structure of a portion400aof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion400amay be included in the portion212. The portion400amay include an insulating film402a, an interconnect404aabove the insulating film402aand an insulating film406aabove the interconnect404a. The insulating films402aand406amay include low-k material. The low-k material in the insulating films402aand406amay include, for example, carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The interconnect404amay correspond to the interconnect128that may include copper (Cu). The insulating film406amay include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu), from the interconnect404a. The portion400amay include a hydrogen barrier film408above the insulating film406a. For example, the hydrogen barrier film408may block hydrogen and hydrogen ions and limit migration of the hydrogen and hydrogen ions from one side of the hydrogen barrier film408to the other. In some embodiments, the hydrogen barrier film408may be used to prevent hydrogen and hydrogen ions from migrating to other films and/or semiconductor structures. For example, preventing hydrogen and hydrogen ions from a hydrogen supply film positioned below the hydrogen barrier film408migrating to films and/or structures positioned above the hydrogen barrier film408. The hydrogen barrier film408may be hydrogen-impermeable, for example, include hydrogen-impermeable material that may not permeate hydrogen and hydrogen ions. The portion400amay be disposed above any one of the portions300b,300c, or300d. The hydrogen barrier film408may prevent the hydrogen and hydrogen ions released from a hydrogen supply film, such as the hydrogen supply film216of the portion212, the hydrogen supply film308of the portion300b, the hydrogen supply film310of the portion300c, or the hydrogen supply film314of the portion300d, from reaching the capacitor136inFIG.1. Because at least one hydrogen supply film may be included above the portion300a, the portion400amay not be disposed above the portion300a. The hydrogen barrier film408may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) deposited by ALD processes. FIG.4Bis a vertical cross-sectional view of a structure of a portion400bof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion400bmay be included in the portion212. The portion400bmay include an insulating film402b, an interconnect404babove the insulating film402band an insulating film406babove the interconnect404b. The insulating films402band406bmay include low-k material. For example, the low-k material in the insulating films402band406bmay include carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The interconnect404bmay correspond to the interconnect128that may include copper (Cu). The insulating film406bmay include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu), from the interconnect404b. The portion400bmay include a hydrogen barrier film410between the interconnect404band the insulating film406b. The portion400bmay also include a hydrogen barrier film412above the insulating film406b. For example, the hydrogen barrier films410and412may block hydrogen and hydrogen ions and limit migration of the hydrogen and hydrogen ions from one side of the hydrogen barrier films410and412to the other respectively. In some embodiments, the hydrogen barrier films410and412may be used to prevent hydrogen and hydrogen ions from migrating to other films and/or semiconductor structures. For example, preventing hydrogen and hydrogen ions from a hydrogen supply film positioned below the hydrogen barrier films410and412migrating to films and/or structures positioned above the hydrogen barrier films410and412. The hydrogen barrier films410and412may be hydrogen-impermeable, for example, include hydrogen-impermeable material that may not permeate hydrogen and hydrogen ions. The portion400bmay be disposed above any one of the portions300b,300c, or300d. The hydrogen barrier films410and412may prevent the hydrogen and hydrogen ions released from a hydrogen supply film, such as the hydrogen supply film216of the portion212, the hydrogen supply film308of the portion300b, the hydrogen supply film310of the portion300c, or the hydrogen supply film314of the portion300d, from reaching the capacitor136inFIG.1. Because at least one hydrogen supply film may be included above the portion300a, the portion400bmay not be disposed above the portion300a. The hydrogen barrier films410and412may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) deposited by ALD processes. FIG.40is a vertical cross-sectional view of a structure of a portion400cof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion400cmay be included in the portion212. The portion400cmay include an insulating film402c, an interconnect404cabove the insulating film402cand an insulating film406cabove the interconnect404c. The insulating films402cand406cmay include low-k material. For example, the low-k material in the insulating films402cand406cmay include carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The interconnect404cmay correspond to the interconnect128that may include copper (Cu). The insulating film406cmay include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu), from the interconnect404c. The portion400cmay include a hydrogen supply film414between the interconnect404cand the insulating film406c. The hydrogen supply film414may release hydrogen and/or hydrogen ions during subsequent thermal processes to treat the transistors108and116inFIG.1. The portion400cmay also include a hydrogen barrier film416above the insulating film406b. For example, the hydrogen barrier film416may block hydrogen and hydrogen ions and limit migration of the hydrogen and hydrogen ions from one side of the hydrogen barrier film416to the other. In some embodiments, the hydrogen barrier film416may be used to prevent hydrogen and hydrogen ions from migrating to other films and/or semiconductor structures. For example, preventing hydrogen and hydrogen ions from a hydrogen supply film positioned below the hydrogen barrier film416migrating to films and/or structures positioned above the hydrogen barrier film416. The hydrogen barrier film416may be hydrogen-impermeable, for example, include hydrogen-impermeable material that may not permeate hydrogen and hydrogen ions. The portion400cmay be disposed above any one of the portions300a.300b,300c, or300d. The hydrogen barrier film416may prevent the hydrogen and hydrogen ions released from the hydrogen supply film414as well as the hydrogen supply film216of the portion212, the hydrogen supply film308of the portion300b, the hydrogen supply film310of the portion300c, or the hydrogen supply film314of the portion300d, from reaching the capacitor136inFIG.1. The hydrogen barrier film416may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) deposited by ALD processes. FIG.4Dis a vertical cross-sectional view of a structure of a portion400dof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion400dmay be included in the portion212. The portion400dmay include an insulating film402d, an interconnect404dabove the insulating film402dand an insulating film406dabove the interconnect404d. The insulating films402dand406dmay include low-k material. For example, the low-k material in the insulating films402dand406dmay include carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The interconnect404dmay correspond to the interconnect128that may include copper (Cu). The insulating film406dmay include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu), from the interconnect404d. The portion400dmay include a hydrogen supply film418above the insulating film406c. The hydrogen supply film418may release hydrogen and/or hydrogen ions during subsequent thermal processes to treat the transistors108and116inFIG.1. The portion400dmay also include a hydrogen barrier film420above the hydrogen supply film418. For example, the hydrogen barrier film420may block hydrogen and hydrogen ions and limit migration of the hydrogen and hydrogen ions from one side of the hydrogen barrier film420to the other. In some embodiments, the hydrogen barrier film420may be used to prevent hydrogen and hydrogen ions from migrating to other films and/or semiconductor structures. For example, preventing hydrogen and hydrogen ions from the hydrogen supply film418positioned below the hydrogen barrier film420migrating to films and/or structures positioned above the hydrogen barrier film420. The hydrogen barrier film420may be hydrogen-impermeable, for example, include hydrogen-impermeable material that may not permeate hydrogen and hydrogen ions. The portion400dmay be disposed above any one of the portions300a,300b,300c, or300d. The hydrogen barrier film420may prevent the hydrogen and hydrogen ions released from the hydrogen supply film418as well as the hydrogen supply film216of the portion212, the hydrogen supply film308of the portion300b, the hydrogen supply film310of the portion300c, or the hydrogen supply film314of the portion300d, from reaching the capacitor136inFIG.1. The hydrogen barrier film420may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) deposited by ALD processes. FIG.4Eis a vertical cross-sectional view of a structure of a portion400eof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion400emay be included in the portion212. The portion400cmay include an insulating film402c, an interconnect404eabove the insulating film402eand an insulating film406eabove the interconnect404e. The insulating films402eand406emay include low-k material. For example, the low-k material in the insulating films402eand406emay include carbon-doped silicon oxide (SiOC) or nitrogen-doped silicon carbide (SiCN). The interconnect404cmay correspond to the interconnect128that may include copper (Cu). The insulating film406cmay include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu), from the interconnect404e. The portion400emay include a hydrogen supply film422above the interconnect404e. The hydrogen supply film422may release hydrogen and/or hydrogen ions during subsequent thermal processes to treat the transistors108and116inFIG.1. The portion400cmay also include a hydrogen barrier film424between the hydrogen supply film422and the insulating film406e. For example, the hydrogen barrier film424may block hydrogen and hydrogen ions and limit migration of the hydrogen and hydrogen ions from one side of the hydrogen barrier film424to the other. In some embodiments, the hydrogen barrier film424may be used to prevent, hydrogen and hydrogen ions from migrating to other films and/or semiconductor structures. For example, preventing hydrogen and hydrogen ions from the hydrogen supply film422positioned below the hydrogen barrier film424migrating to films and/or structures positioned above the hydrogen barrier film424. The hydrogen barrier film424may be hydrogen-impermeable, for example, include hydrogen-impermeable material that may not permeate hydrogen and hydrogen ions. The portion400emay be disposed above any one of the portions300a,300b,300c, or300d. The hydrogen barrier film424may prevent the hydrogen and hydrogen ions released from the hydrogen supply film422as well as the hydrogen supply film216of the portion212, the hydrogen supply film308of the portion300b, the hydrogen supply film310of the portion300c, or the hydrogen supply film314of the portion300d, from reaching the capacitor136inFIG.1. The hydrogen barrier film424may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) deposited by ALD processes. FIG.5is a vertical cross-sectional view of a structure of the capacitor136of the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the capacitor136may be disposed in the insulating film134above the hydrogen barrier film220. The capacitor136may include electrodes502and506. The capacitor136may also include an insulating film504between the electrodes502and506. The electrode506may be coupled to an interconnect510athrough an electrode508a. The electrode502may be coupled to an interconnect510bthrough an electrode508b. There may be another electrode508cthrough the insulating film134to couple the interconnect128to an interconnect510c. In some embodiments, the interconnects510a,510band510cmay be formed as interconnects138in one layer. In some embodiments, the interconnects510a,510band510cmay include aluminum (Al). In some embodiments, the capacitor136may be a metal-in-metal capacitor. The insulating film504may include material with high relative permittivity that has a greater dielectric constant (k) (high-k material) than silicon dioxide (SiO2). For example, the insulating film504may include, oxidized material containing transition metal and the like. For example, the transition metal may be any one of, for example, yttrium (Y), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), or tantalum (Ta). The hydrogen barrier film220may prevent hydrogen and/or hydrogen ions from the hydrogen supply film216through the insulating film218to reach the insulating film504of the capacitor136. Thus, chemical reduction of the high-k material in the insulating film504may be prevented and leakage currents around the capacitor136may be controlled. FIG.6is a vertical cross-sectional view of a structure of a portion600of the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the portion600may be fabricated in the FEOL of the memory device100. In the memory cell region104, the memory cell106including the transistor108and the capacitor110may be disposed on the substrate102. In some embodiments, the capacitor110may be an MIM capacitor. In some embodiments, the capacitor110may be formed at around 500° C. Above the capacitor110, the insulating film112may be formed. In the memory cell peripheral region114, the transistor116may be formed. Above the transistor116, the insulating film118may be formed. In some embodiments, the insulating films112and118may be formed in a same process, (n some embodiments, the insulating films112and118may include silicon dioxide (SiO2). The vias120that couple the transistor116to interconnects disposed in the insulating film118fabricated in the BEOL. FIG.7Ais a vertical cross-sectional view of a structure of a portion70aof the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, in the BEOL, the insulating film202may be formed above the portion600. The insulating film202may be a capping layer. The insulating film202may include a low-k material, such as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN), for example. The insulating film202may further include tetraethyl orthosilicate oxide (TEOS, Si(OC2H5)4). The interconnect124may be formed in the insulating film202. For example, forming the interconnect may be performed by a single-Damascene process. The insulating film202may be patterned with open trenches using photopatterning and dry-etching. A barrier layer and a seed layer of conductive material (e.g., copper (Cu)) may be deposited by a physical vapor deposition (PVD) method, such as sputtering. By electroplating, conductive material may be formed. After forming the conductive material, excess conductive material and the TEOS in the insulating film202may be removed by planarization, such as chemical-mechanical polishing (CMP) to form the interconnect124. The insulating film204may be formed above the interconnect124. The insulating film204may include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu) from the interconnect124. In some embodiments, the insulating film204may be formed by a chemical vapor deposition (CVD) method. The portion206may be formed above the insulating film204. The insulating film208of the portion206may include a low-k material, such as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN), for example. The insulating film208may further include tetraethyl orthosilicate oxide (TEOS, Si(OC2H5)4). The interconnect126may be formed in or above the insulating film208and the interconnect130may be formed in the insulating film208to couple the interconnect126to the interconnect124. In some embodiments, forming the interconnects126and130may be performed by a dual-Damascene process. The insulating film208may be patterned with open trenches using photopatterning and dry-etching. A barrier layer and a seed layer of conductive material (e.g., copper (Cu)) may be deposited by the PVD method, such as sputtering. Conductive material may be formed by electroplating. After forming the conductive material, excess conductive material and the TEOS in the insulating film208may be removed by planarization, such as chemical-mechanical polishing (CMP) to form the interconnects126and130. The insulating film210may be formed above the interconnect126. The insulating film210may include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu) from the interconnect126. In some embodiments, the insulating film210may be formed by the CVD method. In some embodiments, as shown inFIG.3BFIG.3D, a hydrogen supply film may be formed in the portion206. The hydrogen supply film may include a passivation plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si3N4) film that may be formed at a relatively low temperature (e.g., around 400° C.) compared to temperatures that layers in the FEOL is formed. FIG.7Bis a vertical cross-sectional view of a structure of a portion700bof the memory device100in accordance with one embodiment of the present disclosure. The portion700bincludes the portion212formed above the portion206. The insulating film214may include a low-k material, such as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN), for example. The insulating film214may further include tetraethyl orthosilicate oxide (TEOS, Si(OC2H5)4). The interconnect128may be formed in or above the insulating film214In some embodiments, forming the interconnect128may be performed by a dual-Damascene process. The insulating film214may be patterned with open trenches using photopatterning and dry-etching. A barrier layer and a seed layer of conductive material (e.g., copper (Cu)) may be deposited by the PVD method, such as sputtering. By electroplating, conductive material may be formed. After forming the conductive material, excess conductive material and the TEOS in the insulating film214may be removed by planarization, such as chemical-mechanical polishing (CMP) to form the interconnect128. The insulating film218may be formed above the interconnect128. The insulating film218may include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu) from the interconnect128. In some embodiments, the insulating film218may be formed by the CVD method. In some embodiments, as shown inFIG.4C-FIG.4E, a hydrogen supply film216may be formed in the portion212. The hydrogen supply film may include a passivation plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si3N4) film that may be formed at a relatively low temperature (e.g., around 400° C.) compared to temperatures that layers are formed in the FEOL. In some embodiments, as shown inFIG.4A-FIG.4E, one or more hydrogen barrier films220may be formed in the portion212. The one or more hydrogen barrier films may be formed above one or more hydrogen supply films in the portions206and212. The one or more hydrogen barrier films220may include at least one of aluminum oxide (Al2O3), aluminum oxynitride (AlON) or silicon nitride (Si3N4) formed by ALD or the PVD that may use temperatures lower than the temperature used in the FEOL. FIG.7Cis a vertical cross-sectional view of a structure of a portion700cof the memory device100in accordance with one embodiment of the present disclosure. The portion700cincludes the insulating film134above the portion122. In some embodiments, the insulating film134may include silicon dioxide (SiO2) formed by the CVD. The portion700cmay include the capacitor136above the portion122, disposed in or above the insulating film134. In some embodiments, the capacitor136is an MIM capacitor including the electrodes502and504and the insulating film504. The insulating film504may include high-k material. In some embodiments, the high-k material is oxidized transition metal and the like. For example, the transition metal may be any one of, for example, yttrium (Y), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), or tantalum (Ta). The electrode502may be formed by the CVD or the PVD on a lower portion of the insulating film134. The insulating film504may be formed above the electrode502by the CVD or the PVD. The electrode506may be formed above the insulating film504. After forming the electrodes502and506and the insulating film504between the electrode502and506, the insulating film504and the electrode506above the insulating film504may be patterned with open trenches using photopatterning and dry-etching, and an insulating film702, such as a barrier low-k (BLOk) film to prevent diffusion of conductive material, such as copper (Cu) may be formed. Further, the insulating films504and702may be patterned with open trenches using photopatterning and dry-etching, and an insulating film704, such as a barrier low-k (BLOk) film may be formed. Thus, the capacitor136may be formed. An upper portion of the insulating film134above the capacitor136may be formed and planarization, such as chemical-mechanical polishing (CMP), may be performed. The electrodes508a,508band508cofFIG.5may be formed in the insulating film134. For example, openings in the insulating film134using photopatterning and dry-etching are provided and a barrier film, such as titanium nitride (TiN), is provided inside the openings with the PVD. After depositing conductive material, such as tungsten (W) with the CVD, excess conductive material, such as the titanium nitride (TiN) and tungsten (W) may be removed by planarization, such as chemical-mechanical polishing (CMP) to form the electrodes508a,508band508c. The interconnect138including the interconnects510a,510band510cofFIG.5may be formed as one layer. In some embodiments, the interconnect138may include aluminum (Al). Using the PVD, a titanium nitride film, an aluminum film above the titanium nitride film and another titanium nitride film above may be formed, and the formed films are patterned with open trenches using photopatterning and dry-etching. A thermal process at around 400° C. (e.g., 350˜450° C.) may be performed. During the thermal process, such as annealing, hydrogen bonds (e.g., Si—H bonds, N—H bonds) in the one or more hydrogen supply films in the portions206and212may be disconnected and hydrogen may be released. The hydrogen and/or the hydrogen ions may reach around the transistors108and116inFIG.1, and prevent leakage currents of the transistors108and116. Thus, data reliability and refresh rates of memory device100inFIG.1may be improved. In some embodiments, a capacitor may be fabricated in the portion212.FIG.8is a vertical cross-sectional view of a structure of a capacitor802of the memory device100in accordance with one embodiment of the present disclosure. In some embodiments, the capacitor802may be disposed in the insulating film214. One or more hydrogen barrier films (not shown) may be included below the capacitor802in the portion206, such as above or below the insulating film210. One or more hydrogen supply films (not shown) may be included below the one or more hydrogen barrier films in the portion206. The capacitor802may include electrodes804and808. The capacitor802may also include an insulating film806between the electrodes804and808. The electrode804may be coupled to one of the interconnects128through an interconnect812. The electrode808may be coupled to one of the interconnects128through an interconnect810. There may be another interconnect814through the insulating film214to couple the interconnect126to one of the interconnects128. In some embodiments, the interconnects128,810,812and814may be formed by the dual-Damascene process. In some embodiments, the interconnects128,810,812and814may include copper (Cu). After forming interconnects128,810,812and814, excess conductive material and the TEOS in the insulating film214may be removed by planarization, such as chemical-mechanical polishing (CMP) to form the interconnect128. The insulating film218may be formed above the interconnect128. The insulating film218may include a BLOk film that may prevent diffusion of conductive material, such as copper (Cu) from the interconnect128. In some embodiments, the insulating film218may be formed by the CVD method. The insulating film134may be disposed above the portion212. In some embodiments, the insulating film134may include silicon dioxide (SiO2) formed by the CVD. An electrode816may be formed in the insulating film134, similarly to forming the electrodes508a,508band508capplying a barrier film such as titanium nitride (TiN) and filling conductive material, such as tungsten (W) with the CVD followed by planarization, such as chemical-mechanical polishing (CMP). The interconnect138may be formed above the electrode816that couples the interconnect138to the interconnect128. In some embodiments, the interconnect138may include aluminum (Al). A thermal process at around 400° C. (e.g., 350˜450° C.) may be performed. During the thermal process, such as annealing, hydrogen bonds (e.g., Si—H bonds, N—H bonds) in the one or more hydrogen supply films in the portions206and212may be disconnected and hydrogen may be released. The hydrogen and/or the hydrogen ions may reach around the transistors108and116inFIG.1, and prevent leakage currents of the transistors108and116. Thus, data reliability and refresh rates of memory device100inFIG.1may be improved. By providing a hydrogen supply film closer to a memory element, hydrogen and/or the hydrogen ions produced by the hydrogen supply film may reach around the memory element, and prevent leakage currents of around the memory element. Thus, data reliability and refresh rates of the memory element may be improved. At the same time, by providing a hydrogen barrier film between the hydrogen supply film and a capacitor including a high-k material, the capacitor's leakage currents due to chemical reduction of the high-k material may be prevented. Although various embodiments have been disclosed in the present disclosure, it will be understood by those skilled in the art that the scope of the disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above. | 42,363 |
11862555 | DETAILED DESCRIPTION The specific structural or functional description disclosed herein is merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms, and cannot be construed as limited to the embodiments set forth herein. Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings in order for those skilled in the art to be able to readily implement the technical spirit of the present disclosure. It will be understood that although the terms “first”, “second”, “third” etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present disclosure. Further, it will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Embodiments provide a semiconductor device having an easy manufacturing process, a stable structure, and improved characteristics, and a manufacturing method of the semiconductor device. FIGS.1A and1Bare block diagrams, schematically illustrating semiconductor devices, in accordance with embodiments of the present disclosure. Referring toFIGS.1A and1B, each of the semiconductor devices may include a peripheral circuit structure PC and a cell array CAR, which are disposed on a substrate SUB. The substrate SUB may be a single crystalline semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film that may be formed through a selective epitaxial growth process. The cell array CAR may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings may be electrically connected to a bit line, a source line, word lines, and select lines. Each of the cell strings may include memory cells and select transistors, which are connected in series. Each of the select lines may be used as a gate electrode of a select transistor corresponding thereto, and each of the word lines may be used as a gate electrode of a memory cell corresponding thereto. The peripheral circuit structure PC may include NMOS transistors, PMOS transistors, a resistor, and a capacitor, which are electrically connected to the cell array CAR. The NMOS transistors, the PMOS transistors, the resistor, and the capacitor may be used as elements that constitute a row decoder, a column decoder, a page buffer, and a control circuit. As shown inFIG.1A, the peripheral circuit structure PC may be disposed on a partial region of the substrate SUB without overlapping with the cell array CAR. Alternatively, as shown inFIG.1B, the peripheral circuit structure PC may be disposed between the cell array CAR and the substrate SUB. The peripheral circuit structure PC overlaps with the cell array CAR so that the area of the substrate SUB, which is occupied by the cell array CAR and the peripheral circuit structure PC, may be reduced. FIG.2is a sectional view, schematically illustrating a peripheral circuit structure. The peripheral circuit structure PC, shown inFIG.2, may be included in the peripheral circuit structure that is shown inFIG.1Aor be included in the peripheral circuit structure that is shown inFIG.1B. Referring toFIG.2, the peripheral circuit structure PC may include peripheral gate electrodes PG, a peripheral gate insulating layer PGI, junctions in, peripheral circuit lines PCL, and peripheral contact plugs PCP. The peripheral circuit structure PC may be covered by a peripheral circuit insulating layer PIL that may be formed on a substrate SUB. The peripheral gate electrodes PG may be respectively used as gate electrodes of an NMOS transistor and a PMOS transistor of the peripheral circuit PC. The peripheral gate insulating layer PGI may be disposed between each of the peripheral gate electrodes PG and the substrate SUB. The junctions in may be regions that are defined by injecting an n-type or p-type impurity into an active region. The junctions in may be disposed at both sides of each of the peripheral gate electrodes PG to be used as a source junction or a drain junction. The active region of the substrate SUB may be divided by an isolation layer ISO that may be formed in the substrate SUB. The isolation layer ISO may be formed of an insulating material. The peripheral circuit lines PCL, through the peripheral contact plugs PCP, may be electrically connected to transistors, a resistor, and a capacitor, constituting a circuit of the peripheral circuit structure PC. The peripheral circuit insulating layer PIL may include insulating layers that are stacked in a multi-layered structure. FIGS.3A and3Bare plan and sectional views, illustrating a semiconductor device, in accordance with an embodiment of the present disclosure. Referring toFIG.3A, the cell array (CAR shown inFIGS.1A and1B) of the semiconductor device may include a cell region Cell and a contact region CT. A plurality of channel plugs CP1and CP2may be regularly arranged in the cell region Cell. In addition, a first vertical structure VS1, with a line-like shape, disposed between the plurality of channel plugs CP1and the plurality of channel plugs CP2, may be disposed at a central portion of the cell region Cell. The second vertical structures VS2may be arranged at both end portions of the cell region Cell, substantially parallel to the first vertical structure VS1. The plurality of channel plugs CP1and CP2may be arranged between the second vertical structures VS2. Each of the plurality of channel plugs CP1and CP2may include a channel layer112and a memory layer111that surround the channel layer112. The first vertical structure VS1and the second vertical structure VS2may be insulating layers, and may be formed of, for example, an oxide layer. However, the composition of the insulating layers is not limited thereto. A plurality of contact plugs CT1and CT2may be regularly arranged on the contact region CT. In addition, at least one support structure119and a second vertical structure VS2may be arranged in a space between the plurality of contact plugs CT1and CT2on the contact region CT. In the embodiment, the support structure119and the second vertical structure VS2may be disposed between the plurality of contact plugs CT1and the plurality of contact plugs CT2. The support structure119may be formed of the same material as the first vertical structure VS1. The support structure119may be an insulating layer, and may be formed of, for example, an oxide layer. However, the composition of the insulating layer is not limited thereto. The support structure119and the second vertical structure VS2may be disposed in a line shape extending in one direction, in substantially the same direction as the first vertical structure VS1and second vertical structures VS2of the cell region Cell. The support structure119and the second vertical structure VS2may be substantially parallel to each other, without intersecting or overlapping with each other. Referring toFIG.3B, section A-A′ may be a section of the cell region Cell, and section B-B′ may be a section of the contact region CT. The cell region Cell of the semiconductor device may include a source line layer101, a stack structure105/123that is stacked on the source line layer101, channel plugs CP1and CP2that penetrate the stack structure105/123in a vertical direction to come in contact with the source line layer101, second vertical structures VS2that are vertically disposed at both end portions of the stack structure105/123to be in contact with the source line layer101, and a first vertical structure VS1that is disposed to penetrate a portion of the stack structure105/123that is disposed between the channel plugs CP1and CP2. The source line layer101may be a doped semiconductor layer. For example, the source line layer101may be a semiconductor layer that is doped with an n-type impurity. In an embodiment, the source line layer101may be formed by injecting an impurity into a surface of the substrate SUB shown inFIG.1A, or may be formed by depositing at least one doped silicon layer on the substrate SUB. In an embodiment, the source line layer101may be formed by forming an insulating layer on the peripheral circuit structure PC that is shown inFIG.1Band then depositing at least one doped silicon layer on the insulating layer. The stack structure105/123has a structure in which a plurality of gate conductive layers123and a plurality of interlayer insulating layers105may be stacked in an alternating manner, and the interlayer insulating layer105may be disposed at the lowermost and uppermost ends of the stack structure105/123. At least one gate conductive layer123that is disposed at the lowermost end portion of the stack structure105/123may be a source select line SSL, at least one gate conductive layer123that is disposed at the uppermost end portion of the stack structure105/123may be a drain select line DSL, and the rest of the gate conductive layers may be word lines WL. In the embodiment, the first two gate conductive layers123that are disposed at the lowermost end portion of the stack structure105/123may the source select lines SSL, the first two gate conductive layers123that are disposed at the uppermost end portion of the stack structure105/123may the drain select lines DSL, and the rest of the gate conductive layers may be word lines WL. The channel plugs CP1and CP2may penetrate the stack structure105/123and may be vertically arranged. Each of the channel plugs CP1and CP2may include a channel layer112and a memory layer111that surround the channel layer112. The first vertical structure VS1may be disposed to penetrate at least one gate conductive layer123that is disposed at the uppermost end portion of the stack structure105/123, disposed between the channel plugs CP1and CP2, is the at least one gate conductive layer123being used as the drain select line DSL. That is, the first vertical structure VS1electrically separates the portion of the drain select line DSL that is connected to the first channel plug CP1from the drain select line DSL that is connected to the second channel plug CP2. The contact region CT of the semiconductor device may include a source line layer101, a contact pad layer103, an isolation layer102that is disposed between the source line layer101and the contact pad layer103, a stack structure105/123that is stacked on the source line layer101, the isolation layer102, and the contact pad layer103, contact plugs CT1and CT2that penetrate the stack structure105/123in the vertical direction to come in contact with the contact pad layer103, a second vertical structure VS2that penetrates the stack structure105/123in the vertical direction to come in contact with the source line layer101, and at least one support structure119. The source line layer101and the contact pad layer103may be formed on the same layer. The source line layer101and the contact pad layer103may be electrically separated from each other by the isolation layer102that is disposed therebetween. The isolation layer102may be an insulating layer, and may be formed of, for example, an oxide layer. However, the composition of the insulating layer is not limited thereto. The contact pad layer103may be electrically connected to the peripheral circuit structure PC that is shown inFIGS.1A and1B. Each of the contact plugs CT1and CT2may include a conductive layer116for contact plugs and a barrier layer115that surrounds the conductive layer116for contact plugs. The barrier layer115may be formed on the sidewalls of the support structures119. In the semiconductor device, the support structure119for supporting the stack structure105/123may be disposed on the contact region CT and may be formed of the same material as the first vertical structure VS1(i.e., an oxide layer), so that the oxidation and expansion of the support structure119, due to heat that is generated in a subsequent process, may be prevented. FIGS.4to11are sectional and plan views, illustrating a manufacturing method of a semiconductor device, in accordance with an embodiment of the present disclosure. Referring toFIG.4, a source line layer101may be formed on a cell region Cell and a contact region CT of the semiconductor device. The source line layer101may be a doped semiconductor layer. For example, the source line layer101may be a semiconductor layer that is doped with an n-type impurity. In an embodiment, the source line layer101may be formed by injecting an impurity into a surface of the substrate SUB, as shown inFIG.1A, or may be formed by depositing at least one doped silicon layer on the substrate SUB. In an embodiment, the source line layer101may be formed by forming an insulating layer on the peripheral circuit structure PC, as shown inFIG.1B, and then depositing at least one doped silicon layer on the insulating layer. Subsequently, a contact pad layer may be formed may be formed by etching a portion of the source line layer101that may be formed on the contact region CT. The region in which the contact pad layer may be to be formed may be defined as a region that is electrically connected to the peripheral circuit structure PC, shown inFIGS.1A and1B. Subsequently, a contact pad layer103may be formed in the opening created by the etching and removal of the source line layer101. An isolation layer102may be formed between the contact pad layer103and the source line layer101such that the contact pad layer103and the source line layer101may be electrically separated from each other. The isolation layer102may be an insulating layer, and may be formed of, for example, an oxide layer. However, the composition of the insulating layer is not limited thereto. Subsequently, a stack structure105/107, the first material layers105and the second material layers107being stacked in an alternating manner, may be formed on the cell region Cell and the contact region CT. The second material layers107may be used to form conductive layers such as a word line, a select line, and a pad, and the first material layers105may be used to insulate the stacked conductive layers from each other. The first material layers105may be formed of a material with an etching rate that is higher than that of the second material layers107. In an embodiment, the first material layers105may include an insulating material such as an oxide, and the second material layers107may include a sacrificial material such as a nitride. Referring toFIGS.5A and5B, a first mask pattern109may be formed on the cell region Cell and the contact region CT of the stack structure105/107. The first mask pattern109has first openings OP1in order to form channel plugs in the cell region Cell. Referring toFIGS.6A and6B, first holes H1, penetrating the stack structure105/107, may be formed by etching the stack structure105/107by using the first mask pattern as a barrier. The etching of the contact region CT may be prevented by the first mask pattern, and therefore, no holes are formed. Subsequently, the first mask pattern may be removed. Subsequently, channel plugs CP1and CP2, each including a channel layer112and a memory layer111that sounds the channel layer112, may be formed in the first holes H1. For example, first, the memory layer111may be formed on sidewalls of the first holes H1. The memory layer111may include at least one of a charge blocking layer, a data storage layer, and a tunnel insulating layer. The data storage layer may include a floating gate such as silicon, a charge trap material such as nitride, a phase change material, nano dots, and the like. Subsequently, the channel plugs CP1and CP2may be formed by completely filling the first holes H1with the channel layer112. In another embodiment, the channel layer112may be formed in a structure in which the central regions of the first holes H1are opened, and a gap fill layer may be formed in the opened central regions. Subsequently, a second mask pattern113may be formed over the channel plugs CP1and CP2and the stack structure105/107in the cell region Cell and the stack structure105/107in the contact region CT. The second mask pattern113has second openings OP2in order to form contact plugs and support structures in the contact region CT. In the embodiment of the present disclosure, a case where the support structure is formed in a line shape is described as an example. However, the present disclosure is not limited thereto. For example, the support structure may be formed in various patterns such as a circular shape, an elliptical shape, a rectangular shape, a diamond shape, etc. Referring toFIG.7, second holes H2, penetrating the stack structure105/107, may be formed by etching the stack structure105/107on the contact region CT by using the second mask pattern as a barrier. Etching of the cell region Cell may be prevented by the second mask pattern. Subsequently, the second mask pattern is removed. Subsequently, a barrier layer115may be formed on the sidewalls of the second holes H2. Then, contact plugs CT1and CT2, connected to the contact pad layer103, may be formed by filling the second holes H2with a conductive layer116. The same process of forming the barrier layer115and the conductive layer116for contact plugs may be used to form the support structures that are connected to the source line layer101. The forming of the contact plugs and the support structures may occur during the same process. That is, the barrier layer115may be formed on the sidewalls of the second holes H2that expose the source line layer101, and the same conductive layer116that is used for contact plugs may be formed inside of the second holes H2, connected to the source line layer101. Referring toFIGS.8A and8B, a third mask pattern117may be formed over the channel plugs CP1and CP2and the stack structure105/107in the cell region Cell and the contact plugs CT1and CT2and the stack structure105/107in the contact region CT. The third mask pattern117may be formed to have third openings OP3to form additional openings to subsequently form a first vertical structure in the cell region Cell, between the first channel plug CP1and the second channel plug CP2, and support structures in the contact region CT. The third opening OP in the cell region Cell may be formed in a line shape, as shown inFIG.8B, and the third opening OP3of the contact region CT may be formed in a line shape, as shown inFIG.8B. In another embodiment, the third opening OP3of the contact region CT may be formed such that a portion of the conductive layer116for contact plugs, which may be formed in the region in which the support structure is to be formed, may be exposed. Referring toFIG.9, a first slit SI1may be formed by etching a portion of an upper end portion of the stack structure105/107, formed between the channel plugs CP1and CP2in the cell region Cell, using the third mask pattern as a barrier. The first slit SI1may be formed to penetrate at least one second material layer107that is disposed at an uppermost end of the stack structure105/107at which a drain select line is to be formed. Subsequently, third holes H3may be formed by etching the conductive layer116, which is exposed in the contact region CT, using the third mask pattern as the barrier. The barrier layer115may remain on sidewalls of the third holes H3. Subsequently, a first vertical structure VS1and support structures119may be simultaneously formed by filling the first slit SI1and third holes H3with an insulating layer. The first vertical structure VS1and the support structures119may be formed of an oxide layer. However, the composition of the insulating layer is not limited thereto. Referring toFIGS.10A and10B, a fourth mask pattern121may be formed over the channel plugs CP1and CP2, the first vertical structure VS1, and the stack structure105/107in the cell region Cell. The fourth mask pattern121may also formed over the contact plugs CT1and CT2, the support structures119, and the stack structure105/107in the contact region CT. The fourth mask pattern121may be formed to have fourth openings OP4at both end portions of a region in which the channel plugs CP1and CP2are disposed in the cell region Cell. The fourth mask pattern121may also be formed to have a fourth opening OP4at a region between the support structures119in the contact region CT. That is, the fourth mask pattern121may be formed to have the fourth openings OP4in order to form second vertical structures. The fourth openings OP4may be formed in a line shape, as shown inFIG.10B, and may be disposed to be substantially parallel to each other or disposed substantially vertically to each other. In different embodiments, the fourth openings OP4may be formed in various shapes. Subsequently, second slits SI2may be formed by etching the stack structure105/107through the fourth openings OP4by using the fourth mask pattern121as a barrier. The second slit SI2exposes the sidewalls of the first material layer105and the second material layer107. Subsequently, the second material layers107may be removed through the second slit SI2, and the gate conductive layers123may be formed in place of the second material layers. At least one gate conductive layer123that is disposed at a lowermost end portion among the gate conductive layers123may be a lower select line (source select line), at least one gate conductive layer123that is disposed at an upper end portion and separated by the first vertical structure VS1may be an upper select line (drain select line), and the rest of the gate conductive layers123may be word lines. Referring toFIG.11, second vertical structures VS2may be formed by filling the second slits with an insulating layer. The second vertical structure VS2may be formed of an oxide layer. However, the composition of the insulating layer is not limited thereto. As described above, in accordance with the manufacturing method of the semiconductor device in accordance with the embodiment of the present disclosure, the support structure119may be formed of the same material as the first vertical structure VS1, i.e., an oxide layer, so that the oxidation and the expansion of the support structure119, due to the heat that is generated in a subsequent process, may be prevented. Further, although the conductive layer116for contact plugs may be formed in the hole in which the support structure119is to be formed in the process of forming the contact plugs CT1and CT2, the conductive layer116for contact plugs can be removed using the mask pattern for forming the first vertical structure VS1. FIGS.12A and12Bare plan views, illustrating a semiconductor device, in accordance with another embodiment of the present disclosure. Referring toFIG.12A, a plurality of support structures119, formed in a quadrangular shape, may be disposed. Also, the support structures119may be disposed in a line, adjacent to a second vertical structure VS2, as shown in the drawing. Additionally, the support structures119may be disposed in spaces between contact plugs CT1and CT2. That is, the support structures119may also be disposed in a space between the contact plugs CT1and a space between the contact plugs CT2. In different embodiments, the support structures119may be formed in various shapes, e.g., a circular shape, an elliptical shape, a cross (+) shape, and the like, in addition to the quadrangular shape. Referring toFIG.12B, the support structures119may be disposed to surround the periphery of the contact plugs CT1and CT2. Although a case where one support structure119is disposed to surround the periphery of a plurality of contact plugs is illustrated inFIG.12B, the present disclosure is not limited thereto. For instance, one support structure119may be formed in a concave shape to surround to the periphery of one contact plug. FIG.13is a view, illustrating memory blocks included in a semiconductor device, in accordance with an embodiment of the present disclosure. The semiconductor device may include a plurality of memory blocks BLK1to BLKz. The plurality of memory blocks BLK1to BLKz may be arranged to be spaced apart from each other along a direction Y in which bit lines BL1to BLm extend. For example, first to zth memory blocks BLK1to BLKz may be arranged to be spaced apart from each other along a second direction Y, and include a plurality of memory cells stacked along a third direction Z. The first to zth memory blocks BLK1to BLKz may be spaced apart from each other by using slits. Each of the plurality of memory blocks BLK1and BLKz may include a plurality of channel plugs, a plurality of contact plugs, and a plurality of support structures as shown inFIGS.3A and3BorFIGS.12Aand12B. FIG.14is a block diagram illustrating a configuration of a memory system in accordance with an embodiment of the present disclosure. Referring toFIG.14, the memory system1000in accordance with the embodiment of the present disclosure includes a memory device1200and a controller1100. The memory device1200may be used to store data information having various data formats such as texts, graphics, and software codes. The memory device1200may be the semiconductor device described with reference toFIG.1A,1B,2,3A, and3B,12A, or12B, and be manufactured according to the manufacturing method described with reference toFIGS.4to11. The structure and manufacturing method of the memory device1200are the same as described above, and therefore, their detailed descriptions will be omitted. The controller1100may be connected to a host and the memory device1200, and may be configured to access the memory device1200in response to a request from the host. For example, the controller1100may be configured to control reading, writing, erasing, and background operations of the memory device1200. The controller1100includes a random access memory (RAM)1110, a central processing unit (CPU)1120, a host interface1130, an error correction code (ECC) circuit1140, a memory interface1150, and the like. The RAM1110may be used as a working memory of the CPU1120, a cache memory between the memory device1200and the host, and a buffer memory between the memory device1200and the host. The RAM1110may be replaced with a static random access memory (SRAM), a read only memory (ROM), etc. The CPU1120may be configured to control overall operations of the controller1100. For example, the CPU1120may be configured to operate firmware such as a flash translation layer (FTL) stored in the RAM1110. The host interface1130may be configured to interface with the host. For example, the controller1100communicates with the host using at least one of a variety of interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a private protocol. The ECC circuit1140may be configured to detect and correct an error included in data that is read from the memory device1200, using an error correction code (ECC). The memory interface1150may be configured to interface with the memory device1200. For example, the memory interface1150includes an NAND interface or NOR interface. The controller1100may further include a buffer memory (not shown) for temporarily storing data. The buffer memory may be used to temporarily store data transferred to the outside through the host interface1130or data transferred from the memory device1200through the memory interface1150. The controller1100may further include a ROM that stores code data for interfacing with the host. As described above, the memory system1000in accordance with the embodiment of the present disclosure includes the memory device1200having an improved degree of integration and improved characteristics, and thus the degree of integration and characteristics of the memory system1000can be improved. FIG.15is a block diagram illustrating a configuration of a memory system in accordance with an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with those described above will be omitted. Referring toFIG.15, the memory system1000′ in accordance with the embodiment of the present disclosure includes a memory device1200′ and a controller1100. The controller1100includes a RAM1110, a CPU1120, a host interface1130, an ECC circuit1140, a memory interface1150, and the like. The memory device1200′ may be a nonvolatile memory. The memory device1200′ may be the semiconductor device described with reference toFIG.1A,1B,2,3A, and3B,12A, or12B, and be manufactured according to the manufacturing method described with reference toFIGS.4to11. The structure and manufacturing method of the memory device1200′ are the same as described above, and therefore, their detailed descriptions will be omitted. The memory device1200′ may be a multi-chip package including a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups, which are configured to communicate with the controller1100over first to kth channels (CH1to CHk). In addition, memory chips included in one group may be configured to communicate with the controller1100over a common channel. For reference, the memory system1000′ may be modified such that one memory chip may be connected to one channel. As described above, the memory system1000′ in accordance with the embodiment of the present disclosure includes the memory device1200′ having an improved degree of integration and improved characteristics, and thus the degree of integration and characteristics of the memory system1000′ can be improved. Particularly, the memory device1200′ may be configured as a multi-chip package, so that the data storage capacity of the memory system1000′ can be increased, and the operation speed of the memory system1000′ can be improved. FIG.16is a block diagram illustrating a configuration of a computing system in accordance with an embodiment of the present disclosure. Hereinafter, description of contents overlapping with those described above will be omitted. Referring toFIG.16, the computing system2000in accordance with the embodiment of the present disclosure includes a memory device2100, a CPU2200, a RAM2300, a user interface2400, a power supply2500, a system bus2600, and the like. The memory device2100stores data provided through the user interface2400, data processed by the CPU2200, and the like. In addition, the memory device2100may be electrically connected to the CPU2200, the RAM2300, the user interface2400, the power supply2500, and the like through the system bus2600. For example, the memory device2100may be connected to the system bus2600through a controller (not shown) or directly. When the memory device2100is directly connected to the system bus2600, a function of the controller may be performed by the CPU2200, the RAM2300, etc. The memory device2100may be a nonvolatile memory. The memory device2100may be the semiconductor device described with reference toFIG.1A,1B,2,3A, and3B,12A, or12B, and be manufactured according to the manufacturing method described with reference toFIGS.4to11. The structure and manufacturing method of the memory device2100are the same as described above, and therefore, their detailed descriptions will be omitted. The memory device2100may be a multi-chip package including a plurality of memory chips as described with reference toFIG.9. The computing system2000configured as described above may be a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device for communicating information in a wireless environment, one of a variety of electronic devices constituting a home network, one of a variety of electronic devices constituting a computer network, one of a variety of electronic devices constituting a telematics network, an RFID device, etc. As described above, the computing system2000in accordance with the embodiment of the present disclosure includes the memory device2100having an improved degree of integration and improved characteristics, and thus characteristics of the computing system2000can also be improved. FIG.17is a block diagram illustrating a configuration of a computing system in accordance with an embodiment of the present disclosure. Referring toFIG.17, the computing system3000in accordance with the embodiment of the present disclosure includes a software layer including an operating system3200, an application3100, a file system3300, a translation layer3400, and the like. In addition, the computing system3000includes a hardware layer of a memory device3500, etc. The operating system3200may manage software resources, hardware resources, etc. of the computing system3000, and control program execution of a central processing unit. The application3100may be one of a variety of application programs running on the computing system3000, and may be a utility executed by the operating system3200. The file system3300means a logical structure for managing data, files, etc. in the computing system3000, and organizes the data or files stored in the memory device3500according to a rule. The file system3300may be determined depending on the operating system3200used in the computing system3000. For example, when the operating system3200is one of Windows operating systems of Microsoft, the file system3300may be a file allocation table (FAT) or a NT file system (NTFS). When the operating system3200is one of Unix/Linux operating systems, the file system3300may be an extended file system (EXT), a Unix file system (UFS), or a journaling file system (JFS). In this drawing, the operating system3200, the application3100, and the file system3300are shown as individual blocks. However, the application3100and the file system3300may be included in the operating system3200. The translation layer3400translates an address into a form suitable for the memory device3500in response to a request from the file system3300. For example, the translation layer3400translates a logical address generated by the file system3300into a physical address of the memory device3500. Mapping information between the logical address and the physical address may be stored as an address translation table. For example, the translation layer3400may be a flash translation layer (FTL), a universal flash storage link layer (ULL), etc. The memory device3500may be a nonvolatile memory. The memory device3500may be the semiconductor device described with reference toFIG.1A,1B,2,3A, and3B,12A, or12B, and be manufactured according to the manufacturing method described with reference toFIGS.4to11. The structure and manufacturing method of the memory device3500are the same as described above, and therefore, their detailed descriptions will be omitted. The computing system3000configured as described above may be divided into an operating system layer performed in an upper level region and a controller layer performed in a lower level region. The application3100, the operating system3200, and the file system3300are included in the operating system layer, and may be driven by a working memory of the computing system3000. In addition, the translation layer3400may be included in the operating system layer or the controller layer. As described above, the computing system3000in accordance with the embodiment of the present disclosure includes the memory device3500having an improved degree of integration and improved characteristics, and thus characteristics of the computing system3000can also be improved. In accordance with the present disclosure, a semiconductor device having a stable structure can be manufactured, and manufacturing cost can be reduced by simplifying manufacturing procedures. The exemplary embodiments of the present disclosure have been described in the drawings and specification. Although specific terminologies are used here, those are only to explain the embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications can be made on the basis of the technological scope of the present disclosure in addition to the embodiments disclosed herein. So far as not being differently defined, all terms used herein including technical or scientific terminologies have meanings that they are commonly understood by those skilled in the art to which the present disclosure pertains. The terms having the definitions as defined in the dictionary should be understood such that they have meanings consistent with the context of the related technique. So far as not being clearly defined in this application, terms should not be understood in an ideally or excessively formal way. | 38,275 |
11862556 | DETAILED DESCRIPTION Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings. FIGS.1A and1Bare schematic cross-sectional views of a semiconductor device according to example embodiments. FIGS.2A and2Bare enlarged views of a portion of a semiconductor device according to example embodiments.FIGS.2A and2Billustrate region “D” and region “E” illustrated inFIG.1A, respectively. Referring toFIGS.1A to2B, a semiconductor device100may include a peripheral circuit region PERI including a first substrate201, a memory cell region CELL including a second substrate101, a through interconnection region TR including a first through via165electrically connecting the peripheral circuit region PERI to the memory cell region CELL, and a ground interconnection structure GI connecting the first substrate201and the second substrate101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In example embodiments, alternatively, the memory cell region CELL may be disposed below the peripheral circuit region PERI. The through interconnection region TR may be disposed to extend from the memory cell region CELL to the peripheral circuit region PERI. The ground interconnection structure GI may be disposed to extend from a lower region of the memory cell region CELL to the peripheral circuit region PERI. The peripheral circuit region PERI may include the first substrate201, source/drain regions205and device isolation layers210disposed in the first substrate201, circuit devices220disposed on the first substrate201, a peripheral region insulating layer290, a lower protective layer295, and a first interconnection structure LI. The first substrate201may have an upper surface extending in an x direction and a y direction. An active region may be defined by the device isolation layers210on the first substrate201. The source/drain regions205including impurities may be disposed in a portion of the active region. The first substrate201may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate201may also be provided as a bulk wafer or an epitaxial layer. The circuit devices220may include a planar transistor. Each of the circuit devices220may include a circuit gate dielectric layer222, a spacer layer224, and a circuit gate electrode225. The source/drain regions205may be disposed in the first substrate201on both sides of the circuit gate electrode225. The peripheral region insulating layer290may be disposed on the circuit device220on the first substrate201. The peripheral region insulating layer290may include first and second peripheral region insulating layers292and294, and each of the first and second peripheral region insulating layers292and294may also include a plurality of insulating layers. The peripheral region insulating layer290may be formed of an insulating material. The lower protective layer295may be disposed on an upper surface of third lower interconnection lines286between the first and second peripheral region insulating layers292and294. In example embodiments, the lower protective layer295may further be disposed on upper surfaces of first and second lower interconnection lines282and284. The lower protective layer295may be a layer for preventing contamination caused by a metal material of lower interconnection lines280disposed on a lower portion of the lower protective layer295. The lower protective layer295may be formed of a material different from a material of the peripheral region insulating layer290. For example, the lower protective layer295may include silicon nitride, for example. The first interconnection structure LI may be an interconnection structure electrically connected to the circuit devices220and the source/drain regions205. The first interconnection structure LI may include lower contact plugs270each having a cylindrical shape and lower interconnection lines280each having a line shape. The lower contact plugs270may include first to third lower contact plugs272,274, and276. The first lower contact plugs272may be disposed on the circuit devices220and the source/drain regions205, the second lower contact plugs274may be disposed on the first lower interconnection lines282, and the third lower contact plugs276may be disposed on the second lower interconnection lines284. The lower interconnection lines280may include first to third lower interconnection lines282,284, and286. The first lower interconnection lines282may be disposed on the first lower contact plugs272, the second lower interconnection lines284may be disposed on the second lower contact plugs274, and the third lower interconnection lines286may be disposed on the third lower contact plugs276. The first interconnection structure LI may include a conductive material. For example, the first interconnection structure LI may include tungsten (W), copper (Cu), aluminum (Al), or the like, for example, and each of the elements may further include a diffusion barrier. However, in example embodiments, the numbers of layers and arrangement forms of the lower contact plugs270and the lower interconnection lines280constituting the first interconnection structure LI may be varied. The memory cell region CELL may include a second substrate101having a first region A and a second region B, first and second horizontal conductive layers102and104on the second substrate101, gate electrodes130stacked on the second substrate101, first and second separation regions MS1and MS2extending while penetrating a stack structure of the gate electrodes130, upper separation regions SS penetrating a portion of the stack structure, channel structures CH disposed to penetrate the stack structure, and a second interconnection structure UI electrically connected to the gate electrodes130and the channel structures CH. The memory cell region CELL may further include a substrate insulating layer105, interlayer insulating layers120alternately stacked with the gate electrodes130on the second substrate101, gate contacts162connected to the gate electrodes130, a substrate contact164connected to the second substrate101, a cell region insulating layer190covering the gate electrodes130, and an upper protective layer195. The memory cell region CELL may further have a third region C on an external side of the second substrate101, and a through interconnection structure such as a second through via167for connecting the memory cell region CELL to the peripheral circuit region PERI may be disposed in the third region C. The first region A of the first substrate201may be a region in which the gate electrodes130may be vertically stacked and the channel structures CH may be disposed, and memory cells may also be disposed in the first region A. The second region B may be a region in which the gate electrodes130may extend by different lengths, and may be a region for electrically connecting the memory cells to the peripheral circuit region PERI. The second region B may be disposed on at least one end of the first region A in at least one direction, in the x direction, for example. The second substrate101may have an upper surface extending in the x direction and they direction. The second substrate101may include a semiconductor material, such as a group IV semiconductor, a group compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate101may further include impurities. The second substrate101may be provided as a polycrystalline semiconductor layer such as a polycrystalline silicon layer, or an epitaxial layer. The second substrate101may also be provided as a bulk semiconductor substrate. The second substrate101may have a substantially planar upper surface, and a lower surface which may not be planar as a result of a protrusion by an upper via GV. The first and second horizontal conductive layers102and104may be stacked and disposed on the upper surface of the second substrate101. At least a portion of the first and second horizontal conductive layers102and104may function as a portion of a common source line of the semiconductor device100. For example, at least a portion of the first and second horizontal conductive layers102and104may function as common source lines along with the second substrate101, for example. As illustrated in the enlarged view inFIG.1B, the first horizontal conductive layer102may be directly connected to a channel layer140in a circumference of the channel layer140. The first and second horizontal conductive layers102and104may include a semiconductor material, such as a polycrystalline silicon, for example. In this case, at least the first horizontal conductive layer102may be a doped layer, and the second horizontal conductive layer104may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer102. According to example embodiments, the first and second horizontal conductive layers102and104may not extend across the entire span of the second region B of the second substrate101. For example, an insulating layer may be disposed in a portion of the second region B instead of the first and second horizontal conductive layers102and104. The substrate insulating layer105may be disposed in a region formed by partially removing the second substrate101and the first and second horizontal conductive layers102and104, and may be disposed to be surrounded by the second substrate101and the first and second horizontal conductive layers102and104. A lower surface of the substrate insulating layer105may be coplanar with the lower surface of the second substrate101, or may be disposed on a level lower than a level of the lower surface of the second substrate101. In some example embodiments, the substrate insulating layer105may be disposed in a region formed by only removing the second substrate101. In this case, the substrate insulating layer105may have an upper surface substantially coplanar with the upper surface of the second substrate101, and another insulating layer surrounded by the first and second horizontal conductive layers102and104may further be disposed on an upper portion. The substrate insulating layer105may be formed of an insulating material. For example, the substrate insulating layer105may include silicon oxide, silicon oxynitride, or silicon nitride. The gate electrodes130may be vertically spaced apart from each other and stacked on the second substrate101and may constitute a stack structure. The gate electrodes130may include electrodes sequentially constituting gates of ground select transistors, memory cells (e.g., memory cell transistors), and string select transistors. The number of the gate electrodes130constituting the memory cells may be determined depending on capacity of the semiconductor device100. The number of the gate electrodes130forming the string select transistors (i.e., the number of string select lines) and the number of the gate electrodes forming the ground select transistors (i.e., the number of ground select lines) may be one or more (e.g., two), and such gate electrodes130may have a structure the same as or different from a structure of the gate electrodes130of the memory cells. Also, the gate electrodes130may further include a gate electrode130disposed on an upper portion of the gate electrode130constituting the string select transistor and/or below a lower portion of the gate electrode130constituting the ground select transistor, and form erase transistors used in an erase operation using a gate induced drain leakage (GIDL) phenomenon. Also, some of the gate electrodes130adjacent to the gate electrode130constituting the string select transistor (e.g., adjacent the string select line(s)) or the ground select transistor (e.g., adjacent the ground select line(s)), for example, may be dummy gate electrodes. The gate electrodes130may be spaced apart from each other vertically and stacked on the first region A, may extend from the first region A to the second region B by different lengths, and may form a staircase-shaped stepped structure. The gate electrodes130may form a stepped structure between the gate electrodes130in the x direction as illustrated inFIG.1A. In some example embodiments, a certain number of the gate electrodes130such as two to six gate electrodes130, for example, may form a single gate group and may form a stepped structure between the gate groups in the x direction. In this case, the gate electrodes130forming the single gate group may be disposed to have a stepped structure also in the y direction. By the stepped structure, the gate electrodes130may form a staircase form in which the gate electrodes130disposed in a lower portion extend longer than the gate electrodes130disposed in an upper portion (i.e., in the z direction) and may provide ends exposed from the interlayer insulating layers120to an upper portion. In some example embodiments, the gate electrodes130may have an increased thickness on the ends (i.e., in the x and/or y directions). The gate electrodes130may include a metal material, tungsten (W), for example. In example embodiments, the gate electrodes130may include polycrystalline silicon or a metal silicide material. In example embodiments, the gate electrodes130may further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. The interlayer insulating layers120may be disposed between the gate electrodes130. The interlayer insulating layers120may also be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate101and may extend in the x direction, similarly to the gate electrodes130. The interlayer insulating layers120may include an insulating material such as silicon oxide or silicon nitride. The first and second separation regions MS1and MS2may be disposed to penetrate the gate electrodes130and may extend in the x direction in the first region A and the second region B. The first and second separation regions MS1and MS2may be disposed to be parallel to each other. As illustrated inFIG.1B, the first and second separation regions MS1and MS2may penetrate the entire gate electrodes130stacked on the second substrate101and may be connected to the second substrate101. The first separation regions MS1may extend as a single layer along the first region A and the second region B, and the second separation regions MS2may extend only to a portion of the second region B or may be disposed intermittently in the first region A and the second region B. However, in example embodiments, an arrangement order, an arrangement interval, or the like, of the first and second separation regions MS1and MS2may be varied. A separation insulating layer110may be disposed in the first and second separation regions MS1and MS2. In example embodiments, the separation insulating layer110may have a shape in which a width may decrease towards the second substrate101due to a high aspect ratio. However, in example embodiments, a conductive layer may further be disposed within the separation insulating layers110in the first and second separation regions MS1and MS2. In this case, the conductive layer may function as a common source line or a contact plug connected to a common source line. The upper separation regions SS may extend in the x and z directions between the first separation regions MS1and the second separation regions MS2. The upper separation regions SS may be disposed in a portion of the second region B and in the first region A to penetrate a portion of the gate electrodes130including an uppermost gate electrode130of the gate electrodes130. The upper separation regions SS may separate three gate electrodes130in the y direction in total, for example, as illustrated inFIG.1B. However, the number of the gate electrodes130separated by the upper separation regions SS may be varied in example embodiments. The upper separation regions SS may include an upper separation insulating layer107. Each of the channel structures CH may form a single memory cell string, and may be spaced apart from each other while forming rows and columns on the first region A. The channel structures CH may be disposed to form a lattice pattern or may be disposed in a zigzag pattern in one direction on an x-y plane. The channel structures CH may have a cylindrical shape, and may have an inclined side surface of which a width decreases towards the second substrate101depending on an aspect ratio. In example embodiments, dummy channels which do not constitute a memory cell string may be disposed on the end of the first region A adjacent to the second region B and may also be disposed on the end of the second region B. As illustrated in the enlarged view illustrated inFIG.1B, a channel layer140may be disposed in the channel structures CH. The channel layer140in the channel structures CH may have an annular shape surrounding a channel insulating layer150disposed therein, but in example embodiments, the channel layer140may have a columnar shape such as a cylindrical shape or a prism shape without the channel insulating layer150inside. The channel layer140may be connected to the first horizontal conductive layer102in a lower portion. The channel layer140may include a semiconductor material such as polycrystalline silicon or single crystalline silicon. The channel structures CH extend in the z direction and are disposed linearly in the y direction between the first and second separation regions MS1and MS2. The upper separation regions SS may be electrically separated from each other by a second interconnection structure UI connected to channel pads155. In the channel structures CH, the channel pads155may be disposed on an upper portion of the channel layer140. The channel pads155may be disposed to cover an upper surface of the channel insulating layer150and to be electrically connected to the channel layer140. The channel pads155may include doped polycrystalline silicon, for example. A gate dielectric layer145may be disposed between the gate electrodes130and the channel layer140. The gate dielectric layer145may include a tunneling layer, an electric charge storage layer, and a blocking layer, sequentially stacked from the channel layer140. The tunneling layer may tunnel an electric charge to the electric charge storage layer, and may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The electric charge storage layer may be an electric charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In example embodiments, at least a portion of the gate dielectric layer145may extend in a horizontal direction along the gate electrodes130. A cell region insulating layer190may cover the second substrate101, the gate electrodes130on the second substrate101, and the peripheral region insulating layer290. The cell region insulating layer190may include first and second cell region insulating layers192and194, and each of the first and second cell region insulating layers192and194may also include a plurality of insulating layers. The cell region insulating layer190may be formed of an insulating material. An upper protective layer195may be disposed on an upper surface of first upper interconnection lines182between the first and second cell region insulating layers192and194. In example embodiments, the upper protective layer195may further be disposed on an upper surface of second upper interconnection lines184. The upper protective layer195may be a layer for preventing contamination caused by a metal material of upper interconnection lines180disposed on a lower portion. The upper protective layer195may be formed of an insulating material different from that of the cell region insulating layer190, and may include silicon nitride, for example. Gate contacts162may be connected to the gate electrodes130in the second region B. For example, each of the plurality of gate contacts162may be disposed to penetrate at least a portion of the first cell region insulating layer192and connect to one of the gate electrodes130exposed to an upper portion, respectively. The substrate contact164may be connected to the second substrate101on an end of the second region B. The substrate contact164may penetrate at least a portion of the first cell region insulating layer192and may be connected to the second substrate101. The substrate contact164may apply an electrical signal to a common source line including the second substrate101, for example. The second interconnection structure UI may be an interconnection structure electrically connected to the gate electrodes130and the channel structures CH. The second interconnection structure UI may include upper contact plugs170each having a cylindrical shape and upper interconnection lines180each having a line shape. The upper contact plugs170may include first to third upper contact plugs172,174, and176. The first upper contact plugs172may be disposed on the channel pads155, the gate contacts162, and the substrate contact164. The second upper contact plugs174may be disposed on the first upper contact plugs172, and the third upper contact plugs176may be disposed on the first upper interconnection lines182. The upper interconnection lines180may include the first and second upper interconnection lines182and184. The first upper interconnection lines182may be disposed on the second upper contact plugs174, and the second upper interconnection lines182may be disposed on the third upper contact plugs176. The second interconnection structure UI may include a conductive material. For example, the second interconnection structure UI may include tungsten (W), copper (Cu), aluminum (Al), or the like, for example, and each may further include a diffusion barrier layer. In example embodiments, the numbers of layers and arrangement forms of the lower contact plugs170and the lower interconnection lines180constituting the second interconnection structure UI may be varied. The through interconnection region TR may be a region including a through interconnection structure for electrically connecting the memory cell region CELL and the peripheral circuit region PERI. The through interconnection region TR may include a first through via165penetrating the second substrate101from an upper portion of the memory cell region CELL and extending in a z direction and an insulating region surrounding the first through via165. The insulating region may include sacrificial insulating layers118, interlayer insulating layers120disposed parallel to the sacrificial insulating layers118, and a substrate insulating layer105. The size, arrangement, and shape of the through interconnection region TR may vary (e.g., in accordance with the design). InFIG.1A, the through interconnection region TR may be disposed in the second region B, but the invention is not limited thereto, and the through interconnection region TR may also be disposed in the first region A. The through interconnection region TR may be spaced apart from the first and second separation regions MS1and MS2. For example, the through interconnection region TR may be disposed in a central portion of first region A between a pair of the first separation regions MS1adjacent to each other in the y direction. Accordingly, the sacrificial insulating layers118may remain in the through interconnection region TR. The first through via165may partially penetrate a first cell region insulating layer192, the insulating region, a lower protective layer295, and a second peripheral region insulating layer294from an upper portion, and may extend perpendicularly to the upper surface of the second substrate101. An upper end of the first through via165may be connected to the second interconnection structure UI, and a lower end may be connected to the first interconnection structure LI. In example embodiments, in the through interconnection region TR, the number, an arrangement form, and a shape of the first through via165may be varied. The first through via165may include a conductive material. For example, the first through via165may include a metal material such as tungsten (W), copper (Cu), aluminum (Al), or the like. The sacrificial insulating layers118may be disposed on a level the same as a level of the gate electrodes130and may have a thickness the same as a thickness of the gate electrodes130, and a side surface thereof may be in contact with the gate electrodes130on a boundary of the through interconnection region TR. The sacrificial insulating layers118may be alternately stacked with the interlayer insulating layers120and may form an insulating region. The sacrificial insulating layers118may be disposed with a width the same as or different from a width of the substrate insulating layer105. The sacrificial insulating layers118may be formed of an insulating material different from an insulating material of the interlayer insulating layers120, and may include silicon oxide, silicon nitride, or silicon oxynitride, for example. The second through via167may be disposed in the third region C of the memory cell region CELL, an external side region of the second substrate101, and may extend to the peripheral circuit region PERI. The second through via167may connect the second interconnection structure UI and the first interconnection structure LI, similarly to the first through via165of the through interconnection region TR. However, the second through via167may penetrate only a portion of the first cell region insulating layer192and the second peripheral region insulating layer294from an upper portion. The second through via167may include a conductive material. For example, the second through via167may include a metal material such as tungsten (W), copper (Cu), aluminum (Al), or the like, for example. The ground interconnection structure GI may be disposed throughout the peripheral circuit region PERI and the memory cell region CELL to connect the first substrate201and the second substrate101. The ground interconnection structure GI may perform a function of grounding the second substrate101in a process of manufacturing the semiconductor device100. The ground interconnection structure GI may include a lower interconnection structure corresponding to the first interconnection structure LI by similarly including lower contact plugs270and lower interconnection lines280. The ground interconnection structure GI may further include an upper via GV connected to the third lower interconnection lines286of the lower interconnection lines280. The ground interconnection structure GI may be may be referred to as a third interconnection structure, distinguished from the first and second interconnection structures LI and UI. Although only one ground interconnection structure GI is illustrated inFIG.1A, a plurality of ground interconnection structures GI may be disposed and spaced apart from each other in the semiconductor device100. The ground interconnection structure GI may be disposed on a lower portion of the second region B of the second substrate101. Also, the ground interconnection structure GI may be disposed on a lower portion of the first and second horizontal conductive layers102and104in a region in which the first and second horizontal conductive layers102and104extend longer than the gate electrodes130, but the invention is not limited thereto. In example embodiments, the ground interconnection structure GI may also be disposed on a lower portion of the first region A of the second substrate101. The ground interconnection structure GI may be spaced apart from the circuit devices220of the peripheral circuit region PERI. The upper via GV may penetrate the second peripheral region insulating layer294and the lower protective layer295and may be directly connected to the third lower interconnection line286. The upper via GV may be integrated with the second substrate101of the memory cell region CELL. As illustrated inFIG.2A, the upper via GV may have a form in which the second substrate101extends into a via hole towards the first substrate201. The upper via GV may be formed together with the second substrate101and may include a material the same as that of the second substrate101, and an interfacial surface may not be present between the upper via GV and the second substrate101. Specifically, the upper via GV and the second substrate101are formed of the same material. The upper via GV may protrude from the lower surface of the second substrate101in a cylindrical shape or a conical shape. The upper via GV may further include a barrier layer103extending from the lower surface of the second substrate101. The barrier layer103may extend from the lower surface of the second substrate101along an internal side wall of the via hole to cover a bottom surface of the via hole. The barrier layer103may include a metal nitride. For example, the barrier layer103may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof. When a region of the upper via GV extending from the second substrate101includes a semiconductor material and the third lower interconnection line286includes a metal material, a defect may occur in a semiconductor-metal interfacial surface. However, in this case, as the barrier layer103is disposed between a semiconductor layer of the upper via GV integrated with the second substrate101and the third lower interconnection line286is disposed on a lower portion, the occurrence of the defect in the upper via GV may be prevented. The upper via GV may have a height H in a range of about 3000 Å to about 5000 Å in the z direction, a first direction. As the upper via GV is formed to be connected to the third lower interconnection line286, the upper via GV may have a relatively small height H as compared to a thickness of the peripheral region insulating layer290, thereby easily performing a process of forming the upper via GV. The upper via GV may have a greater diameter in an upper portion than in a lower portion. For example, the upper via GV may have a diameter D1in a range of about 200 nm to about 300 nm in an overall portion including the upper portion and the lower portion. The diameter D1of the upper via GV may be greater than an average diameter D2of the gate contacts162and an average diameter D3of the first and second through vias165and167, but the invention is not limited thereto. The upper via GV may be disposed to recess the third lower interconnection line286by a certain depth L. The depth L may be within a range of about 30 Å to about 90 Å. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range. The lower interconnection structure, forming a portion of the ground interconnection structure GI, may include the elements similar to the first interconnection structure LI, and may be electrically separated from the first interconnection structure LI. The lower interconnection structure may include first to third lower contact plugs272,274, and276and first to third lower interconnection lines282,284, and286, spaced apart from the first interconnection structure LI. As illustrated inFIG.2B, in the lower interconnection structure, a lowermost first lower contact plug272may penetrate a portion of the first peripheral region insulating layer292, an etching stop layer291, and the circuit gate dielectric layer222and may be connected to an impurity region207disposed in the first substrate201. The circuit gate dielectric layer222may be a layer extending from the circuit devices220, and the etching stop layer291may be formed on the circuit gate dielectric layer222and may perform an etching stop function when the first lower contact plugs272are formed. The impurity region207may be a doped layer formed in a region connected to the first lower contact plugs272to electrically connect the first lower contact plugs272to the first substrate201. In the lower interconnection structure, the first lower contact plugs272may be connected to the impurity region207disposed in a region surrounded by the device isolation layers210. FIGS.3A to3Care enlarged views illustrating a portion of a semiconductor device according to example embodiments.FIGS.3A to3Cillustrate a region corresponding to region “D” illustrated inFIG.1A. Referring toFIG.3A, in a semiconductor device100a, an upper via GVa of a ground interconnection structure GI may include a barrier layer103acovering an internal side wall and a bottom surface of a via hole. However, the barrier layer103amay be limitedly disposed in the via hole and may not extend along a lower surface of the second substrate101, differently from the example embodiment illustrated inFIG.2A. In this case, an area of the barrier layer103aexposed through an upper surface of the via hole may be reduced in a process of manufacturing the semiconductor device100aso that process variables caused by the barrier layer103amay be reduced. The barrier layer103ahaving such a structure may be formed by a manufacturing method including depositing a material for forming the barrier layer103a, forming a sacrificial layer filling the via hole, performing a planarization process, removing the sacrificial layer, and forming the second substrate101. Referring toFIG.3B, in a semiconductor device100b, an upper via GVb of a ground interconnection structure GI may include a barrier layer103bdisposed on a lower end of a via hole. The barrier layer103bmay be formed by a nitridation process. In this case, as the barrier layer103bis formed while partially consuming a third lower interconnection line286disposed on a lower portion of the via hole, the barrier layer103bmay have a form expanding from a boundary of the via hole marked by a dotted line on a lower end of the via hole to an upper portion of the via hole and also to a lower portion of the via hole. Referring toFIG.3C, in a semiconductor device100c, an upper via GVc of the ground interconnection structure GI may include a second substrate101and a barrier layer103and may further include a metal-semiconductor layer106disposed between the second substrate101and the barrier layer103. The metal-semiconductor layer106may be a layer including a metal element included in the barrier layer103and a semiconductor element included in the second substrate101. For example, the metal-semiconductor layer106may include titanium silicide (TiSi), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), or other metal silicide. The metal-semiconductor layer106may be formed on an interfacial surface with the barrier layer103when the second substrate101is formed according to a process of forming the second substrate101. FIGS.4to6are schematic cross-sectional views of a semiconductor device according to example embodiments.FIGS.4to6illustrate regions corresponding to the region illustrated inFIG.1A. Referring toFIG.4, in a semiconductor device100d, a second substrate101and first and second horizontal conductive layers102and104may have a recessed portion CR formed on an upper portion of a ground interconnection structure GI. The recessed portion CR may be disposed on an upper portion of an upper via GV, and a center of the recessed portion CR may be disposed on the substantially same linear line (i.e., aligned) in the z direction with a center of the upper via GV. In example embodiments, the recessed portion CR may be formed only on the second substrate101. Referring toFIG.5, in a semiconductor device100e, a ground interconnection structure GI may include a plurality of upper vias GVe disposed side by side. For example, the ground interconnection structure GI may include two upper vias GVe and a plurality of lower interconnection structures connected to the upper vias GVe in lower portions of the upper vias GVe, respectively. The plurality of lower interconnection structures may be separated from each other as illustrated, or may be connected to each other. The arrangement form of the upper vias GVe and the lower interconnection structures disposed in the ground interconnection structure GI may also be applied to other example embodiments. Referring toFIG.6, in a semiconductor device100f, a memory cell region CELL may include a region from which a first horizontal conductive layer102is partially removed and in which the second horizontal conductive layer104is in contact with a second substrate101. The second horizontal conductive layer104may have a concave region SR formed by removing the first horizontal conductive layer102from the region. The concave region SR may be disposed to overlap at least a portion of the ground interconnection structure GI and/or the upper via GV in the z direction. FIGS.7A and7Bare schematic cross-sectional views of a semiconductor device according to example embodiments.FIGS.7A and7Billustrate regions corresponding to the region illustrated inFIG.1A. Referring toFIG.7A, in a semiconductor device100g, a ground interconnection structure GI may include an upper via GVg, and first and second lower contact plugs272and274and first and second lower interconnection lines282and284as a lower interconnection structure. In other words, the ground interconnection structure GI may only include a portion of first to third lower contact plugs272,274, and276and a portion of first to third lower interconnection lines282,284, and286as the lower interconnection structure. Accordingly, the upper via GVg may extend relatively more deeply than the upper via GV illustrated in the example embodiment inFIGS.1A to2Band may be connected to the second lower interconnection line284. In this case also, the upper via GVg may include a barrier layer103as illustrated inFIG.2A. Also, the upper via GVg may have a diameter relatively greater than that of the upper via GV illustrated in the example embodiment inFIGS.1A to2B, but the invention is not limited thereto. Referring toFIG.7B, in a semiconductor device100h, a ground interconnection structure GI may only include an upper via GVh. Accordingly, the upper via GVh may not be connected to a lower interconnection structure and may extend from a second substrate101to a first substrate201disposed on a lower portion. In contrast to the structure illustrated inFIG.2A, the upper via GVh in the example embodiment may not include a barrier layer103. Also, the upper via GVh may have a diameter greater than that of the upper via GV illustrated in the example embodiment inFIGS.1A to2B, but the invention is not limited thereto. FIG.8is a schematic cross-sectional view of a semiconductor device according to example embodiments.FIG.8illustrates a region corresponding to the region illustrated inFIG.1B. Referring toFIG.8, in a semiconductor device100i, a stack structure of gate electrodes130may be constituted by vertically stacked lower and upper stack structures, and channel structures CHi may include vertically stacked first and second channel structures CH1and CH2. The structure of the channel structures CHi may be introduced to stably form the channel structures CHi when the number of the stacked gate electrodes130are relatively large. In the channel structures CHi, the first channel structures CH1disposed on a lower portion may be connected to the second channel structures CH2disposed on an upper portion, and the channel structures CHi may have a bent portion formed by a difference in widths in a connection region. A channel layer140, a gate dielectric layer145, and a channel insulating layer150may be connected to each other between the first channel structure CH1and the second channel structure CH2. A channel pad155may only be disposed on an upper end of the second channel structure CH2disposed on an upper portion. In example embodiments, each of the first channel structure CH1and the second channel structure CH2may also include the channel pad155, and in this case, the channel pad155of the first channel structure CH1may be connected to the channel layer140of the second channel structure CH2. An upper interlayer insulating layer125having a relatively thick thickness may be disposed on an uppermost portion of the lower stack structure. However, the forms of the interlayer insulating layers120and the upper interlayer insulating layer125may be varied in example embodiments. FIGS.9A to9Hare schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.FIGS.9A to9Hillustrate regions corresponding to the region illustrated inFIG.1A. Referring toFIG.9A, circuit devices220and a first interconnection structure LI may be formed on a first substrate201. Firstly, device isolation layers210may be formed in the first substrate201, and a circuit gate dielectric layer222and a circuit gate electrode225may be sequentially formed on the first substrate201. The device isolation layers210may be formed by a shallow trench isolation (STI) process, for example. The circuit gate dielectric layer222and the circuit gate electrode225may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer222may be formed of silicon oxide, and the circuit gate electrode225may be formed of one of polycrystalline silicon or a metal silicide layer, but the invention is not limited thereto. Thereafter, a spacer layer224and source/drain regions205may be formed on both side walls of the circuit gate dielectric layer222and the circuit gate electrode225. In example embodiments, the spacer layer224may include a plurality of layers. Thereafter, the source/drain regions205may be formed by performing an ion implantation process. Lower contact plugs270of the first interconnection structure LI may be formed by partially forming a first peripheral region insulating layer292, partially removing the element by an etching process, and filling a conductive material therein. Lower interconnection lines280may be formed by, for example, depositing and patterning a conductive material. When the first interconnection structure LI is formed, a lower interconnection structure constituting a portion of a ground interconnection structure GI (seeFIG.1A) may be formed together. Accordingly, the lower interconnection structure may have a stack structure the same as the first interconnection structure LI. The first peripheral region insulating layer292may include a plurality of insulating layers. The first peripheral region insulating layer292may be partially formed at each of the processes for forming the first interconnection structure LI. A lower protective layer295covering an upper surface of a third lower interconnection lines286may be formed on the first peripheral region insulating layer292. Referring toFIG.9B, a via hole VH may be formed by forming a second peripheral region insulating layer294on the lower protective layer295, and partially removing the second peripheral region insulating layer294. By forming the second peripheral region insulating layer294, an overall portion of a peripheral circuit region PERI may be formed. The via hole VH may be a through-hole for forming an upper via GV (seeFIG.1A) of the ground interconnection structure GI. The via hole VH may be formed by removing the second peripheral region insulating layer294and the lower protective layer295to expose the third lower interconnection line286of the lower interconnection structure constituting the ground interconnection structure GI using a mask layer. In example embodiments, the lower protective layer295may also function as an etching stop layer when the via hole VH is formed. The via hole VH may be formed to partially recess the third lower interconnection line286, but the invention is not limited thereto. For example, the via hole VH may be formed to expose an upper surface of the third lower interconnection line286. Referring toFIG.9C, the second substrate101of a memory cell region CELL and the upper via GV of the ground interconnection structure GI may be formed on an upper portion of the peripheral circuit region PERI. Before the second substrate101is formed, a barrier layer103illustrated inFIG.2Amay be formed on the second peripheral region insulating layer294. The second substrate101may be formed of polycrystalline silicon, for example, and may be formed by a CVD process. When the second substrate101is formed, a material forming the second substrate101may fill the via hole VH such that the upper via GV may be formed. The polycrystalline silicon forming the second substrate101may include impurities such as n-type impurities, for example. The second substrate101may be formed on an overall portion of the second peripheral region insulating layer294, may be patterned, and may be removed from a partial region of the memory cell region CELL including a third region C. The barrier layer103disposed on a lower portion of the second substrate101may also be removed from the region from which the second substrate101is removed. In example embodiments, before each of the barrier layer103and the second substrate101is formed, a process of removing a natural oxide film by performing a cleaning process may further be performed. Accordingly, the natural oxide film may rarely remain on an upper portion and a lower portion of the barrier layer103, or may remain in a thickness of about 20 Å or less. However, in some example embodiments, when the cleaning process is omitted, the natural oxide film may be present on a lower surface and/or an upper surface of the barrier layer103. Also, in example embodiments, after the second substrate101is formed, a planarization process may further be performed. In this case, the second substrate101may have a substantially planar upper surface. In the example embodiment illustrated inFIG.4, such a planarization process may be omitted. Referring toFIG.9D, first and second source sacrificial layers111and112and a second horizontal conductive layer104may be formed, a substrate insulating layer105may be formed, and thereafter, sacrificial insulating layers118and interlayer insulating layers120may be alternately stacked. The first and second source sacrificial layers111and112may be stacked on the second substrate101such that the first source sacrificial layers111may be disposed upwardly and downwardly of the second source sacrificial layers112. The first and second source sacrificial layers111and112may include different materials. The first and second source sacrificial layers111and112may be replaced with a first horizontal conductive layer102illustrated inFIG.1Athrough a subsequent process. For example, the first source sacrificial layers111may be formed of a material the same as that of the interlayer insulating layers120, and the second source sacrificial layers112may be formed of a material the same as that of the sacrificial insulating layers118. The second horizontal conductive layer104may be formed on the first and second source sacrificial layers111and112. The substrate insulating layer105may be formed by partially removing the first and second source sacrificial layers111and112, the second horizontal conductive layer104, and the second substrate101in a region in which a through interconnection region TR (seeFIG.1A) is disposed, and filling the portions with an insulating material. The sacrificial insulating layers118may be partially replaced with the gate electrodes130(seeFIG.1A) through a subsequent process. The sacrificial insulating layers118may be formed of a material different from a material of the interlayer insulating layers120, and may be formed of a material which may be etched with etching selectivity under a certain etching condition with respect to the interlayer insulating layers120. For example, the interlayer insulating layers120may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers118may be formed of a material selected from among silicon, silicon oxide, silicon carbide, and silicon nitride, which is different from the material of the interlayer insulating layers120. In example embodiments, thicknesses of the interlayer insulating layers120may not be the same. Thicknesses of the interlayer insulating layers120and the sacrificial insulating layers118and the number of films of the interlayer insulating layers120and the sacrificial insulating layers118may be varied. In a second region B, a photolithography process and an etching process may be repeatedly performed on the sacrificial insulating layers118using a mask layer such that the sacrificial insulating layers118disposed on an upper portion may extend less than the sacrificial insulating layers118disposed on a lower portion. Accordingly, the sacrificial insulating layers118may form a staircase-shaped stepped structure by a certain unit. Thereafter, a first cell region insulating layer192covering the stack structure of the sacrificial insulating layers118and the interlayer insulating layers120may be formed. Referring toFIG.9E, channel structures CH penetrating the stack structure of the sacrificial insulating layers118and the interlayer insulating layers120may be formed. Firstly, upper separation regions SS (seeFIG.1B) may be formed by partially removing the sacrificial insulating layers118and the interlayer insulating layers120. The upper separation regions SS may be formed by exposing a region in which the upper separation regions SS are to be formed using a mask layer, removing a certain number of the sacrificial insulating layers118and the interlayer insulating layers120from an uppermost portion, and depositing an insulating material. The channel structures CH may be formed by anisotropic-etching the sacrificial insulating layers118and the interlayer insulating layers120, and may be formed by forming a hole-shaped channel holes and filling the holes. Due to a height of the stack structure, a side wall of the channel structures CH may not be perpendicular to an upper surface of the second substrate101. The channel structures CH may be formed to partially recess the second substrate101. Thereafter, at least a portion of the gate dielectric layer145, the channel layer140, the channel insulating layer150, and the channel pad155may be sequentially formed in the channel structures CH. The gate dielectric layer145may be formed to have a uniform thickness using an ALD process or a CVD process. The gate dielectric layer145may be entirely or partially formed in this process, and a portion extending perpendicularly to the second substrate101along the channel structures CH may be formed in this process. The channel layer140may be formed on the gate dielectric layer145in the channel structures CH. The channel insulating layer150may be formed to fill the channel structures CH, and may be an insulating material. However, in example embodiments, a space between the channel layers140may be filled with a conductive material, instead of the channel insulating layer150. The channel pad155may be formed of a conductive material. For example, the channel pad155may be formed of polycrystalline silicon. Referring toFIG.9F, tunnel portions LT may be formed by forming openings penetrating the stack structure of the sacrificial insulating layers118and the interlayer insulating layers120in regions corresponding to first and second separation regions MS1and MS2(seeFIG.1B), and partially removing the sacrificial insulating layers118through the openings. Firstly, sacrificial spacer layers may be formed in the openings, the second source sacrificial layers112may be selectively removed, and thereafter, the first source sacrificial layers111may be removed. The first and second source sacrificial layers111and112may be removed by a wet etching process, for example. In the process of removing the first source sacrificial layers111, a portion of the gate dielectric layer145exposed from the region from which the second source sacrificial layers112is removed may be removed together. According to example embodiments, a portion of the first and second source sacrificial layers111and112may remain in the second region B. The first horizontal conductive layer102may be formed by depositing a conductive material in a region from which the first and second source sacrificial layers111and112are removed, and the sacrificial spacer layers may be removed from the openings. Thereafter, the sacrificial insulating layers118may be removed from an external side of the through interconnection region TR (seeFIG.1A). The sacrificial insulating layers118may remain in the through interconnection region TR and may form an insulating region of the through interconnection region TR along with the interlayer insulating layers120. The sacrificial insulating layers118may be selectively removed with respect to the interlayer insulating layers120using a wet etching process, for example. Accordingly, a plurality of the tunnel portions LT may be formed between the interlayer insulating layers120. A region in which the through interconnection region TR is formed may be a region spaced apart from the openings such that the sacrificial insulating layers118may remain because an etchant does not reach. Accordingly, the through interconnection region TR may be formed in the center region between the first and second separation regions MS1and MS2adjacent to each other. Referring toFIG.9G, the gate electrodes130may be formed by filling the tunnel portions LT from which the sacrificial insulating layers118are partially removed with a conductive material. Side surfaces of the gate electrodes130may be in contact with side surfaces of the sacrificial insulating layers118of the through interconnection region TR. The conductive material may include a metal, polycrystalline silicon, or a metal silicide material. After the gate electrodes130are formed, a separation insulating layer110(seeFIG.1B) may be formed by removing the conductive material deposited in the openings through an additional process and filling the portion with an insulating layer. Referring toFIG.9H, gate contacts162, a substrate contact164, and first and second through vias165and167, which penetrate the first cell region insulating layer192, may be formed. The gate contacts162may be formed to be connected to the gate electrodes130in the second region B, and the substrate contact164may be formed to be connected to the second substrate101on an end of the second region B. The first through via165may be formed to be connected to the first interconnection structure LI of the peripheral circuit region PERI in the through interconnection region TR, and the second through via167may be formed to be connected to the first interconnection structure LI of the peripheral circuit region PERI in the third region C. The gate contacts162, the substrate contact164, and the first and second through vias165and167may be formed with different depths, but the gate contacts162, the substrate contact164, and the first and second through vias165and167may be formed by simultaneously forming contact holes using an etching stop layer, or the like, and filling the contact holes with a conductive material. However, in some of example embodiments, a portion of the gate contacts162, the substrate contact164, and the first and second through vias165and167may also be formed in different processes. Thereafter, referring back toFIG.1A, a second cell region insulating layer194, an upper protective layer195, and an upper interconnection structure UI may be formed. Upper contact plugs170of the upper interconnection structure UI may be formed by partially forming a cell region insulating layer290, partially removing the cell region insulating layer290by an etching process, and filling the portion with a conductive material. Upper interconnection lines180may be formed by depositing and patterning a conductive material, for example. Accordingly, the semiconductor device100illustrated inFIGS.1A to2Bmay be manufactured. According to the aforementioned example embodiments, as the ground interconnection structure includes an upper via extending from the second substrate, a semiconductor device having improved reliability may be provided. While the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims. | 57,385 |
11862557 | DETAILED DESCRIPTION Embodiments describe multi-die structures and methods of formation including monolithic and external die-to-die interconnection sequences. This may be facilitated by integration of intra-chip routing for chip-level (i.e. monolithic) die-to-die routing between adjacent dies at the wafer level before dicing, as well as inter-chip routing for subsequent package-level (i.e. external) die-to-die routing. For example, a routing layer including external package-level die-to-die routing may be formed during a wafer reconstitution process where separate dies are mounted onto the routing layer (e.g. active or passive interposer) or the routing layer is formed directly on a plurality of dies, which can have been reconstituted using an embedded wafer level packaging sequence. Selection of the die-to-die interconnection sequence in accordance with embodiments can be pre-determined or made in-situ at the wafer-level during die fabrication. Selection can be based on need such as power, latency, die area, cost, and average manufacturing time. Test pads may additionally be provided during a partially fabricated back-end-of-the-line (BEOL) build-up structure formed over an array of die areas. These test pads can be probed to provide production data. Alternatively, or in addition, tangential process data can be relied upon. Such design and manufacturing methods can also be used to create small or large configurations of interconnected die sets, such as1x,2X,4X,8X,16X, etc. For example, smaller die sets such as1X,2X,4X interconnected die sets may be diced with higher yield than larger die sets, such as6X,8X,16X, etc. In some embodiments, smaller die sets with expected higher yield may be fabricated and diced including chip-level (monolithic) die-to-die routing. In some embodiments, larger die sets may be fabricated and diced for subsequence package-level (external) die-to-die routing, for example with a wafer reconstitution sequence of diced dies or diced die sets. For example, external die-to-die interconnection may be selected based on expected lower yield for comparable monolithic die-to-die interconnection of comparable die sets. In order to facilitate the selection of monolithic or external die-to-die interconnection the dies can include selection devices, such as multiplexers or demultiplexers, to select either intra-chip routing for chip-level die-to-die routing or inter-chip routing for external package-level die-to-die routing. Alternatively, selection can be made lithographically where mask selection can define intra-chip routing and/or inter-chip routing. An exemplary multi-die structure with monolithic die-to-die interconnection in accordance with embodiments may include a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, with the second FEOL die area separate from the first FEOL die area. The multi-die structure may additionally include a first selection device within the first FEOL die area, a second selection device within the second FEOL die area, and a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area. The BEOL build-up structure may additionally include a chip-level die-to-die routing connecting the first selection device with the second selection device, a first inter-chip routing connected to the first selection device, and a second inter-chip routing with the second selection device. Thus, the complementary arrangement of selection devices, such as multiplexer and demultiplexers, in adjacent dies can be used to select the chip-level die-to-die routing or the inter-chip routing for subsequent external die-to-die interconnection. In an embodiment, the inter-chip routings are connected to electrically open terminals, and the selection devices are programmed to select the chip-level die-to-die routing, which can include corresponding inter-chip routings within the BEOL build-up structure. An exemplary multi-die structure with external die-to-die interconnection in accordance with embodiments may include routing layer (such as interposer, or package-level redistribution layer) that includes a first package-level bond pad, a second package-level bond pad, and a package-level die-to-die routing electrically connecting the first package-level bond pad to the second package-level bond pad. A first die may be bonded to a first side of the routing layer and in electrical connection with the first package-level bond pad, and a second die may be bonded to the first side of the routing layer and in electrical connection with the second package-level bond pad. A variety of bonding methods may be used such as hybrid bonding for a chip-on-wafer (CoW) design, or the routing layer may be formed directly on the first and second dies in an embedded wafer level packaging sequence. Such configurations can eliminate an intermediate conductive bonding layer, such as solder, to create an almost chip-like connection with less power penalty. The first and second dies may be homogenous or heterogenous die types. In an embodiment, at least one of the dies includes a first FEOL die area including a communication device (e.g. transceiver or a receiver), a first BEOL build-up structure spanning over the first FEOL die area, with the first BEOL build-up structure including an electrically open intra-chip routing connected to the communication device, and a chip-level die-to-die routing connecting the communication device to a first bond pad of the first BEOL build-up structure, where the first bond pad is bonded to the routing layer and electrically connected to the first package-level bond pad. Yet another exemplary multi-die structure with external die-to-die interconnection can be accomplished with through silicon vias (TSVs). Such a configuration may facilitate die-to-die interconnection with 3D die stacking. The various monolithic and external die-to-die interconnection designs can be combined to achieve more complex interconnected structures in accordance with embodiments. In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. The terms “over”, “to”, “between”, “spanning” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer or feature “over”, “spanning” or “on” another layer or bonded “to”, in “contact” with or connected “to” another layer may be directly in contact with, or direct connected to, the other layer or feature, or may have one or more intervening layers or features. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers. Referring now toFIGS.1A-1B,FIG.1Ais a circuit diagram of a redundant die-to-die interconnection layout including chip-level die-to-die routing and bond pads for package-level die-to-die interconnection in accordance with an embodiment;FIG.1Bis a combination schematic cross-sectional side view illustration and circuit diagram for a die set including chip-level die-to-die routing and bond pads for package-level die-to-die interconnection prior to singulation in accordance with an embodiment. In particular,FIGS.1A-1Billustrate a combination of various monolithic and external die-to-die interconnection designs within the same structure. It is to be appreciated that practical applications may implement only some of the interconnection features depending upon flexibility to be integrated into the process flows. In interest of clarity and concisenessFIGS.1A-1Bare described concurrently. Dies102A,102B in accordance with embodiments may have redundant die-to-die routing configurations, including intra-chip routing104for chip-level die-to-die routing110, and well as inter-chip routing106to external-facing bond pads112for package-level die-to-die interconnection. As shown, inFIG.1A, the dies102A,102B can optionally include one more selection devices such as demultiplexers120and/or multiplexers122connected to transceivers124and receivers126, respectively. For example, transceivers124can be connected to inputs of the demultiplexers, where inter-chip routing106connects bond pad112to an output of a demultiplexer, and intra-chip routing104connects the chip-level die-to-die routing110to another output of the demultiplexer120. It is to be appreciated that the selection devices in accordance with some embodiments, and other methods of forming die-to-die interconnections in accordance with embodiments may leverage lithography for die-to-die routing path selection. In an embodiment, a multi die structure100includes a first front-end-of-the line (FEOL) die area103A of a first die102A patterned into a semiconductor substrate101and a second FEOL die area103B of a second die102B patterned into the semiconductor substrate101, with the second FEOL die area103B separate from the first FEOL die area103A. As shown inFIG.1B, the multi-die structure may additionally include a first selection device, such as a demultiplexer120, and transceiver124within the first FEOL die area103A, a second selection device, such as a multiplexer122, and receiver126within the second FEOL die area103B. A back-end-of-the-line (BEOL) build-up structure130can be formed over and spanning over the first FEOL die area103A and the second FEOL die area103B. In an embodiment, the BEOL build-up structure130additionally includes a chip-level die-to-die routing110connecting the first selection device (demultiplexer120) with the second selection device (multiplexer122), a first inter-chip routing104connected to the first selection device, and a second inter-chip routing104with the second selection device. Thus, the complementary arrangement of selection devices, such as demultiplexer120and multiplexer122, in adjacent dies can be used to select the chip-level die-to-die routing110or the inter-chip routing104for subsequent external die-to-die interconnection. As shown, each FEOL die area103A,103B is formed in the same (semiconductor) substrate101, such as a silicon wafer. Each FEOL die area103A,103B can include the active and passive devices of the dies. A back-end-of-the-line (BEOL) build-up structure130provides electrical interconnections and optionally metallic seal structures. The BEOL build-up structure130may conventionally fulfill the connectivity requirements of the die(s). The BEOL build-up structure130may be fabricated using conventional materials including metallic wiring layers134(e.g. copper, aluminum, etc.) and insulating interlayer dielectrics (ILD)136such as oxides (e.g. silicon oxide, carbon doped oxides, etc.), nitrides (e.g. silicon nitride), low-k, materials, etc. The chip-level die-to-die routing110may include intra-chip routing104from each die connected to stitch routing105spanning across a scribe region109between the dies. In accordance with embodiments, the intra-chip routing104and inter-chip routing106may be formed from one or more vias133and metal layers134within the BEOL build-up structure130. The inter-chip routing106and chip-level die-to-die routing110may include multiple routings, formed within multiple metal layers. In accordance with embodiments, the routings can be formed within the lower metal layers M_low, upper metal layers M_high, midlevel metal layers M_mid, and combinations thereof. Generally, the lower metal layers M_low have finer line widths and spacing. Additionally, the interlayer dielectrics (ILDs) for the lower metal and midlevel metal layers may be formed of low_k materials, which can allow quicker moisture transport. Thus, when using the finer wiring layers, additional precautions can be taken in accordance with embodiments, such as passivation of diced chip edges. This may be attributed to making connections between devices. The upper metal layers M_high may have coarser line widths and line spacing, with the midlevel metal layers M_mid having intermediate line widths and spacing. In an embodiment, upper metal layers M_high may be primarily used for stitch routing105for lower resistance wiring. In accordance with embodiments, the chip-level die-to-die routing110extends through one or more openings142in the metallic seals140to electrically connect the dies102. Referring again to bothFIGS.1A-1B, the chip-level die-to-die routing110, inter-chip routing106and selection devices (demultiplexer120, multiplexer122) are illustrated with dotted lines to indicate each is optional. For example, rather than inclusion of selection devices, lithography can be used to determine the formation of chip-level die-to-die routing110and/or inter-chip routing106. Alternatively, selection devices can be used in combination with the formation of both chip-level die-to-die routing110and/or inter-chip routing106. In some embodiments, inter-chip routing106can be formed all the way to bond pads112. In other embodiments, inter-chip routing106is partially formed, or not formed at all. Similarly, chip-level die-to-die routing110can be formed partially or not at all. Additionally, an optional bypass routing172is shown connecting the selection devices to through silicon vias (TSVs)170that extend to back side pads174on a back side176of the multi die structure100. The back side176may correspond to a back side passivation layer177on a back side of the semiconductor substrate101. The optional interconnection of the bypass routing172, TSVs170and back side pads174can be formed partially or not at all. Thus, it is to be appreciated thatFIGS.1A-1Billustrated an embodiment with substantial flexibility. In other implementations or embodiments, certain features may be removed for practicality and/or production cost reduction. Still referring toFIG.1B, in an embodiment, the BEOL build-up structure130includes a face side132including a first bond pad112and a second bond pad112, a chip-level die-to-die routing110connecting the demultiplexer120with the multiplexer122, a first inter-chip routing106connecting the first bond pad112with the demultiplexer120, and a second inter-chip routing106connecting the second bond pad112with the multiplexer122. The BEOL build-up structure130may additionally include a plurality of chip-level landing pads138which may be electrically connected to the first and second FEOL die areas103A,103B. The bond pads112in accordance are optional and may be utilized for external die-to-die interconnection, such as with hybrid bonding or stitch routing with embedded wafer level processing. Chip-level landing pads138can assume different configurations, depending upon the designed die-to-die interconnection. For example, chip-level landing pads138may be designed for hybrid bonding with external die-to-die interconnection or designed for solder bump attach for monolithic die-to-die interconnection, such as under burn metallurgy (UBM) pads. Bonding surfaces for hybrid bonding will be planar, while planarity is relaxed for UBM pads to have level top surfaces to receive solder bumps. Additionally, test pads141may be located in a variety of locations depending upon interconnection method. In an embodiment, test pads141are formed alongside chip-level landing pads138. For example, the test pads141in such a configuration may be UBM pads, where the die set includes monolithic die-to-die interconnection. Alternatively, test pads141can be embedded within the BEOL build-up structure130. In such a configuration, the test pads can be below the bond pads112and chip-level landing pads138that are designed for hybrid bonding, for example, and external die-to-die interconnection. In an embodiment, buried test pads141can be formed of aluminum, as opposed to copper material forming the metallization routing layers within the BEOL build-up structure. Each die area may represent a complete system, or sub-system. Adjacent die areas may perform the same or different function. In an embodiment, die areas103A,103B, for example, interconnected to die-to-die routing can include a digital die area tied to a die area with another function, such as analog, wireless (e.g. radio frequency, RF) or wireless input/output, by way of non-limiting examples. The tied die areas may be formed using the same processing nodes, whether or not having the same or different functions. Whether each die and die area includes a complete system, or are tied subsystems, the die-to-die routing may be for inter-die routing (different systems) or intra-die routing (different, or same subsystems within the same system). For example, intra die-to-die routing may connect different subsystems within a system on chip (SOC) where inter die-to-die routing can connect different SOCs, though this is illustrative, and embodiments are not limited to SOCs. In an embodiment, a die set includes both digital and analog or wireless die areas103A.103B. In an embodiment, the different dies102A,102B with a die set can include multiple engines, such as a graphics processing unit (GPU), a central processing unit (CPU), a neural engine (e.g. neural network processing engine), an artificial intelligence (AI) engine, a signal processor, networks, caches, and combinations thereof. However, embodiments are not limited to engines, and may include memory devices, such as SRAM, MRAM, DRAM, NVRAM, NAND, cache memory, or other components such as a capacitor, inductor, resistor, power management integrated circuit (IC), amongst others. In accordance with embodiments, the chip-level die-to-die routing110extends through one or more openings142in the metallic seals140to electrically connect the dies102. In an embodiment, the openings142are lateral openings. For example, the openings142may be similar to a gate opening in a fence. In an embodiment, the openings142are vertical openings. For example, the openings142may be similar to a window in a wall between a floor and ceiling, or open kitchen service counter for illustrative purposes. Openings142can assume different shapes, and combinations of lateral and vertical characterizations. Metallic seals140can be formed along any and all sides of the dies102. For example, each die102can include a metallic seal140along a single side, multiple sides or all sides. A variety of combinations are possible. Still referring toFIG.1B, the BEOL build-up structure130can include a top passivation layer135, which can include one or more layers. For example, the top passivation layer135can include a sealing layer137and optional second sealing layer143or bonding layer139over the sealing layer137. The sealing layer(s)137,143may be formed of a nitride, polyimide, etc. to provide chemical and moisture protection to the underlying structure. The optional bonding layer139can be provided for die bonding to another routing layer, such as with hybrid bonding. In an embodiment, the bonding layer139is formed of a dielectric material such as an oxide (e.g. SiO2) or polymer for dielectric-dielectric (e.g. oxide-oxide, polymer-polymer) bonding in a hybrid bonding operation. Selection of optional second sealing layer143or bonding layer139in accordance with embodiments may be at least partially determined by whether the structure is manufactured for monolithic and/or external die-to-die interconnection. In an embodiment, the BEOL build-up structure130includes a first metallic seal140adjacent the first FEOL die area103A, and a second metallic seal140adjacent the second FEOL die area103B, wherein the chip-level die-to-die routing110extends through a first opening142in the first metallic seal140and a second opening142in the second metallic seal140. In an embodiment, the chip-level die-to-die routing110extends over the first metallic seal140and the second metallic seal140. In some embodiments, a chip-level die-to-de routing110may terminal along a diced die edge111. In some embodiments, the metallic seal140adjacent a diced edge may be continuous, such that a die-to-die routing does not extend through the metallic seal140adjacent the diced edge111. In such a configuration the intra-chip routing of the corresponding chip-level die-to-die routing110may be confined laterally inside the metallic seal140. FIG.2is a flow chart illustrating a method of fabricating a die set including either monolithic chip-level die-to-die interconnection or external package-level die-to-die interconnection in accordance with an embodiment. At operation2010an array of die areas is formed in a semiconductor substrate101. For example, the die areas may have the same or different functionalities. At operation2020a decision is made with regard to individual dies or groups of dies whether the fabrication sequence will proceed for monolithic die-to-die routing process flows (e.g. seeFIGS.4-6) or external die-to-die routing process flows (e.g. seeFIGS.7-14). More specifically, a decision is made whether the die-to-die interconnection configuration will be for large die sets, yield limited die sets, for heterogenous die sets or for physical orientation and configuration (e.g. irregularly shaped area) needs better suiting the system. Where any of these scenarios are a concern, an external die-to-die routing process flow may be followed. Where yields are acceptable (often size of die set limited) and it is possible to form homogenous die sets (from same wafer), then a monolithic die-to-die routing process flow may be followed. The decision may be made prior to BEOL build-up structure130fabrication. For example, the decision may be based on yield pre-calculations, where certain die-set, or cluster, sizes will have unacceptable yield. Thus, the external interconnection fabrication route can be pursued for larger configurations using smaller units. For smaller configurations monolithic die-to-die interconnection result in sufficient yield, where bad sections can still be carved out and good portions of the smaller configurations can be recovered. The decision may also be made during BEOL build-up structure130fabrication, such as around the time before openings142are formed in the metallic seals140(seeFIG.1B). The decision may be aided by probing of test pads within the BEOL build-up structure130, and process metrics. Probing of test pads141may also be performed after the decision has been made. Both monolithic die-to-die interconnection process flows (e.g.FIGS.4-6) and external die-to-die interconnection process flows (e.g.FIGS.7-14) in accordance with embodiments may leverage selection devices (e.g. multiplexer, demultiplexer) or lithographically selected wiring schemes. In a monolithic process flow, through seal chip-level die-to-die routings110may be formed, such as through openings142within or over metallic seals140at operation2030, followed by singulation of the monolithic die sets at operation2040. A predetermined monolithic process flow may include the formation of specific die sets with through seal chip-level die-to-die routings110. In this manner, there is no external interconnection path. Full metallic seals can optionally be formed surrounding the predetermined die sets (e.g. seeFIGS.5B-5C), or optionally through seal chip-level die-to-die routings110can be formed between all dies for additional flexibility in carving die sets (e.g. seeFIG.5A). In a more flexible process flow supporting both monolithic and external die-to-die interconnection (e.g. seeFIG.1B), both intra-chip routings104and inter-chip routings106can be included with termination at UBM pads for flip chip bonding. Specifically, UBM pads include chip-level landing pads138, test pads141, and optionally bond pads112. However, in the exemplary process flows illustrated inFIGS.4-6, the inter-chip routings106(if present) are terminated prior to formation of bond pads112. Description of various pads in accordance with embodiments distinguishes pads suitable for flip chip bonding (e.g. UBM pads) and pads suitable for hybrid bonding or formation of a routing layer directly on the dies with embedded wafer level processing. For example, flip chip/UBM pads may have a pitch of 50-100 μm, and be thicker than hybrid bond pads, and optionally be formed of a different material (e.g. aluminum) relative to hybrid bond pads. Additionally, surface finish roughness and particulate requirements are loosened for flip chip compared to hybrid bonding. In an external process flow, the inter-chip routings106are formed all the way up to bond pads112at operation2050. This may be accompanied by the formation of full metallic seals140all the way up to the top passivation layer135. This may be followed by singulation of dies or die sets at operation2060, which is then followed by connection of the bond pads112to external die-to-die routing at operation2070. In a pre-determined external interconnection process flow through seal chip-level die-to-die routings110are not formed. Bond pads112may be prepared for hybrid bonding. Specifically, pads conditioned for hybrid bonding, or stitch routing with embedded wafer level processing, can include bond pads112and chip-level landing pads138. Both of which may share a planar face side132surface along with bonding layer139. Furthermore, full metallic seals can be formed around each die102. In a more flexible process flow supporting both external and monolithic die-to-die interconnection (e.g. seeFIG.1B), both inter-chip routings106, optionally terminating at bond pads112and through seal chip-level die-to-die routings110can be included. However, in the exemplary process flows illustrated inFIGS.7-14, the intra-chip routings104are often terminated prior to completion of the chip-level die-to-die routings110. As described above, monolithic and external interconnection process flows can have significantly different designs, or substantially similar designs depending upon flexibility to be integrated into the process flow. In the following description various specific process flows are described. It is to be appreciated that the specific configurations illustrated and described are representative of certain implementations of the embodiments, and the embodiments are not necessarily restrictive of one another, as illustrated and described with regard toFIG.1B. Referring nowFIGS.3A-3Bschematic top view illustrations are provided of semiconductor substrates101including arrays of dies102configured for monolithic or external die-to-die interconnection and prior to singulation in accordance with an embodiment. In the embodiment illustrated inFIG.3A, an array of2X die sets is illustrated, each including chip-level die-to-die routing110for monolithic die-to-die interconnection. In the embodiment illustrated inFIG.3B, an array of dies102are formed, each including bond pads112for external die-to-die interconnection. In accordance with embodiments, chip-level die-to-die-routing110and/or bond pads112can be formed along a single side, multiple sides, or all sides of the dies102. Additionally, all dies102can potentially be tied together, or specific groups of dies can be configured to be tied together. Thus, a variety of configurations are possible. A potential configuration (e.g. seeFIG.1B) where each die102includes chip-level die-to-die routing110and bond pads112on one or all sides can present a more costly, yet flexible configuration for either carving die sets with chip-level die-to-die routing110or dies for external die-to-die interconnection. Referring now toFIGS.4-5C,FIG.4is a circuit diagram of a die-to-die interconnect layout including chip-level die-to-die routing in accordance with an embodiment;FIGS.5A-5Bare combination schematic cross-sectional side view illustrations and circuit diagrams for a chip160including selection devices for chip-level die-to-die routing in accordance with embodiments;FIG.5Cis a combination schematic cross-sectional side view illustration and circuit diagram for a chip160including a lithographically patterned chip-level die-to-die routing in accordance with an embodiment. In interest of clarity and concisenessFIGS.4-5Care described concurrently. Specifically,FIG.4illustrates a circuit diagram similar to that ofFIG.1A, where the demultiplexer120and multiplexer122are configured to select the chip-level die-to-die routing110. Thus, the transceiver124and receiver126communicate through the chip-level die-to-die routing110. In the embodiment illustrated, the inter-die routing106is terminated. For example, the inter-die routing106can be terminated at terminals108buried within the BEOL build-up structure130beneath the face side132of the BEOL build-up structure130. Thus, the inter-die routing106can optionally be terminated prior to formation of bond pads112ofFIG.1B. In an embodiment, the inter-die routing106is terminated after the decision operation2020during a partially fabricated BEOL build-up structure130. However, the decision may have been pre-determined prior to fabrication of the BEOL build-up structure130, and inter-die routing106may be absent. In an alternative embodiment, the inter-die routing106can be propagated all the way to bond pads112as described with regard toFIG.1B. The remainder of the BEOL build-up structure130can then be formed, followed by probing of test pads141. This may be followed by placement of solder bumps152on at least the chip-level landing pads138, and optionally test pads141, and dicing of the die set. It is to be appreciated that while a2X die set is illustrated inFIG.5A, that this is exemplary and such as configuration is also applicable for larger and single die sets. In the particular embodiment illustrated inFIG.5A, dicing can be performed through a chip-level die-to-die routing110, which then terminates along a side edge111of a die102. Such processing may be acceptable where the metallic seals140with openings142provide sufficient sealing function for the devices. Alternatively, the metallic seals140along the die (chip) side edges111can be full seals, extending from the semiconductor substrate101to the top passivation layer135as shown inFIG.5B. In this case the chip-level die-to-die routing110at unconnected die side edges111ends at terminals107inside the full metallic seals140. In both embodiments illustrated inFIGS.5A-5Bselection devices, such as demultiplexers120and multiplexers122are included in order to select the chip-level die-to-die routing110, as opposed to the inter-die routings106, which optionally terminate at terminals108. An equivalent circuit can also be produced lithographically as illustrated inFIG.5C. As shown in the embodiment illustrated inFIG.5C, the communication devices (e.g. transceivers124, receivers126) are connected directly to the chip-level die-to-die routing110. In such embodiment, at decision operation2020, it is determined to pattern the chip-level die-to-die routing110. In such an embodiment, intra-die routing104may include common routing113that could have been used for either intra-die routing104or inter-die routing106. Thus, at operation2020it is determined to propagate the common routing as part of the chip-level die-to-die routing110. Thus, there may optionally not be an artifact of inter-die routing106present. In an embodiment, at operation2020it may optionally be determined to terminate the chip-level die-to-die routing110at unconnected die side edges111with terminals107, and to form full metallic seals140. However, this is optional, and dicing may also be performed through open chip-level die-to-die routing110along die edges111. Alternatively, where die sets are pre-determined, intra-die routing104does not exist adjacent the diced side edges111. FIG.6is a combination schematic cross-sectional side view illustration and circuit diagram for a chip160including a chip-level die-to-die routing110after bonding to a routing layer200in accordance with an embodiment. While the chip160included inFIG.6resembles that ofFIG.5A,FIG.6represents a system-level integration where any of the chips160ofFIGS.4-5Ccan be further integrated. For example, the chips160can be flip chip bonded with solder bumps152onto a routing layer200along with other system components. For example, routing layer200can be an interposer, package substrate, or system-level printed circuit board. An underfill material202may optionally be applied underneath the face side132of the chip160. In an embodiment, the underfill material202is an insulator material. The chip160may further be encapsulated in a molding compound (not illustrated) on top of the routing layer200. Referring now toFIGS.7-8Balternative embodiments are illustrated in which external die-to-die interconnection is made with the bond pads112rather than the chip-level die-to-die routing110.FIG.7is a circuit diagram of a die-to-die interconnect layout including (external) package-level die-to-die interconnection in accordance with an embodiment;FIG.8Ais a combination schematic cross-sectional side view illustration and circuit diagram for a package300including die set bonded to a routing layer302, where the dies include electrically open die-to-die routing and the routing layer includes package-level die-to-die routing310for interconnection of the die set in accordance with an embodiment;FIG.8Bis a combination schematic cross-sectional side view illustration and circuit diagram for a die set including a lithographically patterned inter-die routing106in accordance with an embodiment. In interest of clarity and concisenessFIGS.7-8Bare described concurrently. The configurations ofFIGS.7-8Bmay result after decision operation2020, it is determined to pattern the dies102for external die-to-die interconnection. For example, where it is determined that monolithic die-to-die interconnection may not meet yield requirements for larger die set, the dies102may be designed for external die-to-die interconnection at operation2020. In accordance with embodiments, the packages300ofFIGS.8A-8Bcan be formed using reconstitution techniques such as CoW reconstitution, or embedded wafer level processing. In some embodiments, CoW may include hybrid bonding, which can more closely match electrical characteristics of on-chip routing, with mitigated adjustments for performance differences, compared to flip chip solder bonding. Similarly, formation of the routing layer302directly on the dies102, such as a package-level redistribution layer during embedded wafer level processing can similarly be used to match characteristics of on-chip routing. It is to be appreciated that while a1xdie sets are separately bonded to the routing layer illustrated inFIG.8A, that this is exemplary and such as configuration is also applicable for larger die sets that can include chip-level die-to-die routing110therebetween. Specifically,FIG.7illustrates a circuit diagram similar to that ofFIG.1A. In the particular embodiment illustrated inFIG.7, the demultiplexer120and multiplexer122are configured to select the bond pads112for package-level die-to-die interconnection. Thus, the transceiver124and receiver126communicate through the bond pads112and package-level die-to-die routing310. The intra-die routings104are electrically open, or not formed at all. As shown inFIG.8A, the intra-die routings104may terminate at terminals107buried within the BEOL build-up structure130beneath the face side132of the BEOL build-up structures130A,130B. Thus, the intra-die routing104can optionally be terminated prior to addition of stitch routing105. In an alternative embodiment, the intra-die routing104can be propagated with stitch routing105, which can be cut during die singulation. In the embodiment illustrated inFIG.8B, intra-die routing104may optionally be included and also terminate within the BEOL build-up structure130. In accordance with embodiments, termination of the intra-die routing104within the BEOL build-up structure130, or not forming intra-die routing104at all, can help mitigate the generation of particles that may otherwise be associated with dicing through chip-level die-to-die routing110. In this manner, particle generation can be reduced, which can facilitate making the face sides132prime for CoW bonding, such as with hybrid bonding that can be particularly susceptible to particles. Furthermore, where dicing is not performed through metal layers, plasma dicing techniques may be employed, further reducing debris formation compared to other dicing techniques such as blade sawing or laser dicing. In a particular embodiment the routing layer302and dies102can be configured for hybrid bonding. Thus, die face sides132include a bonding layer139(e.g. oxide or polymer), chip-level landing pads138, and bond pads112. Similarly, the routing layer302includes a package-level bonding layer339(e.g. oxide or polymer), package-level landing pads338, and optionally package-level bond pads312. Depending upon determined die set configuration, a first group of the package-level bond pads312can be connected to package-level die-to-die routing310for interconnection with multiple dies102. A second group of package-level bond pads312may optionally be electrically open and used only to support hybrid bonding. In the illustrated embodiment, the second group of package-level bond pads312are not present. The BEOL build-up structures130A,130B illustrated inFIG.8Adiffer from those previously described for flip chip bonding. Foremost, test pads141can be embedded inside the BEOL build-up structures, beneath the face sides132, which can be planarized. As shown, a sealing layer137can be formed over the metallic seals140. Test pads141can be formed over the sealing layer137and connected to the underlying metallization layers with a via. In an embodiment, test pads141can be formed of a material (e.g. aluminum) different from the underlying metallization layers (e.g. copper). In some embodiments, test probes can leave indentations144on the test pads141, which may optionally be left electrically open, or further connected. An insulation layer145can be formed over the sealing layer137to cover the test pads141, and bonding layer139formed over the insulation layer145. Bond pads112and chip-level landing pads138can be connected to the underlying metallization layers with vias146extending through the sealing layer137, and optionally insulation layer145and bonding layer139. Routing layer302may be any suitable routing layer, including organic and inorganic interposers, and may be rigid or flexible. Routing layer may be passive or active interposers. In an active interposer, active devices supporting logic and buffering capabilities are feasible. Routing layer can include a plurality of wiring layers334and dielectric layers336. For example, routing layer302can be formed by a layer-by-layer thin film processing sequence, such as lamination of the dielectric layers336, followed by patterning and deposition of the wiring layers334and vias333. Dielectric layers336may be formed of suitable materials such as polymer, oxide, etc. The routing layer302may optionally include a rigid layer to provide structural integrity. In an embodiment, a plurality of dies102are bonded to a first side350of the routing layer302including package-level bonding layer339(e.g. oxide or polymer), package-level landing pads338, and optionally package-level bond pads312. For example, bonding may be hybrid bonding, with metal-metal bonds formed between package-level landing pads338and chip-level landing pads138, and package-level bond pads312and die bond pads112(when present). Dielectric-dielectric (e.g. oxide-oxide) bonds may be formed between the die bonding layers139and package-level bonding layer339. Alternatively, the routing layer302is formed over a reconstituted structure including dies102face up and embedded in a gap fill material360 In an embodiment, routing layer302is formed over a reconstituted structure including dies102face up and embedded in a gap fill material360. In an embodiment, the BEOL build-up structures130A,130B can include primarily Cu wiring, with an upper metal/wiring layer (e.g. M_high) including test pads being formed of Al. In an embodiment, the routing layer302wiring includes equivalent or thicker metal/wiring layers (though finer wiring is possible) than the upper metal/wiring layer (e.g. M_high) of the BEOL build-up structures130A,130B, or a wiring layer to which contact is made. The routing layer302can be formed using either Cu or Al wiring processes. In an embodiment, the routing layer302uses an Al wiring process, which may optionally use (single) damascene vias. Pads or vias used to contact the BEOL build-up structures130A,130B though may also be formed of Cu in accordance with embodiments. In some embodiments, the quality of service can be used to organize metal usage based on requirements such as latency, power, etc. Thus, in either processing sequence each die102can be a discrete component with a die-level BEOL build-up structure, and the dies102are connected to package-level die-to-die routing310in the routing layer302. The dies102may further be encapsulated in a gap fill material360on the first side350of the routing layer302. The gap fill material360can be formed over and between the separate dies102. Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc. A second side354of the routing layer302can further include a plurality of landing pads320. Solder bumps352may optionally be placed on the landing pads320for further package integration. As shown inFIGS.8A-8B, the packages may further include a carrier400on back sides of the dies102. For example, the carrier400may provide structural support and/or function as a thermal sink. Carrier400may be present where dies102are thinned in some configurations. Referring now toFIGS.9A-9B,FIG.9Ais a circuit diagram of an active routing layer302(e.g. interposer) in accordance with an embodiment;FIG.9Bis a circuit diagram of a die set bonded to an active routing layer302in accordance with an embodiment. As shown, the routing layer302can include transceivers324and receivers326, along with package-level bond pads312, which can be tested for addition of the dies102A,102B. For example, dies102A,102B can be hybrid bonded to the active routing layer302using bond pads112as previously described. An active routing layer302in accordance with embodiments may allow for function testing such as a power delivery network opens/shorts, capacitor opens/shorts and interconnect tests. The active routing layer302may additionally include buffers in the routing layers connecting transceivers324and receivers326. Upon testing of the active routing layer302, known good dies can then be bonded to known good sites of the active routing layer302. Transceiver324and receiver326can be tristated in functional mode as shown with dashed lines inFIG.9B(i.e. after die mounting), and only activated in a testing mode for the routing layer302(e.g.FIG.9A) to determine a known-good routing layer prior to die mounting. Transceiver124and receiver126from dies'102A,102B functional logic are used to communicate. The active routing layer302may provide additional buffering, routing, and logic functions. The packages300in accordance with embodiments can be singulated from a wafer-level or panel-level reconstitution sequence.FIGS.10A-10Bare schematic top view illustration of a plurality of dies102bonded to a routing layer302with pre-existing package-level die-to-die routing310for interconnection of die sets in accordance with embodiments. While not required, the routing layer302can be routed to carve out specific die sets, such as4X,6X,8X etc. depending upon production requirements. The pre-existing or later formed package-level die-to-die routing310is made possible by placement of known good dies102. As shown inFIGS.10A-10B, the dies102can be the same type (homogenous integration) or different (heterogenous integration), and may have different sizes, shapes, and technology nodes for the formation of devices. FIG.10Cis a combination schematic cross-sectional side view illustration and circuit diagram for dies102bonded to a routing layer302prior to singulation of die sets in accordance with an embodiment. As shown, the dies102can be bonded followed by encapsulation with a gap fill material360. Alternatively, the dies can be mounted onto the carrier400face up, followed by deposition of gap fill material, and formation of the routing layer302. Solder bumps352can optionally be placed onto landing pads320, followed by singulation of packages300including specified die sets. Packages300may then be further integrated. For example, in the embodiment illustrated inFIG.11, a package300can be bonded to a routing layer200such as another package substrate or system-level printed circuit board along with other system components and optionally underfilled with an underfill material202. Referring now toFIG.12, a package300is illustrated as including a chip including monolithic chip-level die-to-die routing110along with a second chip where the first chip and second chip are connected to external package-level die-to-die routing310. The embodiment illustrated inFIG.12illustrates how various embodiments can be combined, including the flexibility of the monolithic multi-die structure ofFIGS.1B and4-6with an additional die102/chip160using external die-to-die interconnection ofFIGS.7-11. It is to be appreciated a variety of combinations of the described embodiments are possible to combine both monolithically connected die sets and externally connected die sets. Additionally, the routing layer302can be active or passive. Up until this point, external die-to-die interconnection has been described as being made with bond pads112, and suitable techniques such as chip-on-wafer bonding or stitching with embedded wafer level processing. It is to be appreciated that external die-to-die interconnection can also be made with TSV die-to-die interconnection, as shown inFIGS.1A-1B. TSVs170can also be combined with the other monolithic or external die-to-die interconnection schemes, whether the TSVs170are ultimately connected or not. For example, the TSVs170may correspond to unconnected artifacts, or active die-to-die connections. Furthermore, TSVs170can be pre-selected without formation of inter-chip routing106or intra-chip routing104, or with electrically open inter-chip routing106and/or intra-chip routing104artifacts. Referring now toFIGS.13-15,FIG.13is a circuit diagram of TSV die-to-die interconnection layouts in accordance with an embodiment;FIGS.14-15are combination schematic cross-sectional side view illustrations and circuit diagrams for 3D die stacks including TSV die-to-die interconnection in accordance with embodiments. Specifically, the embodiment illustrated inFIG.14includes additional die stacked on top of an existing external die-to-die interconnection arrangement such as that illustrated and described with regard toFIGS.7-12, while the embodiment illustrated inFIG.15includes additional die stacked on top of an existing monolithic die-to-die interconnection arrangement such as that illustrated and described with regard toFIGS.4-6. It is to be appreciated, these are exemplary implementations, and embodiments including TSV die-to-die interconnection are not so limited. In interest of clarity and concisenessFIGS.13-15are described together. In the particular embodiments illustrated, one or more dies can be connected through TSV170routing. Similar to previous embodiments, the dies102A,102B can each include one or more selection devices (transceivers124and receivers126), as well as bypass routing172connecting the selection devices to the TSVs170, which are connected to back side pads174. As shown, one or more additional dies402A,402B can be bonded to the back sides of the dies102A,102B. For example, one or more dies can be bonded to the back side of a single die102A,102B. Alternatively, a die (e.g.402A) can be bonded to back sides, and span, multiple dies102A,102B. The additional dies402A,402B may further be encapsulated in a gap fill material460after mounting onto the underlying die(s)102A,102B. Gap fill material460may also be formed of similar materials as gap fill material360and may be formed directly on gap fill material360. In the particular embodiment illustrated, each additional die402A,402B includes at least one bond pad474that can be bonded with the back side pads174of the underlying dies102A,102B. For example, this may be a metal-metal bond as with hybrid bonding. Thus, the additional dies402A,402B can include a dielectric bonding layer477(e.g. oxide or polymer) that bonds with the back side passivation layer177(also oxide or polymer). Each additional die402A,402B may additionally include routing434connected to a corresponding selection device (e.g. transceiver424or receiver426) that is complementary with the selection device of the underlying die102A,102B to which it is electrically connected. While the additional dies402A,402B are illustrated as including a single selection device, it is to be appreciated this is intended to not overly complicate the drawings and that each of the additional dies402A,402B may include multiple selection devices, including transceivers and receivers to satisfy functionality. Furthermore, dies102A,102B may be connected to the additional dies402A,402B with multiple complementary selection devices. In an embodiment, a multi-die structure includes a routing layer302, a first die402A bonded to a first side of the routing layer302(FIG.14),200(FIG.15) and in electrical connection with the routing layer302,200. For example, this may be accomplished with chip-level landing pads138/package-level landing pads338and bond pads112/package-level bond pads312as shown in the embodiment illustrated inFIG.14. In the embodiment illustrated inFIG.15, the die set including dies102A,102B can be flip chip mounted onto the routing layer200. In either embodiment, the first die102A includes a first FEOL die area103A including a first communication device (e.g. transceiver124or receiver126), and a first BEOL build-up structure130A spanning over the first FEOL die area103A. The first BEOL build-up structure130A may include a face side including a plurality of chip-level landing pads138bonded to the routing layer302,200. The first BEOL build-up structure130A may additionally include an inter-chip routing106connected to the first communication device, as well as a TSV170connecting the first communication device to a back side pad174on a back side of the first die102A opposite the face side. Intra-chip routing104may also be connected to the first communication device along with the bypass routing172connecting the TSV170with the communication device. In the illustrated embodiment, a second die402A is bonded to the back side of the first die102A and in electrical communication with the back side pad174. For example, the second die402A can be hybrid bonded to the first die102A. In an embodiment, the first FEOL die area103A further includes a selection (e.g. multiplexer or demultiplexer) connected between the first communication device and the inter-chip routing106and the TSV170. The first die102A may additionally be connected to additional dies as described in previous embodiments. As shown inFIG.14, the first FEOL die area103A may additionally include a second communication device and a second inter-chip routing106connecting the second communication device to a bond pad112that is bonded to the first side of the routing layer302, and in electrical connection with third die102B that is also bonded to the first side of the routing layer302. The first die102A and the third die102B can be electrically connected to package-level die-to-die routing310as previously described. As shown inFIG.15, the first BEOL build-up structure is a chip-level BEOL build-up structure130including chip-level die-to-die routing110connecting the first die102A (and first communication device, receiver126) to a third die102B (and corresponding communication device, transceiver124) formed in a same semiconductor substrate101as the first die102A. As shown, embodiments facilitate the formation, and combination of, a variety of die-to-die interconnection schemes, and combinations of monolithic and/or external die-to-die interconnections. In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming die sets with dies configured for monolithic and external die-to-die interconnection. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration. | 54,053 |
11862558 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features may be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A 3D NAND device can include an array region and one or more connection regions positioned at boundaries of the array region. The array region can include a plurality of channel structures that extend through a plurality of word line layers stacked over a substrate of the device. The word line layers can further laterally extend to the connection region with a stair-cased/step-shaped configuration. A plurality of contact structures can be connected to the word line layers in the connection region and further coupled to external control signals. As 3D NAND devices move to higher capacity and density, especially from a 64 layer (64L) to 128 layer (128L) architecture, forming the stair-cased configuration of the connection region becomes an increasingly time-consuming process. The present disclosure includes embodiments directed to staircase configurations in a 3D NAND device. A staircase configuration can include a stair-cased connection region that is arranged between two array regions of the 3D NAND device, where the two array regions are formed at two opposing sides of the 3D NAND device. The staircase configuration can not only enhance word line controls but also simplify a manufacturing process and reduce or minimize mask layers, for example, by combining a chop process and a stair divided scheme during the manufacturing process. In addition, the stair-cased connection region includes stairs with non-quadrilateral treads, which can improve the density of contact structures that are formed on the stairs. FIG.1is a three-dimensional view of a 3D NAND device (or device)100. As shown inFIG.1, the device100can include a stack of word line layers and insulating layers that are arranged alternately over a substrate (not shown). The stack can have an array region102, where a plurality of channel structures (not shown) can extend from the substrate and extend through the word line layers and insulating layers in the array region102. The stack can also have a connection region that is formed with a stair-cased configuration and positioned at a side of the array region102. The connection region can have a first stair-cased portion104that is connected to one or more bottom select gates of the device100. The connection region can also have a second stair-cased portion106that is connected to the channel structures in the array region102to form an array of memory cells. In an exemplary embodiment ofFIG.1, the device100can have four blocks, where each of the four blocks can have one or more sub-blocks (also referred to as fingers, or finger structures). FIG.2is a top down view of a block200in the 3D NAND device100. The block200can have a connection region (also referred to as staircase region)202and an array region204. The connection region202is positioned at a first side of the array region204. In some embodiments, another connection region (not shown) can be positioned at a second side of the array region204. For example, the second side is opposite to the first side. The block200can have slit structures (also referred to gate line slits)206,208,210,212that divide the block200into three sub-blocks (or finger structures)213A-213C. The slit structures (e.g.,206and212) can be positioned at top and bottom boundaries of the block and have a continuous shape. The slit structures (e.g.,208,210) can be disposed within the block200and have a discontinuous shape. In some embodiments, a gate-last fabrication technology is used to form the 3D NAND device100. Thus the slit structures are formed to assist in the removal of sacrificial word line layers, and the formation of the real gates. In some embodiments, the slit structures can be made of conductive materials and positioned on array common source (ACS) regions to serve as contacts, where the ACS regions are formed in the substrate to serve as common sources. In some embodiments, the slit structures can be made of dielectric materials to serve as separation structures. The connection region202can have a plurality of stairs. For example, 14 stairs S1-S14are included in the connection region202ofFIG.2with a step-down direction along the −X direction. The connection region202can have a plurality of dummy channel structures218. The dummy channel structures218can be disposed at suitable places for process variation control during fabrication and/or for additional mechanical support. The connection region202can also have a plurality contact structures216that are positioned on the stairs S1-S14and connected to the word line layers. The contact structures216can extend from the stairs S1-S14and further be connected to metal layers (e.g., M0 layer, M1 layer) of the backend of line (BEOL), where the metal layers are stacked over the contact structures216. In the array region204, a plurality of channel structures214are disposed. The channel structures214can extend from the substrate and extend through the word line layers so as to form an array of vertical memory cell strings. Each of the vertical memory cell string can include a respective channel structure that is coupled to the word line layers to form one or more bottom select transistors (BSTs), a plurality of memory cells (MCs), and one or more top select transistors (TSTs) that are disposed sequentially and in series over the substrate. Each of the channel structures can further include a channel layer, a tunneling layer that surrounds the channel layer, a charge trapping layer that surrounds the tunneling layer, and a barrier layer that surrounds the charge trapping layer and further is in direct contact to the word line layers. In some embodiments, a high-K layer, such as HfO2or AlO, can be disposed between the word line layers and the barrier layer. In some embodiments, one or more trenches220, for example serving as top select gate cut (TSG-Cut) structures can be disposed in the array region204. As shown inFIG.2, the TSG-Cut structures220can be disposed in the middle of each of the finger (or sub-block) portions213A-213C to divide a top select gate (TSG) layer of the corresponding memory finger into two portions, and thereby can divide the corresponding memory finger portion into two separately programmable (read/write) pages. While an erase operation of a 3D NAND device can be carried out at a memory block level, read and write operations can be carried out at a memory page level. In the 3D NAND device100, the connection region202can be formed by performing a resist trim process and an etching process sequentially on the word line layers and the insulating layers. As shown inFIG.2, the connection region202is formed along one step-down direction (e.g., −X direction) with three or more stair divided schemes (or divided stair regions). Accordingly, the word line layers positioned at the bottom portion of the stack can have a long dimension along the step-down direction (e.g., −X direction) as the 3D NAND technology migrates to the 128L architecture, which can result in a high resistance-capacitance (RC) delay. In the present disclosure, staircase configurations in a 3D NAND device are provided. A connection region can be arranged between array regions (e.g., two array regions) of the 3D NAND device. The array regions are formed, for example, at two opposing sides of the 3D NAND device. One or more staircases can be formed in the connection region. Each staircase can have stairs with non-quadrilateral treads extending in two or more step-down directions. The staircase configuration can not only enhance word line controls but also simplify a manufacturing process and minimize a mask request by combining a chop process and a stair divided scheme during the manufacturing process. The non-quadrilateral treads can further improve the density of the contact structures positioned on the stairs. In the present disclosure, each staircase can further include quadrilateral treads and/or treads with other profiles, according to the process flow. FIG.3is a top down view of an exemplary 3D NAND device. For simplicity and clarity,FIG.3illustrates only one block300of the 3D NAND device. However, the 3D NAND device can include any number of blocks, for example, according to the circuit design. As shown inFIG.3, the block300can have a stack that is formed of alternatingly disposed word line layers and insulating layers over a substrate (not shown). The block300can have array regions (e.g., two array regions302and304) and a connection region306. The two array regions302and304are positioned at two opposing sides of the block300. The connection region306can be disposed between the two array regions302and304. The block300can also have a plurality of slit structures (or gate line slits)308,310,312,314,316,318,320,321, and322that can extend from the substrate and extend through the stack formed of alternatingly disposed word line layers and insulating layers. The slit structures308and310are positioned at the top and bottom boundaries of the block300respectively. The slit structures312and314are disposed within the array region302, and the slit structures316and318are disposed within the array region304. Accordingly, the array regions302and304are divided into three sub-blocks (or fingers)324A-324C by the slit structures312,314,316, and318. The slit structures320-322are positioned in the connection region306and can have a discontinuous configuration. In some embodiments, the slit structures320-322can be dummy slit structures, that is the slit structures320-322are not connected to any electrical inputs. In some embodiments, the slit structures (e.g.,320-322) in the connection region are not aligned with, or offset from, one or more of the slit structures (e.g.,312,314,316, and318) in the array regions. The slit structures can have different configurations in other embodiments. For example, the slit structures (e.g.,320-322) in the connection region can be aligned with the slit structures (e.g.,312,314,316, and318) in the array regions according to the circuit layout. Still inFIG.3, similar to the block200, the array regions302and304of the block300can have a plurality of channel structures326. The channel structures326can extend from the substrate and extend through the word line layers and the insulating layers in the array regions302and304. The connection region306can have a plurality of contact structures328and a plurality of dummy channel structures330. The contact structures328and dummy channel structures330are positioned on the word line layers and further extend from the word line layers in the connection region306(e.g., along a direction perpendicular to the substrate). For example, each of the plurality of contact structures328can be positioned on a different word line layer. The connection region306further can have a plurality of stairs332with non-quadrilateral treads. Generally, stairs are formed of treads and risers. In an example, a tread is the part that is disposed horizontally between a top edge of a lower riser and a bottom edge of an upper riser, and a riser connects treads (e.g., the part that is disposed vertically between an inner edge of a lower tread and an outer edge of an upper tread. In some examples, a stair is composed of a tread and a lower riser of the tread. The tread is the part that can be configured into a contact pad for one or more contact structures (e.g.,328) to land on. In an example of theFIG.3, the riser is the sidewall of a stack of layers, such as alternatingly disposed (sacrificial) word line layers and insulating layers. In the present disclosure, a height of the stair can be measured in terms of layer pairs of the word line layer and the insulating layer. In some embodiments, the non-quadrilateral treads332can be triangular, where each of the treads332can have three vertexes. The three vertexes can be located at three dummy channel structures330, and each of the three vertexes can be a respective dummy channel structure. In addition, each of the non-quadrilateral treads332can include a corresponding contact structure328. Each of the contact structures328is accordingly formed on a corresponding non-quadrilateral tread332and extends from the corresponding non-quadrilateral tread332to couple to a controller or a driver, such as a decode structure. FIG.4is a three-dimensional view of an embodiment of the connection region306in the block300. As shown inFIG.4, the connection region306can have a first staircase402and a second staircase404. In some embodiments, the connection region306includes a separation region406that is disposed between the first and second staircases402and404. In some embodiments, the first and second staircases402and406can include a plurality of non-quadrilateral treads. The first staircase402can have a first group of stairs402A and a second group of stairs402B. The first and second groups of stairs402A and402B may have the same number or different number of stairs, for example based on the number of word line layers in the stack. In an exemplary embodiment ofFIG.4, the first group of stairs402A can have a first step-down direction (e.g., X direction), and the second group of stairs402B can have a second step-down direction (e.g., −X direction). The first step-down direction is opposite to the second step-down direction so that the first group of stairs402A and the second group of stairs402B can converge at one or more shared stairs. The first and second groups of stairs402A and402B can further have one or more steps along a third step-down direction (e.g., Y direction) that is perpendicular to the first and second step-down directions. Similarly, the second staircase404can have a third group of stairs404A and a fourth group of stairs404B. The third and fourth groups of stairs404A and404B may have the same number or different number of stairs, for example based on the number of word line layers in the stack. The third group of stairs404A can have the first step-down direction (e.g., X direction), and the fourth group of stairs404B can have the second step-down direction (e.g., −X direction). The third group of stairs404A and the fourth group of stairs404B can converge at one or more shared stairs (e.g., stair408). The third and fourth groups of stairs404A and404B can have a fourth step-down direction (e.g., −Y direction) that is perpendicular to the first and second step-down directions. In some embodiments, the fourth step-down direction can be opposite to the third step-down direction. It should be noted thatFIG.4is merely an example, and the first and second staircases402and404can have any number of groups of stairs. In addition, each of the groups of stairs can have any number of stairs that extend in any number of step-down directions. For example, the first group of stairs404A may extend in the first step-down direction (e.g., X direction), also extend in the fourth step-down direction (e.g., −Y direction) and the third step-down direction (e.g., Y direction) according to the device structure design. FIG.5is schematic top down view of an embodiment of the connection region306in the block300. As shown inFIG.5, the first staircase402includes the first group of stairs402A having triangular treads and extending in the first step-down direction D1along the X direction. The first staircase402further includes the second group of stairs402B having triangular treads and extending in the second step-down direction D2along the −X direction. The first group of stairs402A and the second group of stairs402B converge at one or more first shared stairs, such as stairs labelled with 1, 3, and 5. The first group of stairs402A and the second group of stairs402B further extend in the third step-down direction D3along the Y direction. In an exemplary embodiment ofFIG.5, each of the first and second groups of stairs can have three steps along the Y direction. Accordingly, the first staircase can have three stair divided schemes (or three divided stair regions) along the third step-down direction. The second staircase404includes the third group of stairs404A having triangular treads and extending in the first step-down direction D1along the X direction. Further, the second staircase404includes the fourth group of stairs404B having triangular treads and extending in the second step-down direction D2along the −X direction. The third group of stairs404A and the fourth group of stairs404B converge at one or more first shared stairs, such as stairs labelled with 61, 63, and 65. The third group of stairs404A and the fourth group of stairs404B further extend in the fourth step-down direction D4along the −Y direction. In an exemplary embodiment ofFIG.5, each of the third and fourth groups of stairs can have three steps along the −Y direction. Accordingly, the second staircase can have three stair divided schemes (or three divided stair regions) along the third step-down direction. For example, the second staircase404can have three stair divided schemes SDS1, SDS2, and SDS3. In an exemplary embodiment ofFIG.5, the block300can include a stack with 120 pairs of word line layers and insulating layers. A top word line layer of the stack is labelled as 120 and a bottom word line layer of the stack is labelled as 1. Each stair has a numeric label that refers to a height of the stair, or a number of word line layers that the stair includes. The numeric label also refers to an exposed layer (or uppermost layer) of the word line layers in each stair. By introducing the first staircase402and the second staircase404, each of the word line layers in the block300can be exposed to receive a corresponding contact structure (e.g., contact structures328inFIG.3). For example, the stair408has a numeric label65, which means that the stair408includes 65 word line layers (or has a height of 65 word line layers), and a top layer that is exposed is a 65th word line layer in the stack. In some embodiments, each stair in the first staircase402can have a smaller height than a height of a stair in the second staircase404that is disposed on an opposite side of the separation region406. For example, the stair408in the second staircase402has a larger height (e.g.,65) than a height (e.g.,5) of the stair410in the first staircase402, and the stair408and stair410are disposed on two opposing sides of the separation region406. In addition, an uppermost stair412in the second staircase404and the separation region406can be of a same height (e.g., 120). A height difference between two adjacent stairs can be described based on the second staircase404. The first staircase402has a similar configuration to the second staircase404. According toFIG.5, the second staircase404can have three stairs along the fourth step down direction D4(e.g., −Y direction), and a height difference between two adjacent stairs (e.g., stair408and stair414) of the three stairs can be two, that is equal to a height of two word line layers. Further, the third group of stairs404A can have ten stairs along the first step-down direction D1and a height difference between two adjacent stairs can be one or 11, depending on locations of the stairs. For example, a stair416and a stair418have a height difference of one, and the stair418and a stair420have a height difference of 11. Similarly, the fourth group of stairs404B can have 11 stairs along the second step-down direction and a height difference between two adjacent stairs can be six, one, or 11, depending on locations of the stairs. The third group of stairs404A and the fourth group of stairs404B can converge at one or more shared stairs (e.g.,408,414). FIGS.6,7,8A,8B,9A,9B,10A,10B,11A, and11Bare first top-down views of various intermediate steps of manufacturing an exemplary 3D NAND device. InFIG.6, a stack600of word line layers and insulating layers are provided. In an exemplary embodiment ofFIG.6, 120 pairs of word line layers and insulating layers are stacked alternatingly in a substrate. In some embodiments, the word line layers formed in the stack600can be sacrificial word line layers, and the sacrificial word line layers can be replaced with a conductive material to form word line layers in subsequent manufacturing steps. In some embodiments, the sacrificial word line layers can be made of SiN, and the insulating layers can be made of SiO. Any suitable deposition process can be applied to form the sacrificial word line layers and the insulating layers. For example, a chemical vapor deposition process, a physical vapor deposition process, a diffusion process, an atomic layer deposition process, or other suitable deposition processes can be applied. InFIG.7, portions of one or more of the sacrificial word line layers and the insulating layers can be removed along a vertical direction (e.g., −Z direction) to define a first staircase region600A in the stack600. The vertical direction is perpendicular to the substrate. In order to remove the portions of the one or more sacrificial word line layers and the insulating layers in the stack600, a combination of a photolithography process and an etching process can be applied. The photolithography process can apply a mask layer over a top surface600C of the stack600to expose the first staircase region600A and cover a remaining region of the stack. The etching process can be applied subsequently to remove the portions of the one or more sacrificial word line layers and insulating layers in the first staircase region600A. Any number of word line layers in the first staircase region600A can be removed according to the device structure design. In an exemplary embodiment ofFIG.7, half of the word line layers in the first staircase region600A are removed along the vertical direction. FIGS.8A,9A,10A and11Aillustrate examples of forming the first and second staircases.FIGS.8B,9B,10B and11Billustrate a second example of forming the first and second staircases. InFIG.8A, a first stair608can be formed in the first staircase region600A and a second stair610can be formed in a second staircase region600B of the stack600. The sacrificial word line layers and insulating layers in the first staircase region600A can be shaped to form the first stair608. The first stair608can have a tread with a zig-zag edge profile P1and extend in a step-down direction along a first lateral direction (e.g., −X direction) parallel to the substrate. The first stair608separates the sacrificial word line layers and the insulating layers in the first staircase region600A into a first section602A and a second section602B. In addition, sacrificial word line layers and insulating layers in the second staircase region600B of the stack600can be shaped to form the second stair610. The second stair610can have a tread with the zig-zap edge profile P1and extend in a step-down direction along a lateral direction, such as the first lateral direction, where the second stair610separates the sacrificial word line layers and the insulating layers in the second staircase region600B into a third section604A and a fourth section604B. InFIG.8B, the first stair608can be formed to have a tread with a slant edge profile P2and extend in a step-down direction along the first lateral direction, and the second stair610can be formed to have a tread with the slant edge profile P2and extend in a step-down direction along a lateral direction, such as the first lateral direction. When the first and second staircase regions600A and600B are formed, a separation region606can be formed as a result in the stack600. The first and second staircase regions600A and600B can be separated by the separation region606of the stack600. In order to form the first and second stairs608and610, a combination of a photolithography process and an etching process can be applied. The photolithography process can apply a patterned mask layer to expose the first section602A of the first staircase region600A and the third section604A of the second staircase region600B. The etching process can be applied subsequently to remove portions of one or more of the sacrificial word line layers and the insulating layers in the first section602A of the first staircase region600A and in the third section604A of the second staircase region600B, respectively. The first and second stairs608and610can be formed as a result of the completion of the etching process. In an example, the patterned mask layer can be formed by the photolithography process to generate the zig-zap edge profile P1. In another example, the patterned mask layer can be formed by the photolithography process to generate the slant edge profile P2. FIG.9Aillustrates a subsequent process to the process inFIG.8A, andFIG.9Billustrates a subsequent process to the process inFIG.8B. InFIGS.9A and9B, one or more of the sacrificial word line layers and the insulating layers in the first staircase region600A can be shaped to form one or more stairs with a step-down direction along a second lateral direction (e.g., Y direction), where the second lateral direction is perpendicular to the first lateral direction (e.g., −X direction). For example, as shown inFIGS.9A and9B, three stairs can be formed in the first and second sections602A-602B of the first staircase region600A along the Y direction. Moreover, one or more of the sacrificial word line layers and the insulating layers in the second staircase region600B can be shaped to form one or more stairs with a step-down direction along a third lateral direction; For example, the third lateral direction (e.g., −Y direction) can be opposite to the second lateral direction. For example, three stairs can be formed in the third and fourth sections604A and604B of the second staircase region600B along the third lateral direction. In order to form the one or more stairs along the second or third lateral direction, a resist trim and an etching process can be operated alternately in the first and second staircase regions600A and600B respectively. For example, a resist layer can be deposited on the first section602A of the first staircase region600A. A photolithography process can introduce a patterned resist layer to expose a first part S1of the first section602A along the second lateral direction (e.g., Y direction). A plasma etching process can be applied to remove portions of one or more of the word line layers and insulating layers in the exposed first part S1. A resist trim process, such as a plasma ashing process, is thus applied to expose a second part S2of the first section602A along the second lateral direction, and the plasm etching process can be applied to remove portions of one or more of the word line layers and insulating layers in the exposed second part S2and exposed first part S1. The plasma ashing process can be subsequently applied again to remove the remaining resist layer. Once the remaining resist layer is removed, three stairs are formed in the first section602A of the first staircase region600A along the second lateral direction (e.g., Y direction). FIG.10Aillustrates a subsequent process to the process inFIG.9AandFIG.10Billustrates a subsequent process to the process inFIG.9B. InFIGS.10A and10B, a resist trim process and an etching process can be sequentially applied on the sacrificial word line layers and the insulating layers in the first and second staircase regions600A and600B to form a plurality of stairs. These processes can be applied concurrently or at different times in the first and second staircase regions600A and600B. The stairs can have treads with the zig-zag edge profile P1inFIG.10Aor have treads with the slant edge profile P2inFIG.10Baccording to the photolithography process. The stairs in the first section602A can have a step-down direction along a fourth lateral direction (e.g., X direction) and the stairs in the second section602B can have a step-down direction along the first lateral direction (−X direction). The stairs in the third section604A can have a step-down direction along the fourth lateral direction (e.g., X direction) and the stairs in the fourth section604B can have a step-down direction along the first lateral direction (e.g., −X direction). FIG.11Aillustrates a subsequent process to the process inFIG.10AandFIG.11Billustrates a subsequent process to the process inFIG.10B. InFIGS.11A and11B, the resist trim process and the etching process can be sequentially applied on the sacrificial word line layers and the insulating layers in the first and second staircase regions600A and600B to form a plurality of stairs. These processes can be applied concurrently or at different times in the first and second staircase regions600A and600B. The stairs can have treads with a zig-zag edge profile P3inFIG.11Aor have treads with a slant edge profile P4inFIG.11Baccording to the photolithography process. The stairs in the first section602A can have a step-down direction along the fourth lateral direction (e.g., X direction) and the stairs in the second section602B can have a step-down direction along the first lateral direction (−X direction). The stairs in the third section604A can have a step-down direction along the fourth lateral direction (e.g., X direction) and the stairs in the fourth section604B can have a step-down direction along the first lateral direction (e.g., −X direction). In some embodiments, the zig-zag edge profile P1and the zig-zag edge profile P3are symmetric along a direction A-A′ parallel to the second lateral direction (e.g., Y direction) or the third lateral direction (e.g., −Y direction). In some embodiments, the slant edge profile P2and the slant edge profile P4are symmetric along a direction B-B′ parallel to the second lateral direction (e.g., Y direction) or the third lateral direction (e.g., −Y direction). As shown inFIGS.11A and11B, when the resist trim process and the etching process are completed, the stack600can have a similar configuration to the connection region306inFIGS.4and5. For example, as shown inFIGS.11A and11B, the stack600can have a first staircase612that includes stairs having triangular treads and extending in a step-down direction along the fourth lateral direction (e.g., X direction) in the first section602A. The first staircase612can also include stairs having triangular treads and extending in a step down direction along the first lateral direction (e.g., −X direction) in the second section602B. The first staircase612further can extend in a step-down direction along the second lateral direction (e.g., Y direction). The stack600can have a second staircase614that includes stairs having triangular treads and extending in a step-down direction along the fourth lateral direction (e.g., X direction) in the third section604A. The second staircase614can also include stairs having triangular treads and extending in a step down direction along the first lateral direction (e.g., −X direction) in the fourth section604B. The second staircase614further can extend in a step-down direction along the third lateral direction (e.g., −Y direction). In addition, the first and second staircases612and614are separated, or spaced apart, from one another by the separation region606. FIGS.12-18are exemplary top-down views of various intermediate steps of manufacturing an exemplary 3D NAND device. Comparing to the top-down views of various intermediate steps illustrated inFIGS.6,7,8A,8B,9A,9B,10A,10B,11A, and11B, a photolithography-etch process (also referred to as photo-etch process) rather than a resist trim-etch process can be repetitively applied in order to form stairs with non-quadrilateral treads. In some embodiments, the photolithography-etch process can improve the edge profile of the treads. InFIG.12, a stack700can be formed over a substrate. The stack700can include 64 pairs of sacrificial word line layers and insulating layers that are stacked alternatingly in the substrate. InFIG.13, a first staircase region700A can be formed in the stack700where the top 32 pairs of the sacrificial word line layers and the insulating layers are removed in the first staircase region700A through a patterning process, such as a photolithography-etch process. InFIG.14, a combination of a photolithography process and an etching process can be applied to form a first stair708in the first staircase region700A and a second stair710in the second staircase region700B. The first stair708can have a tread with a slant edge profile, such as the slant edge profile P2, and divide the first staircase region700A into a first section702A and a second section702B. The first stair708can have a step-down direction along the −X direction. The second stair710can have a tread with the slant edge profile P2and divide the second staircase region700B into a third section704A and a fourth section704B. The second stair710can have a step-down direction along the −X direction. InFIG.15, a photolithography process and an etching process can be applied sequentially to form a plurality of stairs (e.g., two stairs), in the first staircase region700A, where the stairs extend in a step-down direction along the Y direction. The photolithography process and the etching process can further be applied sequentially to form a plurality of stairs (e.g., two stairs), in the second staircase region700B, where the stairs extend in a step-down direction along the −Y direction. In order to form the stairs along the Y or −Y direction, an exemplary embodiment can be provided according to the stairs formed in the first section702A. As shown inFIG.15, a patterned mask can be applied to cover a first part S1of the first section702A through the photolithography process, and the etching process can remove one or more of the sacrificial word line layers and the insulating layers in a second part S2. Further, a patterned mask can be applied to cover the second part S2of the first section702A through the photolithography process and the etching process can remove one or more of the sacrificial word line layers and the insulating layers in the first part S1. InFIG.16, the first staircase region700A and the second staircase region700B can be divided into four sub-sections by applying the photolithography process and the etching process sequentially to form more stairs that have treads with the slant edge profile P2. For example, four stairs can be formed in the first section702A. The four stairs in the first section702A can have treads with the slant edge profile P2and extend in the X direction. Similarly, four stairs can be formed in the second section702B. The four stairs in the second section702B can have treads with the slant edge profile P2and extend in the −X direction InFIG.17, the first staircase region700A and the second staircase region700B can be divided further into eight sub-sections by applying the photolithography process and the etching process sequentially to form more stairs. For example, eight stairs can be formed in the first section702A. The eight stairs in the first section702A can have treads with the slant edge profile P2and extend in the X direction. Similarly, eight stairs can be formed in the second section702B. The eight stairs in the second section702B can have treads with the slant edge profile P2and extend in the −X direction. InFIG.18, the photolithography process and the etching process can be sequentially applied on the sacrificial word line layers and the insulating layers in the first and second staircase regions700A and700B to form a plurality of stairs that have treads with a slant edge profile, such as the slant edge profile P4. The stairs in the first section702A can have a step-down direction along the X direction and the stairs in the second section702B can have a step-down direction along the −X direction. The stairs in the third section704A can have a step-down direction along the X direction and the stairs in the fourth section704B can have a step-down direction along the −X direction. When the photolithography process and the etching process are completed, the stack700can have a similar configuration to the connection region306inFIGS.4and5that includes a plurality of stair having non-quadrilateral treads. FIG.19is a flowchart of a process1900for manufacturing the disclosed 3D NAND device in accordance with some embodiments of the present disclosure. The process1900begins at step S1904where an initial stack of sacrificial word line layers and insulating layers can be formed over a substrate of the 3D NAND device. Subsequently, portions of one or more of the sacrificial word line layers and the insulating layers can be removed along a vertical direction in a first staircase region of a connection region of the initial stack. The connection region is positioned between array regions (e.g., two array regions) of the initial stack. The connection region is, for example, disposed at two opposing sides of the initial stack. In some embodiments, step S1104can be performed as illustrated with reference toFIGS.6and7. The process1900then proceeds to step S1906where one or more of the sacrificial word line layers and the insulating layers in the first staircase region can be shaped, or removed, to form a first stair. The first stair can have a tread with a first edge profile and extend in a step-down direction along a first lateral direction (e.g., −X direction). The first stair separates the sacrificial word line layers and the insulating layers in the first staircase region into a first section and a second section. Further, one or more sacrificial word line layers and insulating layers can be shaped, or removed, in a second staircase region of the connection region to form a second stair. The second stair can have a tread with an edge profile, such as the first edge profile, and extend in a step-down direction along a lateral direction, such as the first lateral direction. The second stair separates the sacrificial word line layers and the insulating layers in the second staircase region into a third section and a fourth section. The first and second staircase regions can further be separated by a separation region of the connection region. In some embodiments, the first stair can be formed before the second stair. In some embodiments, the second stair can be formed before the first stair. In some embodiments, the first and second stairs can be formed concurrently. In some embodiments, the step S1906can be performed as illustrated with reference toFIGS.8A and8B. In step S1908of the process1900, one or more of the sacrificial word line layers and the insulating layers in the first staircase region can be shaped to form one or more stairs with a step-down direction (e.g., second step down direction) along a second lateral direction (e.g., Y direction). The second lateral direction is, for example, perpendicular to the first lateral direction (e.g., −X direction). Further, one or more of the sacrificial word line layers and the insulating layers in the second staircase region can be shaped to form one or more stairs with a step-down direction (e.g., a third step down direction) along a third lateral direction (e.g., −Y direction). The third lateral direction is, for example, opposite to the second lateral direction. In some embodiments, the steps S1908can be performed as illustrated with reference toFIGS.9A and9B. The process1900then proceeds to step S1910where a patterning process, such as a resist trim-etching process, or a photolithography-etch process can be operated repetitively on the sacrificial word line layers and the insulating layers in the first and second staircase regions to form stairs having treads with the first edge profile in the first section and extending in a step-down direction along a fourth lateral direction (e.g., X direction), and stairs having tread with the first edge profile in the second section and extending in a step-down direction along the first lateral direction (e.g., −X direction), where the fourth lateral direction is for example opposite to the first lateral direction. Further, the patterning process can be operated repetitively on the sacrificial word line layers and the insulating layers in the second staircase region to form stairs having treads with the first edge profile in the third section and extending in a step-down direction along the fourth lateral direction (e.g., X direction), and stairs having treads with the first edge profile in the fourth section and extending in a step-down direction along the first lateral direction (e.g., −X direction). In some embodiments, the step S1910can be performed as illustrated with reference toFIGS.10A-10B. In step S1912of the process1900, the patterning process, such as a resist trim-etch process, or a photolithography-etch process can be operated repetitively on the sacrificial word line layers and the insulating layers in the first and second staircase regions to form stairs having treads with a second edge profile in the first section and extending in a fourth lateral direction (e.g., X direction), and stairs having tread with the second edge profile in the second section and extending in a step-down direction along the first lateral direction (e.g., −X direction). Further, the patterning process can be operated repetitively on the sacrificial word line layers and the insulating layers in the second staircase region to form stairs having treads with the second edge profile in the third section and extending in a step-down direction along the fourth lateral direction (e.g., X direction), and stairs having treads with the second edge profile in the fourth section and extending in a step-down direction along the first lateral direction (e.g., −X direction). In some embodiments, the first edge profile and the second edge profile are symmetric. In some embodiments, the first edge profile is a zig-zag edge profile or a slant edge profile. In some embodiments, the step S1912can be performed as illustrated with reference toFIGS.11A-11B. It should be noted that additional steps can be provided before, during, and after the process1900, and some of the steps described can be replaced, eliminated, or performed in a different order or separately in other embodiments of the process1900. For example, in subsequent process steps, channel structures can be formed in the array regions of the initial stack. The channel structures can extend from the substrate and extend through the sacrificial word line layers and the insulating layers in the array regions of the initial stack. The sacrificial word line layers then can be replaced with a conductive material to form word line layers. Further, first contact structures can be formed on the first staircase, and second contact structures can be formed on the second staircase. The first contact structures can be connected to the word line layers in the first staircase, and the second contact structures can be connected to the word line layers in the second staircase. Moreover, various additional interconnect structures (e.g., metallization layers having conductive lines and/or vias) may be formed over the 3D NAND device. Such interconnect structures electrically connect the 3D NAND device with other contact structures and/or active devices to form functional circuits. Additional device features such as passivation layers, input/output structures, and the like may also be formed. The various embodiments described herein can offer several advantages over related memory devices. For example, in the disclosed 3D NAND device, a connection region is arranged between array regions of the 3D NAND device, where the array regions can be formed at two opposing sides of the 3D NAND device. The disclosed connection region can have one or more staircases. The one or more staircases can further have two or more step-down directions. The disclosed connection region can not only enhance word line controls but also simplify a manufacturing process and minimize a mask request by combining a chop process and a stair divided scheme during the manufacturing process. In addition, the stair-cased connection region includes stairs with non-quadrilateral treads, which can improve the density of the contact structures that are formed on the stairs. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 46,590 |
11862559 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm. Still further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. An IC manufacturing process flow can typically be divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL) and back-end-of-line (BEOL). FEOL generally encompasses processes related to fabrication of IC devices, such as transistors. For example, FEOL processes can include formation of isolation structures for isolating IC devices, gate structures, and source and drain structures (also referred to as source/drain structures) that form a transistor. MEOL generally encompasses processes related to fabrication of connecting structures (also referred to as contacts or plugs) that connect to conductive features (or conductive regions) of the IC devices. For example, MEOL processes can include formation of connecting structures that connect to the gate structures and connecting structures that connect to the source/drain structures. BEOL generally encompasses processes related to fabrication of multilayer interconnect (MLI) structures that electrically connect the IC devices to the connecting structures fabricated by FEOL and MEOL. Accordingly, operation of the IC devices can be enabled. As mentioned above, the scaling-down processes have increased the complexity of processing and manufacturing ICs. In some embodiments, a BEOL MLI includes a plurality of metal layers (or metallization lines) referred to as, in ascending order, a zeroth metal layer M0, a first metal layer M1, and an Nth metal layer Mn, and a plurality of connecting vias referred to as a first via V1, a second via V2, and an (N−1)th via Vn−1, where n is a positive integer. The connecting vias are configured to electrically couple together two adjacent metal layers. For example, the (N−1)th metal layer Mn−1 and the Nth metal layer Mn may be electrically connected by the (N−1)th via Vn−1. Further, the metal layer Mn and the connecting vias Vn−1 may be formed in an inter-metal dielectric (IMD) layer IMDn to provide mechanical support and electrical isolation therebetween. In some embodiments, the formation of the metal layers and the connecting vias include forming openings in an IMD layer, filling the openings with a conductive material(s), and performing a planarization process, such as a chemical mechanical polishing (CMP) operation, to the conductive material(s). In some comparative approaches, it is found that when the metal layers become shorter due to downscaling, the above-mentioned filling of the openings with conductive material(s) becomes much more challenging. Such challenge associated with opening-filling or gap-filling may cause voids in the metal layers, which may adversely impact device performance. The present disclosure provides a semiconductor structure and a method for forming the same. In the present embodiments, a metallization line is formed in an inter-metal dielectric layer and a metal-cutting operation is performed to remove portions of the metallization line, thereby segmenting the metallization line into multiple metallization features. Subsequently, openings formed by the segmenting are filled with a dielectric material to provide isolation between the metallization features. Accordingly, the gap-filling issue may be mitigated, and the device performance can be ensured. FIG.1is a flowchart representing a method10for forming a semiconductor structure200according to aspects of the present disclosure. In some embodiments, the method10includes a number of operations (11,12,13,14and15) and is further described below according to one or more embodiments. It should be noted that the operations of the method10may be omitted, rearranged, or otherwise modified within the scope of the various aspects. It should further be noted that additional operations may be provided before, during, and after the method10, and that some other operations may be only briefly described herein. In the present embodiments, the method10is used to form a BEOL interconnection (e.g., MLI) structure, in part or in entirety, over a semiconductor structure. In some embodiments, the method10can be used to form a zeroth metal layer M0 of a semiconductor structure. For example,FIGS.2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,13A,14A,15A,16A,17A,18A, and19Aare schematic planar top views of a semiconductor structure at various stages of the method10according to aspects of one or more embodiments of the present disclosure. Further,FIGS.2B,3B,4B,5B,6B,7B,8B,9B,10B,11B,13B,14B,15B,16B,17B,18B, and19Bare schematic cross-sectional views of the semiconductor structure taken along line II-II′ ofFIGS.2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,13A,14A,15A,16A,17A,18A, and19A, respectively, according to aspects of one or more embodiments of the present disclosure.FIGS.2C,3C,4C,5C,6C,7C,8C,9C,10C,11C,12,13C,14C,15C,16C,17C,18C, and19Care schematic cross-sectional views taken along line I-I′ ofFIGS.2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,13A,14A,15A,16A,17A,18A, and19A, respectively, according to aspects of one or more embodiments of the present disclosure. Referring toFIGS.2A to2C, in operation11, the method10receives (or is provided with) a semiconductor structure200(hereinafter referred to as structure200) that includes a semiconductor substrate202. In some embodiments, the semiconductor substrate202including one or more FEOL devices can be a portion of an IC chip, a system on chip (SoC), or a portion of a system on chip. In some embodiments, the semiconductor substrate202can be a substrate accommodating FEOL devices such as microprocessors, memories, and/or other IC devices. In some embodiments, the semiconductor substrate202can include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide semiconductor field-effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The transistors may be planar transistors or multi-gate transistors, such as fin-like FETs (FinFETs).FIGS.2A to2Chave been simplified for the sake of clarity to better illustrate the inventive concepts of the present disclosure. In some embodiments, the semiconductor substrate202includes silicon. Alternatively or additionally, the semiconductor substrate202includes another elementary semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In some implementations, the semiconductor substrate202includes one or more group III-V materials, one or more group II-IV materials, or a combination thereof. In some implementations, the semiconductor substrate202is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In the present embodiments, the semiconductor substrate202includes one or more three-dimensional, fin-like active regions (or fins)204over which components including gate structures and epitaxial source/drain features are subsequently formed to provide one or more FEOL devices. Referring toFIG.2B, the fins204are oriented lengthwise along a direction D2and spaced from each other along a direction D1that is substantially perpendicular to the direction D2. In some embodiments, the fin204includes a single semiconductor layer configured to provide a fin-like device, such as fin-like field-effect transistor (FinFET). In some embodiments, the fin204includes a stack of semiconductor layers interleaved with a portion of a gate structure to provide a gate-all-around (GAA) device, such as GAA FET. The semiconductor substrate202may include various doped regions (not shown) configured according to design requirements of an FEOL device, such as p-type doped regions, n-type doped regions, or combinations thereof. P-type doped regions (for example, p-type wells) include p-type dopants, such as boron, indium, another p-type dopant, or a combination thereof. N-type doped regions (for example, n-type wells) include n-type dopants, such as phosphorus, arsenic, another n-type dopant, or a combination thereof. In some implementations, the semiconductor substrate202includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions can be formed directly on and/or in the semiconductor substrate202, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and/or another suitable doping process can be performed to form the various doped regions. The structure200further includes isolation features206formed over and/or in the semiconductor substrate202to electrically isolate various regions, such as various device regions, of the structure200. For example, the isolation features206can define and electrically isolate active device regions and/or passive device regions from each other. The isolation features206can include silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material, or a combination thereof. The isolation features206can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. Various gate structures can be disposed over the semiconductor substrate202, such as gate structures208. In some embodiments, the gate structures208extend lengthwise along the direction D1and spaced from each other along the direction D2, i.e., the gate structures208are oriented substantially perpendicular to the fins204. As shown inFIG.2B, the gate structures208interpose a source region and a drain region, where a channel region is defined between the source region and the drain region. In some embodiments, the gate structures208are formed over a fin structure. In some embodiments, the gate structures208include a metal gate structure. In some embodiments, the metal gate structure includes a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. A high-k dielectric material generally refers to a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of silicon oxide (k≈3.9). Example high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable materials, or combinations thereof. For example, the gate dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2—Al2O3, TiO2, Ta2O5, La2O3, Y2O3, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate structure208may include other material layers, such as an interfacial layer (IL) including, for example, silicon oxide, a barrier layer, a capping layer, other suitable layers, or combinations thereof. The gate electrode includes an electrically-conductive material, such as one or more metals. Accordingly, the gate structures208may be referred to as high-k metal gate stacks. In some implementations, the gate electrode includes multiple layers, such as one or more work function metal layers and gap-filling metal layers. The work function metal layer includes a conductive material tuned to have a desired work function (such as an n-type work function or a p-type work function). Example work function materials include TiN, TaN, Ru, Mo, Al, ZrSi2, MoSi2, TaSi2, NiSi2, WN, Ti, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other suitable work function materials, or combinations thereof. The gap-filling metal layer may include a suitable conductive material, such as Al, W, Cu, Co, Ru, other suitable conductive materials, or combinations thereof. The gate structures208may further include spacers209, which are disposed adjacent to (for example, along sidewalls of) the gate structures208. The spacers209may be formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, another suitable material, or a combination thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some embodiments, the spacers209include a multilayer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. In some embodiments, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are formed adjacent to the gate structures208. Implantation, diffusion, and/or annealing processes can be performed to form lightly-doped source and drain (LDD) features and/or heavily-doped source and drain (HDD) features in the semiconductor substrate202before and/or after the forming of the spacers. In the present embodiments, source/drain (S/D) regions of each fin204include epitaxial S/D structures210. For example, a semiconductor material may be epitaxially grown on the semiconductor substrate202to form the epitaxial S/D structures210over a source region and a drain region of the semiconductor substrate202. Accordingly, the gate structure208, the epitaxial S/D structure210, and a channel region defined between the epitaxial source/drain structures form an FEOL device, such as a transistor. In some embodiments, the epitaxial S/D structures210surround source/drain regions of a fin structure. In some embodiments, the epitaxial S/D structures210replace portions of the fin structure. The epitaxial S/D structures210are doped with n-type dopants and/or p-type dopants. In some embodiments, where the transistor is configured as an n-type device (for example, a device having an n-channel), the epitaxial S/D structures210include silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers doped with phosphorous, other n-type dopants, or combinations thereof (for example, forming Si:P epitaxial layers or Si:C:P epitaxial layers). In some embodiments, where the transistor is configured as a p-type device (for example, a device having a p-channel), the epitaxial S/D structures210include silicon-and-germanium-containing epitaxial layers doped with boron, other p-type dopants, or combinations thereof (for example, forming Si:Ge:B epitaxial layers). In some embodiments, the epitaxial S/D structures210include materials and/or dopants that achieve desired tensile stress and/or compressive stress in the channel region. In some embodiments, a metal silicide layer210smay be formed on top surfaces of the epitaxial S/D structures210. As shown inFIGS.2A to2C, the structure200may further include a plurality of S/D contacts211on the epitaxial S/D structures210and in dielectric layers212and213. In the present embodiments, the dielectric layer212is a contact etch-stop layer (CESL) and includes a suitable dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), other dielectric materials, or combinations thereof. In the present embodiments, the dielectric layer213is an interlayer-dielectric (ILD) layer and includes a suitable dielectric material, such as silicon oxide (SiO), tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, other dielectric materials, or a combination thereof. Example low-k dielectric materials may include fluoride-doped silicate glass (FSG), carbon-doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SILK (Dow Chemical, Midland, Mich.), polyimide, other low-k dielectric materials, and combinations thereof. As shown inFIGS.2A to2C, the dielectric layer212is disposed over the epitaxial S/D structures210, and the dielectric layer213is disposed over the dielectric layer212. Furthermore, the structure200includes a dielectric layer214disposed over the S/D contacts211and the dielectric layers212and213. In the present embodiments, the dielectric layer214is an etch stop layer having a single-layered structure or a multi-layered structure. For example, in the depicted embodiments, the dielectric layer214include a first etch stop layer214-1and a second etch stop layer214-2over the first etch stop layer214-1. In some embodiments, the first etch stop layer214-1and the second etch stop layer214-2may each include silicon nitride (SiN), silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), hafnium oxide (HfO), zinc oxide (ZnO), titanium oxide (TiO), tantalum oxide (TaO), tantalum carbonitride (TaCN), yttrium oxide (YO), silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), other suitable materials, or combination thereof. In some embodiments, the first etch stop layer214-1and the second etch stop layer214-2include different materials. In some embodiments, a thickness of each of the first etch stop layer214-1and the second etch stop layer214-2is approximately 2 nanometers to approximately 20 nanometers, but the disclosure is not limited thereto. In some embodiments, a plurality of connecting vias216are formed in the dielectric layer214over the source/drain region or the gate structure208, as shown inFIGS.2A to2C. In some embodiments, the connecting vias216each include a bulk conductive layer having Co, W, Ru, Al, Mo, Ti, Cu, other suitable conductive materials, or combinations thereof. In some embodiments, the connecting vias216each include a barrier layer (not shown separately) over which the bulk conductive layer is disposed, and the barrier layer may include titanium nitride (TiN), titanium silicide (TiSi), titanium silicide nitride (TiSiN), cobalt silicide (CoSi), Ni, nickel silicide (NiSi), Cu, tantalum nitride (TaN), other suitable materials, or combination thereof. In some embodiments, the connecting vias216include a via-to-gate (VG), which generally refers to a contact coupled to the gate structure208, such that the gate structure208may be connected to a BEOL interconnection (not shown) through the connecting via216. In some embodiments, the connecting vias216include a via-to-drain (VD), which generally refers to a contact coupled to a source/drain region, such that the epitaxial S/D structures210may be connected to the BEOL interconnection through the connecting via216. Accordingly, the FEOL devices can be electrically connected to the BEOL interconnection through the connecting vias216, which may also be referred to as the MEOL interconnect structures. Referring toFIGS.3A to3C, in operation11, the method10forms a dielectric layer220over the structure200. The dielectric layer220can be referred to as an IMD layer or alternatively, as an ILD layer. The dielectric layer220may include a dielectric material including, for example, silicon oxide, TEOS, PSG, BPSG, a low-k dielectric material (examples provided above), another suitable dielectric material, or a combination thereof. In some embodiments, the dielectric layer220and the dielectric layer214include different materials. In some embodiments, the dielectric layer220and the second etch stop layer214-2include different materials. A thickness of the dielectric layer220may be approximately 0.5 nanometers to approximately 30 nanometers, but the disclosure is not limited thereto. In the present embodiments, the thickness of the dielectric layer220is greater than that of the first etch-stop layer214-1and the second etch-stop layer214-2. In operation12, the method10forms a trench225in the dielectric layer220. Referring toFIGS.4A to4C, in some embodiments, forming the trench225includes first forming a patterned masking element221over the dielectric layer220. In some embodiments, the patterned masking element221includes a top layer comprising a resist material (e.g., a photoresist layer), a middle layer, and a bottom layer (e.g., an anti-reflective coating). The masking element may be patterned via a series of lithography and etching processes during which the top layer is patterned by being exposed to radiation through a photomask, the exposed top layer is developed to form a patterned resist, and the underlying middle and bottom layers are subsequently etched (by, for example, a dry etching process, a wet etching process, a reactive ion etching (RIE) process, or combinations thereof) using the patterned resist as a mask to form the patterned masking element221. In the present embodiments, the patterned masking element221includes a plurality of openings223configured to define a dimension and location of the trench225to be formed in the dielectric layer220. Accordingly, portions of the dielectric layer220are exposed though the openings223. Referring toFIGS.5A to5C, the portions of the dielectric layer220exposed through the openings223of the patterned masking element221are removed by one or more suitable etching process, such as a dry etching process, a wet etching process, an RIE process, or combinations thereof, thereby forming one or more trenches225in the dielectric layer220. The patterned masking element221is then removed after the forming of the trenches225by a suitable method, such as plasma ashing and/or resist stripping. In the present embodiments, the trenches225are configured to expose a top surface of each connecting via216and the dielectric layer214(i.e., the second etch stop layer214-2), and further define sidewalls of the dielectric layer220. Due to factors such as uneven etchant loading while forming the trench225, an opening of a bottom portion of the trench225(for example, a length of the trench225defined along the direction D2) is less than an opening of a top portion of the trench225, i.e., the trench225is configured with an inverted trapezoidal profile, as shown inFIG.5C. In other words, an included angle226of the trench225as shown inFIG.5Cis greater than about 90°, i.e., the included angle226is an obtuse angle. In some embodiments, still referring toFIGS.5A to5C, a length L of the trench225defined along the direction D2is greater than a width W of the trench225defined along the direction D1, though the present disclosure does not limit the length L or the width W to any particular dimensions. Notably, in the present embodiments, the width W corresponds to a width of a subsequently-formed metallization feature in the trench225along the direction D1, while the length L is greater than a length of such metallization feature along the direction D2. In other words, a metallization line subsequently formed in the trench225further undergoes a cutting (or etching) process to define multiple metallization features of desired dimension (i.e., length) and locations. In contrast, existing implementations generally form metallization features by directly patterning the dielectric layer220to form openings with the desired final dimensions (i.e., both length and width) for the metallization features, and subsequently filling the openings with a conductive material to form the metallization features. In some instances, filling such small openings may introduce unwanted voids, which adversely affects performance of the device. Embodiments provided herein may circumvent such shortcomings by first forming a metallization line in a trench configured to have a greater length than a final length of each metallization feature, thereby reducing the formation of voids, and subsequently segmenting (and isolating) the metallization line to multiple portions that correspond to the final lengths of the metallization features. In operation13, the method10fills the trench225to form a metallization line (or a metal layer)234in the dielectric layer220. Referring toFIGS.6A to6C, in the present embodiments, the trenches225are filled with a conductive material230including, for example, Co, W, Ru, Al, Mo, Ti, Cu, other suitable conductive materials, or combinations thereof. In some embodiments, the conductive material230is the same as the composition of bulk conductive layer of the connecting via216. The conductive material230may be formed by any suitable deposition process including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof. In the present embodiments, the metallization line234is configured with an inverted trapezoidal shape according to the profile of the trench225discussed in detail above. In some embodiments, a barrier layer232is formed in the trench225prior to the depositing of the conductive material230. In some embodiments, the barrier layer232includes Ti, TiN, Ta, TaN, W, WN, other suitable materials, or combinations thereof. The barrier layer232may be formed by any suitable method, such as CVD, ALD, PVD, other methods, or combinations thereof. A thickness of the barrier layer232may be approximately 0.5 nanometer to approximately 10 nanometers, but the disclosure is not limited thereto. The barrier layer232may be a single-layered structure, or, alternatively, a multi-layered structure. For example, the barrier layer232may include a sub-barrier layer232-1and a sub-barrier layer232-2(both shown inFIG.12). In such embodiments, the sub-barrier layer232-1and the sub-barrier layer232-2include different materials. A thickness of the sub-barrier layer232-1may be approximately 0.5 nanometer to approximately 10 nanometers, and a thickness of the sub-barrier layer232-2may be approximately 0.5 nanometer to approximately 10 nanometers, but the disclosure is not limited thereto. Referring toFIGS.7A to7C, the method10removes any superfluous materials from a top surface of the dielectric layer220in a CMP operation. Accordingly, portions of the conductive material230and portions of the barrier layer232are removed to obtain a metallization line234in the dielectric layer220. As shown inFIGS.7A and7C, the metallization line234extends along the direction D2. In some embodiments, a width of the metallization line234, i.e., the width W defined previously, is greater than a width of the connecting via216, as shown inFIG.7B, to ensure that the metallization line234is in contact with the connecting via216and is thus electrically connected to the FEOL devices formed over the semiconductor substrate202. In the present embodiments, the metallization line234includes a plurality of bottom corners, and each of the bottom corners is defined by the included angle226defined previously. Accordingly, in the present embodiments, the included angle226of the bottom corners of the metallization line234is greater than 90°, i.e., an obtuse angle. In operation14, the method10segments (or separates) the metallization line234to form at least a metallization feature240aand a metallization feature240b, disposed adjacent to each other and oriented lengthwise along the direction D2. In the present embodiments, the metallization feature240aand the metallization feature240bare separated from each other by a recess241defined by the metallization line234and the dielectric layer220(shown inFIGS.9A to9C). Referring toFIGS.8A to8C, in the present embodiments, a patterned masking element235is formed over the semiconductor substrate202and includes a plurality of openings237for defining dimensions and locations of recesses241to be formed. In some embodiments, the patterned masking element235is similar to the patterned masking element221in terms of structure and method of processing. In the present embodiment, portions of the metallization line234are exposed through the openings237. In the depicted embodiments, a length of a portion of the metallization line234disposed under the patterned masking element235corresponds to a length of the subsequently-formed metallization feature240aor240b, where a width of each of the metallization features240aand240bhas been previously defined as the width W. Referring toFIGS.9A to9C, the method10performs an etching operation, such as a dry etching process, a wet etching process, an RIE process, or combinations thereof, to remove the portions of the metallization line234exposed through the patterned masking element235, resulting in one or more recesses241. In the present embodiments, the recesses241are formed to segment (or separate) the metallization line234into at least the metallization features240aand240b. In the present embodiments, the recesses241expose portions of the dielectric layer214. In some embodiments, because the metallization features240aand240bare formed by etching the metallization line234, geometric profiles of the metallization features240aand240bmay be different from each other, the details of which are discussed below. After segmenting the metallization line234, the patterned masking element235is removed from the structure200by a suitable method, such as plasma ashing and/or resist stripping. In operation15, the method10fills the recesses241with a dielectric material242. Referring toFIGS.10A to10C, in the present embodiments, the dielectric material242is formed to fill the recesses241and may cover top surfaces of the metallization features240aand240band the dielectric layer220. The dielectric material242may be referred to as an IMD layer. The dielectric material242may include, for example, silicon oxide, TEOS, PSG, BPSG, low-k dielectric material (examples provided above), another suitable dielectric material, or a combination thereof. In some embodiments, the dielectric material242and the dielectric layer220include different materials. In some embodiments, the dielectric material242and the dielectric layer220include the same material. Referring toFIGS.11A to11C, in the present embodiments, the method10removes superfluous dielectric material242by a planarization process, such as a CMP process, thereby forming dielectric features244between the metallization features240aand240b. In other words, the metallization feature240aand the metallization feature240bare separated from each other by the dielectric feature244. For purposes of discussion and not intending to be limiting, metallization features240aand240a′ (as well as the metallization features240band240b′) are substantially the same with respect to dimension and geometry and are separated along the direction D1. As depicted herein, when viewed along the direction D2, the metallization feature240ais end-capped by a portion of the dielectric layer220and the dielectric feature244, and the metallization feature240bis end-capped by the dielectric features244. As shown inFIG.11C, top surfaces of the metallization features240aand240b, a top surface of the dielectric layer220, and a top surface of the dielectric feature244are substantially aligned with each other, i.e., are substantially co-planar. Accordingly, in the present embodiments, metallization features belonging to different metallization lines234, such as the metallization features240aand240a′ or the metallization features240band240b′, are separated from each other by the dielectric layer220along the direction D1. In contrast, metallization features belonging to the same metallization line234, such as the metallization features240aand240b, are separated from each other by the dielectric features244. In the depicted embodiments, the metallization feature240aand the metallization feature240bare defined by a length L1and L2, respectively, along the direction D2, which are both less than the length L of the trench225as defined previously. Referring toFIG.12, which is the same asFIG.11Cbut depicted with more details, the structure200includes at least a zeroth metal layer M0 formed by the method10, where the metal layer M0 includes the metallization feature240aand the metallization feature240bhaving different geometric profiles and separated by the dielectric layer220and/or the dielectric feature244. In the present embodiments, referring toFIGS.11A to11C and12, the metallization feature240aincludes a pair of long sides defined by a portion of the dielectric layer (the portion may alternatively be referred to as dielectric feature220hereafter) along the direction D2, one short side defined by the dielectric feature244, and another short side defined by a portion of the dielectric layer220along the direction D1. The metallization feature240ahas a first bottom corner C1adjacent to the dielectric feature244and a second bottom corner C2adjacent to the dielectric layer220, where the first bottom corner C1is defined by an included angle θ1and the second bottom corner C2is defined by an included angle θ2(corresponding to the included angle226as discussed above with reference toFIG.6C). In the present embodiments, the included angle θ1of the first bottom corner C1is less than about 90° (i.e., is an acute angle), and the included angle θ2of the second bottom corner C2is greater than about 90° (i.e., is an obtuse angle). Further, in the present embodiments, because the barrier layer232is formed before forming the dielectric features244, the barrier layer232is disposed along, and in direct contact with an entirety of, the sidewall of the metallization feature240adefined by the dielectric layer220but not along the opposite sidewall of the metallization feature240adefined by the dielectric feature244. In the present embodiments, portions of the barrier layer232are disposed between the metallization feature240aand the underlying dielectric layer214. Still further, in the present embodiments, the metallization feature240ais in direct contact with at least one connecting via216, thereby allowing the FEOL device disposed over the semiconductor substrate202to be electrically connected to the metallization feature240a. In the present embodiments, still referring toFIGS.11A to11C and12, the metallization feature240bincludes a pair of long sides defined by a portion of the dielectric layer220(i.e., the dielectric feature220) along the direction D2(as shown inFIG.11A), and a pair of short sides defined by the dielectric features244along the direction D1. In other words, the metallization feature240bis end-capped by the dielectric features244. The metallization feature240bhas a third bottom corner C3and a fourth bottom corner C4opposite to the third bottom corner C3along the direction D2. The third bottom corner C3is defined by an included angle θ3and the fourth bottom corner C4is defined by an included angle θ4. In the present embodiments, though the included angle θ3of the third bottom corner C3and the included angle θ4of the fourth bottom corner C4may differ in magnitude, they are both less than 90°, i.e., are both acute angles. Thus, the metallization feature240bis defined by a trapezoid shape, such that its width along the direction D2increases towards the semiconductor substrate202. Further, in the present embodiments, because the barrier layer232is formed before forming the dielectric features244, the barrier layer232is not entirely disposed along either sidewall of the dielectric features244that end-cap the metallization features240b. Of course, the barrier layer232is disposed between the metallization feature240band the dielectric layer214as discussed above with respect to the metallization feature240a. Still further, in the present embodiments, the metallization feature240bis in direct contact with at least a connecting via216(not shown), thereby electrically connecting the FEOL device formed over the semiconductor substrate202to the metallization feature240b. In the present embodiments, and for reasons discussed above with respect to the included angle226, the included angle θ2of the second bottom corner C2of the metallization feature240a, which is adjacent to the dielectric layer220and formed prior to the forming of the metallization features240aand240b, is greater than about 90°. In contrast, the included angle θ1of the first bottom corner C1of the metallization feature240a, the included angle θ3of the third bottom corner C3of the metallization feature240b, and the included angle θ4of the fourth bottom corner C4of the metallization feature240b, which are adjacent to the dielectric features244and formed with the forming of the metallization features240aand240b, are less than about 90°. Accordingly, the present embodiments provide that the dielectric feature244is defined by an inverted trapezoid shape. In other words, a width of the dielectric feature244defined along the direction D2decreases towards the semiconductor substrate202. In some embodiments, a width of a bottom portion of the dielectric feature244is approximately 1 nanometer to approximately 13 nanometers, and a width of a top portion of the dielectric feature244is approximately 2 nanometers to approximately 15 nanometers; of course, the disclosure is not limited thereto. In some embodiments, the method10may be used to form an Nth metal layer Mn over the structure200, where N is a positive integer. For example,FIGS.13A,14A,15A,16A,17A,18A, and19Aare schematic planar top views of a semiconductor structure at various stages in the method10according to aspects of one or more embodiments of the present disclosure. Further,FIGS.13B,14B,15B,16B,17B,18B,19B, and20are schematic cross-sectional views taken along line II-II′ ofFIGS.13A,14A,15A,16A,17A,18A, and19A, respectively.FIGS.13C,14C,15C,16C,17C,18C, and19Care schematic cross-sectional views taken along line I-I′ ofFIGS.13A,14A,15A,16A,17A,18A, and19A, respectively. It should be noted that in the present embodiments, the method10is performed to form the zeroth metal layer M0 as discussed above with respect toFIGS.2A to12or to form any subsequent metal layer, e.g., the first metal layer M1 over the zeroth metal layer M0, the second metal layer M2 over the first metal layer M1, etc. Therefore, the same elements of the structure200inFIGS.2A to12and inFIGS.13A to20are indicated by the same reference numerals, and repeated descriptions of such elements are omitted for brevity. Referring toFIGS.13A to13C, in operation11, the method10receives (or is provided with) the structure200that includes the semiconductor substrate202. The semiconductor substrate202may include various FEOL devices configured with, for example, epitaxial source/drain structures and gate structures, MEOL interconnecting structures such as, for example, the connecting vias electrically coupled to VDs or VGs, and at least a metal layer Mn−1 formed thereon and including at least the metallization features240aand240bas discussed in detail above. In some embodiments, the structure200further includes connecting vias252disposed in a dielectric layer250that is formed over and electrically coupled to the metallization features240aand240b. The dielectric layer250may include a single-layered structure or a multilayered structure. The dielectric layer250may be referred to as an IMD layer and may include substantially the same composition as the dielectric layer220as discussed above. In some embodiments, when the connecting via252is coupled to a metallization feature, such as the metallization feature240aor240b, in the metal layer Mn−1, the connecting via252is referred to as the (N−1)th via, or Vn−1. For example, the connecting via252that is coupled to the metallization features240a(or240b; not shown), may be referred to as a zeroth via V0. In some embodiments, the connecting via252is similar to the connecting via216in structure and is formed by similar processes. In the depicted embodiments, the connecting vias252are each electrically coupled to one of the metallization features240aand240a′, such that the connecting vias252are spaced from each other along the direction D1and separated by the dielectric layer220; of course, the present disclosure is not limited to this arrangement. For example, additional connecting vias252may be formed to electrically couple with the metallization features240band/or240b′. Still referring toFIGS.13A to13C, the method10forms a dielectric layer260over the structure200. In the present embodiments, the dielectric layer260is similar to the dielectric layer250in composition and structure. In some embodiments, the dielectric layer250and the dielectric layer260are referred to as an IMDn layer, which accommodates the forming of the Nth metal layer Mn and the (N−1)th via Vn−1. For example, the dielectric layer250and the dielectric layer260may be referred to as a first IMD1layer which accommodates the forming of the first metal layer M1 and the zeroth via V0(i.e., the connecting via252). In operation12, the method10forms a trench265in the dielectric layer260. Referring toFIGS.14A to14C, in some embodiments, forming the trench265includes first forming a patterned masking element261over the dielectric layer260, where the patterned masking element261includes at least an opening263configured to define a dimension and a location of the trench265to be formed in the dielectric layer260. In some embodiments, the patterned masking element261is similar to the patterned masking element221in terms of structure and method of processing. Referring toFIGS.15A to15C, portions of the dielectric layer260exposed through the patterned masking element261is removed by a suitable etching process, such as a dry etching process, a wet etching process, an RIE process, or combinations thereof, to form the trench265in the dielectric layer260. The patterned masking element261is then removed after the forming of the trench265by a suitable method, such as plasma ashing and/or resist stripping. In the depicted embodiments, the trench265extends lengthwise along the direction D1, as shown inFIGS.15A and15B, but the disclosure is not limited thereto. For example, the trench265may also be formed to extend lengthwise along the direction D2, i.e., substantially parallel to the metallization features240aand240b, according to specific design requirements. In the depicted embodiments, the connecting vias252and portions of the dielectric layer250are exposed through the trench265, whose sidewalls are defined by the dielectric layer260. Similar to the discussion above with respect to the trench225, an opening of a bottom portion of the trench265(for example, a length of the trench225defined along the direction D2) is less than an opening of a top portion of the trench265, i.e., the trench265is configured with an inverted trapezoidal profile, as shown inFIG.15B. In other words, an included angle266as shown inFIG.15Bis greater than about 90°, i.e., the included angle266is an obtuse angle. In operation13, referring toFIGS.16A to16C, the method10fills the trench265with a conductive material to form a metallization line270in the dielectric layer260. In some embodiments, the conductive material of the metallization line270includes Co, W, Ru, Al, Mo, Ti, Cu, other suitable conductive materials, or combinations thereof, and may be formed by any suitable method, such as CVD, PVD, ALD, electroplating, other suitable methods, or combinations thereof. In some embodiments, the conductive material used to form the metallization line270is the same as the composition of the conductive material230discussed in detail above with respect to the metallization line234. Subsequently, any superfluous conductive material is removed by a planarization process such as a CMP operation, resulting in the metallization line270. In the present embodiments, the resulting metallization line270is configured with an inverted trapezoidal shape according to the same profile of the trench265discussed above. In some embodiments, a barrier layer272is formed prior to the filling of the trench265. In some embodiments, the barrier layer272is a single-layered structure. In some embodiments, the barrier layer272is a multi-layered structure. The barrier layer272may include materials similar to those of the barrier layer232and may be formed by similar process as those discussed with respect to the barrier layer232. In some embodiments, the barrier layer272includes Ti, TiN, Ta, TaN, W, WN, other suitable materials, or combinations thereof. As shown inFIGS.16A and16B, the metallization line270extends lengthwise along the direction D1. In some embodiments, a width D of the metallization line270defined along the direction D2is greater than a width D′ of the connecting via252defined along the same direction, as shown inFIG.16C. In the present embodiments, the metallization line270is configured to be in contact with (i.e., electrically coupled to) the connecting via252. Further, in the present embodiments, the metallization line270is electrically connected to the FEOL device over the semiconductor substrate202through the connecting via252, the metallization feature240a(or the metallization feature240b), and the connecting via216. In the present embodiments, the metallization line270includes a plurality of bottom corners each defined by an included angle that is greater than about 90°, i.e., the included angle is an obtuse angle. In operation14, the method10segments (or separates) the metallization line270to form a metallization feature280aand a metallization feature280b. Referring toFIGS.17A to17C, in the present embodiments, a patterned masking element271is formed over the structure200. The patterned masking element271includes at least an opening273for defining a dimension and a location of a recess281to be formed in the metallization line270. As such, a portion of the metallization line270is exposed through the opening273. In some embodiments, the patterned masking element271is similar to the patterned masking element221in terms of structure and method of processing. Referring toFIGS.18A to18C, the method10performs an etching operation to remove the portion of the metallization line270exposed through the opening273of the patterned masking element271, thereby forming the recess281that separates the metallization line270into metallization features280aand280balong the direction D2. In the present embodiments, a portion of the dielectric layer250is exposed through the recess281. In operation15, the method10fills the recess281with a dielectric feature282. Referring toFIGS.19A to19C, in the present embodiments, the dielectric feature282fills the recess281and provides isolation between the metallization features280aand280b. In the present embodiments, the dielectric feature282includes silicon oxide, TEOS, PSG, BPSG, low-k dielectric material (examples provided above), other suitable materials, or combinations thereof. In some embodiments, the dielectric feature282includes a material similar to that of the dielectric feature244discussed in detail above. In some embodiments, the dielectric feature282and the dielectric layer260include different materials. In some embodiments, the dielectric feature282and the dielectric layer260include the same material. As shown inFIG.19C, top surfaces of the metallization features280aand280b, a top surface of the dielectric layer260, and a top surface of the dielectric feature282are aligned (i.e., substantially co-planar) with each other. As shown inFIGS.19A and19B, along the direction D1, the metallization features280aand280bare separated from each other by the dielectric feature282. Referring toFIG.20, which is the same asFIG.19Cbut depicted with more details, the structure200includes an Nth metal layer Mn formed by the method10. For example, the first metal layer M1 may be formed over the zeroth metal layer M0 by the method10. Of course, additional metal layers may be formed over the first metal layer M1 using the method10as provided herein. In the present embodiments, referring toFIGS.19A to19C and20, each of the metallization features280aand280bincludes a pair of long sides defined by a portion of the dielectric layer260(the portion is alternatively referred to as the dielectric feature260hereafter), one short side defined by the dielectric feature282, and another short side defined by the dielectric layer260. In some embodiments, if one end of the metallization feature280adefines an end of the metallization line270, such end of the metallization feature280ais defined by the dielectric layer260, while the opposite end of the metallization feature280ais defined by the dielectric feature282. Similarly, if one end of the metallization feature280bdefines an end of the metallization line270, such end is defined by the dielectric layer260, while the opposite end of the metallization feature280bis defined by the dielectric feature282. In the present embodiments, the metallization feature280ahas a first bottom corner C1′ adjacent to the dielectric feature282and a second bottom corner CT adjacent to the dielectric layer260(i.e., opposite to the first bottom corner C1′ along the direction D1), where the first bottom corner C1′ is defined by an included angle θ1′ and the second bottom corner C2′ is defined by an included angle θ2′, which corresponds to the angle266as depicted inFIG.15B. In the present embodiments, the included angle θ1′ of the first bottom corner C1′ is less than about 90° (i.e., is an acute angle), while the included angle θ2′ of the second bottom corner C2′ is greater than about 90° (i.e., is an obtuse angle). Further, similar to the discussion above with respect to the barrier layer232, because the barrier layer272is formed before forming the dielectric feature282, the barrier layer272is disposed along (i.e., in direct contact with an entirety of) the sidewall of the metallization feature280adefined by the dielectric layer260but not along the opposite sidewall of the metallization feature280adefined by the dielectric feature282. In the present embodiments, a portion of the barrier layer272is disposed between the metallization feature280aand the dielectric layer250. Still further, in the present embodiments, the metallization feature280ais in direct contact with at least one connecting via252, thereby allowing the FEOL device disposed over the semiconductor substrate202to be electrically connected to the metallization feature280a. In the depicted embodiments, still referring toFIGS.19A to19C and20, the metallization feature280bhas a geometry that is substantially similar to that of the metallization feature280a. For example, the metallization feature280balso includes a pair of long sides defined by a portion of the dielectric layer260(i.e., the dielectric feature260) along the direction D1, a short side defined by the dielectric feature282, and an opposite short side defined by the dielectric layer260. Further, in the present embodiments, the metallization feature240bhas a third bottom corner C3′ adjacent to the dielectric feature282and a fourth bottom corner C4′ adjacent to the dielectric layer260, where the third bottom corner C3′ is defined by an included angle θ3′ and the fourth bottom corner C4′ is defined by an included angle θ4′. In the present embodiments, the included angle θ3′ of the third bottom corner C3′ is less than about 90° (i.e., is an acute angle), while the included angle θ4′ of the fourth bottom corner C4′ is greater than about 90° (i.e., is an obtuse angle). Still further, a portion of the barrier layer272is disposed between the metallization feature280band the dielectric layer250and between the metallization feature280band the dielectric layer260but is not disposed along a sidewall defined by the dielectric feature282. Additionally, in the present embodiments, the metallization feature280bis in direct contact with one connecting via252, allowing the FEOL device disposed over the semiconductor substrate202to be electrically connected to the metallization feature280b. In the present embodiments and for reasons discussed above with respect to the included angle226, the included angle θ2′ of the second bottom corner C2′ of the metallization feature280aand the included angle θ4′ of the fourth bottom corner C4′ of the metallization feature280b, which are adjacent to the dielectric feature260formed prior to the forming of the metallization features280aand280b, are greater than about 90°. In contrast, the included angle θ1′ of the first bottom corner C1′ of the metallization feature280aand the included angle θ3′ of the third bottom corner C3′ of the metallization feature280b, which are adjacent to the dielectric feature282and formed with the forming of the metallization features280aand280b, are less than about 90°. Accordingly, the present embodiments provide that the dielectric feature282is defined by an inverted trapezoid shape. In other words, a width of the dielectric feature282defined along the direction D1decreases towards the semiconductor substrate202. According to the present embodiments, a metallization line is formed in a trench disposed in an IMD (or ILD) layer, the trench having a relatively greater dimension (i.e., greater length) than the metallization features to be formed in the metallization line, where the metallization features are configured as portions of an BEOL interconnect structure. Thus, any gap-filling issue related to the forming of the metallization line at reduced length scales may be mitigated by filling a trench of greater dimension. Subsequently, a metal-cutting operation (including, for example, patterning and etching processes) is performed to segment the metallization line by one or more recesses, resulting in the metallization features. Further, in the present embodiments, the metallization features are electrically isolated from each other by filling the recesses with a dielectric material. In some embodiments, the dielectric material used to fill the recesses differs from the IMD (or ILD) layer in composition, thereby providing greater design freedom during device fabrication. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner. The metallization feature is interposed between the first dielectric feature and the second dielectric feature. In some embodiments, an included angle of the first bottom corner defined by a sidewall of first dielectric feature and a bottom surface of the metallization feature is less than 90°. The via contact is configured to connect the metallization feature to the semiconductor substrate. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a first metallization feature over the semiconductor substrate, a second metallization feature over the semiconductor substrate, a first dielectric feature between the first metallization feature and the second metallization feature, and a second dielectric feature adjacent to the first metallization feature at a side opposite to the first dielectric feature. The first metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner, and the second metallization feature includes a third bottom corner and a fourth bottom corner opposite to the third bottom corner. In some embodiments, the first metallization feature, the second metallization feature, the first dielectric feature, and the second dielectric feature are arranged along the same direction. In some embodiments, the first bottom corner of the first metallization feature is adjacent to the first dielectric feature and defined by an acute angle. The third bottom corner of the second metallization feature is adjacent to the first dielectric feature and defined by an acute angle. In some embodiments, a method for forming a semiconductor structure is provided. The method includes following operations. A semiconductor substrate is received. In some embodiments, a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 60,689 |
11862560 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, terms, such as “first”, “second”, “third”, “fourth”, “fifth” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease cost. FIG.1toFIG.32are schematic cross sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the present disclosure. In embodiments, the manufacturing method is part of a wafer level packaging process. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a package structure. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. InFIG.1toFIG.32, more than one (semiconductor) chips or dies are shown to represent plural (semiconductor) chips or dies of the wafer, and one (semiconductor) package structure is shown to represent plural (semiconductor) package structures obtained following the (semiconductor) manufacturing method, however the disclosure is not limited thereto. In other embodiments, one or more than one (semiconductor) chips or dies are shown to represent plural (semiconductor) chips or dies of the wafer, and one or more than one (semiconductor) package structure are shown to represent plural (semiconductor) package structures obtained following the (semiconductor) manufacturing method, however the disclosure is not limited thereto. Referring toFIG.1, in some embodiments, a carrier112is provided. In some embodiments, the carrier112may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstituted wafer for the manufacturing method of the semiconductor package. In some embodiments, the carrier112is coated with a debond layer114. The material of the debond layer114may be any material suitable for bonding and debonding the carrier112from the above layer(s) or any wafer(s) disposed thereon. In some embodiments, the debond layer114may include a dielectric material layer made of a dielectric material including any suitable polymer-based dielectric material (such as benzocyclobutene (BCB), polybenzoxazole (PBO)). In an alternative embodiment, the debond layer114may include a dielectric material layer made of an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating film. In a further alternative embodiment, the debond layer114may include a dielectric material layer made of an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. In certain embodiments, the debond layer114may be dispensed as a liquid and cured, or may be a laminate film laminated onto the carrier112, or may be the like. The top surface of the debond layer114, which is opposite to a bottom surface contacting the carrier112, may be levelled and may have a high degree of coplanarity. In certain embodiments, the debond layer114is, for example, a LTHC layer with good chemical resistance, and such layer enables room temperature debonding from the carrier112by applying laser irradiation, however the disclosure is not limited thereto. In an alternative embodiment, a buffer layer (not shown) may be coated on the debond layer114, where the debond layer114is sandwiched between the buffer layer and the carrier112, and the top surface of the buffer layer may further provide a high degree of coplanarity. In some embodiments, the buffer layer may be a dielectric material layer. In some embodiments, the buffer layer may be a polymer layer which made of polyimide (PI), PBO, BCB, or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer may be Ajinomoto Buildup Film (ABF), Solder Resist film (SR), or the like. In other words, the buffer layer is optional and may be omitted based on the demand, so that the disclosure is not limited thereto. Continued onFIG.1, in some embodiments, a redistribution circuit structure118is formed over the carrier112. For example, inFIG.1, the redistribution circuit structure118is formed on the debond layer114, and the formation of the redistribution circuit structure118includes sequentially forming one or more dielectric layers118aand one or more metallization layers118bin alternation. In some embodiments, the redistribution circuit structure118includes two dielectric layers118aand one metallization layer118bas shown inFIG.1, where the metallization layer118bis sandwiched between the dielectric layers118a, and portions of a top surface of the metallization layer118bare respectively exposed by the openings of a topmost layer of the dielectric layers118a. However, the disclosure is not limited thereto. The numbers of the dielectric layers118aand the metallization layer118bincluded in the redistribution circuit structure118is not limited thereto, and may be designated and selected based on the demand. For example, the numbers of the dielectric layers118aand the metallization layer118bmay be one or more than one. In certain embodiments, the portions of a top surface of the metallization layer118bare exposed by contact openings OP1formed in the topmost layer of the dielectric layers118a, as shown inFIG.1. For example, the topmost layer of the dielectric layers118aincludes two contact openings OP1as shown inFIG.1. However, the disclosure is not limited thereto. The number and shape of the contact openings OP1formed in the topmost layer of the dielectric layers118ais not limited thereto, and may be designated and selected based on the demand. In certain embodiments, the material of the dielectric layers118amay be PI, PBO, BCB, a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In some embodiments, the material of the dielectric layers118aformed by suitable fabrication techniques such as spin-on coating process, chemical vapor deposition (CVD) process (such as plasma-enhanced chemical vapor deposition (PECVD) process), or the like. The disclosure is not limited thereto. In some embodiments, the material of the metallization layer118bmay be made of conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. In some embodiments, the metallization layer118bmay be patterned copper layers or other suitable patterned metal layers. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc. Referring toFIG.2, in some embodiments, through vias120are formed on the redistribution circuit structure118(e.g. a first side S1of the redistribution circuit structure118). In some embodiments, the through vias120may be through integrated fan-out (InFO) vias. In some embodiments, the through vias122are arranged along but not on a cutting line (not shown) between two package structures PS1. For simplification, only two through vias120are presented inFIG.2for illustrative purposes, however it should be noted that more than two through vias120may be formed; the disclosure is not limited thereto. The number of the through vias120may be designated and selected based on the demand, and adjusted by changing the number and shape of the contact openings OP1. In some embodiments, the through vias120are formed by photolithography, plating, photoresist stripping processes or any other suitable method. For example, the plating process may include an electroplating plating, an electroless plating, or the like. In one embodiment, the through vias120may be formed by forming a mask pattern (not shown) covering the redistribution circuit structure118with openings exposing the top surface of the metallization layer118bexposed by the contact openings OP1formed in the topmost layer of the dielectric layers118a, forming a metallic material filling the openings formed in the mask pattern and the contact openings OP1to form the through vias120by electroplating or deposition, and then removing the mask pattern. In one embodiment, the mask pattern may be removed by acceptable ashing process and/or photoresist stripping process, such as using an oxygen plasma or the like. In one embodiment, prior to the formation of the mask pattern, a seed layer may be formed conformally over the redistribution circuit structure. The disclosure is not limited thereto. In one embodiment, the material of the through vias120may include a metal material such as copper or copper alloys, or the like. However, the disclosure is not limited thereto. In alternative embodiments, the through vias120may be pre-fabricated through vias which may be disposed on the redistribution circuit structure118by picking-and placing. Continued onFIG.2, in some embodiments, at least one semiconductor die130with a connecting film CM disposed thereon is provided over the carrier112. Hereafter, two semiconductor dies130are shown inFIG.2for illustration purpose; however, the disclosure is not limited thereto. In other embodiments, the number of the semiconductor die130may be one or more than one based on the demand and the design layout. For example, as shown inFIG.2, the semiconductor dies130are disposed over the carrier102and on the redistribution circuit structure118through the connecting films CM, respectively. In some embodiments, each of the connecting films CM is located between a respective one of the semiconductor dies130and the redistribution circuit structure118, and each of the connecting films CM physically contacts a backside surface130fof the respective one of the semiconductor dies130and the redistribution circuit structure118(e.g. the topmost layer of the dielectric layers118a). In some embodiments, due to the connecting films CM provided between the semiconductor dies130and the redistribution circuit structure118, the semiconductor dies130and the redistribution circuit structure118are stably adhered to each other. In some embodiments, the connecting films CM may be, for example, a semiconductor die attach film, a layer made of adhesives or epoxy resin, or the like. In some embodiments, the redistribution circuit structure118is referred to as a back-side redistribution layer of the semiconductor dies130for providing routing function. In some embodiments, as shown inFIG.2, the semiconductor dies130each include a semiconductor substrate130shaving an active surface130aand the backside surface130fopposite to the active surface130a, a plurality of pads130bdistributed on the active surface130a, a passivation layer130ccovering the active surface130aexposed by the pads130band a portion of the pads130b, a plurality of conductive vias130dconnected to the portion of the pads130bexposed by the passivation layer130cand a portion of the passivation layer130c, and a protection layer130ecovering the conductive vias130dand the passivation layer130cexposed by the conductive vias130d. The pads130bare partially covered by the passivation layer130c, the conductive vias130dare directly disposed on and electrically connected to the pads130b, and the protection layer130ecovers the passivation layer130cand the conductive vias130d. In an alternative embodiment, the conductive vias130dand the protection layer130emay be omitted; that is, the semiconductor dies130each may include the semiconductor substrate130shaving the active surface130aand the backside surface130fopposite to the active surface130a, the pads130bdistributed on the active surface130a, the passivation layer130ccovering the active surface130aand the pads130b. The disclosure is not limited thereto. The material of the semiconductor substrate130smay include a silicon substrate including active components (e.g., transistors and/or memories such as N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, or the like) and/or passive components (e.g., resistors, capacitors, inductors or the like) formed therein. In some embodiments, such active components and passive components may be formed in a front-end-of-line (FEOL) process. In an alternative embodiment, the semiconductor substrate130smay be a bulk silicon substrate, such as a bulk substrate of monocrystalline silicon, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, where the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant or a combination thereof. The disclosure is not limited thereto. In addition, the semiconductor substrate130smay further include an interconnection structure (not shown) disposed on the active surface130a. In certain embodiments, the interconnection structure may include one or more inter-dielectric layers and one or more patterned conductive layers stacked alternately for providing routing function to the active components and the passive components embedded in the semiconductor substrate130s, where the pads130bmay be referred to as an outermost layer of the patterned conductive layers. In one embodiment, the interconnection structure may be formed in a back-end-of-line (BEOL) process. For example, the inter-dielectric layers may be silicon oxide layers, silicon nitride layers, silicon oxy-nitride layers, or dielectric layers formed by other suitable dielectric materials, and the inter-dielectric layers may be formed by deposition or the like. For example, the patterned conductive layers may be patterned copper layers or other suitable patterned metal layers, and the patterned conductive layers may be formed by electroplating or deposition. However, the disclosure is not limited thereto. In some embodiments, the pads130bmay be aluminum pads or other suitable metal pads. In some embodiments, the conductive vias130dare copper pillars, copper alloy pillar or other suitable metal pillars, for example. In some embodiments, the passivation layer130cand/or the protection layer130emay be a PBO layer, a PI layer or other suitable polymers. In some alternative embodiments, the passivation layer130cand/or the protection layer130emay be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. In certain embodiments, the materials of the passivation layer130cand the protection layer130emay be the same or different, the disclosure is not limited thereto. In some embodiments, each of the semiconductor dies130described herein may be referred to as a chip or an integrated circuit (IC). In some embodiments, the semiconductor dies130may include chip(s) of the same type or different types. For example, the semiconductor dies130include wireless and radio frequency (RF) chips. For example, in an alternative embodiment, the semiconductor dies130digital chips, analog chips, or mixed signal chips, such as application-specific integrated circuit (“ASIC”) chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, voltage regulator chips, or a combination thereof. In an alternative embodiment, the semiconductor dies130, one or all, may be referred to as a chip or a IC of combination-type. For example, at least one of the semiconductor dies130may be a WiFi chip simultaneously including both of a RF chip and a digital chip. The disclosure is not limited thereto. As shown inFIG.2, in some embodiments, the through vias120are located aside of a location of the semiconductor dies130, and are mechanically and electrically connected to the metallization layer118bof the redistribution circuit structure118. InFIG.2, a height of the through vias120is greater than a height of the semiconductor dies130, for example; however, the disclosure is not limited thereto. In an alternative embodiment, the height of the through vias120may be less than or substantially equal to the height of the semiconductor dies130. In one embodiment, the through vias120may be formed prior to the formation of the semiconductor dies130. In an alternative embodiment, the through vias120may be formed after the formation of the semiconductor dies130. The disclosure is not limited to the disclosure. Referring toFIG.3, in some embodiments, the through vias120and the semiconductor dies130are encapsulated in an insulating encapsulation140. In some embodiments, the insulating encapsulation140is formed on the redistribution circuit structure118and over the carrier112. As shown inFIG.3, the insulating encapsulation140at least fills up the gaps between the semiconductor dies130, between the through vias120, and between the semiconductor dies130and the through vias120, for example. In some embodiments, the insulating encapsulation140covers the through vias120and the semiconductor dies130. In other words, for example, the through vias120and the semiconductor dies130are not accessibly revealed by and embedded in the insulating encapsulation140. In some embodiments, the insulating encapsulation140is a molding compound formed by a molding process. In some embodiments, the insulating encapsulation140, for example, may include polymers (such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), dielectric materials, or other suitable materials. In an alternative embodiment, the insulating encapsulation140may include an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulation140may further include inorganic filler or inorganic compound (e.g. silica, clay, and so on) which can be added therein to optimize coefficient of thermal expansion (CTE) of the insulating encapsulation140. The disclosure is not limited thereto. Referring toFIG.4, in some embodiments, the insulating encapsulation140is planarized to form an insulating encapsulation140′ exposing the through vias120and the semiconductor dies130. In certain embodiments, as shown inFIG.4, after the planarization, top surfaces120aof the through vias120and top surfaces of the semiconductor dies130(e.g. top surfaces of the conductive vias130dand the protection layer130eof each of the semiconductor dies130) are exposed by a top surface140aof the insulating encapsulation140′. That is, for example, the top surfaces120aof the through vias120and the top surfaces of the semiconductor dies130become substantially leveled with the top surface140aof the insulating encapsulation140′. In other words, the top surfaces120aof the through vias120, the top surfaces of the semiconductor dies130, and the top surface140aof the insulating encapsulation140′ are substantially coplanar to each other. In some embodiments, as shown inFIG.4, the through vias120and the semiconductor dies130are accessibly revealed by the insulating encapsulation140′. That is, for example, the conductive vias130dof the semiconductor dies130and the through vias120are accessibly revealed by the insulating encapsulation140′. The insulating encapsulation140may be planarized by mechanical grinding or chemical mechanical polishing (CMP), for example. After the planarizing step, a cleaning step may be optionally performed, for example to clean and remove the residue generated from the planarizing step. However, the disclosure is not limited thereto, and the planarizing step may be performed through any other suitable method. In some embodiments, during planarizing the insulating encapsulation140, the conductive vias130dand the protection layer130eof the semiconductor dies130and/or the through vias120may also be planarized. In certain embodiments, the planarizing step may be, for example, performed on the over-molded insulating encapsulation140to level the top surface140aof the insulating encapsulation140′, the top surfaces120aof the through vias120, and the top surfaces of the conductive vias130dand the protection layer130eof each of the semiconductor dies130. In some embodiments, a redistribution circuit structure150is formed on the semiconductor dies130and the insulating encapsulation140′. As shown inFIG.5toFIG.25, the redistribution circuit structure150includes one or more than one seed layers152(e.g., a seed layer152-1, a seed layer152-2, a seed layer152-3, and a seed layer152-4), one or more than one patterned conductive layers154(e.g., a patterned conductive layer154-1, a patterned conductive layer154-2a, a patterned conductive layer154-2b, and a patterned conductive layer154-3), and one or more than one dielectric layers156(e.g., a dielectric layer156-1, a dielectric layer156-2, and a dielectric layer156-3). However, in the disclosure, the numbers of layers of the seed layers152, the patterned conductive layer154, and the dielectric layers156are not limited to what is depicted inFIG.5toFIG.25. The numbers of the layers of the seed layers152, the patterned conductive layer154, and the dielectric layers156may be one or more than one based on the demand and the design layout. Referring toFIG.5, in some embodiments, a seed material layer SL1is disposed on the semiconductor dies130and the insulating encapsulation140′. In some embodiments, the seed material layer SL1is conformally formed on the semiconductor die dies130and the insulating encapsulation140′ in a form of multiple metal or metal alloy layers, where each of the multiple metal or metal alloy layers is a blanket layer of metal or metal alloy materials. In some embodiments, as shown inFIG.5, the seed material layer SL1includes a first seed material layer SL1aand a second seed material layer SL1bstacked on the first seed material layer SL1aalong a stacking direction (e.g. a direction Z) of the redistribution circuit structure118and the semiconductor dies130. As shown inFIG.5, along the direction Z, a thickness T1aof the first seed material layer SL1ais greater than a thickness T1bof the second seed material layer SL1b, for example. In some embodiments, the thickness T1aof the first seed material layer SL1aapproximately ranges from 10 nm to 30 nm. In some embodiments, the thickness T1bof the second seed material layer SL1bapproximately ranges from 40 nm to 70 nm. In some embodiments, a ratio of the thickness T1aof the first seed material layer SL1ato the thickness T1bof the second seed material layer SL1bapproximately ranges from 1/7 to ¾. In other words, a thickness of the seed material layer SL1has a thickness T1, where the thickness T1is a sum of the thickness T1aof the first seed material layer SL1aand the thickness T1bof the second seed material layer SL1b. For example, a material of the first seed material layer SL1amay include copper, copper alloy or the like, and the first seed material layer SL1amay be formed by deposition (such as physical vapor deposition (PVD)) or sputtering. For example, a material of the second seed material layer SL1bmay include titanium, titanium alloy or the like, and the second seed material layer SL1bmay be formed by deposition (such as PVD) or sputtering. As shown inFIG.5, in some embodiments, the seed material layer SL1is in physical and electrical contact with the conductive vias130dof the semiconductor dies130and the top surface140aof the insulating encapsulation140′. Referring toFIG.6, in some embodiments, a patterned photoresist layer PR1is formed on the seed material layer SL1, where the patterned photoresist layer PR1includes at least one opening O1. In some embodiments, as shown inFIG.6, a plurality of openings O1are formed in the patterned photoresist layer PR1. In one embodiment, the patterned photoresist layer PR1may be formed by coating and photolithography processes or the like. The number and shape of the openings O1may, for example, correspond to the number and shape of later-formed conductive structure(s) (such as a conductive segment or a conductive trace, a conductive pillar or conductive via). However, the disclosure is not limited thereto. As shown inFIG.6, portions of the seed material layer SL1are exposed by the openings O1formed in the patterned photoresist layer PR1, respectively. In some embodiments, a material of the patterned photoresist layer PR1, for example, includes a positive resist material or a negative resist material, that is suitable for a patterning process such as a photolithography process with a mask or a mask-less photolithography process (for instance, an electron-beam (e-beam) writing or an ion-beam writing). Referring toFIG.7, in some embodiments, the patterned conductive layer154-1is formed on the seed material layer SL1. In some embodiments, the patterned conductive layer154-1is formed by plating process, deposition, or any other suitable method, where the plating process may include electroplating or electroless plating, or the like. In one embodiment, a metallic material filling the openings O1formed in the patterned photoresist layer PR1is formed by electroplating or deposition to form the patterned conductive layer154-1. In one embodiment, the material of the patterned conductive layer154-1may include a metal material such as copper or copper alloys, or the like. The number of patterns in the patterned conductive layer154-1can be selected based on the demand, and adjusted by changing the number and shape of the openings O1. As shown inFIG.7, the patterned conductive layer154-1is located on the seed material layer SL1and in the openings O1of the patterned photoresist layer PR1, where the patterned conductive layer154-1is in physical and electrical contact with the seed material layer SL1. Referring toFIG.8, in some embodiments, after the patterned conductive layer154-1is formed, the patterned photoresist layer PR1is removed. In one embodiment, the patterned photoresist layer PR1is removed by acceptable ashing process and/or photoresist stripping process, such as using an oxygen plasma or the like. The disclosure is not limited thereto. Referring toFIG.9, in some embodiments, the seed material layer SL1is patterned to form the seed layer152-1, where the first seed material layer SL1ais patterned to form a first sub-layer152-1aand the second seed material layer SL1bis patterned to form a second sub-layer152-1b. In other words, the first sub-layer152-1aand the second sub-layer152-1bare together referred to as the seed layer152-1. In some embodiments, the seed layer152-1and the patterned conductive layer154-1together form one or more conductive patterns/features (such as conductive vias or conductive traces) which are mechanically and electrically isolated from one another, where each of the conductive patterns/features includes the seed layer152-1(including the first seed material layer SL1aand the second seed material layer SL1b) and the patterned conductive layer154-1stacked thereon and electrically connected thereto, for example. In certain embodiments, portions of the seed material layer SL1(including the first seed material layer SL1aand the second seed material layer SL1b) not covered by the patterned conductive layer154-1are removed to form the seed layer152-1. In other words, for example, the seed material layer SL1is etched to form the seed layer152-1by using the patterned conductive layer154-1as an etching mask. With such, in a vertical projection on the carrier112along the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130, a projection area of the patterned conductive layer154-1is substantially the same as the projection area of the seed layer152-1. That is, in direction Z, the patterned conductive layer154-1is completely overlapped with the seed layer152-1(including the first sub-layer152-1aand the second sub-layer152-1b). In some embodiments, sidewalls of one pattern in the seed layer152-1are aligned with sidewalls of a respective one pattern in the patterned conductive layer154-1. For example, the etching process may include a dry etching process or a wet etching process. As shown inFIG.9, the patterned conductive layer154-1is electrically connected to the semiconductor dies130through the seed layer152-1. Referring toFIG.10, in some embodiments, a dielectric material layer DI1is formed on the patterned conductive layer154-1and over the carrier112. The dielectric material layer DI1is formed by, but not limited to, forming a blanket layer of dielectric material over the structure depicted inFIG.9to completely cover the seed layer152-1, the patterned conductive layer154-1, and the semiconductor dies130and the insulating encapsulation140′ exposed by the seed layer152-1and the patterned conductive layer154-1. In some embodiments, the material of the dielectric material layer DI1may be PI, PBO, BCB, a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, a combination thereof or the like. In some embodiments, the dielectric material layer DI1may be formed by suitable fabrication techniques such as spin-on coating, CVD (e.g. PECVD), or the like. The disclosure is not limited thereto. As shown inFIG.10, the patterned conductive layer154-1is not accessibly revealed by the dielectric material layer DI1. Referring toFIG.11, in some embodiments, the dielectric material layer DI1is planarized to form the dielectric layer156-1exposing portions P1of the patterned conductive layer154-1. In certain embodiments, as shown inFIG.11, after the planarization, the portions P1of the patterned conductive layer154-1are protruded out of and exposed by the dielectric layer156-1. In other words, the portions P1of the patterned conductive layer154-1are not in physical contact with the dielectric layer156-1. In some embodiments, top surfaces S154-1of the portions P1of the patterned conductive layer154-1are non-coplanar to a top surface S156-1of the dielectric layer156-1. In some embodiments, a height difference ΔH1between the top surfaces S154-1of the portions P1of the patterned conductive layer154-1and the top surface S156-1of the dielectric layer156-1is approximately ranging from 0.1 μm to 0.7 μm. In other words, the top surfaces S154-1of the portions P1of the patterned conductive layer154-1and the top surface S156-1of the dielectric layer156-1are misaligned to each other along a direction X perpendicular to the stacking direction Z. In some embodiments, as shown inFIG.11, the patterned conductive layer154-1is accessibly revealed by the dielectric layer156-1, where the portions P1of the patterned conductive layer154-1are free of the dielectric layer156-1. In the disclosure, the seed layer152-1(including the first sub-layer152-1aand the second sub-layer152-1b), the patterned conductive layer154-1, and the dielectric layer156-1are together referred to as a first build-up layer of the redistribution circuit structure150. The dielectric material layer DI1may be planarized by mechanical grinding or chemical mechanical polishing (CMP), for example. After the planarizing step, a cleaning step may be optionally performed, for example to clean and remove the residue generated from the planarizing step. However, the disclosure is not limited thereto, and the planarizing step may be performed through any other suitable method. In some embodiments, during planarizing the dielectric material layer DI1, portions of the portions P1of the patterned conductive layer154-1may also be removed. In certain embodiments, as shown inFIG.11, each of the portions P1has the top surface S154-1, a sidewalls S3, and a sidewall S4, where the top surface S154-1is connected to the sidewall S4by the sidewalls S3. In some embodiments, an angle θ1defined by an extending line of the sidewalls S3of each portion P1and an extending line of the top surface S156-1of the dielectric layer156-1is approximately ranging from 100° to 140°. Furthermore, due to the angle θ1(e.g. the presence of the sidewall S3), a contact area between the seed layer152-2and the patterned conductive layer154-1is increased, thereby significantly suppressing a delamination phenonium occurring at the interface of the seed layer152-2and the patterned conductive layer154-1. Referring toFIG.12, in some embodiments, a seed material layer SL2is disposed on the patterned conductive layer154-1and the dielectric layer156-1. In some embodiments, the seed material layer SL2is conformally formed on the patterned conductive layer154-1and the dielectric layer156-1in a form of multiple metal or metal alloy layers. In some embodiments, as shown inFIG.12, the seed material layer SL2includes a first seed material layer SL2aand a second seed material layer SL2bstacked on the first seed material layer SL2aalong the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130. As shown inFIG.12, along the direction Z, a thickness T2aof the first seed material layer SL2ais greater than a thickness T2bof the second seed material layer SL2b, for example. In some embodiments, the thickness T2aof the first seed material layer SL2aapproximately ranges from 10 nm to 30 nm. In some embodiments, the thickness T2bof the second seed material layer SL2bapproximately ranges from 40 nm to 70 nm. In some embodiments, a ratio of the thickness T2aof the first seed material layer SL2ato the thickness T2bof the second seed material layer SL2bapproximately ranges from 1/7 to ¾. In other words, a thickness of the seed material layer SL2has a thickness T2, where the thickness T2is a sum of the thickness T2aof the first seed material layer SL2aand the thickness T2bof the second seed material layer SL2b. For example, the material and formation of the first seed material layer SL2amay the same as the material and formation of the first seed material layer SL1a, the material and formation of the second seed material layer SL2bmay the same as the material and formation of the second seed material layer SL1b, and thus are not repeated herein for simplicity. As shown inFIG.12, in some embodiments, the seed material layer SL2is in physical and electrical contact with the portions P1of the patterned conductive layer154-1. Referring toFIG.13, in some embodiments, a patterned photoresist layer PR2is formed on the seed material layer SL2, where the patterned photoresist layer PR2includes at least one opening O2. For example, as shown inFIG.13, a plurality of openings O2are formed in the patterned photoresist layer PR2to expose portions of the seed material layer SL2. The material and formation of the patterned photoresist layer PR2may be substantially the same or similar to the material and formation of the patterned photoresist layer PR1, and thus are not repeated herein for simplicity. The number and shape of the openings O2may, for example, correspond to the number and shape of later-formed conductive structure(s) (such as a conductive segment or a conductive trace, a conductive pillar or conductive via), the disclosure is not limited thereto. Referring toFIG.14, in some embodiments, the patterned conductive layer154-2ais formed on the seed material layer SL2. The material and formation of the patterned conductive layer154-2ais substantially the same or similar to the material and formation of the patterned conductive layer154-1, and thus are not repeated herein for simplicity. The number of patterns in the patterned conductive layer154-2acan be selected based on the demand, and adjusted by changing the number and shape of the openings O2. As shown inFIG.14, the patterned conductive layer154-2ais located on the seed material layer SL2and in the openings O2of the patterned photoresist layer PR2, where the patterned conductive layer154-2ais in physical and electrical contact with the seed material layer SL2. Referring toFIG.15, in some embodiments, after the patterned conductive layer154-2ais formed, the patterned photoresist layer PR2is removed. In one embodiment, the patterned photoresist layer PR2is removed by acceptable ashing process and/or photoresist stripping process, such as using an oxygen plasma or the like. The disclosure is not limited thereto. Referring toFIG.16, in some embodiments, the seed material layer SL2is patterned to form the seed layer152-2, where the first seed material layer SL2ais patterned to form a first sub-layer152-2aand the second seed material layer SL2bis patterned to form a second sub-layer152-2b. In other words, the first sub-layer152-2aand the second sub-layer152-2bare together referred to as the seed layer152-2. The formation of the seed layer152-2(including the first sub-layer152-2aand the second sub-layer152-2b) is similar to the formation of the seed layer152-1described inFIG.9, and thus is not repeated herein. In some embodiments, in a vertical projection on the carrier112along the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130, a projection area of the patterned conductive layer154-2ais substantially the same as the projection area of the seed layer152-2. That is, in direction Z, the patterned conductive layer154-2ais completely overlapped with the seed layer152-2(including the first sub-layer152-2aand the second sub-layer152-2b). In some embodiments, sidewalls of one pattern in the seed layer152-2are aligned with sidewalls of a respective one pattern in the patterned conductive layer154-2a. As shown inFIG.16, the patterned conductive layer154-2ais electrically connected to the patterned conductive layer154-1through the seed layer152-2. Referring toFIG.17, in some embodiments, a seed material layer SL3is disposed on the patterned conductive layer154-2a, the seed layer152-2, and the dielectric layer156-1exposed by the patterned conductive layer154-2aand the seed layer152-2. In some embodiments, the seed material layer SL3is conformally formed on the patterned conductive layer154-2a, the seed layer152-2, and the dielectric layer156-1exposed by the patterned conductive layer154-2aand the seed layer152-2in a form of multiple metal or metal alloy layers, where each of the multiple metal or metal alloy layers is a blanket layer of metal or metal alloy materials. In some embodiments, as shown inFIG.17, the seed material layer SL3includes a first seed material layer SL3aand a second seed material layer SL3bstacked on the first seed material layer SL3aalong a stacking direction (e.g. a direction Z) of the redistribution circuit structure118and the semiconductor dies130. As shown inFIG.17, along the direction Z, a thickness T3aof the first seed material layer SL3ais greater than a thickness T3bof the second seed material layer SL3b, for example. In some embodiments, the thickness T3aof the first seed material layer SL3aapproximately ranges from 60 nm to 80 nm. In some embodiments, the thickness T3bof the second seed material layer SL3bapproximately ranges from 100 nm to 140 nm. In some embodiments, a ratio of the thickness T3aof the first seed material layer SL3ato the thickness T3bof the second seed material layer SL3bapproximately ranges from 3/7 to ⅘. In other words, a thickness of the seed material layer SL3has a thickness T3, where the thickness T3is a sum of the thickness T3aof the first seed material layer SL3aand the thickness T3bof the second seed material layer SL3b. For example, the material and formation of the first seed material layer SL3aare substantially the same or similar to the materials and formations of the first seed material layer SL1a, SL2a, and the material and formation of the second seed material layer SL3bare substantially the same or similar to the materials and formations of the second seed material layer SL1b, SL2b, and thus are not repeated herein. As shown inFIG.17, in some embodiments, the seed material layer SL3is in physical and electrical contact with the patterned conductive layer154-2aand the seed layer152-2. Referring toFIG.18, in some embodiments, a patterned photoresist layer PR3is formed on the seed material layer SL3, where the patterned photoresist layer PR3includes at least one opening O3. For example, as shown inFIG.18, a plurality of openings O3are formed in the patterned photoresist layer PR3to expose portions of the seed material layer SL3. The material and formation of the patterned photoresist layer PR3may be substantially the same or similar to the materials and formations of the patterned photoresist layers PR1and/or PR2, and thus are not repeated herein for simplicity. The number and shape of the openings O3may, for example, correspond to the number and shape of later-formed conductive structure(s) (such as a conductive segment or a conductive trace, a conductive pillar or conductive via), the disclosure is not limited thereto. Referring toFIG.19, in some embodiments, the patterned conductive layer154-2bis formed on the seed material layer SL3. The material and formation of the patterned conductive layer154-2bis substantially the same or similar to the materials and formations of the patterned conductive layers154-1and/or154-2a, and thus are not repeated herein. The number and shape of patterns in the patterned conductive layer154-2bcan be selected based on the demand, and adjusted by changing the number and shape of the openings O3. As shown inFIG.19, the patterned conductive layer154-2bis located on the seed material layer SL3and in the openings O3of the patterned photoresist layer PR3, where the patterned conductive layer154-2bis in physical and electrical contact with the seed material layer SL3. Referring toFIG.20, in some embodiments, after the patterned conductive layer154-2bis formed, the patterned photoresist layer PR3is removed. In one embodiment, the patterned photoresist layer PR3is removed by acceptable ashing process and/or photoresist stripping process, such as using an oxygen plasma or the like. The disclosure is not limited thereto. Referring toFIG.21, in some embodiments, the seed material layer SL3is patterned to form the seed layer152-3, where the first seed material layer SL3ais patterned to form a first sub-layer152-3aand the second seed material layer SL3bis patterned to form a second sub-layer152-3b. In other words, the first sub-layer152-3aand the second sub-layer152-3bare together referred to as the seed layer152-3. The formation of the seed layer152-3(including the first sub-layer152-3aand the second sub-layer152-3b) is similar to the formation of the seed layer152-1described inFIG.9, and thus is not repeated herein for simplicity. In some embodiments, in a vertical projection on the carrier112along the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130, a projection area of the patterned conductive layer154-2bis substantially the same as the projection area of the seed layer152-3. That is, in direction Z, the patterned conductive layer154-2bis completely overlapped with the seed layer152-3(including the first sub-layer152-3aand the second sub-layer152-3b). In some embodiments, sidewalls of one pattern in the seed layer152-3are aligned with sidewalls of a respective one pattern in the patterned conductive layer154-2b. As shown inFIG.21, the patterned conductive layer154-2bis electrically connected to the patterned conductive layer154-2athrough the seed layer152-3. In some embodiments, the seed layer152-2, the patterned conductive layer154-2a, the seed layer152-3, and the patterned conductive layer154-2btogether form one or more conductive patterns/features (such as conductive vias or conductive traces) which are mechanically and electrically isolated from one another, for example. Referring toFIG.22, in some embodiments, a dielectric material layer DI2is formed on the patterned conductive layers154-2a,154-2band over the carrier112. The dielectric material layer DI2is formed by, but not limited to, forming a blanket layer of dielectric material over the structure depicted inFIG.21to completely cover the seed layer152-2, the patterned conductive layer154-2a, the seed layer152-3, the patterned conductive layer154-2b, and the dielectric layer156-1exposed by the seed layer152-2, the patterned conductive layer154-2a, the seed layer152-3, and the patterned conductive layer154-2b. In some embodiments, the material and formation of the dielectric material layer DI2may be substantially the same or similar to the material and formation of the dielectric material layer DI1, and thus is not repeated herein. As shown inFIG.22, the seed layer152-2, the patterned conductive layer154-2a, the seed layer152-3, the patterned conductive layer154-2b, and the dielectric layer156-1is not accessibly revealed by the dielectric material layer DI2. Referring toFIG.23, in some embodiments, the dielectric material layer DI2is planarized to form the dielectric layer156-2exposing portions P2of the patterned conductive layer154-2b. The planarizing process is similar to the planarizing process described inFIG.11, and thus is not repeated herein for simplicity. In certain embodiments, as shown inFIG.23, after the planarization, the portions P2of the patterned conductive layer154-2bare protruded out of and exposed by the dielectric layer156-2. In other words, the portions P2of the patterned conductive layer154-2bare not in physical contact with the dielectric layer156-2. In some embodiments, top surfaces S154-2bof the portions P2of the patterned conductive layer154-2bare non-coplanar to a top surface S156-2of the dielectric layer156-2. In some embodiments, a height difference ΔH2between the top surfaces S154-2bof the portions P2of the patterned conductive layer154-2and the top surface S156-2of the dielectric layer156-2is approximately ranging from 0.1 μm to 0.7 μm. In other words, the top surfaces S154-2bof the portions P2of the patterned conductive layer154-2and the top surface S156-2of the dielectric layer156-2are misaligned to each other along a direction X perpendicular to the stacking direction Z. In some embodiments, as shown inFIG.23, the patterned conductive layer154-2bis accessibly revealed by the dielectric layer156-2, where the portions P2of the patterned conductive layer154-2bare free of the dielectric layer156-2. In the disclosure, the seed layer152-2(including the first sub-layer152-2aand the second sub-layer152-2b), the patterned conductive layer154-2a, the seed layer152-3(including the first sub-layer152-3aand the second sub-layer152-3b), the patterned conductive layer154-2b, and the dielectric layer156-2are together referred to as a second build-up layer of the redistribution circuit structure150. In some embodiments, as shown inFIG.23, an interface IF1of the dielectric layer156-1and the dielectric layer156-2is located at a sidewall of the patterned conductive layer154-1. In some embodiments, during planarizing the dielectric material layer DI2, portions of the portions P2of the patterned conductive layer154-2bmay also be removed. In certain embodiments, as shown inFIG.23, each of the portions P2has the top surface S154-2b, a sidewalls S5, and a sidewall S6, where the top surface S154-2bis connected to the sidewall S6by the sidewalls S5. In some embodiments, an angle θ2defined by an extending line of the sidewalls S5of each portion P2and an extending line of the top surface S156-2of the dielectric layer156-2is approximately ranging from 100° to 140°. Furthermore, due to the angle θ2(e.g. the presence of the sidewall S5), a contact area between the seed layer152-4and the patterned conductive layer154-2bis increased, thereby significantly suppressing a delamination phenonium occurring at the interface of the seed layer152-4and the patterned conductive layer154-2b. Referring toFIG.24, in some embodiments, a seed layer152-4and a patterned conductive layer154-3are sequentially formed on the dielectric layer156-2and the patterned conductive layer154-2bexposed by the dielectric layer156-2. In some embodiments, the seed layer152-4and the patterned conductive layer154-3together form one or more conductive patterns/features (such as conductive vias or conductive traces) which are mechanically and electrically isolated from one another, where each of the conductive patterns/features includes the seed layer152-4and the patterned conductive layer154-3stacked thereon and electrically connected thereto, for example. The material and formation of the seed layer152-4is substantially the same or similar to the materials and formations of the seed layers152-1,152-2, and/or152-3, and the material and formation of the patterned conductive layer154-3is substantially the same or similar to the materials and formations of the patterned conductive layers154-1,154-2a, and/or154-2b, and thus are not repeated therein. As shown inFIG.24, for example, the seed layer152-4is in physical and electrical contact with the patterned conductive layer154-2b, where the seed layer152-4includes a first sub-layer152-4aand the second sub-layer152-4b, and the first sub-layer152-4ais sandwiched between the patterned conductive layer154-2band the second sub-layer152-4b. In some embodiments, in a vertical projection on the carrier112along the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130, a projection area of the patterned conductive layer154-3is substantially the same as the projection area of the seed layer152-4. That is, in direction Z, the patterned conductive layer154-3is completely overlapped with the seed layer152-4(including the first sub-layer152-4aand the second sub-layer152-4b). In some embodiments, sidewalls of one pattern in the seed layer152-4are aligned with sidewalls of a respective one pattern in the patterned conductive layer154-3. As shown inFIG.24, the patterned conductive layer154-3is electrically connected to the patterned conductive layer154-2bthrough the seed layer152-4. For example, the material of the first sub-layer152-4ais substantially the same or similar to the materials of the first sub-layers152-1a,152-2a, and/or152-3a, and the material of the second sub-layer152-4bis substantially the same or similar to the materials of the second sub-layers152-1b,152-2b, and/or152-3. In some embodiments, the thickness T4aof the first sub-layer152-4aapproximately ranges from 10 nm to 30 nm. In some embodiments, the thickness T4bof the second sub-layer152-4bapproximately ranges from 40 nm to 70 nm. In some embodiments, a ratio of the thickness T4aof the first sub-layer152-4ato the thickness T4bof the second sub-layer152-4bapproximately ranges from 1/7 to ¾. In other words, a thickness of the seed layer152-4has a thickness T4, where the thickness T4is a sum of the thickness T4aof the first sub-layer152-4aand the thickness T4bof the second sub-layer152-4b. Referring toFIG.25, in some embodiments, the dielectric layer156-3is formed on the patterned conductive layer154-3and over the carrier112. The dielectric layer156-3is formed with a plurality of recesses R1exposing portions of the patterned conductive layer154-3, for example. In some embodiments, the material of the dielectric layer156-3may be PI, PBO, BCB, a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, a combination thereof or the like. In some embodiments, the dielectric layer156-3may be formed by suitable fabrication techniques such as spin-on coating, deposition along with a patterning process (such as photolithograph and etching steps), or the like. The disclosure is not limited thereto. In the disclosure, the seed layer152-4(including the first sub-layer152-4aand the second sub-layer152-4b), the patterned conductive layer154-3, and the dielectric layer156-3are together referred to as a third build-up layer of the redistribution circuit structure150. In some embodiments, as shown inFIG.25, an interface IF2of the dielectric layer156-2and the dielectric layer156-3is located at a sidewall of the patterned conductive layer154-2b. Upon this, the redistribution circuit structure150of the package structure PS1is manufactured. In addition, the critical dimensions of the patterned conductive layer154-1,152-2a,152-2b, and152-3can be controlled by respectively adjusting the thickness T1of the seed layer152-1, the thickness T2of the seed layer152-2, the thickness T3of the seed layer152-3, and the thickness T4of the seed layer152-4. That is, in the disclosure, the critical dimension of the metal features in the redistribution circuit structure150′ can be controlled by adjusting the seed layer underlying thereto while maintaining the reliability of the circuitry of the redistribution circuit structure150. For example, as shown inFIG.39, due to the thickness T3of the seed layer152-3is greater than the thickness T1of the seed layer152-1, the thickness T2of the seed layer152-2, and the thickness T4of the seed layer152-4, the critical dimension of the patterned conductive layer154-2bis smaller the critical dimensions of the patterned conductive layer154-1,152-2a, and152-3, where the critical dimension of the patterned conductive layer154-2bmay be reduced to less than 2 μm by controlling the thickness T3of the seed layer152-3. Referring toFIG.5toFIG.25together, in some embodiments, the redistribution circuit structure150is formed on the semiconductor dies130and the insulating encapsulation140′, where the redistribution circuit structure150is electrically connected to the semiconductor dies130. For example, the redistribution circuit structure150is formed on the top surfaces of the semiconductor dies130and the top surface140aof the insulating encapsulation140′. In some embodiments, the redistribution circuit structure150is electrically connected to the semiconductor dies130through the conductive vias130dand the pads130b. In some embodiments, the redistribution circuit structure150is referred to as a front-side redistribution layer of the semiconductor dies130for providing routing function. In some embodiments, the semiconductor dies130are located between the redistribution circuit structure150and the connecting films CM, and the insulating encapsulation140′ are located between the redistribution circuit structure150and the debond layer114. As shown inFIG.25, the semiconductor dies130are electrically communicated to each other through the redistribution circuit structure150, for example. In some embodiments, the redistribution circuit structure118is electrically coupled to the semiconductor dies130through the through vias120and the redistribution circuit structure150. In the disclosure, for illustration purpose, one of each of the first, second, and third build-up layers are included in the redistribution circuit structure150ofFIG.25; however, the disclosure is not limited thereto. The numbers of the first build-up layer, the second build-up layer, and the third build-up layer included in the redistribution circuit structure150is not limited in the disclosure, and may be determined based on the demand and the design layout. For example, the number of each of the first build-up layer, the second build-up layer, and the third build-up layer included in the redistribution circuit structure150may be zero, one, or more than one. Referring toFIG.26, in some embodiments, a seed material layer SL5is disposed on the dielectric layer156-3. In some embodiments, the seed material layer SL5is conformally formed on the dielectric layer156-3and further extends into the recesses R1to physically contact the exposed portions of the patterned conductive layer154-3in a form of multiple metal or metal alloy layers. In some embodiments, as shown inFIG.26, the seed material layer SL5includes a first seed material layer SL5aand a second seed material layer SL5bstacked on the first seed material layer SL5aalong the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130. In one embodiment, along the direction Z, a thickness of the first seed material layer SL5ais substantially equal to a thickness of the second seed material layer SL5b, for example; however, the disclosure is not limited thereto. In an alternative embodiment, the thickness of the first seed material layer SL5ais greater than the thickness of the second seed material layer SL5b. In a further alternative embodiment, the thickness of the first seed material layer SL5ais less than the thickness of the second seed material layer SL5b. In one embodiment, the material and formation of the first seed material layer SL5amay the same as the material and formation of the first seed material layers SL1a, SL2a, SL3aand/or SL4a, the material and formation of the second seed material layer SL5bmay the same as the material and formation of the second seed material layers SL1b, SL2b, SL3band/or SL4b, and thus are not repeated herein for simplicity. As shown inFIG.26, in some embodiments, the seed material layer SL5is in physical and electrical contact with the patterned conductive layer154-3exposed by the dielectric layer156-3. Referring toFIG.27, in some embodiments, a patterned photoresist layer PR4is formed on the seed material layer SL5, where the patterned photoresist layer PR4includes at least one opening O4. For example, as shown inFIG.27, a plurality of openings O4are formed in the patterned photoresist layer PR4to expose portions of the seed material layer SL5. The material and formation of the patterned photoresist layer PR4may be substantially the same or similar to the material and formation of the patterned photoresist layers PR1, PR2, and/or PR3, and thus are not repeated herein for simplicity. The number and shape of the openings O4may, for example, correspond to the number and shape of later-formed conductive structure(s) (such as a conductive segment or a conductive trace, a conductive pillar or conductive via), the disclosure is not limited thereto. Referring toFIG.28, in some embodiments, a plurality of seed-layer patterns160and a plurality of conductive terminals170are formed over the redistribution circuit structure150, where the seed-layer patterns160are sandwiched between the redistribution circuit structure150and the conductive terminals170. In some embodiments, the seed-layer patterns160each are located between a respective one of the conductive terminals170and the redistribution circuit structure150. Due to the seed-layer patterns160, the adhesive strength between the conductive terminals170and the redistribution circuit structure150is enhanced. In some embodiments, the seed-layer patterns160are directly located on dielectric layer156-3and further extend into the recesses R1formed in the dielectric layer156-3to physically and electrically contact the portions of the patterned conductive layer154-3exposed by the recesses R1formed in the dielectric layer156-3. As shown inFIG.28, in some embodiments, the seed-layer patterns160are electrically connected to the redistribution circuit structure150, and the conductive terminals170are electrically connected to the redistribution circuit structure150through the seed-layer patterns160. In some embodiments, some of the conductive terminals170are electrically connected to at least one of the semiconductor dies130through the redistribution circuit structure150and the seed-layer patterns160. In some embodiments, some of the conductive terminals170are electrically connected to the redistribution circuit structure118through the through vias120, the redistribution circuit structure150, and the seed-layer patterns160. In some embodiments, the seed-layer patterns160and the conductive terminals170may be formed by the following steps. For example, a plurality of conductive elements170-1are formed on the seed material layer SL5and in the openings O4formed in the patterned photoresist layer PR4by a plating process; the conductive elements170-2is disposed on the conductive elements170-1to form the conductive terminals170by dispensing; the patterned photoresist layer PR4is removed by an acceptable ashing process and/or a photoresist stripping process; and, the seed material layer SL5is patterned by using the conductive terminals170-1as a mask to form the seed-layer patterns160by etching process(es) (such as an etching process for patterning the first seed material layer SL5ato form a first sub-layer160-1, and an etching process for patterning the second seed material layer SL5bto form a second sub-layer160-2). The material of the conductive elements170-1may include copper, copper alloy, or the like; and the material of the conductive elements170-2may include solder or the like. However, the disclosure is not limited thereto, the above method and processes may be substituted by any other suitable method and processes based on the demand. In some embodiments, the conductive elements170-2may be omitted form the conductive terminals170. As shown inFIG.28, for example, in a vertical projection on the carrier112along the stacking direction (e.g. the direction Z) of the redistribution circuit structure118and the semiconductor dies130, a projection area of the conductive terminals170is substantially the same as the projection area of the seed-layer patterns160underlying thereto, respectively. That is, in direction Z, the conductive terminals170each are completely overlapped with the seed-layer patterns160(including the first sub-layer160-1and the second sub-layer160-2) underlying thereto. In some embodiments, sidewalls of one pattern in the seed-layer patterns160are aligned with sidewalls of a respective one pattern in the conductive terminals170. Referring toFIG.29, in some embodiments, the whole structure depicted inFIG.28along with the carrier112is flipped (turned upside down), where the conductive terminals170are placed to a holding device HD, and the carrier112is then debonded from the redistribution circuit structure118. As shown inFIG.29, a surface S2of the redistribution circuit structure118is exposed. In some embodiments, the holding device HD may be an adhesive tape, a carrier film or a suction pad. The disclosure is not limited thereto. In some embodiments, the redistribution circuit structure118is easily separated from the carrier112due to the debond layer114. In some embodiments, the carrier112is detached from the surface S2of the redistribution circuit structure118through a debonding process, and the carrier112and the debond layer114are removed. In certain embodiments, the redistribution circuit structure118is exposed, as show inFIG.29. In one embodiment, the debonding process is a laser debonding process. During the debonding step, the holding device HD is used to secure the package structure PS1before debonding the carrier112and the debond layer114. Referring toFIG.30, in some embodiments, an outermost layer of the dielectric layers118aof the redistribution circuit structure118(e.g. the bottommost layer of the dielectric layer118adepicted inFIG.2) is further patterned, such that a plurality of contact openings OP2are formed in the outermost layer of the dielectric layers118aof the redistribution circuit structure118to expose portions of the metallization layer118b. The number and shape of the contact openings OP2may, for example, correspond to the number and shape of later-formed conductive structure(s) (such as conductive terminals). However, the disclosure is not limited thereto. In some embodiments, the contact openings OP2in the outermost layer of the dielectric layers118aof the redistribution circuit structure118are formed by laser drilling process or other suitable processes. In some embodiments, after the formation of the contact openings OP2, a plurality of under-ball metallurgy (UBM) patterns180are disposed on the portions of the metallization layer118bexposed by the contact openings OP2for electrically connecting later-formed or later-disposed conductive elements (e.g. conductive balls) to the exposed portions of the metallization layer118b. In some embodiments, the UBM patterns180may be a single layer or a composite layer having a plurality of sub-layers formed of different materials. The UBM patterns180may include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed by an electroplating process, for example. As shown inFIG.30, the UBM patterns180are in physical and electrical contact with the metallization layer118b. The number of the UBM patterns180may correspond to the number of the contact openings OP2. In an alternative embodiment, the UBM patterns180may be optionally omitted based on demand and/or design layout. In such embodiment, parts of the metallization layer118bunderlying the later-formed or later-disposed conductive elements may function as under-ball metallurgy (UBM) layers. In some embodiments, prior to forming or disposing the later-formed or later-disposed conductive elements, a solder paste (not shown) or flux is applied, so that the later-formed or later-disposed conductive elements are better fixed to the metallization layer118b. Referring toFIG.31, in some embodiments, a plurality of conductive terminals190are formed on the redistribution circuit structure118. In some embodiments, the redistribution circuit structure118is located between the connecting films CM and the conductive terminals190, between the semiconductor dies130and the conductive terminals190, and between the insulating encapsulation140′ and the conductive terminals190. As shown inFIG.31, the conductive terminals190are physically and electrically connected to the UBM patterns180. In some embodiments, the conductive terminals190are electrically connected to the redistribution circuit structure118through the UBM patterns180. In some embodiments, some of the conductive terminals190are electrically coupled to the redistribution circuit structure150through the UBM patterns180, the redistribution circuit structure118, and the through vias120. In some embodiments, some of the conductive terminals190are electrically coupled to the semiconductor dies130through the UBM patterns180, the redistribution circuit structure118, the through vias120, and the redistribution circuit structure150. In some embodiments, some of the conductive terminals190are electrically coupled to some of the conductive terminals170through the UBM patterns180, the redistribution circuit structure118, the through vias120, and the redistribution circuit structure150. In some embodiments, the conductive terminals190may be disposed on the UBM patterns180by ball placement process or reflow process. In some embodiments, the conductive terminals190may be solder balls or ball grid array (BGA) balls. The disclosure is not limited thereto. The number of the conductive terminals190may correspond to the number of the UBM patterns180. Referring toFIG.32, in some embodiments, the conductive terminals170are released from the holding device HD to form the package structure PS1. In some embodiments, prior to releasing the conductive terminals170from the holding device HD, a dicing (singulation) process is performed to cut a plurality of the package structure PS1interconnected therebetween into individual and separated package structures PS1. In one embodiment, the dicing (singulation) process is a wafer dicing process including mechanical blade sawing or laser cutting. The disclosure is not limited thereto. Up to here, the manufacture of the package structure PS1is completed. However, the disclosure is not limited thereto. In certain embodiments, the conductive terminals170may be substituted by conductive terminals200which may include solder balls or BGA balls, see a package structure PS2depicted inFIG.33. In an alternative embodiment, the redistribution circuit structure118, the through vias120, the UBM patterns180, and the conductive terminals190may be optionally omitted, see a package structure PS3depicted inFIG.34. In a further alternative embodiment, the conductive terminals170may be substituted by conductive terminals200which may include solder balls or BGA balls while the redistribution circuit structure118, the through vias120, the UBM patterns180, and the conductive terminals190may be optionally omitted, see a package structure PS4depicted inFIG.35. In further alternative embodiments, in addition to the conductive terminals170,190, and/or200inFIG.32toFIG.35, an additional semiconductor element(s) (not shown) may be disposed on the seed layer patterns160and/or the UBM patterns180for electrically coupling at least one of the semiconductor dies130. In some embodiments, the additional semiconductor element(s) may include a passive component or active component. The number of the additional semiconductor element(s) is not limited in the disclosure, and may be designated based on the demand and design layout. FIG.36toFIG.40are schematic cross sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the present disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, etc.) of the same elements would not be repeated herein. Referring toFIG.32andFIG.40, a package structure PS5depicted inFIG.40is similar to the package structure PS1depicted inFIG.32; the difference is that, in the package structure PS7, the redistribution circuit structure150is substituted by a redistribution circuit structure150′. As shown inFIG.36toFIG.39, the redistribution circuit structure150′ includes one or more than one seed layers152(e.g., a seed layer152-1, a seed layer152-2, a seed layer152-3, and a seed layer152-4), one or more than one patterned conductive layers154(e.g., a patterned conductive layer154-1, a patterned conductive layer154-2a, a patterned conductive layer154-2b, and a patterned conductive layer154-3), one or more than one dielectric layers156(e.g., a dielectric layer156-1, a dielectric layer156-2, and a dielectric layer156-3), and one or more than one inter-layer film (e.g., an inter-layer film158-1and an inter-layer film158-2). However, in the disclosure, the numbers of layers of the seed layers152, the patterned conductive layer154, and the dielectric layers156, and the inter-layer films158are not limited to what is depicted inFIG.36toFIG.39, and may be one or more than one based on the demand and the design layout. Referring toFIG.36, in some embodiments, the inter-layer film158-1is formed on the dielectric layer156-1and laterally wrapped around the patterned conductive layer154-2a, following the process as described inFIG.16. In certain embodiments, as shown inFIG.36, portions P3of the patterned conductive layer154-2aare protruded out of and exposed by the inter-layer film158-1. In other words, the portions P3of the patterned conductive layer154-2aare not in physical contact with the inter-layer film158-1. In some embodiments, top surfaces S154-2aof the portions P3of the patterned conductive layer154-2aare non-coplanar to a top surface S158-1of the inter-layer film158-1. In some embodiments, a height difference ΔH3between the top surfaces S154-2aof the portions P3of the patterned conductive layer154-2aand the top surface S158-1of the inter-layer film158-1is approximately ranging from 0.1 μm to 0.7 μm. In other words, the top surfaces S154-2aof the portions P3of the patterned conductive layer154-2aand the top surface S158-1of the inter-layer film158-1are misaligned to each other along a direction X perpendicular to the stacking direction Z. In some embodiments, as shown inFIG.36, the patterned conductive layer154-2ais accessibly revealed by the dielectric layer158-1, where the portions P3of the patterned conductive layer154-2aare free of the dielectric layer158-1. In some embodiments, as shown inFIG.36, an interface IF3of the dielectric layer156-1and the inter-layer film158-1is located at a sidewall of the patterned conductive layer154-1. The material and formation of the inter-layer film158-1is substantially the same or similar to the material and formation of the dielectric layer156-1described inFIG.10toFIG.11and/or the material and formation of the dielectric layer156-2described inFIG.22toFIG.23, and thus are not repeated herein for simplicity. In certain embodiments, as shown inFIG.36, each of the portions P3has the top surface S154-2a, a sidewalls S7, and a sidewall S8, where the top surface S154-2ais connected to the sidewall S8by the sidewalls S7. In some embodiments, an angle θ3defined by an extending line of the sidewalls S7of each portion P3and an extending line of the top surface S158-1of the inter-layer film158-1is approximately ranging from 100° to 140°. Referring toFIG.37, in some embodiments, the seed layer152-3, the patterned conductive layer154-2b, and the dielectric layer156-2are formed on the inter-layer film158-1. The materials and formations of the seed layer152-3, the patterned conductive layer154-2b, and the dielectric layer156-2are described inFIG.17toFIG.23, and thus are not repeated herein. In the disclosure, the seed layer152-2(including the first sub-layer152-2aand the second sub-layer152-2b), the patterned conductive layer154-2a, the inter-layer film158-1, the seed layer152-3(including the first sub-layer152-3aand the second sub-layer152-3b), the patterned conductive layer154-2b, and the dielectric layer156-3are together referred to as a second build-up layer of the redistribution circuit structure150′. In some embodiments, as shown inFIG.37, an interface IF4of the inter-layer film158-1and the dielectric layer156-2is located at a sidewall of the patterned conductive layer154-2a. Referring toFIG.38, in some embodiments, the seed layer152-4and the patterned conductive layer154-3are formed on the dielectric layer156-2. In some embodiments, after the formation of the patterned conductive layer154-3, the inter-layer film158-2is formed on the dielectric layer156-2and laterally wrapped around the patterned conductive layer154-3. The materials and formations of the seed layer152-4and the patterned conductive layer154-3are described inFIG.24, the material and formation of the inter-layer film158-2is substantially the same or similar to the material and formation of the inter-layer film158-1, and thus are not repeated herein. In certain embodiments, as shown inFIG.38, portions P4of the patterned conductive layer154-3are protruded out of and exposed by the inter-layer film158-2. In other words, the portions P4of the patterned conductive layer154-3are not in physical contact with the inter-layer film158-2. In some embodiments, top surfaces S154-3of the portions P4of the patterned conductive layer154-3are non-coplanar to a top surface S158-2of the inter-layer film158-2. In some embodiments, a height difference ΔH4between the top surfaces S154-3of the portions P4of the patterned conductive layer154-3and the top surface S158-2of the inter-layer film158-2is approximately ranging from 0.1 μm to 0.7 μm. In other words, the top surfaces S154-3of the portions P4of the patterned conductive layer154-3and the top surface S158-2of the inter-layer film158-2are misaligned to each other along a direction X perpendicular to the stacking direction Z. In some embodiments, as shown inFIG.38, the patterned conductive layer154-3is accessibly revealed by the dielectric layer158-2, where the portions P4of the patterned conductive layer154-3are free of the dielectric layer158-2. In some embodiments, as shown inFIG.38, an interface IF5of the dielectric layer156-2and the inter-layer film158-2is located at a sidewall of the patterned conductive layer154-2b. Referring toFIG.39, in some embodiments, after the formation of the inter-layer film158-2, the dielectric layer156-3is formed on the inter-layer film158-2and over the carrier112. As shown inFIG.39, for example, the dielectric layer156-3covers the patterned conductive layer154-3and the inter-layer film158-2and exposes portions of the patterned conductive layer154-3. The dielectric layer156-3is formed with a plurality of recesses R1exposing portions of the patterned conductive layer154-3, for example. In some embodiments, the formation and material of the dielectric layer156-3is described inFIG.25, and thus are not repeated herein. In the disclosure, the seed layer152-4(including the first sub-layer152-4aand the second sub-layer152-4b), the patterned conductive layer154-3, the inter-layer film158-2, and the dielectric layer156-3are together referred to as a third build-up layer of the redistribution circuit structure150′. In some embodiments, as shown inFIG.39, an interface IF6of the inter-layer film158-2and the dielectric layer156-3is located at a sidewall of the patterned conductive layer154-3. Upon this, the redistribution circuit structure150′ of the package structure PS5is manufactured. In addition, the critical dimensions of the patterned conductive layer154-1,152-2a,152-2b, and152-3can be controlled by respectively adjusting the thickness T1of the seed layer152-1, the thickness T2of the seed layer152-2, the thickness T3of the seed layer152-3, and the thickness T4of the seed layer152-4. That is, in the disclosure, the critical dimension of the metal features in the redistribution circuit structure150′ can be controlled by adjusting the seed layer underlying thereto while maintaining the reliability of the circuitry of the redistribution circuit structure150′. For example, as shown inFIG.39, due to the thickness T3of the seed layer152-3is greater than the thickness T1of the seed layer152-1, the thickness T2of the seed layer152-2, and the thickness T4of the seed layer152-4, the critical dimension of the patterned conductive layer154-2bis smaller the critical dimensions of the patterned conductive layer154-1,152-2a, and152-3, where the critical dimension of the patterned conductive layer154-2bmay be reduced to less than 2 μm by controlling the thickness T3of the seed layer152-3. Also, owing to the presences of the inter-layer films158-1and158-2, the reliability of the package structure PS1is further enhanced as the topography of each of the patterned conductive layers154-2aand154-3is modified and thus a great process window of the redistribution circuit structure150′ is achieved. For illustration purpose, one of each of the first, second, and third build-up layers are included in the redistribution circuit structure150′ ofFIG.39; however, the disclosure is not limited thereto. The numbers of the first build-up layer, the second build-up layer, and the third build-up layer included in the redistribution circuit structure150′ is not limited in the disclosure, and may be determined based on the demand and the design layout. For example, the number of each of the first build-up layer, the second build-up layer, and the third build-up layer included in the redistribution circuit structure150′ may be zero, one, or more than one. Referring toFIG.40, in some embodiments, the package structure PS5is manufactured by performing the processes described inFIG.26toFIG.32on the structure depicted inFIG.39. In some embodiments, as shown inFIG.40, the redistribution circuit structure150′ is formed on the semiconductor dies130and the insulating encapsulation140′, where the redistribution circuit structure150′ is electrically connected to the semiconductor dies130. For example, the redistribution circuit structure150′ is formed on the top surfaces of the semiconductor dies130and the top surface140aof the insulating encapsulation140′. In some embodiments, the redistribution circuit structure150′ is electrically connected to the semiconductor dies130through the conductive vias130dand the pads130b. In some embodiments, the redistribution circuit structure150′ is referred to as a front-side redistribution layer of the semiconductor dies130for providing routing function. In some embodiments, the semiconductor dies130are located between the redistribution circuit structure150′ and the connecting films CM, and the insulating encapsulation140′ are located between the redistribution circuit structure150′ and the debond layer114. As shown inFIG.40, the semiconductor dies130are electrically communicated to each other through the redistribution circuit structure150′, for example. In some embodiments, the redistribution circuit structure118is electrically coupled to the semiconductor dies130through the through vias120and the redistribution circuit structure150′. In some embodiments, the conductive terminals190are electrically connected to the redistribution circuit structure118through the UBM patterns180. In some embodiments, the redistribution circuit structure118is located between the connecting films CM and the conductive terminals190, between the semiconductor dies130and the conductive terminals190, and between the insulating encapsulation140′ and the conductive terminals190. In some embodiments, some of the conductive terminals190are electrically coupled to the redistribution circuit structure150′ through the UBM patterns180, the redistribution circuit structure118, and the through vias120. In some embodiments, some of the conductive terminals190are electrically coupled to the semiconductor dies130through the UBM patterns180, the redistribution circuit structure118, the through vias120, and the redistribution circuit structure150′. In some embodiments, some of the conductive terminals190are electrically coupled to some of the conductive terminals170through the UBM patterns180, the redistribution circuit structure118, the through vias120, and the redistribution circuit structure150′. However, the disclosure is not limited thereto. In certain embodiments, the conductive terminals170may be substituted by conductive terminals200which may include solder balls or BGA balls, see a package structure PS6depicted inFIG.41. In an alternative embodiment, the redistribution circuit structure118, the through vias120, the UBM patterns180, and the conductive terminals190may be optionally omitted, see a package structure PS7depicted inFIG.42. In a further alternative embodiment, the conductive terminals170may be substituted by conductive terminals200which may include solder balls or BGA balls while the redistribution circuit structure118, the through vias120, the UBM patterns180, and the conductive terminals190may be optionally omitted, see a package structure PS8depicted inFIG.43. In further alternative embodiments, in addition to the conductive terminals170,190, and/or200inFIG.40toFIG.43, an additional semiconductor element(s) (not shown) may be disposed on the seed layer patterns160and/or the UBM patterns180for electrically coupling at least one of the semiconductor dies130. In some embodiments, the additional semiconductor element(s) may include a passive component or active component. The number of the additional semiconductor element(s) is not limited in the disclosure, and may be designated based on the demand and design layout. In some embodiments, the package structures PS1to PS8may be further mounted with an additional package, chips/dies, other electronic devices, or a suitable substrate (e.g. an organic substrate) to form a stacked package structure, the disclosure is not limited thereto. In the disclosure, owing to the configuration of the interface IF1to IF6, the reliability of the package structures PS1to PS8is further enhanced. In accordance with some embodiments, a package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer. In accordance with some embodiments, a package structure includes a semiconductor die, an insulating encapsulation, a redistribution circuit structure, and conductive elements. The insulating encapsulation encapsulates the semiconductor die. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the semiconductor die, and includes a first build-up layer and a second build-up layer. The first build-up layer includes a first metallization layer and a first seed layer sandwiched between the first metallization layer and the semiconductor die. The second build-up layer includes a second metallization layer having a first portion and a second portion stacked on the first portion, a second seed layer sandwiched between the first portion of the second metallization layer and the first metallization layer, and a third seed layer sandwiched between the first portion and the second portion. A thickness of the third seed layer is greater than a thickness of the first seed layer and a thickness of the second seed layer. The conductive elements are disposed on and electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is located between the conductive elements and the insulating encapsulation. In accordance with some embodiments, a method of manufacturing package structure includes the following steps, providing a semiconductor die; encapsulating the semiconductor die in an insulating encapsulation; forming a first redistribution circuit structure, wherein the first redistribution circuit structure is electrically connected to the semiconductor die, and forming the redistribution circuit structure includes forming a first metallization layer on the insulating encapsulation, disposing a first dielectric material to embed the first metallization layer therein, and planarizing the first dielectric material to form a first dielectric layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer; and forming conductive elements on the first redistribution circuit structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure. | 89,648 |
11862561 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various embodiments provide methods for forming signal and power routing in semiconductor devices and semiconductor devices including the same. In some embodiments, the routing may be formed in an interconnect structure on a backside of a semiconductor chip including the semiconductor devices. The backside interconnect structure may be routed for power supply lines, electrical ground lines, and signaling to provide connectivity to certain front-side devices, such as transistors or the like. Moreover, routing the power supply lines, the electrical ground lines, and the signaling through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density. Some embodiments discussed herein are described in the context of a die including nano-FETs. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs. FIG.1illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures55(e.g., nanosheets, nanowire, or the like) over fins66on a substrate50(e.g., a semiconductor substrate), wherein the nanostructures55act as channel regions for the nano-FETs. The nanostructure55may include p-type nanostructures, n-type nanostructures, or a combination thereof. Shallow trench isolation (STI) regions68are disposed between adjacent fins66, which may protrude above and from between neighboring STI regions68. Although the STI regions68are described/illustrated as being separate from the substrate50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the STI regions. Additionally, although bottom portions of the fins66are illustrated as being single, continuous materials with the substrate50, the bottom portions of the fins66and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fins66refer to the portion extending between the neighboring STI regions68. Gate dielectric layers100are over top surfaces of the fins66and along top surfaces, sidewalls, and bottom surfaces of the nanostructures55. Gate electrodes102are over the gate dielectric layers100. Epitaxial source/drain regions92are disposed on the fins66on opposing sides of the gate dielectric layers100and the gate electrodes102. FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode102and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions92of a nano-FET. Cross-section B-B′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions92of multiple nano-FETs. Cross-section C-C′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin66of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions92of the nano-FET. Subsequent figures refer to these reference cross-sections for clarity. Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs). FIGS.2through34Care cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS.2through5,6A,7A,8A,9A,10A,11A,12A,13A,14A,15A,16A,17A,18A,19A,20A,21A,22A,23A,24A,25A,26A,27A,28A, and31A-31D illustrate reference cross-section A-A′ illustrated inFIG.1.FIGS.6B,7B,8B,9B,10B,11B,12B,12D,13B,14B,15B,16B,17B,18B,19B,20B,21B,22B,23B,24B,25B,26B,27B,28B,29A,29B,30A,30B, and31A-31D illustrate reference cross-section B-B′ illustrated inFIG.1.FIGS.7C,8C,9C,10C,11C,11D,12C,12E,13C,14C,15C,16C,17C,18C,19C,20C,21C,22C,23C,24C,25C,26C,27C, and28C illustrate reference cross-section C-C′ illustrated inFIG.1.FIG.32Aillustrates reference cross-section X-X′ (see alsoFIGS.32A and32C-32H), which is a version of reference cross-section B-B′.FIG.32Billustrates reference cross-section Y-Y′ (see alsoFIGS.32B and32C-32H), which is another version of reference cross-section B-B′.FIGS.30C-30E,32C-32H,33A,33B,34A, and34Billustrate plan views.FIGS.33C and34Cillustrate circuit layouts. InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors (e.g., n-type nano-FETs) and the p-type region50P can be for forming p-type devices, such as PMOS transistors (e.g., p-type nano-FETs). The n-type region50N may be physically separated from the p-type region50P (as illustrated by divider20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. Although one n-type region50N and one p-type region50P are illustrated, any number of n-type regions50N and p-type regions50P may be provided. Further inFIG.2, a multi-layer stack64is formed over the substrate50. The multi-layer stack64includes alternating layers of first semiconductor layers51A-51C (collectively referred to as first semiconductor layers51) and second semiconductor layers53A-53C (collectively referred to as second semiconductor layers53). For purposes of illustration and as discussed in greater detail below, the first semiconductor layers51will be removed and the second semiconductor layers53will be patterned to form channel regions of nano-FETs in the n-type region50N and the p-type region50P. However, in some embodiments the first semiconductor layers51may be removed and the second semiconductor layers53may be patterned to form channel regions of nano-FETs in the n-type region50N, and the second semiconductor layers53may be removed and the first semiconductor layers51may be patterned to form channel regions of nano-FETs in the p-type region50P. In some embodiments the second semiconductor layers53may be removed and the first semiconductor layers51may be patterned to form channel regions of nano-FETs in the n-type region50N, and the first semiconductor layers51may be removed and the second semiconductor layers53may be patterned to form channel regions of nano-FETs in the p-type region50P. In some embodiments, the second semiconductor layers53may be removed and the first semiconductor layers51may be patterned to form channel regions of nano-FETs in both the n-type region50N and the p-type region50P. The multi-layer stack64is illustrated as including three layers of each of the first semiconductor layers51and the second semiconductor layers53for illustrative purposes. In some embodiments, the multi-layer stack64may include any number of the first semiconductor layers51and the second semiconductor layers53. Each of the layers of the multi-layer stack64may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers51may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium or the like, and the second semiconductor layers53may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like. The multi-layer stack64is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments, multi-layer stack64may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs. The first semiconductor materials and the second semiconductor materials may be materials having a high etch selectivity to one another. As such, the first semiconductor layers51of the first semiconductor material may be removed without significantly removing the second semiconductor layers53of the second semiconductor material thereby allowing the second semiconductor layers53to be patterned to form channel regions of nano-FETs. Similarly, in embodiments in which the second semiconductor layers53are removed and the first semiconductor layers51are patterned to form channel regions, the second semiconductor layers53of the second semiconductor material may be removed without significantly removing the first semiconductor layers51of the first semiconductor material, thereby allowing the first semiconductor layers51to be patterned to form channel regions of nano-FETs. Referring now toFIG.3, fins66are formed in the substrate50and nanostructures55are formed in the multi-layer stack64, in accordance with some embodiments. In some embodiments, the nanostructures55and the fins66may be formed in the multi-layer stack64and the substrate50, respectively, by etching trenches in the multi-layer stack64and the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures55by etching the multi-layer stack64may further define first nanostructures52A-52C (collectively referred to as the first nanostructures52) from the first semiconductor layers51and define second nanostructures54A-54C (collectively referred to as the second nanostructures54) from the second semiconductor layers53. The first nanostructures52and the second nanostructures54may be collectively referred to as nanostructures55. The fins66and the nanostructures55may be patterned by any suitable method. For example, the fins66and the nanostructures55may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins66. FIG.3illustrates the fins66in the n-type region50N and the p-type region50P as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fins66in the n-type region50N may be greater or thinner than the fins66in the p-type region50P. Further, while each of the fins66and the nanostructures55are illustrated as having a consistent width throughout, in other embodiments, the fins66and/or the nanostructures55may have tapered sidewalls such that a width of each of the fins66and/or the nanostructures55continuously increases in a direction towards the substrate50. In such embodiments, each of the nanostructures55may have a different width and be trapezoidal in shape. InFIG.4, shallow trench isolation (STI) regions68are formed adjacent the fins66. The STI regions68may be formed by depositing an insulation material over the substrate50, the fins66, and nanostructures55, and between adjacent fins66. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures55. Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of the substrate50, the fins66, and the nanostructures55. Thereafter, a fill material, such as those discussed above may be formed over the liner. A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures55. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures55such that top surfaces of the nanostructures55and the insulation material are level after the planarization process is complete. The insulation material is then recessed to form the STI regions68. The insulation material is recessed such that upper portions of fins66in the n-type region50N and the p-type region50P protrude from between neighboring STI regions68. Further, the top surfaces of the STI regions68may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions68may be formed flat, convex, and/or concave by an appropriate etch. The STI regions68may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins66and the nanostructures55). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. The process described above with respect toFIGS.2through4is just one example of how the fins66and the nanostructures55may be formed. In some embodiments, the fins66and/or the nanostructures55may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins66and/or the nanostructures55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. Additionally, the first semiconductor layers51(and resulting first nanostructures52) and the second semiconductor layers53(and resulting second nanostructures54) are illustrated and discussed herein as comprising the same materials in the p-type region50P and the n-type region50N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers51and the second semiconductor layers53may be different materials or formed in a different order in the p-type region50P and the n-type region50N. Further inFIG.4, appropriate wells (not separately illustrated) may be formed in the fins66, the nanostructures55, and/or the STI regions68. In embodiments with different well types, different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins66and the STI regions68in the n-type region50N and the p-type region50P. The photoresist is patterned to expose the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 1013atoms/cm3to about 1014atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process. Following or prior to the implanting of the p-type region50P, a photoresist or other masks (not separately illustrated) is formed over the fins66, the nanostructures55, and the STI regions68in the p-type region50P and the n-type region50N. The photoresist is patterned to expose the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 1013atoms/cm3to about 1014atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. InFIG.5, a dummy dielectric layer70is formed on the fins66and/or the nanostructures55. The dummy dielectric layer70may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer72is formed over the dummy dielectric layer70, and a mask layer74is formed over the dummy gate layer72. The dummy gate layer72may be deposited over the dummy dielectric layer70and then planarized, such as by a CMP. The mask layer74may be deposited over the dummy gate layer72. The dummy gate layer72may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer72may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer72may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer74may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer72and a single mask layer74are formed across the n-type region50N and the p-type region50P. It is noted that the dummy dielectric layer70is shown covering only the fins66and the nanostructures55for illustrative purposes only. In some embodiments, the dummy dielectric layer70may be deposited such that the dummy dielectric layer70covers the STI regions68, such that the dummy dielectric layer70extends between the dummy gate layer72and the STI regions68. FIGS.6A through28Cillustrate various additional steps in the manufacturing of embodiment devices.FIGS.6A through18Cillustrate features in either the n-type region50N or the p-type region50P. InFIGS.6A through6C, the mask layer74(seeFIG.5) may be patterned using acceptable photolithography and etching techniques to form masks78. The pattern of the masks78then may be transferred to the dummy gate layer72and to the dummy dielectric layer70to form dummy gates76and dummy gate dielectrics71, respectively. The dummy gates76cover respective channel regions of the fins66. The pattern of the masks78may be used to physically separate each of the dummy gates76from adjacent dummy gates76. The dummy gates76may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins66. InFIGS.7A through7C, a first spacer layer80and a second spacer layer82are formed over the structures illustrated inFIGS.6A through6C. The first spacer layer80and the second spacer layer82will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. InFIGS.7A through7C, the first spacer layer80is formed on top surfaces of the STI regions68; top surfaces and sidewalls of the fins66, the nanostructures55, and the masks78; and sidewalls of the dummy gates76and the dummy gate dielectric71. The second spacer layer82is deposited over the first spacer layer80. The first spacer layer80may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer82may be formed of a material having a different etch rate than the material of the first spacer layer80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like. After the first spacer layer80is formed and prior to forming the second spacer layer82, implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above inFIG.4, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins66and nanostructures55in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins66and nanostructures55in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×1015atoms/cm3to about 1×1019atoms/cm3. An anneal may be used to repair implant damage and to activate the implanted impurities. InFIGS.8A through8C, the first spacer layer80and the second spacer layer82are etched to form first spacers81and second spacers83. As will be discussed in greater detail below, the first spacers81and the second spacers83act to self-align subsequently formed source drain regions, as well as to protect sidewalls of the fins66and/or nanostructure55during subsequent processing. The first spacer layer80and the second spacer layer82may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer82has a different etch rate than the material of the first spacer layer80, such that the first spacer layer80may act as an etch stop layer when patterning the second spacer layer82and such that the second spacer layer82may act as a mask when patterning the first spacer layer80. For example, the second spacer layer82may be etched using an anisotropic etch process wherein the first spacer layer80acts as an etch stop layer, wherein remaining portions of the second spacer layer82form second spacers83as illustrated inFIG.8B. Thereafter, the second spacers83acts as a mask while etching exposed portions of the first spacer layer80, thereby forming first spacers81as illustrated inFIGS.8B and8C. As illustrated inFIG.8B, the first spacers81and the second spacers83are disposed on sidewalls of the fins66and/or nanostructures55. As illustrated inFIG.8C, in some embodiments, the second spacer layer82may be removed from over the first spacer layer80adjacent the masks78, the dummy gates76, and the dummy gate dielectrics71, and the first spacers81are disposed on sidewalls of the masks78, the dummy gates76, and the dummy gate dielectrics60. In other embodiments, a portion of the second spacer layer82may remain over the first spacer layer80adjacent the masks78, the dummy gates76, and the dummy gate dielectrics71. It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers81may be patterned prior to depositing the second spacer layer82), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. InFIGS.9A through9C, first recesses86and second recesses87are formed in the fins66, the nanostructures55, and the substrate5o, in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses86, and first epitaxial materials and epitaxial source/drain regions will be subsequently formed in the second recesses87. The first recesses86and the second recesses87may extend through the first nanostructures52and the second nanostructures54, and into the substrate5o. As illustrated inFIG.9B, top surfaces of the STI regions68may be level with bottom surfaces of the first recesses86. In various embodiments, the fins66may be etched such that bottom surfaces of the first recesses86are disposed below the top surfaces of the STI regions68. Bottom surfaces of the second recesses87may be disposed below the bottom surfaces of the first recesses and the top surfaces of the STI regions68. The first recesses86and the second recesses87may be formed by etching the fins66, the nanostructures55, and the substrate5ousing anisotropic etching processes, such as RIE, NBE, or the like. The first spacers81, the second spacers83, and the masks78mask portions of the fins66, the nanostructures55, and the substrate5oduring the etching processes used to form the first recesses86and the second recesses87. A single etch process or multiple etch processes may be used to etch each layer of the nanostructures55and/or the fins66. Timed etch processes may be used to stop the etching after the first recesses86and the second recesses87reach desired depths. The second recesses87may be etched by the same processes used to etch the first recesses86and an additional etch process before or after the first recesses86are etched. For example, regions corresponding to the first recesses86may be masked while the additional etch process for the second recesses87is performed. InFIGS.10A through10C, portions of sidewalls of the layers of the multi-layer stack64formed of the first semiconductor materials (e.g., the first nanostructures52) exposed by the first recesses86and the second recesses87are etched to form sidewall recesses88. Although sidewalls of the first nanostructures52adjacent the sidewall recesses88are illustrated as being straight inFIG.10C, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In an embodiment in which the first nanostructures52include, for example, SiGe, and the second nanostructures54include, for example, Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first nanostructures52. InFIGS.11A through11D, first inner spacers90are formed in the sidewall recess88. The first inner spacers90may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated inFIGS.10A through10C. The first inner spacers90act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions and epitaxial materials will be formed in the first recesses86and the second recesses87, while the first nanostructures52will be replaced with corresponding gate structures. The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first inner spacers90. Although outer sidewalls of the first inner spacers90are illustrated as being flush with sidewalls of the second nanostructures54, the outer sidewalls of the first inner spacers90may extend beyond or be recessed from sidewalls of the second nanostructures54. Moreover, although the outer sidewalls of the first inner spacers90are illustrated as being straight inFIG.11C, the outer sidewalls of the first inner spacers90may be concave or convex. As an example,FIG.11Dillustrates an embodiment in which sidewalls of the first nanostructures52are concave, outer sidewalls of the first inner spacers90are concave, and the first inner spacers90are recessed from sidewalls of the second nanostructures54. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers90may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions92, discussed below with respect toFIGS.12A through12E) by subsequent etching processes, such as etching processes used to form gate structures. InFIGS.12A through12E, first epitaxial materials91are formed in the second recesses87and epitaxial source/drain regions92are formed in the first recesses86and the second recesses87. In some embodiments, the first epitaxial materials91may be sacrificial materials, which are subsequently removed to form backside vias (such as the backside vias130, discussed below with respect toFIGS.26A through26D). As illustrated inFIGS.12B through12E, top surfaces of the first epitaxial materials91may be level with bottom surfaces of the first recesses86. However, in some embodiments, top surfaces of the first epitaxial materials91may be disposed above or below bottom surfaces of the first recesses86. The first epitaxial materials91may be epitaxially grown in the second recesses87using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial materials91may include any acceptable material, such as silicon germanium or the like. The first epitaxial materials91may be formed of materials having high etch selectivity to materials of the epitaxial source/drain regions92and dielectric layers (such as the STI regions68and second dielectric layers125, discussed below with respect toFIGS.24A through24C). As such, the first epitaxial materials91may be removed and replaced with the backside vias without significantly removing the epitaxial source/drain regions92and the dielectric layers. Similarly as before, regions corresponding to the first recesses86may be masked while the first epitaxial materials91are formed in the second recesses87. The epitaxial source/drain regions92are then formed in the first recesses86and over the first epitaxial materials91in the second recesses87. In some embodiments, the epitaxial source/drain regions92may exert stress on the second nanostructures54, thereby improving performance. As illustrated inFIG.12C, the epitaxial source/drain regions92are formed in the first recesses86and the second recesses87such that each dummy gate76is disposed between respective neighboring pairs of the epitaxial source/drain regions92. In some embodiments, the first spacers81are used to separate the epitaxial source/drain regions92from the dummy gates76and the first inner spacers90are used to separate the epitaxial source/drain regions92from the nanostructures55by an appropriate lateral distance so that the epitaxial source/drain regions92do not short out with subsequently formed gates of the resulting nano-FETs. The epitaxial source/drain regions92in the n-type region50N (e.g., the NMOS region) may be formed by masking the p-type region50P (e.g., the PMOS region). Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86and the second recesses87in the n-type region50N. The epitaxial source/drain regions92may include any acceptable material appropriate for n-type nano-FETs. For example, if the second nanostructures54are silicon, the epitaxial source/drain regions92may include materials exerting a tensile strain on the second nanostructures54, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions92may have surfaces raised from respective upper surfaces of the nanostructures55and may have facets. The epitaxial source/drain regions92in the p-type region50P (e.g., the PMOS region) may be formed by masking the n-type region50N (e.g., the NMOS region). Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86and the second recesses87in the p-type region50P. The epitaxial source/drain regions92may include any acceptable material appropriate for p-type nano-FETs. For example, if the first nanostructures52are silicon germanium, the epitaxial source/drain regions92may comprise materials exerting a compressive strain on the first nanostructures52, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions92may also have surfaces raised from respective surfaces of the multi-layer stack56and may have facets. The epitaxial source/drain regions92, the first nanostructures52, the second nanostructures54, and/or the substrate50may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1019atoms/cm3and about 1×1021atoms/cm3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions92may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions92in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions92have facets which expand laterally outward beyond sidewalls of the nanostructures55. In some embodiments, these facets cause adjacent epitaxial source/drain regions92of a same nano-FET to merge as illustrated byFIG.12B. In other embodiments, adjacent epitaxial source/drain regions92remain separated after the epitaxy process is completed as illustrated byFIG.12D. In the embodiments illustrated inFIGS.12B and12D, the first spacers81may be formed to a top surface of the STI regions68thereby blocking the epitaxial growth. In some other embodiments, the first spacers81may cover portions of the sidewalls of the nanostructures55further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers81may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI regions68. The epitaxial source/drain regions92may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions92may comprise a first semiconductor material layer92A, a second semiconductor material layer92B, and a third semiconductor material layer92C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions92. Each of the first semiconductor material layer92A, the second semiconductor material layer92B, and the third semiconductor material layer92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer92A may have a dopant concentration less than the second semiconductor material layer92B and greater than the third semiconductor material layer92C. In embodiments in which the epitaxial source/drain regions92comprise three semiconductor material layers, the first semiconductor material layer92A may be deposited, the second semiconductor material layer92B may be deposited over the first semiconductor material layer92A, and the third semiconductor material layer92C may be deposited over the second semiconductor material layer92B. FIG.12Eillustrates an embodiment in which sidewalls of the first nanostructures52are concave, outer sidewalls of the first inner spacers90are concave, and the first inner spacers90are recessed from sidewalls of the second nanostructures54. As illustrated inFIG.12E, the epitaxial source/drain regions92may be formed in contact with the first inner spacers90and may extend past sidewalls of the second nanostructures54. InFIGS.13A through13C, a first interlayer dielectric (ILD)96is deposited over the structure illustrated inFIGS.12A through12C. The first ILD96may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)94is disposed between the first ILD96and the epitaxial source/drain regions92, the masks78, and the first spacers81. The CESL94may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD96. InFIGS.14A through14C, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD96with the top surfaces of the dummy gates76or the masks78. The planarization process may also remove the masks78on the dummy gates76, and portions of the first spacers81along sidewalls of the masks78. After the planarization process, top surfaces of the dummy gates76, the first spacers81, and the first ILD96are level within process variations. Accordingly, the top surfaces of the dummy gates76are exposed through the first ILD96. In some embodiments, the masks78may remain, in which case the planarization process levels the top surface of the first ILD96with top surface of the masks78and the first spacers81. InFIGS.15A through15C, the dummy gates76, and the masks78if present, are removed in one or more etching steps, so that third recesses98are formed. Portions of the dummy gate dielectrics60in the third recesses98are also be removed. In some embodiments, the dummy gates76and the dummy gate dielectrics60are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates76at a faster rate than the first ILD96or the first spacers81. Each of the third recess98exposes and/or overlies portions of nanostructures55, which act as channel regions in subsequently completed nano-FETs. Portions of the nanostructures55which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions92. During the removal, the dummy gate dielectrics60may be used as etch stop layers when the dummy gates76are etched. The dummy gate dielectrics60may then be removed after the removal of the dummy gates76. InFIGS.16A through16C, the first nanostructures52are removed extending the third recesses98. The first nanostructures52may be removed by performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures52, while the second nanostructures54, the substrate50, the STI regions68remain relatively unetched as compared to the first nanostructures52. In embodiments in which the first nanostructures52include, for example, SiGe, and the second nanostructures54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructures52. InFIGS.17A through17C, gate dielectric layers100and gate electrodes102are formed for replacement gates. The gate dielectric layers100are deposited conformally in the third recesses98. The gate dielectric layers100may be formed on top surfaces and sidewalls of the substrate50and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures54. The gate dielectric layers100may also be deposited on top surfaces of the first ILD96, the CESL94, the first spacers81, and the STI regions68and on sidewalls of the first spacers81and the first inner spacers90. In accordance with some embodiments, the gate dielectric layers100comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layers100may comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers100include a high-k dielectric material, and in these embodiments, the gate dielectric layers100may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers100may be the same or different in the n-type region50N and the p-type region50P. The formation methods of the gate dielectric layers100may include molecular-beam deposition (MBD), ALD, PECVD, and the like. The gate electrodes102are deposited over the gate dielectric layers100, respectively, and fill the remaining portions of the third recesses98. The gate electrodes102may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although single layer gate electrodes102are illustrated inFIGS.17A and17C, the gate electrodes102may comprise any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers which make up the gate electrodes102may be deposited in the n-type region50N between adjacent ones of the second nanostructures54and between the second nanostructure54A and the substrate50, and may be deposited in the p-type region50P between adjacent ones of the first nanostructures52. The formation of the gate dielectric layers100in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers100in each region are formed from the same materials, and the formation of the gate electrodes102may occur simultaneously such that the gate electrodes102in each region are formed from the same materials. In some embodiments, the gate dielectric layers100in each region may be formed by distinct processes, such that the gate dielectric layers100may be different materials and/or have a different number of layers, and/or the gate electrodes102in each region may be formed by distinct processes, such that the gate electrodes102may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. After the filling of the third recesses98, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers100and the material of the gate electrodes102, which excess portions are over the top surface of the first ILD96. The remaining portions of material of the gate electrodes102and the gate dielectric layers100thus form replacement gate structures of the resulting nano-FETs. The gate electrodes102and the gate dielectric layers100may be collectively referred to as gate structures103. InFIGS.18A through18C, the gate structures103(including the gate dielectric layers100and the corresponding overlying gate electrodes102) are recessed, so that recess are formed directly over the gate structures103and between opposing portions of first spacers81. Gate masks104comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled in the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD96. Subsequently formed gate contacts (such as the gate contacts114, discussed below with respect toFIGS.20A through20C) penetrate through the gate masks104to contact the top surfaces of the recessed gate electrodes102. As further illustrated byFIGS.18A through18C, a second ILD106is deposited over the first ILD96and over the gate masks104. In some embodiments, the second ILD106is a flowable film formed by FCVD. In some embodiments, the second ILD106is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. InFIGS.19A through19C, the second ILD106, the first ILD96, the CESL94, and the gate masks104are etched to form fourth recesses108exposing surfaces of the epitaxial source/drain regions92and/or the gate structures103. The fourth recesses108may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the fourth recesses108may be etched through the second ILD106and the first ILD96using a first etching process; may be etched through the gate masks104using a second etching process; and may then be etched through the CESL94using a third etching process. A mask, such as a photoresist, may be formed and patterned over the second ILD106to mask portions of the second ILD106from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the fourth recesses108extend into the epitaxial source/drain regions92and/or the gate structures103, and a bottom of the fourth recesses108may be level with (e.g., at a same level, or having a same distance from the substrate50) or lower than (e.g., closer to the substrate50) a top surface of the epitaxial source/drain regions92and/or the gate structures103. AlthoughFIG.19Cillustrates the fourth recesses108as exposing the epitaxial source/drain regions92and the gate structures103in a same cross-section, in various embodiments, the epitaxial source/drain regions92and the gate structures103may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After the fourth recesses108are formed, first silicide regions110are formed over the epitaxial source/drain regions92. In some embodiments, the first silicide regions110are formed by first depositing a metal (not separately illustrated) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions92(e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions92, then performing a thermal anneal process to form the first silicide regions110. The un-reacted portions of the deposited metal are then removed, for example, by an etching process. Although the first silicide regions110are referred to as silicide regions, the first silicide regions110may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide). In an embodiment, the first silicide regions110comprise TiSi and have a thickness in a range between about 2 nm and about 10 nm. InFIGS.20A through20C, source/drain contacts112and gate contacts114(also referred to as contact plugs) are formed in the fourth recesses108. The source/drain contacts112and the gate contacts114may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the source/drain contacts112and the gate contacts114each include a barrier layer and a conductive material, and are each electrically connected to an underlying conductive feature (e.g., a gate electrode102and/or a first silicide region110). The gate contacts114are electrically connected to the gate electrodes102and the source/drain contacts112are electrically connected to the first silicide regions110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from surfaces of the second ILD106. The epitaxial source/drain regions92, the second nanostructures54, and the gate structures103(including the gate dielectric layers100and the gate electrodes102) may collectively be referred to as transistor structures109. The transistor structures109may be formed in a device layer, with a first interconnect structure (such as the front-side interconnect structure120, discussed below with respect toFIGS.21A through21C) being formed over a front-side thereof and a second interconnect structure (such as the backside interconnect structure140, discussed below with respect toFIGS.27A through27C) being formed over a backside thereof. Although the device layer is described as having nano-FETs, other embodiments may include a device layer having different types of transistors (e.g., planar FETs, finFETs, thin film transistors (TFTs), or the like). AlthoughFIGS.20A through20Cillustrate a source/drain contact112extending to each of the epitaxial source/drain regions92, the source/drain contacts112may be omitted from certain ones of the epitaxial source/drain regions92. Similarly, althoughFIGS.20A through20Cillustrate a gate contact114extending to each of the gate structures103, the gate contact114may be omitted from certain ones of the gate structures103. For example, as explained in greater detail below, conductive features (e.g., backside vias or power rails) may be subsequently attached through a backside of one or more of the epitaxial source/drain regions92and/or the gate structures103. For these particular epitaxial source/drain regions92and/or the gate structures103, the source/drain contacts112and/or the gate contacts114, respectively, may be omitted or may be dummy contacts that are not electrically connected to any overlying conductive lines (such as the first conductive features122, discussed below with respect toFIGS.21A through21C). FIGS.21A through28Cillustrate intermediate steps of forming a front-side interconnect structure and a backside interconnect structure over the transistor structures109. The front-side interconnect structure and the backside interconnect structure may each comprise conductive features that are electrically connected to the nano-FETs formed over the substrate50and/or the transistor structures109.FIGS.21A,22A,23A,24A,25A,26A,27A, and28Aillustrate reference cross-section A-A′ illustrated inFIG.1.FIGS.21B,22B,23B,24B,25B,26B,27B, and28Billustrate reference cross-section B-B′ illustrated inFIG.1.FIGS.21C,22C,23C,24C,25C,26C,27C, and28Cillustrate reference cross-section C-C′ illustrated inFIG.1. The process steps described inFIGS.21A through28Cmay be applied to both the n-type region50N and the p-type region50P. As noted above, a backside conductive feature (e.g., a backside via or a power rail as described in greater detail below) may be connected to one or more of the epitaxial source/drain regions92and/or the gate structures103. As such, the source/drain contacts112may be optionally omitted from the epitaxial source/drain regions92. InFIGS.21A through21C, a front-side interconnect structure120is formed on the second ILD106. The front-side interconnect structure120may be referred to as a front-side interconnect structure because it is formed on a front-side of the transistor structures109(e.g., a side of the transistor structures109on which active devices are formed). The front-side interconnect structure120may comprise one or more layers of first conductive features122formed in one or more stacked first dielectric layers124. Each of the stacked first dielectric layers124may comprise a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The first dielectric layers124may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like. The first conductive features122may comprise conductive lines and conductive vias interconnecting the layers of conductive lines. The conductive vias may extend through respective ones of the first dielectric layers124to provide vertical connections between layers of the conductive lines. The first conductive features122may be formed through any acceptable process, such as, a damascene process, a dual damascene process, or the like. In some embodiments, the first conductive features122may be formed using a damascene process in which a respective first dielectric layer124is patterned utilizing a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the first conductive features122. An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the first conductive features122may be formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the respective first dielectric layer124and to planarize surfaces of the first dielectric layer124and the first conductive features122for subsequent processing. FIGS.21A through21Cillustrate five layers of the first conductive features122and the first dielectric layers124in the front-side interconnect structure120. However, it should be appreciated that the front-side interconnect structure120may comprise any number of first conductive features122disposed in any number of first dielectric layers124. The front-side interconnect structure120may be electrically connected to the gate contacts114and the source/drain contacts112to form functional circuits. In some embodiments, the functional circuits formed by the front-side interconnect structure120may comprise logic circuits, memory circuits, image sensor circuits, or the like. InFIGS.22A through22C, a carrier substrate150is bonded to a top surface of the front-side interconnect structure120by a first bonding layer152A and a second bonding layer152B (collectively referred to as a bonding layer152). The carrier substrate150may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. The carrier substrate150may provide structural support during subsequent processing steps and in the completed device. In various embodiments, the carrier substrate150may be bonded to the front-side interconnect structure120using a suitable technique, such as dielectric-to-dielectric bonding, or the like. The dielectric-to-dielectric bonding may comprise depositing the first bonding layer152A on the front-side interconnect structure120. In some embodiments, the first bonding layer152A comprises silicon oxide (e.g., a high density plasma (HDP) oxide, or the like) that is deposited by CVD, ALD, PVD, or the like. The second bonding layer152B may likewise be an oxide layer that is formed on a surface of the carrier substrate150prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may be used for the first bonding layer152A and the second bonding layer152B. The dielectric-to-dielectric bonding process may further include applying a surface treatment to one or more of the first bonding layer152A and the second bonding layer152B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water or the like) that may be applied to one or more of the bonding layers152. The carrier substrate150is then aligned with the front-side interconnect structure120and the two are pressed against each other to initiate a pre-bonding of the carrier substrate150to the front-side interconnect structure120. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). After the pre-bonding, an annealing process may be applied by, for example, heating the front-side interconnect structure120and the carrier substrate150to a temperature of about 170° C. to about 400° C., for example. Further inFIGS.22A through22C, after the carrier substrate150is bonded to the front-side interconnect structure120, the device may be flipped such that a backside of the transistor structures109faces upwards. The backside of the transistor structures109may refer to a side opposite to the front-side of the transistor structures109on which the active devices are formed. InFIGS.23A through23C, a thinning process may be applied to the backside of the substrate50. The thinning process may comprise a planarization process (e.g., a mechanical grinding, a CMP, or the like), an etch-back process, a combination thereof, or the like. The thinning process may expose surfaces of the first epitaxial materials91opposite the front-side interconnect structure120. Further, a portion of the substrate50may remain over the gate structures103(e.g., the gate electrodes102and the gate dielectric layers100) and the nanostructures55after the thinning process. As illustrated inFIGS.23A through23C, backside surfaces of the substrate50, the first epitaxial materials91, the STI regions68, and the fins66may be level with one another following the thinning process. InFIGS.24A through24C, remaining portions of the fins66and the substrate50are removed and replaced with a second dielectric layer125. The fins66and the substrate50may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The etching process may be one that is selective to the material of the fins66and the substrate50(e.g., etches the material of the fins66and the substrate50at a faster rate than the material of the STI regions68, the gate dielectric layers100, the epitaxial source/drain regions92, and the first epitaxial materials91). After etching the fins66and the substrate50, surfaces of the STI regions68, the gate dielectric layers100, the epitaxial source/drain regions92, and the first epitaxial materials91may be exposed. The second dielectric layer125is then deposited on the backside of the transistor structures109in recesses formed by removing the fins66and the substrate50. The second dielectric layer125may be deposited over the STI regions68, the gate dielectric layers100, and the epitaxial source/drain regions92. The second dielectric layer125may physically contact surfaces of the STI regions68, the gate dielectric layers100, the epitaxial source/drain regions92, and the first epitaxial materials91. The second dielectric layer125may be substantially similar to the second ILD106, described above with respect toFIGS.18A through18C. For example, the second dielectric layer125may be formed of a like material and using a like process as the second ILD106. As illustrated inFIGS.24A through24C, a CMP process or the like may be used to remove material of the second dielectric layer125such that top surfaces of the second dielectric layer125are level with top surfaces of the STI regions68and the first epitaxial materials91. InFIGS.25A through25C, the first epitaxial materials91are removed to form fifth recesses128, and second silicide regions129are formed in the fifth recesses128. The first epitaxial materials91may be removed by a suitable etching process, which may be an isotropic etching process, such as a wet etching process. The etching process may have a high etch selectivity to materials of the first epitaxial materials91. As such, the first epitaxial materials91may be removed without significantly removing materials of the second dielectric layer125, the STI regions68, or the epitaxial source/drain regions92. The fifth recesses128may expose sidewalls of the STI regions68, backside surfaces of the epitaxial source/drain regions92, and sidewalls of the second dielectric layer125. Second silicide regions129may then be formed in the fifth recesses128on backsides of the epitaxial source/drain regions92. The second silicide regions129may be similar to the first silicide regions110, described above with respect toFIGS.19A through19C. For example, the second silicide regions129may be formed of a like material and using a like process as the first silicide regions110. InFIGS.26A through26C, backside vias130are formed in the fifth recesses128. The backside vias130may extend through the second dielectric layer125and the STI regions68and may be electrically connected to the epitaxial source/drain regions92through the second silicide regions129. The backside vias130may be similar to the source/drain contacts112, described above with respect toFIGS.20A through20C. For example, the backside vias130may be formed of a like material and using a like process as the source/drain contacts112. A planarization process (e.g., a CMP, a grinding, an etch-back, or the like) may be performed to remove excess portions of the backside vias130formed over the STI regions68and/or the second dielectric layer125. InFIGS.27A through27C, a backside interconnect structure140is formed on the second dielectric layer125and the STI regions68. The backside interconnect structure140may be referred to as a backside interconnect structure because it is formed on a backside of the transistor structures109(e.g., an opposite side of the substrate50and/or the transistor structures109on which active devices are formed). The backside interconnect structure140may comprise one or more layers of second conductive features (e.g., conductive lines133, conductive vias134, conductive lines135, conductive vias136, and conductive line137) formed in one or more stacked second dielectric layers (e.g., second dielectric layers132A-C, collectively referred to as second dielectric layers132). Each of the stacked second dielectric layers132may comprise a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The second dielectric layers132may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like. The backside interconnect structure140comprises conductive vias134and136interconnecting the layers of conductive lines133,135, and137. The conductive vias134/136may extend through respective ones of the second dielectric layers132to provide vertical connections between layers of the conductive lines133/135/137. For example, the conductive vias134may couple the conductive lines133to the conductive lines135, and the conductive vias136may couple the conductive lines135to the conductive lines137. The conductive lines133/135/137and the conductive vias134/136may be formed using a similar process and similar materials as described above in connection with the first conductive features122, including a single or dual damascene process, through any acceptable process, or the like. The conductive lines133are formed in the second dielectric layer132A. Forming the conductive lines133may include patterning recesses in the second dielectric layer132A using a combination of photolithography and etching processes, for example. A pattern of the recesses in the second dielectric layer132A may correspond to a pattern of the conductive lines133. The conductive lines133are then formed by depositing a conductive material in the recesses. In some embodiments, the conductive lines133comprise a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the conductive lines133comprise copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like. An optional diffusion barrier and/or optional adhesion layer may be deposited prior to filling the recesses with the conductive material. Suitable materials for the barrier layer/adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, or the like. The conductive lines133may be formed using, for example, CVD, ALD, PVD, plating or the like. The conductive lines133are electrically connected to the epitaxial source/drain regions92through the backside vias130and the second silicide regions129. A planarization process (e.g., a CMP, a grinding, an etch-back, or the like) may be performed to remove excess portions of the conductive lines133formed over the second dielectric layer132A. The conductive lines135and137and the conductive vias134and136may be formed in a similar way using similar materials. In some embodiments, the conductive lines133are formed in a single damascene process through the second dielectric layer132A, while the conductive lines135and the conductive vias134are formed in a dual damascene process through the second dielectric layer132B and the conductive lines137and the conductive vias136are also formed in a dual damascene process through the second dielectric layer132C. FIGS.27A through27Cillustrate three layers of the second conductive lines133/135/137and the second dielectric layers132A/132B/132C in the backside interconnect structure140. However, it should be appreciated that the backside interconnect structure140may comprise any number of conductive lines and conductive vias disposed in any number of second dielectric layers132. The backside interconnect structure140may be electrically connected to the backside vias130to form functional circuits. In some embodiments, the functional circuits formed by the backside interconnect structure140in conjunction with the front-side interconnect structure120may comprise logic circuits, memory circuits, image sensor circuits, or the like. Discussed in greater detail below, the conductive lines135in the second dielectric layer132B may comprise power rails and signal lines (identified and labeled separately in connection withFIGS.27A through27Cand thereafter). The power rails may be used to provide a voltage source to the integrated circuit, and the signal lines may be used to transmit signals between elements of the integrated circuit. InFIGS.28A through28C, a passivation layer144, under bump metallurgies (UBMs)146, and external connectors148are formed over the backside interconnect structure140. The passivation layer144may comprise polymers such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer144may include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer144may be deposited by, for example, CVD, PVD, ALD, or the like. The UBMs146are formed through the passivation layer144over the conductive lines137and the second dielectric layer132C in the backside interconnect structure140, and the external connectors148are formed on the UBMs146. In some embodiments in which the conductive lines137are not formed, the passivation layer144is formed directly over the conductive lines135and the second dielectric layer132B. The UBMs146may comprise one or more layers of copper, nickel, gold, or the like, which are formed by a plating process, or the like. The external connectors148(e.g., solder balls) are formed on the UBMs146. The formation of the external connectors148may include placing solder balls on exposed portions of the UBMs146and reflowing the solder balls. In some embodiments, the formation of the external connectors148includes performing a plating step to form solder regions over the topmost conductive lines137and then reflowing the solder regions. The UBMs146and the external connectors148may be used to provide input/output connections to other electrical components, such as, other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBMs146and the external connectors148may also be referred to as backside input/output pads that may provide signal, supply voltage, and/or supply ground connections to the nano-FETs described above. FIGS.29A through29Billustrate exemplary layouts of backside routing, including the backside interconnect structure140. The backside interconnect structure140may comprise power regions140P and signal regions140S for the corresponding routing to be substantially separate from one another. The signal regions140S include routing of the transistor structures109(e.g., the epitaxial source/drain regions92and/or the gate structures103, such as the gate electrodes102) and the backside vias130to the conductive lines135. The power regions140P include routing from the transistor structures109and the backside vias130to the power rails135P. FIGS.29A through29Billustrate an exemplary layout of the backside routing, including the backside interconnect structure140, from the transistor structures109to signal lines135S and power rails135P. In accordance with some embodiments, the signal lines135S and the power rails135P are portions of the conductive lines135. However, a person of ordinary skill in the art would understand that signal lines and/or power rails may, instead, be formed as part of other conductive lines, such as the conductive lines133and the conductive lines137. By forming the signal lines135S and the power rails135P among the conductive lines135, such as within the same level of conductive lines, the conductive lines133may be routed with greater complexity and density from the transistor structures109to the signal lines135S and the power rails135P. As further illustrated, the backside interconnect structure140may be separated into a plurality of signal regions140S and power regions140P. The signal regions140S substantially or entirely contain routing from some transistor structures109to the signal lines135S. The power regions140P substantially or entirely contain routing from other transistor structures109to the power rails135P. Separating the backside routing between signal regions140S and power regions140P achieves benefits, such as reducing effects of parasitic capacitance that the wider routing of the power regions140P may have on the narrower routing of the signal regions140S. In accordance with some embodiments, routing of the power regions140P is formed substantially directly over the corresponding transistor structures109in order to minimize the lateral widths of the power regions140P. Such a design layout provides more lateral space available for density and complexity in the routing through the signal regions140S. Referring toFIG.29A, each of a first epitaxial source/drain region92A, a second epitaxial source/drain region92B, a third epitaxial source/drain region92C, and a fourth epitaxial source/drain region92D may be electrically connected to the backside interconnect structure140. For the sake of simplicity, the epitaxial source/drain regions92A/92B/92C/92D are illustrated as being adjacent to one another and in the same B-B′ cross-section. However, a person of ordinary skill in the art would understand that some or all of the epitaxial source/drain regions92A/92B/92C/92D may be non-adjacent to one another and/or located in different B-B′ cross-sections. In the case of adjacent epitaxial source/drain regions92A/92B/92C/92D, the epitaxial source/drain regions92A/92B/92C/92D may be separated by one or more hybrid fins161. The hybrid fins161may be formed after formation of the fins66(seeFIG.4) and before formation of the dummy gates76(seeFIG.5) by etching recesses in the multi-layer stack64. The hybrid fins161may then be formed by depositing a sacrificial layer (not separately illustrated) on sidewalls of the fins66using a conformal deposition process, such as CVD, ALD, PECVD, or the like. In some embodiments, the sacrificial material is a semiconductor material (e.g., SiGe, Si, or the like) that has a same material composition as the first semiconductor material or the second semiconductor material. The sacrificial material may define the recesses between the fins66over the sacrificial material and between sidewalls of the sacrificial material. One or more insulating materials are deposited in the recesses to form the hybrid fins161. For example, a liner and a fill material (not separately illustrated) may be deposited in the recesses by CVD, ALD, PECVD, or the like. The liner may comprise a low-k material, such as an oxide, SiOC, SiOCN, SiON, or the like, and the fill material may comprise an oxide, such as a flowable CVD, or the like (separate components not specifically illustrated). In some embodiments, a portion of the liner and the fill material may be partially etched, and a high-k material, such as HfO, ZrO, or the like, may be deposited into that recess over the liner and the fill material. The hybrid fin161provides an insulating boundary between adjacent epitaxial source/drain regions92, which may have different conductivity types. After the hybrid fins161are formed, the sacrificial material may be removed concurrently with removing the first semiconductor material and/or the second semiconductor material to define the nanostructures55. In some embodiments, the epitaxial source/drain regions92may contact sidewalls of the hybrid fins161, and a portion of the first ILD96may be deposited between the hybrid fins161and the STI regions68. As illustrated, the first and fourth epitaxial source/drain regions92A and92D may be coupled through different power regions140P of the backside interconnect structure140to the power rails135P. The first and fourth epitaxial source/drain regions92A and92D, therefore, may not need source/drain contacts112to the front-side interconnect structure120. In addition, the second and third epitaxial source/drain regions92B and92C may be coupled through a same signal region140S of the backside interconnect structure140to the signal lines135S. As discussed above, a substantially vertical layout of the power regions140P provides more available lateral space for the signal regions140S. Although only the second and third epitaxial source/drain regions92B and92C are illustrated as being further coupled to the front-side interconnect structure120, any or all of the epitaxial source/drain regions92A/92B/92C/92D may be coupled to one or both of the front-side interconnect structure120and the backside interconnect structure140. Similarly, any or all of the epitaxial source/drain regions92A/92B/92C/92D may be coupled through the backside interconnect structure140to either a signal line135S or a power rail135P. Note that a single integrated circuit die may comprise a plurality of the above-described configurations. Referring toFIG.29B, as discussed above in connection withFIGS.27A through27C, additional second dielectric layers132(e.g., second dielectric layer132C) and additional conductive lines (e.g., conductive lines137) may be formed over the conductive lines135to complete the backside interconnect structure140. In addition, as discussed above in connection withFIGS.28A through28C, passivation layer144, UBMs146, and external connectors148may be formed over the backside interconnect structure140. In some embodiments, the signal region140S is limited to the signal lines135S, which means an entirety of the additional dielectric layers132may be utilized for the conductive lines137to electrically couple the power rails135P to the external connectors148. In some embodiments not separately illustrated, portions of the additional dielectric layers132may be utilized for the conductive lines137to electrically couple some of the signal lines135S to some of the external connectors148. As illustrated, the conductive lines137, the UBMs146, and the external connectors148have the spatial freedom to extend over portions of the signal region140S, if necessary. However, in some embodiments, the routing through some or all of the power regions140may remain substantially vertical aligned over the corresponding epitaxial source/drain regions (e.g., the first and fourth epitaxial source/drain regions92A and92B). InFIGS.30A through30E, the backside interconnect structure140may comprise a drain to drain signal connection between a first epitaxial source/drain region92A of a first transistor structure109A (seeFIG.30A) and a second epitaxial source/drain region92B of a second transistor structure109B (seeFIG.30B). The transistor structures109A and109B may be part of an array of transistors and may be adjacent to one another or displaced from one another. As illustrated, the first and second epitaxial source/drain regions92A and92B may be electrically connected to one another through one of the signal lines135S of the backside interconnect structure140. In some embodiments not separately illustrated, the signal line135S may be further electrically connected to an external signal source through one of the UBMs145and one of the external connectors148. FIGS.30C through30Eillustrate plan view schematics of how the first and second epitaxial source/drain regions92A and92B fromFIGS.30A and30Bmay be electrically connected to one another through the backside interconnect structure140. For example, the first epitaxial source/drain region92A may be coupled to a first backside via130A, and the second epitaxial source/drain region may be coupled to a second backside via130B. In addition, the first backside via130A may be coupled to a first conductive line133A, and the second backside via130B may be coupled to a second conductive line133B. Each of the first and second conductive lines133A and133B may be coupled to a first and a second conductive via134A and134B, respectively, and those conductive vias134A and134B may be coupled to the signal line135S. The signal line135S may be disposed in a same dielectric layer (e.g., the second dielectric layer132B) as other signal lines135S and the power rails135P, which advantageously reduces the number of layers in the backside interconnect structure140. In addition, as noted above, the extra layer(s) of the conductive lines133and the conductive vias134electrically interposed between the backside vias130and the conductive lines (e.g., the signal line135S and the power rail135P) allows for more complexity and density in the backside interconnect structure140. Note that some or all of the layouts illustrated inFIGS.30C through30Emay be formed within the same integrated circuit die. FIGS.30C,30D, and30Eillustrate different layouts for connecting the first epitaxial source/drain region92A and the second epitaxial source/drain region with the signal line135S according to some embodiments. As illustrated inFIG.30C, the first epitaxial source/drain region92A and the second epitaxial source/drain region92B may be parts of a cell, such as a memory cell. The first and second epitaxial source/drain regions92A and92B may be near one another but not necessarily adjacent. As illustrated inFIGS.30D and30E, the first epitaxial source/drain region92A and the second epitaxial source/drain region92B may be parts of the same or different cells, as indicated by dividers160. Further, inFIGS.30C and30D, the conductive line133A and the conductive line133B may be on the same side of the signal line135S, while inFIG.30E, the conductive line133A and the conductive line133B may be on opposite sides of the signal line135S. FIGS.31A through31Dillustrate the formation of a backside interconnect structure140that comprises a drain to gate signal connection from an epitaxial source/drain region92A of a first transistor structure109A to a gate structure103B (e.g., a gate electrode102B) of a second transistor structure109B. Similarly as discussed above with respect toFIGS.24A through26C, after bonding the carrier substrate150to the front-side interconnect structure120and flipping the structure over so that the transistor structures109face upwards, all or part of the substrate50may be removed to form the second dielectric layer125, and the first epitaxial materials91may be removed to form the backside vias130.FIG.31Aillustrates the B-B′ cross-section of epitaxial source/drain regions92A of the first transistor structure109A with a backside via130formed over the epitaxial source/drain regions92A and extending through the second dielectric layer125.FIG.31Billustrates the A-A′ cross-section along gate electrode102B of the second transistor structure109B. Referring toFIGS.31C and31D, similarly as discussed above with respect toFIGS.27A through27C, portions of the backside interconnect structure140are formed over the transistor structures109A and109B. For example, the conductive lines133may be formed over and electrically connected to the backside vias130(e.g., the backside via130A). In addition, the conductive vias134and the conductive lines135may be formed over and electrically connected to the conductive lines133using single damascene processes or a dual damascene process. Forming backside gate vias164may be formed before, after, or simultaneously with the conductive vias134. Similarly as discussed above, the conductive vias134may be formed in the second dielectric layer132B, for example, by patterning recesses in the second dielectric layer132B using a combination of photolithography and etching processes. Similarly, the backside gate vias164may include patterning recesses in the second dielectric layer132B that further extend through the second dielectric layer132A, the STI region68, and the gate dielectric100. In addition, recesses for the conductive lines135may be patterned into the second dielectric layer132B. The conductive vias134, the backside gate vias164, and the conductive lines135are then formed by depositing a conductive material in the recesses as discussed above. As a result, the backside gate vias164couple the gate electrodes102to the conductive lines135. In accordance with other embodiments, a single damascene process is performed such that the conductive vias134and the backside gate vias164are formed before the second dielectric layer132B is patterned to form the conductive lines135. In some embodiments in which the conductive vias and the backside gate vias164are formed before the conductive lines135, a second dielectric layer132C may be deposited over the second dielectric layer132B and patterned to form the conductive lines135. As discussed above, the conductive lines135of the backside interconnect structure140comprise the signal line135S, which is the portion of the conductive lines135that may complete the drain to gate signal connection between the epitaxial source/drain region92A of the first transistor structure109A and the gate electrode102B of the second transistor structure109B. As a result, the epitaxial source/drain region92A and the gate electrode102B are electrically connected to one another through the backside via130, the conductive line133, the conductive via134, the signal line135S, and the backside gate via164. As illustrated, the conductive via134and the backside gate via164may each be directly coupled to the signal line135S. Although not specifically illustrated, the remainder of the backside interconnect structure140, the UBMs146, and the external connectors148may be formed as described above to complete the integrated circuit for other routing and other devices. FIGS.32A through32Hillustrate schematic cross-sections and plan views of an array of transistor structures109electrically connected to a front-side interconnect structure120and a backside interconnect structure140through the epitaxial source/drain regions92. Note that some details have been omitted from the cross-sections and plan views to emphasize other features and for ease of illustration. In addition, for the sake of emphasis, sizes and shapes of some features illustrated inFIGS.32A through32Hmay differ from the sizes and shapes of those analogous features in other figures. However, like reference numerals indicate like elements are formed using like processes as discussed above. FIG.32Aillustrates a cross-section X-X′, which is a version of cross-section B-B′ discussed above, of a first epitaxial source/drain region92A and a second epitaxial source/drain region92B, andFIG.32Billustrates a cross-section Y-Y′, which is another version of cross-section B-B′ discussed above, of a third epitaxial source/drain region92C and a fourth epitaxial source/drain region92D.FIGS.32C through32Hillustrate plan views of the epitaxial source/drain regions92from different levels (e.g., level L0, level L1, level LN, level L−1, level L−2, and level L−N, respectively). Corresponding cross-sections X-X′ and Y-Y′ are labeled inFIGS.32C through32Hfor reference. FIGS.32C through32Eillustrate plan views of the front-side interconnect structure120at levels L0, L1, and LN, respectively, over the transistor structures109. Referring toFIG.32C, illustrating a plan view at level L0, the epitaxial source/drain regions92(e.g., the epitaxial source/drain regions92A/92B/92C/92D) are formed on opposing sides of a gate electrode102to form parts of the transistor structures109. For example, the first epitaxial source/drain region92A and the third epitaxial source/drain region92C may be disposed on opposing sides of a first gate electrode102, and the second epitaxial source/drain region92B and the fourth epitaxial source/drain region92D may also be disposed on opposing sides of the first gate electrode102. FIG.32Dillustrates a plan view at the levels L0and L1, wherein level L1includes source/drain contacts112electrically connecting the epitaxial source/drain regions92to the front-side interconnect structure120and a gate contact114electrically connecting the gate electrode102to the front-side interconnect structure120. Other features that compose level L1such as the second ILD106have been omitted to provide a clearer view of level L0. FIG.32Eillustrates a plan view at the levels L0, L1, and LN, wherein level LNrepresents one or more layers of the front-side interconnect structure120while omitting some details of the specific routing. The first conductive features122may be directly coupled to the underlying source/drain contacts112or indirectly coupled through other features electrically interposed therebetween. The first conductive features122may further comprise dummy first conductive features122D. Although three functional first conductive features122are illustrated, a person of ordinary skill would understand that the epitaxial source/drain regions92may be electrically connected through the source/drain contacts112to more or fewer than those three functional first conductive features122in the front-side interconnect structure120. Each of the three first conductive features122may be electrically connected to deliver signals to the epitaxial source/drain regions92. FIGS.32F through32Hillustrate plan views of the backside interconnect structure140at levels L−1, L−2, and L−N, respectively, over the transistor structures109.FIG.32Fillustrates a plan view at the levels L0and L−1, wherein level L−1includes backside vias130electrically connected to each of the epitaxial source/drain regions92. Other features that may compose level L−1such as the STI regions68have been omitted in order to provide a clearer view of level L0. FIG.32Gillustrates a plan view at the levels L0, L−1, and L−2, wherein level L−2includes the conductive lines133electrically connected to the backside vias130. Other features that compose level L−2such as the second dielectric layer132A have been omitted in order to provide a clearer view of levels L−1and L0. FIG.32Hillustrates a plan view at the levels L0, L−1, L−2, and L−N, wherein level L−Nincludes one or more additional layers of the conductive lines (e.g., the conductive lines135), such as the signal lines135S and the power rails135P, which are electrically connected to the conductive lines133through the conductive vias134(not separately illustrated). Other features that compose level L−Nsuch as the second dielectric layer132B have been omitted in order to provide a clearer view of levels L−2, L−1, and L0. As illustrated inFIGS.32A and32H, the first epitaxial source/drain region92A and the second epitaxial source/drain region92B may be coupled through the backside interconnect structure140to the power rail135P, which may be coupled to VDDor VSSvoltage sources through, for example, external connectors148(not separately illustrated). In addition, the third epitaxial source/drain region92C and the fourth epitaxial source/drain region92D may be coupled through the backside interconnect structure140to the signal lines135S, which may be coupled through the backside interconnect structure140to other devices of the integrated circuit die, as discussed above. FIGS.33A through34Cillustrate additional examples for electrically connecting an array of transistor structures109to signal lines and power rails through the backside interconnect structure140. For example,FIGS.33A through33Cillustrate a drain to drain to drain signal connection through the backside interconnect structure140by coupling devices of the same conductivity type (e.g., PMOS devices or NMOS devices) to one another, andFIGS.34A through34Cillustrate a drain to drain signal connection through a backside interconnect structure140by coupling devices of opposite conductivity types (e.g., a PMOS device to an NMOS device). Note that some or all of the layouts illustrated inFIGS.33A through34Cmay be formed within the same integrated circuit die. FIG.33Aillustrates a plan view of an array of transistor structures109and the front-side interconnect structure120, andFIG.33Billustrates a plan view of the array of transistor structures109and the backside interconnect structure140. Among the various conductive features, the front-side interconnect structure120comprises a zener diode170coupling two transistor structures109of opposite conductivity types to form a p-n junction (e.g., an n-type and a p-type).FIG.33Cillustrates a circuit layout for the transistor structures109depicted inFIGS.33A and33B, including the power rails135P/VDD and135P/VSS and the signal lines (e.g., the first conductive features122and the signal lines135S) through the front-side interconnect structure120and the backside interconnect structure140. As illustrated inFIGS.33B and33C, a first epitaxial source/drain region92A, a second epitaxial source/drain region92B, and a third epitaxial source/drain region92C (indicated with arrows as the regions covered by other features described herein) may be coupled to one another through the backside interconnect structure140. In particular, backside vias130couple the epitaxial source/drain regions92A/92B/92C to conductive lines133, and conductive vias134couple those conductive lines133to the signal line135S. As further illustrated, through the backside interconnect structure140, a fourth epitaxial source/drain region92X, a fifth epitaxial source/drain region92Y, and a sixth epitaxial source/drain region92Z are coupled to power rails135P of the conductive lines135. In particular, the fourth epitaxial source/drain region92X is coupled to the positive voltage power rail135P/VDD, while the fifth epitaxial source/drain region92Y and the sixth epitaxial source/drain region92Z are coupled to the ground voltage power rail135P/VSS. FIG.34Aalso illustrates a plan view of an array of transistor structures109and the front-side interconnect structure120, andFIG.34Billustrates a plan view of the array of transistor structures109and the backside interconnect structure140. Among the various conductive lines, the backside interconnect structure140comprises a zener diode170coupling two transistor structures109of opposite conductivity types to form a p-n junction.FIG.34Cillustrates a circuit layout for the transistor structures109depicted inFIGS.34A and34B, including the power rails135P/VDD and135P/VSS and the signal lines (e.g., the first conductive features122and the signal lines135S) through the front-side interconnect structure120and the backside interconnect structure140. As illustrated inFIGS.34B and34C, a first epitaxial source/drain region92A and a second epitaxial source/drain region92B (indicated with arrows as the regions covered by other features described herein) may be coupled to one another through the backside interconnect structure140. In particular, backside vias130couple those epitaxial source/drain regions92A/92B to conductive lines133, and conductive vias134couple those conductive lines133to the signal line135S (e.g., the zener diode170). As further illustrated, through the backside interconnect structure140, a third epitaxial source/drain region92X, a fourth epitaxial source/drain region92Y, and a fifth epitaxial source/drain region92Z are coupled to the power rails135P of the conductive lines135. In particular, the third epitaxial source/drain region92X is coupled to the positive voltage power rail135P/VDD, while the fourth epitaxial source/drain region92Y and the fifth epitaxial source/drain region92Z are coupled to the ground voltage power rail135P/VSS. In a transistor array that is electrically connected to the front-side interconnect structure120and the backside interconnect structure140, the transistor structures109(e.g., the epitaxial source/drain regions92and/or the gate electrodes102) may be routed in a variety of pathways not specifically described or illustrated herein. A person of ordinary skill in the art would recognize the many variations for coupling the front-side interconnect structure120and the backside interconnect structure140to coordinate power lines and signal lines to the transistor structures109. Embodiments may achieve advantages. For example, including signal lines and power lines in the backside interconnect structure allows for more versatility in the integrated circuit connections through both the front-side interconnect structure and the backside interconnect structure, which improves device performance. In particular, wider conductive lines and conductive features may increase the reliability and throughput of the electrical signals. In addition, routing the backside interconnect structure to the signal lines through a signal region and to the power rails through a power region, as described above, improves performance of the device by minimizing parasitic capacitance between the regions. Further, forming one or more levels of conductive lines before forming the signal lines and the power rails increases the complexity of routing and circuit density of the backside interconnect structure. As a result of these benefits, semiconductor devices may be formed in a smaller area and with increased density. In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via. In another embodiment, the method further includes forming a third conductive line over the first backside via, the third conductive line electrically connecting the first backside via and the first conductive line; and forming a fourth conductive line over the second backside via, the fourth conductive line electrically connecting the second backside via and the second conductive line. In another embodiment, the first conductive line is electrically connected to a source/drain region of the first transistor, and wherein the second conductive line is electrically connected to a source/drain region of the second transistor. In another embodiment, the method further includes forming a third transistor over the first substrate, a gate structure of the third transistor being electrically connected to the second conductive line. In another embodiment, the method further includes forming a third transistor over the first substrate, a source/drain region of the third transistor being electrically connected to the second conductive line. In another embodiment, the method further includes forming a third conductive line over the first backside via, the third conductive line being electrically interposed between the first backside via and the second conductive line. In another embodiment, the method further includes forming a fourth conductive line over the first conductive line, the fourth conductive line electrically connected to the first transistor. In another embodiment, the method further includes forming an under bump metallurgy (UBM) over the fourth conductive line; and forming an external connector over the UBM. In an embodiment, a semiconductor device includes a power rail embedded in a first dielectric layer; a conductive signal line embedded in the first dielectric layer; a second dielectric layer disposed over the first dielectric layer; a first backside via disposed over and electrically connected to the power rail; a first transistor disposed over and electrically connected to the first backside via; a first gate contact disposed over and electrically connected to a first gate electrode of the first transistor; a second backside via disposed over and electrically connected to the conductive signal line; and a second transistor disposed over and electrically connected to the second backside via. In another embodiment, the first backside via is electrically connected to a first source/drain region of the first transistor. In another embodiment, the second backside via is electrically connected to a second source/drain region of the second transistor. In another embodiment, the semiconductor device further includes a third backside via disposed over and electrically connected to the conductive signal line; and a third transistor disposed over and electrically connected to the third backside via. In another embodiment, the semiconductor device further includes a third via embedded in the second dielectric layer, the third via disposed over and electrically connected to the conductive signal line; and a third conductive line electrically connecting the third via and the third backside via. In another embodiment, a source/drain region of the first transistor is electrically connected to a gate electrode of the third transistor. In another embodiment, a source/drain region of the first transistor is electrically connected to a source/drain region of the third transistor. In another embodiment, the source/drain region of the first transistor and the source/drain region of the third transistor are on opposite sides of the conductive signal line. In an embodiment, a semiconductor device includes a first transistor and a second transistor disposed over a first interconnect structure; a first via disposed over and electrically connected to the first transistor; a second via disposed over and electrically connected to the second transistor; and a second interconnect structure disposed over the first transistor and the second transistor, the second interconnect structure includes a first conductive line embedded in a first dielectric layer, the first conductive line electrically connected to the first via; a second conductive line embedded in the first dielectric layer, the second conductive line electrically connected to the second via; a second dielectric layer disposed over the first dielectric layer; a power rail embedded in the second dielectric layer, the power rail electrically connected to the first conductive line; and a conductive signal line embedded in the second dielectric layer, the conductive signal line electrically connected to the second conductive line. In another embodiment, the semiconductor device further includes a third transistor; a third via disposed over and electrically connected to the third transistor; and a fourth conductive line embedded in the first dielectric layer, the fourth conductive line electrically connected to the conductive signal line. In another embodiment, the semiconductor device further includes a fourth transistor; a fourth via disposed over and electrically connected to the fourth transistor; and a fifth conductive line embedded in the first dielectric layer, the fifth conductive line electrically connected to the conductive signal line. In another embodiment, a source/drain region of the first transistor, a source/drain region of the third transistor, and a source/drain region of the fourth transistor are electrically connected. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 106,644 |
11862562 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some embodiments, a CFET has a first-type transistor stacked with a second-type transistor. Additionally or alternatively, the first-type transistor has a channel region in a first-type active-region semiconductor structure, and the second-type transistor has a channel region in a second-type active-region semiconductor structure. In some embodiments, the transistor stack includes a front-side conductive layer above the CFET transistors and a back-side conductive layer below the CFET transistors. Additionally or alternatively, the CFET performance improves based upon the positioning of a power conductive line, signal conductive lines, and a shielding conductive line, in one or more embodiments. In some embodiments, the power connections to the CFET are improved with reduced resistance between the CFET and the power conductive lines based on the increased size of the power conductive line. Additionally or alternatively, the front-side shielding conductive line in the front-side conductive layer and back-side shielding conductive line in the back-side conductive layer alleviates some restrictions on the pitch of the IC device, in one or more embodiments. In some embodiments, signal shielding for the front-side signal conductive lines are improved by the front-side shielding conductive line and inter-CFET signal shielding is improved by the back-side shielding conductive lines. In some embodiments, a CFET includes an asymmetric front-side and back-side arrangement of power conductive lines, signal conductive lines, and shielding conductive lines. Additionally or alternatively, a CFET includes a structure that provides sufficient power, signal and shielding routing resources for one or more cells (e.g., a Scan D Flip-flop) to be fabricated at a more flexible pitch, in one or more embodiments. In some embodiments, two or more structures include a shielding conductive line and/or a routing resource conductive line. Additionally or alternatively, power conductive lines are shared and the width is increased (i.e., to reduce resistivity), in one or more embodiments. In some embodiments, the cell height of the CFET (including front-side and back-side power, signal and shielding conductive lines) does not increase with the addition of additional shielding conductive lines and/or routing resource conductive lines to the front-side and/or back-side and the arrangement of transistors in the stacked transistor structure is maintained (e.g., reducing redesign costs). Additionally or alternatively, the CFET structure includes one power conductive line, two signal conductive lines, and one shielding conductive line on the front-side of a substrate where the power and shielding conductive line is shared between one or more neighboring stacked transistors. In some embodiments, one power conductive line and two signal conductive lines are on the back-side of the substrate where the bottom power conductive line is not shared with the top transistor, but the power conductive line is close to a cell boundary and configured to be shared with another bottom transistor in a neighboring cell. Additionally or alternatively, the power conductive lines act as a natural shielding for signal cross talk. In some embodiments, at least three separate methods for signal connection between the first-type transistor and the second-type transistor are disclosed below offering circuit design flexibility. Additionally or alternatively, the methods include 1) a source terminal/drain terminal connection or interconnect (also referred to as “MDLI”) between source terminal/drain terminals of the stacked transistors; 2) a gate connection between the gates of the stacked transistors; and 3) a via from top to bottom (VTB) between a source terminal/drain terminal of a top transistor in the stacked transistor structure and a metal layer on the back-side of the CFET structure. In accordance with some embodiments,FIG.1Ais a schematic perspective view of a circuit structure100A (also referred to herein as a “cell”), implemented with a CFET, that includes power conductive line107A, signal conductive lines109A,109B (hereinafter referred to as signal conductive lines109), and a shielding conductive line112A in a front-side conductive layer105A. Additionally or alternatively, while some embodiments are discussed with reference to an inverter circuit structure, another IC device, transistor stack or cell is between a front-side metal layer and a back-side metal layer. In some embodiments, a circuit structure100A includes a substrate (not shown inFIG.1A, but corresponding to, e.g., substrate260inFIG.2C), and a first transistor stack101over the substrate. The first transistor stack101comprises a first transistor102which is a first conductivity type, and a second transistor104, which is above first transistor102and is a second conductivity type different from the first conductivity type. Circuit structure100A also includes a plurality of first conductive lines103A in a first metal layer105A above first transistor stack101. A plurality of first conductive lines103A over first transistor stack101includes a power conductive line107A configured to route power to first transistor stack101, one or more signal conductive lines109configured to route signals to first transistor stack101, and a shielding conductive line112A configured to shield the routed signals on one or more signal conductive lines109, where one or more signal conductive lines109are between power conductive line107A and shielding conductive line112A. In some embodiments, circuit structure100A is an inverter circuit structure that implements a logical negation. Additionally or alternatively, circuit structure100A, or the like, is a basic building block in digital electronics. In some embodiments, circuit structure100A is implemented in multiplexers, decoders, state machines, flip-flops, or other sophisticated digital devices and the like. In some embodiments, first transistor stack101is a CFET. Additionally or alternatively, first transistor stack101is constructed in such a way that a P-type transistor includes an input from a voltage source or VDD. Additionally or alternatively, first transistor stack101includes an N-type transistor that includes an input from VSS or ground. In some embodiments, transistor stack101complements every N-type transistor with a P-type transistor. Additionally or alternatively, high voltage on the gates will cause the N-type transistor to conduct and the P-type transistor not to conduct, while a low voltage on the gates causes an opposite behavior. In some embodiments, the outputs of the P-type and N-type transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, in some embodiments, the CMOS circuit output is the inverse of the input. In some embodiments, second transistor104is a PMOS (P-channel metal-oxide semiconductor field-effect transistor) active device. Additionally or alternatively, first transistor102is an NMOS (N-channel metal-oxide semiconductor filed effect transistor) active device. In some embodiments, second transistor104and first transistor102include a gate terminal (e.g., metal or polycrystalline silicon), oxide insulation and a semiconductor, such as silicon. In some embodiments, first metal layer105A including first conductive lines103A that includes power conductive line107A, signal conductive lines109, and shielding conductive line112A, second conductive lines118that includes power conductive line120and signal conductive lines132A,132B (hereinafter referred to as signal conductive lines132), and vias (122A,124A,126,134,128A,136) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive line112A is a floating conductive line or shielding conductive line112A is connected to a reference voltage (e.g., VDD, VSS or another voltage on circuit100A). Additionally or alternatively, shielding conductive line112A shields, prevents and/or reduces signal interference or signal cross-talk between signals on signal conductive lines109A,109B and signals on other neighboring circuit structures or cells. In some embodiments, circuit structure100A includes a first transistor102, an NMOS device, and a second transistor104, a PMOS device. First transistor102is sometimes referred to as a “bottom device” or “bottom transistor,” and second transistor104is sometimes referred to as a “top device” or “top transistor.” Additionally or alternatively, gate terminals110B,110A (hereinafter referred to as gate terminal110) of first transistor102and second transistor104are electrically connected together by a gate connection131, while functioning as an input terminal receiving a signal, through a top gate via122A (also referred to as via-to-gate, or VG), from signal conductive line109A. In at least one embodiment, gate connection131is omitted. In some embodiments, a bottom VG via (not shown) is provided to couple gate terminal110B of the bottom device, i.e., first transistor102, to a signal conductive line132A,132B on the metal layer116. An example of a bottom VG via is described with respect toFIG.1E. In some embodiments, drain terminals130A,130B (hereinafter referred to as drain terminals130) of second transistor104and first transistor102are connected together by an MDLI138, while functioning as an output terminal outputting a signal, through via134(also referred to as VTB or via top to bottom), to signal conductive line132B. In at least one embodiment, a similar MDLI is provided between source terminal114A of second transistor104and source terminal114B of first transistor102. In one or more embodiments, either or both of the described MDLI is/are omitted. Additionally or alternatively, drain terminal130A of second transistor104is maintained at the supply voltage VDD through top VD via128A electrically connected to power conductive line107A, and source terminal114B of first transistor102is maintained at the supply voltage VSS through via140(not shown inFIG.1Abut indicated inFIG.1E) electrically connected to power conductive line120. Source terminals/drain terminals are also referred to as metal-to-device (MD) contact structures. The described “source terminal” and/or “drain terminal” are examples, and can be reversed as “drain terminal” and/or “source terminal” in one or more embodiments. In some embodiments, circuit structure100A includes a P-type active-region semiconductor structure106and an N-type active-region semiconductor structure108extending in the X-direction. Additionally or alternatively, the X-direction, the Y-direction, and the Z-direction, inFIG.1Aand other FIGS. throughout the disclosure are mutually orthogonal to each other and form an orthogonal coordinate frame. In some embodiments, P-type active-region semiconductor structure106is stacked with N-type active-region semiconductor structure108along the Z-direction. Additionally or alternatively, gate terminal110extending in the Y-direction intersects both P-type active-region semiconductor structure106and N-type active-region semiconductor structure108. In some embodiments, gate terminal110functions as two stacked gate terminals110A,110B, conductively joined together: one gate terminal110A intersects P-type active-region semiconductor structure106at a channel region of second transistor104, and another gate terminal110B intersects N-type active-region semiconductor structure108at a channel region of first transistor102. Additionally or alternatively, gate terminal110A of second transistor104is conductively connected to gate terminal110B of first transistor102through gate connection131. In some embodiments, each of P-type active-region semiconductor structure106and N-type active-region semiconductor structure108includes one or more nano-sheets, and consequently, each of second transistor104and first transistor102is a nano-sheet transistor. Additionally or alternatively, each of P-type active-region semiconductor structure106and N-type active-region semiconductor structure108includes one or more nano-wires, and consequently, each of second transistor104and first transistor102is a nano-wire transistor. In some embodiments, circuit structure100A includes conductive segments including source terminals114and drain terminals130. Additionally or alternatively, each of source terminal114and drain terminal130, extend in the Y-direction and intersect P-type active-region semiconductor structure106of second transistor104. In some embodiments, each of source terminal114and drain terminal130, extend in the Y-direction and intersect N-type active-region semiconductor structure108of first transistor102. Additionally or alternatively, drain terminal130A and drain terminal130B are conductively connected through MDLI138. In some embodiments, source terminal114A of second transistor104is conductively connected to front-side signal conductive line109B through a top via124A, and source terminal114B of the first transistor102is conductively connected to back-side power conductive line120through a bottom via (VB)140(FIG.1E). Additionally or alternatively, front-side power conductive line107A is configured to be held at a first supply voltage VDD, and back-side power conductive line120is configured to be held at a second supply voltage VSS. In some embodiments, front-side power conductive line107A extends in the X-direction in front-side metal layer105A. Additionally or alternatively, back-side power conductive line120extends in the X-direction in back-side metal layer116. In some embodiments, each of front-side metal layer105A and the back-side metal layer116is in a plane having the normal vector orientated towards the Z-direction. Additionally or alternatively, front-side metal layer105A is above both P-type active-region semiconductor structure106and N-type active-region semiconductor structure108. In some embodiments, back-side metal layer116is below both P-type active-region semiconductor structure106and N-type active-region semiconductor structure108. Additionally or alternatively, back-side metal layer116is fabricated on a substrate (260FIG.2C) as a buried conductive layer, and, N-type active-region semiconductor structure108is fabricated above the buried conductive layer. In some embodiments, P-type active-region semiconductor structure106is fabricated above N-type active-region semiconductor structure108, and front-side metal layer105A is fabricated above P-type active-region semiconductor structure106. Additionally or alternatively, other arrangements of back-side metal layer116are also discussed in the disclosure (see, e.g.,FIGS.3A-4D). In some embodiments, conductive lines in front-side metal layer105A and conductive lines in back-side metal layer116are asymmetrical to one another. In some embodiments, circuit structure100A includes front-side signal conductive lines109in front-side metal layer105A and also back-side metal layer116includes back-side signal conductive lines132. Additionally or alternatively, front-side signal conductive line109A is an input signal conductive line for providing an input to gate terminal110A and front-side signal conductive line109B is an output signal conductive line for providing an output through drain terminal130. In some embodiments, front-side signal conductive line109A is conductively connected to gate terminal110A through a top gate via122A and configured as an input signal conductive line of circuit structure100A. In some embodiments, front-side signal conductive line109B is conductively connected to source terminal114A through via124A and configured as an output signal conductive line of circuit structure100A. Additionally or alternatively, back-side signal conductive lines132are configured to route signals between neighboring cells or circuit structures at opposite sides of circuit structure100A. For example, in some embodiments, through VTB134(shown in dotted line as an optional element) connected to drain terminal130A, an output of transistor stack101is routed through signal conductive line132B. In this structure, as discussed above, drain terminal130A of second transistor104is connected, through VTB134, to another transistor outside circuit structure100A, when a gate and/or a source terminal/drain terminal of such another transistor is electrically coupled to the signal conductive line132B. In another example, additionally or alternatively, via136(shown in dotted line as an optional element—also referred to as bottom VD) electrically connects source terminal114B to signal conductive line132B. In this structure, source terminal114B of first transistor102is connected, through bottom VD via136and signal conductive line132B, to another transistor outside circuit structure100A. In yet another example, additionally or alternatively, bottom VD via126(shown in dotted line as an optional element) electrically connects drain terminal130B to power conductive line120to receive, e.g., a VSS voltage. In the example configuration inFIG.1A, signal conductive line132B includes two disconnected sections aligned along the X direction. However, in at least one embodiment, the two sections are continuous and signal conductive line132B extends continuously from under drain terminal130A to under source terminal114B. In at least one embodiment, drain terminal130A is electrically coupled to source terminal114B through VTB134, continuous signal conductive line132B, and bottom VD via136. In some embodiments, one or more other signal conductive lines described herein (e.g.,109A,109B,132A) comprises aligned but disconnected sections as exemplarily illustrated for signal conductive line132B inFIG.1A. In accordance with some embodiments,FIG.1Bis a schematic perspective view of a circuit structure100B (also referred to herein as a “cell”) having power conductive line107B, signal conductive lines109C,109D, and shielding conductive line112B in a front-side conductive layer105B. In some embodiments, a circuit structure100B includes a substrate (260FIG.2C) that includes a first transistor stack101over the substrate where a first transistor102is a first conductivity type, and a second transistor104, above first transistor102, where second transistor104is a second conductivity type different from the first conductivity type. Circuit structure100B also includes a plurality of first conductive lines103B in a first metal layer105B above first transistor stack101. A plurality of first conductive lines103B over first transistor stack101includes a power conductive line107B configured to route power to first transistor stack101, one or more signal conductive lines109C,109D (hereinafter referred to as signal conductive lines109E) configured to route signals to first transistor stack101, and a shielding conductive line112B configured to shield the routed signals on one or more signal conductive lines109E, where one or more signal conductive lines109E are between power conductive line107B and shielding conductive line112B. In some embodiments, circuit structures100A and100B are alike in back-side metal layer116and transistor stack101. Compared to circuit structure100A, circuit structure100B does not include a via connection from front-side metal layer105B to drain terminal130A, via122B is electrically connected to front-side signal conductive line109D, and gate terminal110A and via128B are electrically connected to front-side power conductive line107B and source terminal114A. In some embodiments, circuit structure100B is like circuit structure100A and includes front-side signal conductive lines109C,109D in front-side metal layer105B and also back-side metal layer116having back-side signal conductive lines132which are asymmetrical to front-side signal conductive lines109C,109D. Additionally or alternatively, front-side signal conductive line109D is conductively connected to gate terminal110A through top gate via122B and configured as an input signal conductive line of circuit structure100B. In some embodiments, back-side signal conductive line132B is conductively connected to drain terminal130A through VTB134and configured as an output signal conductive line of circuit structure100B. In some embodiments, first metal layer105B including first conductive lines103B that includes power conductive line107B, signal conductive lines109C,109D, and shielding conductive line112B, second conductive lines118that includes power conductive line120and signal conductive lines132A,132B (hereinafter referred to as signal conductive lines132), and vias (122B,126,134,128B,136) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive line112B is a floating conductive line or shielding conductive line112B is connected to a reference voltage (e.g., VDD, VSS or any voltage on circuit100B). Additionally or alternatively, shielding conductive line112B shields, prevents and/or reduces signal interference or signal cross-talk between signals on signal conductive lines109C,109D and signals on other neighboring circuit structures or cells. In some embodiments, circuit structure100B includes a first transistor102, an NMOS device, and a second transistor104, a PMOS device. First transistor102is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor104is sometimes referred to as “top device” or “top transistor.” Additionally or alternatively, gate terminals110B,110A (hereinafter referred to as gate terminal110) of first transistor102and second transistor104are electrically connected together by a gate connection131, while functioning as an input terminal receiving a signal, through a top gate via122B (also referred to as via-to-gate, or VG), from signal conductive line109D. In at least one embodiment, gate connection131is omitted. In some embodiments, a bottom VG via (not shown) is provided to couple gate terminal110B of the bottom device, i.e., first transistor102, to a signal conductive line132A,132B on the metal layer116. An example of a bottom VG via is described with respect toFIG.1E. In some embodiments, drain terminals130A,130B (hereinafter referred to as drain terminals130) of second transistor104and first transistor102are connected together by an MDLI138, while functioning as an output terminal outputting a signal, through via134(also referred to as VTB, or via top to bottom), to signal conductive line132B. In at least one embodiment, a similar MDLI is provided between source terminal114A of second transistor104and source terminal114B of first transistor102. In one or more embodiments, either or both of the described MDLI is/are omitted. Additionally or alternatively, source terminal114A of second transistor104is maintained at the supply voltage VDD through top VD via128B electrically connected to power conductive line107A, and source terminal114B of first transistor102is maintained at the supply voltage VSS through bottom via140(not shown inFIG.1Abut indicated inFIG.1E) electrically connected to power conductive line120. Source terminals/drain terminals are also referred to as metal-to-device (MD) contact structures. The described “source terminal” and/or “drain terminal” are examples, and can be reversed as “drain terminal” and/or “source terminal” in one or more embodiments. In some embodiments, circuit structure100B includes a P-type active-region semiconductor structure106and an N-type active-region semiconductor structure108extending in the X-direction. Additionally or alternatively, the X-direction, the Y-direction, and the Z-direction, inFIG.1Band other FIGS. throughout the disclosure are mutually orthogonal to each other and form an orthogonal coordinate frame. In some embodiments, P-type active-region semiconductor structure106is stacked with N-type active-region semiconductor structure108along the Z-direction. Additionally or alternatively, gate terminal110extending in the Y-direction intersects both P-type active-region semiconductor structure106and N-type active-region semiconductor structure108. In some embodiments, gate terminal110functions as two stacked gate terminals110A,110B, conductively joined together: one gate terminal110A intersects P-type active-region semiconductor structure106at a channel region of second transistor104, and another gate terminal110B intersects N-type active-region semiconductor structure108at a channel region of first transistor102. Additionally or alternatively, gate terminal110A of second transistor104is conductively connected to gate terminal110B of first transistor102through gate connection131. In some embodiments, each of P-type active-region semiconductor structure106and N-type active-region semiconductor structure108includes one or more nano-sheets, and consequently, each of second transistor104and first transistor102is a nano-sheet transistor. Additionally or alternatively, each of P-type active-region semiconductor structure106and N-type active-region semiconductor structure108includes one or more nano-wires, and consequently, each of second transistor104and first transistor102is a nano-wire transistor. In some embodiments, circuit structure100B includes conductive segments including source terminals114and drain terminals130. Additionally or alternatively, each of source terminal114and drain terminal130, extend in the Y-direction and intersect P-type active-region semiconductor structure106of second transistor104. In some embodiments, each of source terminal114and drain terminal130, extend in the Y-direction and intersect N-type active-region semiconductor structure108of first transistor102. Additionally or alternatively, drain terminal130A and drain terminal130B are conductively connected through MDLI138. In some embodiments, source terminal114A of second transistor104is conductively connected to front-side power conductive line107B through a top via128B, and source terminal114B of the first transistor102is conductively connected to back-side power conductive line120through a bottom via140(FIG.1E). Additionally or alternatively, front-side power conductive line107B is configured to be held at a first supply voltage VDD, and back-side power conductive line120is configured to be held at a second supply voltage VSS. In some embodiments, front-side power conductive line107B extends in the X-direction in front-side metal layer105B. Additionally or alternatively, back-side power conductive line120extends in the X-direction in back-side metal layer116. In some embodiments, each of front-side metal layer105B and the back-side metal layer116is in a plane having the normal vector orientated towards the Z-direction. Additionally or alternatively, front-side metal layer105B is above both P-type active-region semiconductor structure106and N-type active-region semiconductor structure108. In some embodiments, back-side metal layer116is below both P-type active-region semiconductor structure106and N-type active-region semiconductor structure108. Additionally or alternatively, back-side metal layer116is fabricated on a substrate (260FIG.2C) as a buried conductive layer, and, N-type active-region semiconductor structure108is fabricated above the buried conductive layer. In some embodiments, P-type active-region semiconductor structure106is fabricated above N-type active-region semiconductor structure108, and front-side metal layer105B is fabricated above P-type active-region semiconductor structure106. Additionally or alternatively, other arrangements of back-side metal layer116are also discussed in the disclosure (see, e.g.,FIGS.3A-4D). In some embodiments, conductive lines in front-side metal layer105B and conductive lines in back-side metal layer116are asymmetrical to one another. In some embodiments, circuit structure100B includes front-side signal conductive lines109C,109D in front-side metal layer105B and also back-side metal layer116includes back-side signal conductive lines132. In some embodiments, front-side signal conductive line109D is conductively connected to gate terminal110A through a top gate via122B and configured as an input signal conductive line of circuit structure100B. Additionally or alternatively, back-side signal conductive lines132are configured to route signals between neighboring cells or circuit structures at opposite sides of circuit structure100B. For example, in some embodiments, through VTB134(shown in dotted line as an optional element) connected to drain terminal130A, an output of transistor stack101is routed through signal conductive line132B. In this structure, as discussed above, drain terminal130A of second transistor104is connected, through VTB134, to another transistor outside circuit structure100B, when a gate and/or a source terminal/drain terminal of such another transistor is electrically coupled to the signal conductive line132B. In another example, additionally or alternatively, via136(shown in dotted line as an optional element—also referred to as bottom VD) electrically connects source terminal114B to signal conductive line132B. In this structure, source terminal114B of first transistor102is connected, through bottom VD via136and signal conductive line132B, to another transistor outside circuit structure100B. In yet another example, additionally or alternatively, bottom VD via126(shown in dotted line as an optional element) electrically connects drain terminal130B to power conductive line120to receive, e.g., a VSS voltage. In the example configuration inFIG.1B, signal conductive line132B includes two disconnected sections aligned along the X direction. However, in at least one embodiment, the two sections are continuous and signal conductive line132B extends continuously from under drain terminal130A to under source terminal114B. In at least one embodiment, drain terminal130A is electrically coupled to source terminal114B through VTB134, continuous signal conductive line132B, and bottom VD via136. In some embodiments, one or more other signal conductive lines described herein (e.g.,109C,109D,132A) comprises aligned but disconnected sections as exemplarily illustrated for signal conductive line132B inFIG.1B. In accordance with some embodiments,FIGS.1C,1D, and1Eare layout diagrams of circuit structures configured as inverter circuit structures. In some embodiments,FIG.1Cis a layout diagram of circuit structure100A, specifically front-side metal layer105A and second transistor104in the Z-direction. In some embodiments,FIG.1Dis a layout diagram of circuit structure100B, specifically front-side metal layer105B and second transistor104in the Z-direction. In some embodiments,FIG.1Eis a layout diagram of either circuit structure100A or circuit structure100B, specifically back-side metal layer116and first transistor102in the Z-direction, as the back-side metal layer and first transistor do not change between circuit structures100A and100B. In some embodiments, layout diagrams144,146, and148are inverter circuit structures with a 2 CPP. In some embodiments, CPP is an abbreviation of the term ‘contact poly pitch’. In some embodiments, CPP is the center-to-center distance between adjacent gate patterns corresponding to gate terminals (electrodes) in a semiconductor device produced by a process technology node associated with layout diagrams such as layout diagrams144,146, and148. Additionally or alternatively, H is represented as the height of each of active-region semiconductor structures106,108along the Z-direction as described with respect toFIG.2C. In some embodiments, a cell height, represented as the distance between cell boundary111A and111B, along the Y direction in each of layout diagrams144,146and148is between 5H and 30H. Additionally or alternatively, cell boundary lines111A and111B, together with dummy gate-strip patterns110C (discussed below), act as edges of a cell boundary (also referred to as “place-and-route boundary”) that are placed in abutment with edges of the cell boundaries of neighboring cells. Layout diagrams144,146, and148as well circuit structures100A,100B correspond to cells which have, along the Y direction, one stack of active-region semiconductor structures106,108and are referred to as single cell height cells. Other examples of single cell height cells are described with respect toFIGS.3A-3F. Examples of double cell height cells are described with respect toFIGS.2A-2C,4A-4D,5A-5Bwhich describe cells with two stacks of active-region semiconductor structures along the Y direction. In some embodiments, the layout diagram inFIG.1Cincludes a layout diagram144for a top portion or top device of circuit structure100A, including P-type active-region semiconductor structure106, gate terminal110A, drain terminal130A and source terminal114A, front-side signal conductive lines109A and109B, front-side power conductive line107A, shielding conductive line112A and various vias124A and128A. In some embodiments, the layout diagram inFIG.1Dincludes a layout diagram146for a top portion or top device of circuit structure100B, including P-type active-region semiconductor structure106, gate terminal110A, drain terminal130A and source terminal114A, the front-side signal conductive lines109C and109D, front-side power conductive line107B, shielding conductive line112B and various vias124B and128B. In some embodiments, the layout diagram inFIG.1Eincludes layout diagram148for a bottom portion or bottom device of circuit structure100A or100B, including N-type active-region semiconductor structure108, gate terminal130B, source terminal114B, drain terminal130B, back-side power conductive line120, signal conductive lines132A,132B, MDLI138, and various vias, VSS via140and gate via142. The gate via142is a bottom VG via functionally corresponding to VG via122A inFIG.1A. In some embodiments, one VG via (either VG122A inFIG.1Aor bottom VG142inFIG.1E) is sufficient to electrically couple both gate terminals110A,110B to an input of the inverter, because gate terminals110A,110B are already connected together by gate connection131. In some embodiments, each of P-type active-region semiconductor structure106, N-type active-region semiconductor structure108, front-side signal conductive lines109,109E, and front-side power conductive line107A,107B, front-side shielding conductive line112A,112B, back-side signal conductive lines132, and back-side power conductive line120are extending in the X-direction. Additionally or alternatively, gate terminal110extends in the Y-direction and intersects P-type active-region semiconductor structure106at a channel region of second transistor104. In some embodiments, source terminal114extends in the Y-direction and intersects P-type active-region semiconductor structure106at a channel region of second transistor104. Additionally or alternatively, drain terminal130extends in the Y-direction and intersects P-type active-region semiconductor structure106at a channel region of second transistor104. In some embodiments, via128A,128B electrically connects corresponding source terminal114A and front-side power conductive line107A,107B. Additionally or alternatively, via142electrically connects gate terminal110B and back-side signal conductive line132B. In some embodiments, each of N-type active-region semiconductor structure108, the back-side signal conductive lines132, and back-side power conductive line120extend in the X-direction. Additionally or alternatively, gate terminal110extends in the Y-direction and intersects N-type active-region semiconductor structure108at a channel region of first transistor102. In some embodiments, source terminal114B extends in the Y-direction and intersects N-type active-region semiconductor structure108. Additionally or alternatively, drain terminal130B extends in the Y-direction and intersects N-type active-region semiconductor structure108at a channel region of first transistor102. In some embodiments, via140provides electrical connection between source terminal114B and back-side power conductive line120. In some embodiments,FIGS.1C,1D, and1Ealso include dummy gate-strip patterns110C at the edges of layout diagrams144,146,148. In some embodiments, the intersections between dummy gate-strip patterns110C and the layout diagram of P-type active-region semiconductor structure106are for isolating P-type active-region semiconductor structure106from active-regions in neighboring cells. Additionally or alternatively, the intersections between dummy gate-strip patterns110C and the layout diagram of N-type active-region semiconductor structure108isolate N-type active-region semiconductor structure108from active-regions in neighboring cells. In some embodiments, the isolation regions in active-region semiconductor structures106,108are created based on the poly on oxide definition edge (PODE) technology or based on the continuous poly on oxide definition edge (CPODE) technology. Additionally or alternatively, other suitable technologies for generating the isolation regions in active-region semiconductor structures106,108are also within the contemplated scope of present disclosure. In some embodiments, the cell height of layout diagrams144,146, and148does not change with the addition of shielding conductive line112A,112B. Additionally or alternatively, shielding conductive line112A,112B is added to front-side conductive layer105A,105B. Additionally or alternatively, a wide power conductive line lowers resistance and Joule heating. In some embodiments, a wide power conductive line allows for a merged or shared power conductive line with abutting stacked cells. Additionally or alternatively, a single shielding conductive line is shared with adjacent stacked cells. In some embodiments, as is discussed below in greater detail, when vertical abutting (i.e., abutting along the Y-direction) of stacked transistor cells is implemented, sharing a common power conductive line and/or a common shielding conductive line is achieved between top transistors of abutting cells. Additionally or alternatively, inFIGS.1C and1D, each of power conductive line107A and107B has a length of overhang154that extends outside of layout diagrams144and146. In some embodiments, layout diagrams144and146have a certain amount of overhang156from shielding conductive lines112A and112B. Additionally or alternatively, each of overhangs154and156provides for electrical connections to adjoining cells for the sharing of power conductive lines107A,107B or shielding conductive lines112A,112B. In some embodiments, the aspect of a common power conductive line or a common shielding conductive line are discussed in greater detail below. Additionally or alternatively, power conductive line120inFIG.1Eadditionally has a back-side overhang158. In some embodiments, back-side overhang158is used to couple power to one or more other first/bottom transistors of one or more adjoining/abutting cells. In accordance with some embodiments,FIG.2Ais a schematic perspective view of a circuit structure200C that combines a top cell circuit structure200A and a bottom cell circuit structure200B at a common power conductive line207A. Additionally or alternatively, power conductive line207A of first transistor stack201A extends partially over second transistor stack201B and is configured to route power to both first transistor stack201A and second transistor stack201B. Circuit structure200A abuts or adjoins circuit structure200B in the Y-direction. Circuit structure200A is arranged further towards a positive orientation of the Y direction than circuit structure200B, and is referred to as “top cell” or “top cell circuit structure.” Thus, circuit structure200B is referred to as “bottom cell” or “bottom cell circuit structure.” In some embodiments, circuit structure200C corresponds to a double cell height cell. In some embodiments, a circuit structure200C includes a substrate (260FIG.2C) that includes a first transistor stack201A and a second transistor stack201B over the substrate where first transistors202A,202B are a first conductivity type, and second transistors204A,204B are above corresponding first transistors202A,202B, where second transistors204A,204B are a second conductivity type different from the first conductivity type. Circuit structure200C also includes a plurality of first conductive lines203A in a first metal layer205A above transistor stacks201A,201B. A plurality of first conductive lines203A over transistor stacks201A,201B includes a power conductive line207A configured to route power to transistor stacks201A,201B, one or more signal conductive lines209A,209B,209C,209D (hereinafter referred to as signal conductive lines209) configured to route signals to transistor stacks201A,201B, and one or more shielding conductive lines212A,212B configured to shield the routed signals on one or more signal conductive lines209, where one or more signal conductive lines209are between power conductive line207A and shielding conductive lines212A,212B. In some embodiments, circuit structures200A,200B with transistor stacks201A,201B are like circuit structures100A and100B with transistor stacks101. Additionally or alternatively, circuit structure200C represents a combination of circuit structures200A and200B where circuit structures200A and200B are like circuit structures100A and100B and share a common power conductive line207A that is like power conductive lines107A or107B. In some embodiments, first metal layer205A including first conductive lines203A that includes power conductive line207A, signal conductive lines209, and shielding conductive lines212A,212B, second conductive lines218that includes power conductive lines220A,220B and signal conductive lines232A,232B,232C,232D (hereinafter referred to as signal conductive lines232), and vias (222A,222B,224A,228A,228B) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive lines212A,212B is a floating conductive line or shielding conductive lines212A,212B is connected to a reference voltage (e.g., VDD, VSS or any voltage on circuit200C). Additionally or alternatively, shielding conductive lines212A,212B shields, prevents and/or reduces signal interference or signal cross-talk between signals on signal conductive lines209and signals on other neighboring circuit structures or cells. In some embodiments, circuit structure200C includes first transistors202A,202B, an NMOS device, and second transistors204A,204B, a PMOS device. First transistors202A,202B is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor204A,204B is sometimes referred to as “top device” or “top transistor.” In accordance with some embodiments,FIG.2Bis a schematic perspective view of a circuit structure200F that combines a top cell circuit structure200D and a bottom cell circuit structure200E at a common shielding conductive line212C. Circuit structure200D abuts or adjoins circuit structure200E in the Y-direction. Circuit structure200D is arranged further towards a positive orientation of the Y direction than circuit structure200E, and is referred to as “top cell” or “top cell circuit structure.” Thus, circuit structure200E is referred to as “bottom cell” or “bottom cell circuit structure.” In some embodiments, circuit structure200F corresponds to a double cell height cell. In some embodiments, circuit structures200D,200E with transistor stacks201A,201B are like circuit structures100A and100B with transistor stack101. Additionally or alternatively, circuit structure200F represents a combination of circuit structures200D and200E that are like each of circuit structures100A and100B and share a common shielding conductive line212C that is like shielding conductive line112A or112B. In some embodiments, circuit structure200F includes a substrate (260FIG.2C) that includes a first transistor stack201A and a second transistor stack201B over the substrate where first transistors202A,202B are a first conductivity type. Second transistors204A,204B are above corresponding first transistors202A,202B, where second transistors204A,204B are a second conductivity type different from the first conductivity type. Circuit structure200F also includes a plurality of first conductive lines203B in a first metal layer205B above transistor stacks201A,201B. Plurality of first conductive lines203B over transistor stacks201A,201B includes power conductive lines207B,207C configured to route power to transistor stacks201A, and201B. One or more signal conductive lines209E,209F,209G,209H (hereinafter referred to as signal conductive lines209I) configured to route signals to transistor stacks201A,201B; and one common shielding conductive line212C configured to shield the routed signals on one or more signal conductive lines209I, where one or more signal conductive lines209I are between power conductive lines207B,207C and shielding conductive line212C. In some embodiments, first metal layer205B including first conductive lines203B that includes power conductive lines207B,207C, signal conductive lines209I, and shielding conductive line212C, second conductive lines218that includes power conductive lines220A,220B and signal conductive lines232A,232B,232C,232D (hereinafter referred to as signal conductive lines232), and vias (222C,222D,224B,228C,228D) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive line212C is a floating conductive line or shielding conductive line212C is connected to a reference voltage (e.g., VDD, VSS or any voltage on circuit200F). Additionally or alternatively, shielding conductive line212C shields, prevents and/or reduces signal interference or signal cross-talk between signals on signal conductive lines209I and signals on other neighboring circuit structures or cells. In some embodiments, in a double cell height cell like circuit structure200F, shielding conductive line212C is configured as an internal signal conductive line for routing signals inside the cell. For example, shielding conductive line212C is disconnected at the cell boundary so that signals on shielding conductive line212C stay internal within the cell. In some embodiments, circuit structure200F includes first transistors202A,202B, an NMOS device, and second transistors204A,204B, a PMOS device. First transistors202A,202B is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor204A,204B is sometimes referred to as “top device” or “top transistor.” In accordance with some embodiments,FIG.2Cis a schematic cross-sectional view of circuit structure200G. In some embodiments, circuit structure200G includes a substrate260that includes a first transistor stack201A and a second transistor stack201B over substrate260. In some embodiments, circuit structures200H,200I with transistor stacks201A,201B are like circuit structures100A and100B with transistor stack101. Additionally or alternatively, circuit structure200G represents a combination of circuit structures200H and200I that are like each of circuit structures100A and100B and share a common shielding conductive line212D that is like shielding conductive line112A or112B. In some embodiments, power conductive lines207D,207E have a width262of from 3H to 7H where H is represented as the height of active-region semiconductor structures206A,206B,208A,208B in the Z-direction. Additionally or alternatively, width262of power conductive lines207D,207E reduces the resistance of power conductive lines207D,207E and thus reduces Joule heating within power conductive lines207D,207E. In some embodiments, resistance within a conductor decreases proportionally as the cross-sectional area increases. Additionally or alternatively, Joule heating decreases as resistance decreases. In some embodiments, signal conductive line209M has a width264of from 0.5H and 3H, and the distance266between signal conductive lines232C and232D is from 0.5H and 3H. Additionally or alternatively, transistor stack height268is from 10H and 50H, and cell width270is from 5H and 30H. In some embodiments, circuit structure200G includes conductive segments including source terminals214A,214B,214C and214D and drain terminals (not shown). Additionally or alternatively, each of source terminal214A,214B,214C and214D and the drain terminal, extend in the Y-direction and intersect P-type active-region semiconductor structures206A,206B, of second transistors204A,204B. In some embodiments, each of source terminal214A,214B,214C and214D and the drain terminal, extend in the Y-direction and intersect N-type active-region semiconductor structure208A,208B of first transistors202A,202B. In some embodiments, source terminal214A of second transistor204A is conductively connected to front-side signal conductive line209J through a top via224A, and source terminal214B of the first transistor202A is conductively connected to back-side signal conductive line232A through a bottom via236A. In some embodiments, top devices (or top transistors204A,204B) in abutted cells, such as in circuit structures200H,200I, have front-end features and VTBs (234A,234B) that are stackable (or the same), and have back-end features with a mirror structure. In some embodiments, bottom devices (or bottom transistors202A,202B) in abutted cells, such as in circuit structure200H,200I, have both front-end features and back-end features that are stackable (or the same). Front-end features include features manufactured in front-end-of-line (FEOL) fabrication, and back-end features include features manufactured in back-end-of-line (BEOL) fabrication. Examples of front-end features include PO, CPO, MD and OD features. Examples of back-end features include M0, BM0, VG, VD and CMD features. PO features correspond to where gates are formed, and CPO (cut-PO) features correspond to where gates are disconnected. MD features or MD contact structures correspond to where source terminal/drain terminals as described herein are formed, and CMD (cut-MD) features correspond to where MD contact structures are disconnected. OD features correspond to active regions (or active-region semiconductor structures). M0 features correspond to conductive patterns in a metal zero (M0) layer. In at least one embodiment, the conductive lines207D,209J,209K,212D,209L,209M and107E over transistor stacks201A,201B are conductive patterns in the M0 layer. BM0 features correspond to conductive patterns in a backside metal zero (BM0) layer. In at least one embodiment, the conductive lines220B,232A,232B,220B,232C, and232D under transistor stacks201A,201B are conductive patterns in the BM0 layer. VG, VB (224A,224B,236A,236B), and VD features correspond to various VG, VB and VD vias described herein. In some embodiments, the front-end features and VTBs of the top transistors, e.g.,204A,204B inFIGS.2A-2B, are stackable (or the same), whereas the back-end features of the top transistors, e.g.,204A,204B inFIGS.2A-2B, have a mirror structure. For example, the conductive lines203B over the top transistor204A and the conductive lines203B over the top transistor204B are symmetrical to one another across a center line of common shielding conductive line212C, as shown inFIGS.2B-2C. In some embodiments, the front-end features and back-end features of the bottom transistors, e.g.,202A,202B inFIGS.2A-2B, are stackable (or the same). For example, the conductive lines216under the bottom transistor202A and the conductive lines216under the bottom transistor202B are the same, as shown inFIGS.2B-2C. In accordance with some embodiments,FIG.3Ais a schematic perspective view of a circuit structure300A (also referred to herein as a “cell”), implemented with a CFET, that includes power conductive line307A, signal conductive lines309A,309B (hereinafter referred to as signal conductive line309), and a shielding conductive line312A in a front-side conductive layer305A. Additionally or alternatively, circuit structure300A includes a substrate (not shown inFIG.3A, but corresponding to, e.g.,460inFIG.4C) and a first transistor stack301A over the substrate. The first transistor stack301A includes: a first transistor302A where first transistor302A is a first conductivity type; and a second transistor304A, that is above the first transistor302A, where second transistor304A is a second conductivity type different from the first conductivity type. Circuit structure300A also includes a plurality of first conductive lines303A in a first metal layer305A above first transistor stack301A, a plurality of first conductive lines303A electrically connected to first transistor stack301A. Circuit structure300A also includes a plurality of second conductive lines318A in a second metal layer316A below the substrate and underneath first transistor stack301A, a plurality of second conductive lines318A electrically connected to first transistor stack301A. The plurality of first conductive lines303A are configured asymmetrically with respect to the plurality of second conductive lines318A. In some embodiments, circuit structure300A with front side conductive layer305A, first conductive lines303A, first transistor stack301A, first transistor302A and second transistor304A are like circuit structure100A with front side conductive layer105A, first conductive lines103A, first transistor stack101, first transistor102and second transistor104. Additionally or alternatively, circuit structure300A includes an additional back-side shielding conductive line333A. In some embodiments, additional shielding conductive line333A is the main difference between circuit structure300A and100A. Additionally or alternatively, shielding conductive line333A is a floating line or is connected to a reference voltage (e.g., VDD, VSS or any other voltage in between) to shield/prevent/reduce signal interference or cross talk between signals on332A,332B and signals on signal conductive lines of other/neighboring circuit structures/cells. In some embodiments, circuit structure300A includes a first transistor302A, an NMOS device, and a second transistor304A, a PMOS device. First transistor302A is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor304A is sometimes referred to as “top device” or “top transistor.” Additionally or alternatively, gate terminals310B,310A (hereinafter referred to as gate terminal310) of first transistor302A and second transistor304A are electrically connected together by a gate connection331while functioning as an input terminal receiving a signal, through a top gate via322A (also referred to as via-to-gate, or VG) from signal conductive line309A. In some embodiments, drain terminals330A,330B (hereinafter referred to as drain terminals330) of second transistor304A and first transistor302A are connected together while functioning as an output terminal, through via334A to signal conductive line332B or through via326A to signal conductive line332A. Additionally or alternatively, source terminal314A of second transistor304A is maintained at the supply voltage VDD through via328A electrically connected to power conductive line307A and source terminal314B of first transistor304A is maintained at the supply voltage VSS through via340A (FIG.3E) electrically connected to power conductive line320A. In at least one embodiment, gate connection331is omitted. In some embodiments, a bottom VG via (not shown) is provided to couple gate terminal310B of the bottom device, i.e., first transistor302A, to a signal conductive line332A,332B on the back-side metal layer316A. An example of a bottom VG via is described with respect toFIGS.3E-3F. In some embodiments, drain terminals330A,330B (hereinafter referred to as drain terminals330) of second transistor304A and first transistor302A are connected together by an MDLI138, while functioning as an output terminal outputting a signal, through via334A (also referred to as top via-top-to-bottom, or top VTB), to signal conductive line332B. In at least one embodiment, a similar MDLI is provided between source terminal314A of second transistor304A and source terminal314B of first transistor302A. In one or more embodiments, either or both of the described MDLI is/are omitted. Additionally or alternatively, source terminal314A of second transistor304A is maintained at the supply voltage VDD through top VD via328A electrically connected to power conductive line307A, and source terminal314B of first transistor302A is maintained at the supply voltage VSS through via340A (not shown inFIG.3Abut indicated inFIG.3E) electrically connected to power conductive line320A. Source terminals/drain terminals are also referred to as metal-to-device (MD) contact structures. The described “source terminal” and/or “drain terminal” are examples, and can be reversed as “drain terminal” and/or “source terminal” in one or more embodiments. In some embodiments, circuit structure300A includes a P-type active-region semiconductor structure306and an N-type active-region semiconductor structure308extending in the X-direction. In some embodiments, P-type active-region semiconductor structure306is stacked with N-type active-region semiconductor structure308along the Z-direction. Additionally or alternatively, gate terminal310extending in the Y-direction intersects both P-type active-region semiconductor structure306and N-type active-region semiconductor structure308. In some embodiments, gate terminal310functions as two stacked gate terminals310A,310B, conductively joined together: one gate terminal310A intersects P-type active-region semiconductor structure306at a channel region of second transistor304A, and another gate terminal310B intersects N-type active-region semiconductor structure308at a channel region of first transistor302A. Additionally or alternatively, gate terminal310A of second transistor304A is conductively connected to gate terminal310B of first transistor302A through gate connection331. In some embodiments, each of P-type active-region semiconductor structure306and N-type active-region semiconductor structure308includes one or more nano-sheets, and consequently, each of second transistor304A and first transistor302A is a nano-sheet transistor. Additionally or alternatively, each of P-type active-region semiconductor structure306and N-type active-region semiconductor structure308includes one or more nano-wires, and consequently, each of second transistor304A and first transistor302A is a nano-wire transistor. In some embodiments, circuit structure300A includes conductive segments including source terminals314and drain terminals330. Additionally or alternatively, each of source terminal314and drain terminal330, extend in the Y-direction and intersect P-type active-region semiconductor structure306of second transistor304A. In some embodiments, each of source terminal314and drain terminal330, extend in the Y-direction and intersect N-type active-region semiconductor structure308of first transistor302A. Additionally or alternatively, drain terminal330A and drain terminal330B are conductively connected through MDLI338A. In some embodiments, source terminal314A of second transistor304A is conductively connected to front-side power conductive line307A through a top via328A, and source terminal314B of the first transistor302A is conductively connected to back-side power conductive line320A through a bottom via340A (FIG.3E). Additionally or alternatively, front-side power conductive line307A is configured to be held at a first supply voltage VDD, and back-side power conductive line320A is configured to be held at a second supply voltage VSS. In some embodiments, front-side power conductive line307A extends in the X-direction in front-side metal layer305A. Additionally or alternatively, back-side power conductive line320A extends in the X-direction in back-side metal layer316A. In some embodiments, each of front-side metal layer305A and the back-side metal layer316A is in a plane having the normal vector orientated towards the Z-direction. Additionally or alternatively, front-side metal layer305A is above both P-type active-region semiconductor structure306and N-type active-region semiconductor structure308. In some embodiments, back-side metal layer316A is below both P-type active-region semiconductor structure306and N-type active-region semiconductor structure308. Additionally or alternatively, back-side metal layer316A is fabricated on a substrate (460FIG.4C) as a buried conductive layer, and, N-type active-region semiconductor structure308is fabricated above the buried conductive layer. In some embodiments, P-type active-region semiconductor structure306is fabricated above N-type active-region semiconductor structure308, and front-side metal layer305A is fabricated above P-type active-region semiconductor structure306. Additionally or alternatively, conductive lines in front-side metal layer305A and conductive lines in back-side metal layer316A are asymmetrical to one another. In some embodiments, circuit structure300A includes front-side signal conductive lines309in front-side metal layer305A and also back-side metal layer316A includes back-side signal conductive lines332and shielding conductive line333A. Additionally or alternatively, front-side signal conductive line309A is an input signal conductive line for providing an input to gate terminal310A. In some embodiments, front-side signal conductive line309A is conductively connected to gate terminal310A through a top gate via322A and configured as an input signal conductive line of circuit structure300A. In some embodiments, back-side signal conductive line332B is conductively connected to drain terminal330A through via334A and configured as an output signal conductive line of circuit structure300A. Additionally or alternatively, back-side signal conductive lines332A is conductively connected to drain terminal330B through via326A and configured as an output signal conductive line of circuit structure300A. Additionally or alternatively, back-side signal conductive lines332are configured to route signals between neighboring cells or circuit structures at opposite sides of circuit structure300A. For example, in some embodiments, through VTB334A (shown in dotted line as an optional element) connected to drain terminal330A, an output of transistor stack301A is routed through signal conductive line332B. In this structure, as discussed above, drain terminal330A of second transistor304A is connected, through VTB334A, to another transistor outside circuit structure300A, when a gate terminal and/or a source terminal/drain terminal of such another transistor is electrically coupled to the signal conductive line332B. In another example, additionally or alternatively, via336(shown in dotted line as an optional element—also referred to as VTB) electrically connects source terminal314A to signal conductive line332B. In this structure, source terminal314A of first transistor302A is connected, through via336and signal conductive line332B, to another transistor outside circuit structure300A. In yet another example, additionally or alternatively, bottom VD via326A (shown in dotted line as an optional element) electrically connects drain terminal330B to signal conductive line332A. In the example configuration inFIG.3A, signal conductive line332B is a continuous signal conductive line132B and extends from under drain terminal330A to under source terminal314A. Additionally or alternatively, conductive line332B includes two disconnected sections aligned along the X direction. In at least one embodiment, drain terminal330A is electrically coupled to source terminal314A through VTB334A, continuous signal conductive line332B, and VTB via336. In some embodiments, one or more other signal conductive lines described herein (e.g.,309A,309B,332A,332B) comprises aligned but disconnected sections. In accordance with some embodiments,FIG.3Bis a schematic perspective view of a circuit structure300B (also referred to herein as a “cell”) having power conductive line307B, signal conductive lines309C,309D,309E (hereinafter referred to as signal conductive line309F) and shielding conductive line312B in a front-side conductive layer305B. Additionally or alternatively, circuit structure300B includes a substrate (460FIG.4C) that includes a first transistor stack301B over the substrate that includes a first transistor302B where first transistor302B is a first conductivity type. A second transistor304B is above the first transistor302B, where second transistor304B is a second conductivity type different from the first conductivity type. Circuit structure300B also includes a plurality of first conductive lines303B in a first metal layer305B above first transistor stack301B, plurality of first conductive lines303B electrically connected to first transistor stack301B. Circuit structure300B also includes a plurality of second conductive lines318B in a second metal layer316B below the substrate and underneath first transistor stack301B, plurality of second conductive lines318B electrically connected to first transistor stack301B. Plurality of first conductive lines303B are configured asymmetrically with respect to plurality of second conductive lines318B. For simplicity, gate terminals of first transistor302B and second transistor304B are shown as a common gate terminal310. This gate terminal310, in one or more embodiments, includes a gate connection similar to gate connection331inFIG.3A. In some embodiments, a gate connection is omitted from gate terminal310inFIG.3B, and first transistor302B and second transistor304B have gate terminals which are disconnected from each other. In some embodiments, circuit structure300B with front side conductive layer305B, first conductive lines303B, first transistor stack301B, first transistor302B and second transistor304B are like circuit structure100B with front side conductive layer105B, first conductive lines103B, first transistor stack101, first transistor102and second transistor104. Additionally or alternatively, circuit structure300B includes an additional back-side shielding conductive line333B and additional signal conductive line309E. In some embodiments, additional shielding conductive line333B and additional signal conductive line309E are the main difference between circuit structure300B and100B. In some embodiments, circuit structure300A and300B are alike in that back-side metal layer316B is like back-side metal layer316A rotated 180 degrees and transistor stack301A and transistor stack301B are both transistor stacks, another IC device or the like. Additionally or alternatively, circuit structure300B does not include via328A, via322B is electrically connected to front-side signal conductive line309D, source terminal314A and via324B are electrically connected to front-side signal conductive line309C, and source terminal314B and via324A (also referred to herein as “via-bottom-to-top” or “VBT”) are electrically connected to front-side signal conductive line309E. In some embodiments, one or more VBT(s) (not shown) is/are included in circuit structure300A. In some embodiments, circuit structure300B includes front-side signal conductive line309C,309D, and309E in front-side metal layer305B and also back-side metal layer316B having back-side signal conductive lines332C and332D which are asymmetrical to front-side signal conductive lines309C,309D, and309E. Additionally or alternatively, back-side metal layer318B includes a shielding conductive line333B that serves as a shielding conductive line for signal conductive lines332C,332D between power conductive line320B and shielding conductive line333B. In some embodiments, first metal layer305B including first conductive lines303B that includes power conductive line307B, signal conductive lines309C,309D,309E and shielding conductive line312B, second conductive lines318B that includes power conductive line320and signal conductive lines332C,332D, and vias (322B,324A,324B,340B) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive lines312B and333B are a floating conductive line or shielding conductive lines312B and333B are connected to a reference voltage (e.g., VDD, VSS or any voltage on circuit300B). Additionally or alternatively, shielding conductive lines312B and333B shield, prevent and/or reduce signal interference or signal cross-talk between signals on signal conductive lines309C,309D,309E,332C,332D and signals on other neighboring circuit structures or cells. In some embodiments, circuit structure300B includes a first transistor302B, an NMOS device, and a second transistor304B, a PMOS device. First transistor302B is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor304B is sometimes referred to as “top device” or “top transistor.” Additionally or alternatively, gate terminal310functions as an input terminal receiving a signal, through a top gate via322B (also referred to as via-to-gate, or VG), from signal conductive line309D. In some embodiments, a bottom VG via (not shown) is provided to couple gate terminal310to a signal conductive line332C,332D on metal layer316B. In some embodiments, drain terminals330A,330B (hereinafter referred to as drain terminals) of second transistor304B and first transistor302B are connected together by an MDLI338B (FIG.3C), while functioning as an output terminal outputting a signal, through via334B (also referred to as VTB, or via top to bottom), to signal conductive line332C. In at least one embodiment, a similar MDLI is provided between source terminal314A of second transistor304B and source terminal314B of first transistor302B. In one or more embodiments, either or both of the described MDLI is/are omitted. Additionally or alternatively, source terminal314B of first transistor302B is maintained at the supply voltage VSS through bottom VSS via340B electrically connected to power conductive line320B. Source terminal/drain terminals are also referred to as metal-to-device (MD) contact structures. The described “source terminal” and/or “drain terminal” are examples, and can be reversed as “drain terminal” and/or “source terminal” in one or more embodiments. In some embodiments, circuit structure300B includes a P-type active-region semiconductor structure306and an N-type active-region semiconductor structure308extending in the X-direction. Additionally or alternatively, the X-direction, the Y-direction, and the Z-direction, inFIG.3Band other FIGS. throughout the disclosure are mutually orthogonal to each other and form an orthogonal coordinate frame. In some embodiments, P-type active-region semiconductor structure306is stacked with N-type active-region semiconductor structure308along the Z-direction. Additionally or alternatively, gate terminal310extending in the Y-direction intersects both P-type active-region semiconductor structure306and N-type active-region semiconductor structure308. In some embodiments, gate terminal310functions as two stacked gate terminals, conductively joined together: one gate terminal intersects P-type active-region semiconductor structure306at a channel region of second transistor304B, and another gate terminal intersects N-type active-region semiconductor structure308at a channel region of first transistor302B. In some embodiments, each of P-type active-region semiconductor structure306and N-type active-region semiconductor structure308includes one or more nano-sheets, and consequently, each of second transistor304B and first transistor302B is a nano-sheet transistor. Additionally or alternatively, each of P-type active-region semiconductor structure306and N-type active-region semiconductor structure308includes one or more nano-wires, and consequently, each of second transistor304B and first transistor302B is a nano-wire transistor. In some embodiments, circuit structure300B includes conductive segments including source terminals314and drain terminals330. Additionally or alternatively, each of source terminal314and drain terminal330, extend in the Y-direction and intersect P-type active-region semiconductor structure306of second transistor304A. In some embodiments, each of source terminal314and drain terminal330, extend in the Y-direction and intersect N-type active-region semiconductor structure308of first transistor302B. Additionally or alternatively, drain terminal330A and drain terminal330B are conductively connected through MDLI338B. In some embodiments, source terminal314A of second transistor304B is conductively connected to front-side signal conductive line309C through a top via324B, and source terminal314B of the first transistor302B is conductively connected to back-side power conductive line320B through a bottom via340B. Additionally or alternatively, front-side power conductive line307B is configured to be held at a first supply voltage VDD, and back-side power conductive line320B is configured to be held at a second supply voltage VSS. In some embodiments, front-side power conductive line307B extends in the X-direction in front-side metal layer305B. Additionally or alternatively, back-side power conductive line320B extends in the X-direction in back-side metal layer316B. In some embodiments, each of front-side metal layer305B and the back-side metal layer316B is in a plane having the normal vector orientated towards the Z-direction. Additionally or alternatively, front-side metal layer305B is above both P-type active-region semiconductor structure306and N-type active-region semiconductor structure308. In some embodiments, back-side metal layer316B is below both P-type active-region semiconductor structure306and N-type active-region semiconductor structure308. Additionally or alternatively, back-side metal layer316B is fabricated on a substrate (460FIG.4C) as a buried conductive layer, and, N-type active-region semiconductor structure308is fabricated above the buried conductive layer. In some embodiments, P-type active-region semiconductor structure306is fabricated above N-type active-region semiconductor structure308, and front-side metal layer305B is fabricated above P-type active-region semiconductor structure306. In some embodiments, conductive lines in front-side metal layer305B and conductive lines in back-side metal layer316B are asymmetrical to one another. In some embodiments, circuit structure300B includes front-side signal conductive lines309C,309D,309E in front-side metal layer305B and also back-side metal layer316B includes back-side signal conductive lines332C,332D. In some embodiments, front-side signal conductive line309D is conductively connected to gate terminal310through a top gate via322B and configured as an input signal conductive line of circuit structure300B. Additionally or alternatively, back-side signal conductive lines332are configured to route signals between neighboring cells or circuit structures at opposite sides of circuit structure300B. For example, in some embodiments, through VTB334B (FIG.3F) connected to drain terminal330A, an output of transistor stack301B is routed through signal conductive line332C. In this structure, as discussed above, drain terminal330A of second transistor304B is connected, through VTB334B, to another transistor outside circuit structure300B, when a gate and/or a source terminal/drain terminal of such another transistor is electrically coupled to the signal conductive line332C. Compared to circuit structures100A,100B, circuit structures300A,300B include an additional conductive line in M0 layer and/or an additional conductive line in BM0 layer, without increasing the cell height along the Y direction. In at least one embodiment, circuit structures300A,300B include one or more VBT(s) (e.g.,324A inFIG.3B) not included in circuit structures100A,100B. As a result, additional routing resources are provided and/or routing flexibility is increased, in one or more embodiments. In some embodiments, circuit structures100A,100B have mirror arrangements of conductive lines in M0 layer, and the same arrangement of conductive lines in BM0 layer. In some embodiments, circuit structures300A,300B have mirror arrangements of conductive lines in M0 layer, and the same arrangement of conductive lines in BM0 layer. In some embodiments, each of circuit structures100A,100B,300A,300B has asymmetrical arrangements of conductive lines in M0 layer and BM0 layer. For example, in each of circuit structures100A,100B,300A,300B, the arrangement of conductive lines in M0 layer is not a mirror image of (i.e., is asymmetrical to) the arrangement of conductive lines in BM0 layer. This is different from other approaches where the arrangement of conductive lines in M0 layer is a mirror image of (i.e., is symmetrical to) the arrangement of conductive lines in BM0 layer. Compared to the other approaches, circuit structures100A,100B,300A,300B include an additional conductive line in M0 layer and/or an additional conductive line in BM0 layer, without increasing the cell height along the Y direction. As a result, compared to the other approaches, additional routing resources are provided and/or routing flexibility is increased, in one or more embodiments. In accordance with some embodiments,FIGS.3C,3D,3E, and3Fare layout diagrams of circuit structures300A and300B inFIGS.3A and3B. In some embodiments,FIG.3Cis a layout diagram of circuit structure300A, specifically front-side metal layer305A and second transistor304A in the Z-direction. In some embodiments,FIG.3Dis a layout diagram of circuit structure300A, specifically back-side metal layer316A and first transistor302A in the Z-direction. In some embodiments,FIG.3Eis a layout diagram of circuit structure300B, specifically front-side metal layer305B and second transistor304B in the Z-direction. In some embodiments,FIG.3Fis a layout diagram of circuit structure300B, specifically back-side metal layer316B and first transistor302B in the Z-direction. In some embodiments, layout diagrams344,346,348and350are circuit structures with a 2 CPP. Additionally or alternatively, H is represented as the height of active-region semiconductor structures306and308. In some embodiments, layout diagrams344,346,348, and350have a height of from 5H and 30H. In some embodiments, a cell height, represented as the distance between cell boundary311A and311B, along the Y direction in each of layout diagrams344,346,348, and350is from 5H and 30H. Additionally or alternatively, cell boundary lines311A and311B, together with dummy gate-strip patterns310C (discussed below), act as edges of a cell boundary (also referred to as “place-and-route boundary”) that are placed in abutment with edges of the cell boundaries of neighboring cells. In some embodiments, the layout diagram inFIG.3Cincludes a layout diagram344for a top portion or top device of circuit structure300A, including P-type active-region semiconductor structure306, gate terminal310A, drain terminal330A and source terminal314A, front-side signal conductive lines309A and309B, front-side power conductive line307A, shielding conductive line312A and various vias322A and328A. In some embodiments, the layout diagram inFIG.3Dincludes layout diagram346for a bottom portion or bottom device of circuit structure300A, including N-type active-region semiconductor structure308, gate terminal310B, source terminal314B, drain terminal330B, back-side power conductive line320A, signal conductive lines332A,332B, shielding conductive line333A, MDLI338A, and vias340A,326A. In some embodiments, the layout diagram inFIG.3Eincludes a layout diagram348for a top portion or top device of circuit structure300B, including P-type active-region semiconductor structure306, gate terminal310, drain terminal330A and source terminal314A, the front-side signal conductive lines309C,309D, and309E, front-side power conductive line307B, shielding conductive line312B and various vias322B and324B. In some embodiments, the layout diagram inFIG.3Fincludes layout diagram350for a bottom portion or bottom device of circuit structure300B, including N-type active-region semiconductor structure308, gate terminal310, source terminal314B, drain terminal330B, back-side power conductive line320B, signal conductive lines332C,332D, shielding conductive line333B, MDLI338B, and drain via326B and VSS via340B. In some embodiments, each of P-type active-region semiconductor structure306, N-type active-region semiconductor structure308, front-side signal conductive lines309A,309B,309C,309D, and309E, and front-side power conductive line307A,307B, front-side shielding conductive line312A,312B, back-side signal conductive lines332A,332B,332C, and332D, back-side shielding conductive lines333A,333B and back-side power conductive lines320A,320B are extending in the X-direction. Additionally or alternatively, gate terminal310extends in the Y-direction and intersects P-type active-region semiconductor structure306at a channel region of second transistor304A,304B. In some embodiments, source terminal314extends in the Y-direction and intersects P-type active-region semiconductor structure306at a channel region of second transistor304A,304B. Additionally or alternatively, drain terminal330extends in the Y-direction and intersects P-type active-region semiconductor structure306at a channel region of second transistor304A,304B. In some embodiments, via328A electrically connects source terminal314A and front-side power conductive line307A. Additionally or alternatively, via322A,322B electrically connect gate terminal310and front-side signal conductive lines309A,309C respectively. In some embodiments, each of N-type active-region semiconductor structure308, the back-side signal conductive lines332A,332B,332C, and332D, back-side power conductive line320A,320B, and back-side shielding conductive line333A,333B extend in the X-direction. Additionally or alternatively, gate terminal310extends in the Y-direction and intersects N-type active-region semiconductor structure308at a channel region of first transistor302A,302B. In some embodiments, source terminal314B extends in the Y-direction and intersects N-type active-region semiconductor structure308. Additionally or alternatively, drain terminal330B extends in the Y-direction and intersects N-type active-region semiconductor structure308at a channel region of first transistor302A,302B. In some embodiments, via340B provides electrical connection between source terminal314B and back-side power conductive line320B. In some embodiments,FIGS.3C,3D,3E, and3Falso include dummy gate-strip patterns310C at the edges of layout diagrams344,346,348and350. In some embodiments, the intersections between dummy gate-strip patterns310C and the layout diagram of P-type active-region semiconductor structure306are for isolating P-type active-region semiconductor structure306from active-regions in neighboring cells. Additionally or alternatively, the intersections between dummy gate-strip patterns310C and the layout diagram of N-type active-region semiconductor structure308isolate N-type active-region semiconductor structure308from active-regions in neighboring cells. In some embodiments, the isolation regions in active-region semiconductor structures306,308are created based on the poly on oxide definition edge (PODE) technology or based on the continuous poly on oxide definition edge (CPODE) technology. Additionally or alternatively, other suitable technologies for generating the isolation regions in active-region semiconductor structures306,308are also within the contemplated scope of present disclosure. In some embodiments, the cell height of layout diagrams344,346,348and350do not change with the addition of back-side shielding conductive line333A,333B or front-side signal conductive line309E. Additionally or alternatively, a wide power conductive line lowers resistance and Joule heating. In some embodiments, a wide power conductive line allows for a merged or shared power conductive line with abutting stacked cells. Additionally or alternatively, a single shielding conductive line is used to share with adjacent stacked cells. In some embodiments, in vertical abutting of single cells (seeFIGS.4A-4D), common power conductive line and common shielding conductive line are able to be implemented. Additionally or alternatively, in double height cells, an additional shielding conductive line, such as309E provide additional signal conductive line shielding. In some embodiments, in double height cells, drain terminal330B extends further away from power conductive lines320A,320B and electrically connects to a drain via on shielding conductive line333A, or333B. In some embodiments, as is discussed below in greater detail, when vertical abutting (i.e., abutting along the Y-direction) of stacked transistor cells is implemented, sharing a common power conductive line and/or a common shielding conductive line is achieved between top transistors of abutting cells. Additionally or alternatively, inFIGS.3C and3Deach of power conductive line307A and307B has a length of overhang354that extends outside of layout diagrams344and346. In some embodiments, layout diagram348has a certain amount of overhang356from shielding conductive line312B. Additionally or alternatively, each of overhang354and356provide for electrical connections to adjoining cells for the sharing of power conductive lines307A,307B or shielding conductive lines312A,312B. In some embodiments, the aspect of a common power conductive line or a common shielding conductive line are discussed in greater detail below. Additionally or alternatively, power conductive lines320A,320B inFIGS.3D and3Fadditionally has an overhang358. In some embodiments, back-side overhang358is used to couple power to one or more other first/bottom transistors of one or more adjoining/abutting cells. In some embodiments, shielding conductive line333A has an overhang360,FIG.3D, that is used to couple and/or shield signal conductive lines332of adjoining cells. In accordance with some embodiments,FIG.4Ais a schematic perspective view of a circuit structure400C that combines a top cell circuit structure400A and a bottom cell circuit structure400B at a common power conductive line407A. Circuit structure400A abuts or adjoins circuit structure400B in the Y-direction. Circuit structure400A is arranged further towards a positive orientation of the Y direction than circuit structure400B, and is referred to as “top cell” or “top cell circuit structure.” Thus, circuit structure400B is referred to as “bottom cell” or “bottom cell circuit structure.” In some embodiments, a circuit structure400C includes a substrate (FIG.4C) that includes a first transistor stack401A and a second transistor stack401B over the substrate where first transistors402A,402B are a first conductivity type; and second transistors404A,404B are above first transistors402A,402B respectively, where second transistors404A,404B are a second conductivity type different from the first conductivity type. Circuit structure400C also includes a plurality of first conductive lines403A in a first metal layer405A above transistor stacks401A,401B. A plurality of first conductive lines403A over transistor stacks401A,401B includes a power conductive line407A configured to route power to transistor stacks401A,401B; one or more signal conductive lines409A,409B,409C,409D, and409E (hereinafter referred to as signal conductive lines409) configured to route signals to transistor stacks401A,401B; and one or more shielding conductive line412A,412B configured to shield the routed signals on one or more signal conductive lines409, where one or more signal conductive lines409are between power conductive line407A and shielding conductive lines412A,412B. Additionally or alternatively, circuit structure400A includes a substrate (460FIG.4C) that includes a first transistor stacks401A and401B over the substrate that includes: first transistors402A,402B where first transistors402A and402B are a first conductivity type; and a second transistor404, above the first transistor402A and402B, where second transistor404is a second conductivity type different from the first conductivity type. Circuit structure400A also includes a plurality of first conductive lines403A in a first metal layer405A above first transistor stacks401A and401B, a plurality of first conductive lines403A electrically connected to first transistor stacks401A and401B. Circuit structure400A also includes a plurality of second conductive lines418A in a second metal layer416A below the substrate and underneath first transistor stacks401A and401B, a plurality of second conductive lines418A electrically connected to first transistor stacks401A and401B. The plurality of first conductive lines403A are configured asymmetrically with respect to the plurality of second conductive lines418A. In some embodiments, circuit structures400A,400B with transistor stacks401A,401B are like circuit structures300B and300A with transistor stacks301B and301A. Additionally or alternatively, circuit structure400C represents a combination of circuit structures400A and400B that are like circuit structures300B and300A where each of circuit structure300B and300A shares a common front-side power conductive line407A and a common back-side power conductive line420A. In some embodiments, first metal layer405A including first conductive lines403A that includes power conductive line407A, signal conductive lines409A,409B,409C,409D,409E, and shielding conductive lines412A,412B, second conductive lines418A that includes power conductive lines420A and signal conductive lines432A,432B,432C,432D (hereinafter referred to as signal conductive lines432), and vias (422A,422B,424A,426A,428B,434A,436) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive lines412A,412B is a floating conductive line or shielding conductive lines412A,412B is connected to a reference voltage (e.g., VDD, VSS or any voltage on circuit400C). Additionally or alternatively, shielding conductive lines412A,412B shields, prevents and/or reduces signal interference or signal cross-talk between signals on signal conductive lines409A,409B,409C,409D,409E and signals on other neighboring circuit structures or cells. In some embodiments, circuit structure400C includes first transistors402A,402B, an NMOS device, and second transistors404A,404B, a PMOS device. First transistors402A,402B is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor204A,204B is sometimes referred to as “top device” or “top transistor.” In accordance with some embodiments,FIG.4Bis a schematic perspective view of a circuit structure400F that combines a top cell circuit structure400D and a bottom cell circuit structure400E at a common shielding conductive line412C. Circuit structure400D abuts or adjoins circuit structure400E in the Y-direction. Circuit structure400D is arranged further towards a positive orientation of the Y direction than circuit structure400E, and is referred to as “top cell” or “top cell circuit structure.” Thus, circuit structure400E is referred to as “bottom cell” or “bottom cell circuit structure.” In some embodiments, circuit structures400D,400E with transistor stacks401A,401B are like circuit structures300A and300B with transistor stacks301A and301B. Additionally or alternatively, circuit structure400F represents a combination of circuit structures400D and400E where each of circuit structure400D and400E shares a common front-side shielding conductive line412C and a common back-side shielding conductive line433C. In some embodiments, circuit structure400F includes a substrate (460FIG.4C) that includes first transistor stacks401A and401B over the substrate. First transistor stacks401A and401B include first transistors402A,402B where first transistors402A,402B is a first conductivity type. Second transistors404A,404B, are above the first transistors402A,402B, where second transistors404A,404B are a second conductivity type different from the first conductivity type. Circuit structure400F also includes a plurality of first conductive lines403B in a first metal layer405B above first transistor stacks401A and401B, a plurality of first conductive lines403B electrically connected to first transistor stacks401A and401B. Circuit structure400F also includes a plurality of second conductive lines418B in a second metal layer416B below the substrate and underneath first transistor stacks401A and401B, a plurality of second conductive lines418B electrically connected to first transistor stacks401A and401B. The plurality of first conductive lines403B are configured asymmetrically with respect to the plurality of second conductive lines418B. In some embodiments, first metal layer405B including first conductive lines403B that includes power conductive lines407B,407C, signal conductive lines409F,409G,409H,409I,409J, and shielding conductive line412C, second conductive lines418B that includes power conductive lines420B,420C and signal conductive lines432A,432B,432C,432D (hereinafter referred to as signal conductive lines432), and vias (422C,422D,424B,424C,426B,428C,434B,440C) are one or more conductive materials, e.g., a metal such as copper, aluminum, tungsten, titanium, polysilicon, or another material capable of providing a low resistance signal path. In some embodiments, shielding conductive line412C is a floating conductive line or shielding conductive line412C is connected to a reference voltage (e.g., VDD, VSS or any voltage on circuit400F). Additionally or alternatively, shielding conductive line412C shields, prevents and/or reduces signal interference or signal cross-talk between signals on signal conductive lines409F,409G,409H,409I,409J and signals on other neighboring circuit structures or cells. In some embodiments, in a double cell height cell like circuit structure400F, shielding conductive line412C is configured as an internal signal conductive line for routing signals inside the cell. For example, shielding conductive line412C is disconnected at the cell boundary so that signals on shielding conductive line412C stay internal within the cell. In some embodiments, circuit structure400F includes first transistors402A,402B, an NMOS device, and second transistors404A,404B, a PMOS device. First transistors402A,402B is sometimes referred to as “bottom device” or “bottom transistor,” and second transistor404A,404B is sometimes referred to as “top device” or “top transistor.” In accordance with some embodiments,FIG.4Cis a schematic cross-sectional view of circuit structure400G with a common front-side shielding conductive line412D and common back-side shielding conductive line433D. In some embodiments, circuit structure400G includes a plurality of first conductive lines that includes power conductive lines407D,407E configured to route power to transistor stacks401A,401B; one or more signal conductive lines409K,409L,409M,409N, and409O configured to route signals to transistor stacks401A,401B; and one front-side common shielding conductive line412D configured to shield the routed signals on one or more signal conductive lines409K,409L,409M,409N, and409O, where one or more signal conductive lines409K,409L,409M,409N, and409O are between power conductive lines407D,407E and shielding conductive line412D. In some embodiments, circuit structures400H,400I with transistor stacks401A,401B are like circuit structures300A and300B with transistor stack301A and301B. Additionally or alternatively, circuit structure400G represents a combination of circuit structures400H and400I that are like each of circuit structures300A and300B and share a common shielding conductive line412D that is like shielding conductive line312A or312B. In some embodiments, circuit structure400G includes a plurality of second conductive lines that includes power conductive lines420C,420D configured to route power to first transistors in transistor stacks401A,401B through via440E; one or more signal conductive lines432E,432F,432G, and432H configured to route signals to transistor stacks401A,401B through vias426B and426C; and one back-side common shielding conductive line433D configured to shield the routed signals on one or more signal conductive lines432E,432F,432G, and432H, where one or more signal conductive lines432E,432F,432G, and432H are between power conductive lines420C,420D and shielding conductive line433D. In some embodiments, power conductive lines407D,407E have a width462of from 3H and 7H where H is represented as the height of active-region semiconductor structures406A,406B,408A,408B in the Z-direction. Additionally or alternatively, back-side power conductive lines420C,420D have a width472of from 6H and 9H. Additionally or alternatively, width462of front-side power conductive lines407D,407E and width472of back-side power conductive lines420C,420D reduce the resistance of power conductive lines407D,407E,420C,420D and thus reduce Joule heating. In some embodiments, signal conductive lines409K,409L,409M,409N, and409O have a width464of from 0.5H and 3H and the distance466between conductive lines409K,409L,409M,409N, and409O is from 0.5H and 3H. Additionally or alternatively, transistor stack height468is between 10H and 50H and cell width470is from 5H and 30H. In some embodiments, circuit structure400G includes conductive segments including source terminals414A,414B,414C, and414D and drain terminals (not shown). Additionally or alternatively, each of source terminal414A,414B,414C and414D and the drain terminal, extend in the Y-direction and intersect P-type active-region semiconductor structures406A,406B, of second transistors404A,404B. In some embodiments, each of source terminal414A,414B,414C and414D and the drain terminal, extend in the Y-direction and intersect N-type active-region semiconductor structure408A,408B of first transistors402A,402B. In some embodiments, source terminal414A of second transistor404A is conductively connected to back-side signal conductive line432F through VTB434C, source terminal414A of the second transistor404A is conductively connected to back-side shielding conductive line433D through a VTB434D, source terminal414D of the first transistor402B is conductively connected to front-side signal conductive line409O through a VTB434D, source terminal414A of the second transistor404A is conductively connected to front-side signal conductive line409K through a via424E, source terminal414C of the second transistor404B is conductively connected to front-side signal conductive lines409M through a via424F, source terminal414C of the second transistor404B is conductively connected to front-side power conductive lines407E through a via428D. In some embodiments, VTBs434C and434D are optional, i.e., circuit structure400G includes none of VTBs434C and434D, either434C or434D, or both434C and434D. In some embodiments, top devices (or top transistors404A,404B) in abutted cells, such as in circuit structures400H,400I, have front-end features and VTBs (434C,434D) that are stackable (or the same), and have back-end features with a mirror structure. In some embodiments, bottom devices (or bottom transistors402A,402B) in abutted cells, such as in circuit structure400H,400I, have both front-end features and back-end features that are stackable (or the same). Front-end features include features manufactured in front-end-of-line (FEOL) fabrication, and back-end features include features manufactured in back-end-of-line (BEOL) fabrication. Examples of front-end features include PO, CPO, MD and OD features. Examples of back-end features include M0, BM0, VG, VD and CMD features. PO features correspond to where gates are formed, and CPO (cut-PO) features correspond to where gates are disconnected. MD features or MD contact structures correspond to where source terminal/drain terminals as described herein are formed, and CMD (cut-MD) features correspond to where MD contact structures are disconnected. OD features correspond to active regions (or active-region semiconductor structures). M0 features correspond to conductive patterns in a metal zero (M0) layer. In at least one embodiment, the conductive lines407D,409K,409L,412D,409O,409N,409M and407E over transistor stacks401A,401B are conductive patterns in the M0 layer. BM0 features correspond to conductive patterns in a backside metal zero (BM0) layer. In at least one embodiment, the conductive lines420C,432E,432F,433D,420D,432G, and432H under transistor stacks401A,401B are conductive patterns in the BM0 layer. VG, VB (424E,424D,424F,428D,434C,434D), and VD features correspond to various VG, VB and VD vias described herein. In some embodiments, the front-end features and VTBs of the top transistors, e.g.,404A,404B inFIGS.4A-4B, are stackable (or the same), whereas the back-end features of the top transistors, e.g.,404A,404B inFIGS.4A-4B, have a mirror structure. For example, the conductive lines403B over the top transistor404A and the conductive lines403B over the top transistor404B are symmetrical to one another across a center line of common shielding conductive line412C, as shown inFIGS.4B-4C. In some embodiments, the front-end features and back-end features of the bottom transistors, e.g.,402A,402B inFIGS.4A-4B, are stackable (or the same). For example, the conductive lines418B under the bottom transistor402A and the conductive lines418B under the bottom transistor402B are the same, as shown inFIGS.4B-4C. In accordance with some embodiments,FIG.4Dis a schematic perspective cross-sectional view of circuit structures400J,400K,400L, and400M with common power circuit structure400H and common shielding circuit structures400G. Additionally or alternatively, circuit structures400J and400L are like circuit structures300A and circuit structures400K and400M are like circuit structures300B. In some embodiments, circuit structure400H is like circuit structure400A and circuit structures400G are like circuit structure400F. To abut the two circuit structures400G inFIG.4D, power conductive lines407D and420C (seeFIG.4C) of the circuit structure400G on the right inFIG.4Dare merged correspondingly with power conductive lines407E and420D (seeFIG.4C) of the circuit structure400G on the left inFIG.4D. In some embodiments, circuit structure400G corresponds to circuit structure400F and/or circuit structure400H corresponds to circuit structure400C. In some embodiments, circuit structure400I includes one or more common power circuit structures400H and one or more common shielding circuit structures400G. Additionally or alternatively, circuit structure400H includes circuit structures400K and400L that share a front-side common power conductive line407F and a back-side common power conductive line420E. In some embodiments, right side circuit structure400G includes circuit structures400L and400M that share an front-side common shielding conductive line412E and a back-side common shielding conductive line433E. Additionally or alternatively, left side circuit structure400G includes circuit structures400J and400K that share a front-side common shielding conductive line412F and a back-side common shielding conductive line433F. In accordance with some embodiments,FIG.5Ais a layout diagram of an upper or top portion of a Scan D Flip-flop (SDF) circuit500. In some embodiments,FIG.5Bis a layout diagram of a lower or bottom portion of the SDF circuit500. Additionally or alternatively, circuit structure500includes at least one common shielding conductive line structure like circuit structure400G or400F. In some embodiments, SDF circuit500has a CPP of 20 (10 CPPs in the upper portion inFIG.5A, and another 10 CPPs in the lower portion inFIG.5B). In at least one embodiment, SDF circuit500with 20 CPPs provides an improvement over other approaches which require at least 22 CPPs to achieve an SDF circuit. Additionally or alternatively, SDF circuit500has a height of from 10H and 60H. In some embodiments, a cell height, represented as the distance between cell boundary511A and511B, along the Y direction in layout diagram500is from 10H and 60H. Additionally or alternatively, cell boundary lines511A and511B, together with dummy gate-strip patterns, act as edges of a cell boundary (also referred to as “place-and-route boundary”) that are placed in abutment with edges of the cell boundaries of neighboring cells. In some embodiments, various elements for forming the SDF circuit500are specified by the corresponding layout diagrams. Additionally or alternatively,FIG.5Aincludes an upper portion (or top devices) of layout diagram502, andFIG.5Bincludes a lower portion (or bottom devices) of layout diagram502. In some embodiments, elements specified inFIG.5Ainclude a first P-type active-region semiconductor structure506A and a second P-type active-region semiconductor structure506B. Additionally or alternatively, elements specifiedFIG.5Bincludes a first N-type active-region semiconductor structure508A and a second N-type active-region semiconductor structure508B. In some embodiments, a circuit structure500includes power conductive lines507A and507B configured to route power to transistor stacks; signal conductive lines509A,509B,509C,509D, and509E (hereinafter referred to as signal conductive lines509); and shielding conductive line512A configured to shield the routed signals on one or more signal conductive lines509, where one or more signal conductive lines509are between power conductive line507A and507B and shielding conductive line512A. Additionally or alternatively, circuit structure500includes back-side power conductive lines520A and520B, signal conductive lines532A,532B,532C, and532D, and shielding conductive line533A. In some embodiments, for double-height cells (e.g.,FIGS.5A and5B) power conductive lines507A,507B,520A and520B serve as natural shielding conductive lines between different cells and there is no line intended only for shielding since line533A is inside the cell and can be used for routing. Additionally or alternatively, however, for single height cells, line533A is intended only for shielding since it should be at the boundary of the cell. In accordance with some embodiments,FIG.6Ais a flowchart of a method660of generating an integrated circuit (IC) layout diagram. Additionally or alternatively, additional operations are performed before, during, and/or after the method660depicted inFIG.6A, and that some other processes are only be briefly described herein. In some embodiments, the method660is usable to generate one or more layout diagrams, such as the layout diagrams inFIGS.1C,1D,1E,3C,3D,3E,3ForFIGS.5A-5B. Additionally or alternatively, the method660is usable to form integrated circuits having similar structural relationships as one or more of the semiconductor structures formed based on the layout diagrams inFIGS.1C,1D,1E,3C,3D,3E,3ForFIGS.5A-5B. In some embodiments, method660is performed by a processing device (e.g., processor802inFIG.8) configured to execute instructions for generating one or more layout diagrams, such as the layout diagrams inFIGS.1C,1D,1E,3C,3D,3E,3ForFIGS.5A-5B. In some embodiments, in operation662of method660, an array of front-side power conductive lines is generated. Additionally or alternatively, each of the front-side power conductive lines specifies a front-side conductive line in a front-side conductive layer. In the example designs ofFIGS.6B-6G, front side conductive layer605includes front-side power conductive lines607A and607B. In some embodiments, in operation664of method660, an array of first-type active-region semiconductor structures is generated. Additionally or alternatively, the first-type active-region semiconductor structures are positioned in parallel with the front-side power conductive lines. In some embodiments, each of the first-type active-region semiconductor structures specifies a first-type active-region semiconductor structure. In the example designs ofFIGS.6B-6G, the array of first-type active-region semiconductor structures includes the layout diagrams for P-type active-region semiconductor structures606A,606B,606C, and606D. The layout diagrams for P-type active-region semiconductor structures606A,606B,606C, and606D are positioned in parallel between the layout diagrams for front-side power conductive lines607A and607B. In some embodiments, in operation666of method660, an array of back-side power conductive lines is generated. Additionally or alternatively, each back-side power conductive line specifies a back-side power conductive line in a back-side conductive layer. In the example layout diagrams ofFIGS.6B-6G, back-side conductive layer616includes back-side power conductive lines620A and620B. In some embodiments, in operation668of method660, an array of second-type active-region semiconductor structures is generated. Additionally or alternatively, the second-type active-region semiconductor structures are positioned in parallel with back-side power conductive lines620A and620B. In some embodiments, each of the second-type active-region semiconductor structures specifies a second-type active-region semiconductor structure608that is stacked with a corresponding first-type active-region semiconductor structure606. In the example layout diagrams ofFIGS.6B-6G, the array of second-type active-region semiconductor structures includes the layout diagrams for N-type active-region semiconductor structures608A,608B,608C, and608D. In some embodiments, in the integrated circuit fabricated according to the layout diagrams ofFIGS.6B-6G, N-type active-region semiconductor structures608A,608B,608C, and608D is staked with the P-type active-region semiconductor structures606A,606B,606C, and606D respectively. In some embodiments, in operation670of method660, at least one front-side signal conductive line pattern is generated between a pair of adjacent front-side power conductive lines. Additionally or alternatively, the at least one front-side signal conductive line pattern specifies a front-side signal conductive line in the front-side conductive layer above both the first-type active-region semiconductor structure and the second-type active-region semiconductor structure. In the example layout diagrams ofFIGS.6B-6G, the layout diagrams for front-side signal conductive lines609A,609B,609C,609D, and609E are positioned between the layout diagrams for front-side power conductive lines607A and607B. In some embodiments, in operation672of method660, at least one back-side signal conductive line pattern is generated between a pair of adjacent back-side power conductive lines. Additionally or alternatively, back-side signal conductive lines632A,632B,632C, and632D in back-side conductive layer616are below both first-type active-region semiconductor structures606A,606B,606C, and606D and second-type active-region semiconductor structures608A,608B,608C and608D. In the example layout diagrams ofFIGS.6B-6G, the layout diagrams for back-side signal conductive lines632A,632B,632C, and632D are positioned between the layout diagrams for back-side conductive lines620A and620B. In some embodiments, in operation674of method660, at least one front-side shielding conductive line pattern is generated adjacent to front-side signal conductive lines609B and609C. Additionally or alternatively, front-side shielding conductive line612specifies a front-side shielding conductive line612in front-side conductive layer605above both first-type active-region semiconductor structures606A and606B and second-type active-region semiconductor structures608A and608B. In the example layout diagrams ofFIGS.6B-6G, the layout diagrams for front-side shielding conductive lines612is positioned between the layout diagrams for front-side signal conductive lines609B and609C. In some embodiments, in operation676of method660, at least one back-side shielding conductive line pattern633is generated between a pair of adjacent back-side signal conductive lines. Additionally or alternatively, back-side shielding conductive line633is in back-side conductive layer616are below both first-type active-region semiconductor structures606A,606B,606C, and606D and second-type active-region semiconductor structures608A,608B,608C and608D. In the example layout diagrams ofFIGS.6B-6G, the layout diagrams for back-side shielding conductive line633is positioned between the layout diagrams for back-side signal conductive lines632B and632C. In some embodiments,FIG.6Eincludes curved arrow660that represents power routed from VDD through power conductive line607A, via628, source terminal614A, VTB634, and to shielding conductive line633, so that shielding conductive line633can shield signal cross talk between signal conductive lines632A,632B and signal conductive lines632C and632D. Additionally or alternatively, power is connected to bottom devices through VTB634. In at least one embodiment where VDD may be available only at a front-side metal layer (e.g., M0) and VSS may be available only at a back-side metal layer (e.g., BM0), by routing VDD from M0 layer to a conductive line, e.g.,633, in BM0 layer, it is possible to configure conductive line633as a shielding conductive line, or as an additional VDD power conductive line for supplying VDD to one or more circuit elements from an otherwise VSS-only BM0 layer. In at least one embodiment, this arrangement increases routing resources and/or flexibility. In accordance with some embodiments,FIG.7Ais a flowchart of a method700of manufacturing an IC. Additionally or alternatively, additional operations are performed before, during, and/or after method700depicted inFIG.7A, and that some other processes are only briefly described herein. In some embodiments, in operation710of method700, first and second-type active-region semiconductor structures are fabricated on a substrate. Additionally or alternatively, the first and second-type active-region semiconductor structures are fabricated atop a layer of dielectric material. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, P-type active-region semiconductor structure106is fabricated atop the layer of dielectric material which is above N-type active-region semiconductor structure108. In some embodiments, then, in operation712of method700, a first and a second gate terminals are fabricated. Additionally or alternatively, the first and second gate terminals intersect the first and second-type active-region semiconductor structures. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, gate terminals110A and110B are fabricated in operation712, and gate terminal110B intersects N-type active-region semiconductor structure108, and gate terminal110A intersects P-type active region semiconductor structure106. In some embodiments, gate connection131is fabricated together with gate terminals110A and110B, resulting in a continuous gate structure extending around the stacked active-region semiconductor structures106,108. In at least one embodiment, where gate terminals110A and110B are not to be interconnected, gate connection131is not fabricated, or is fabricated and then removed. In some embodiments, a source terminal and a drain terminal of a bottom device (referred to herein as bottom MDs) are fabricated in operation714. In some embodiments, the source terminal and drain terminal of the bottom device intersects the second-type active-region semiconductor structure. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, source terminal114B and drain terminal130B are fabricated, and source terminal114B and drain terminal130B intersect N-type active-region semiconductor structure108and form the source terminal and drain terminal of first transistor102(bottom device). In some embodiments, in operation720of method700, an MDLI interconnect is fabricated. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, MDLI138that will connected drain terminals130B and130A is fabricated. In some embodiments, then, in operation730of method700, one or more VTB (via-top-to-bottom) are fabricated to electrically connect a back-side conductive line with a source terminal or drain terminal of the top device. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, VTB134that will connect drain terminal130A and signal conductive line132B is fabricated. In some embodiments, in operation732of method700, a source terminal and a drain terminal of a top device (referred to herein as top MDs) are fabricated. In some embodiments, the source terminal and drain terminal of the top device intersect the first-type active-region semiconductor structure. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, source terminal114A and drain terminal130A are fabricated, and source terminal114A and drain terminal130A intersect P-type active-region semiconductor structure106and form the source terminal and drain terminal of second transistor104(top device). In some embodiments, then, in operation734of method700, one or more VD and/or VG vias are fabricated to electrically connect front-side conductive lines (to be formed later) with the source terminal, drain terminal and/or gate terminal of the top device. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, via128A that will connect drain terminal130A and signal conductive line132B, via122A that will connect gate terminal110A to signal conductive line109A, and via124A that will connect source terminal114A to signal conductive line109B are fabricated. In some embodiments, then, in operation740of method700, one or more VBT (via-bottom-to-top) are fabricated to electrically connect a front-side conductive line with a bottom MD, i.e., a source terminal or a drain terminal of a bottom device. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.3B, VBT324A that will connect source terminal314B and signal conductive line309E is fabricated. In some embodiments, a first insulating material is deposited and covers the gate terminal, drain terminal and source terminal of the top device, as well as one or more VD, VG, VBT vias that have been fabricated. Additionally or alternatively, after operation740, in operation750of method700, a front-side metal layer is deposited over the first insulating material. In some embodiments, the front-side metal layer is patterned to form a front-side power conductive line, one or more front-side signal conductive lines, and a front-side shielding conductive line which are in electrical contact with corresponding VD, VG, and/or VBT vias. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, front-side power conductive line107A, front-side signal conductive lines (109A and109B), and front-side shielding conductive line112A are fabricated in front-side metal layer105A overlying the insulating material covering gate terminal110A, drain terminal130A and source terminal114A. Additionally or alternatively, front-side power conductive line107A is conductively connected to drain terminal130A through a top VD via128A, and front-side signal conductive line109A is conductively connected to gate terminal110A through a top VG via122A. In some embodiments, after operations740and750, the wafer containing the substrate is flipped in operation755. Additionally or alternatively, then, the process flow proceeds to760. In some embodiments, then, in operation760of method700, one or more bottom vias are fabricated to electrically connect back-side conductive lines (to be formed later) with the source terminal, drain terminal and/or gate terminal of the bottom device. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1AandFIGS.1C-1E, one or more of bottom VD via126that will connect drain terminal130B and power conductive line120, bottom VD via136that will connect source terminal114B to signal conductive line132B, bottom VD via140that will connect source terminal114B to power conductive line120, and bottom VG via142that will connect gate terminal110B to signal conductive line132B, are fabricated. In operation770of method700, a back-side metal layer is formed on a backside of the substrate. In some embodiments, the back-side metal layer is patterned to form a back-side power conductive line, one or more back-side signal conductive line, and/or a back-side shielding conductive line which are in electrical contact with corresponding bottom vias. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.3AandFIGS.3C-3F, the back-side power conductive line320A, one or more back-side signal conductive lines (332A and332B), and back-side shielding conductive line333A are fabricated in back-side metal layer316A at the backside of the substrate. Additionally or alternatively, back-side power conductive line320A is conductively connected to source terminal314B through a bottom VD via340A. In accordance with some embodiments,FIG.7Bis a flowchart of a method780of manufacturing an IC. Additionally or alternatively, additional operations are performed before, during, and/or after method780depicted inFIG.7B, and that some other processes are only briefly described herein. In some embodiments, in operation782of method780, a first transistor of a first conductivity type is formed over a substrate. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1A,FIGS.1C-1E, andFIG.2Cfirst transistor102is formed over substrate260. In some embodiments, in operation784of method780, a second transistor of a second conductivity type, where the second conductivity type is different from the first conductivity type, is formed over the first transistor to obtain a transistor stack. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1A,FIGS.1C-1E, andFIG.2Csecond transistor104is formed over first transistor102. In some embodiments, in operation786of method780, a metal zero (M0) layer is deposited and patterned over the transistor stack. Additionally or alternatively, the metal zero (M0) layer includes a power conductive line to route power to the transistor stack, one or more signal conductive lines to route signals to the transistor stack, and a shielding conductive line to shield the routed signals on the one or more signal conductive lines. In some embodiments, the one or more signal conductive lines are between the power conductive line and the shielding conductive line. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1A,FIGS.1C-1E, andFIG.2Cmetal layer116is formed under first transistor102and second transistor104. The metal layer105includes a power conductive line107, one or more signal conductive lines109A,109B and shielding conductive line112. In some embodiments, in operation788of method780, a backside metal zero (M0) layer is deposited and patterned below the substrate and underneath the transistor stack. Additionally or alternatively, the back-side metal zero (BM0) layer includes a power conductive line to route power to the transistor stack and one or more signal conductive lines to route signals to the transistor stack. In some embodiments, as a non-limiting example, in the embodiments as shown inFIG.1A,FIGS.1C-1E, andFIG.2Cmetal layer116is formed under first transistor102and second transistor104. The metal layer116includes a power conductive line120and one or more signal conductive lines132A,132B. FIG.8is a block diagram of an electronic design automation (EDA) system800in accordance with some embodiments. Additionally or alternatively, EDA system800includes an APR system. In some embodiments, methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system800, in accordance with some embodiments. In some embodiments, EDA system800is a general purpose computing device including a hardware processor802and a non-transitory, computer-readable storage medium804. Additionally or alternatively, storage medium804, amongst other things, is encoded with, i.e., stores, computer program code806, i.e., a set of executable instructions. In some embodiments, execution of computer program code806by hardware processor802represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). In some embodiments, processor802is electrically coupled to computer-readable storage medium804via a bus808. Additionally or alternatively, processor802is also electrically coupled to an I/O interface810by bus808. In some embodiments, a network interface812is also electrically connected to processor802via bus808. Additionally or alternatively, network interface812is connected to a network814, so that processor802and computer-readable storage medium804are capable of connecting to external elements via network814. In some embodiments, processor802is configured to execute computer program code806encoded in computer-readable storage medium804in order to cause EDA system800to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor802is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, computer-readable storage medium804is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium804includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium804includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, storage medium804stores computer program code806configured to cause EDA system800(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium804also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium804stores library807of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium804stores one or more layout diagrams809corresponding to one or more layout diagrams disclosed herein. In some embodiments, EDA system800includes I/O interface810. Additionally or alternatively, I/O interface810is coupled to external circuitry. In one or more embodiments, I/O interface810includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor802. In some embodiments, EDA system800also includes network interface812coupled to processor802. Additionally or alternatively, network interface812allows EDA system800to communicate with network814, to which one or more other computer systems are connected. In some embodiments, network interface812includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EDA systems800. In some embodiments, EDA system800is configured to receive information through I/O interface810. Additionally or alternatively, the information received through I/O interface810includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor802. In some embodiments, the information is transferred to processor802via bus808. Additionally or alternatively, EDA system800is configured to receive information related to a UI through I/O interface810. In some embodiments, the information is stored in computer-readable medium804as user interface (UI)842. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system800. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout diagram generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. FIG.9is a block diagram of an integrated circuit (IC) manufacturing system900, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system900. In some embodiments, inFIG.9, IC manufacturing system900includes entities, such as a design house920, a mask house930, and an IC manufacturer/fabricator (“fab”)950, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device960. Additionally or alternatively, the entities in system900are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. Additionally or alternatively, the communications network includes wired and/or wireless communication channels. In some embodiments, each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house920, mask house930, and IC fab950is owned by a single larger company. In some embodiments, two or more of design house920, mask house930, and IC fab950coexist in a common facility and use common resources. In some embodiments, design house (or design team)920generates an IC design layout diagram922. Additionally or alternatively, IC design layout diagram922includes various geometrical patterns designed for an IC device960. In some embodiments, the geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device960to be fabricated. Additionally or alternatively, the various layers combine to form various IC features. For example, a portion of IC design layout diagram922includes various IC features, such as an active region, gate terminal, source terminal and drain terminal, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers on the semiconductor substrate. In some embodiments, design house920implements a proper design procedure to form IC design layout diagram922. Additionally or alternatively, the design procedure includes one or more of logic design, physical design or place and route. In some embodiments, IC design layout diagram922is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram922is expressed in a GDSII file format or DFII file format. In some embodiments, mask house930includes mask data preparation932and mask fabrication944. Additionally or alternatively, mask house930uses IC design layout diagram922to manufacture one or more masks945to be used for fabricating the various layers of IC device960according to IC design layout diagram922. In some embodiments, mask house930performs mask data preparation932, where IC design layout diagram922is translated into a representative data file (“RDF”). Additionally or alternatively, mask data preparation932provides the RDF to mask fabrication944. In some embodiments, mask fabrication944includes a mask writer. Additionally or alternatively, a mask writer converts the RDF to an image on a substrate, such as a mask (reticle)945or a semiconductor wafer953. In some embodiments, the design layout diagram922is manipulated by mask data preparation932to comply with particular characteristics of the mask writer and/or requirements of IC fab950. Additionally or alternatively, inFIG.9, mask data preparation932and mask fabrication944are illustrated as separate elements. In some embodiments, mask data preparation932and mask fabrication944are collectively referred to as mask data preparation. In some embodiments, mask data preparation932includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that arise from diffraction, interference, other process effects and the like. Additionally or alternatively, OPC adjusts IC design layout diagram922. In some embodiments, mask data preparation932includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, mask data preparation932includes a mask rule checker (MRC) that checks the IC design layout diagram922that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram922to compensate for limitations during mask fabrication944, which undoes part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, mask data preparation932includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab950to fabricate IC device960. Additionally or alternatively, LPC simulates this processing based on IC design layout diagram922to create a simulated manufactured device, such as IC device960. In some embodiments, the processing parameters in LPC simulation include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram922. In some embodiments, the above description of mask data preparation932has been simplified for the purposes of clarity. In some embodiments, mask data preparation932includes additional features such as a logic operation (LOP) to modify the IC design layout diagram922according to manufacturing rules. Additionally, the processes applied to IC design layout diagram922during mask data preparation932are executed in a variety of different orders. In some embodiments, after mask data preparation932and during mask fabrication944, a mask945or a group of masks945are fabricated based on the modified IC design layout diagram922. In some embodiments, mask fabrication944includes performing one or more lithographic exposures based on IC design layout diagram922. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)945based on the modified IC design layout diagram922. Additionally or alternatively, mask945is formed in various technologies. In some embodiments, mask945is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. Additionally or alternatively, a radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask945includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask945is formed using a phase shift technology. In a phase shift mask (PSM) version of mask945, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask is attenuated PSM or alternating PSM. Additionally or alternatively, the mask(s) generated by mask fabrication944is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer953, in an etching process to form various etching regions in semiconductor wafer953, and/or in other suitable processes. In some embodiments, IC fab950is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC fab950is a semiconductor foundry. For example, there is a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility provides the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility provides other services for the foundry business. In some embodiments, IC fab950includes fabrication tools952configured to execute various manufacturing operations on semiconductor wafer953such that IC device960is fabricated in accordance with the mask(s), e.g., mask945. In various embodiments, fabrication tools952include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein. In some embodiments, IC fab950uses mask(s)945fabricated by mask house930to fabricate IC device960. Additionally or alternatively, IC fab950at least indirectly uses IC design layout diagram922to fabricate IC device960. In some embodiments, semiconductor wafer953is fabricated by IC fab950using mask(s)945to form IC device960. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram922. In some embodiments, semiconductor wafer953includes a silicon substrate or other proper substrate having material layers formed thereon. Additionally or alternatively, semiconductor wafer953further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). In some embodiments, details regarding an integrated circuit (IC) manufacturing system (e.g., system900ofFIG.9), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 2066640838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. In some embodiments, a circuit structure includes a substrate that includes a first transistor stack over the substrate where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack. The plurality of first conductive lines over the first transistor stack includes a power conductive line configured to route power to the first transistor stack; one or more signal conductive lines configured to route signals to the first transistor stack; and a shielding conductive line configured to shield the routed signals on the one or more signal conductive lines, where the one or more signal conductive lines are between the power conductive line and the shielding conductive line. In some embodiments, a circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines disposed in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines. In some embodiments, a method includes forming a first transistor over a substrate, where the first transistor is a first conductivity type. The method also includes forming a second transistor over the first transistor to obtain a transistor stack, where the second transistor is a second conductivity type different from the first conductivity type. The method also includes forming, in a metal layer and over the transistor stack, a power conductive line to route power to the transistor stack; one or more signal conductive lines to route signals to the transistor stack; and a shielding conductive line to shield the routed signals on the one or more signal conductive lines, where the one or more signal conductive lines are between the power conductive line and the shielding conductive line. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 147,610 |
11862563 | DETAILED DESCRIPTION Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer of a semiconductor device is necessarily shown. “An embodiment”, “various embodiments” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First”, “second”, “third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and “coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. One embodiment of the invention is a cobalt interconnect which includes a manganese (Mn) based adhesion layer and a cobalt fill material. The adhesion layer (sometimes also referred to herein as a barrier layer or wetting layer) may include various Mn based compositions such as, for example, Mn, manganese nitride (MnN), or manganese silicon nitride (MnSixNy). The Mn based adhesion layer may comprise a film deposited in patterned backend interconnect structures. These interconnect structures may be metalized with cobalt. The Mn based layer adheres well to the interlayer dielectric (ILD) that helps form the interconnect in some embodiments. The Mn based layer also provides wetting to the cobalt metal. Thus, the Mn based adhesion layer helps achieve robust gap filling of interconnect structures at small scales such as 22 nm, 14 nm, 10 nm and beyond. An embodiment includes a cobalt interconnect that includes a cobalt plug layer and a cobalt fill material. The plug layer is formed from a different composition and/or by a different process than that used to for the cobalt fill material. Such cobalt interconnects are advantageous since they have a low resistance (e.g., lower than tungsten) and are highly resistive to electromigration (e.g., more resistive to electromigration than copper), enabling fabrication of high performance interconnect structures. As dimensions scale in conventional interconnect processing, the high resistance of traditional barrier layers (e.g., TNT barrier layers) can impact the performance of conventional copper interconnects to greater extents. However, lower resistance Mn layers may mitigate these resistance issues. In a first aspect, a conformal Mn based adhesion layer is formed in an opening in a dielectric layer. A cobalt-based fill material is then deposited or grown on the Mn based adhesion layer to form a cobalt interconnect. FIGS.1A-1Eillustrate a method of forming a cobalt interconnect with a Mn based adhesion layer and a cobalt-containing fill layer according to embodiments of the present invention.FIG.1Aillustrates a substrate106with top surface118that may be used as a substrate on which a cobalt interconnect can be formed. Substrate106can include any portion of a partially fabricated IC on which a cobalt interconnect is ultimately fabricated. For example, substrate106will typically include, or have formed thereon, active and passive devices. As depicted inFIG.1A, a conductive region150is included in substrate106, on to which a cobalt interconnect is ultimately formed. In one such embodiment, the substrate106has been processed through front end of line (FEOL), and the conductive region150is a diffusion region formed in a crystalline semiconductor substrate or layer (e.g., the conductive region is a source or drain region of a transistor). In another such embodiment, the conductive region150is an underlying metal line in a back end of line (BEOL) metallization structure, as is described in greater detail below in association withFIG.2. Thus, while portion150is at times referred to herein as a “conductive region150” this may or may not indicate that area150is any more or less conductive than the rest of106. Also, the use of150is not intended to indicate that150is necessarily nonmonolithic with106or was formed with a different process or non-simultaneously with106. For example, when106is an interconnect line area150is monolithic with106and structurally and functionally indistinguishable from the rest of106. However, area150may also be an area doped differently than the rest of106when150is to serve as a source or drain. The above clarification is provided to avoid excessive figures and to otherwise provide clarity in succinct manner. Although embodiments may be ideally suited for fabricating semiconductor ICs such as, but not limited to, microprocessors, memories, charge-coupled devices (CCDs), system on chip (SoC) ICs, or baseband processors, other applications can also include microelectronic machines, MEMS, lasers, optical devices, packaging layers, and the like. Embodiments may also be used to fabricate individual semiconductor devices (e.g., a cobalt structure described herein may be used to fabricate a gate electrode of a metal oxide semiconductor (MOS) transistor). Referring again toFIG.1A, a dielectric layer102is formed above substrate106. The dielectric layer102may be composed of any suitable dielectric or insulating material such as, but not limited to, silicon dioxide, SiOF, carbon-doped oxide, a glass or polymer material, and the like. An opening is formed in the dielectric layer. The opening exposes the conductive region150to which contact (indirect or direct) by a cobalt interconnect is ultimately made. In one embodiment, as depicted inFIG.1A, the opening includes a lower opening114(e.g., a via hole or slot) with sidewalls116and an upper opening110(e.g., a metal line trench) with sidewalls112, as is common in a dual damascene process. Although two openings are depicted (or a single opening with varying widths), it is to be appreciated that a single opening may instead be formed in the dielectric layer102(e.g., as is used in a single damascene approach where only a line or a via, but not both, is fabricated in a single operation). The opening or openings may be fabricated in dielectric layer102by well known lithography and etch processing techniques typically used in damascene and dual damascene type fabrication. Although only a single dielectric layer102is depicted, multiple layers of the same or differing dielectric materials may instead be used (e.g., a first dielectric layer having opening114therein, and a second dielectric layer having opening110therein). Additionally, in an embodiment, and as depicted inFIG.1A, the dielectric layer102is formed on an etch stop layer104disposed on substrate106. The etch stop layer104may be composed of a material such as silicon nitride or silicon oxynitride. Referring toFIG.1B, a Mn based adhesion layer120(e.g., an adhesion layer including Mn, MnN, MnSixNyand the like) is deposited. In other systems a seed layer may be formed on a TNT based adhesion layer. Seed layers, such as the seed layer disclosed in U.S. patent application Ser. No. 13/730,184, may facilitate formation of fill material. However, no such seed layer is needed in the embodiment ofFIG.1B. Nor is deposition of an alloy between an adhesion layer and a seed layer needed in the embodiment ofFIG.1B. Thus, as will be seen below, a Mn based adhesion layer may directly contact ILD102and directly contact cobalt fill (described below) without the need for a TNT based adhesion layer, any seed layer, or any alloy layer between a TNT based adhesion layer and a seed layer. InFIG.1Bthe Mn based adhesion layer120may be formed on a top surface108of the dielectric layer102as well as on the exposed top surface118of the substrate106(e.g., on conductive region150). While106is referred to as “substrate” in another embodiment106could be a metal interconnect line, and the like. The Mn based adhesion layer120is also formed on the sidewalls116of the upper opening114, and the sidewalls112of the lower opening110. Mn based adhesion layer120may be a conformal layer composed of a material including Mn, MnN, MnSixNy, MnSixOy(e.g., Mn2[SiO4], MnSiO3), other Mn based silicates, and the like. In an embodiment with the adhesion layer including Mn, the Mn content may include 90-100% Mn, where contamination (i.e., the remaining 10%) may include C, H, O and combinations thereof. In an embodiment with the adhesion layer including MnNx, the Mn may compose 0-50% Mn and the N may compose 0-50%. In an embodiment with the adhesion layer including MnNx, the adhesion layer may include Mn4N or Mn3N2. In an embodiment with the adhesion layer including MnNxSiythe Mn and N may include up to 50% with the Si constituting the remainder of the material. In an embodiment Mn, N, and Si may be included with one another in various adhesion multilayer combinations such as bilayers or trilayers (e.g., an adhesion layer includes one sublayer including MnN and another sublayer including Mn), (e.g., one adhesion layer including a sublayer having Mn and N and another sublayer including primarily Mn), (e.g., one adhesion layer including a sublayer including MnNxSiyand another sublayer including primarily Mn), and the like. As used herein, % of composition refers to atomic %. In one embodiment, the Mn based adhesion layer120is formed to a thickness less than 3 nm, and typically 1 nm to 3 nm. In an embodiment thickness ranges for layer120(whether layer120includes a single layer or multiple sublayers such as one sublayer including MnN and another immediately adjacent sublayer including Mn) may range from 0.1 A to 50 A. In an embodiment layer120is between 10 A-20 A including, for example, 10, 12, 14, 16, 18, or 20 A. In an embodiment, conductive region150includes at least some germanium (e.g., an exposed doped silicon germanium or doped germanium region, or a metal germanide region). In an embodiment, conductive region150includes at least some silicon (e.g., an exposed doped silicon region, or a metal silicide region). The layer120may be deposited or grown by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating or other suitable process that deposits conformal thin films. In an embodiment, the layer120is deposited to form a high quality conformal layer that sufficiently and evenly covers all exposed surfaces within the openings and top surfaces. The adhesion layer may be formed, in one embodiment, by depositing the Mn based material at a slow deposition rate to evenly and consistently deposit the conformal adhesion layer. By forming the layer120in a conformal manner, compatibility of a subsequently formed fill material (such as cobalt) with the underlying structure may be improved. Specifically, the layer120can assist a deposition process by providing appropriate surface energetics for deposition thereon. Deposition recipes of thin films using processes such as CVD, ALD, and PVD may vary depending on the desired process time, thickness, and quality of conformity. For example, utilizing CVD to deposit the adhesion layer120may create a conformal thin film layer more quickly than it would take an ALD process to deposit the same layer; however, the quality of the thin film deposited by the CVD process may be lower than the quality of the thin film deposited by the ALD process. In another embodiment, the layer120is deposited by a PVD process. The PVD process may be performed with an increased distance between the receiving substrate and the corresponding sputter target to form a highly conformal thin film. Referring toFIG.1C, a fill material122may be formed on the exposed surfaces of the adhesion layer120, such that the fill material122completely fills the openings110and114and is formed on the top surface of the adhesion layer120and on the top surface108of dielectric102. A seam124may be formed within the openings110,114during deposition of the fill material122. In an embodiment, the fill material122is composed of a dilute alloy composed of approximately 0.25-5% of a non-cobalt element (e.g., Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, or Pd) with the remainder approximately 95+% cobalt. Such a dilute alloy can involve, either during deposition or processing subsequent to deposition, migration of the non-cobalt species to surfaces of fill122. The migration can provide a diffusion barrier for the cobalt (in addition to adhesion/barrier layer120) and/or be used to enhance adhesion of the cobalt to layer120. Grain boundaries within the cobalt may also be filled by the non-cobalt species. In one embodiment, the fill material122consists essentially only of cobalt. In another embodiment, the fill material122is at least 90% cobalt. In yet another embodiment, the fill material122is composed of at least 50% cobalt. In an embodiment of the invention, the cobalt fill material122may be formed by a process such as, but not limited to, CVD, ALD, PVD, electroplating, or electro-less plating. In one embodiment, the process method used to form the fill material122may be different than the process used to form the layer120. Furthermore, the layer120may be formed conformally, while the fill material122is formed in a non-conformal or bottom up approach. For example, the layer120may be formed by an ALD deposition process that forms a conformal layer on exposed surfaces of the receiving substrate, while the fill material122may be formed by PVD process that directionally sputters the fill material onto the surfaces of the layer120, with greater deposition rates on flat horizontal surfaces as opposed to on more vertically oriented sidewall surfaces. In another example, the layer120may be formed by an ALD deposition process that forms a conformal layer on exposed surfaces of the receiving substrate, while the fill material122may be formed by an electroplating process that grows the fill material from the surfaces of the layer120. In yet another example, the layer120may be formed by a CVD deposition process and the fill material may be formed by a PVD process. In another embodiment, the layer120and the fill material122may be deposited by the same process (e.g. ALD, CVD, or PVD) but with different sets of deposition parameters, such as pressure, deposition rate, temperature, and the like. For example, the layer120and the fill material122may be deposited by a CVD process; however, the set of parameters used in the CVD processing for the adhesion layer120, such as deposition pressure and temperature, may be different than the set of parameters used in the CVD processing for the fill material122. In another example, the layer120and the fill material122are formed by a PVD process, but the layer120may be formed by a PVD process with a larger distance between the target and the receiving substrate than the PVD process used to form the fill material122. In another embodiment, the metal fill material122is formed by a colummated PVD process, while the layer120is formed by a non-colummated PVD process. Or alternatively, the layer120is formed by an ALD process with a lower deposition rate than the deposition rate of the ALD process used to form the fill material122such that the layer120is formed more conformally than the fill material122. Referring toFIG.1D, an anneal process may optionally be performed to reflow the deposited interconnect layer. The seam124fromFIG.1Cmay be removed subsequent to the anneal process, forming a solid structure within openings110and114within dielectric layer102. The anneal process may help grow larger grain structures within the fill material122, decreasing resistivity and expelling impurities from poor grain structures. In one embodiment, the anneal process uses gasses such as nitrogen, hydrogen, and argon. Furthermore, the anneal process may be performed at a temperature less than the thermal budget of the backend structures. For example, in one embodiment, the anneal process is performed at a temperature of room temperature to 300° C., 400° C., 500° C. or more. In another embodiment, the anneal process is performed at a temperature that is higher than the melting point of fill material122but lower than the thermal budget of the backend structures. In various embodiments the anneal process can vary widely (e.g., room temperature to 300° C., 400° C., 500° C. or more for interconnects ranging up to 900° C. for Front end applications). In such embodiments the anneal temperature is not higher than the melting point of the material being annealed as reflow of materials to be annealed can happen at much lower temperatures than the melting point for the material to be annealed. In such embodiments anneal temperatures for the material to be annealed may be less than the thermal budget of backend structures. In yet another embodiment, a cycling technique may optionally be utilized to deposit the interconnect layer122(also referred to as fill layer122) within the openings114and110without the seam124. One cycle may involve one deposition of the fill material122and one anneal process. The anneal operation of one cycle may be set at a temperature and time duration to briefly reflow the fill material to improve step coverage. The deposition operation of one cycle may be a short deposition to deposit less fill material, such that several operations are required to completely fill the via and line openings114and110. In one embodiment, less than 5 cycles are needed to deposit the fill material122without a seam124. Referring toFIG.1E, a chemical mechanical planarization (CMP) process may be performed to remove the fill material122and the adhesion layer120disposed above the top surface108of the dielectric layer102. In one embodiment, the CMP process may be a timed CMP process that is timed to stop at the top surface108of the line dielectric layer. In another embodiment, the CMP process may utilize the top surface108of the line dielectric layer as a stopping layer. Because the thickness of the fill material deposited above the top surface of the line dielectric layer may vary, utilizing the top surface108as a stopping layer may be a more reliable method. In an alternative embodiment, an etch process is used to remove the fill material122and the layer120disposed above the top surface108of the dielectric layer102. FIG.2illustrates a cross-section200of a portion of an IC structure with cobalt metal interconnects according to an embodiment of the present invention. A stack of dielectric layers102includes metal interconnects having adhesion layers120and metal (e.g., cobalt) fill layers124. The portion of the IC structure shown inFIG.2can be a portion of a back end of line (BEOL) metallization structure as found, for example, in a microprocessor die or memory die. FIG.3is a flow chart300illustrating a method of forming a cobalt metal interconnect according to an embodiment of the present invention. At302, an opening is formed in a dielectric layer to expose a conductive region in a substrate (or on an additional metal interconnect). At304, a Mn based adhesion/barrier layer is formed over the substrate, in contact with the conductive region, as well as over the dielectric layer and on sidewalls of the opening. At306, a fill material is formed on the adhesion layer and fills the opening. The fill material is composed of a cobalt-based material. At308, in an optional embodiment, heat is applied to reflow the fill material. At310, the fill material and adhesion layer material disposed above an upper surface of the dielectric layer are removed. In an embodiment a cobalt-based plug is formed in a lower portion (e.g., a via hole or slot) of an opening in a dielectric layer. A cobalt-based conductive line is then formed on the cobalt-based plug, in an upper portion (e.g., a metal line trench) of the opening, to form a cobalt interconnect. For example,FIGS.4A-4Dillustrate a method of forming a cobalt metal interconnect according to an embodiment of the invention. The method begins with the same structure as illustrated and described in association withFIG.1B, which includes adhesion layer120and will not be described again for the sake of brevity. Referring toFIG.4A, a plug420is formed on adhesion layer120. In an embodiment, as depicted, the plug420is formed only within the lower opening114of the dielectric layer102such that the lower opening114is completely filled with plug material420. In another embodiment, however, the top surface of the plug420may not be planar with the top surface of the lower opening114. For example, the top surface of the plug420may be higher or lower than the top surface of the lower opening. The top surface of the plug420may be at, above, or below the horizontal top surface of layer120where layer120is horizontally disposed at the top of114and bottom of110. As depicted inFIG.4Athe plug420has a top surface just below the horizontal top surface of layer120where layer120is horizontally disposed at the top of114and bottom of110. In another embodiment, the top surface of the plug420may form a mushroom-like dome as a result of the growth profile during formation of plug420. In an embodiment, plug420is formed in a bottom-up approach. That is, the plug420is not formed by conformal deposition. For example, in one embodiment, the formation of plug420is performed by selectively depositing on, and then growing from, the surface of layer120directly above the conductive region150. In a specific embodiment, the plug420is formed by electrolessly plating the plug material onto an exposed and compatible surface of layer120. As an example, the conductive region150has an upper metalized or metal-containing surface such as cobalt (Co), copper (Cu) or Tungsten (W), and a cobalt-based plug420is formed by electroless deposition involving bottom-up growth from the layer120above the metalized or metal-containing surface of conductive region150. In other embodiments, other suitable bottom-up fill and growth deposition approaches may be used such as, but not limited to, electroplating. A bottom-up fill approach is one in which a deposition rate is faster on planar or flat surfaces than on vertical sidewall surfaces. The plug420may be a cobalt-based plug composed of at least 50% cobalt. In a particular embodiment, the plug420is composed of at least 90% cobalt. In any such cases, the non-cobalt remainder of the plug420composition, if any, can include one or more of Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, or Pd. In another embodiment, the plug420is composed of a cobalt-based compound or alloy material. For example, in one embodiment, the plug420is composed of a dilute alloy composed of approximately 0.25-5% of a non-cobalt element, such as those listed above, with the remainder approximately 95+% cobalt, is used. Such a dilute alloy can involve, either during deposition or processing subsequent to deposition, migration of the non-cobalt species to surfaces or interfaces of the cobalt plug. The migration can provide a diffusion barrier for the cobalt and/or be used to enhance adhesion of the cobalt to layer120. Grain boundaries within the cobalt may also be filled by the non-cobalt species. In other embodiments, however, the plug420may include less than 50% cobalt, but still be referred to as a cobalt-based material. Exemplary embodiments of cobalt-based compound plug420materials include cobalt silicide or cobalt germanide plug materials. In a specific such embodiment, conductive region150includes at least some germanium (e.g., an exposed doped silicon germanium or doped germanium region, or a metal germanide region), and the plug420material is a cobalt germanide layer. In another specific such embodiment, conductive region150includes at least some silicon (e.g., an exposed doped silicon region, or a metal silicide region), and the plug420material is a cobalt silicide layer. Exemplary embodiments of cobalt-based alloy plug420materials include cobalt alloyed with one or more of the following: Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, or Pd. In the above described embodiments, the cobalt plug420may have a small grain structure. In an embodiment the above mentioned dopant (i.e., the 0.25-5% of a non-cobalt element) could be used without layer120so that cobalt would adhere directly to sidewall116as well as portion150. In an embodiment the dopant essentially creates a layer120(an adhesion layer) by diffusion to interfaces such as interfaces at150and116. In one embodiment the dopant forms a layer with portion150. In another embodiment the dopant makes no layer formation with150so that the barrier is bottomless and plug420directly contacts area150. Referring toFIG.4B, pretreatment422may optionally be performed on the exposed top surface of the plug420and layer120. Pretreatment may be performed by a plasma process or ion bombardment to enhance adhesion of a later formed compound to the treated surface. In one embodiment, pretreatment may be performed in a plasma chamber at a temperature ranging from room temperature up to approximately 300° C., 400° C., 500° C. or more for approximately 20 to 60 seconds utilizing, for example, H2/He plasma, Ar plasma, NH3plasma, N2plasma, and/or combinations thereof. In another embodiment, the pretreatment may include Ar ion bombardment. It is to be understood that such pretreatment may be performed at other stages of the process flow (e.g., prior to forming plug materials). In an embodiment the pretreatment is performed before layer120is formed. However, in other embodiments a treatment of layer120can be quite beneficial to density without affecting dielectrics such as layer102. Referring toFIG.4C, a fill material424is formed on the plug420and layer120within upper opening110. A seam426may be formed within the upper opening110subsequent to deposition of the fill material424. In one embodiment, fill material424is composed of a material comprising cobalt. For example, fill material may be composed of, and deposited by, materials and processes described above for fill material122. Furthermore, the fill material424may differ from the plug420material by composition and/or deposition technique. An anneal process may optionally be performed to reflow the deposited fill material424. The seam426fromFIG.4Cmay be removed subsequent to the anneal process, forming a solid structure within openings110and114within dielectric layer102. The anneal process may enable growth of larger grain structures within the fill material424, decreasing resistivity and expelling impurities from otherwise poor grain structures. In one embodiment, the anneal process involves use of a forming gas such as, but not limited to, nitrogen, hydrogen, or argon. Furthermore, the anneal process may be performed at a temperature less than the thermal budget of the backend structures. For example, in one embodiment, the anneal process is performed at a temperature of room temperature to 300° C., 400° C., 500° C. or more. In another embodiment, the anneal process is performed at a temperature that is higher than the melting point of fill material424but lower than the thermal budget of the backend structures. In embodiments the anneal temperature is not higher than the melting point of the material being annealed as reflow of materials to be annealed can happen at much lower temperatures than the melting point for the material to be annealed. In such embodiments anneal temperatures for the material to be annealed may be less than the thermal budget of backend structures. In yet another embodiment, a cycling technique is optionally utilized to deposit the fill material424within the opening110without the seam426. One cycle may involve a single deposition of the fill material424and a single anneal process. The anneal operation of one cycle may be set at a temperature and time duration to briefly reflow the fill material424to improve step coverage. The deposition operation of one cycle may be a short deposition to deposit less fill material424, such that several operations are required to completely fill the upper opening110. In one embodiment, less than 5 cycles are needed to deposit the fill material424without a seam426. Referring toFIG.4D, a CMP process may be performed to remove the fill material424above the top surface of layer120to provide the cobalt-based structure428. In one embodiment, the CMP process may be a timed CMP process that is timed to stop at the top surface108of the line dielectric layer. In another embodiment, the CMP process may utilize the top surface108of the dielectric layer102as a stopping layer. Because the thickness of the fill material deposited above the top surface108of the dielectric layer102may vary, utilizing the top surface108as a stopping layer may be a more reliable method. In an alternative embodiment, an etch process is used to remove the fill material424above the top surface108of the dielectric layer102. In an embodiment a cobalt-based plug is formed in a lower portion (e.g., a via hole or slot) of an opening in a dielectric layer. An adhesive layer is then formed in an upper portion (e.g., a metal line trench) of the opening, over the cobalt-based plug. A cobalt-based conductive line is then formed on the portion of the adhesive layer that is directly over the plug to fill the upper portion of the opening to form a cobalt interconnect. For example,FIGS.5A-5Dillustrate a method of forming a cobalt interconnect with a Mn based adhesion layer and a cobalt containing fill layer according to an embodiment of the invention. The method begins with the same structure as illustrated and described in association withFIG.1A. Next, referring toFIG.5A, the cobalt-based plug420is formed in the lower opening114of the dielectric layer102, on the conductive region150of substrate106. However, in another embodiment the adhesion layer be first formed along the side walls of dielectric102and/or on top of portion150before plug420is formed. Referring toFIG.5B, a Mn based adhesion layer524(e.g., Mn, MnN, MnSixNyMnSixOy(e.g., Mn2[SiO4], MnSiO3), other Mn based silicates, and the like) is deposited conformally with the structure ofFIG.5A. For example, in one embodiment, the Mn based adhesion layer524is formed in the upper opening114of the dielectric layer102and on the exposed plug420. The composition and method of forming the adhesion layer524may be as described for adhesion layer120ofFIG.1B. Referring toFIG.5C, a fill material526is formed on the adhesion layer524, within upper opening110, and on the top surface108of the dielectric layer102. A seam528may be formed within the opening110subsequent to deposition of the fill material526. The composition and method of forming the fill material layer526may be as described for fill material122of FIG.1C. Furthermore, although in an embodiment the plug420and the fill material526are all cobalt-based, they may all differ from one another by composition and/or deposition technique. An anneal process may optionally be performed to reflow the deposited fill material526. The seam528fromFIG.5Cmay be removed subsequent to the anneal process, forming a solid structure within opening110of dielectric layer102. The anneal process may enable growth of larger grain structures within the fill material526, decreasing resistivity and expelling impurities from poor grain structures. In one embodiment, the anneal process involves a use of gas such as, but not limited to, nitrogen, hydrogen, or argon. Furthermore, the anneal process may be performed at a temperature less than the thermal budget of the backend structures. For example, in one embodiment, the anneal process is performed at a temperature of room temperature to 300° C., 400° C., 500° C. or more. In another embodiment, the anneal process is performed at a temperature that is higher than the melting point of fill material526but lower than the thermal budget of the backend structures. In embodiments the anneal temperature is not higher than the melting point of the material being annealed as reflow of materials to be annealed can happen at much lower temperatures than the melting point for the material to be annealed. In such embodiments anneal temperatures for the material to be annealed may be less than the thermal budget of backend structures. In yet another embodiment, a cycling technique may be utilized to deposit the fill material526within the opening110without the seam528. One cycle may involve one deposition of the fill material526and one anneal process. The anneal operation of one cycle may be set at a temperature and time duration to briefly reflow the fill material to improve step coverage. The deposition operation of one cycle may be a short deposition to deposit less fill material, such that several operations are required to completely fill the opening510. In one embodiment, less than 5 cycles are needed to deposit the fill material526without a seam528. Referring toFIG.5D, a CMP process may be performed to remove the fill material526and the adhesion layer524disposed above the top surface108of the dielectric layer102to provide the cobalt-based structure530. In one embodiment, the CMP process may be a timed CMP process that is timed to stop at the top surface108of the dielectric layer102. In another embodiment, the CMP process may utilize the top surface108of the dielectric layer102as a stopping layer. Because the thickness of the fill material deposited above the top surface108of the dielectric layer102may vary, utilizing the top surface108as a stopping layer may be a more reliable method. In an alternative embodiment, an etch process is used to remove the fill material526and the layer524disposed above the top surface108of the dielectric layer102. FIG.6is a flow chart600illustrating a method of forming a cobalt metal interconnect according to an embodiment of the present invention. At602, an opening is formed in a dielectric layer to expose a conductive region in a substrate. At604, a cobalt plug is formed in a lower portion of the opening, in contact with the conductive region. At605a Mn based adhesion layer (e.g., Mn, MnN, MnSixNyand the like) is formed in the upper portion of the opening. At606, a fill material is formed on the plug and adhesion layer to fill the opening. The fill material is composed of a cobalt-based material. At608, in an optional embodiment, heat is applied to reflow the fill material. At610, the fill material disposed above an upper surface of the dielectric layer is removed. In one such embodiment, the fill material and the plug both include cobalt, but have different material compositions. In another such embodiment, the fill material and the plug both include cobalt, but are formed by different deposition or growth techniques. In yet another such embodiment, the fill material and the plug both include cobalt, but have different material compositions and are formed by different deposition or growth techniques. In an embodiment a metal gate electrode of a semiconductor device is composed, as least partially, of cobalt. That is, embodiments of the present invention need not be limited to forming cobalt-based interconnects. In an example,FIG.7depicts a metal oxide semiconductor field effect transistor (MOS-FET)700fabricated on a substrate702, in accordance with an embodiment of the present invention. A gate dielectric layer704is disposed above a channel region706, and a gate electrode708is disposed above gate dielectric layer704. Gate dielectric layer704and gate electrode708may be isolated by gate isolation spacers710. Tip extensions712may be formed by implanting dopant atoms into substrate702. Source and drain regions (e.g., strain-inducing source/drain regions720) may be formed by selectively growing an epitaxial film in etched-out portions of substrate702and are doped either in situ or after epitaxial film growth, or both. In an embodiment tip extensions712may be formed simultaneously with the source and drain regions to create “epi” tip extensions. In typical MOS-FETs, the channel region706is composed of a semiconductor material, such as single crystalline silicon. In an embodiment, the gate electrode708is a metal gate electrode (e.g., the workfunction of the gate electrode708is based on a metal or metal-containing layer). In one such embodiment, the metal gate electrode is composed, at least somewhat, of cobalt. For example, in a specific embodiment, the metal gate electrode708includes a Mn based adhesion layer (e.g., Mn, MnN, MnSixNyand the like as described above)708A and a cobalt fill metal thereon708B. For example, the cobalt-based material or film708B is composed of at least 90% cobalt. In a specific such embodiment, the cobalt-based material or film708B is composed of a dilute alloy having approximately 0.25-5% of a non-cobalt element, with the remainder approximately 95+% cobalt. Also, it is to be understood that the MOS-FET700may be a planar device or include a three-dimensional body (e.g., as in a double-gate, fin-fet, tri-gate, or gate-all-around transistor). As such, the substrate702may be a planar substrate or depict a cross-sectional view of a three-dimensional body. Finally, it is to be understood that only several features of the MOS-FET700are depicted for clarity. It is to be understood that isolation layers, e.g., interlayer dielectric layer740, and metallization routing layers used for integrating MOS-FET700into, e.g., an integrated circuit may also be included, as is well known in the art. Various cobalt based embodiments may be included in, for example, a mobile computing node such as a cellular phone, Smartphone, tablet, Ultrabook®, notebook, laptop, personal digital assistant, and mobile processor based platform. Example 1 includes a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. In an embodiment the dielectric directly contacts the substrate but in other embodiments one or more layers are between the dielectric and the substrate. In an embodiment the additional interconnect structure may include a via, a trench filled with metal (interconnect line), and the like. While examples have included dual damascene approaches the opening addressed immediately above need not have varying widths such as those found in, for example,FIG.1or the line over via commonly associated with dual damascene processes. As explained below, saying “an adhesive layer, comprising manganese, disposed over the conductive region” does not necessarily mean manganese will be in the portion of the adhesive layer that is over the conductive region. For example, “an adhesive layer, comprising manganese, disposed over the conductive region” is still satisfied if manganese in not in the adhesion layer portion over the conductive region but is in the adhesion layer that is on the sidewalls. In example 2 the subject matter of Example 1 can optionally include wherein the fill material is composed of at least 50 atomic % cobalt. In example 3 the subject matter of Examples 1-2 can optionally include wherein the adhesion layer includes at least one element selected from a group consisting of silicon, nitrogen, carbon, hydrogen, and oxygen. In example 4 the subject matter of Examples 1-3 can optionally include wherein the adhesion layer is no thicker than 50 A. In example 5 the subject matter of Examples 1-4 can optionally include wherein the adhesion layer directly contacts the fill material. In example 6 the subject matter of Examples 1-5 can optionally include wherein the adhesion layer directly contacts the conductive region. In another version of example 6 the subject matter of Examples 1-5 can optionally include wherein the adhesion layer directly contacts the conductive region and the dielectric layer. In example 7 the subject matter of Examples 1-6 can optionally include wherein the fill material includes at least one element selected from a group consisting of silicon and manganese. This may be due to silicon or manganese migrating from the adhesion layer into the fill material and/or this may be due to the fill material being deposited with silicon and/or manganese already present in addition to cobalt. In example 8 the subject matter of Examples 1-7 can optionally include wherein the fill material includes manganese that directly contacts the manganese included in the adhesion layer. The cobalt fill layer may include manganese and/or silicon. This may not be visually evident with a scanning electron microscopic (SEM) image or transmission electron microscopic (TEM) image but other detection methods may indicate the presence of manganese and/or silicon in the cobalt fill layer. The manganese and/or silicon may be present along the outer edge of the cobalt fill layer because the manganese and/or silicon may have migrated from the adhesion layer to the cobalt fill layer. For example, there is solubility between manganese and cobalt and the manganese from the adhesion layer, in contact with the fill layer, may have mixed with the cobalt fill layer. This migration helps the cobalt fill adhere to the adhesion layer and also allows the adhesion layer to function as a wetting layer for the cobalt fill layer. A wetting layer includes an initial layer of atoms epitaxially grown on a surface upon which self-assembled quantum dots or thin films are created. An example concerns TEM energy dispersive x-rays (EDX). The small TEM probe electrons interact with material being imaged and that material emits x-rays from the different elements present within one pixel of the image. This allows for elemental maps of the image. Higher sensitivity is achieved by taking line scans across structures with more dwell time (e.g., across a via rather than every pixel in image). In an embodiment (example 8a) if there is manganese in the cobalt fill layer, the manganese may migrate to the adhesion layer/fill material interface improving adhesion. EDX may then detect manganese in the cobalt fill layer and around the adhesion layer/fill layer edge/interface. In an embodiment (example 8b) if manganese is at the adhesion layer/fill layer interface it might diffuse into cobalt and other interfaces (e.g., like top layer after CMP has been performed). Such a case would be detected in both the fill layer and around edges/interfaces. In an embodiment, if no diffusion of manganese occurs the manganese may only be in the fill layer of example 8a and at the interface in example 8b. In embodiment, if manganese is present both in120and the fill layer, the manganese may be detected in both areas. Diffusion may change relative concentrations/compositions and ability to adhere or wet so the processes of examples 8a and/or 8b take place but manganese may still be detectable in both scenarios in an embodiment. An embodiment is similar to the embodiment ofFIG.5Dbut includes a dielectric capping layer/etch stop (e.g., similar or directly equal to the materials and structure of element104) that extends from the top surface on the left dielectric portion102, across the tops of524and526, and then across the top of the right dielectric portion102. This caps the polished metal and is later broken through by etch to form a via for a next layer just like shown with a via going through space116and through layer104inFIG.5D. The cap protects the lines (e.g., material530) hermetically and manganese (which in this embodiment is mixed and present in cobalt fill530) would diffuse to the capping layer to improve adhesion of dielectric capping layer/etch stop to the cobalt530(e.g., by silicate formation). The manganese may diffuse from layer120or diffuse from an alloy cobalt fill layer that was deposited already including some amount of manganese. The dielectric cap may be deposited at a high temperature and so that temperature drives the thermal diffusion of manganese from within the layers120and/or530and/or420up to the top of the trench110. The manganese could be detected at the new dielectric cap/layer530interface by TEM EDX methods and the like. In another example the subject matter of Examples 1-8 can optionally include a dielectric layer formed directly on top of the adhesive layer and the fill material, the dielectric layer comprising manganese; wherein the fill material also includes manganese. The manganese may have migrated from the adhesion layer and/or adhesion layer into the dielectric. In another example 9 the subject matter of Examples 1-8 can optionally include a dielectric layer formed directly on top of the fill material, the dielectric layer comprising a first material; wherein the first material is also included in the fill material and the first material is selected from the group comprising Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, and Pd. The material may have migrated into the dielectric from the fill material. In example 9 the subject matter of Examples 1-8 can optionally include wherein (a) the adhesion layer includes a first portion directly contacting the dielectric layer and second portion directly contacting the conductive region, and (b) the first portion includes a higher atomic % manganese than the second portion. Manganese bonds well with the dielectric as well as the cobalt fill layer. On the adhesion layer/dielectric interface manganese forms MnSixOy(e.g., Mn2[SiO4], MnSiO3), and other Mn based silicates. The silicate has the function of a diffusion barrier, preventing diffusion of cobalt into the surrounding dielectric and will also will have adhesive/wetting functions making sure cobalt adheres well to the dielectric. On the adhesion layer/cobalt fill layer interface metal-to-metal bonding occurs (e.g., between the manganese and cobalt) and results in some alloying at the interface. This bonding gives an additional benefit that manganese will dissolve at the via bottom (where in an embodiment the adhesion layer directly contacts the metal fill layer and possibly another interconnect or a conduction substrate portion). This lowers electrical resistance in the via at the adhesion layer interface to the other interconnect or conductive portion of the substrate. For example, the manganese from120that forms at the via bottom initially starts out as thick as similar120portions on ILD. After anneal the manganese may diffuse completely into the cobalt fill or may remain in layer120. The amount that remains may vary. Thus, in some embodiments the adhesion layer near the bottom of the via may have little to no manganese remaining after device processing is complete. In example 10 the subject matter of Examples 1-9 can optionally include wherein the fill material consists essentially of cobalt. In another example the subject matter of Examples 1-9 can optionally include wherein the adhesion layer does not completely separate the conductive region from the fill material and the fill material directly contacts a portion of the conductive region. Thus, by TEM EDX detection or otherwise (regardless of whether the adhesion layer completely or incompletely separates the fill material from the conductive region); there may be areas where no manganese in an adhesion layer separates the fill material from the conductive region. This may be deemed an area where there is no adhesion layer present that can be detected (regardless of whether the layer is there or not) and thus the “adhesion layer does not completely separate the conductive region from the fill material and the fill material directly contacts a portion of the conductive region.” Example 11 includes a method of forming a metal interconnect structure, comprising: forming an opening in a dielectric layer on a substrate, wherein the opening exposes a conductive region of at least one of the substrate and an additional interconnect structure; forming an adhesion layer, comprising manganese, in the opening and on the conductive region and also on the sidewalls; forming a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer; and removing portions of the fill material and the adhesion layer above an upper surface of the dielectric layer. In example 12 the subject matter of Example 11 can optionally include wherein the adhesion layer includes at least one element selected from a group consisting of silicon, nitrogen, carbon, hydrogen, and oxygen. In example, 13 the subject matter of examples 11-12 can optionally include wherein the adhesion layer directly contacts the fill material. In example 14 the subject matter of Examples 11-13 can optionally include wherein the adhesion layer directly contacts the conductive region. In example 15 the subject matter of Examples 13-14 can optionally include wherein (a) the adhesion layer includes a first portion directly contacting the dielectric layer and second portion directly contacting the conductive region, and (b) the first portion includes a higher atomic % manganese than the second portion. In example 16 the subject matter of Examples 13-15 can optionally include forming the adhesion layer with a conformal method and forming the fill layer with a method that is non-conformal. In another example the subject matter of Examples 13-15 can optionally include forming a dielectric layer directly on top of the adhesive layer and the fill material, the dielectric layer comprising manganese; wherein the fill material also includes manganese. Again, the manganese may have migrated into the dielectric from the adhesive layer and/or fill material. Example 17 includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening disposed in the dielectric layer and exposing a conductive region in at least one of the substrate and an additional interconnect structure, the opening having a lower portion and an upper portion; a plug comprising cobalt disposed in the lower portion of the opening; an adhesive layer, comprising manganese, disposed on the sidewalls; and a fill material comprising cobalt disposed on the plug and in the upper portion of the opening. In example 18 the subject matter of Example 17 can optionally include wherein the adhesive layer directly contacts the plug and the dielectric. In example 19 the subject matter of Examples 17-18 can optionally include wherein the adhesive layer is between the plug and the fill material. In example 20 the subject matter of Examples 17-19 can optionally include wherein the plug and fill material have different compositions. In another example 20 the subject matter of Examples 17-19 can optionally include a dielectric layer formed directly on top of the adhesive layer and the fill material, the dielectric layer comprising manganese; wherein the fill material also includes manganese. The manganese may have migrated from the adhesion layer into the dielectric. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. | 54,129 |
11862564 | DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments according to the present invention will be described. The present invention is not limited to the following embodiments, and the embodiments may be modified as necessary. In the drawings, width, length, thickness or the like may be shown with emphasis, and may be different from those in actual cases of carrying out the present invention. The film thicknesses, materials, conditions and the like described below regarding film formation are examples, and may be changed as necessary. Embodiment 1 FIG.1is a cross-sectional view of a line structure in an embodiment according to the present invention. The cross-sectional view shown inFIG.1includes a cross-sectional view of a connection hole provided to connect a line in a first layer (lower layer) and a line in a second layer (upper layer) to each other. The connection hole is located in an area where the first layer line and the second layer line overlap each other. A part of the second layer line that is located in the connection hole will be occasionally referred to as a “via connection part”. As shown inFIG.1, a line material102is located on a substrate (plate)101. There is no specific limitation on the material of the substrate101. The substrate101may be formed of, for example, a semiconductor such as silicon or the like, glass and the like. In the case where the substrate101is formed of silicon, it is preferable that a silicon oxide film is formed as an insulating film on the silicon substrate. There is no specific limitation on the thickness of the substrate101. For example, the thickness of the substrate101may be set to a range of 300 μm or greater and 1000 μm or less. In the case where a support substrate (not shown) is used below the substrate101, a substrate having a thickness in the range of 10 μm or greater and 100 μm or less may be used as the substrate101. Alternatively, the substrate101may have a layer structure, and one or a plurality of layers in the layer structure may have a line already formed therein. The line material102forms the first layer line. The line material102is formed of a conductive material such as Au, Al, Cu or the like. Among these materials, Cu, which is highly conductive and costs low, is preferably used. There is no specific limitation on the thickness of the line material102. The line material102has a thickness of, for example, about 4 μm. It is preferable that a barrier metal103is located between the substrate101and the line material102. This prevents the metal forming the line material102from being diffused to the substrate101. The barrier metal103may be formed of a high-melting-point metal material or a compound thereof. Such a high-melting-point metal material or a compound thereof has a melting point higher than a temperature at which an organic insulating material usable to form an organic resin film is thermally cured. The melting point of the high-melting-point metal material or a compound thereof is 1500° C. or higher. Examples of the high-melting-point metal material or a compound thereof usable for the barrier metal103include Ti, TiN, Ta, TaN, and the like. On a top surface of the substrate101and on a top surface and a side surface of the line material102, an inorganic film is located. The inorganic film forms an insulating film that is located in an area other than in the connection hole provided to connect the first layer line and the second layer line to each other. The inorganic film is formed of a single layer or a plurality of layers. Preferably, the inorganic film includes a stack of a plurality of inorganic films of different materials. InFIG.1, the inorganic film includes a first inorganic film104and a second inorganic film105formed on the first inorganic film104. The first inorganic film104is formed of, for example, silicon nitride and produced by a plasma CVD method. The second inorganic film105is formed of, for example, silicon oxide and produced by a plasma CVD method. The top surface and the side surface of the line material102are covered with the silicon nitride film, and thus atoms, molecules or ions of the line material102can be prevented from being diffused. The barrier metal103is located on a bottom surface of the line material102, and this can also prevents the atoms, molecules or ions of the line material102from being diffused. Each of the first inorganic film104and the second inorganic film105may have a thickness properly selected such that a desired insulating property is provided. The thickness of the first inorganic film104may be 0.1 μm, and the thickness of the second inorganic film105may be 2 μm. On the second inorganic film105, an organic resin film106formed of an organic resin material is located. The organic resin film106forms an insulating film located in an area other than in the connection hole provided to connect the first layer line and the second layer line to each other. The organic resin film106may be formed of, for example, polyimide. An organic material such as polyimide or the like has a dielectric constant lower than that of an inorganic material of a P—SiN film or a P—SiO2film formed by a plasma CVD method. Therefore, such an organic material can decrease the line capacitance between the plurality of lines in a plurality of layers and can decrease the delay of signals transmitted through the lines. The organic resin film106may have a thickness properly selected such that a desired insulating property is provided. It is preferable that the thickness of the organic resin film106is adjusted such that the thickness of the organic resin film106is 20% or greater and 80% or less of a total thickness of the first inorganic film104, the second inorganic film105and the organic resin film106in an area on the second inorganic film105above the line material102. In this manner, both of the size reduction and reducing an adverse effect on the surrounding of the organic resin film106due to thermal expansion of the organic resin film106can be provided to a certain degree. The reason is as follows. The dielectric constant of an inorganic material is generally higher than that of an organic material. Therefore, when the thickness of the organic resin film106is lower than 20% of the total thickness of the films104,105and106, a parasitic capacitance is increased by size reduction. The thermal expansion coefficient of an organic material is higher than that of the line material. Therefore, when the thickness of the organic resin film106is higher than 80% of the total thickness of the films104,105and106, the ratio of occurrence of voids by thermal expansion is increased. For example, the thermal expansion coefficient (linear expansion coefficient) of a P—SiO2film is 0.5 to 2 E-6/K, which is about 1/10 to 1/100 of that of an organic resin film. It is preferable that the material forming the organic film106has a dielectric constant lower than that of each of the material forming the first inorganic film104and the material forming the second inorganic film105. This can suppress the line capacitance between the lines from being increased. The dielectric constant of the material forming the first inorganic film104and that of the material forming the second inorganic film105may be equal to each other, the former may be higher than the latter, or the former may be lower than the latter. Specific values of the dielectric constant of the materials are as follows. In the case where polyimide is used as the material of the organic resin film106, it is preferable that the dielectric constant of the polyimide is 3.5 or lower. A reason for this is that the dielectric constant of P—SiN, which is an example of the material usable to form the first inorganic film104, is usually 7.0, and the dielectric constant of P—SiO2, which is an example of the material usable to form the second inorganic film105, is usually 4.1. In the case where P—SiN is used as the material of the first inorganic film104and P—SiO2is used as the material of the second inorganic film105, the dielectric constant of the material forming the first inorganic film104is higher than that of the material forming the second inorganic105. Therefore, in this case, it is preferable that the thickness of the first inorganic film104is small, and is, for example, smaller than the thickness of the second inorganic film105, from the point of view of suppressing the increase of the line capacitance. In the case where a P—SiN film is used as the first inorganic film104, a P—SiO2film is used as the second inorganic film105, and a polyimide film is used as the organic resin film106, the thicknesses of the films may be, for example, 0.1 μm, 2.0 μm and 8.0 μm (which are thicknesses of each film on the lines), respectively. Therefore, in this case, the thickness of the P—SiO2film is 25% of the thickness of the polyimide film. Polyimide is thermally contracted by about 15% when being thermally treated to be cured. Therefore, polyimide is applied so as to have a thickness of 9.4 μm above the line in consideration of such thermal contraction. The thickness of the line material102may be 0.4 μm. In this case, the total thickness of the polyimide and the line material102is 13.4 μm. The first inorganic film104and the second inorganic film105each have the same thickness in a part above the line and the remaining part. Therefore, the thicknesses of the first inorganic film104and the second inorganic film105may be ignored. The connection hole through which the first layer line and the second layer line are connected to each other is formed as follows. In the organic resin film106, the second inorganic film105and the first inorganic film104, a via connection hole is formed having a bottom part reaching the line material102. On a bottom surface and a side surface of the via connection hole (an inner wall of the via connection hole), a barrier metal film107is formed as a barrier conductive layer. On the barrier metal film107, a line material108is located. The barrier metal film107may be formed of a high-melting-point metal material or a compound thereof. The barrier metal film107may be formed of, for example, Ti, TiN, Ta, TaN, or the like. The line material108forms a line in the upper layer, i.e., forms the second layer line. Namely, the line material108forms a line located in a layer different from the layer in which the line material102is located. The polyimide film may be formed by spin coating or film bonding. However, there is a limit on the thickness of the film. In the case where, for example, spin coating or film bonding is used, about 20 μm is the upper limit of the thickness. By contrast, there is no limit on the thickness of the P—SiO2film. Therefore, when the connection hole does not have a sufficient height, the height of the connection hole can be adjusted by the thickness of the P—SiO2film. In this manner, the line capacitance between the lower layer line and the upper layer line can be controlled, and the impedances can be matched among the lines. In the case where a silicon wafer is used as the substrate101, the wafer may be warped because the organic resin and the Cu lines have a tensile stress. The degree of warp is raised as the number of the layers of lines is increased, and the substrate101may become unsuitable to be treated with an exposure device or a plasma CVD device. After an interposer is removed from the wafer and the wafer is put into individual chips, the substrate101is still warped. As a result, a flaw may occur during a process of stacking the chips on each other or a process of bonding the chips to a motherboard. This problem is solved by providing the P—SiO2with a compressive stress so that the compressive stress is well balanced with the tensile stress of the organic resin or the Cu lines. As described above, the P—SiO2film having a lower thermal expansion coefficient that that of the organic resin is located below the organic resin film106, and thus the tensile stress caused when Cu is provided in the connection hole can be decreased. For example, the distance between the upper layer line and the lower layer line, namely, the height of the connection hole is set to 10 μm, and a P—SiO2film having a thickness of 2 μm is formed in an area corresponding to the distance of 10 μm. An area corresponding to the remaining 8 μm is filled with the organic resin film. The tensile stress in this state is lower by 20% than that in the case where the area corresponding to 10 μm is fully filled with the organic resin film. The above value is simply calculated from the difference in the thermal expansion coefficient. The tensile stress is further decreased when an action caused by a strong adhesive force between a material of the barrier metal film107containing Ti or Ta that is formed on the side surface of the connection hole and P—SiO2(the adhesive force is 800 N/cm or greater; by contrast, the material of the barrier metal layer107and polyimide have an adhesive force of 300 N/m or less), and caused by a high elastic modulus of P—SiO2(40 GPa or greater; by contrast, polyimide has an elastic modulus of 3 to 7 GPa), is added. During the formation of the lines, polyimide, located in the layer having the lines formed therein by a high-temperature treatment, has a property of being elastically deformed by thermal expansion. However, the elastic deformation does not easily occur because P—SiO2located to sandwich the polyimide has a high elastic modulus. This further decreases the tensile stress in the connection hole. A top surface and a side surface of the line material108is covered with an inorganic material, like the line material102. For example, a first inorganic film109is located on the top surface and the side surface of the line material108, and a second inorganic film110is located on the first inorganic film109. On the second inorganic film110, an organic resin film111is located. A part of the line material108that is not in contact with the barrier metal and the top surface and the side surface of the line material102are covered with a plasma nitride film (P—SiN film), and thus atoms, molecules or ions of the line material102and the line material108can be prevented from being diffused in the organic resin films106and111. The barrier metal film107on the bottom surface and the side surface of the connection hole can also prevent atoms, molecules or ions of the line material108from being diffused in the organic resin film106by heat or the like. Silicon oxide is used as a material of the second inorganic film105, and thus the adhesiveness thereof with the barrier metal located on an inner surface of the connection hole is increased and thus occurrence of a disconnecting can be suppressed. In this case, the second inorganic film105is made thicker than the first inorganic film104, so that the adhesiveness between the second inorganic film105and the barrier metal can be increased. In the case where a P—SiN film is used as the first inorganic film104, the thickness of the second inorganic film105is made substantially equal to that of the first inorganic film104, so that the adhesiveness between the second inorganic film105and the barrier metal can be further increased. Side surfaces of the upper layer line and the lower layer line formed of the line material108and the line material102do not need to be covered with a barrier metal. In general, a barrier metal has a resistance value higher than that of a line material such as Cu or the like. When a barrier metal is used excessively, the resistance value of the lines is increased. In this embodiment, the side surfaces of the lines formed of the line material108and the line material102do not need to be covered with a barrier metal. Therefore, the resistance value of the lines can be suppressed from being increased. It is assumed that, for example, a line has a width of 1 μm. If a barrier metal having a thickness of 0.1 μm is located at side surfaces of the line, the barrier metal occupies 20% of the cross-sectional area of the line. Therefore, the resistance of the line is increased by 20% than that in the case where the barrier metal is not located. The degree of such increase of the resistance of the line is raised as the width of the line is decreased. It is considered that such an increase of the resistance of the line can be avoided by decreasing the thickness of the barrier metal. However, when the thickness of the barrier metal is decreased, the barrier metal is oxidized in a thickness direction thereof by oxygen diffusing from the insulating film around the barrier metal. This lowers the level of barrier performance of the barrier metal. By contrast, P—SiN is stable against oxygen. Therefore, even when the side surfaces of the line are covered with P—SiN as in this embodiment, the P—SiN is not deteriorated. As can be seen, according to this embodiment, the increase of the resistance of the line can be suppressed even when the size of the line is reduced and thus the width of the line is decreased. With reference toFIGS.2A to2JandFIG.3, a method for producing a line structure in this embodiment will be described. First, as shown inFIG.2A, the barrier metal103is located on a part of the substrate101where the line material102is to be located. The line material102is located thereon by electrolytic plating so as to have a thickness of, for example, 4 μm. The first inorganic film104having a thickness of 0.1 μm and the second inorganic film105having a thickness of 2.0 μm are formed sequentially. Next, as shown inFIG.2B, an organic resin material such as photosensitive polyimide or the like is applied onto the second inorganic film105by a spin coating method or the like so as to have a thickness of, for example, 15 μm. Thus, the organic resin film106is formed. An opening106ais formed in the organic resin film106by lithography. The opening106ais to be a part of the via connection hole. After the opening106ais formed, the organic resin film106is thermally cured. As shown inFIG.3, when the organic resin film106is thermally cured, a top part106bof the organic resin film106may protrude by the presence of the line material102and the thermal contraction of the organic resin material. When this occurs, the top surface is flattened by use of a fly cutter or the like. Alternatively, in order to avoid the top part of the organic resin film106from protruding like this, the organic resin film106may be formed of an organic resin material having a low thermal contraction coefficient. Next, as shown inFIG.2D, the via connection hole running through the second inorganic film105and the first inorganic film104and having a bottom part reaching the line material102is formed by etching, with the organic resin film106being used as a mask. As a result, the via connection hole runs through an insulating film including the organic resin film106, the second inorganic film105and the first inorganic film104in an up-down direction. The opening106adoes not need to be formed at a position other than a position where the via connection hole is to be formed. Polyimide has an upper limit of photosensing resolution of 0.5 μm. Therefore, it is considered that the via connection hole has a diameter of 0.5 μm at the minimum. Next, as shown inFIG.2E, the barrier metal film107is formed on a top surface of the organic resin film106including an inner surface of the opening106a, and a Cu film108ais formed thereon. At this point, it is preferable to put the barrier metal film107and the second inorganic film105into contact with each other. A reason for this is that when the adhesiveness between the barrier metal film107and the second inorganic film105is high, occurrence of a disconnecting can be suppressed. Next, a photoresist is applied onto the Cu film108a, and exposure and development are performed to form a line pattern108bas shown inFIG.2F. Next, Cu is grown by electrolytic plating on a part of the Cu film108athat is not covered with the line pattern108b. As shown inFIG.2G, the via connection hole and a part inner to the line pattern108bare filled with Cu as the line material108. Thus, the via connection part is formed in the connection hole, and also an upper layer line is formed on the via connection part. Next, the line pattern108bis removed, and a part of the Cu film108athat is exposed by the removal of the line pattern108band a part of the barrier metal film107below the exposed part of the Cu film108aare removed with an acidic aqueous solution or the like. As a result, a structure shown inFIG.2His obtained. Then, as shown inFIG.2I, the first inorganic film109is formed so as to cover the organic resin film106and the line material108. Then, as shown inFIG.2J, the second inorganic film110is formed. In the case where another line is to be formed on the upper layer line formed of the line material108, the process inFIG.2Aand thereafter is performed again, with the line material108being regarded as the line material102, the first inorganic film109being regarded as the first inorganic film104, and the second inorganic film110being regarded as the second inorganic film105. In this embodiment, the side surface of the line material102, for example, does not need to be covered with a barrier metal. Therefore, the increase of the resistance value of the lines can be suppressed. Since the side surface of the line material102, for example, is covered with the first inorganic film104, atoms or the like of the line material102can be suppressed from being diffused. In the case where the adhesiveness between the barrier metal formed on the inner surface of the connection hole and the inorganic film (e.g., P—SiN film) is high, a disconnecting in the connection hole, which would be caused by thermal expansion of the organic resin film106, can be suppressed from occurring. Since a photosensitive material is used as a material of the organic resin film106, the opening106acan be formed in the organic resin film106and the organic resin film106can be used as a mask for forming an opening in the first inorganic film104and the second inorganic film105. This can simplify the method. As described above, the minimum value of the diameter of the via connection hole is considered to be 0.5 μm, and the width of each line has a small value of 0.5 μm at the minimum. In this embodiment, the side surfaces of the lines do not need to be covered with a barrier metal. Therefore, even though the width of each line is 0.5 μm, the increase of the resistance of the lines can be suppressed. Embodiment 2 FIG.4shows an example of arrangement of LSI chips made by use of line structures according to embodiment 2 of the present invention. This is an example of arrangement called a “2.5-dimensional mounting”. InFIG.4, an interposer401is a multi-layer line structure in this embodiment. On the interposer401, a logic LSI402such as a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit) or the like and memory LSIs403,404,405and406such as a DRAM, a flash memory or the like are located, and are connected together via lines in the interposer401. Because of this arrangement, signal lines, power supply lines and ground lines can be connected together with a short distance between the memory LSIs403,404,405and406and the logic LSIs402. Therefore, a high-speed process can be performed as a whole. With reference toFIGS.5A to5L, a method for producing a line structure as the interposer401in this embodiment will be described. As shown inFIG.5A, on a substrate501such as a silicon substrate or the like, an SiO2film (P—SiO2film)502having a thickness of 3 μm is formed by plasma CVD. Next, a Ti film503having a thickness of 0.1 μm and a Cu film504ahaving a thickness of 0.3 μm are formed by sputtering. The Ti film503acts as a barrier metal film for preventing Cu from being diffused to the substrate501. The Cu film504aacts as a seed from which Cu is grown by electrolytic plating. In this example, TiN or Ta, which is a high-melting-point metal material, for example, may be used as a material of the barrier metal instead of Ti. Next, as shown inFIG.5B, a photoresist is applied onto the Cu film504a, and exposure and development are performed to form a line pattern505. Then, a Cu film504is grown on a part of the Cu film504athat is exposed from the line pattern505by electrolytic plating so that the Cu film504has a thickness of 4.4 μm. In this embodiment, Cu in the Cu film504,504ais used as the material of a first layer line, and the first layer line is designed to have a thickness of 4.0 μm. Next, after the Cu is grown, the photoresist forming the line pattern505is removed with an organic solvent. As a result, a structure shown inFIG.5Cis obtained. The photoresist may be removed by ashing with oxygen plasma instead of with an organic solvent. Next, as shown inFIG.5D, a part of the Cu film504aand a part of the Ti film503that were covered with the line pattern505are removed with an acidic aqueous solution to form Cu lines504bin the first layer. As a result of the part of the Cu film504athat was covered with the line pattern505being removed, the thickness of the Cu film504is decreased from 4.4 μm to about 4.0 μm. Thus, the designed value can be achieved. The Cu film504aand the Ti film503may be removed by ion milling instead of with an acidic aqueous solution. In the case where an acidic aqueous solution is used, as shown inFIG.6, a large undercut601is formed. Especially when the width of each of the Cu lines is 5 μm or less, the Cu lines504band the underlying layer may not have a sufficiently high adhesiveness therebetween, and as a result, the Cu lines may be peeled off by a stress thereof. By contrast, in the case where ion milling is used, such an undercut is not likely to be formed. Therefore, microscopic lines can be formed. Next, as shownFIG.5E, a P—SiN film506having a thickness of 0.1 μm is formed by plasma CVD on the Cu lines504bin the first layer, and then a P—SiO2film507having a thickness of 2 μm is formed thereon. For forming the P—SiN film506, SiH4is usable as a source of Si and NH3is usable as a source of nitrogen. For forming the P—SiO2film507, SiH4is usable as a source of Si and N2O is usable as a source of oxygen. As a source of Si, tetraethoxysilane (TEOS) is also usable. As a source of oxygen, O2is also usable. It can be considered that the structure shown inFIG.2Ais included in the structure shown inFIG.5E. In order to suppress the warp of the wafer used as the substrate101, it is preferable to adjust P—SiO2to have a compressive stress of −100 to −300 MPa as a film stress. It is especially preferable to adjust the film stress to −200 MPa. If copper oxide is present on surfaces of the Cu lines504bin the first layer, the adhesive force between P—SiN and Cu is decreased. Therefore, it is preferable to wash the lines504bwith diluted sulfuric acid or the like before the P—SiN film506is formed. Alternatively, before the P—SiN film506is formed, the surfaces of the Cu lines504bmay be subjected to NH3plasma in the same chamber as that to be used for the formation of the P—SiN film506, so that the copper oxide is removed. The P—SiN film506acts as a barrier film for preventing Cu atoms, Cu molecules or Cu ions of the Cu lines504bfrom being thermally diffused to the P—SiO2film507from side surfaces or the top surfaces of the Cu lines504b, and for also preventing diffusion from occurring due to an electric field between lines adjacent to each other. SiC (which may contain several to 10% of oxygen) may be used as a barrier insulating film instead of P—SiN. The SiC film can be formed by plasma CVD, and has an effect of preventing the diffusion of the Cu atoms, Cu molecules or Cu ions of the Cu lines504b. An SiOC film, an SiOF film or the like may be formed instead of the P—SiO2film507. The SiOC film and the SiOF film can be formed by plasma CVD. SiOC and SiOF each have a dielectric constant lower than that of P—SiO2, and thus can decrease the line capacitance between lines adjacent to each other. Next, polyimide is applied onto the P—SiO2film507by spin coating so as to have a thickness of 9.4 μm above the lines. Bisbenzocyclobutene may be applied instead of polyimide. Alternatively, a non-photosensitive resin may be used. In the case where a non-photosensitive resin is used, however, a photosensitive resin needs to be applied to perform patterning by lithography. Therefore, use of a non-photosensitive resin may increase the number of steps of production. In the following example, polyimide, which is photosensitive, is applied. In the case where a photosensitive polyimide508is applied, exposure and then development are performed by use of a photomask to form, as shown inFIG.5F, opening patterns508aat necessary positions above the Cu lines504b. The “necessary positions” are positions where the Cu lines504bneed to be connected to lines which will be formed in a layer above the Cu lines504b. It can be considered that the structure shown inFIG.2Cis included in the structure shown inFIG.5F. In order to cure the applied polyimide after the opening patterns508aare formed, the polyimide is thermally cured at a temperature of 250° C. for 1 hour in an N2atmosphere. The temperature is not limited to 250° C. In general, it is preferable to set the temperature at a glass transition temperature of polyimide or lower. A reason for this is that if the polyimide is cured at a temperature higher than the glass transition temperature, each of the openings508ais deformed, resulting in a problem that, for example, the diameter of the opening is larger than the designed size. Assuming that the glass transition temperature of polyimide is, for example, 280° C., the thermal-curing temperature is set to 250° C. as described above. It is preferable that the thermal curing treatment and the process in steps after this are performed such that the temperature does not exceed the glass transition temperature of polyimide. When the polyimide is thermally cured, a stepped portion508bas shown inFIG.7may be formed at a surface of a part of the photosensitive polyimide508other than in the openings508adue to convexed and concaved portions caused by the Cu line504. Unless being treated in some way, the size of the stepped portion is increased as more lines are stacked. This causes a focus shift at the time of pattern exposure. When this occurs, it becomes difficult to form a line pattern in accordance with the designed size. As a result, a desired contact resistance may not be provided, or shortcircuit may occur because of adjacent lines being connected. In order to decrease the size of such a stepped portion, it is preferable to use polyimide having a low thermal expansion coefficient (preferably, 15% or less). In order to remove the convexed and concaved portions at the surface of the polyimide at high precision, a fly cutter may be used. Alternatively, the convexed and concaved portions can be removed also by chemical mechanical polishing (CMP). Next, a part of the P—SiO2film507that is located in bottom parts of the openings508ais etched away by plasma etching, with the photosensitive polyimide508being used as a mask. As an etching gas, a mixed gas of CF4(flow rate: 20 sccm) and H2(flow rate: 5 sccm) may be used. The flow rate ratio of the materials of the mixed gas may be changed so that the etching rate for each of the cured photosensitive polyimide508and the P—SiO2film507can be changed. It is preferable that the etching rate for the P—SiO2film507is high and the etching rate for the photosensitive polyimide508is low. In general, the ratio of the etching rate for P—SiO2with respect to the etching rate for polyimide is about 5, and the ratio of the etching rate for P—SiO2with respect to the etching rate for P—SiN is about 8. The etching gas is not limited to the above-described gas, and may be CHF3or CH2F2instead of CF4. After the P—SiO2layer507is etched, the etching gas is changed to a mixed gas of CF4and O2and the P—SiN layer506is etched. At this point, for example, the flow rate of CF4may be 20 sccm and the flow rate of 02 may be 2 sccm. The ratio of the etching rate for P—SiN with respect to the etching rate for polyimide may be about 2. As a result of the etching performed on the P—SiN layer506, first connection holes usable for electrically connecting the Cu lines504sin the first layer to Cu lines in the second layer which will be formed in a later step is formed. In a state immediately after the first connection holes are formed, a carbon compound containing Si of F adheres to side walls or bottom parts of the first connection holes. In order to remove the carbon compound, washing is performed with an organic solvent. A surface of Cu that is exposed at the bottom parts of the first connection holes is in an oxidized state as a result of the plasma etching. In order to remove the oxide formed as a result of the oxidization, washing is performed with dilute sulfuric acid. As a result of the plasma etching performed on the P—SiO2layer507and the P—SiN layer506, the surface of the photosensitive polyimide508is plasma-damaged, and thus the photosensitive polyimide508may not have a sufficient heat resistance, which polyimide should originally have. In this case, a heat treatment may be performed, for example, at a temperature of 250° C. for 30 minutes, so that the plasma-damaged part of the surface can be removed. The temperature of 250° C. is an example of temperature which is lower than, or equal to, the glass transition temperature of polyimide. As a result of the above-described process, a structure shown inFIG.5Gis obtained. It can be considered that the structure shown inFIG.2Dis included in the structure shown inFIG.5G. Next, a Ti film having a thickness of 0.1 μm and a Cu film509having a thickness of 0.3 μm are formed by sputtering on the structure shown inFIG.5G. The Ti film acts as a barrier metal for preventing the diffusion of Cu atoms, Cu molecules or Cu ions of the Cu film509as described above. The Cu film509acts as a seed from which Cu is grown by electrolytic plating in a later step. As shown inFIG.5H, a photoresist is applied onto the Cu film509, and exposure and development are performed to form a line pattern510. Then, a Cu film511is grown by electrolytic plating on a part of the Cu film509exposed from the line pattern510. Assuming that the final thickness of the Cu film511from top edges of the first connection holes (namely, the thickness of the Cu lines in the second layer) is 4.0 μm, it is preferable to form the Cu film511to have a thickness of 4.4 μm from the top edges of the first connection holes in this step. Next, as shown inFIG.5I, after the Cu film511is grown, the photoresist forming the line pattern510is removed with, for example, an organic solvent. As described above, the photoresist may be removed by ashing with oxygen plasma. It can be considered that the structure shown in FIG.2H2H is included in the structure shown inFIG.5I. Next, an exposed part of the Cu film509and a part of the Ti film below the exposed part of the Cu film509are removed with, for example, an acidic aqueous solution to form Cu lines511in the second layer. As a result of this step, the thickness of the Cu film511is slightly decreased, and thus the designed size can be achieved. Ion milling may be used instead of the acidic aqueous solution. As a result of the above-described process, the Cu lines504bin the first layer and the Cu lines511in the second layer are connected to each other through via connection parts formed in the first connection holes. Now, a process of forming Cu lines in a third layer and connecting the Cu lines in the third layer to the Cu lines511in the second layer will be described. As shown inFIG.5J, a P—SiN film512having a thickness of 0.1 μm is formed by plasma CVD on the Cu lines511, and a P—SiO2film513having a thickness of 2 μm is formed thereon. The reaction system is the same as that used for forming the P—SiN film506. It is preferable to set the temperature for the film formation to, for example, 250° C. in consideration of the glass transition temperature of polyimide. If the film formation is performed at a temperature exceeding the glass transition temperature of polyimide, the thermal expansion of polyimide is increased. As a result, the photosensitive polyimide508may be wrinkled or the P—SiN film512or the P—SiO2film513may be cracked due to a difference in the thermal expansion coefficient between polyimide and P—SiN or P—SiO2. It can be considered that the structure shown inFIG.2Jis included in the structure shown inFIG.5J. In order to remove copper oxide present on surfaces of the Cu lines511in the second layer, the Cu lines511in the second layer are washed with diluted sulfuric acid before the P—SiN film512is formed. Alternatively, before the P—SiN film512is formed, the surfaces of the Cu lines511may be subjected to NH3plasma in the same chamber as that to be used for the formation of the P—SiN film512, so that the copper oxide is removed. If the surfaces of the Cu lines511are exposed to NH3plasma excessively, the imide bond of the photosensitive polyimide508is broken. Therefore, it is preferable that the surfaces of the Cu lines511are exposed to NH3plasma for 30 seconds or shorter, for example, for 20 seconds. The formation of the P—SiN film512is different from the formation of the P—SiN film506on the Cu lines504bin the first layer in that the underlying layer is the photosensitive polyimide508instead of P—SiO2. The photosensitive polyimide508, when being exposed to an acidic aqueous solution for removing the Cu film509and the Ti film below the Cu film509, contains a large amount of water. Even after the Cu film509and the Ti film below the Cu film509are removed, the photosensitive polyimide508has water in the air absorbed thereto. In general, when a P—SiN film is formed on polyimide containing water, the water contained in the polyimide is vaporized to push up the P—SiN film. As a result, the P—SiN film may be peeled off. In order to avoid this, it is preferable to, before the treatment with NH3plasma, heat the substrate501in the same chamber as that to be used for the treatment with NH3plasma, so that the water contained in the photosensitive polyimide508is removed. For example, the treatment with NH3plasma is performed after degassing is performed for 3 minutes with the substrate temperature in the plasma CVD device being set at 250° C. Next, photosensitive polyimide is applied onto the P—SiO2film513by spin coating so as to have a thickness of 9.4 μm above the Cu lines. A photosensitive resin such as bisbenzocyclobutene or the like may be applied instead of polyimide as described above. Alternatively, a non-photosensitive resin may be used. In this case, after the non-photosensitive resin is applied, a photosensitive resin is applied to perform patterning by lithography. Next, the applied photosensitive polyimide is exposed by use of a photomask and development is performed to form opening patterns514aat necessary positions above the Cu lines511in the second layer. After the formation of the opening patterns514a, the polyimide is thermally cured at a temperature of 250° C. for 1 hour in an N2atmosphere. Then, the P—SiO2film513and the P—SiN film512are etched with the opening patterns514abeing used as a mask. As a result, a structure shown inFIG.5Kincluding second connection holes514a/513a/512ais obtained. It can be considered that the structure shown inFIG.2Dis included in the structure shown inFIG.5K. Next, a barrier metal is formed on inner surfaces of the second connection holes514a/513a/512aand top edges of the opening patterns514ain substantially the same process as described above, and then Cu lines in the third layer are formed. Then, substantially the same process is repeated. As a result, as shown in, for example,FIG.5L, a line structure including Cu lines in the first through fifth layers is obtained. It can be considered that the structure shown inFIG.2Dis included in the structure shown inFIG.5L. In a cross-sectional view shown inFIG.5L, even-numbered layers, more specifically, the second and fourth layers each include Cu lines that are not connected to the Cu lines in the layer above or the layer below. In this manner, the layers including such non-connected Cu lines are provided so as not to be adjacent to each other, namely, so as to have another layer therebetween. Because of this structure, the line capacitance between the Cu lines can be controlled. The present invention is not limited to having the cross-sectional view shown inFIG.5L, and such non-connected Cu lines may be located in any layer. The thermal-curing temperature of polyimide is set to be lower in an upper layer than in a lower layer. Because of this, the thermal load on the polyimide in the lower layer is decreased. As a result, peel-off of the films or a disconnecting, which would be caused by the thermal stress or the thermal expansion of the polyimide, the P—SiN films, the P—SiO2films and the Cu lines, becomes unlikely to occur. In the case where there are a large number of layers, it is preferable to set the thermal-curing temperature to be lower in an upper layer than in a lower layer, and also set the temperature, for film formation performed by use of plasma, to be lower in an upper layer than in a lower layer. Now, inFIG.5L, it may be assumed as follows: the third layer is the first layer, the second layer is the second layer, the Cu lines in the first layer is first Cu lines, and the Cu lines in the second layer is second Cu lines. In this case, the first inorganic film (e.g., P—SiN film) covers a surface of each Cu line in the second layer that faces the first layer, and also covers a side surface of each Cu line in the second layer. In the line structure shown inFIG.5L, each layer includes a P—SiN film and a P—SiO2film that are formed of an inorganic material. The present invention is not limited to having such a structure, and the line structure may include a layer that does not include a P—SiN film or a P—SiO2film. For example,FIG.5M, likeFIG.5I, shows a state where the Cu lines504bin the first layer and the Cu lines511in the second layer are connected to each other through the via connection parts formed in the first connection holes. After the structure shown inFIG.5Eis obtained, a structure shown inFIG.5Nmay be obtained as follows. Neither P—SiN film nor a P—SiO2film, both of which are formed in order to obtain the structure shown inFIG.5J, is formed. Photosensitive polyimide is applied so as to have a thickness of 9.4 μm above the Cu lines. The applied polyimide is exposed by use of a photomask and development is performed to form opening patterns514aat necessary positions above the Cu lines511in the second layer. Then, the polyimide is cured. Thus, the structure shown inFIG.5Nis obtained.FIG.5NandFIG.5Kwill be compared. InFIG.5K, the Cu lines511in the second layer are covered with the first inorganic film512and the second inorganic layer513except for in the openings514a. By contrast, inFIG.5N, neither the first inorganic film512nor the second inorganic layer513is present, and the Cu lines511in the second layer are not covered with a first inorganic film or a second inorganic layer. The Cu lines in the third layer, the Cu lines in the fourth layer and the Cu lines in the fifth layer are covered with a first inorganic film and a second inorganic film except for in the openings formed in the organic resin films. As a result, a line structure shown inFIG.5Ois obtained.FIG.5OandFIG.5Lwill be compared. InFIG.5L, the Cu lines in the second layer are covered with the first inorganic film and the second inorganic film except for in the openings. By contrast, inFIG.5O, the Cu lines in the second layer are not covered with the a first inorganic film and a second inorganic film. Therefore, the Cu lines in the second layer are considered to be located between the organic resin film in the first layer and the organic resin film in the second layer. The via connection parts used to connect the Cu lines in the first layer and the Cu lines in the third layer to each other are each divided into an upper part belonging to the second layer and a lower part belong to the first layer. The division is made by the Cu line located between the Cu line in the first layer and the Cu line in the third layer among the Cu lines in the second layer. In other words, the upper part is located above the Cu line located between the Cu line in the first layer and the Cu line in the third layer, and the lower part is located below the Cu line located between the Cu line in the first layer and the Cu line in the third layer. Between the upper part, and the Cu line located between the Cu line in the first layer and the Cu line in the third layer, namely, at a bottom part of the upper part, a barrier conductive material is located. The Cu lines that are not covered with a first inorganic film and a second inorganic film are not limited to being located in the second layer, and may be located in any layer. Alternatively, Cu lines that are not covered with a first inorganic film and a second inorganic film may be located in continuous layers. Since the Cu lines that are not covered with a first inorganic film and a second inorganic film are provided as described above, the steps of forming the first inorganic film and the second inorganic film can be omitted, which decreases the number of production steps. In addition, the thickness of the organic resin film can be controlled, the warp of the substrate101can be controlled, and the impedances can be matched among the lines. As shown especially inFIG.5LandFIG.5O, between the second and third Cu lines from the left among the four Cu lines in the second layer, and the second and third Cu lines from the left among the four Cu lines in the fourth layer, only insulating layers are present with no other Cu line being located. In this manner, a layer in which no Cu line is arranged is located between Cu lines in one layer and Cu lines in a layer over the one layer; namely, no Cu line is located in a layer between one layer and a layer over the one layer. Because of this arrangement, the impedances can be matched between the Cu lines in the one layer and the Cu lines in the layer over the one layer. The number of layer(s) between the one layer and the layer over the one layer may be one, or two or more. Between the Cu lines in the one layer and the Cu lines in the layer over the one layer, only an organic insulating layer may be located, or any number of inorganic insulating layer(s) may be located. Because of such an arrangement, the impedances can be matched between the Cu lines in the one layer and the Cu lines in the layer over the one layer, and thus transfer characteristics can be improved. Embodiment 3 FIG.8Ashows an arrangement of chips made by use of line structures according to embodiment 3 of the present invention. This is an example of an arrangement of so-called three-dimensional mounting. As shown inFIG.8A, a CPU803is located on a motherboard801with an interposer802being provided therebetween. On the CPU803, an ASIC805is located with an interposer804being provided therebetween. On the ASIC805, a DRAM is located with an interposer806being provided therebetween. Another DRAM is located thereon with another interposer807being provided therebetween, and a DRAM809is located thereon with still another interposer808being provided therebetween. The interposers802,804,806,807and808each have a line structure in this embodiment at both of a top surface and a bottom surface thereof so as to be bump-connected with each of the LSIs. Because of such three-dimensional mounting, signal lines, power supply lines and ground lines of the LSIs are connected via the Cu lines in the interposers. Three-dimensional mounting, in which the lines to be connected are shorter than in the 2.5-dimensional mounting, is suitable for higher speed information processing. FIG.8Bshows a cross-section of an Si interposer as an example of interposer. The Si interposer includes Cu embedded, by electrolytic plating, in a plurality of vias running through an Si substrate having a thickness of 300 μm. For example, the vias may each have a diameter of 10 μm and may be located at a pitch of 40 μm. In this embodiment, lines each having a width of 1 μm or less and stacked vias can be formed. Therefore, line layers can be stacked at a high density even on an interposer including vias at such a small pitch. As shown inFIG.8B, in order to insulate the Cu in the Si interposer and the Si substrate, a P—SiO4film814and a P—SiN film815are formed in this order on an inner surface of each via, and Cu813is embedded in an inner surface of the P—SiN film815. For example, the P—SiO4film814has a thickness of 0.5 μm, and the P—SiN film815has a thickness of 0.1 μm. A P—SiO4film814and a P—SiN film815are also formed on each of a top surface and a bottom surface of the Si interposer. As shown inFIG.9A, a Ti film821having a thickness of 0.1 μm and a Cu film822ahaving a thickness of 0.3 μm are formed by sputtering on each of a top surface and a bottom surface of an Si interposer811. The Ti film821acts as a barrier metal for preventing the diffusion of Cu in the Si substrate. The Cu film822aacts as a seed from which a Cu layer is grown by electrolytic plating in a later step. Next, as shown inFIG.9B, a photoresist is applied onto the Cu film822a, and exposure and development are performed to form a line pattern823. Then, a Cu layer822having a thickness of 2.2 μm is grown by electrolytic plating on an exposed part of the Cu film822a. Cu lines in a first layer to be formed of the Cu layer822is designed to have a thickness of 2.0 μm. After the Cu layer822is grown, the photoresist forming the line pattern823is removed with, for example, an organic solvent. As a result, a structure shown inFIG.9Cis obtained. As described above, the photoresist may be removed by ashing with oxygen plasma instead of with an organic solvent. Next, as shown inFIG.9D, an exposed part of the Cu film822aand a part of the Ti film821below the exposed part of the Cu film822aare removed with an acidic aqueous solution, and thus the Cu lines in the first layer are formed of the Cu layer822. As a result of the exposed part of the Cu film822abeing removed, the thickness of the Cu layer822can be decreased to 2.0 μm, which is the designed size. The exposed part of the Cu film822aand the part of the Ti film821below the exposed part of the Cu film822amay be removed by ion milling. Next, as shown inFIG.9E, a P—SiN film824having a thickness of 0.1 μm is formed by plasma CVD on the Cu lines in the first layer, and then a P—SiO2film825having a thickness of 1 μm is formed thereon. It can be considered that the structure shown inFIG.2Ais included in the structure shown inFIG.9E. Since the P—SiN film824and the P—SiO2film825are formed on side surfaces of the Cu lines in the first layer, the interval between the Cu lines adjacent to each other as seen in a plan view can be decreased. In the case where the density or the pattern of the Cu lines in the first layer is different between at the top surface and at the bottom surface of the interposer811, a residual stress of the lines is different between the surfaces, and thus the interposer811may be warped toward one side. In this case, the thickness or the film stress of the P—SiO2film on one of the surfaces is changed, so that the warp can be controlled. For example, the film stress of the P—SiO2film825may be adjusted to −200 MPa. Next, copper oxide present on the surfaces of the Cu lines in the first layer is removed as in embodiment 2. Next, photosensitive polyimide is applied by spin coating onto the P—SiO2film825on the top surface of the interposer811so as to have a thickness of 4.7 μm above the Cu lines. As in embodiment 2, a resin different from polyimide may be used. The applied polyimide is exposed by use of a photomask and development is performed to form, above the interposer811, a pattern826including openings826aat necessary positions above the Cu lines in the first layer. Similarly, a pattern826including openings826ais formed also below the interposer811. Then, the polyimide is cured as in the above embodiments. As a result, a structure shown inFIG.9Fis obtained. It can be considered that the structure shown inFIG.2Cis included in the structure shown inFIG.9F. Next, the P—SiO2film825and the P—SiN film824are etched by plasma etching with the pattern826above the interposer811being used as a mask, to form first connection holes826a/825a/824a. Similarly, first connection holes826a/825a/824aare formed also below the interposer811. As a result, a structure shown inFIG.9Gis obtained. It can be considered that the structure shown inFIG.2Dis included in the structure shown inFIG.9G. Then, as in embodiment 2, a carbon compound containing Si of F adhering to side walls or bottom parts of the first connection holes is removed, the oxidized surfaces of the Cu lines are removed, and the polyimide damaged by plasma etching is heat-treated to be recovered. Next, a Ti film having a thickness of 0.1 μm and a Cu film827having a thickness of 0.3 μm are formed above the interposer811by sputtering. Similarly, a Ti film and a Cu film827are formed also below the interposer811. Then, a photoresist is applied onto the Cu film827above the interposer811, and exposure and development are performed to form a line pattern828. Similarly, a line pattern828is formed also below the interposer811. A Cu layer829having a thickness of 2.2 μm is grown by electrolytic plating on an exposed part of each of the Cu films827. As a result, a structure shown inFIG.9His obtained. The Cu lines are designed to have a thickness of, for example, 2.0 μm. Next, in substantially the same manner as in the above embodiments, the photoresist forming the line patterns828is removed, and the exposed part of each Cu film827and a part of each Ti film corresponding to the exposed part of each Cu film827are removed. As a result, a structure shown inFIG.9Iis obtained. Since the exposed part of each Cu film827is removed, the thickness of each Cu layer829can be made the designed value. Because of this step, as shown inFIG.9I, lines in each second layer are formed of the Cu layer829and are connected to the lines in the first layer. It can be considered that the structure shown inFIG.2His included in the structure shown inFIG.9I. Next, as shown inFIG.9J, a P—SiN film830having a thickness of 0.1 μm is formed by plasma CVD above and below the interposer811, and a P—SiO2film831having a thickness of 1 μm is formed thereon above and below the interposer811. The reaction system is substantially the same as that used for forming the P—SiN film824and the P—SiO2film825. The temperature for the film formation is set so as not to exceed the glass transition temperature of polyimide. It can be considered that the structure shown inFIG.2Ais included in the structure shown inFIG.9J. As in embodiment 2, before the above-mentioned films are formed, the Cu lines in the second layers are washed in order to remove copper oxide from the surfaces of the Cu lines, and water is removed from the pattern of polyimide826. Next, photosensitive polyimide or the like is applied above the interposer811so as to have a thickness of 4.7 μm, and exposure and development are performed to form a pattern832including openings832aat necessary positions above the Cu lines in the second layer. Similarly, a pattern832is formed also below the interposer811. Then, as in embodiment 2, the polyimide is cured. The P—SiO2films831and the P—SiN films830are etched with the polyimide being used as a mask. As a result, a structure shown inFIG.9Kincluding second connection holes832ais obtained. It can be considered that the structure shown inFIG.2Dis included in the structure shown inFIG.9K. After Cu lines829in the second layers are exposed to bottom parts of the second connection holes832a, substantially the same process is repeated to form Cu lines in third layers. In substantially the same manner, as shown inFIG.9L, Cu lines in fourth layers and Cu lines in fifth layers can be formed. It can be considered that the structure shown inFIG.2Dis included in the fifth layer in the structure shown inFIG.9L. As in embodiment 2, the thermal-curing temperature of polyimide is set to be lower in an upper layer than in a lower layer. Because of this, the thermal load on the polyimide in the lower layer is decreased. As a result, peel-off of the films or a disconnecting, which would be caused by the thermal stress or the thermal expansion of the polyimide, the P—SiN films, the P—SiO2films and the Cu lines, becomes unlikely to occur. Also as in embodiment 2, in the case where there are a large number of layers, it is preferable to set the thermal-curing temperature to be lower in an upper layer than in a lower layer, and also set the temperature, for film formation performed by use of plasma, to be lower in an upper layer than in a lower layer. In this embodiment, a same number of Cu lines are formed on both sides of the interposer811. As necessary, the number of Cu lines above the interposer811may be different from the number of Cu lines below the interposer811. In this embodiment, as described above in embodiment 2, there may be a layer in which Cu lines are not covered with a first inorganic film or a second inorganic film. Layers including such non-connected Cu lines may be provided so as not to be adjacent to each other, namely, so as to have another layer therebetween. EXAMPLES FIG.11is a graph showing the percentage defective of line structures as a result of a heat cycle test. The line structures were formed on Si interposers by the method described above in embodiment 3. For this heat cycle test, a stack via chain (number of chains: 100) including four layers connected to each other through a via connection part was formed on each of a top surface and a bottom surface of the Si interposer. A temperature cycle of −25° C. to 125° C. was repeated 3000 times. When the chain resistance was raised by 20% or more, the line structure was determined to be defective. Two types of measurement samples were prepared; one type had a diameter of the connection hole of 0.5 μm, and the other type had a diameter of the connection hole of 20 μm. The diameter of the connection hole of 0.5 μm is a resolution limit in the exposure and development of polyimide. The diameter of the connection hole of 20 μm is the maximum possible diameter with which size reduction is advantageous. In the connection hole, the ratio of the thickness of P—SiO2was changed. The ratio of the thickness of P—SiO2was calculated with the thickness of P—SiN (fixed at 0.1 μm) being included. The ratio of the thickness of P—SiO2is calculated by [P—SiO2thickness/(P—SiO2thickness+polyimide thickness)]. This will be described more specifically with reference toFIG.10. A distance from a top end of a line1003in a first layer to a bottom end of a barrier metal below a line1008in a second layer, namely, the height of the connection hole, is set to X. The thickness of P—SiO2in an area between the top end of the line1003in the first layer and the bottom end of the barrier metal below the line1008in the second layer is set to Y. The ratio of the thickness of P—SiO2is a value calculated by Y/X. Namely, Y/X is the ratio of P—SiO2with respect to the height of the connection hole (length of the connection hole running through the insulating layers). As shown inFIG.11, as Y/X increased, the percentage defective of line structures decreased. When the diameter of the connection hole was 20 μm, the percentage defective of line structures was 0% at Y/X of 20%. When the diameter of the connection hole was 0.5 μm, the percentage defective of line structures was 0% at Y/X of 30%. From these results, it is considered that the ratio of the thickness of the P—SiO2film in the connection hole is preferably 20% or greater, and more preferably 30% or more. Strictly describing, Y/X is calculated with the thickness of the P—SiN film being included. Therefore, it may be considered that the ratio of the thickness of the inorganic film containing Si is preferably 20% or greater. However, when the ratio of the thickness of the P—SiO2film is excessively high, the line capacitance between upper and lower lines is increased and it becomes difficult to match the impedances. Therefore, it is preferable that the ratio of the thickness of the P—SiO2film is 80% at the maximum. FIG.12A andFIG.12Bshows the percentage defective of line structures as a result of the above-described heat cycle test. The line structures were formed on Si interposers by the method described above in embodiment 3. Two types of measurement samples were prepared; one type had a diameter of the connection hole of 0.5 μm, and the other type had a diameter of the connection hole of 20 μm. The height of the connection hole was changed in the range of about 5 μm to 20 μm. When the diameter of the connection hole was 0.5 μm, the ratio of the thickness of the P—SiO2film (including the thickness of P—SiN, i.e., 0.1 μm) with respect to the height of the connection hole, namely, Y/X, was set to 20% and 30%. When the diameter of the connection hole was 20 μm, the ratio of the thickness of the P—SiO2film (including the thickness of P—SiN, i.e., 0.1 μm) with respect to the height of the connection hole was set to 10% and 20%. When the diameter of the connection hole was 0.5 μm and the ratio of the thickness was 20%, the percentage defective of line structures was about 18% regardless of the height of the connection hole. When the ratio of the thickness was increased to 30%, the percentage defective of line structures was decreased to 0% regardless of the height of the connection hole. When the diameter of the connection hole was 20 μm and the ratio of the thickness was 10%, the percentage defective of line structures was about 15% regardless of the height of the connection hole. When the ratio of the thickness was increased to 20%, the percentage defective of line structures was decreased to 0% regardless of the height of the connection hole. From the above results, it has been found that when the diameter of the connection hole is in the range of 0.5 μm or greater and 20 μm or less, the height of the connection hole does not influence the ratio of defective line structures. Even if the height of the connection hole is changed, as long as the ratio of the thickness of the P—SiO2film is the same, thermal expansion of polyimide is suppressed by the high elastic modulus of P—SiO2. It is considered that the strong adhesive force between P—SiO2and the barrier metal also alleviates the tensile stress of Cu in the connection hole, and thus suppresses formation of voids in the bottom part of the via connection hole to decrease the ratio of defective line structures. | 63,267 |
11862565 | The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. In general, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something, but also includes the meaning of “on” something with an intermediate feature or a layer therebetween. Moreover, “above” or “over” not only means “above” or “over” something, but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process step in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly. As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate includes a “top” surface and a “bottom” surface. The top surface of the substrate is typically where a semiconductor device is formed, and therefore the semiconductor device is formed at a top side of the substrate unless stated otherwise. The bottom surface is opposite to the top surface and therefore a bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer. As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer has a top side and a bottom side where the bottom side of the layer is relatively close to the substrate and the top side is relatively away from the substrate. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and/or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers. In the present disclosure, for ease of description, “tier” is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as “a tier,” a word line and the underlying insulating layer can together be referred to as “a tier,” word lines of substantially the same height can be referred to as “a tier of word lines” or similar, and so on. As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process step, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value). In the present disclosure, the term “horizontal/horizontally/lateral/laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical” or “vertically” means nominally perpendicular to the lateral surface of a substrate. As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. FIG.1illustrates a top-down view of an exemplary three-dimensional (3D) memory device100, according to some embodiments of the present disclosure. The 3D memory device100can be a memory chip (package), a memory die or any portion of a memory die, and can include one or more memory planes101, each of which can include a plurality of memory blocks103. Identical and concurrent operations can take place at each memory plane101. The memory block103, which can be megabytes (MB) in size, is the smallest size to carry out erase operations. Shown inFIG.1, the exemplary 3D memory device100includes four memory planes101and each memory plane101includes six memory blocks103. Each memory block103can include a plurality of memory cells, where each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. The direction of bit lines and word lines are labeled as “BL” and “WL” inFIG.1. In this disclosure, memory block103is also referred to as a “memory array” or “array.” The memory array is the core area in a memory device, performing storage functions. The 3D memory device100also includes a periphery region105, an area surrounding memory planes101. The periphery region105contains many digital, analog, and/or mixed-signal circuits to support functions of the memory array, for example, page buffers, row and column decoders and sense amplifiers. Peripheral circuits use active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art. It is noted that, the arrangement of the memory planes101in the 3D memory device100and the arrangement of the memory blocks103in each memory plane101illustrated inFIG.1are only used as an example, which does not limit the scope of the present disclosure. Referring toFIG.2, an enlarged top-down view of a region108inFIG.1is illustrated, according to some embodiments of the present disclosure. The region108of the 3D memory device100can include a staircase region210and a channel structure region211. The channel structure region211can include an array of memory strings212, each including a plurality of stacked memory cells. The staircase region210can include a staircase structure and an array of contact structures214formed on the staircase structure. In some embodiments, a plurality of slit structures216, extending in the direction of the word lines (WL) across the channel structure region211and the staircase region210, can divide a memory block into multiple memory fingers218, where the direction of the WL (i.e., the WL direction) is similar to the one shown inFIG.1. At least some slit structures216can function as the common source contact for an array of memory strings212in channel structure regions211. A top select gate cut220can be disposed, for example, in the middle of each memory finger218to divide a top select gate (TSG) of the memory finger218into two portions, and thereby can divide a memory finger into two memory slices224, where memory cells in a memory slice224that share the same word line form a programmable (read/write) memory page. While erase operation of a 3D NAND memory can be carried out at memory block level, read and write operations can be carried out at memory page level. A memory page can be kilobytes (KB) in size. In some embodiments, region108also includes dummy memory strings222for process variation control during fabrication and/or for additional mechanical support. FIG.3illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure300, according to some embodiments of the present disclosure. The memory array structure300includes a substrate330, an insulating film331over the substrate330, a tier of lower select gates (LSGs)332over the insulating film331, and a plurality of tiers of control gates333, also referred to as “word lines (WLs),” stacking on top of the LSGs332to form a film stack335of alternating conductive and dielectric layers. The dielectric layers adjacent to the tiers of control gates are not shown inFIG.3for clarity. The control gates of each tier are separated by slit structures216-1and216-2through the film stack335. The memory array structure300also includes a tier of top select gates (TSGs)334over the stack of control gates333. The stack of TSG334, control gates333and LSG332is also referred to as “gate electrodes.” The memory array structure300further includes memory strings212and doped source line regions344in portions of substrate330between adjacent LSGs332. Each memory string212includes a channel hole336extending through the insulating film331and the film stack335of alternating conductive and dielectric layers. Memory strings212also includes a memory film337on a sidewall of the channel hole336, a channel layer338over the memory film337, and a core filling film339surrounded by the channel layer338. A memory cell340can be formed at the intersection of the control gate333and the memory string212. The memory array structure300further includes a plurality of bit lines (BLs)341connected with the memory strings212over the TSGs334. The memory array structure300also includes a plurality of metal interconnect lines343connected with the gate electrodes through a plurality of contact structures214. The edge of the film stack335is configured in a shape of staircase to allow an electrical connection to each tier of the gate electrodes. InFIG.3, for illustrative purposes, three tiers of control gates333-1,333-2, and333-3are shown together with one tier of TSG334and one tier of LSG332. In this example, each memory string212can include three memory cells340-1,340-2and340-3, corresponding to the control gates333-1,333-2and333-3, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The memory array structure300can also include other structures, for example, TSG cut, common source contact and dummy memory string. These structures are not shown inFIG.3for simplicity. To pursue higher storage capacity in a 3D memory, the number of vertically stacked memory cells has been increased greatly. As a result, the number of control gates or word lines333has been increased greatly. To form electrical contact (e.g., contact structure214) for each word line333, the staircase region210has been extended laterally from either side of the channel structure region211. The increased dimension of staircase region210reduces the effective storage capacity per unit area and thus increases cost per bit of the 3D memory. Furthermore, large staircase region210may introduce mechanical stress in the channel structure region211, which may cause reliability problems in the memory cells. Therefore, a need exists to form contact structures for a 3D memory without relying on a staircase structure. FIG.4illustrates an exemplary fabrication process400for forming a 3D memory device, accordance to some embodiments of the present disclosure.FIGS.5-13,14A-14B,15-20illustrate cross-sectional views of the 3D memory device at various process steps according to the fabrication process400. It should be understood that the process steps shown in fabrication process400are not exhaustive and that other process steps can be performed as well before, after, or between any of the illustrated process steps. In some embodiments, some process steps of exemplary fabrication process400can be omitted or other process steps can be included, which are not described here for simplicity. In some embodiments, process steps of fabrication process400can be performed in a different order and/or vary. As shown inFIG.4, fabrication process400starts at process step S410, where an alternating dielectric stack can be disposed on a substrate. An example of a 3D memory device at the process step S410is shown as a 3D memory structure500inFIG.5. In some embodiments, the substrate of the 3D memory structure500can be similar to the substrate330inFIG.3. The substrate330can provide a platform for forming subsequent structures. In some embodiments, the substrate330can be any suitable semiconductor substrate having any suitable semiconductor materials, such as monocrystalline, polycrystalline or single crystalline semiconductors. For example, the substrate330can include silicon, silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compound, or any combinations thereof. In some embodiments, the substrate330can include a layer of semiconductor material formed on a handle wafer, for example, glass, plastic, or another semiconductor substrate. A front surface330fof the substrate330is also referred to as a “main surface” or a “top surface” of the substrate herein. Layers of materials can be disposed on the front surface330fof the substrate330. A “topmost” or “upper” layer is a layer farthest or farther away from the front surface330fof the substrate. A “bottommost” or “lower” layer is a layer closest or closer to the front surface330fof the substrate. In some embodiments, the alternating dielectric stack554includes a plurality of dielectric layer pairs556alternatingly stacked on top of each other, where each dielectric layer pair556includes a first dielectric layer558and a second dielectric layer560(also referred to as “sacrificial layer”) that is different from the first dielectric layer558. The alternating dielectric stack554extends in a lateral direction that is parallel to the front surface330fof the substrate330. In the alternating dielectric stack554, first dielectric layers558and second dielectric layers560alternate in a vertical direction, perpendicular to the substrate330. In the other words, each second dielectric layer560can be sandwiched between two first dielectric layers558, and each first dielectric layer558can be sandwiched between two second dielectric layers560(except the bottommost and the topmost layer). The formation of the alternating dielectric stack554can include disposing the first dielectric layers558to each have the same thickness or to have different thicknesses. Example thicknesses of the first dielectric layers558can range from 10 nm to 500 nm, preferably about 25 nm. Similarly, the second dielectric layer560can each have the same thickness or have different thicknesses. Example thicknesses of the second dielectric layer560can range from 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of dielectric layer pairs556inFIG.5is for illustrative purposes only and that any suitable number of layers may be included in the alternating dielectric stack554. In some embodiments, the first dielectric layer558includes any suitable insulating materials, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS or silicon oxide with F-, C-, N-, and/or H-incorporation. The first dielectric layer558can also include high-k dielectric materials, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide films. In some embodiments, the first dielectric layer558can be any combination of the above materials. The formation of the first dielectric layer558on the substrate330can include any suitable deposition methods such as, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density-plasma CVD (HDP-CVD), thermal oxidation, nitridation, any other suitable deposition method, and/or combinations thereof. In some embodiments, the second dielectric layer560includes any suitable material that is different from the first dielectric layer558and can be removed selectively with respect to the first dielectric layer558. For example, the second dielectric layer560can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon, and any combinations thereof. In some embodiments, the second dielectric layer560also includes amorphous semiconductor materials, such as amorphous silicon or amorphous germanium. The second dielectric layer560can be disposed using a similar technique as the first dielectric layer558, such as CVD, PVD, ALD, thermal oxidation or nitridation, or any combination thereof. In some embodiments, the first dielectric layer558can be silicon oxide and the second dielectric layer560can be silicon nitride. In some embodiments, the alternating dielectric stack554can include layers in addition to the first dielectric layer558and the second dielectric layer560, and can be made of different materials and/or with different thicknesses. In addition to the alternating dielectric stack554, in some embodiments, peripheral devices (not shown) can be formed in the periphery region105(seeFIG.1) on the front surface330fof the substrate330. In some embodiments, active device areas (not shown) can also be formed in the memory blocks103(seeFIG.1) on the front surface330fof the substrate330. In some embodiments, the substrate330can further include an insulating film331on the front surface330f(not shown inFIG.5). The insulating film331can be made of the same or different material from the alternating dielectric stack554. The peripheral devices can include any suitable semiconductor devices, for example, metal oxide semiconductor field effect transistors (MOSFETs), diodes, resistors, capacitors, etc. The peripheral devices can be used in the design of digital, analog and/or mixed signal circuits supporting the storage function of the memory core, for example, row and column decoders, drivers, page buffers, sense amplifiers, timing and controls. The active device areas in the memory blocks are surrounded by isolation structures, such as shallow trench isolation. Doped regions, such as p-type doped and/or n-type doped wells, can be formed in the active device area according to the functionality of the array devices in the memory blocks. Referring toFIG.4, at process step S415, a hard mask can be disposed on the alternating dielectric stack, according to some embodiments of the present disclosure. An example of a 3D memory device at process step S415is illustrated as a 3D memory structure600inFIG.6. The 3D memory structure600includes a hard mask662disposed on the alternating dielectric stack554. The hard mask662is used to provide protection to the underlying structures and materials during subsequent etching process. In some embodiments, the hard mask662includes any suitable material that can withstand the etching process, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous silicon, polycrystalline silicon, high-k dielectric materials, or any combination thereof. In some embodiments, the hard mask662can include amorphous carbon. In some embodiments, amorphous carbon can be doped with other etch-resistant elements, such as boron, to improve the etch-resistance of the amorphous carbon. In some embodiments, a thin metal or metal oxide layer, such as zirconium oxide (ZrO2), yttrium oxide (Y2O3), and aluminum oxide (Al2O3), can be disposed on top of the amorphous carbon layer. The hard mask662can be disposed by LPCVD, RTCVD, PECVD, ALD, PVD, evaporation, sputtering, or any combination thereof. FIG.7illustrates a 3D memory structure700, according to some embodiments of the present disclosure. The 3D memory structure700includes a contact defining mask764disposed on the hard mask662over the alternating dielectric stack554. In some embodiments, the contact defining mask764can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. The contact defining mask764defines the location of contact structures for control gates and select gates of a 3D memory device that will be formed in the subsequent processes. In some embodiments, the contact structures can be similar to the contact structures214for the control gate333, top select gate (TSG)334and lower select gate (LSG)332shown inFIG.3. The contact structures214can be placed in a region (e.g., the staircase region210) adjacent to the channel structure region211inFIG.3. In some embodiments, the contact structures214can also be placed inside the channel structure region211, which will be discussed in detail below. Referring toFIG.4, at process step S420, a plurality of hard mask openings can be formed by patterning the hard mask, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S420is illustrated as a 3D memory structure800inFIG.8. The 3D memory structure800includes a plurality of hard mask openings866, formed by patterning the hard mask662using the contact defining mask764inFIG.7. The hard mask openings expose a top surface866-tof the first dielectric layer pair (i.e., the topmost dielectric layer pair in the alternating dielectric stack554). In some embodiments, the hard mask openings866can be patterned by using a suitable etching process such as wet etching, dry etching, and/or a combination thereof. In some embodiments, the hard mask662can be etched using an anisotropic etching such as a reactive ion etching (ME) or other dry etching processes. In some embodiments, the hard mask662is silicon oxide. In this example, the etching of silicon oxide can include ME using fluorine-based gases such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6and/or any other suitable gases. In some embodiments, the silicon oxide layer can be etched by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the hard mask662is silicon nitride. In this example, the etching of silicon nitride can include ME using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and/or combinations thereof. The methods and etchants to pattern the hard mask662should not be limited by the embodiments of the present disclosure. In some embodiments, after forming the hard mask openings866, the contact defining mask764inFIG.7can be removed by using techniques such as dry etching with O2or CF4plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals. Referring toFIG.4, at process step S425, a first contact mask can be formed over the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S425is illustrated as a 3D memory structure900inFIG.9. In some embodiments, the 3D memory structure900includes a first contact mask968disposed on the 3D memory structure800, over at least a portion of the alternating dielectric stack. In some embodiments, the first contact mask968covers half of the hard mask openings866and exposes the other half of the hard mask openings866. In some embodiments, the first contact mask968can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. Referring toFIG.4, at process step S430, a first subset of contact openings can be formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S430is illustrated as a 3D memory structure1000inFIG.10. The 3D memory structure1000includes a first subset of contact openings1070. In some embodiments, the first subset of contact openings1070can be formed by etching one dielectric layer pair556using the first contact mask968shown inFIG.9. The first subset of contact openings1070expose a top surface1070-tof the second dielectric layer pair, where the second dielectric layer pair is located below the first or topmost dielectric layer pair in the alternating dielectric stack554. In this disclosure, the dielectric layer pairs are counted sequentially from top to bottom in the alternating dielectric stack554. In some embodiments, one or more dielectric layer pairs556can be etched with the first contact mask968. The etching process for the first dielectric layer558can have a high selectivity over the second dielectric layer560, and/or vice versa. Accordingly, an underlying dielectric layer pair556can function as an etch-stop layer. As a result, multiple dielectric layer pairs556can be etched controllably. In some embodiments, dielectric layer pair556can be etched by using an anisotropic etching such as a reactive ion etching (RIE) or other dry etching processes. In some embodiments, the first dielectric layer558is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6and/or any other suitable gases. In some embodiments, the silicon oxide layer can be etched by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the second dielectric layer560is silicon nitride. In this example, the etching of silicon nitride can include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and/or combinations thereof. The methods and etchants used for etching the dielectric layer pair556should not be limited by the embodiments of the present disclosure. In some embodiments, after forming the first subset of contact openings1070, the first contact mask968can be removed by using techniques such as dry etching with O2or CF4plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals. In some embodiments, after the process step S430, half of the hard mask openings866can be converted to the first subset of contact openings1070, with the other half remains as hard mask openings866. Accordingly, top surfaces of the first and second dielectric layer pairs866-tand1070-tcan be exposed inside the hard mask openings866and the first subset of contact openings1070, respectively. In some embodiments, the alternating dielectric stack554includes L number of dielectric layer pairs556. In some embodiments, the 3D memory structure800(inFIG.8) includes N number of hard mask openings866, wherein the number N is larger or equal to the number L, i.e., N≥L. In this example, half of the hard mask openings866can be converted to the first subset of contact openings1070. In the other words, after process step S430, the number of first subset of contact openings1070can be N/2 and the number of remaining hard mask openings866can also be N/2. However, the first subset of contact openings1070is not limited as described above and can include any suitable number of the hard mask openings866. Referring toFIG.4, at process step S435, a second contact mask can be formed over the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S435is illustrated as a 3D memory structure1100inFIG.11. In some embodiments, the 3D memory structure1100includes a second contact mask1172disposed on the 3D memory structure1000, over at least a portion of the alternating dielectric stack554. In some embodiments, the second contact mask1172covers half of the remaining hard mask openings866and exposes the other half of the remaining hard mask openings866. In some embodiments, the second contact mask1172also covers half of the first subset of contact openings1070and exposes the other half of the first subset of contact openings1070. In some embodiments, the second contact mask1172can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. Referring toFIG.4, at process step S440, a second subset of contact openings and a third subset of contact openings can be formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S440is illustrated as a 3D memory structure1200inFIG.12. The 3D memory structure1200includes a second subset of contact openings1274and a third subset of contact openings1275. In some embodiments, the second and third subsets of contact openings1274can be formed by etching two dielectric layer pairs556using the second contact mask1172shown inFIG.11. In some embodiments, one or more dielectric layer pairs556can be etched with the second contact mask1172. The etching processes for the first and second dielectric layers558and560can be similar to those used for the first subset of contact openings1070, where each dielectric layer pair556can be etched controllably with an etch-stop on the underlying dielectric layer pair556. In some embodiments, the first and second contact masks968and1172can be designed such that the second subset of contact openings1274include half of the first subset of contact openings1070and the third subset of contact openings1275include half of the remaining hard mask openings866that are not converted to the first subset of contact openings1070at the process step430. In the example that the hard mask openings866are formed by etching through the hard mask662and the first subset of contact openings1070are formed by etching one dielectric layer pair556, by etching two dielectric layer pair556at process step S440, the second subset of contact openings1274can extend through three dielectric layer pairs and expose a top surface1274-tof the fourth dielectric layer pair. In the meantime, the third subset of contact openings1275can extend through two dielectric layer pairs and expose a top surface1275-tof the third dielectric layer pair. Accordingly, after process step S440, half of the first subset of contact openings1070are converted to the second subset of contact openings1274and half of the remaining hard mask openings866are converted to the third subset of contact openings1275. As shown inFIG.12, the 3D memory structure1200can also include some of the first subset of contact openings1070extending through one dielectric layer pair556and exposing the top surface1070-tof the second dielectric layer pair. The 3D memory structure1200can also include some of the hard mask openings866extending through the hard mask662and exposing the top surface866-tof the first dielectric layer pair. As illustrated inFIG.11, these openings are covered by the second contact mask1172at process step S435, and are protected during the etching process of the dielectric layer pairs556at process step S440. Therefore, depths of the aforementioned openings are not changed at process step S440. After process step S440, top surfaces of the first, second, third and fourth dielectric layer pairs can be exposed inside in the hard mask openings866, the first subset of contact openings1070, the third subset of contact openings1275and the second subset of contact openings1274, respectively. In the example that the 3D memory structure1000includes N/2 number of first subset of contact openings1070and N/2 number of hard mask openings866, after process step S430, the 3D memory structure1200can include N/4 number of second subset of contact openings1274and N/4 number of third subset of contact openings1275. In the meantime, there can be N/4 number of first subset of contact openings1070and N/4 number of hard mask openings866remaining in the 3D memory structure1200. It is noted that arrangement of the first, second and third subsets of contact openings1070,1274and1275and the hard mask openings866inFIG.12is for illustration purpose only. The 3D memory structure1200can include different arrangements and depths in the first, second and third subsets of contact openings1070,1274and1275, as well as the hard mask openings866. Referring toFIG.4, at process step S445, a third contact mask is formed over the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S445is illustrated as a 3D memory structure1300inFIG.13. The 3D memory structure1300includes a third contact mask1376disposed on the 3D memory structure1200, over at least a portion of the alternating dielectric stack554. In some embodiments, the third contact mask1376covers half of the remaining hard mask openings866and exposes the other half of the remaining hard mask openings866. In some embodiments, the third contact mask1376also covers half of the remaining first subset of contact openings1070and exposes the other half of the remaining first subset of contact openings1070. In some embodiments, the third contact mask1376also covers half of the second subset of contact openings1274and exposes the other half of the second subset of contact openings1274. In some embodiments, the third contact mask1376also covers half of the third subset of contact openings1275and exposes the other half of the third subset of contact openings1275. In some embodiments, the third contact mask1376can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. Referring toFIG.4, at process step S450, a fourth subset, a fifth subset, a sixth subset and a seventh subset of contact openings are formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S450is illustrated as a 3D memory structure1400inFIG.14A. The 3D memory structure1400includes a fourth subset of contact openings1478, a fifth subset of contact openings1479, a sixth subset of contact openings1480and a seventh subset of contact openings1481, formed in the alternating dielectric stack554, according to some embodiments of the present disclosure. In some embodiments, the fourth, fifth, sixth and seventh subsets of contact openings1478-1481can be formed by etching four dielectric layer pairs556using the third contact mask1376shown inFIG.13. In some embodiments, one or more dielectric layer pairs556can be etched using the third contact mask1376. The etching processes for the first and second dielectric layers558and560can be similar to those used for the first, second and third subsets of contact openings1070,1274and1275, where each dielectric layer pair556can be etched controllably with an etch-stop on the underlying dielectric layer pair556. FIG.14Billustrates the relationships between contact openings at various process steps, according to some embodiments of the present disclosure. The dielectric layer pair566(counted from top to bottom) that each contact opening exposes is shown in parenthesis. In some embodiments, the first, second and third contact masks968,1172and1376can be designed such that a portion of the hard mask openings866can be converted to the first subset of contact openings1070at process step S430. A portion of the first subset of contact openings1070can be converted to the second subset of contact openings1274at process step S440and then a portion of the second subset of contact openings1274can be converted to the fourth subset of contact openings1478at process step S450. In the meantime, a portion of the remaining first subset of contact openings1070at process step S440can be converted to the fifth subset of contact openings1479at process step S450. In this example, a portion of the remaining hard mask openings866at process step S430can be converted to the third subset of contact openings1275at process step S440, while a portion of the third subset of contact openings1275can be converted to the seventh subset of contact openings1481at process step S450. A portion of the remaining hard mask openings866at process step S440can be converted to the sixth subset of contact openings1480at process step S450. It is noted that the portion of contact openings subjected to the etching of dielectric layer pair566at each process step can be any suitable number and is not limited to a half or 50% shown in theFIGS.9-13and14A. As discussed previously, in some embodiments, there are N number of hard mask openings866after process step S420and the 3D memory structure1000can have N/2 number of first subset of contact openings1070and N/2 number of hard mask openings866after process step S420. The 3D memory structure1200can have N/4 number of first subset of contact openings1070, N/4 number of second subset of contact openings1274, N/4 number of third subset of contact openings1275, and N/4 number of hard mask openings866after process step S440. In some embodiments, the 3D memory structure1400can have N/8 number of first subset of contact openings1070, N/8 number of second subset of contact openings1274, N/8 number of third subset of contact openings1275, N/8 number of fourth subset of contact openings1478, N/8 number of fifth subset of contact openings1479, N/8 number of sixth subset of contact openings1480, N/8 number of seventh subset of contact openings1481and N/8 number of hard mask openings866. As previously discussed, in some embodiments, the hard mask openings866can be formed by etching through the hard mask662at process step S420, and the first subset of contact openings1070can be formed by etching one dielectric layer pair556at process step S430. Subsequently, the second and third subsets of contact openings1274and1275can be formed by etching two dielectric layer pairs556at process step S440. Accordingly, the hard mask opening866can expose the first dielectric layer pair, i.e., the topmost dielectric layer pair. The first subset of contact openings1070, converted from the hard mask openings866, can extend through one dielectric pair566and expose the second dielectric pair, below the first dielectric layer pair. The second and third subsets of contact openings1274and1275, converted from respective first subset of contact openings1070and the hard mask openings866, can extend through three and two dielectric layer pairs566, respectively. In the other words, the second and third subsets of contact openings1274and1275can expose the fourth and the third dielectric layer pair, respectively. Referring toFIGS.14A and14B, in some embodiments, the fourth to seventh subsets of contact openings1478-1481can be formed by etching through four dielectric layer pairs556. As a result, after process step S450, the fourth subset of contact openings1478, converted from the second subset of contact openings1274, can extend through seven dielectric layer pairs556and expose a top surface1478-tof the eighth dielectric layer pair. The fifth subset of contact openings1479, converted from the first subset of contact openings1070, can extend through five dielectric layer pairs556and expose a top surface1479-tof the sixth dielectric layer pair. The sixth subset of contact openings1480, converted from the hard mask openings866, can extend through four dielectric layer pairs556and expose a top surface1480-tof the fifth dielectric layer pair. Similarly, the seventh subset of contact openings1481, converted from the third subset of contact openings1070, can extend through six dielectric layer pairs556and expose a top surface1481-tof the seventh dielectric layer pair. It is noted that arrangement of the first to seventh subsets of contact openings1070,1274-1275,1478-1481and the hard mask openings866inFIGS.14A and14Bare for illustration purpose only. The 3D memory structure1400can have different arrangements and different depths (i.e., etched dielectric layer pair) in the first to seventh subsets of contact openings1070,1274-1275,1478-1481and the hard mask openings866. In the other words, the aforementioned contact openings can be randomly distributed in the alternating dielectric stack554. The fabrication processes can be continued by forming another contact mask covering at least a portion of the contact holes on the 3D memory structure1400and then etching one or more dielectric layer pairs566. These process steps can be repeated until a top surface of each dielectric layer pair566is exposed inside at least one of the contact openings. In some embodiments, at an i-th process step for forming one or more subsets of contact openings, where 1=1, 2, 3, . . . , each of current subsets of contact openings can be split into two groups, where one group can be subject to an etching process of 2(i−1)number of dielectric layer pairs and form new subsets of contact openings. The other group in each of current subsets of contact openings can be protected by a mask and exposed to the etching process. After the i-th process step, top surfaces of the 1st, 2nd, 2i-th dielectric layer pairs can be exposed inside at least one of the contact openings. In some embodiments, each of the current subsets of contact openings can be split into two groups with equal number of contact openings, where one group remains the same as current subsets of contact openings and the other group forms new subsets of contact openings. For example, N number of hard mask openings can be split into N/2 number of hard mask openings and N/2 number of first subset of contact openings. Next, the first subset of contact openings can be split into N/4 number of second subset of contact openings and N/4 number of first subset of contact openings . . . and so on. In this example, at least one contact opening can be formed for each dielectric layer pair of an alternating dielectric stack with a total 2(i−1)number of dielectric layer pairs by using as few as n number of masks and etching steps. After forming contact openings in the alternating dielectric stack554, the hard mask662can be removed. Referring toFIG.4, at process step S455, a filling material can be disposed inside the contact openings, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S455is illustrated as a 3D memory structure1500inFIG.15. The 3D memory structure1500includes contact fills1584formed by disposing a filling material1586inside the contact openings (1070,1274-1275,1478-1481) and hard mask openings866in the 3D memory structure1400(as shown inFIG.14A). In some embodiments, the contact fill1584also include a liner1587disposed prior to the deposition of the filling material1586. The filling material1586and the liner1587can be any suitable material that can be selectively removed over the first dielectric layer558and/or second dielectric layer560in the subsequent processes. In some embodiments, the filling material1586and the liner1587can be an insulator, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous carbon, and/or a combination thereof. In some embodiments, the filling material1586can be silicon nitride and the liner1587can be silicon oxide. The filling material1586and the liner1587can be formed by CVD, PVD, sputtering, evaporating, and/or any combination thereof. In some embodiments, the 3D memory structure1500can be planarized after disposing the filling material1586and the liner1587to form a coplanar top surface. Referring toFIG.4, at process step S460, a plurality of memory strings can be formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S460is illustrated as a 3D memory structure1600inFIG.16. The 3D memory structure1600includes a plurality of memory strings (e.g., the memory strings212inFIGS.2and3). To form the plurality of memory strings212, a plurality of channel holes (e.g., the channel holes336) can be formed first in the alternating dielectric stack554, penetrating the entire alternating dielectric stack554and extending into the substrate330. In some embodiments, forming of the channel holes336includes processes such as photolithography and etching. In some embodiments, a capping layer1688formed by a carbon-based polymer material or a hard mask can be used in addition to photoresist for the etching process. The capping layer1688can include silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon, or any combination thereof. The etching process to form the channel holes336can include a dry etching, a wet etching, or a combination thereof. In some embodiments, the alternating dielectric stack554can be etched using an anisotropic etching such as a reactive ion etch (ME). In some embodiments, fluorine or chlorine based gases such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, C3F6, Cl2, BCl3, etc., or any combination thereof, can be used. The methods and etchants to etch the first and second dielectric layers558/560should not be limited by the embodiments of the present disclosure. In some embodiments, the 3D memory structure1600further includes an epitaxial layer1690inside the channel hole336. The epitaxial layer1690can include any suitable semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compound, or any combination thereof. The epitaxial layer1690can be epitaxially grown from the substrate330. In some embodiments, the epitaxial layer1690can be selectively grown from an exposed surface of the substrate330inside the channel hole336. In some embodiments, the epitaxial layer1690can be a polycrystalline semiconductor material, for example, polycrystalline silicon. In some embodiments, the epitaxial layer1690can be epitaxially grown from a doped region (not shown inFIG.16) in the substrate330. The doped region can be formed by ion implantation using p-type or n-type dopants, for example boron, phosphorus, arsenic, or any combination thereof. The ion implantation can be performed before the deposition of the alternating dielectric stack554. In some embodiments, the ion implantation can be performed after channel hole etching. After forming the channel holes336and epitaxial layer1690, a memory film (e.g., the memory film337inFIG.3) can be disposed on a sidewall of each channel hole336, and a top surface of the epitaxial layer558. In some embodiments, the memory film337can be a composite layer including a tunneling layer, a storage layer (also known as “charge trap/storage layer”), and a blocking layer. Each channel hole336can have a cylinder shape. The tunneling layer, the storage layer, and the blocking layer are arranged along a direction from the center toward the outer of the channel hole in the above order, according to some embodiments. The tunneling layer can include silicon oxide, silicon nitride, or any combination thereof. The blocking layer can include silicon oxide, silicon nitride, high dielectric constant (high-k) dielectrics, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film337includes ONO dielectrics (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide). Next, a channel layer338and a core filling film339can be disposed inside the channel holes336. The channel layer338covers a sidewall of the memory film337inside the channel hole336and is connected with the epitaxial layer1690. The channel layer338can be any suitable semiconductor material such as silicon. In some embodiments, the channel layer338can be amorphous, polysilicon, or single crystalline silicon. The channel layer338can be formed by any suitable thin film deposition processes including, but not limited to, CVD, PVD, ALD, or a combination thereof. In some embodiments, a thickness of the channel layer338can be in a range from about 10 nm to about 30 nm. In some embodiments, the core filling film339can be disposed to fill each channel hole336. In some embodiments, the middle of the core filling film339can include one or more air gaps. The core filling film339can be any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on-glass, boron or phosphorus doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine doped oxide (SiOF), or any combination thereof. The core filling film339can be deposited by using, for example, ALD, PVD, CVD, spin-coating, sputtering, or any other suitable film deposition techniques. The core filling film339can also be formed by using repeated deposition and etch-back processes. The etch-back process can include, but not limited to, a wet etching, a dry etching, or a combination thereof. In some embodiments, the core filling film339, the channel layer338and the capping layer1688are can be coplanar in the 3D memory structure1600. The planarization process includes chemical mechanical polishing, ME, wet etching, or a combination thereof. The planarization process removes excess core filling film339, channel layer338and the memory film337outside the channel hole336. Accordingly, the channel layer338and the memory film337can be disconnected between adjacent channel holes336. In some embodiments, a plurality of dummy memory strings (e.g., the dummy memory strings222inFIG.2) can also be formed in the alternating dielectric stack554, adjacent to the memory strings212and/or contact openings1070,1274-1275, and1478-1481. While the memory strings212can be used for memory storage, dummy memory strings222can be used to provide structural support and improve process uniformity during manufacturing. In some embodiments, the dummy memory strings222can also include the core filling film339and can be formed using similar techniques as the memory strings212. FIG.17illustrates a 3D memory structure1700, according to some embodiments of the present disclosure. The 3D memory structure1700includes a plurality of slit openings1792penetrating through the entire alternating dielectric stack554. In some embodiments, the slit openings1792can extend laterally along the WL direction in the x-y plane that parallel to the top surface330f. The slit openings1792can form slit structures216(inFIGS.2and3) in subsequent fabrication processes. The arrangement of the slit openings1792inFIG.17is only for illustration purpose and is not so limited. Referring toFIG.4, at process step S465, a film stack of alternating conductive and dielectric layers can be formed, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S465is illustrated as a 3D memory structure1800inFIG.18. The 3D memory structure1800includes a film stack of alternating conductive and dielectric layers, similar to the film stack335inFIG.3. After forming the slit openings1792, the second dielectric layer560in the alternating dielectric stack554(inFIG.17) can be removed laterally from the slit openings1792, forming lateral tunnels (not shown inFIG.18). Conductive layers1894can then be disposed inside these lateral tunnel to form the film stack335. The second dielectric layer560(inFIG.17) can be removed by any suitable etching process, e.g., an isotropic dry etch or wet etch, that is selective over the alternating dielectric stack554, such that the etching process can have minimal impact on the first dielectric layer558. In some embodiments, the second dielectric layer560can be silicon nitride. In this example, the second dielectric layer560can be removed by RIE using one or more etchants of CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, the second dielectric layer560can be removed using wet etch, such as phosphoric acid. After removing the second dielectric layer560, sidewalls of the memory film337can be exposed in the lateral tunnels. In some embodiments, the conductive layer1894can include any suitable conductive material that is suitable for a gate electrode, e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and/or any combination thereof. The conductive material can fill the lateral tunnels using a suitable deposition method such as CVD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, thermal evaporation, e-beam evaporation, metal-organic chemical vapor deposition (MOCVD), and/or ALD. In some embodiments, the conductive layers1894include tungsten (W) deposited by CVD. In some embodiments, the conductive layer1894can also be poly-crystalline semiconductors, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the conductive layer1894can also be amorphous semiconductors. In some embodiments, the conductive layer1894can be made from a metal silicide, including WSix, CoSix, NiSix, or AlSix, etc. The forming of the metal silicide material can include forming a metal layer and a poly-crystalline semiconductor using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer, followed by removal of unreacted metal. In some embodiments, a gate dielectric layer can be disposed in the lateral tunnels prior to the conductive layer1894(not shown inFIG.18) to reduce leakage current between adjacent word lines (gate electrodes) and/or to reduce leakage current between gate and channel. The gate dielectric layer can include silicon oxide, silicon nitride, silicon oxynitride, and/or any suitable combinations thereof. The gate dielectric layer can also include high-k dielectric materials, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and/or any combination thereof. The gate dielectric layer can be disposed by one or more suitable deposition processes, such as CVD, PVD, and/or ALD. The conductive layers1894can function as gate electrodes at the intersection with memory strings212. InFIG.18, the ten conductive layers1894can form ten gate electrodes for each memory string212, e.g., TSG334, LSG332and eight control gates333. Corresponding to eight control gates333, each memory string212can have eight memory cells340. It is noted that the number of memory strings and memory cells are shown for illustrative purposes inFIG.18, and can be increased for higher storage capacity. After forming the film stack335of alternating conductive and dielectric layers, conductive materials inside the slit openings1792during deposition can be removed. In some embodiments, insulating materials can be disposed inside some of the slit openings1792to form slit structures216, separating a memory block into multiple programmable and readable memory fingers (seeFIG.2A-2B). FIG.19illustrates a 3D memory structure1900, according to some embodiments of the present disclosure. The 3D memory structure1900includes a plurality of contact holes1996, formed by removing the filling materials1586inside the contact fills1584in the 3D memory structure1800inFIG.18. In some embodiments, the contact holes1996can be formed by lithography, wet chemical etch, dry etch, or a combination thereof. In some embodiments, the contact holes1996extend through the capping layer1688, one or more pairs of conductive layer1894and first dielectric layer558. The contact holes1996can expose the conductive layer1894in the film stack335. In some embodiments, the liner1587covers a sidewall of each conductive layer1894inside each contact hole1996. A top surface of a conductive layer1894can be exposed at a bottom of each contact hole1996. As shown inFIG.19, the contact hole1996can go through at least one more first dielectric layer558to expose one conductive layer1894at the bottom of the contact hole1996. As such, the liner1587is distant from the bottom of the contact hole1996in a direction perpendicular to the substrate, and is thereby distant from the exposed conductive layer1894at the bottom of the contact hole1996. In some embodiments, an isolation liner1997can be formed on a sidewall of the slit opening1792, where the isolation liner1997inside the slit opening1792covers a sidewall of each conductive layer1894of the film stack335. In some embodiments, the isolation liner1997can also be formed inside the contact hole1996. The isolation liner1997can be any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. Referring toFIG.4, at process step S470, a contact structure can be formed to electrically connect with the conductive layer in the film stack of alternating conductive and dielectric layers, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S470is illustrated as a 3D memory structure2000inFIG.20. The 3D memory structure2000includes a plurality of contact structures, similar to the contact structures214inFIG.3, where the contact structure214provides electric connection with the conductive layer1894in the film stack335. In some embodiments, each contact structure214includes a liner surrounding a conductive material. In some embodiments, the isolation liner1997and/or the liner1587, covered a sidewall of the contact structure214, can electrically isolate the contact structure214from one or more conductive layers1894of the film stack335. The 3D memory structure2000can also include a common source contact2098, electrically connected with the substrate330. In some embodiments, the isolation liner1997can electrically isolate the common source contact2098from the conductive layers1894of the film stack335. As described above, the liner1587is distant from the exposed conductive layer1894at the bottom of the contact hole1996. Therefore, after forming the contact structure214, the liner1587is distant from the respective conductive layer1894that is electrically connected to the contact structure214. (SeeFIG.20.) The contact structure214and the common source contact2098can be formed by disposing a conductive material inside the contact hole1996and the slit opening1792. In some embodiments, the conductive material can include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and/or any combination thereof. The conductive material can be disposed by CVD, PVD, PECVD, MOCVD, sputtering, thermal evaporation, e-beam evaporation, ALD, and/or a combination thereof. In some embodiments, the conductive material can be tungsten (W) deposited by CVD. In some embodiments, the conductive material used for the contact structure214and common source contact2098can also be poly-crystalline semiconductors, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the conductive material can also be amorphous semiconductors. In some embodiments, the conductive material can be made from a metal silicide, including WSix, CoSix, NiSix, or AlSix, etc. The forming of the metal silicide material can include forming a metal layer and a poly-crystalline semiconductor using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer, followed by removal of unreacted metal. In some embodiments, excess conductive material outside the contact hole1996and slit opening1792can be removed after the deposition by using an etching process or planarization process. The etching process to remove the excess conductive material can include wet chemical etch and/or dry etch (e.g., RIE). The planarization process can include chemical mechanical polishing (CMP). It is noted that the contact structures214inFIG.20and contact holes1996inFIG.19correspond to the hard mask openings866and/or contact openings1070,1274-1275,1478-1481inFIG.14A. As discussed previously, in some embodiments, at least one contact opening can be formed for each dielectric layer pair in an alternating dielectric stack with a total 2(n−1)number of dielectric layer pairs by using only n number of masks and etching steps. In addition, according to the present disclosure, at least one contact structure214can be formed for each conductive layer1894in the film stack335without using a staircase structure. In this example, the contact structures214can be formed anywhere in the channel structure region211(shown inFIG.2), i.e., inside a memory array, and can be formed adjacent to, or surrounded by, the memory strings212. In some embodiments, the contact structures214can be randomly distributed in the memory array, adjacent to the memory strings212and/or dummy memory strings222. The conductive layer1894of the film stack335can be functioned as gate electrodes, for example, the control gate (word line)333and the top and lower select gates334and332shown inFIG.3. By moving the contact structures214close to the memory strings212, delay from word lines to gate electrodes of the memory cells340can be shortened accordingly. As a result, the performance of the 3D memory device can be improved. In some embodiments, dummy memory strings222can also be formed adjacent to the contact structures214and/or the memory strings212in the memory array. In some embodiments, the contact masks used in the fabrication process400described inFIG.4can have different designs and arrangements.FIGS.21A-21Nprovide perspective views of 3D memory structures at various process steps (e.g., process steps S410-S470), showing a different method to form the contact openings, compared with the examples inFIGS.5-13,14A-14B and15-20. Detailed description forFIGS.21A-21Nis omitted here as the method shown is self-explanatory from these figures and can be understood by a person skilled in the art. FIG.22illustrates another exemplary fabrication process2200for forming a 3D memory device, accordance to some embodiments of the present disclosure.FIGS.23-29illustrate cross-sectional views of the 3D memory device at various process steps according to the fabrication process2200. It should be understood that the process steps shown in fabrication process2200are not exhaustive and that other process steps can be performed as well before, after, or between any of the illustrated process steps. In some embodiments, some process steps of exemplary fabrication process2200can be omitted or other process steps can be included, which are not described here for simplicity. In some embodiments, process steps of fabrication process2200can be performed in a different order and/or vary. Only the differences fromFIGS.4-13,14A-14B, and15-20are illustrated inFIGS.22-29. Similar process steps and structures can be referred back to the previous figures and corresponding descriptions. Referring toFIG.22, fabrication process2200starts at process step S2210, where an alternating dielectric stack is disposed on a substrate. The exemplary 3D memory structure500of a 3D memory device at process step S2210is shown inFIG.5. The alternating dielectric stack554can include first and second dielectric layers558and560. Referring toFIG.22, at process step S2220, channel holes and memory strings can be formed in the alternating dielectric stack. An exemplary 3D memory structure2300at process step S2220is shown inFIG.23, where the channel holes336and the memory strings212are similar to the respective ones inFIG.16and can be formed by using similar techniques. At process step S2220, dummy memory strings, similar to the dummy memory strings222inFIG.16can also be formed by using similar techniques. Referring toFIG.22, at process step S2230, a plurality of contact openings can be formed in the alternating dielectric stack by using multiple contact masks. An exemplary 3D memory structure2400at process step S2230is shown inFIG.24, where the hard mask openings866, the first subset of contact openings1070, the second and third subsets of contact openings1274-1275, and the fourth to seventh subsets of contact openings1478-1481can be similar to the respective ones inFIG.14Aand can be formed by using similar processes in the process steps S415-S450described inFIG.4andFIGS.6-13and14A-14B. Referring toFIG.22, at process step S2240, a liner is disposed on a sidewall of each contact openings. An exemplary 3D memory structure2500at process step S2240is shown inFIG.25, where the liner1587is similar to the one inFIG.15and can be formed using similar techniques. Referring toFIG.22, at process step S2250, slit openings can be formed in the alternating dielectric stack. An exemplary 3D memory structure2600at process step S2250is shown inFIG.26, where the slit opening1792is similar to the one inFIG.17and can be formed using similar techniques. Referring toFIG.22, at process step S2260, a film stack of alternating conductive and dielectric layers can be formed. An exemplary 3D memory structure2700at process step S2260is shown inFIG.27, where the film stack335of alternating conductive and dielectric layers is similar to the one inFIG.18and can be formed using similar techniques. FIG.28illustrates a 3D memory structure2800, according to some embodiments of the present disclosure. The 3D memory structure2800includes the isolation liner1997formed on a sidewall of the slit opening1792. The isolation liner1997can be similar to the one inFIG.19, and can be formed using similar techniques. The 3D memory structure2800can also include the contact holes1996formed inside the plurality of contact openings inFIG.27(e.g., the hard mask openings866, the first subset of contact openings1070, the second and third subsets of contact openings1274-1275, and the fourth to seventh subset of contact openings1478-1481). The contact holes1996expose top surfaces of the conductive layers1894and can be formed using similar techniques as the ones shown inFIG.19. Referring toFIG.22, at process step S2270, contact structures can be formed to electrically connect with the conductive layer in the film stack of alternating conductive and dielectric layers. An exemplary 3D memory structure2900at process step S2270is shown inFIG.29, where the contact structures214are similar to the ones inFIG.20and can be formed using similar techniques. The 3D memory structure2900can also include the common source contact2098, similar to the one inFIG.20. Similar to fabricate process400, fabrication process2200can also form at least one contact structure214for each conductive layer1894in the film stack335of alternating conductive and dielectric layers. These contact structures214can be formed inside the channel structure region211(inFIGS.2-3), and can be arranged adjacent to the memory strings212. In summary, the present disclosure describes various embodiments of a 3D memory device and methods of making the same. The first aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory structure that includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes first and second dielectric layers alternatingly stacked on top of each other. The method also includes forming a plurality of contact openings in the alternating dielectric stack such that a dielectric layer pair is exposed inside at least one of the plurality of contact openings, wherein the dielectric layer pair includes one pair of the first and second dielectric layers. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers. The formation of the plurality of contact openings includes forming a plurality of openings in the alternating dielectric stack by etching N number of dielectric layer pairs (N is a whole number). Next, a mask is formed to protect a first group of the plurality of openings and expose a second group of the plurality of openings, wherein the first group of the plurality of openings is a first subset of openings extending through the N number of dielectric layer pairs. The formation of the plurality of contact openings further includes forming a second subset of openings in the second group of the plurality of openings by etching M number of dielectric layer pairs (M is a whole number). The second subset of openings extend through (N+M) number of dielectric layer pairs. By repeating the steps of forming a mask and etching for each of the subsets of openings, the plurality of contact openings can be formed in the alternating dielectric stack. The second aspect of the present disclosure provides a three-dimensional (3D) memory structure that includes a film stack disposed on a substrate, the film stack having conductive and dielectric layers alternatingly stacked on top of each other. The 3D memory structure also includes a plurality of memory strings vertically penetrating through the film stack, wherein each of the plurality of memory strings comprises a memory film, a channel layer and a core filling film. The 3D memory structure also includes a plurality of contact structures disposed inside the film stack, the plurality of contact structures vertically penetrating one or more conductive and dielectric layers such that each conductive layer of the film stack is electrically connected to at least one of the plurality of contact structures. The plurality of contact structures are surrounded by the plurality of memory strings. The third aspect of the present disclosure provides another method for forming a three-dimensional (3D) memory structure that includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes 2″ number of dielectric layer pairs, wherein n is an integer and each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer. The method also includes forming a plurality of contact openings by using (n+1) cycles of repetitive patterning process. An i-th patterning process includes etching 2(i−1)number of dielectric layer pairs such that top 2inumber of dielectric layer pairs are exposed inside the plurality of contact openings, where i is an integer ranging from 1 to n. The method of forming the 3D memory structure further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure electrically connected to the conductive layer in the film stack of alternating conductive and dielectric layers. The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt, for various applications, such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance. Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. | 76,745 |
11862566 | DETAILED DESCRIPTION FIG.1is a block diagram of a semiconductor device according to an example embodiment. Referring toFIG.1, a semiconductor device10may include a memory cell array20and a peripheral circuit30. The memory cell array20may include a plurality of memory cell blocks BLK1through BLKn. Each of the memory cell blocks BLK1through BLKn may include a plurality of memory cells. The memory cell blocks BLK1through BLKn may be connected to the peripheral circuit30via bitlines BL, wordlines WL, at least one string selection line SSL, and at least one ground selection line GSL. The memory cell blocks BLK1through BLKn may be connected to a row decoder33via the wordlines WL, the string selection line SSL, and the ground selection line GSL. The memory cell blocks BLK1through BLKn may also be connected to a page buffer35via the bitlines BL. The peripheral circuit30may receive an address ADDR, commands CMD, and control signals CTRL from outside the semiconductor device10, and may exchange data DATA with an external device outside the semiconductor device10. The peripheral circuit30may include a control logic37, the row decoder33, and the page buffer35. The peripheral circuit30may further include various sub-circuits such as an input/output circuit, a voltage generating circuit for generating various voltages needed for an operation of the semiconductor device10, and an error correction circuit for correcting error in data DATA read from the memory cell array20. The control logic37may be connected to the row decoder33, the input/output circuit, and the voltage generating circuit. The control logic37may control a general operation of the semiconductor device10. The control logic37may generate various internal control signals for use in the semiconductor device10in response to the control signals CTRL. For example, the control logic37may adjust the levels of voltages to be provided to the wordlines WL and the bitlines BL during a memory operation such as a program operation or an erase operation. The row decoder33may select at least one of the memory cell blocks BLK1through BLKn in response to the address ADDR, and may select at least one of the wordlines WL of the selected memory cell block, the string selection signal SSL, and the ground selection line GSL. The row decoder33may transmit a voltage for performing a memory operation to the selected wordline WL of the selected memory cell block. The page buffer35may be connected to the memory cell array20via the bitlines BL. The page buffer35may operate as a write driver and/or a sense amplifier. During a program operation, the page buffer35may operate as a write driver and may apply a voltage corresponding to data “DATA” to be stored in the memory cell array20to the bitlines BL. During a read operation, the page buffer35may operate as a sense amplifier and may sense data “DATA” stored in the memory cell array20. FIG.2is a circuit diagram of a semiconductor device according to an example embodiment. Referring toFIG.2, a memory cell array (e.g., the memory cell array20ofFIG.1) of the semiconductor device may include common source lines CSL, bitlines BL, and cell strings CSTR. The bitlines BL may be arranged two-dimensionally. For example, the bitlines BL may extend in a first direction X and may be spaced apart from one another in a second direction Y. Multiple cell strings CSTR may be connected in parallel to each of the bitlines BL. The cell strings CSTR may be connected in common to the common source lines CSL. Thus, a plurality of cell strings CSTR may be interposed between the bitlines BL and the common source lines CSL. The common source lines CSL may be arranged two-dimensionally. For example, the common source lines CSL may be spaced apart from one another in the first direction X and may extend in the second direction Y. Voltages that are electrically identical may be applied to the common source lines CSL. In another implementation, different voltages may be applied to the common source lines CSL to control the common source lines CSL separately. In an example embodiment, each of the cell strings CSTR may include ground selection transistors GST that are connected to the common source lines CSL, a plurality of string selection transistors SST that are connected to one of the bitlines BL, and a plurality of memory cell transistors MCT that are interposed between the ground selection transistors GST and the string selection transistors SST. Each of the memory cell transistors MCT may include a data storage element. The ground selection transistors GST, the string selection transistors SST, and the memory cell transistors MCT may be connected in series. The common source lines CSL may be connected in common to the sources of the ground selection transistors GST. Ground selection lines GSL1and GSL2, a plurality of wordlines WL1through WLn, and string selection lines SSL1through SSL3may be interposed between the common source lines CSL and the bitlines BL. The ground selection lines GSL1and GSL2may be used as the gate electrodes of the ground selection transistors GST, the wordlines WL1through WLn may be used as the gate electrodes of the memory cell transistors MCT, and the string selection lines SSL1through SSL3may be used as the gate electrodes of the string selection transistors SST. In an example embodiment, one ground selection line (e.g., the ground selection line GSL1) may correspond to two string selection lines (e.g., the string selection lines SSL1and SSL2). For example, cell strings CSTR connected to the string selection line SSL1or SSL2may be connected in common to the ground selection line GSL1. FIG.3is a layout view of a semiconductor device according to an example embodiment.FIG.4is a layout view illustrating a region R1ofFIG.3.FIG.5is a cross-sectional view taken along line A-A ofFIG.4.FIGS.6and7are enlarged cross-sectional views illustrating a region R2ofFIG.5. Referring toFIG.3, the semiconductor device may include a cell array region CELL and an extension region EXT, which may be arranged adjacent to one another in the second direction Y. The cell array region CELL and the extension region EXT may be cut and divided by a plurality of block isolation regions WLC to form a plurality of memory cell blocks BLK1through BLKn. For example, the block isolation regions WLC may extend in the second direction Y to cut the cell array region CELL and the extension region EXT. A memory cell array (e.g., the memory cell array20ofFIG.1) including a plurality of memory cells may be formed in the cell array region CELL. For example, channel structures CH and bitlines BL may be formed in the cell array region CELL. The extension region EXT may be disposed near the cell array region CELL. In an example embodiment, the cell array region CELL and the extension region EXT may be arranged along the direction in which the block isolation regions WLC extend. For example, the cell array region CELL and the extension region EXT may be arranged along the second direction Y. As illustrated inFIG.5, a plurality of gate electrodes (GSL, WL1through WLn, and SSL) may be stacked in a stepwise fashion in the extension region EXT. The extension region EXT may include contact regions CNR and through regions THR. The contact regions CNR and the through regions THR may be alternately arranged along the direction in which the block isolation regions WLC extend, e.g., the contact regions CNR and the through regions THR may be alternately arranged along the second direction Y. Gate contacts152, which are connected to the gate electrodes (GSL, WL1through WLn, and SSL), may be formed in the contact regions CNR of the extension region EXT. Through structures THV may be formed in the through regions THR of the extension region EXT. The contact regions CNR and the through regions THR will be further described below with reference toFIGS.4and5. Referring toFIGS.3through7, the semiconductor device may include a first substrate100, a mold structure MS, the channel structures CH, the bitlines BL, the block isolation regions WLC, cell gate cutting regions CAC, extension gate cutting regions CNC, the through structures THV, the gate contacts152, and first through vias154. The first substrate100may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In an implementation, the first substrate100may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In an example embodiment, the first substrate100may include impurity regions105. The impurity regions105may extend in the second direction Y and may be provided as common source lines (e.g., the common source lines CSL ofFIG.2). The mold structure MS may be formed on the first substrate100in the cell array region CELL and the extension region EXT. The mold structure MS may be formed in a stepwise fashion on the first substrate100in the extension region EXT. The mold structure MS may include the gate electrodes (GSL, WL1through WLn, and SSL) are alternately stacked on the first substrate100with a plurality of first insulating patterns110. For example, the gate electrodes (GSL, WL1through WLn, and SSL) and the first insulating patterns110may form a stratified structure extending in a first direction X and the second direction Y. The gate electrodes (GSL, WL1through WLn, and SSL) and the first insulating patterns110may be alternately stacked in a third direction Z that is perpendicular to the top surface of the first substrate100. Accordingly, the gate electrodes (GSL, WL1through WLn, and SSL) may be stacked on the first substrate100while being spaced apart from one another. In an example embodiment, the gate electrodes (GSL, WL1through WLn, and SSL) may include at least one ground selection line GSL, a plurality of wordlines WL1through WLn, and at least one string selection line SSL. In an example embodiment, the ground selection line GSL may be a lowermost one of the gate electrodes (GSL, WL1through WLn, and SSL). In an example embodiment, the string selection line SSL may be an uppermost one of the gate electrodes (GSL, WL1through WLn, and SSL). The mold structure MS is illustrated as including one ground selection line GSL and one string selection line SSL, but the mold structure MS may include a plurality of ground selection lines GSL and/or a plurality of string selection lines SSL. The gate electrodes (GSL, WL1through WLn, and SSL) may include a metal, such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si). The gate electrodes (GSL, WL1through WLn, and SSL) may be formed by, for example, a replacement process. The first insulating patterns110may include an insulating material. For example, the first insulating patterns110may include an oxide (e.g., silicon oxide). The channel structures CH may penetrate the mold structure MS. The channel structures CH may extend in a direction that intersects the gate electrodes (GSL, WL1through WLn, and SSL). For example, the channel structures CH may be in a pillar shape extending in the third direction Z. As illustrated inFIG.6, each of the channel structures CH may include a semiconductor pattern130and an information storage film132. The semiconductor pattern130may extend in the third direction Z to penetrate the mold structure MS. The semiconductor pattern130is illustrated as being in a cup shape but the semiconductor pattern130may have various shapes such as a cylindrical shape, a square cylinder shape, or a non-hollow pillar shape. The semiconductor pattern130may include a semiconductor material such as, for example, monocrystalline silicon, polycrystalline silicon, an organic semiconductor material, or a carbon nanostructure. The information storage film132may be interposed between the semiconductor pattern130and the gate electrodes (GSL, WL1through WLn, and SSL). For example, the information storage film132may extend along the sides of the semiconductor pattern130. The information storage film132may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a greater dielectric constant than silicon oxide. The high-k material may include at least one of, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and a combination thereof. In an example embodiment, the information storage film132may be formed as a multilayer film. For example, the information storage film132may include a tunnel insulating film132a,a charge storage film132b,and a blocking insulating film132c,which are sequentially stacked on the semiconductor pattern130. The tunnel insulating film132amay include, for example, silicon oxide or a high-k material (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)) having a greater dielectric constant than silicon oxide). The charge storage film132bmay include, for example, silicon nitride. The blocking insulating film132cmay include, for example, silicon oxide or a high-k material (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)) having a greater dielectric constant than silicon oxide). In an example embodiment, each of the channel structures CH may further include a filler pattern134. The filler pattern134may be formed to fill the inside of the semiconductor pattern130having a cup shape. For example, the semiconductor pattern130may extend along the sides and the bottom surface of the filler pattern134. The filler pattern134may include an insulating material such as, for example, silicon oxide. In an example embodiment, each of the channel structures CH may further include a channel pad136, as illustrated inFIG.5. The channel pad136may be formed to be connected to the top of the semiconductor pattern130. For example, the channel pad136may be formed in a first insulating pattern110on the uppermost one (e.g., the string selection line SSL) of the gate electrodes (GSL, WL1through WLn, and SSL) to be connected to the semiconductor pattern130. The channel pad136may include, for example, polysilicon doped with impurities. In an example embodiment, the channel structures CH may be arranged in a zigzag fashion. For example, as illustrated in the plan view ofFIG.4, the channel structures CH may be arranged in a staggered manner in the first and second directions X and Y. By arranging the channel structures CH in a zigzag fashion, the integration density of the semiconductor device may be increased. The bitlines BL may be formed on the mold structure MS. For example, the bitlines BL may be formed on first, second, and third interlayer insulating films142,144, and146, which are sequentially stacked on the mold structure MS. The bitlines BL may extend in the first direction X to be connected to the channel structures CH. For example, as illustrated inFIG.5, the bitlines BL may be connected to the channel structures CH via bitline contacts170. The bitline contacts170may electrically connect the bitlines BL and the channel structures CH through, for example, the first, second, and third interlayer insulating films142,144, and146. The block isolation regions WLC may be formed in the cell array region CELL and the extension region EXT to cut the gate electrodes (GSL, WL1through WLn, and SSL). The block isolation regions WLC may extend in a direction that intersects the bitlines BL. For example, a plurality of block isolation regions WLC may be arranged along the first direction X in the cell array region CELL and the extension region EXT. The block isolation regions WLC may extend in the second direction Y to cut the mold structure MS. As described above with reference toFIG.3, the block isolation regions WLC may cut and divide the cell array region CELL and the extension region EXT to form the memory cell blocks BLK1through BLKn. For example, the block isolation regions WLC may extend in the second direction Y to completely cut the mold structure MS. The mold structure MS may form each of the memory cell blocks BLK1through BLKn by being cut and divided by each pair of adjacent block isolation regions WLC. The cell gate cutting regions CAC may be formed in the cell array region CELL to cut the gate electrodes (GSL, WL1through WLn, and SSL). The cell gate cutting regions CAC may extend in the direction that intersects the bitlines BL. For example, a plurality of cell gate cutting regions CAC may be arranged along the first direction X in the cell array region CELL, and may extend in the second direction Y to cut the mold structure MS in the cell array region CELL. The cell gate cutting regions CAC may cut and divide the cell array region CELL, and may thus form a plurality of first, second, and third sections I, II, and III in each of the memory cell blocks BLK1through BLKn. For example, as illustrated inFIG.4, two cell gate cutting regions CAC may be formed between each pair of adjacent block isolation regions WLC. Accordingly, three sections (e.g., first, second, and third sections I, II, and III) may be formed between each pair of adjacent block isolation regions WLC. The extension gate cutting regions CNC may be formed in the extension region EXT to cut the gate electrodes (GSL, WL1through WLn, and SSL). The extension gate cutting regions CNC may extend in the direction that intersects the bitlines BL. For example, a plurality of extension gate cutting regions CNC may be arranged along the first direction X in the extension region EXT. The extension gate cutting regions CNC may extend in the second direction Y to cut the mold structure MS in the extension region EXT. In an example embodiment, at least some of the extension gate cutting regions CNC may be arranged to overlap with their respective cell gate cutting regions CAC in the second direction Y. For example, as illustrated inFIG.4, five extension gate cutting regions CNC may be formed between each pair of adjacent block isolation regions WLC, and two of the five extension gate cutting regions CNC may overlap with their respective cell gate cutting regions CAC in the second direction Y. In an example embodiment, the extension gate cutting regions CNC may be formed in the contact regions CNR of the extended region EXT, but not in the through regions THR of the extended region EXT. For example, the extension gate cutting regions CNC may extend in the second direction Y, but not to encroach upon the through regions THR. The block isolation regions WLC, the cell gate cutting regions CAC, and the extension gate cutting regions CNC may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a greater dielectric constant than silicon oxide. In an example embodiment, the block isolation regions WLC, the cell gate cutting regions CAC, and the extension gate cutting regions CNC may be formed on the same level. The expression “formed on the same level”, as used herein, may indicate that the corresponding elements are formed by the same manufacturing process. For example, the block isolation regions WLC, the cell gate cutting regions CAC, and the extension gate cutting regions CNC may include the same insulating material. In an example embodiment, the block isolation regions WLC may include a conductive material. For example, the block isolation regions WLC may include conductive patterns and spacers, which isolate the mold structures MS from the conductive patterns. The conductive patterns of the block isolation regions WLC may be connected to the impurity regions105, and may thus be provided as common source lines (e.g., the common source lines CSL ofFIG.2) of the semiconductor device. In an example embodiment, cutting structures SC may be formed in the mold structure MS in the cell array region CELL to cut the string selection line SSL. The cutting structures SC may be interposed between the block isolation regions WLC to cut the string selection line SSL of the mold structure MS. For example, a plurality of cutting structures SC may be arranged along the first direction X in the cell array region CELL. The cutting structures SC may extend in the second direction Y to cut the string selection line SSL. In an example embodiment, the cutting structures SC may be interposed between the block isolation regions WLC and the cell gate cutting regions CAC. For example, the cutting structures SC may be interposed between the block isolation regions WLC, which define the first, second, and third regions I, II, and III in each of the memory cell blocks BLK1through BLKn, and the cell gate cutting regions CAC. Accordingly, the first, second, and third regions I, II, and III in each of the memory cell blocks BLK1through BLKn may be electrically isolated from one another, and as a result, two string selection line SSL that can be controlled separately may be provided. Although not specifically illustrated, additional cutting structures SC may be arranged to overlap with their respective cell gate cutting regions CAC in the second direction Y. For example, two additional cutting structures SC may be formed between the first and second regions I and II in each of the memory cell blocks BLK1through BLKn and between the second and third regions II and III in each of the memory cell blocks BLK1through BLKn, in the cell array region CELL. Thus, five cutting structures SC may be formed between each pair of adjacent block isolation regions WLC. String selection lines SSL in the first and second regions I and II in each of the memory cell blocks BLK1through BLKn may be electrically isolated from each other and may thus be controlled separately, and string selection lines SSL in the second and third regions II and III in each of the memory cell blocks BLK1through BLKn may be electrically isolated from each other and may thus be controlled separately. Thus, for example, six string selection lines SSL may be formed between each pair of adjacent block isolation regions WLC. In an example embodiment, the number of extension gate cutting regions CNC formed between each pair of block isolation regions WLC may be the same as, or smaller than, the number of cutting structures SC formed between each pair of adjacent block isolation regions WLC. For example, five cutting structures SC and five (or less than five) extension gate cutting regions CNC may be formed between each pair of adjacent block isolation regions WLC. The through structures THV may be formed in the through regions THR of the extension region EXT. Each of the through structures THV may include a plurality of second insulating patterns115that are spaced apart from one another and are stacked on the first substrate100. For example, the second insulating patterns115may form a stratified structure extending in the first and second directions X and Y. The second insulating patterns115may be stacked on the same level as at least some of the gate electrodes (GSL, WL1through WLn, and SSL). The expression “stacked on the same level”, as used herein, may indicate that the corresponding elements are formed at substantially the same height with respect to the top surface of the first substrate100. For example, as illustrated inFIG.5, the second insulating patterns115may be stacked on the same level as a gate electrode We exposed in the through regions THR and may be stacked on the same levels as gate electrodes (GSL, WL1, and Wa through Wd) disposed below the gate electrode We. The first insulating patterns110and the second insulating patterns115may be alternately stacked in the through regions THR. The second insulating patterns115may cut the gate electrodes (GSL, WL1through WLn, and SSL) in the through regions THR. Referring toFIG.4, in an example embodiment, each of the second insulating patterns115may include a first side S1that is straight in a plan view and a second side S2that is curvy in a plan view. For example, as illustrated inFIG.4, the second insulating patterns115may include first sides S1that extend straight in the second direction Y. The second insulating patterns115may also include second sides S2that are curvy, e.g., having concave regions. In an example embodiment, the second sides S2of the second insulating patterns115may form arcs that are centered around ends of the extension gate cutting regions CNC. For example, each of the second sides S2of the second insulating patterns115may correspond to a plurality of extension gate cutting regions CNC and may form a plurality of arcs that are arranged along the first direction X. The second insulating patterns115may include a different insulating material from the first insulating patterns110. For example, in a case where the first insulating patterns110include an oxide (e.g., silicon oxide), the second insulating patterns115may include a nitride (e.g., silicon nitride). In an example embodiment, the length by which the gate electrodes (GSL, WL1through WLn, and SSL) protrude in the through regions THR may be greater than the length by which the gate electrodes (GSL, WL1through WLn, and SSL) protrude in the contact regions CNR. For example, as illustrated inFIG.5, the length by which the gate electrode We exposed in the through regions THR protrudes beyond a gate electrode Wf directly above the gate electrode We may be greater than the length by which a gate electrode Wg exposed in the contact regions CNR protrudes beyond a gate electrode Wh directly above the gate electrode Wg. Referring toFIG.4, in an example embodiment, lower cutting regions GC may cut the ground selection lines GSL. As illustrated inFIG.4, the lower cutting regions GC may be connected to the cell gate cutting regions CAC, the extension gate cutting regions CNC, or the through structures THV to cut the ground selection lines GSL. For example, three ground selection lines GSL that are cut by the cell gate cutting regions CAC, the extension gate cutting regions CNC, the through structures THV, and the lower cutting regions GC may be formed between a pair of adjacent block isolation regions WLC. Accordingly, the first, second, and third regions I, II, and III in each of the memory cell blocks BLK1through BLKn may be electrically isolated from one another, and as a result, three separately controllable ground selection lines GSL may be provided. The gate contacts152may be formed in the extension region EXT. The gate contacts152may be connected to the gate electrodes (GSL, WL1through WLn, and SSL). For example, the gate contacts152may be connected to the gate electrodes (GSL, WL1through WLn, and SSL) through the first, second, and third interlayer insulating films142,144, and146. In an example embodiment, the gate contacts152may be formed in the contact regions CNR of the extension region EXT. For example, as illustrated inFIG.5, gate electrodes Wa through Wh exposed in the contact regions CNR may be arranged in a stepwise fashion. The gate contacts152may be arranged in a stepwise fashion to be connected to ends of the gate electrodes Wa through Wh. First through vias154may be formed in the through regions THR of the extension region EXT. The first through vias154may penetrate the through structures THV. For example, the first through vias154may extend in the third direction Z in the through regions THR to penetrate the first insulating patterns110and the second insulating patterns115. In an example embodiment, the first through vias154may be connected to the gate contacts152. For example, connecting wires156may be formed on the third interlayer insulating film146. The gate contacts152and the first through vias154may be connected to the connecting wires156through the first, second, and third interlayer insulating films142,144, and146. Accordingly, the connecting wires156may connect the gate contacts152and the first through vias154. In an example embodiment, a second substrate200and peripheral circuit elements PT may be formed below the first substrate100. The second substrate200may include a semiconductor substrate such as, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In an implementation, the second substrate200may include an SOI substrate or a GOI substrate. The peripheral circuit elements PT may be formed on the second substrate200. The peripheral circuit elements PT may configure a peripheral circuit (e.g., the peripheral circuit30ofFIG.1) that controls operations of memory cells. For example, the peripheral circuit elements PT may include a row decoder (e.g., the row decoder33ofFIG.1), a page buffer (e.g., the page buffer35ofFIG.1), and a control logic (e.g., the control logic37ofFIG.1). The peripheral circuit elements PT may include, for example, transistors. The peripheral circuit elements PT may include various active elements such as transistors, and/or various passive elements such as capacitors, resistors, or inductors. In an example embodiment, the first through vias154may be connected to the peripheral circuit elements PT. For example, a fourth interlayer insulating film240that covers the peripheral circuit elements PT may be formed on the second substrate200, and peripheral circuit wires PW may be formed in the fourth interlayer insulating film240. The first through vias154may be connected to the peripheral circuit elements PT via the peripheral circuit wires PW. Referring toFIGS.5and7, the semiconductor device may further include a source structure300. The source structure300may be formed on the first substrate100. In an example embodiment, the source structure300may be interposed between the first substrate100and the mold structure MS. The source structure300may include, for example, polysilicon doped with impurities or a metal. In an example embodiment, the channel structures CH may be connected to the first substrate100through the source structure300. For example, as illustrated inFIG.7, a lower part of the channel structures CH may be buried in the first substrate100through the source structure300. In an example embodiment, the source structure300may be formed to be connected to the semiconductor patterns130of the channel structures CH. For example, the source structure300may be connected to the semiconductor patterns130through the information storage films132. In an example embodiment, part of the source structure300near the semiconductor pattern130may project toward the information storage film132. For example, the length by which the source structure300extends in the third direction Z may be greater near the semiconductor pattern130than anywhere else, and this structure may be formed by the characteristics of etching for removing part of the information storage film132to form the source structure300. FIG.8is a layout view of a semiconductor device according to an example embodiment.FIG.9is a perspective view illustrating an extension region ofFIG.8.FIG.10is an enlarged perspective view illustrating a region R3ofFIG.9. Specifically,FIG.8is a layout view of a region R1(ofFIG.3) of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through7may be omitted or simplified. Also, for convenience, extension gate cutting regions CNC are not illustrated inFIGS.9and10. Referring toFIGS.8through10, a plurality of gate electrodes (GSL, WL1through WLn, and SSL) of an extension region EXT may be stacked in a stepwise fashion in first and second directions X and Y. As illustrated inFIG.9, in contact regions CNR of the extension region EXT, the gate electrodes (GSL, WL1through WLn, and SSL) may be stacked in a stepwise fashion in both the first and second directions X and Y. For example, as illustrated inFIG.10, gate electrodes from different layers in the second direction Y (e.g., Wb1and Wc1, Wb2and Wc2, Wb3and Wc3, Wb4and Wc4, Wb5and Wc5, or Wb6and Wc6) may have height differences in the second direction Y. Also, gate electrodes from different layers in the first direction X (e.g., Wb1through Wb6or Wc1through Wc6) may have height differences in the first direction X. In an example embodiment, in through regions THR of the extension region EXT, the gate electrodes (GSL, WL1through WLn, and SSL) may be stacked in a stepwise fashion only in the first direction X. For example, as illustrated inFIG.9, the top surfaces of through structures THV, which are formed in the through regions THR, may have height differences only in the first direction X. In an example embodiment, the number of steps formed in the first direction X between each pair of adjacent block isolation regions WLC may be the same as, or smaller than, the number of string selection lines SSL formed between each pair of adjacent block isolation regions WLC. For example, as illustrated inFIG.8, six steps and six string selection lines SSL may be formed between each pair of adjacent block isolation regions WLC along the first direction X. FIG.11is a layout view of a semiconductor device according to an example embodiment.FIGS.12and13are cross-sectional views taken along line B-B ofFIG.11. Specifically,FIG.11is a layout view of a region R1(ofFIG.3) of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through7may be omitted or simplified. Referring toFIGS.11through13, at least one of a plurality of gate electrodes (GSL, WL1through WLn, and SSL) may overlap with through structures THV in a third direction Z. For example, as illustrated inFIG.11, at least one of the gate electrodes (GSL, WL1through WLn, and SSL) may include protruding parts GP that overlap with the through structures THV in the third direction Z. In an example embodiment, the lowermost one of the gate electrodes (GSL, WL1through WLn, and SSL), for example, ground selection lines GSL, may include protruding parts GP. For example, as illustrated inFIG.12, the ground selection lines GSL may include protruding parts GP that protrude beyond the other gate electrodes (i.e., WL1through WLn and SSL) toward through structures THV. Accordingly, the protruding parts GP of the ground selection lines GSL may overlap with a plurality of second insulating patterns115in the third direction Z. In an example embodiment, second insulating patterns115corresponding to a gate electrode having protruding parts GP may include a material with a different etching rate from second insulating patterns115corresponding to the other gate electrodes such that an etch selectivity exists. For example, the ground selection lines GSL may include protruding parts GP. In this example, second insulating patterns115corresponding to the ground selection lines GSL may have a different nitrogen ratio from second insulating patterns115corresponding to the other gate electrodes (i.e., WL1through WLn and SSL). In an example embodiment, the amount by which the second insulating patterns115corresponding to the ground selection lines GSL are etched may be increased as compared to the amount by which the second insulating patterns115corresponding to the other gate electrodes (i.e., WL1through WLn and SSL) are etched. Accordingly, the ground selection lines GSL may include protruding parts GP that protrude beyond the other gate electrodes (i.e., WL1through WLn and SSL) toward the through structures THV. In an example embodiment, lower cutting regions GC may be formed to cut the ground selection lines GSL. As illustrated inFIGS.11and12, the lower cutting regions GC may be connected to cell gate cutting regions CAC, extension gate cutting regions CNC, or the through structures THV to cut the ground selection lines GSL. In an example embodiment, the protruding parts GP may protrude toward through structures THV where the lower cutting regions GC are not formed. For example, referring toFIG.11, some of the lower cutting regions GC may surround the left sides, right sides, and bottom surfaces of the through structures THV. In this case, the protruding parts GP may protrude only from the top surfaces of the through structures THV toward the through structures THV. During a process of forming the gate electrodes (GSL, WL1through WLn, and SSL) (e.g., during a replacement process), the lower cutting regions GC may prevent the second insulating patterns115corresponding to the ground selection lines GSL from being etched. As a result, the lower cutting regions may be used adjust areas in which the protruding parts GP are to be formed. In an example embodiment, second through vias158that are connected to the protruding parts GP may be formed in the through regions THR of the extension region EXT. The second through vias158may be connected to the protruding parts GP through the through structures THV. For example, the second through vias158may extend in the third direction Z in the through regions THR to penetrate a plurality of first insulating patterns110and a plurality of second insulating patterns115. In an example embodiment, the second through vias158may be connected to the first through vias154. For example, connecting wires156may be formed on a third interlayer insulating film146. The first through vias154and the second through vias158may be connected to the connecting wires156through first and second interlayer insulating films142and144and through the third interlayer insulating film146. Accordingly, the connecting wires156may connect the first through vias154and the second through vias158. In an example embodiment, the ground selection lines GSL may be connected to peripheral circuit elements PT via the first through vias154. Referring toFIGS.11and13, the thickness of a gate electrode including protruding parts GP may be greater than the thickness of other gate electrodes not including protruding parts GP. For example, the ground selection lines GSL may include protruding parts GP. A thickness D11of the ground selection lines GSL may be greater than a thickness D12of other gate electrodes (e.g., WL1) stacked on the ground selection lines GSL. In this example, the amount by which the second insulating patterns115corresponding to the ground selection lines GSL are etched during the process of forming the gate electrodes (GSL, WL1through WLn, and SSL) (e.g., during a replacement process) may be increased. Accordingly, the ground selection lines GSL may include protruding parts GP that protrude beyond the other gate electrodes (i.e., WL1through WLn and SSL) toward the through structures THV. FIG.14is a layout view of a semiconductor device according to an example embodiment. Specifically,FIG.14is a layout view of a region R1(ofFIG.3) of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through13may be omitted or simplified. Referring toFIG.14, the semiconductor device further includes additional cutting regions AC that cut ground selection lines GSL. The additional cutting regions AC may extend from extension gate cutting regions CNC that cut the ground selection lines GSL. For example, the additional cutting regions AC may extend in a second direction Y in the ground selection lines GSL to be connected to the extension gate cutting regions GNC that cut the ground selection lines GSL. Thus, the additional cutting regions AC may cut the ground selection lines GSL together with the extension gate cutting regions CNC. The additional cutting regions AC may be adjacent to protruding parts GP. The amount by which second insulating patterns115corresponding to the ground selection lines GSL where the additional cutting regions AC are formed are etched during a process of forming a plurality of gate electrodes (GSL, WL1through WLn, and SSL) (e.g., during a replacement process) may be increased. Accordingly, the ground selection lines GSL may include protruding parts GP that protrude beyond the other gate electrodes (i.e., WL1through WLn and SSL) toward through structures THV. FIG.15is a layout view of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through7may be omitted or simplified. Referring toFIG.15, the semiconductor device includes first and second extension regions EXT1and EXT2. The first and second extension regions EXT1and EXT2may be disposed on both sides of a cell array region CELL. For example, the first extension region EXT1, the cell array region CELL, and the second extension region EXT2may be sequentially arranged along a second direction Y. The first and second extension regions EXT1and EXT2may be substantially the same as the extension region EXT ofFIGS.1through7, and thus, a detailed description thereof will not be repeated Each of the first and second extension regions EXT1and EXT2may include contact regions CNR and through regions THR. In an example embodiment, the first and second extension regions EXT1and EXT2may be arranged symmetrically with respect to the cell array region CELL. FIG.16is a layout view of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through15may be omitted or simplified. Referring toFIG.16, through structures THV in a first extension region EXT1and through structures THV in a second extension region EXT may be arranged in a zigzag fashion. For example, for a memory cell block BLK1, through structures THV may be formed in the second extension region EXT2, but not in the first extension region EXT1. Also, for example, for a memory cell block BLK2, through structures THV may be formed in the first extension region EXT1, but not in the second extension region EXT2. FIG.17is a layout view of a semiconductor device according to an example embodiment.FIGS.18A through18Care layout views illustrating a region R4ofFIG.17. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through16may be omitted or simplified. Referring toFIG.17, widths of the memory cell blocks BLK1through BLKn of a first extension region EXT1and/or a second extension region EXT2may be greater than widths of corresponding memory cell blocks BLK1through BLKn of a cell array region CELL. Here, the term “width”, as used herein, denotes the width, in a first direction X, of the corresponding element. For example, a width D22of part of the first extension region EXT1corresponding to a memory cell block BLK2may be greater than a width D21of a corresponding part of the cell array region CELL. In a case where the width of the parts of the first extension region EXT1and/or the second extension region EXT2is greater than the width of the corresponding parts of the cell array region CELL, larger contact regions CNR and/or larger through regions THR than the first extension region EXT1and/or the second extension region EXT2may be formed. For example, regions where through structures THV are formed may be larger in the semiconductor device ofFIG.17than in the semiconductor device ofFIG.16. Referring toFIGS.17through18C, cell gate cutting regions CAC, extension gate cutting regions CNC, through structures THV, and lower cutting regions GC may be arranged in various manners between each pair of adjacent block isolation regions WLC. For example, one cell gate cutting region CAC may be formed between each pair of adjacent block isolation regions WLC. Accordingly, two sections (e.g., fourth and fifth sections IV and V) may be formed between each pair of adjacent block isolation regions WLC. In an example embodiment, the cutting structures SC may be interposed between the block isolation regions WLC and the cell gate cutting regions CAC. For example, the cutting structures SC may be interposed between the block isolation regions WLC that define fourth sections IV and fifth sections V, and the cell gate cutting regions CAC. Accordingly, the fourth sections IV may be electrically isolated from their respective fifth sections V, and as a result, two separately controllable string selection lines SSL may be provided. The lower cutting regions GC may be connected to the cell gate cutting regions CAC, the extension gate cutting regions CNC, or the through structures THV and may thus cut ground selection lines GSL. For example, referring toFIG.18A, two ground selection lines GSL that are cut by the cell gate cutting regions CAC, the extension gate cutting regions CNC, the through structures THV, and the lower cutting regions GC may be formed between each pair of adjacent block isolation regions WLC. Accordingly, the fourth sections IV may be electrically isolated from their respective fifth sections V, and as a result, two separately controllable ground selection lines GSL may be provided. In an example embodiment, parts of the lower cutting regions GC may connect each pair of adjacent block isolation regions WLC. For example, parts of the lower cutting regions GC may extend in the first direction X in regions (e.g., at the boundary between the cell array region CELL and the first extension region EXT1) where each pair of adjacent block isolation regions WLC become closer to each other. Referring toFIGS.17and18B, the size of through structures THV may be increased, as compared to the size of the through structures THV ofFIG.18A. For example, the size of regions where extension gate cutting regions CNC are formed may be decreased. In this example, the amount by which second insulating patterns115are etched during a process of forming a plurality of gate electrodes (GSL, WL1through WLn, and SSL) (e.g., during a replacement process) may be decreased. For example, the trough structures THV may extend further in a second direction Y. In an example embodiment, two ground selection lines GSL that are cut by cell gate cutting regions CAC, the through structures THV, and lower cutting regions GC may be formed. Referring toFIGS.17and18C, in a first extension region EXT1, parts of lower cutting regions GC may extend longer in a second direction Y than the corresponding parts of the lower cutting regions GC ofFIG.18A. For example, through structures THV may not be formed between each pair of adjacent block isolation regions WLC. In this example, parts of the lower cutting regions GC may extend long in the second direction Y, and as a result, two ground selection lines GSL may be provided between each pair of adjacent block isolation regions WLC. FIG.19is a layout view of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through18Cmay be omitted or simplified. Referring toFIG.19, each of a plurality of memory cell blocks BLK1through BLKn may not be formed in one of first and second extension regions EXT1and EXT2. For example, the memory cell block BLK1may be formed in a cell array region CELL and the second extension region EXT2, but may not extend to the first extension region EXT1. Also, for example, the memory cell block BLK2may be formed in the cell array region CELL and the first extension region EXT1, but may not extend to the second extension region EXT2. In an example embodiment, unlike in the embodiment ofFIG.17, only one block cutting region WLC may be formed between the memory cell blocks BLK1and BLK3. FIG.20is a layout view of a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through7may be omitted or simplified. Referring toFIG.20, contact regions CNR and through regions THR may be alternately arranged along a first direction X. For example, in a first extension region EXT1, the contact regions CNR and the through regions THR may be alternately arranged along the first direction X. Also, for example, in a second extension region EXT2, the contact regions CNR and the through regions THR may be alternately arranged along the first direction X. FIG.20illustrates an example in which only one through region is formed in each of a plurality of memory cell blocks BLK1through BLKn. Alternatively, a plurality of through regions THR and a plurality of contact regions may be formed in each of the memory cell blocks BLK1through BLKn to be alternately arranged along a second direction Y. A method of fabricating a semiconductor device according to an example embodiment will hereinafter be described with reference toFIGS.1through29. FIGS.21through29illustrate stages in a method of fabricating a semiconductor device according to an example embodiment. For convenience, descriptions of the elements or features that have already been described above with reference toFIGS.1through20may be omitted or simplified. Referring toFIGS.21and22, a mold structure MS is formed on a first substrate100.FIG.22is a cross-sectional view taken along line A-A ofFIG.21. The mold structure MS may be formed on the first substrate100. The mold structure MS may include first insulating films110L and second insulating films115L, which are alternately stacked on the first substrate100. In an example embodiment, cutting structures SC may be formed in the mold structure MS in a cell array region CELL. For example, a plurality of cutting structures SC may be arranged along a first direction X in the cell array region CELL. The cutting structures SC may be arranged in a second direction Y to cut the uppermost one of the second insulating films115L. Referring toFIGS.23and24, the mold structure MS may be patterned into a stepwise fashion in an extension region EXT.FIG.24is a cross-sectional view taken along line A-A ofFIG.23. The first insulating films110L may be patterned into first insulating patterns110, which form a stepwise structure together in the second direction Y. Also, the second insulating films115L may be patterned into second insulating patterns115, which form a stepwise structure together in the second direction Y. The extension region EXT may include contact regions CNR and through regions THR. The contact regions CNR and the through regions THR may be alternately arranged along the second direction Y. In an example embodiment, the length by which the second insulating patterns115protrude in the through regions THR may be greater than the length by which the second insulating patterns115protrude in the contact regions CNR. Referring toFIGS.25and26, channel structures CH, block isolation trenches WLT, cell gate cutting trenches CAT, and extended gate cutting trenches CNT are formed in the mold structure MS.FIG.26is a cross-sectional view taken along line A-A ofFIG.25. The channel structures CH may penetrate the mold structure MS. The channel structures CH may extend in a direction that intersects the first insulating patterns110and the second insulating patterns115. For example, the channel structures CH may be in a pillar shape (e.g., a cylindrical shape) that extends in a third direction Z. The block isolation trenches WLT may be formed in the cell array region CELL and the extension region EXT to cut a plurality of gate electrodes (GSL, WL1through WLn, and SSL). The cell gate trenches CAT may be formed in the cell array region CELL to cut the gate electrodes (GSL, WL1through WLn, and SSL). The extended gate cutting trenches CNT may be formed in the extension region EXT to cut the gate electrodes (GSL, WL1through WLn, and SSL). Referring toFIGS.28and29, the second insulating patterns115may be at least partially removed using the block isolation trenches WLT, the cell gate cutting trenches CAT, and the extended gate cutting trenches CNT.FIG.29is a cross-sectional view taken along line A-A ofFIG.28. For example, a pull-back process may be performed to at least partially remove the second insulating patterns115using the block isolation trenches WLT, the cell gate cutting trenches CAT, and the extended gate cutting trenches CNT. As a result, parts of the second insulating patterns115may remain so that through structures THV may be formed in the through regions THR. The through structures THV may include a plurality of first insulating patterns110and a plurality of second insulating patterns115, which are alternately stacked. Thereafter, block isolation regions WLC, cell gate cutting regions CAC, and extension gate cutting regions CNC may be formed to fill the block isolation trenches WLT, the cell gate cutting trenches CAT, and the extended gate cutting trenches CNCT, respectively. Thereafter, referring toFIGS.4and5, gate contacts152, first through vias154, bitlines BL, and connecting wires156may be formed. In this manner, a method of fabricating a semiconductor device with an improved integration density and reliability may be provided. As described above, embodiments relate to a semiconductor device including a stepwise extension region and a method of fabricating the semiconductor device. Embodiments may provide a semiconductor device with an improved integration density and reliability. Embodiments may provide a method of fabricating a semiconductor device with an improved integration density and reliability. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 54,502 |
11862567 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Detailed embodiments of the claimed structures and methods are described herein; however, it is to be understood that the described embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details described herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present description. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the described methods and structures, as it is oriented in the drawing figures. The terms “present on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. With increasing scaling for next generation complementary metal oxide semiconductor (CMOS) devices, the middle of the line (MOL) resistance can affect device performance. It has been determined that in order to overcome the MOL high resistance issues, that in some embodiments, the high-resistance interface between the contact to the source and drain regions (CA) contact, and the trench silicon (TS) contact can play a critical role. In some embodiments, the methods and structures that are described herein provide a novel method to form a lower-resistance contact to the source and drain regions by forming contact region on the source and drain regions of the semiconductor device comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the source/drain region of the semiconductor device. Some embodiments of the methods and structures provided herein, are now described in more detail with reference toFIGS.1-10. FIG.1depicts one embodiment of a via opening15through a dielectric layer10to the contact surface5of a semiconductor device. As used herein, the term “semiconductor device” refers to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor determines the conductivity type of the semiconductor. The methods and structures are suitable to many types of semiconductor devices, such as planar semiconductor devices, e.g., field effect transistors (FETs); fin type field effect transistors (FinFETs); bipolar junction transistors and other related types of semiconductor devices. In some embodiments, the contact surfaces5that the contacts that are described herein are in electrical communication with can be the source/drain regions of a semiconductor device, or a gate region of a semiconductor device. The contact surfaces5of the semiconductor devices are typically composed of a semiconductor material. For example, the contact surfaces5may be composed of a type IV semiconductor material. By “type IV semiconductor” it is meant that the semiconductor material includes at least one element from Group IVA (i.e., Group 14) of the Periodic Table of Elements. Examples of type IV semiconductor materials that are suitable for the fin structure include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C), silicon germanium doped with carbon (SiGe:C) and a combination thereof. In some examples, the contact surfaces5may be source/drain regions composed of silicon (Si) or silicon germanium (SiGe). In the instances in which the contact surfaces5are the source/drain regions of a semiconductor device, the base semiconductor material of the contact surfaces5can be doped with an n-type or p-type conductivity dopant, i.e., depending on the conductivity type of the semiconductor device, e.g., if the semiconductor device is an n-type or p-type field effect transistor (FET). The dielectric layer10that is present atop the contact surface5that the via opening15is formed through may be blanket deposited atop the entirety of the semiconductor device that includes the contact surface5. The dielectric layer10may be an oxide, nitride or oyxnitride material. In some instances, the dielectric layer10may be referred to as interlevel dielectric or an intralevel dielectric. In some embodiments, the dielectric layer10is be selected from the group consisting of silicon containing materials, such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). The dielectric layer10may be deposited using chemical vapor deposition (CVD) or spin on deposition. Following deposition, the upper surface of the dielectric layer10can be planarized, using a planarization process, such as chemical mechanical planarization (CMP). Still referring toFIG.1, via openings15can be formed through the dielectric layer10to expose the contact surfaces5of the semiconductor devices, e.g., contact surfaces of the source and drain region portions of the semiconductor devices. The via openings15may be formed using photolithography and etch processes. Specifically, and in one example, a etch mask pattern is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections of the dielectric layer10covered by the photoresist are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions to form the via openings15. The etch process may be reactive ion etch (RIE), which can be selective to the contact surface5. FIG.2depicts forming a nickel (Ni) and platinum (Pt) containing alloy20with a semiconductor element at a base of the via opening15. In the embodiments, in which the contact surface5is composed of silicon (Si), the semiconductor element that alloys with the nickel (Ni) and platinum (Pt) may be silicon (Si), in which the alloy is a silicide, such as nickel platinum silicide (NiPtSi). In the embodiments, in which the semiconductor element at the base of the via opening15include germanium (Ge), such as silicon germanium (SiGe), the alloy formed with the nickel (Ni) and platinum (Pt) can be a metal germanosilicide, e.g., the alloy may include nickel (Ni), platinum (Pt), germanium (Ge), and in some instances silicon (Si). In some embodiments, the process for forming the nickel (Ni) and platinum (Pt) containing alloy20with a semiconductor element at a base of the via opening15may include depositing a metal layer including nickel (Ni) and platinum (Pt) within the via opening15. The metal layer of nickel (Ni) and platinum (Pt) can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) methods. In one example, in which the metal layer of nickel (Ni) and platinum (Pt) is deposited by physical vapor deposition (PVD) method, the deposition process can include sputtering. Examples of sputtering apparatus that can be suitable for depositing the metal layer including nickel (Ni) and platinum (Pt) within the via opening15include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In another example, the metal layer including nickel (Ni) and platinum (Pt) within the via opening15using plating processes, such as electroplating or electroless plating. In the embodiments, in which the metal layer including nickel (Ni) and platinum (Pt) is deposited within the via opening15using chemical vapor deposition (CVD), the chemical vapor deposition (CVD) process may be selected from the group consisting of Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. It is noted that the aforementioned examples of deposition processes are provided for illustrative purposes only, and are not intended to limit the present description, as other deposition processes may be equally applicable, so long as enough material may be deposited within the via opening for the deposited metals to interact with the semiconductor material of the contact surface during the subsequently described annealing steps. Following deposition of the metal layer including nickel (Ni) and platinum (Pt) within the via opening15, an anneal process can be applied to interdiffuse the metal elements from the metal layer including nickel (Ni) and platinum (Pt) deposited within the via opening15with the semiconductor elements of the contact surface5of the semiconductor device at the base of the via opening15to form the metal semiconductor alloy. For example, the annealing process provides a nickel (Ni) and platinum (Pt) containing alloy20with a semiconductor element, e.g., silicide (nickel platinum silicide (NiPtSi) and/or metal germinicide, at a base of the via opening15. In some embodiments, the annealing process can include furnace annealing, rapid thermal annealing (RTA) and/or pulsed laser annealing. The temperature and time of the anneal process is selected so the deposited metal, e.g., metal layer including nickel (Ni) and platinum (Pt), reacts with the semiconductor material of the contact surface, e.g., type IV semiconductor (e.g., silicon (Si), germanium (Ge), and/or silicon germanium (SiGe)) forming a metal semiconductor, e.g., silicide, such as nickel platinum silicide (NiPtSi) or nickel platinum germanosilicide. For example, the annealing temperature may range from 300° C. to 750° C., and the time period for the anneal may range from the millisecond range, e.g., 1 millisecond, to on the order of minute, such as 15 minutes, particularly depending upon the anneal process, e.g. laser annealing vs. furnace annealing. Following formation of the metal semiconductor alloy, the unreacted metal can be removed by a selective etch. The aforementioned process conditions can be modified to provide a metal semiconductor alloy region having a thickness of less than 15 nm, e.g., 10 nm or less. In one example, the thickness of the nickel (Ni) and platinum (Pt) containing alloy20with a semiconductor element, e.g., silicide (nickel platinum silicide (NiPtSi) and/or metal germinicide, at a base of the via opening15ranges from 1 nm to 10 nm. In another example, the thickness of the nickel (Ni) and platinum (Pt) containing alloy20with a semiconductor element, e.g., silicide (nickel platinum silicide (NiPtSi) and/or metal germinicide, at a base of the via opening15ranges from 2 nm to 5 nm. FIG.3depicts one embodiment of depositing a titanium (Ti) layer25having an angstrom scale thickness that within the via in contact with the nickel platinum semiconductor alloy20, wherein an aluminum containing fill30is deposited atop the titanium (Ti) layer25. The titanium (Ti) layer25can be 95 wt. % titanium (Ti) or greater. In some embodiments, the titanium (Ti) layer25can be greater than 99 wt. % titanium (Ti). In yet other embodiments, the titanium (Ti) layer25can be 100 wt. % titanium (Ti). The titanium (Ti) layer25is a conformally deposited layer, in which the titanium (Ti) layer25is deposited on the sidewalls and base of the via opening15. The term “conformal” denotes a layer having a thickness that does not deviate from greater than or less than 30% of an average value for the thickness of the layer. The titanium (Ti) layer25is deposited to an angstrom scale thickness. In some embodiments, the term “angstrom scale” means 150 Å or less. For example, the titanium (Ti) layer25can have a thickness of 100 Å or less. In some examples, the titanium (Ti) layer25may have a thickness of 95 Å, 90 Å, 85 Å, 80 Å, 70 Å, 60 Å, 50 Å, 40 Å, 30 Å, 20 Å, 15 Å, 10 Å, 5 Å or 1 Å, or may be equal to any range of thickness that includes one of the aforementioned values as an upper limit to the range, and one of the aforementioned values as a lower limit to the range. The titanium (Ti) layer25can be deposited using a method that can provide the aforementioned purity of titanium and the aforementioned thicknesses. In one example, the titanium (Ti) layer25is deposited using thermal electron beam deposition, which may also be referred to as electron beam physical vapor deposition (EBPVD). In some examples, electron beam physical vapor deposition, or EBPVD, is a form of physical vapor deposition in which a target anode, i.e., a titanium (Ti) anode, is bombarded with an electron beam given off by a charged tungsten filament under high vacuum. In accordance with the present description, the electron beam of the EBPVD device causes atoms from a titanium target to transform into the gaseous phase. These atoms then precipitate into solid form, coating everything in the vacuum chamber (within line of sight) with a thin layer of the anode material, i.e., titanium (Ti). In the present example, the structure depicted inFIG.3is placed in the deposition chamber of the EBPVD process, hence forming the titanium (Ti) layer25on the exposed sidewalls of the via opening15and on the nickel platinum semiconductor alloy20at the base of the via opening15. In some embodiments, the titanium (Ti) layer25is formed using an atomic layer deposition (ALD) process. Still referring toFIG.3, in some embodiments, following the formation of the titanium (Ti) layer25, at least a portion of the via opening15is filled with an aluminum (Al) fill30. The aluminum (Al) fill30can be 95 wt. % aluminum (Al) or greater. In some embodiments, the aluminum (Al) fill30can be greater than 99 wt. % aluminum (Al) or greater. In yet other embodiments, the aluminum (Al) fill30can be 100 wt. % aluminum (Al). The aluminum (Al) fill30can be deposited using any method suitable for filling the via opening15. For example, the aluminum (Al) fill30can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) methods. In one example, in which the aluminum (Al) fill30is deposited within the via opening by physical vapor deposition (PVD) method, the deposition process may include sputtering, such as sputtering via DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In another example, the aluminum (Al) fill30is deposited within the via opening15using plating processes, such as electroplating or electroless plating. In the embodiments, in which the aluminum (Al) fill30is deposited within the via opening15using chemical vapor deposition (CVD), the chemical vapor deposition (CVD) process can be selected from the group consisting of Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. It is noted that the aforementioned examples of deposition processes are provided for illustrative purposes only, and are not intended to limit the described methods and structures. In some embodiments, following deposition of the aluminum (Al) fill30, the structure can be planarized, e.g., the structure can be planarized using a chemical mechanical planarization (CMP) process. FIG.4depicts one embodiment of applying an anneal to the material stack depicted inFIG.3to provide a contact alloy35acomprising nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device. For example, the contact alloy35amay be Ni(Pt)—Ti—Al alloy with Si or SiGe. The anneal for forming the contact alloy35acan be a forming gas anneal (FGA) to getter oxygen (O) and form the intermetallic alloy that provides the contact alloy35a. A forming gas anneal (FGA) is a thermal process including an atmosphere that is a mixture of hydrogen and nitrogen. It is sometimes called a “dissociated ammonia atmosphere”. In one embodiment, the forming gas anneal atmosphere includes a 5% H2in N2. By gettering oxygen, the forming gas anneal (FGA) may reduce the formation of oxides on the contact alloy35acomposed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device. The forming gas anneal (FGA) may be conducted in a furnace. In some embodiments, the forming gas anneal (FGA) can include an elevated temperature ranging from 250° C. to 550° C. In some other embodiments, the forming gas anneal (FGA) can include an elevated temperature ranging from 300° C. to 500° C. In yet other embodiments, the forming gas anneal (FGA) ca include an elevated temperature ranging from 300° C. to 450° C., e.g., 350° C. to 450° C. The time period of the anneal may range from 1 minutes to 30 minutes. In one embodiment, the time period of the anneal may range from 10 minutes to 20 minutes. In one example, the forming gas anneal may include a time period of 15 minutes, at a temperature ranging from 350° C. to 450° C. Applying the anneal described above to the structure depicted inFIG.3typically causes the titanium (Ti) from the titanium (Ti) layer25, and the aluminum (Al) from the aluminum (Al) fill30, to diffuse and intermix with the nickel (Ni) and platinum (Pt) containing alloy20to convert the nickel (Ni) and platinum (Pt) containing alloy20into the contact alloy35acomprising nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device. In some embodiments, in which the contact surface5is composed of silicon (Si), the contact alloy35ais composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti), and silicon (Si). In some embodiments, the contact alloy35acan be of the phase (AlxSi1-x)7Ni3. In some embodiments, the contact alloy35ais composed of nickel (Ni) ranging from 20 at. % to 30 at. %, platinum (Pt) ranging from 0 at. % to 10 at. %, aluminum (Al) ranging from 40 at. % to 60 at. %, and silicon (Si) ranging from 5 at. % to 20 at. %. In some embodiments, because this phase does not contain titanium (Ti), during the anneal and phase formation, the titanium (Ti) may segregate to the interfaces above or below alloy35a, as well as grain boundaries within layer35a. As a result chemical composition analysis of this layer may reveal the presence of Ti. In some embodiments, Ni is deposited with Pt (typically up to 10%). In some embodiments, in which the contact surface5is composed of silicon germanium (SiGe), the contact alloy35ais composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti), silicon (Si) and germanium (Ge). In some embodiments, the contact alloy35ais composed of nickel (Ni) ranging from 20 at. % to 30 at. %, platinum (Pt) ranging from 0 at. % to 10 at. %, aluminum (Al) ranging from 40 at. % to 60 at. %, silicon (Si) ranging from 5 at. % to 20 at. % and germanium (Ge) ranging from 0 at. % to 15 at. %. The contact alloy35acan have a thickness of 30 nm or less. In some examples, the contact alloy35amay have a thickness ranging from 5 nm to 15 nm. In some embodiments, the above described intermetallic contact alloy35acomposed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device can provide a contact, e.g., source/drain contact, having a very low specific contact resistivity, which can be below 1×10−9ohm/cm2. FIGS.1,2,5and6describe another embodiment of forming a contact in accordance with the present description. The contact structure depicted inFIGS.1,2,5and6is similar to the contact structure that is formed using the method described above with reference toFIGS.1-4. In the embodiment that is described with reference toFIGS.1,2,5and6the contract further includes a metal nitride liner40and a metal fill45(also referred to as metal containing contact45). Referring toFIG.5, in accordance with one embodiment of the present description beginning with the structure depicted inFIG.2, a titanium (Ti) layer25is first deposited in the via opening15including a portion at the base of the via opening15in contact with the nickel platinum semiconductor alloy20. The titanium (Ti) layer25that is depicted inFIG.5is similar to the titanium (Ti) layer25depicted inFIG.3. Therefore, the description of the titanium (Ti) layer25provided above with reference toFIG.3is suitable for describing at least one embodiment of the titanium (Ti) layer depicted inFIG.5. In a following step, the aluminum (Al) fill30is deposited in the via opening15. The aluminum (Al) fill30depicted inFIG.5is similar to the aluminum (Al) fill30that is depicted inFIG.3. Therefore, at least one embodiment of the aluminum (Al) fill30depicted inFIG.5has been described above with reference toFIG.3. Different than the embodiment of the aluminum (Al) fill depicted inFIG.3that fills the entirety of the via opening, the aluminum (Al) fill30that is depicted inFIG.5only fills a lower portion of the via opening15. The aluminum (Al) fill30that is depicted inFIG.5can be deposited to the correct height of the via opening15, or the aluminum (Al) fill30can be deposited and then recessed to the correct height within the via opening15using a etch process, such as reactive ion etch (RIE). Referring toFIG.5, in one embodiment, a metal nitride layer40can be deposited on the exposed portions of the titanium (Ti) layer25that is present on the sidewalls of the via opening15, and is deposited on the recessed portion of the aluminum (Al) fill30that is present in the lower portion of the via15. In some embodiments, the metal nitride layer40is composed of titanium nitride (TiN). In other embodiments, the metal nitride layer40is composed of tantalum nitride (TaN), tungsten nitride (WN), aluminum nitride and combinations thereof. The metal nitride layer40is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods. In another example, the metal nitride layer40may be formed using atomic layer deposition (ALD). Examples of CVD suitable for forming the metal nitride layer40include plasma enhanced CVD. Examples of PVD suitable for forming the metal nitride layer40include plating or sputtering. The thickness of the metal nitride layer40can range from 1 nm to 10 nm. In some examples, the thickness of the metal nitride layer40may range from 1 nm to 5 nm. Following formation of the metal nitride layer40, the via openings15may be filled with a metal containing contact45of the interconnect being formed in the via openings15. The metal containing contact45is typically composed of an electrically conductive material. For example, the metal containing contact45can be composed of tungsten (W). In other embodiments, the metal containing contact45is composed of a metal that is selected from cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) and combinations thereof. The electrically conductive material for the metal containing contact45may be deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Examples of CVD suitable for forming the metal containing contact45include metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), and high density plasma (HDPCVD). Examples of PVD suitable for forming the metal containing contact45of the interconnect including plating, electroplating, electroless plating, sputtering and combinations thereof. The upper surface of the metal containing contact45can be planarized to be coplanar with the upper surface of the dielectric layer10. FIG.6depicts one embodiment of applying an anneal to the material stack depicted inFIG.5to provide a contact alloy35bcomprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface5of the semiconductor device. For example, the contact alloy35bcan be Ni(Pt)—Ti—Al alloy with Si or SiGe. The anneal for forming the contact alloy35bcan be a forming gas anneal (FGA) to getter oxygen (O) and form the intermetallic alloy that provides the contact alloy35b. In some embodiments, the forming gas anneal (FGA) may include an elevated temperature ranging from 250° C. to 550° C. In some other embodiments, the forming gas anneal (FGA) includes an elevated temperature ranging from 300° C. to 500° C. In yet other embodiments, the forming gas anneal (FGA) includes an elevated temperature ranging from 350° C. to 450° C. The time period of the anneal may range from 5 minutes to 30 minutes. In one embodiment, the time period of the anneal ranges from 10 minutes to 20 minutes. In one example, the forming gas anneal can include a time period of 15 minutes, at a temperature ranging from 350° C. to 450° C. Applying the anneal described above to the structure depicted inFIG.5typically causes the titanium (Ti) from the titanium (Ti) layer25, and the aluminum (Al) from the aluminum (Al) fill30, to diffuse and intermix with the nickel (Ni) and platinum (Pt) containing alloy20to convert the nickel (Ni) and platinum (Pt) containing alloy20into the contact alloy35bcomprising nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device. In some embodiments, in which the contact surface5is composed of silicon (Si), the contact alloy35bmay be composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti), and silicon (Si). In some embodiments, the contact alloy35bcan be of the phase (AlxSi1-x)7Ni3. In some embodiments, the contact alloy35bmay be composed of nickel (Ni) ranging from 20 at. % to 30 at. %, platinum (Pt) ranging from 0 at. % to 10 at. %, aluminum (Al) ranging from 40 at. % to 60 at. %, and silicon (Si) ranging from 5 at. % to 20 at. %. In some embodiments, because this phase does not contain titanium (Ti), during the anneal and phase formation, the titanium (Ti) may segregate to the interfaces above or below alloy35b, as well as grain boundaries within layer35b. As a result chemical composition analysis of this layer may reveal the presence of Ti. In some embodiments, Ni may be deposited with Pt (typically up to 10%). In some embodiments, in which the contact surface5is composed of silicon germanium (SiGe), the contact alloy35bmay be composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti), silicon (Si) and germanium (Ge). In some embodiments, in which the contact surface5is composed of silicon germanium (SiGe), the contact alloy35bmay be composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti), silicon (Si) and germanium (Ge). In some embodiments, the contact alloy35bmay be composed of nickel (Ni) ranging from 20 at. % to 30 at. %, platinum (Pt) ranging from 0 at. % to 10 at. %, aluminum (Al) ranging from 40 at. % to 60 at. %, silicon (Si) ranging from 5 at. % to 20 at. % and germanium (Ge) ranging from 0 at. % to 15 at. %. In some embodiments, the above described intermetallic contact alloy35bthat is depicted inFIG.6is composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device can provide a contact, e.g., source/drain contact, having a very low specific contact resistivity, which can be below 1×10−9ohm/cm2. The contact structures, e.g., interconnect structures, that are depicted inFIGS.1-6may be employed in any electrical device. For example, the interconnect structures that are described herein may be present within electrical devices that employ semiconductors that are present within integrated circuit chips. The integrated circuit chips including the interconnects described herein may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, including computer products or devices having a display, a keyboard or other input device, and a central processor. FIG.7depicts one embodiment of a field effect transistor (FET)100aincluding a contact200ato the source/drain regions70a,70bof the semiconductor device including a nickel, platinum, aluminum and titanium including intermetallic contact region35athat is alloyed with the source/drain region contact semiconductor surface5(also referred to as contact alloy35acomprising nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device). A “field effect transistor (FET)” is a semiconductor device in which the output current, i.e., source-drain current, is controlled by the voltage applied to the gate. A FET has three terminals, i.e., gate structure50, source region70aand drain region70b. As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain. As used herein, the term “channel” is the region underlying the gate structure50and between the source and drain region70a,70bof a semiconductor device that becomes conductive when the semiconductor device is turned on. As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel. The gate structure50is formed on the channel portion of the substrate1that the FET100ais formed on. The gate structure50may include a gate dielectric51, and a gate conductor52. The gate structure50may be formed using gate first or gate last, i.e., replacement gate processing. In one embodiment, the gate dielectric51may be composed of silicon oxide, or a high-k dielectric material, such as hafnium oxide (HfO2). The gate conductor52may be composed of a conductive material, such as a doped semiconductor, e.g., n-type doped polysilicon, or a metal, such as tungsten (W) or an n-type or p-type work function metal, e.g., titanium nitride. Gate sidewall spacers53may be formed on the sidewalls of the gate structure50. Following formation of the gate sidewall spacers50, the source and drain regions70a,70bmay be formed in the substrate1. This can include ion implantation of n-type or p-type dopants into the substrate1and/or epitaxial growth of n-type or p-type semiconductor material on the source and drain region portions of the substrate1. Following formation of the source and drain regions70a,70b, the contacts200ato the source and drain regions70a,70bmay be formed. The contacts200aare formed in a via opening15through a dielectric layer10, and include a nickel, platinum, aluminum and titanium including intermetallic contact region35athat is alloyed with the source/drain region contact semiconductor surface5(also referred to as contact alloy35acomprising nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor element from the contact surface5of the semiconductor device). The contacts200adepicted inFIG.7may be formed using methods described above with reference toFIGS.1-4. Therefore, the above description of the dielectric layer10, via opening15and the contact alloy35athat is described with reference toFIGS.1-4is suitable for the dielectric layer10, via opening15and the intermetallic contact region35athat is depicted inFIG.7. It is noted that the titanium (Ti) layer25, and the aluminum (Al) fill that are depicted inFIG.7have been described above in the description of the structures depicted inFIGS.1-4having the same reference numbers. FIG.8depicts another embodiment of a field effect transistor (FET)100bthat is similar to the field effect transistor (FET)100adepicted inFIG.7. The FET100bdepicted inFIG.8is different from the FET depicted inFIG.7, because the FET100adepicted inFIG.7has contacts200aformed in accordance with the methods described with reference toFIGS.1-4, and the contact200bto the FET100bdepicted inFIG.8has been formed in accordance with the methods described with reference toFIGS.1-2and5-6. Therefore, the features of the FET1100bdepicted inFIG.8, such as the gate structure50, source region70a, and drain region70bhave been described inFIG.7by the description of the structures having the same reference numbers. The description of the elements of the contact200b, such as the metal containing contact45, the metal nitride layer40, the aluminum fill30, the titanium layer25, and the contact alloy35bcan be provided by the description of the structures having the same reference numbers that are depicted inFIGS.1-2and5-6. The structures depicted inFIGS.7and8are planar semiconductor devices. The present description is not limited to only these types of semiconductor devices. For example, the contacts200a,200bthat are depicted inFIGS.7and8can be applied to the contact surface5of the source and drain regions70a,70bof Fin type Field Effect Transistors (FinFETs)100c,100d, as depicted inFIGS.9and10. A FinFET includes a fin structure2, which may be present on a supporting substrate3. As used herein, a “fin structure” refers to a semiconductor material, which is employed as the body of a semiconductor device, in which the gate structure50is positioned around the fin structure2such that charge flows down the channel on the two sidewalls of the fin structure2and optionally along the top surface of the fin structure2. The portions of the fin structure2adjacent on the opposing sides of the channel portion are the source and drain region portions of the fin structure2. Source and drain regions70a,70bmay be formed by ion implantation or by employing in situ epitaxial doped semiconductor material that is formed on the source and drain region portions of the fin structure2. The gate structure50is similar to the gate structures50described inFIGS.7and8and includes at least one gate dielectric and a gate conductor52. A gate sidewall spacer53may also be present on the sidewalls of the gate structure50. FIG.9depicts one embodiment of a fin type field effect transistor (FinFET)100cincluding a contact200awith a nickel, platinum, aluminum and titanium including intermetallic contact region35athat is alloyed with the source/drain region contact semiconductor surface of the source and drain regions70a,70bof the FinFET100c. The contacts200adepicted inFIG.9may be formed using methods described above with reference toFIGS.1-4. Therefore, the above description of the dielectric layer10, via opening15and the contact alloy35athat is described with reference toFIGS.1-4is suitable for the dielectric layer10, via opening15and the intermetallic contact region35athat is depicted inFIG.9. It is noted that the titanium (Ti) layer25, and the aluminum (Al) fill that are depicted inFIG.9have been described above in the description of the structures depicted inFIGS.1-4having the same reference numbers. FIG.10depicts one embodiment of a fin field effect transistor (FinFET)100dincluding a nickel, platinum, aluminum and titanium including intermetallic contact region35bthat is alloyed with the source/drain region contact semiconductor surface, wherein the contact further includes a metal nitride liner40and a metal containing fill45(also referred to as metal containing contact45). The fin type field effect transistor (FinFET)100ddepicted inFIG.10includes a contact200bformed in accordance with method described with reference toFIGS.1-2and5-6. The description of the elements of the contact200b, such as the metal containing contact45, the metal nitride layer40, the aluminum fill30, the titanium layer25, and the contact alloy35bcan be provided by the description of the structures having the same reference numbers that are depicted inFIGS.1-2and5-6. Having described preferred embodiments of a structure and method for forming LOW RESISTANCE CONTACTS INCLUDING INTERMETALLIC ALLOY OF NICKEL, PLATINUM, TITANIUM, ALUMINUM AND TYPE IV SEMICONDUCTOR ELEMENTS, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments described which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims. | 37,793 |
11862568 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Depicted inFIG.1is an exploded block diagram of a portion of an example integrated circuit (IC) during fabrication. The example integrated circuit includes one or more multi-layer semiconductor device structure(s)10and a plurality of metal layers12,14,16sequentially formed above the multi-layer semiconductor device structure10. In this example, only three metal layers (metal 1/2/3) are shown. But, the example integrated circuit may include additional upper metal layers such as metal 4/5/6/7/8/9/10/11/12/13/AP or others. The multi-layer semiconductor device structure10comprises one or more circuits and the one or more circuits may be derived from standard cell designs. Standard cell designs may include a group of transistor and interconnect structures that provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, or inverters) or a storage function (e.g., flip flop or latch). The multiple layers in the multi-layer device structure includes base layers, which correspond to the different structures of the transistor devices. The metal layers12,14,16are interconnect wiring layers, which join together the terminals of the transistor formations. The interconnect wiring layers are numbered and have specific via layers representing specific connections between each sequential layer. In the example shown, the interconnect wiring layers include a metal-1 layer12formed above the multi-layer semiconductor device structure10, a metal-2 layer14formed above the metal-1 layer, and a metal-3 layer16formed above the metal-2 layer. The metal layers include conduction paths that are used to interconnect circuits, transistors, and standard cell designs in the multi-layer semiconductor device structure. The via layers include a via1) (V0) layer (not shown) for joining a terminal of the transistor formation with a metal-1 conduction path, a via1 (V1) layer (not shown) for joining a metal-1 conduction path with a metal-2 conduction path, and a via2 (V2) layer (not shown) for joining a metal-2 conduction path with a metal-3 conduction path. An example multi-layer semiconductor device structure may include one or more diffusion (OD) layers which may be designated as OD1, OD2, etc. A layer of metal commonly referred to as metal-0 (“metal zero” or M0) may be formed above the OD layer, often in the form of metal-0 oxide diffusions (M0OD). There may be multiple metal oxide diffusion layers over multiple OD layers (M0OD1, M0OD2, etc.) and/or multiple metal oxide diffusion layers (M0OD1, M0OD2) over a single OD layer. In some embodiments, an M0OD1 layer may be used as an OD contact layer in the source-drain regions of a transistor. Depicted inFIG.2is a top view illustrating an example configuration of the upper layers of an example semiconductor device structure. The upper layers of the example semiconductor structure may include a polysilicon (PO) layer200, an OD layer202, an M0OD layer204, and an M0OD2 layer206. Depicted inFIG.3is a schematic diagram of an example circuit that may be fabricated in the semiconductor device structure. The example circuit includes three input ports, input port A, input port B and input port C. The example circuit further includes a first inverter20with its input connected to input port B and a second inverter22with its input connected to input port C. The example circuit includes a two-input NAND gate24with a first input connected to input port A and a second input connected to the output (Net B) of the first inverter20. The example circuit further includes a three input NOR gate26with a first input connected to the output (Net A) of NAND gate24, a second input connected to Net B, and a third input connected to the output (Net C) of inverter22. The output of the NAND gate26is connected to the output terminal (Out). Each of first inverter20, second inverter22, NOR gate24, and NAND gate26may be implemented using standard cell designs. Interconnect wiring layers and vias may be used to interconnect the transistors within a cell that make up the standard cell logic device as well as interconnecting transistors in different cells to provide inter-cell connections to complete the depicted circuit. The connections made within a cell are referred to herein as intra cell connections and the connections made between transistors in different cells are referred to herein as inter cell connections. Also, interconnect wiring layers and vias may be used to provide connection points for the input ports A, B, C and the output port (OUT). FIG.4is a flow chart depicting an example method of fabricating a semiconductor device structure such as one embodying the circuit depicted inFIG.3. The example method comprises defining the semiconductor device structure using standard cells (operation100) and defining the interconnections (operation102). The method further includes fabricating the semiconductor structure so defined (operation104). The standard cell designs used in defining the semiconductor structure may specify certain interconnections using a first interconnect layer (e.g., a metal-1 layer). The standard cell designs may specify certain intra cell connections, blockages, input port(s), and output ports using the metal-1 layer (operation106). Defining interconnections may involve defining interconnection paths on the metal-1 layer (operation108), defining interconnection paths on a metal-2 layer above the metal-1 layer (operation110), defining interconnection paths on a metal-3 layer above the metal-2 layer (operation112), and defining interconnection paths on any upper metal-3/4/5/6/7/8/9/10/11/12/13/AP layers. Each metal layer may include a first and second set of interconnection paths with specific rules on which type of interconnection path, e.g., intra cell or inter cell, can be made with the respective set of interconnection paths. For example, a first set of interconnection paths could be assigned to making inter cell connections and a second set of interconnection paths could be assigned to making intra cell connections. In some embodiments, standard cells can use up to 6 horizontal direction metal-1 conduction paths. This can have a limiting effect on the routing because metal-1 is not bendable. To perform routing between standard cells, routing may be performed using upper level metal layers. Using upper level metal layers for routing, however, may result in a decreased number of standard cells that may be placed in an area on an integrated circuit because greater space between the standard cells may be needed. FIG.5is a flow chart depicting another example method of fabricating a semiconductor device structure such as one embodying the circuit depicted inFIG.3. In this example method, metal-1 usage for inter cell routing is increased and upper level metal usage (e.g., metal-2, metal-3 and/or other upper metal level usage) is decreased. Because of increased metal-1 usage and decreased upper level metal usage, the example semiconductor device can have more digital blocks, IR drop can be reduced and routing can be made more flexible. This example method comprises defining a semiconductor device structure (operation300), defining input port(s) on M0OD and PO layers of the semiconductor device structure and output port(s) on M0OD layers (operation302), and defining inter cell and intra cell connections (operation304) in a way that maximizes the use of the metal-1 layer for interconnections and minimizes the use of upper metal layers for interconnections. In this example method, defining inter cell and intra cell connections (operation304) may involve defining a first set and a second set of interconnection paths (e.g., metal-1 mask A and metal-1 mask B) on the metal-1 layer above the semiconductor structure (operation306) and defining a first set and a second set of interconnection paths (e.g., metal-2 mask A and metal-2 mask B) on the metal-2 layer above the metal-1 layer (operation308) wherein the metal-2 conduction paths are in a direction perpendicular to the direction of the metal-1 conduction paths. First sets and second sets of interconnection paths (e.g., metal-3/4/5/6/7/8/9/10/11/12/13/AP mask A and metal-3/4/5/6/7/8/9/10/11/12/13/AP mask B) may be defined on the upper metal layers as needed (operation310). FIG.6is a flow chart depicting another example method of fabricating a semiconductor device structure such as one embodying the circuit depicted inFIG.3. In this example method, metal-1 usage for inter cell routing is increased and upper level metal usage (e.g., metal-2, metal-3 and/or other upper metal level usage) is decreased. Because of increased metal-1 usage and decreased upper level metal usage, the example semiconductor device can have more digital blocks, IR drop can be reduced and routing can be made more flexible. IR drop increases when paths in upper levels are used for interconnections because paths become longer. IR drop also increases because vias are used to connect metal paths in different layers. The resistivity of the vias are typically much higher than the resistivity of the metal paths. This example method comprises defining a multi-layer semiconductor device structure comprising a plurality of standard cells arranged on a substrate using a fabrication technology having an M0OD layer and a PO layer (operation400), defining input port(s) on the M0OD and/or PO layers of the semiconductor device structure and output port(s) on the M0OD layers (operation402), defining a first set and a second set of interconnection paths (e.g., metal-1 mask A and metal-1 mask B) on the metal-1 layer above the semiconductor structure (operation404) and defining a first set and a second set of interconnection paths (e.g., metal-2 mask A and metal-2 mask B) on the metal-2 layer above the metal-1 layer (operation406) as necessary, wherein the metal-2 conduction paths are in a direction perpendicular to the direction of the metal-1 conduction paths. Interconnection paths may be defined on the upper metal layers (e.g., metal 3/4/5/6/7/8/9/10/11/12/13/AP) as needed (operation407). In this example, defining a multi-layer semiconductor device structure comprises removing the metal-1 interconnection design, metal-1 blockages, input port(s), and output port(s) from the standard cell design. Also in this example, defining a first set and a second set of interconnection paths on the metal-1 layer comprises defining inter cell routing on the first set of interconnection paths (e.g., MaskA) wherein at least one metal-1 conduction path in the first set of conduction paths extends across multiple cells (operation410) and defining the intra cell routing on the second set of interconnection paths (e.g., MaskB) (operation412). The first set of metal-1 conduction paths and the metal-2 conduction paths are configured to interconnect circuit components in different cells. Depicted inFIG.7is a top view illustrating an example layout of the upper layers of the semiconductor structure of the circuit ofFIG.3and the associated metal-1 layer fabricated in accordance with the method specified inFIG.5or6. Illustrated in the example layout are a VDD power rail510, a VSS power rail512, a PO layer514, an OD layer516, a M0OD1 layer518, a M0OD2 layer520, metal-1 mask A conduction paths524, metal-1 mask B conduction paths526, a V0 MD via layer528, a V0 MG via layer530, RVIA532, and CM1 element534. The layout shows metal-1 mask A conduction paths524spanning across multiple cells, which allows inter cell connections without using upper metal layers. Because the metal-1 interconnection design, metal-1 blockages, input port(s), and output port(s) are removed from the standard cell design, the metal-1 mask A conduction paths524can span across multiple cells, which allows inter cell connections without using upper metal layers. FIG.8is a layout diagram illustrating an example layout of the metal-2 and metal-3 layers for the semiconductor structure of the circuit ofFIG.3fabricated in accordance with the method specified inFIG.5or6. The example layout includes VIA1 550, Metal-2 maskA conduction path554, and Metal-2 maskB conduction path556. In this example, two Metal-2 conduction paths are fabricated in the metal-2 layer (one Metal-2 mask A and one Metal-2 Mask B path) and no metal-3 conduction paths are fabricated in the metal-3 layer. These example methods resulted in decreased upper metal usage. The example semiconductor device can have more digital blocks, IR drop has been reduced and routing is more flexible. FIG.9is a flow chart depicting another example method of fabricating a semiconductor device structure such as one embodying the circuit depicted inFIG.3. In this example method, metal-1 usage for inter cell routing is increased and upper level metal usage is decreased. Because of increased metal-1 usage and decreased upper level metal usage, the example semiconductor device can have more digital blocks, IR drop can be reduced and routing can be made more flexible. This example method comprises defining a multi-layer semiconductor device structure comprising a plurality of standard cells arranged on a substrate using N10 fabrication technology having an M0OD layer and a PO layer (operation600), defining input port(s) and output port(s) on M0OD and/or PO layers of the semiconductor device structure (operation602), defining a metal-1 layer having up to six horizontal direction metal-1 conduction paths per cell over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths wherein at least one metal-1 conduction path in the first set of conduction paths extends across multiple cells (operation604), and defining a metal-2 layer over the metal-1 layer wherein the metal-2 conduction paths are in a direction perpendicular to the direction of the metal-1 conduction paths, the metal-2 layer having a first set of metal-2 conduction paths and a second set of metal-2 conduction paths (operation606). Interconnection paths may be defined on the upper metal layers (e.g., metal 3/4/5/6/7/8/9/10/11/12/13/AP) as needed (operation607). In this example, defining a multi-layer semiconductor device structure comprises removing the metal-1 interconnection design, metal-1 blockages, input port(s), and output port(s) from the standard cell design (operation608). Also in this example, defining a first set and a second set of interconnection paths on the metal-1 layer comprises defining inter cell routing on the first set of interconnection paths (e.g., MaskA) (operation610) and defining the intra cell routing on the second set of interconnection paths (e.g., MaskB) (operation612). The example method also comprises configuring the first set of metal-1 conduction paths, the metal-2 conduction paths, and the upper level metal conduction paths (e.g., metal 3/4/5/6/7/8/9/10/11/12/13/AP to interconnect circuit components in different cells (operation614). The methods described herein can be used to fabricate integrated circuits that rely heavily on metal-1 conduction paths for inter cell routing. Thus, use of upper level metal conduction paths can be reduced. This can result in more digital blocks in the integrated circuit, IR drop can be reduced and routing can be made more flexible. In one embodiment, a method of fabricating an integrated circuit is provided. The method comprises defining a multi-layer semiconductor device structure comprising a plurality of standard cells arranged on a substrate using a fabrication technology having a metal-0 oxide diffusion (M0OD) layer and a polysilicon (PO) layer, defining an input port on either the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer of the semiconductor device structure, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths wherein at least one metal-1 conduction path in the first set of conduction paths extends across multiple cells. The method further comprises defining a metal-2 layer having horizontal direction metal-2 conduction paths over the metal-1 layer wherein the metal-2 conduction paths are in a direction perpendicular to the direction of the metal-1 conduction paths, the metal-2 layer having a first set of metal-2 conduction paths and a second set of metal-2 conduction paths, and configuring the first set of metal-1 conduction paths and the first set of metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths. These aspects and other embodiments may include one or more of the following features. Configuring the first set of metal-1 conduction paths and the first set of metal-2 conduction paths to interconnect circuit components in different cells may comprise defining a via to connect a metal-1 conduction paths to a circuit component. The method may further comprise defining a first via to connect a metal-2 conduction path with a first of the metal-1 conduction paths and a second via to connect the metal-2 conduction path with a second of the metal-1 conduction paths. The first of the metal-1 conduction paths and the second of the metal-1 conduction paths may extend across different cells. The metal-1 layer may have up to six horizontal direction metal-1 conduction paths per cell. Defining an input port on either the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer of the semiconductor device structure may comprise defining each input port of the semiconductor device structure and each output port of the semiconductor device structure such that no input port or output port is defined on the metal-1 layer. The integrated circuit may comprise a second semiconductor device structure comprising a plurality of standard cells arranged on a substrate using a fabrication technology having a metal-0 oxide diffusion (M0OD) layer and a polysilicon (PO) layer. The method may be implemented such that no inter cell connection in the semiconductor device structure is made using a metal-3 conduction path in a metal-3 layer above the metal-1 and metal-2 layers. The method may be implemented such that all inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and first set of metal-2 conduction paths. The method may further comprise configuring the second set of metal-1 conduction paths and the second set of metal-2 conduction paths to interconnect circuit components within the same cell. no blockages may be defined in the metal-1 layer. The method may be implemented such that no top level connections are made to the metal-1 layer. In another embodiment, a multi-layer semiconductor device structure in an integrated circuit (IC) is provided. The multi-layer semiconductor device structure comprises a plurality of cells arranged on a substrate and fabricated using a fabrication technology having a metal-0 oxide diffusion (M0OD) layer and a polysilicon (PO) layer, an input port fabricated on the M0OD or PO layer of a first cell of the plurality of cells, and an output port fabricated on the M0OD layer of a second cell of the plurality of cells. The multi-layer semiconductor device structure further comprises a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths wherein at least one metal-1 conduction path in the first set of conduction paths extends across multiple cells, and a metal-2 layer having horizontal direction metal-2 conduction paths over the metal-1 layer wherein the metal-2 conduction paths are in a direction perpendicular to the direction of the metal-1 conduction paths, the metal-2 layer having a first set of metal-2 conduction paths and a second set of metal-2 conduction paths, wherein the first set of metal-1 conduction paths and the first set of metal-2 conduction paths are configured to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths. These aspects and other embodiments may include one or more of the following features. Each input port of the semiconductor device structure may be defined on either the M0OD or PO layer of the semiconductor device structure and each output port of the semiconductor device structure may be defined on the M0OD layer of the semiconductor device structure. The method may be implemented such that no inter cell connection in the semiconductor device structure may be made using a metal-3 conduction path in a metal-3 layer above the metal-1 and metal-2 layers. The method may be implemented such that all inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and first set of metal-2 conduction paths. The second set of metal-1 conduction paths and the second set of metal-2 conduction paths may be configured to interconnect circuit components within the same cell. The metal-1 layer may have up to six horizontal direction metal-1 conduction paths per cell. In another embodiment, a method for defining interconnections in an integrated circuit comprising a multi-layer semiconductor device structure comprising a plurality of cells arranged on a substrate using standard cells using a fabrication technology having a metal-0 oxide diffusion (M0OD) layer and a polysilicon (PO) layer is provided. The method comprises defining an input port of the semiconductor device structure on either the M0OD or PO layer of the semiconductor device structure and an output port of the semiconductor device structure on the M0OD layer of the semiconductor device structure and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths wherein at least one metal-1 conduction path in the first set of conduction paths extends across multiple cells. The method further comprises defining a metal-2 layer having horizontal direction metal-2 conduction paths above the metal-1 layer wherein the metal-2 conduction paths are in a direction perpendicular to the direction of the metal-1 conduction paths, the metal-2 layer having a first set of metal-2 conduction paths and a second set of metal-2 conduction paths, defining a plurality of upper level metal layers having upper level conduction paths above the metal-2 layers, configuring the first set of metal-1 conduction paths, the metal-2 conduction paths, and the plurality of upper level conduction paths to interconnect circuit components in different cells, wherein inter cell connections are made using the first set of metal-1 conduction paths, the metal-2 conduction paths and the upper level conduction paths, and configuring the second set of metal-1 conduction paths to interconnect circuit components within the same cell. These aspects and other embodiments may include one or more of the following features. Defining an input port on either the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer of the semiconductor device structure may comprise defining each input port of the semiconductor device structure on either the M0OD or PO layer of the semiconductor device structure and each output port of the semiconductor device structure on the M0OD layer of the semiconductor device structure. The method may be implemented such that no intra cell connection in the semiconductor device structure is made using an upper level conduction path. The method may be implemented such that all inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths. The method may further comprise configuring the second set of metal-1 conduction paths and the second set of metal-2 conduction paths to interconnect circuit components within the same cell. The metal-1 layer may have up to six horizontal direction metal-1 conduction paths per cell. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 26,908 |
11862569 | DETAILED DESCRIPTION The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate, a singulated die-level substrate, or another die for die-stacking applications. Suitable steps of the methods described herein can be performed at the wafer-level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques. The present technology includes a semiconductor device having an interconnect structure for backside electrical connection formed (e.g., “pre-positioned”) during front-end-of-line (FEOL) processing. FEOL is the stage of integrated circuit fabrication in which individual devices (transistors, capacitors, resistors, etc.) are formed at the active side of the semiconductor material. In contrast to the present technology, FEOL processes occur before fabricating metal interconnect structures at the backside. Conventional semiconductor device packages use back-end-of-line (BEOL) processing to form contact pads, through silicon vias, interconnect wires, and/or dielectric structures. During BEOL processing, metals and/or dielectric materials are deposited on the wafer to create contacts, insulating materials, metal levels, and/or bonding sites for chip-to-chip and chip-to-package connections. After BEOL processing, a probe stage is performed to physically acquire signals from the internal nodes of a semiconductor device for failure analysis and defect detection. Following the probe stage, post-probe processing is performed, which includes processes on the front side and/or the backside, including, e.g., three-dimensional integration (3DI) processing among other processing. The present technology is generally directed to forming an interconnect structure during FEOL processing (e.g., gate level processing) at or near the active side of the die and exposing or otherwise accessing the pre-positioned interconnect structure during BEOL or post-probe processing with ultra-thin silicon processing or total silicon removal. In some embodiments, the present technology eliminates the need for forming BEOL TSVs, allows direct-to-device routing, and enables ultra-thin die stacking among other advantages over conventional process. In some embodiments, a shallow interconnect area is positioned deeper than a shallow trench isolation (STI) structure and is formed in or on the substrate during first level FEOL processing. The FEOL processed interconnect or interconnect area has an active contact surface that is at least partially buried within the substrate material and/or dielectric materials during at least a portion of the FEOL processing. The FEOL interconnect is then revealed for access from the backside during BEOL or post-probe processing. Various FEOL interconnect configurations are within the scope of the present technology, such as array, sacrificial oxide, etc., or any combination thereof. Processing of three-dimensional integration (3DI) using the present technology is expected to reduce cost and provide a high degree of design flexibility for routing and other structures. For example, backside routing components can be formed during FEOL processing and accessed for electrical connection through the substrate during BEOL or post-probe processing, as will be described below. In contrast, conventional processing requires forming backside routing components by patterning, etching, and filling deep holes in the silicon material to create through silicon vias during BEOL processing, which poses various challenges, e.g., etching and filling relatively deep holes, processing without damaging thin layers, layout design limitations, etc. In these regards, interconnects of the present technology are more directly integrated than conventional device connections. Some embodiments can be applied to bonded microelectronic devices, such as NAND circuits, among others. In these configurations, separate complementary metal-oxide-semiconductor (CMOS) and array chips are bonded together face-to-face. During FEOL processing, a FEOL interconnect is pre-positioned in the silicon material and/or the dielectric materials of the array chip assembly and accessed for electrical connection through the backside of the array chip assembly. In some embodiments, the CMOS assembly includes periphery circuit devices that support the array, but generally does not include memory cells and access devices; and the array assembly includes wordlines, bitlines, access devices, and memory cells, but generally does not include periphery circuit devices such as drivers, latches, controllers, regulators, etc. FIGS.1A-1Eshow enlarged cross-sectional views of various stages of fabricating a semiconductor device comprising an array chip assembly100(“array assembly100”) and a CMOS chip assembly200(CMOS200) in accordance with embodiments of the present technology. The array assembly100includes a substrate110, such as a silicon, silica, or silicate substrate, on which various materials and components may be formed. The array assembly100also includes a dielectric material112on the substrate110and a metal conducting material114formed on at least a portion of the dielectric material112. The dielectric material112can be silicon oxide or another non-conductive material grown or deposited on the substrate110, or the dielectric material112can be a non-resin or other inorganic material capable of withstanding temperatures over 600° C. The electrically conducting material114can have line portion114aand an interconnect structure114b, where the interconnect structure114bcan have FEOL pre-positioned interconnect150(“FEOL interconnect”), such as a 3Dx contact. The FEOL interconnect150is at least partially embedded within the dielectric material112in this example. The array assembly can further include an additional dielectric material116on the side of the FEOL interconnect150opposite the dielectric material112to protect the FEOL interconnect150during processing. The array assembly100may further include a 3D memory array120proximate the dielectric material112and having a plurality of stacked memory array layers121electrically coupled to the line portion114athrough one or more base pillars122. Although illustrated with ten array layers121in a stacked configuration in the instant example, the 3D memory array120may have any number of array layers121. The array assembly100may also have multi-height pillars136defining interconnects that electrically couple the array layers121to one or more first bond pads130through conductive traces/caps132and134(e.g., copper, solder, etc.). In some embodiments, the array assembly100may also include one or more second bond pads140electrically coupled to the line portion114, for example using a TSV146connected to the second bond pad140through a conductive trace/cap142and144. A dielectric material118may encase components of the semiconductor device, e.g., the 3D memory array120, the pillars136, the bond pads130,140, and210, etc. Although one configuration of the array assembly100is depicted in the Figures, any suitable configuration of the array assembly100is also within the scope of the present technology. The CMOS200may be any suitable CMOS chip and includes a substrate202, active electrical components204(e.g., transistor, etc.), and bond pads210configured to be electrically coupled to the bond pads of the array assembly100. As shown inFIG.1A, the array assembly100and the CMOS200are separately formed and prepared for bonding through the bond pads130,140, and210. Next, inFIG.1B, the array assembly100is flipped such that the array assembly100and the CMOS200are face-to-face to position the first and second bond pads130and140toward the bond pads210. As shown, each bond pad of the array assembly100corresponds to a bond pad210; however, in other embodiments some of the bond pads may be configured to bond to multiple bond pads in a bridging configuration. InFIG.1C, the first and second bond pads130and140of the array assembly100are mated and bonded to the bond pads210of the CMOS200to form electrical connections between the array assembly100and the CMOS200. During BEOL, the FEOL interconnect150is exposed on the backside of the array assembly100. As shown inFIG.1D, the silicon substrate110is thinned or removed to expose at least a portion of the dielectric material112. Next, inFIG.1E, the dielectric material112is patterned and etched to form an opening113that exposes an active contact surface152of the FEOL interconnect150such that electrical connections can be made to the components of the array assembly100and the CMOS200from the backside of the array assembly100. Once exposed, the FEOL interconnect150can be patterned to create bond pads (not shown) for further interconnects, to receive solder balls, etc. Although one configuration of an FEOL interconnect is shown, other configurations are within the scope of the present technology. FIGS.2A-2Fshow enlarged cross-sectional views of semiconductor devices having an FEOL interconnect structure configured in accordance with additional embodiments of the present technology.FIGS.2A-2Fshow array chip assemblies300-800, respectively, which are similar in overall structure and configuration to the array assembly100ofFIGS.1A-1E, except that the array chip assemblies300-800show several possible variations of FEOL interconnects. The configurations of the FEOL interconnects inFIGS.2A-2Fare intended to illustrate some of the variations in the FEOL interconnects; however, further suitable variations are within the scope of the present technology. In these embodiments, similar steps to those inFIGS.1A-1Ehave already been performed to the semiconductor device (e.g., bonding, removal of the substrate, and etching of the insulating material, etc.), such that the exposed FEOL interconnect is shown. The CMOS200remains the same configuration as inFIGS.1A-1E. Like reference numbers refer to similar features inFIGS.2A-2F, but are in the 300-800-series, respectively, and the features may have variations and/or have different shapes and sizes. FIG.2Ashows an embodiment of an array chip assembly300(“array assembly300”) bonded to the CMOS200. In this configuration, a portion of a dielectric material312is removed to form an opening313and thereby expose a portion of a metal conducting material314formed in the array assembly300. The conducting material314has a line portion315and an FEOL pre-positioned interconnect350defined by a distal portion of the conducting material314, which can be a 3Dx contact. The FEOL interconnect has a contact surface352through which electrical connections can be made to the components of the array assembly300and the CMOS200from the backside of the array assembly300. Once exposed, the contact surface352of the FEOL interconnect350can be patterned to create bond pads (not shown) for further interconnects, to receive solder balls, etc. FIG.2Bshows an embodiment of an array chip assembly400(“array assembly400”) bonded to the CMOS200. In this configuration, a dielectric material412is thinner than the dielectric material312ofFIG.2A, and the dielectric material412follows the sloped contour of a metal conducting material414such that a portion of a substrate410remains after, e.g., ultra-thin silicon processing. The conducting material414can have a line portion415and an FEOL pre-positioned interconnect450defined by a distal portion of the conducting material414. A portion of the substrate410and a portion of the insulating material412are removed to expose the conducting material414at the FEOL interconnect450. The exposed portion of the FEOL interconnect450has a contact surface452through which electrical connections can be made to the components of the array assembly400and the CMOS200from the backside of the array assembly400. Once exposed, the contact surface452of the FEOL interconnect450can be patterned to create bond pads (not shown) for further interconnects, receive solder balls, etc. Since some of the substrate410remains after exposing the FEOL interconnect450, the substrate410can be doped such that further devices can be built in the remaining substrate material410to provide additional configurations of the semiconductor device. FIG.2Cshows an embodiment of an array chip assembly500(“array assembly500”) bonded to the CMOS200. The array assembly500has planar electrical conducting material514with a line portion515and an FEOL interconnect550defined by a distal end of the conducting material514. In this configuration, a portion of a dielectric insulating material512is removed to form an opening513and thereby expose a contact surface552of the FEOL interconnect550. An additional insulating material560is formed on the insulating material512. The metal conducting material514has a planar configuration without a slope. The contact surface552can be coupled to electrical connectors through which electrical connections can be made to the components of the array assembly500and the CMOS200from the backside of the array assembly500. Once exposed, the contact surface552of the FEOL interconnect550can be patterned to create bond pads (not shown) for further interconnects, to receive solder balls, etc. FIG.2Dshows an embodiment of an array chip assembly600(“array assembly600”) bonded to the CMOS200. In this configuration, a metal conducting material614comprises a first metal conducting material614a(e.g., a line portion) and a second metal conducting material614bat a different level in the array assembly600than the first metal conducting material614a. The first and second conducting materials614aand614bcan be electrically connected to each other by an interconnect670. The second conducting material614bdefines an FEOL pre-positioned interconnect650having a contact surface652. During processing, a portion of a dielectric insulating material612is removed to form an opening613and thereby expose the contact surface652. The FEOL interconnect650enables electrical connections to be made to the components of the array assembly600and the CMOS200from the backside of the array assembly600. Once exposed, the contact surface652of the FEOL interconnect650can be patterned to create bond pads (not shown) for further interconnects, to receive solder balls, etc. FIG.2Eshows an embodiment of an array chip assembly700(“array assembly700”) bonded to the CMOS200. The assembly700has a metal conducting material714comprising a first metal conducting material714aand a second metal conducting material714bat different levels in the array assembly700. The first and second conducting materials714aand714bare electrically connected to each other by an interconnect770. The second conducting material714bdefines an FEOL pre-positioned interconnect750having a contact surface752. During processing, a portion of a dielectric insulating material712is removed to form an opening713having a sidewall714that exposes the contact surface752. In this configuration, an additional insulating material760is formed on the insulating material712. The contact surface752can be configured to electrically couple the components of the array assembly700and the CMOS200to other components (e.g., a package substrate) from the backside of the array assembly700. For example, the contact surface752of the FEOL interconnect750can be patterned to create bond pads (not shown) for further interconnects, to receive solder balls, etc. FIG.2Fshows an embodiment of an array chip assembly800(“array assembly800”) bonded to the CMOS200. In this configuration, a dielectric insulating material812is thin and follows the stepped contour of a metal conducting material814such that a portion of a substrate810remains after, e.g., ultra-thin silicon processing. The substrate810may include a first substrate material810aand a second substrate material810b, each having different levels of doping. The metal conducting material814can have a line portion814aand an interconnect structure814b, and the conducting material814can have trench862in which an additional dielectric insulating material816may be formed. A portion of the substrate810and a portion of the insulating material812are removed to expose a portion of the conducting material814formed in the array assembly800. The interconnect structure814bdefines an FEOL pre-positioned interconnect850having a contact surface852through which electrical connections can be made to the components of the array assembly800and the CMOS200from the backside of the array assembly800. The contact surface852of the FEOL interconnect850can be patterned to create bond pads (not shown) for further interconnects, receive solder balls, etc. Since some of the substrate810remains after exposing the FEOL interconnect850, the first substrate material810acan be doped such that further devices can be built in the remaining substrate materials810aand/or810bto provide additional configurations of the semiconductor device. FIGS.3A-3Dshow enlarged cross-sectional views of semiconductor devices having FEOL pre-positioned interconnects configured in accordance with additional embodiments of the present technology.FIGS.3A-3Dshow a portion of an array chip assembly1000(“array assembly1000”), e.g., the portion of the array assembly800defined by the broken line border3A-4D shown inFIG.2F. The array assembly1000is similar in overall structure and configuration to the array assemblies100and800ofFIGS.1A-1E and2F, respectively, except that the array assembly1000shows additional variations in the FEOL interconnects and selected steps of creating contact with the FEOL interconnects. Further suitable variations are within the scope of the present technology. In these embodiments, some of the steps shown inFIGS.1A-1Ehave already been performed (e.g., bonding to the CMOS, etc.). Like reference numbers refer to similar features inFIGS.3A-3D, but are in the 1000-series, and the features may have variations and/or have different shapes and sizes. FIG.3Ashows an embodiment of the array assembly1000which may be bonded to a CMOS assembly (not shown). The array assembly1000includes a substrate1010, such as a silicon, silica, or silicate substrate, on which various materials and components may be formed. The substrate1010may include multiple regions with different levels of doping, such as a first substrate region1010a(e.g., a bulk silicon region), a second substrate region1010b(e.g., an implant region), and a third substrate region1010c(e.g., an additional implant region having a different doping level than the second substrate region1010b). In other embodiments, the substrate1010has any number of different doping materials/regions, or a single level of doping throughout. The array assembly1000includes a dielectric insulating material1012and a metal conducting material1014formed within the regions of the substrate1010. The distal portion of the conducting material1014defines an FEOL pre-positioned interconnect structure1050that is at least partially formed within the insulating material1012. An additional dielectric insulating material1016may be formed in a trench1062. FIG.3Bshows the array assembly1000in an inverted position relative to the position shown inFIG.3Aand after a portion of the first substrate material1010aand a portion of the insulating material1012have been removed to expose a the distal portion of the conducting material1014. The FEOL pre-positioned interconnect structure1050has a conductive surface1052through which electrical connections can be made to the components of the array assembly1000and the CMOS (not shown) from the backside of the array assembly1000. The conductive surface1052of the FEOL interconnect1050may have protrusions1090that increase the surface area for adhesion, etc. FIG.3Cshows the array assembly1000after an additional insulating material1060has been formed on the insulating material1012and patterned/etched to form an opening1064that exposes the conductive surface1052of the FEOL interconnect1050.FIG.3Dshows the array assembly1000after a backside metal material1094has been deposited and electrically coupled to the contact surface1052. The backside metal1094is accordingly a contact feature of the FEOL interconnect1050. FIGS.4A-4Dshow enlarged cross-sectional views of semiconductor devices having an FEOL pre-positioned interconnect configured in accordance with additional embodiments of the present technology.FIGS.4A-4Dshow a portion of an array chip assembly1100(“array assembly1100”), e.g., the portion of the array assembly800defined by the broken line border3A-4D shown inFIG.2F. The array assembly1100is similar in overall structure and configuration to the array assemblies100and800ofFIGS.1A-1E and2F, respectively, except that the array assembly1100shows an additional variation for an FEOL interconnect and selected steps of forming the FEOL interconnect. Further suitable variations are within the scope of the present technology. In these embodiments, some of the steps shown inFIGS.1A-1Ehave already been performed (e.g., bonding to the CMOS, etc.). Like reference numbers refer to similar features inFIGS.4A-4D, but are in the 1100-series and the features may have variations and/or have different shapes and sizes. FIG.4Ashows an embodiment of the array assembly1100which may be bonded to a CMOS assembly (not shown). The array assembly1100includes a substrate1110, such as a silicon, silica, or silicate substrate, on which various materials and components may be formed. The substrate1110may include multiple regions with different levels of doping, such as a first substrate region1110a(e.g., a bulk silicon region), a second substrate region1110b(e.g., an implant region), and a third substrate region1110c(e.g., an additional implant region having a different doping level than the second substrate region1110b). In other embodiments, the substrate1110has any number of different doping materials/regions, or a single level of doping throughout. The array assembly1100includes a dielectric material1112and a metal conducting material1114formed within the regions of the substrate1110. The conducting material1114has a line portion and an FEOL pre-positioned interconnect structure1150with a contact surface1152. An additional dielectric insulating material1116may be formed in a trench1162. FIG.4Bshows the array assembly1100after a portion of the first substrate region1110ahas been removed to expose a portion of the dielectric material1112. As opposed to the embodiment shown inFIG.3B, the dielectric material1112may remain after ultra-thin silicon processing. The line portion of the conducting material1114remains beneath the dielectric material1112. The FEOL interconnect1150may be configured with a conductive surface1152for forming further interconnects, to receive solder balls, etc.FIG.4Cshows the array assembly1100after an additional insulating material1160has been formed on the dielectric material1112, and a plurality of openings1196have been formed through the dielectric material1112and insulating material1160to expose the conductive surface1152of the FEOL interconnect1150.FIG.4Dshows a backside metal deposition material1194filling the openings1196and contacting the conductive surface1152for electrically coupling the FEOL interconnect1150to other components (e.g., a package substrate or another device). The interconnects described herein may be formed from suitable conductive materials, such as copper (Cu), and may have solder caps to form the electrical connections (e.g., tin-silver (SnAg) solder caps). During assembly, the solder cap can be reflowed using gang reflow, sonic reflow, or other techniques. The bond pads can be copper pads and may be bonded using copper-to-copper bonding or other suitable techniques. FIG.5is a block diagram illustrating a system that incorporates a semiconductor device in accordance with embodiments of the present technology. Any one of the semiconductor devices having the features described above with reference toFIGS.1A-4Dcan be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system1200shown schematically inFIG.5. The system1200can include a processor1202, a memory1204(e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices1206, and/or other subsystems or components1208. The semiconductor assemblies, devices, and device packages described above with reference toFIGS.1A-4Dcan be included in any of the elements shown inFIG.5. The resulting system1200can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system1200include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system1200include lights, cameras, vehicles, etc. In these and other examples, the system1200can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system1200can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media. As used in the foregoing description, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, left/right, and distal/proximate can be interchanged depending on the orientation. Moreover, for ease of reference, identical reference numbers are used to identify similar or analogous components or features throughout this disclosure, but the use of the same reference number does not imply that the features should be construed to be identical. Indeed, in many examples described herein, identically numbered features have a plurality of embodiments that are distinct in structure and/or function from each other. Furthermore, the same shading may be used to indicate materials in cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical unless specifically noted herein. The foregoing disclosure may also reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the new technology. Also, in this regard, the present disclosure may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. For the purposes of the present disclosure, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed. From the foregoing, it will be appreciated that specific embodiments of the new technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the present disclosure. Accordingly, the invention is not limited except as by the appended claims. Furthermore, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present disclosure. Accordingly, the present disclosure and associated technology can encompass other embodiments not expressly shown or described herein. | 29,579 |
11862570 | DETAILED DESCRIPTION Semiconductor packages according to some example embodiments of the present disclosure will hereinafter be described with reference toFIGS.1through17. FIG.1is a layout view of a semiconductor package, according to some example embodiments of the present disclosure.FIG.2is a cross-sectional view taken along line A-A ofFIG.1.FIGS.3and4are enlarged views illustrating a region R ofFIG.2. Referring toFIGS.1through4, the semiconductor package includes a first substrate100, a first semiconductor chip150, an interposer200, first connecting members170, supporting members180, a second substrate300, a second semiconductor chip350, and second connecting members280. The first substrate100may be a substrate for a package. For example, the first substrate100may be a printed circuit board (PCB) or a ceramic substrate. In another example, the first substrate100may be a substrate for a wafer-level package (WLP). The first substrate100may have bottom and top surfaces that are opposite to each other. The first substrate100may include a first insulating layer110, first conductive patterns112, a first lower passivation film120, first lower pads122, a first upper passivation film130, first upper pads132, and second upper pads134. The first insulating layer110and the first conductive patterns112in the first insulating layer110may form wiring patterns for electrically connecting the first lower pads122and the first upper pads132. The first insulating layer110is illustrated as having a single-layer structure, but the present disclosure is not limited thereto. For example, the first insulating layer110may be formed to have a multilayer structure to form multilayer first conductive patterns112. The first lower passivation film120and the first lower pads122may be formed on the bottom surface of the first insulating layer110. The first lower pads122may be electrically connected to the first conductive patterns112. The first lower passivation film120may cover the bottom surface of the first insulating layer110and may expose the first lower pads122. In some embodiments, third connecting members140may be formed on the bottom surface of the first substrate100. The third connecting members140may be attached to the first lower pads122. The third connecting members140may have, for example, a spherical or an elliptical spherical shape, when viewed in plan view, but the present disclosure is not limited thereto. The third connecting members140may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or a combination thereof, but the present disclosure is not limited thereto. The third connecting members140may electrically connect the first substrate100and an external device. Accordingly, the third connecting members140may provide electrical signals to the first substrate100or may provide electrical signals from the first substrate100to the external device. The first upper passivation film130, the first upper pads132, and the second upper pads134may be formed on the top surface of the first insulating layer110. The first upper passivation film130may cover the top surface of the first insulating layer110and may expose the first upper pads132and the second upper pads134. In some embodiments, top surfaces of the first upper passivation film130, the first upper pads132, and the second upper pads134may be coplanar with one another, and bottom surfaces of the first upper passivation film130, the first upper pads132, and the second upper pads134may be coplanar with one another. In other embodiments, a top surface of the first upper passivation film130may be at a higher vertical level (e.g., in a direction perpendicular to a top surface of the first substrate100) than top surfaces of the first upper pads132and the second upper pads134, and bottom surfaces of the first upper passivation film130, the first upper pads132, and the second upper pads134may be coplanar with one another. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein, encompass near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. In some embodiments, the first upper pads132may be electrically connected to the first lower pads122, and the second upper pads134may not be electrically connected to the first lower pads122. For example, the first upper pads132may be in contact with the first conductive patterns112, and the second upper pads134may not be in contact with the first conductive patterns112. In some embodiments, bottom surfaces of the second upper pads134may contact only a top surface of the first insulating layer110. The first lower passivation film120and the first upper passivation film130may include, for example, a photo-imageable dielectric (PID) material, but the present disclosure is not limited thereto. The first semiconductor chip150may be disposed on the first substrate100. For example, the first semiconductor chip150may be mounted on the top surface of the first substrate100. The first semiconductor chip150may be an integrated circuit (IC) into which hundreds to millions of semiconductor elements are integrated. For example, the first semiconductor chip150may be an application processor (AP) such as a central processing unit (CPU), a graphic processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like, but the present disclosure is not limited thereto. For example, the first semiconductor chip150may be a logic chip such as an analog-to-digital converter (ADC) or an application-specific IC (ASIC) or a memory chip such as a volatile memory (e.g., a dynamic random access memory (DRAM)) or a nonvolatile memory (e.g., a read-only memory (ROM) or a flash memory). Also, the first semiconductor chip150may be the combination of a logic chip and a memory chip. FIGS.1through4illustrate that only one first semiconductor chip150is formed on the first substrate100, but the present disclosure is not limited thereto. For example, the plurality of first semiconductor chips150may be formed side-by-side on the first substrate100or may be sequentially stacked on the first substrate100. In some embodiments, the first semiconductor chip150may be mounted on the first substrate100via flip-chip bonding. For example, first bumps160may be formed between the top surface of the first substrate100and the bottom surface of the first semiconductor chip150. The first bumps160may electrically connect the first substrate100and the first semiconductor chip150. Each of the first bumps160may include, for example, a first pillar layer162and a first solder layer164. The first pillar layers162may protrude from the bottom surface of the first semiconductor chip150. For example, the first pillar layers162may include Cu, a Cu alloy, Ni, a Ni alloy, Pd, Pt, Au, Co, or a combination thereof, but the present disclosure is not limited thereto. The first solder layers164may connect the first pillar layers162and the first substrate100. For example, the first solder layers164may be connected to some of the first upper pads132. The first solder layers153may have, for example, a spherical or elliptical spherical shape, when viewed in plan view, but the present disclosure is not limited thereto. The first solder layers164may include, for example, Sn, In, Bi, Sb, Cu, Ag, Zn, Pb, or a combination thereof, but the present disclosure is not limited thereto. The interposer200may be interposed between the first and second substrates100and300. For example, the interposer200may be disposed on the top surface of the first substrate100. In some embodiments, the interposer200may be disposed on the top surface of the first semiconductor chip150. The interposer200may facilitate connecting the first and second substrates100and300. Also, the interposer200may prevent warpage of the first and second substrates100and300. The interposer200may have bottom and top surfaces that are opposite to each other. For example, the bottom surface of the interposer200may face the top surface of the first substrate100, and the top surface of the interposer200may face the bottom surface of the second substrate300. In some embodiments, the interposer200may be spaced apart from the first substrate100. In some embodiments, a distance D21from the top surface of the first substrate100to the bottom surface of the interposer200may be about 120 μm to about 200 μm. In some embodiments, the interposer200may be spaced apart from the first semiconductor chip150. In some embodiments, a distance D22from the top surface of the first semiconductor chip150to the bottom surface of the interposer200may be about 15 μm to about 45 μm. The interposer200may include a second insulating layer210, second conductive patterns212, a second lower passivation film220, second lower pads222, third lower pads224, a second upper passivation film230, and third upper pads232. The second insulating layer210and the second conductive patterns212in the second insulating layer210may form wiring patterns for electrically connecting the second lower pads222and the third upper pads232. The second insulating layer210is illustrated as having a single-layer structure, but the present disclosure is not limited thereto. For example, the second insulating layer210may be formed to have a multilayer structure to form multilayer second conductive patterns212. The second lower passivation film220, the second lower pads222, and the third lower pads224may be formed on the bottom surface of the second insulating layer210. The second lower passivation film220may cover the bottom surface of the second insulating layer210and may expose the second lower pads222and the third lower pads224. For example, a top surface of the second lower passivation film220may contact the bottom surface of the second insulating layer210. In some embodiments, top surfaces of the second lower passivation film220, the second lower pads222, and the third lower pads224may be coplanar with one another, and bottom surfaces of the second lower passivation film220, the second lower pads222, and the third lower pads224may be coplanar with one another. In other embodiments, top surfaces of the second lower passivation film220, the second lower pads222, and the third lower pads224may be coplanar with one another, and a bottom surface of the second lower passivation film220may be at a lower vertical level (e.g., in a direction perpendicular to the top surface of the first substrate100) than bottom surfaces of the second lower pads222and the third lower pads224. In some embodiments, the second lower pads222may be electrically connected to the third upper pads232, and the third lower pads224may not be electrically connected to the third upper pads232. For example, the second lower pads222may be in contact with the second conductive patterns212, and the third lower pads224may not be in contact with the second conductive patterns212. In some embodiments, top surfaces of the third lower pads224may contact only a bottom surface of the second insulating layer210. The second upper passivation film230and the third upper pads232may be formed on the top surface of the second insulating layer210. The third upper pads232may be electrically connected to the second conductive patterns212. The second upper passivation film230may cover the top surface the second insulating layer210and may expose the third upper pads232. For example, a bottom surface of the second upper passivation film230may contact the top surface of the second insulating layer210. The second lower passivation film220and the second upper passivation film230may include, for example, a photo-imageable dielectric material, but the present disclosure is not limited thereto. The first connecting members170may be interposed between the first substrate100and the interposer200. The first connecting members170may be in contact with the top surface of the first substrate100and the bottom surface of the interposer200. The first connecting members170may electrically connect the first substrate100and the interposer200. For example, the first connecting members170may be in contact with the first upper pads132of the first substrate100and the second lower pads222of the interposer200. Accordingly, the first connecting members170may electrically connect the first conductive patterns112and the second conductive patterns212. A height L11(ofFIG.3) of the first connecting members170may be the same as the distance D21from the top surface of the first substrate100to the bottom surface of the interposer200. Here, the term “height” means maximum length in a vertical direction that is perpendicular to the top surface of the first substrate100. In some embodiments, the height L11of the first connecting members170may be about 120 μm to about 200 μm. In some embodiments, a width W11of the first connecting members170may be about 120 μm to about 200 μm. Here, the term “width” means maximum length in a horizontal direction that is parallel to the top surface of the first substrate100(e.g., a first direction X or a second direction Y). The first connecting members170may have, for example, a spherical or elliptical spherical shape, but the present disclosure is not limited thereto. The first connecting members170may include, for example, Sn, In, Bi, Sb, Cu, Ag, Zn, Pb, or a combination thereof, but the present disclosure is not limited thereto. The supporting members180may be spaced apart from the first connecting members170in the first direction X and/or the second direction Y, and may be interposed between the first substrate100and the interposer200. The supporting members180may be in contact with the top surface of the first substrate100and the bottom surface of the interposer200. In some embodiments, the supporting members180may be dummy connecting members that do not electrically connect the first substrate100and the interposer200. For example, the supporting members180may be in contact with the second upper pads134of the first substrate100and the third lower pads224of the interposer200. Accordingly, the supporting members180may not electrically connect the first conductive patterns112and the second conductive patterns212. The supporting members180may include solder parts184and core parts182in the solder parts184. The solder parts184may surround the core parts182. The core parts182may include a different material from the solder parts184. The core parts182may have, for example, a spherical or elliptical spherical shape, but the present disclosure is not limited thereto. The solder parts184may include, for example, Sn, In, Bi, Sb, Cu, Ag, Zn, Pb, or a combination thereof, but the present disclosure is not limited thereto. The supporting members180, which include the core parts182, may support the interposer200so that the interposer200may maintain a predetermined distance (e.g., the distance D21or D22) from the first substrate100(or from the first semiconductor chip150) while being bonded onto the first substrate100. This will be described later with reference toFIG.18. The core parts182may be formed to be smaller than the first connecting members170. For example, as illustrated inFIG.3, a height L12of the core parts182may be smaller than the height L11of the first connecting members170. In some embodiments, the height L12of the core parts182may be 75% to 90% of the height L11of the first connecting members170. In a case where the height L12of the core parts182is 75% or greater of the height L11of the first connecting members170, the supporting members180may support the interposer200so that the interposer200may maintain a predetermined distance from the first substrate100(or from the first semiconductor chip150) while being bonded onto the first substrate100. In a case where the height L12of the core parts182is less than 90% of the height L11of the first connecting members170, the supporting members180secures a space for the solder parts184, so that the non-wet defect of the supporting members180can be prevented during the bonding of the interposer200on the first substrate100. In some embodiments, the height L12of the core parts182may be about 90 μm to about 180 μm. In some embodiments, the solder parts184may completely surround the core parts182. For example, the core parts182may not be in contact with the first substrate100and the interposer200due to the presence of the solder parts184. In some embodiments, a width W13of the core parts182may be smaller than a width W12of the solder parts184. In some embodiments, the width W13of the core parts182may be 75% to 90% of the width W12of the solder parts184. In some embodiments, the width W13of the core parts182may be about 90 μm to about 180 μm. In some embodiments, the width W13of the core parts182may be smaller than the width W11of the first connecting members170. In some embodiments, the solder parts184may have a first melting point, and the core parts182may have a second melting point, which is higher than the first melting point. Accordingly, the core parts182can support the interposer200so that the interposer200can maintain a predetermined distance (e.g., the distance D21or D22) from the first substrate100(or from the first semiconductor chip150) while the solder parts184are becoming wet and being attached to the first substrate100and the interposer200in the process of bonding the interposer200on the first substrate100. In some embodiments, the solder parts184may include the same material as the first connecting members170. For example, the solder parts184of the supporting members180and the first connecting members170may be formed on the same level. The expression “two elements being formed on the same level”, as used herein, means that the two elements are formed by the same process and at the same time. In this case, the first connecting members170may have the first melting point. In some embodiments, the supporting members180may be disposed closer than the first connecting members170to the first semiconductor chip150. As the supporting members180are disposed close to the first semiconductor chip150, the distance (e.g., the distance D22) between the first semiconductor chip150and the interposer200can be efficiency maintained in the process of bonding the interposer200on the first substrate100. Referring toFIG.4, the first upper passivation film130may cover parts of the first upper pads132and parts of the second upper pads134. For example, the first upper passivation film130may include first trenches130t1, which expose parts of the first upper pads132, and second trenches130t2, which expose parts of the second upper pads134. In some embodiments, the lower parts of the first connecting members170may be formed in the first trenches130t1to be connected to the first upper pads132. For example, the lower parts of the first connecting members170may contact side surfaces of the first upper passivation film130in the first trenches130t1. In some embodiments, the lower parts of the supporting members180may be formed in the second trenches130t2to be connected to the second upper pads134. For example, the lower parts of the supporting members180may contact side surfaces of the first upper passivation film130in the second trenches130t2. The second lower passivation film220may cover parts of the second lower pads222and parts of the third lower pads224. For example, the second lower passivation film220may include third trenches220t1, which expose parts of the second lower pads222, and fourth trenches220t2, which expose parts of the third lower pads224. In some embodiments, the upper parts of the first connecting members170may be formed in the third trenches220t1to be connected to the second lower pads222. For example, the upper parts of the first connecting members170may side surfaces of the second lower passivation film220in the third trenches220t1. In some embodiments, the upper parts of the supporting members180may be formed in the fourth trenches220t2to be connected to the third lower pads224. For example, the upper parts of the supporting members180may contact side surfaces of the second lower passivation film220in the fourth trenches220t2. As illustrated inFIG.1, a plurality of first connecting members170and a plurality of supporting members180may be formed between the first substrate100and the interposer200. In some embodiments, the first connecting members170and the supporting members180may be arranged at regular intervals of a predetermined distance. For example, a distance D1lin the second direction Y between the plurality of first connecting members170may be the same as a distance D12in the second direction Y between the plurality of supporting members180. In some embodiments, distances in the second direction Y between a supporting member180and an adjacent first connecting member170may be the same as the distance D1lor the distance D12. In some embodiments, distances in the first direction X between a supporting member180and an adjacent first connecting member170may be the same as the distance D11or the distance D12. In some embodiments, a plurality of supporting members180may be arranged along at least one side of the first semiconductor chip150. For example, as illustrated inFIG.1, the plurality of supporting members180may form first and second groups G1and G2disposed on sides of the first semiconductor chip150. For example, the first semiconductor chip150may have a first side surface, which intersects a first direction X, and a second side surface, which is opposite to the first side surface. The first group G1may include a plurality of first supporting members180a, which are arranged along the first side surface. For example, the plurality of first supporting members180amay be arranged along a second direction Y, which intersects the first direction X. The second group G2may include a plurality of second supporting members180b, which are arranged along the second side surface. For example, the plurality of second supporting members180bmay be arranged along the second direction Y. Referring again toFIG.2, in some embodiments, a first molding film190may be formed on the first substrate100. The first molding film190may fill the gap between the first substrate100and the interposer200. Accordingly, the first molding film190may cover and protect the first substrate100, the first semiconductor chip150, the first bumps160, the first connecting members170, and the supporting members180. The first molding film190may contact surfaces of the first substrate100, the first semiconductor chip150, the first bumps160, the first connecting members170, and the supporting members180. The first connecting members170and the supporting members180may penetrate the first molding film190to electrically connect the first substrate100and the interposer200. The first molding film190may include, for example, an insulating polymer material such as an epoxy molding compound (EMC), but the present disclosure is not limited thereto. In some embodiments, an underfill152may be formed on the first substrate100. The underfill152may fill the gap between the first substrate100and the first semiconductor chip150. The underfill152may fix the first semiconductor chip150on the first substrate100and may thus prevent the first semiconductor chip150from being broken. The underfill152may cover the first bumps160. The underfill152may surround and contact the first bumps160. The first bumps160may penetrate the underfill152to electrically connect the first substrate100and the first semiconductor chip150. The underfill152may include, for example, an insulating polymer material such as an EMC, but the present disclosure is not limited thereto. In some embodiments, the underfill152may include a different material from the first molding film190. For example, the underfill152may include an insulating material with greater fluidity than the first molding film190. Accordingly, the underfill152may efficiently fill a narrow space between the first substrate100and the first semiconductor chip150. The second substrate300may be disposed on the top surface of the interposer200. The second substrate300may be a substrate for a package. For example, the second substrate300may be a PCB or a ceramic substrate. Also, the second substrate300may be a substrate for a WLP. The second substrate300may have bottom and top surfaces that are opposite to each other. For example, the bottom surface of the second substrate300may face the top surface of the interposer200. The second substrate300may include a third insulating layer310, a third lower passivation film320, fourth lower pads322, a third upper passivation film330, and fourth upper pads332. The third insulating layer310and conductive patterns (not illustrated) in the third insulating layer310may form wiring patterns for electrically connecting the fourth lower pads322and the fourth upper pads332. The third insulating layer310is illustrated as having a single-layer structure, but the present disclosure is not limited thereto. For example, the third insulating layer310may be formed to have a multilayer structure to form multilayer conductive patterns. The third lower passivation film320and the fourth lower pads322may be formed on the bottom surface of the third insulating layer310. The third lower passivation film320may cover the bottom surface of the third insulating layer310and may expose the fourth lower pads322. In some embodiments, top surfaces of the third lower passivation film320and the fourth lower pads322may be coplanar with one another, and bottom surfaces of the third lower passivation film320and the fourth lower pads322may be coplanar with one another. The third upper passivation film330and the fourth upper pads332may be formed on the top surface of the third insulating layer310. The third upper passivation film330may cover the top surface of the third insulating layer310and may expose the fourth upper pads332. In some embodiments, top surfaces of the third upper passivation film330and the fourth upper pads332may be coplanar with one another, and bottom surfaces of the third upper passivation film330and the fourth upper pads332may be coplanar with one another. The third lower passivation film320and the third upper passivation film330may include, for example, a PID material, but the present disclosure is not limited thereto. The second connecting members280may be interposed between the interposer200and the second substrate300. The second connecting members280may be in contact with the top surface of the interposer200and the bottom surface of the second substrate300. The second connecting members280may electrically connect the interposer200and the second substrate300. For example, the second connecting members280may be in contact with the third upper pads232of the interposer200and the fourth lower pads322of the second substrate300. The second connecting members280may have, for example, a spherical or elliptical spherical shape, but the present disclosure is not limited thereto. The second connecting members280may include, for example, Sn, In, Bi, Sb, Cu, Ag, Zn, Pb, or a combination thereof, but the present disclosure is not limited thereto. The second semiconductor chip350may be disposed on the second substrate300. For example, the second semiconductor chip350may be mounted on the top surface of the second substrate300. The second semiconductor chip350may be an IC into which hundreds to millions of semiconductor elements are integrated. In some embodiments, the first semiconductor chip150may be a logic chip, as an AP, etc., and the second semiconductor chip350may be a memory chip such as a volatile memory (e.g., a DRAM) or a nonvolatile memory (e.g., a ROM or a flash memory). FIGS.1through4illustrate that only one second semiconductor chip350is formed on the second substrate300, but the present disclosure is not limited thereto. For example, the plurality of second semiconductor chips350may be formed side-by-side on the second substrate300or may be sequentially stacked on the second substrate300. In some embodiments, the second semiconductor chip350may be mounted on the second substrate300via flip-chip bonding. For example, second bumps360may be formed between the top surface of the second substrate300and the bottom surface of the second semiconductor chip350. The second bumps360may electrically connect the second substrate300and the second semiconductor chip350. For example, the second bumps360may contact the fourth upper pads332. The second bumps360may include, for example, second pillar layers362and second solder layers364. The second pillar layers362and the second solder layers364may be similar to the first pillar layers162and the first solder layers164, respectively, but detailed descriptions thereof will be omitted. In some embodiments, a second molding film390may be formed on the second substrate300. The second molding film390may cover and protect the second substrate300, the second semiconductor chip350, and the second bumps360. The second molding film390may include, for example, an insulating polymer material such as an EMC, but the present disclosure is not limited thereto. FIG.5is a cross-sectional view of a semiconductor package, according to some example embodiments of the present disclosure. For convenience, the semiconductor package ofFIG.5will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIG.5, supporting members180may be in contact with a first upper passivation film130and/or a second lower passivation film220. FIG.5illustrates that the supporting members180are in contact with both the first upper passivation film130and the second lower passivation film220, but the present disclosure is not limited thereto. Alternatively, the supporting members180may be in contact with only one of the first upper passivation film130and the second lower passivation film220. For example, the lower parts of the supporting members180may be in contact with the first upper passivation film130, and the upper parts of the supporting members180may be in contact with third lower pads224(ofFIG.2). For example, the lower parts of the supporting members180may be in contact with second upper pads134(ofFIG.2), and the upper parts of the supporting members180may be in contact with the second lower passivation film220. The supporting members180may be dummy connecting members that are in contact with the first upper passivation film130and/or the second lower passivation film220and do not electrically connect the first substrate100and the interposer200. FIG.6is a cross-sectional view of a semiconductor package, according to some example embodiments of the present disclosure.FIGS.7and8are perspective views of a core part ofFIG.6. For convenience, the semiconductor package ofFIGS.6through8will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIGS.6through8, core parts182of supporting members180may be pillar-shaped. In some embodiments, the axes of the core parts182, which are pillar-shaped, may extend to intersect the top surface of a first substrate100. For example, as illustrated inFIG.7, the core parts182may have a cylindrical shape whose axis intersects the top surface of the first substrate100at a substantially right angle. For example, as illustrated inFIG.8, the core parts182may have a polygonal pillar shape whose axis intersects the top surface of the first substrate100at a substantially right angle. FIG.9is a cross-sectional view of a semiconductor package, according to some example embodiments of the present disclosure. For convenience, the semiconductor package ofFIG.9will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIG.9, the semiconductor package may further include a third molding film154. The third molding film154may cover the top surface of a first substrate100and side surfaces of a first semiconductor chip150. In some embodiments, a top surface of the third molding film154may be coplanar with the top surface of the first semiconductor chip150. The third molding film154may be formed between the first semiconductor chip150, first connecting members170, and supporting members180. For example, the third molding film154may cover the top surface of the first substrate100and may include fifth trenches154t, which expose first upper pads132and second upper pads134. The first connecting members170and the supporting members180may be formed in the fifth trenches154tand may be connected to the first upper pads132and the second upper pads134, respectively. In some embodiments, the top surface of the third molding film154may be spaced apart from the bottom surface of an interposer200. Accordingly, a first molding film190may fill the gap between the third molding film154and the interposer200. The third molding film154may include, for example, an insulating polymer material such as an EMC, but the present disclosure is not limited thereto. In some embodiments, the third molding film154may include a different material from the first molding film190. For example, the first molding film190may include an insulating material with greater fluidity than the third molding film154. Accordingly, the first molding film190may efficiently fill a narrow space between the first semiconductor chip150and the interposer200. FIG.10is a cross-sectional view of a semiconductor package, according to some example embodiments of the present disclosure. For convenience, the semiconductor package ofFIG.10will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIG.10, an interposer200may further include protruding patches220P. For example, the protruding patches220P may protrude from a second lower passivation film220in the direction of a first semiconductor chip150to face the top surface of the first semiconductor chip150. A plurality of protruding patches220P may be formed to support the interposer200from above the first semiconductor chip150. FIG.10illustrates that all the protruding patches220P are in contact with the top surface of the first semiconductor chip150, but the present disclosure is not limited thereto. For example, at least some of the protruding patches220P may be spaced apart from the top surface of the first semiconductor chip150depending on the size of first connecting members170or supporting members180. FIG.11is a cross-sectional view of a semiconductor package, according to some example embodiments of the present disclosure. For convenience, the semiconductor package ofFIG.11will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIG.11, a second semiconductor chip350may be mounted on a second substrate300by a method other than flip-chip bonding. For example, the second semiconductor chip350may be mounted on the second substrate300by a first adhesive layer352. The first adhesive layer352may attach the bottom surface of the second semiconductor chip350on the top surface of the second substrate300via adhesion means. The first adhesive layer352may include, for example, at least one of liquid epoxy, an adhesive tape, a conductive medium, and a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second semiconductor chip350may be electrically connected to the second substrate300via first bonding wires374. For example, the first bonding wires374may connect first chip pads372of the second semiconductor chip350and fourth upper pads332of the second substrate300, but the present disclosure is not limited thereto. For example, the second semiconductor chip350may be electrically connected to fourth upper pads332via, for example, a bonding tape. In some embodiments, a plurality of semiconductor chips may be stacked on the second substrate300. For example, a third semiconductor chip450may be stacked on the second semiconductor chip350. For example, the third semiconductor chip450may be disposed on the second semiconductor chip350via a second adhesive layer452. The second adhesive layer452may attach the bottom surface of the third semiconductor chip450and the top surface of the second semiconductor chip350via adhesion means. In some embodiments, the third semiconductor chip450may be electrically connected to the second substrate300via second bonding wires474. For example, the second bonding wires474may connect second chip pads472of the third semiconductor chip450and the fourth upper pads332of the second substrate300. FIGS.12through16are layout views of a semiconductor package, according to some example embodiments of the present disclosure. For convenience, the semiconductor package ofFIGS.12through16will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIG.12, a plurality of supporting members180may further form third and fourth groups G3and G4, which are disposed on sides of a first semiconductor chip150. The third group G3may be adjacent to a first group G1in a first direction X. The third group G3may include a plurality of third supporting members180c, which are arranged side-by-side with the first group G1. For example, the plurality of third supporting members180cmay be arranged side-by-side with a plurality of first supporting members180ain a second direction Y. In some embodiments, distances in the first direction X between a supporting member180of the first group G1and an adjacent supporting member180of the third group G3may be the same as the distance D1lor the distance D12. The fourth group G4may be adjacent to a second group G2in the first direction X. The fourth group G4may include a plurality of fourth supporting members180d, which are arranged side-by-side with the second group G2. For example, the plurality of fourth supporting members180dmay be arranged side-by-side with a plurality of second supporting members180bin the second direction Y. In some embodiments, distances in the first direction X between a supporting member180of the second group G2and an adjacent supporting member180of the fourth group G4may be the same as the distance D11or the distance D12. Referring toFIG.13, the plurality of supporting members180may further form fifth and sixth groups G5and G6, which are disposed on sides of the first semiconductor chip150. For example, the first semiconductor chip150may have a third side, which is intersects the second direction Y, and a fourth side, which is opposite to the third side. The fifth group G5may include a plurality of fifth supporting members180e, which are arranged along the third side of the first semiconductor chip150. For example, the plurality of fifth supporting members180emay be arranged along the first direction X. The sixth group G6may include a plurality of sixth supporting members180f, which are arranged along the fourth side of the first semiconductor chip150. For example, the plurality of sixth supporting members180fmay be arranged along the first direction X. Since the supporting members180, which include the first, second, fifth and sixth groups G1, G2, G5, and G6, surround the first semiconductor chip150in a plan view, the supporting members180can support an interposer200so that the interposer200can maintain a predetermined distance from a first substrate100(or from the first semiconductor chip150) while being bonded on the first substrate100. Referring toFIG.14, there may exist supporting members180that are adjacent to the corners of the first semiconductor chip150in a plan view. For example, the first semiconductor chip150may have four corners, when viewed in a plan view, and the supporting members180may include seventh through tenth supporting members180gthrough180jthat are adjacent to the four corners of the first semiconductor chip150. For example, each of the seventh through tenth supporting members180gthrough180jmay be provided at a diagonal to a corresponding one of the corners of the first semiconductor chip150. Since the supporting members180, which include the seventh through tenth supporting members180gthrough180j, are located at the corners of the first semiconductor chip150in a plan view, the supporting members180can support the interposer200so that the interposer200can maintain a predetermined distance from the first substrate100(or from the first semiconductor chip150) while being bonded on the first substrate100. Referring toFIG.15, the plurality of supporting members180may be arranged in a zigzag fashion with respect to a plurality of first connecting members170, in a plan view. For example, the first connecting members170and the supporting members180may be alternately arranged along the first direction X. Also, the first connecting members170and the supporting members180may be alternately arranged along the second direction Y. Since the supporting members180are arranged in a zigzag fashion with respect to the first connecting members170, the supporting members180can evenly support the interposer200while the interposer200is being bonded on the first substrate100. In some embodiments, each of the first connecting members170and the supporting members180may be spaced equidistant in the first and second directions X and Y from adjacent ones of the first connecting members170and the supporting members180. Referring toFIG.16, a distance D11in the second direction Y between the plurality of first connecting members170may differ from a distance D13in the second direction Y between the plurality of supporting members180. For example, the distance D13between the plurality of supporting members180may be greater than the distance D11between the plurality of first connecting members170. Although not specifically illustrated, in another example, the distance D13between the plurality of supporting members180may be smaller than the distance D11between the plurality of first connecting members170. FIG.17is a cross-sectional view of a semiconductor package, according to some example embodiments of the present disclosure. For convenience, the semiconductor package ofFIG.17will hereinafter be described, focusing mainly on the differences with the semiconductor package ofFIGS.1through4. Referring toFIG.17, a first semiconductor chip150is not interposed between a first substrate100and an interposer200. For example, the first semiconductor chip150may be mounted on the top surface of the interposer200. In some embodiments, first bumps160may be in contact with third upper pads232of the interposer200. Accordingly, the first semiconductor chip150may be electrically connected to the first substrate100via the interposer200. In some embodiments, a high-bandwidth memory (HBM)500may be mounted on the top surface of the interposer200. For example, the HBM500may include a controller chip510and a plurality of memory chips522,524, and526. The controller chip510may be mounted on the top surface of the interposer200, and the memory chips522,524, and526may be sequentially stacked on the controller chip510. The controller chip510may be a logic chip and each of the plurality of memory chips522,524, and526may be a memory chip. In some embodiments, the HBM500may include third bumps530and through vias540. The third bumps530may be interposed between the controller chip510and the plurality of memory chips522,524, and526. The through vias540may penetrate the controller chip510and at least some of the plurality of memory chips522,524, and526to be connected to the third bumps530. Accordingly, the HBM500may be electrically connected to the first substrate100via the interposer200. In some embodiments, the HBM500may be electrically connected to the first semiconductor chip150via the interposer200. For example, some of second conductive patterns212may connect third upper pads232that are in contact with the first semiconductor chip150to third upper pads232that are in contact with the HBM500. A semiconductor package according to some example embodiments of the present disclosure will hereinafter be described with reference toFIG.18. FIG.18is a schematic diagram for explaining the process of bonding an interposer on a first substrate100. Referring toFIG.18, an interposer200may be bonded on a first substrate100. The bonding of the interposer200on the first substrate100may be performed by, for example, a thermal compression bonding method in which heat is applied to the interposer200while pressing the top surface of the interposer200with the use of bonding equipment1000. Meanwhile, to prevent defects that may be caused by warpage or the like, the interposer200needs to maintain a predetermined distance (e.g., a distance D22) from a first semiconductor chip150. To this end, the interposer200may be equipped with protruding patches220P, but due to the presence of the protruding patches220P, part of the top surface of the interposer200may undesirably protrude in the process of being pressed with the bonding equipment1000. This type of defect leads to deterioration of the product quality of the interposer200. However, since the semiconductor package ofFIG.18includes supporting members180that include core parts182, damage to the interposer200can be prevented. For example, while the interposer200is being bonded on the first substrate100, solder parts184may get wet, and while the supporting members180are being attached to the first substrate100and the interposer200, the core parts182may support the interposer200to maintain a predetermined distance (e.g., a distance D21or the distance D22) from the first substrate100(or a first semiconductor chip150). Accordingly, a semiconductor package with improved product reliability can be provided. In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present inventive concept. Therefore, the disclosed preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation. | 46,690 |
11862571 | DETAILED DESCRIPTION FIG.1illustrates a perspective view of a semiconductor package according to example embodiments.FIG.2Aillustrates a cross-sectional view taken along line I-I′ ofFIG.1.FIG.2Billustrates a cross-sectional view of a semiconductor package according to example embodiments.FIGS.3A,3B, and3Cillustrate enlarged views of portion ‘P1’ ofFIG.2A.FIG.4illustrates an enlarged view of portion ‘P2’ ofFIG.3A. Referring toFIGS.1and2A, a semiconductor package100according to example embodiment may include a semiconductor chip10. The semiconductor chip10may include, e.g., a system large scale integration (LSI), a logic circuit, an image sensor, such as CMOS image sensor (CIS), a memory device, such as a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, an ReRAM, a high bandwidth memory (HBM), or a hybrid memory cubic (HMC), or a microelectromechanical system (MEMS). As used herein, the term “or” is not an exclusive term, e.g., “A or B” could include A, B, or A and B. Referring toFIG.2A, a chip protection layer14may cover a (e.g., lower) surface of the semiconductor chip10. The chip protection layer14may be formed of an insulating material, e.g., silicon nitride or polyimide. Chip conductive patterns12spaced apart from each other may be between the lower surface of the semiconductor chip10and the chip protection layer14. The chip conductive patterns12may include, e.g., aluminum, copper, gold, tin, or titanium nitride. Each of the chip conductive patterns12may be formed of a single layer or multiple layers. External connection terminals16may pass through the chip protection layer14to be connected to the chip conductive patterns12, respectively. The external connection terminals16may each include, e.g., a conductive bump, a conductive pillar, a solder layer, or a solder ball. Referring toFIGS.1and2A, a capping insulation layer20may cover a surface (e.g., an upper surface that is opposite to the lower surface) and a sidewall (e.g., four sidewalls) of the semiconductor chip10. For example, the capping insulation layer20may cover five surfaces of the semiconductor chip10. A shielding layer30may be on the capping insulation layer20. The shielding layer30may cover an upper surface and a sidewall or sidewalls of the capping insulation layer20. The semiconductor package100may be a kind of fan-in wafer-level package. Referring toFIGS.3A and4, the capping insulation layer20may include a laterally protruding capping protrusion20pcovering (or contacting, e.g., directly contacting) a lower surface of the shielding layer30. The lower surface of the capping insulation layer20may be coplanar with a lower surface of the chip protection layer14. The capping insulation layer20may have a first capping sidewall20s1over the capping protrusion20pand a second capping sidewall20s2below the first capping sidewall20s1. The second capping sidewall20s2may correspond to or be a sidewall of the capping protrusion20p. A surface roughness of the second capping sidewall20s2may be greater than a surface roughness of the first capping sidewall20s1. A lower portion of the shielding layer30may be closed or covered by the capping protrusion20p, and when the semiconductor package100is mounted on a board substrate, undesirable contact between the shielding layer30and an adjacent conductive pattern may be blocked. The capping insulation layer20may have a thickness of, e.g., about 1 μm to about 20 μm. The capping insulation layer20may include an inorganic layer, e.g., aluminum oxide layer, or silicon oxide layer, or a polymer-containing layer, e.g., epoxy or polyurethane, and may have a single or multilayered structure. When the capping insulation layer20is formed of an inorganic layer, e.g. aluminum oxide layer or a silicon oxide layer, the capping insulation layer20may be formed by a deposition process, e.g., a sputtering process, a physical vapor deposition (PVD), a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. For example, when the capping insulation layer20is formed by an ALD process, the capping insulation layer20may be conformally formed to have a uniform thickness regardless of locations. In addition, when the capping insulation layer20is formed of a polymer-containing layer, the capping insulation layer20may be formed by a spray dry process. In an implementation, referring toFIG.4, the capping insulation layer20may include a polymer-containing layer20aand insulating particles20bdispersed in the polymer-containing layer20a. The polymer-containing layer20amay include, e.g., epoxy or polyurethane, and the insulating particles20bmay include and inorganic material, e.g., silicon oxide or aluminum oxide. The insulating particles20bmay be distributed in contact with each other in the polymer-containing layer20a. The insulating particles20bmay be distributed in contact with each other, and the heat dissipation effect may be increased. The silicon oxide layer or the aluminum oxide layer may have an insulation property and a relatively excellent heat conductivity. For example, when the capping insulation layer20is formed of silicon oxide or aluminum oxide or the insulating particles20bare formed of silicon oxide or aluminum oxide, the heat dissipation effect may be increased. In an implementation, referring again toFIG.3A, the shielding layer30may have a thickness of, e.g., about 1 μm to about 10 μm. The shielding layer30may include a single or multilayered structure and may include metal, e.g., stainless steel (SUS), copper, or nickel. The shielding layer30may be formed by a deposition process, e.g., a sputtering process, a PVD process, a CVD process, or an ALD process. The shielding layer30may have a first shielding sidewall30s1adjacent to or roughly aligned with the sidewall of the semiconductor chip10and a second shielding sidewall30s2adjacent to or roughly aligned with a sidewall of the chip protection layer14and below the first shielding sidewall30s1. A surface roughness of the second shielding sidewall30s2may be greater than a surface roughness of the first shielding sidewall30s1. The second shielding sidewall30s2may be vertically aligned with the second capping sidewall20s2. In an implementation, referring toFIG.3B, a lower portion of the shielding layer30may laterally protrude. For example, the shielding layer30may include a laterally protruding shielding protrusion30p. The second shielding sidewall30s2of the shielding layer30may correspond to or be a sidewall of the shielding protrusion30p. In an implementation, referring toFIG.3C, the shielding layer30may include a double layer of a first shielding layer30aand a second shielding layer30b. The first shielding layer30amay include metal that is different from a metal of the second shielding layer30b. The first shielding layer30amay include a laterally protruding first shielding protrusion30ap. In an implementation, the shielding layer30may have a triple or more layered structure. The shielding layer30of the double or multilayered structure may help increase an electromagnetic interference (EMI) shielding effect. In an implementation, referring toFIG.2B, a semiconductor package100amay include an edge chip conductive pattern12pon an edge (e.g., outer side) of the lower surface of the semiconductor chip10. A sidewall of the edge chip conductive pattern12pmay be vertically aligned with the sidewall of the semiconductor chip10and the sidewall of the chip protection layer14. The edge chip conductive pattern12pmay be insulated from the shielding layer30by the capping insulation layer20. The other components of the semiconductor package100aexcept the edge chip conductive pattern12pmay be the same or similar as described with reference toFIGS.3A to3C and4. Referring toFIGS.2A and2B, the semiconductor packages100and100amay have the upper surfaces and the sidewalls protected by the capping insulation layer20. The semiconductor package100and100amay have the EMI shielding function by the shielding layer30. The shielding layer30may be spaced apart from the edge chip conductive pattern12pby the capping insulation layer20, and a design freedom of the chip conductive patterns12and12pmay be increased. In an implementation, the capping insulation layer20may include, e.g., the aluminum oxide layer and/or the silicon oxide layer, and the heat dissipation effect may be increased. The capping insulation layer20may include the capping protrusion20pcontacting the lower surface of the shielding layer30, and when the semiconductor packages100and100aare mounted on the board substrate, the semiconductor packages100and100amay be prevented from shorting with the adjacent conductive pattern. For example, a poor mounting may be prevented, and a semiconductor package with improved reliability and durability may be provided. FIGS.5A,5B, and5Cillustrate cross-sectional views of stages in a method of manufacturing a semiconductor package having a cross section ofFIG.2Aaccording to example embodiments. Referring toFIG.5A, a preliminary semiconductor package100pmay be manufactured. The preliminary semiconductor package100pmay have a structure excluding or without the capping insulation layer20and the shielding layer30in the semiconductor package100ofFIG.2A. The preliminary semiconductor package100pmay be formed by a manufacturing method of the fan-in wafer level package. A carrier substrate50may be prepared. The carrier substrate50may include an accommodating part51. In an implementation, as illustrated inFIG.5A, one accommodating part51may be included. In an implementation, a plurality of accommodating parts51may be arranged in the carrier substrate50. The preliminary semiconductor package100pmay be located on the carrier substrate50. At that time, the external connection terminals16attached to a lower surface of the semiconductor chip10may be inserted into the accommodating part51and an edge of the chip protection layer14may contact the carrier substrate50. Referring toFIG.5B, the capping insulation layer20may be formed to cover an upper surface and sidewalls of the semiconductor chip10. The capping insulation layer20may be continuously formed on an upper surface of the carrier substrate50. The capping insulation layer20may be formed of an inorganic layer by performing a deposition process, e.g., a sputtering process, a PVD process, a CVD process, or an ALD process. In an implementation, the capping insulation layer20may be formed of a polymer-containing layer by a spray dry process. The shielding layer30may be formed on the capping insulation layer20. The shielding layer30may be formed of a metal layer, e.g., SUS, copper, or nickel, by performing a deposition process, e.g., a sputtering process, a PVD process, a CVD process, or an ALD process. The shielding layer30may be formed on the upper surface of the carrier substrate50as well as the upper surface and the sidewalls of the semiconductor chip10(e.g., on the capping insulation layer20). Referring toFIG.5C, the semiconductor chip10may be lifted from the carrier substrate50. For example, the capping insulation layer20and the shielding layer30on the semiconductor chip10may be separated from the capping insulation layer20and the shielding layer30on the carrier substrate50. The capping insulation layer20and the shielding layer30adjacent to a lower surface of the semiconductor chip10may laterally protrude similar to those shown inFIG.3B. In an implementation, the protrusions (the capping protrusion20pofFIG.3Band the shielding protrusion30pofFIG.3B) may be polished, removing at least a portion of the protrusions. For example, the shielding protrusion30pmay be removed as shown inFIG.3A, and a size of the capping protrusion20pmay be reduced. In an implementation, as shown inFIG.3AorFIG.3B, the surface roughness of the second capping sidewall20s2of the capping insulation layer20and the surface roughness of the second shielding sidewall30s2of the shielding layer30may be relatively increased. A resulting structure may become the structure shown inFIG.3AorFIG.3Bdepending on a polishing/removal amount of the shielding protrusion30pand/or the capping protrusion20p. In an implementation, before the semiconductor chip10is lifted from the carrier substrate50, the capping insulation layer20and the shielding layer30may be cut off using a laser or a drill. The semiconductor package100ofFIG.2Amay be manufactured through such processes. FIG.6illustrates a cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.6, a semiconductor package101may be an example of a fan-out wafer level package. For example, the semiconductor package101may have a chip-first or mold-first fan-out wafer-level package structure. The semiconductor package101may further include a redistribution layer40electrically connected to the semiconductor chip10. Redistribution patterns41may be in the redistribution layer40. Some of the redistribution patterns41may pass through the chip protection layer14to contact the chip conductive pattern12of the semiconductor chip10. The redistribution patterns41may electrically connect the chip conductive pattern12of the semiconductor chip10and the external connection terminal16. The redistribution patterns41may include metal, e.g., copper or aluminum. The redistribution layer40may protrude outwardly from and below the sidewall of the semiconductor chip10. A mold layer18may cover the redistribution layer40and the semiconductor chip10. A lower surface (e.g., redistribution layer-facing surface) of the mold layer18may be coplanar with a lower surface of the chip protection layer14. The mold layer18may include an insulating resin, e.g., an epoxy molding compound (EMC). The mold layer18may further include fillers. The fillers may be dispersed in the insulating resin. The fillers may include, e.g., silicon oxide. An upper surface and a sidewall of the mold layer18and a sidewall of the redistribution layer40may be covered by the capping insulation layer20. An upper surface and a sidewall of the capping insulation layer20may be covered by the shielding layer30. A lower portion of the capping insulation layer20may laterally protrude and may contact a lower surface of the shielding layer30. Detailed structures of the capping insulation layer20and the shielding layer30may be the same or similar as described with reference toFIGS.3A to3C and4. In an implementation, in the semiconductor package101, one semiconductor chip10may be on the redistribution layer40. In an implementation, two or more semiconductor chips10may be side by side on the redistribution layer40. The semiconductor package101may be manufactured as follows. The semiconductor chip10may be on an extra carrier substrate and then the mold layer18may be formed to cover the semiconductor chip10. After the semiconductor chip10and the mold layer18are separated from the extra carrier substrate, the redistribution layer40may be formed on a lower surface of the semiconductor chip10and the lower surface of the mold layer18to manufacture a preliminary semiconductor package. The preliminary semiconductor package may be located on the carrier substrate50, instead of the preliminary semiconductor package100pofFIG.5A. Thereafter, the subsequent processes as described with reference toFIGS.5B and5Cmay be performed to form the capping insulation layer20and the shielding layer30. FIG.7illustrates a cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.7, a semiconductor package102may include a package substrate42. The semiconductor chip10may be mounted on the package substrate42by a flip chip bonding method using an internal connector15. The package substrate42may be a printed circuit board (PCB) substrate having a single or multilayered wiring structure. The internal connector15may include, e.g., a conductive bump, a conductive pillar, a solder layer, or a solder ball. The conductive bump and the conductive pillar may include, e.g., copper. The solder layer and the solder ball may include, e.g., tin or lead. A ball land43may be on a lower surface of the package substrate42. The external connection terminal16may be bonded to the ball land43. The package substrate42may protrude outwardly from and below a sidewall of the semiconductor chip10. The mold layer18may cover the sidewall of the semiconductor chip10and an upper surface of the package substrate42. An upper surface of the mold layer18may be coplanar with an upper surface of the semiconductor chip10. The mold layer18may extend to fill a space between the semiconductor chip10and the package substrate42. The capping insulation layer20may contact the upper surface of the semiconductor chip10, the upper surface and a sidewall of the mold layer18, and the sidewall of the package substrate42. An upper surface and a sidewall of the capping insulation layer20may be covered by the shielding layer30. A lower portion of the capping insulation layer20may laterally protrude to contact a lower surface of the shielding layer30. Detailed structures of the capping insulation layer20and the shielding layer30may be the same or similar as described with reference toFIGS.3A to3C and4. In an implementation, in the semiconductor package102, one semiconductor chip10may be on the package substrate42. In an implementation, two or more semiconductor chips10may be disposed side by side or vertically stacked on the package substrate42. The semiconductor package102may be manufactured as follows. After a preliminary semiconductor package of a structure except or not including the capping insulation layer20and the shielding layer30in the structure ofFIG.7is manufactured, the preliminary semiconductor package may be located on the carrier substrate50, instead of the preliminary semiconductor package100pofFIG.5A. Thereafter, the subsequent processes as described with reference toFIGS.5B and5Cmay be performed. FIG.8illustrates a cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.8, a semiconductor package103may be an example of a package on package structure. The semiconductor package103may include a lower semiconductor package LPK and an upper semiconductor package UPK mounted on the lower semiconductor package LPK. The lower semiconductor package LPK may include a lower package substrate42and a lower semiconductor chip10mounted on the lower package substrate42. The lower package substrate42may be a PCB substrate having a single or multilayered wiring structure. The lower semiconductor chip10may be mounted on the lower package substrate42by a flip chip bonding method using the internal connector15. The external connection terminal16may be adhered to the lower package substrate42. The internal connector15and the external connection terminal16may each include, e.g., a conductive bump, a conductive pillar, a solder layer, or a solder ball. A lower mold layer18may cover an upper surface of the lower package substrate42and the lower semiconductor chip10. An upper surface of the lower mold layer18may be coplanar with an upper surface of the lower semiconductor chip10. The upper semiconductor package UPK may include an upper package substrate54and upper semiconductor chips56mounted on the upper package substrate54. The upper semiconductor chips56may be stacked on the upper package substrate54and may be connected to the upper package substrate54by a wiring bonding method. The upper semiconductor chips56and the upper package substrate54may be covered by an upper mold layer58. The lower mold layer18and the upper mold layer58may each include an insulating resin, e.g., an epoxy molding compound (EMC). The lower mold layer18and the upper mold layer58may further include fillers. The fillers may be dispersed in the insulating resin. The fillers may include, e.g., silicon oxide. The upper semiconductor package UPK may be electrically connected to the lower semiconductor package LPK by a package connector52. The package connector52may electrically connect the lower package substrate42and the upper package substrate54. The lower mold layer18may include an opening into which the package connector52is inserted. The package connector52may include, e.g., a conductive bump, a conductive pillar, a solder layer, or a solder bump. The upper package substrate54may be spaced apart from the lower semiconductor chip10and the lower mold layer18. A thermal interface material layer60may be between the upper package substrate54and the lower semiconductor chip10. The thermal interface material layer60may include, e.g., thermal grease or thermal epoxy. In an implementation, the thermal grease or the thermal epoxy may include metal solid particles. The upper semiconductor package UPK and the lower semiconductor package LPK may be covered by the capping insulation layer20. The capping insulation layer20may contact an upper surface and a sidewall of the upper mold layer58, a sidewall of the upper package substrate54, a sidewall of the lower mold layer18, and a sidewall of the lower package substrate42. The capping insulation layer20may extend between the lower mold layer18and the upper package substrate54. The capping insulation layer20may extend to contact a sidewall of the package connector52and the thermal interface material layer60. An upper surface and a sidewall of the capping insulation layer20may be covered by the shielding layer30. A lower portion of the capping insulation layer20may laterally protrude to contact a lower surface of the shielding layer30. Detailed structures of the capping insulation layer20and the shielding layer30may be the same or similar as described with reference toFIGS.3A to3C and4. The semiconductor package103may be manufactured as follows. After a preliminary semiconductor package having a structure except the capping insulation layer20and the shielding layer30in the structure ofFIG.8is manufactured, the preliminary semiconductor package may be located on the carrier substrate50, instead of the preliminary semiconductor package100pofFIG.5A. Thereafter, the subsequent processes as described with reference toFIGS.5B and5Cmay be performed. The capping insulation layer20may be conformally formed by an ALD process. At that time, a source gas for forming the capping insulation layer20may be diffused between the upper semiconductor package UPK and the lower semiconductor package LPK, such that the capping insulation layer20may fill a space between the upper semiconductor package UPK and the lower semiconductor package LPK. FIG.9illustrates a cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.9, a semiconductor package104may be an example of a package on package structure. The semiconductor package104may include the lower semiconductor package LPK and the upper semiconductor package UPK mounted on the lower semiconductor package LPK. The lower semiconductor package LPK may include the redistribution layer40and the semiconductor chip10mounted on the redistribution layer40. A connection substrate70including a cavity72may be on the redistribution layer40. In an implementation, the cavity72may be in a central portion in the connection substrate70, and the connection substrate70may have a rectangular loop shape in plan view. The connection substrate70may include connection wiring structures71and connection insulation layers73. The connection wiring structures71may include conductive via plugs passing through the connection insulation layers73, conductive wiring lines, and conductive pads. The connection insulation layers73may each include a thermoset resin, e.g. epoxy resin, a thermoplastic resin, e.g., polyimide, or a resin having a reinforcing material, e.g., a glass fiber (glass cloth or glass fabric) or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as prepreg, an ajinomoto build-up film (BF), bismaleimide triazine (BT), or a photo imageable dielectric (PLD) resin. The connection wiring structures71may be electrically connected to the redistribution patterns41in the redistribution layer40. The lower semiconductor chip10may be inserted into the cavity72. The lower semiconductor chip10may be spaced apart from an inner sidewall of the cavity72. The lower mold layer18may fill a space between the lower semiconductor chip10and the inner sidewall of the cavity72. The lower mold layer18may contact an upper surface of the redistribution layer40. The lower mold layer18may extend to cover an upper surface of the lower semiconductor chip10. The lower mold layer18may also extend to cover an upper surface of the connection substrate70. A sidewall of the lower mold layer18may be vertically aligned with a sidewall of the connection substrate70and a sidewall of the redistribution layer40. The upper semiconductor package UPK may include the upper package substrate54and the upper semiconductor chip56mounted on the upper package substrate54. The upper semiconductor chip56may be mounted on the upper package substrate54by a flip chip bonding method. The upper mold layer58may cover an upper surface of the upper package substrate54and a sidewall of the upper semiconductor chip56. The upper mold layer58may fill a space between the upper semiconductor chip56and the upper package substrate54. An upper surface of the upper mold layer58may be coplanar with an upper surface of the upper semiconductor chip56. The upper semiconductor package UPK may be spaced apart from the lower semiconductor package LPK. The upper semiconductor package UPK may be electrically connected to the lower semiconductor package LPK by the package connectors52. The package connectors52may electrically connect the connection substrate70and the upper package substrate54. The lower mold layer18may include openings into which the package connectors52are inserted. The package connectors52may each include, e.g., a conductive bump, a conductive pillar, a solder layer, or a solder ball. The upper semiconductor package UPK and the lower semiconductor package LPK may be covered by the capping insulation layer20. The capping insulation layer20may contact the upper surface and the sidewall of the upper mold layer58, an upper surface of the upper semiconductor chip56, a sidewall of the upper package substrate54, the sidewall of the lower mold layer18, the sidewall of the connection substrate70, and the sidewall of the redistribution layer40. The capping insulation layer20may extend between the lower mold layer18and the upper package substrate54. The capping insulation layer20may extend to contact sidewalls of the package connectors52. The capping insulation layer20may have a constant thickness regardless of locations. A first air gap region V1and a second air gap region V2may be present in the capping insulation layer20. The first air gap region V1may be present between the connection substrate70and the upper package substrate54or between the adjacent package connectors52. The second air gap region V2may be present between the lower semiconductor chip10and the upper package substrate54. A recess region R1may be in the capping insulation layer20between an edge of the upper semiconductor package UPK and an edge of the lower semiconductor package LPK. The shielding layer30may cover an upper surface and a sidewall of the capping insulation layer20. The shielding layer30may include a middle shielding protrusion30spfilling the recess region R1. A lower portion of the capping insulation layer20may laterally protrude to contact a lower surface of the shielding layer30. Detailed structures of the capping insulation layer20and the shielding layer30may be the same or similar as described with reference toFIGS.3A to3B and4. The semiconductor package104may be manufactured as follows. After a preliminary semiconductor package having a structure except the capping insulation layer20and the shielding layer30in the structure ofFIG.9is manufactured, the preliminary semiconductor package may be located on the carrier substrate50, instead of the preliminary semiconductor package100pofFIG.5A. Thereafter, the subsequent processes as described with reference toFIGS.5B and5Cmay be performed. The capping insulation layer20may be conformally formed by an ALD process. At that time, a source gas for forming the capping insulation layer20may be diffused between the upper semiconductor package UPK and the lower semiconductor package LPK, such that the capping insulation layer20may be interposed between the upper semiconductor package UPK and the lower semiconductor package LPK. In addition, at that time, the first air gap region V1and the second air gap region V2may be formed. FIG.10illustrates a cross-sectional view of a semiconductor package according to example embodiments.FIG.11illustrates an enlarged view of portion ‘P1’ ofFIG.10. Referring toFIGS.10and11, in a semiconductor package105, the shielding layer30ofFIG.2Amay be omitted. An upper surface and a sidewall of the semiconductor chip10may be covered by only the capping insulation layer20. For example, the capping protrusion20pofFIG.2Amay not be present at a lower portion of the capping insulation layer20. The capping insulation layer20may include the first capping sidewall20s1and a second capping sidewall20s2below the first capping sidewall20s1. A surface roughness of the second capping sidewall20s2may be greater than a surface roughness of the first capping sidewall20s1. Such a structure of the semiconductor package excluding the shielding layer30may be applied to the semiconductor packages101,102,103, and104ofFIGS.6to9. For example, the semiconductor packages101,102,103, and104ofFIGS.6to9may not include the shielding layer30. In this case, the capping insulation layer20may not include the capping protrusion20pofFIG.2Aand a lower structure of the capping insulation layer20may be the same or similar as described with reference toFIG.11. The semiconductor package105may be manufactured by performing the same processes as described with reference toFIG.5A to5Cexcept omitting forming of the shielding layer30ofFIG.5C. FIG.12illustrates a cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.12, a semiconductor package106may have a chip-last or redistribution (RDL)-first fan-out wafer-level package structure. For example, the semiconductor chip10may be on the redistribution layer40. An upper surface and sidewalls of the semiconductor chip10may be sequentially covered by the capping insulation layer20and the shielding layer30. The capping insulation layer20and the shielding layer30may be the same or similar as described with reference toFIGS.1to4. Multilayer redistribution patterns41may be in the redistribution layer40. Some of the redistribution patterns41may electrically connect the external connection terminals16and the internal connectors15contacting the chip conductive patterns12. Each of the internal connectors15may include a conductive pillar15aand a solder layer15bbelow the conductive pillar15a. The conductive pillar15amay include, e.g., copper. The solder layer15bmay include, e.g., tin and/or lead. The structure in which the internal connector15includes the conductive pillar15aand the solder layer15bmay be advantageous in preventing the electrical short, as an interval between the internal connectors15is narrower. The redistribution layer40may extend outwardly from and below a sidewall of the semiconductor chip10. A space between the semiconductor chip10and the redistribution layer40may be filled with an underfill layer17. The underfill layer17may contact the capping insulation layer20, and may be spaced apart from the shielding layer30. The shielding layer30and the redistribution layer40may be covered by the mold layer18. The mold layer18may contact a lower sidewall (e.g., a sidewall of the capping protrusion) of the capping insulation layer20. A lower surface of the mold layer18may be lower than a lower surface of the semiconductor chip10and a lower surface of the chip protection layer14with respect to an upper surface of the redistribution layer40. The mold layer18may contact the underfill layer17. The other components of the semiconductor package106may be the same or similar as described with reference toFIG.6. The semiconductor package106may be manufactured as follows. The semiconductor chip10may be provided to be covered by the capping insulation layer20and the shielding layer30through the processes described with reference toFIGS.5A,5B, and5C. The redistribution layer40may be formed on an extra carrier substrate, and the semiconductor chip10may be mounted on the redistribution layer40. Thereafter, the underfill layer17and the mold layer18may be formed. FIG.13illustrates a cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.13, a semiconductor package107may be an example of a package on package structure. The semiconductor package107may include the lower semiconductor package LPK and the upper semiconductor package UPK mounted on the lower semiconductor package LPK. The lower semiconductor package LPK may have a similar structure as the semiconductor package106ofFIG.12. For example, the lower semiconductor package LPK may include the lower semiconductor chip10mounted on a lower redistribution layer40. The lower redistribution layer40may include lower redistribution patterns41. An upper surface and sidewalls of the lower semiconductor chip10may be covered by the capping insulation layer20and the shielding layer30. The shielding layer30and the lower redistribution layer40may covered by the lower mold layer18. An upper redistribution layer80may be on the lower mold layer18. The upper redistribution layer80may include upper redistribution patterns81. A through-via83may pass through the lower mold layer18to electrically connect the upper redistribution layer80and the lower redistribution layer40. The upper semiconductor package UPK may include the upper package substrate54and the upper semiconductor chip56mounted on the upper package substrate54. The upper semiconductor chip56may be connected to the upper package substrate54by a wire bonding method. The upper semiconductor chip56and the upper package substrate54may be covered by the upper mold layer58. The upper semiconductor package UPK may be electrically connected to the lower semiconductor package LPK by the package connector52. For example, the package connector52may electrically connect the upper redistribution layer80and the upper package substrate54. The upper mold layer58and the lower mold layer18may not be covered by the capping insulation layer20and the shielding layer30, and may be exposed. The other components of the semiconductor package107may be the same or similar as described with reference toFIGS.8and12. By way of summation and review, with development of the electronic industry, various studies have been conducted to improve reliability and durability of the semiconductor package. One or more embodiments may provide a semiconductor package that helps prevent shorting with an adjacent semiconductor package, and thus a poor mounting may be prevented, providing a semiconductor package with improved reliability and durability. Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 37,328 |
11862572 | DETAILED DESCRIPTION OF THE DRAWINGS The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices. The terms “die” and “semiconductor die” are used interchangeably. Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, wirebonds, or other suitable interconnect structures. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components. FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor die or components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106as described above. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm). FIG.1Bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or over the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit. Semiconductor die104may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. Back surface108of semiconductor wafer100may undergo an optional backgrinding operation with a mechanical grinding or etching process to remove a portion of base material102and reduce the thickness of semiconductor wafer100and semiconductor die104. An electrically conductive layer112is formed over active surface110using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers112include one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110. Conductive layer112can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die104, as shown inFIG.1B. Alternatively, conductive layer112can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row disposed a second distance from the edge of the die. Conductive layer112represents the last conductive layer formed over semiconductor die104with contact pads for subsequent electrical interconnect to a larger system. However, there may be one or more intermediate conductive and insulating layers formed between the actual semiconductor devices on active surface110and contact pads112for signal routing. An electrically conductive bump material is deposited over conductive layer112using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer112using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form conductive balls or bumps114. Conductive bumps114are optionally formed over an under-bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. Conductive bumps114can also be compression bonded or thermocompression bonded to conductive layer112. Conductive bumps114represent one type of interconnect structure that can be formed over conductive layer112for electrical connection to a substrate. The interconnect structure can also use bond wires, conductive paste, stud bumps, micro bumps, or other electrical interconnects. InFIG.1c, semiconductor wafer100is singulated through saw street106using a saw blade or laser cutting tool118into individual semiconductor die104. The individual semiconductor die104can be inspected and electrically tested for identification of known-good die (KGD) post-singulation. FIG.2aillustrates a cross-sectional view of an exemplary semiconductor package200being formed with semiconductor die104.FIG.2ashows semiconductor package200in an intermediate formation step wherein a first layer210of the package has been completed. Substrate212includes one or more insulating layers214interleaved with one or more conductive layers216. Insulating layer214is a core insulating board in one embodiment, with conductive layers216patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers216also include conductive vias electrically coupled through insulating layers214for vertical interconnect. Substrate212can include any number of conductive layers216and insulating layers214interleaved over each other. A solder mask or passivation layer can be formed over either side or both sides of substrate212. Openings are formed in the passivation layer to expose contact pads of conductive layer216for subsequent interconnection. Any suitable type of substrate or leadframe is used for substrate212in other embodiments. Typically, first layer210is formed on substrate212as a panel or strip large enough to form several to hundreds or thousands of packages at one time. First layer210can be singulated from the strip once completed, or packages200are singulated into individual packages after completion of all desired layers. Any components desired for the functionality of first layer210are mounted on or disposed over substrate212and electrically connected to conductive layers216using solder, solder paste, bond wires, or another suitable mechanism.FIG.2aillustrates semiconductor die104mounted on substrate212along with discrete electrical components224. Discrete electrical components224can be passive components such as capacitors, resistors, or inductors, active components such as diodes or transistors, or any other desired electrical component. Multiple semiconductor die can be disposed on substrate212. Semiconductor die104can be provided as part of a smaller sub-package rather than a bare die. Any desired electrical component can be mounted on substrate212, such as passive devices, semiconductor die, wafer-level chip-scale packages (WLCSP), or system-in-package (SiP) modules. The mounted components can have EMI shielding layers formed over the individual components in addition to shielding provided as part of forming semiconductor package200. Semiconductor die104is mounted to substrate212by disposing the semiconductor die on the substrate using, e.g., a pick-and-place process or machine, and then reflowing bumps114to physically and electrically connect the bumps to exposed contact pads of conductive layer216. Discrete components224are connected by similar solder bumps or solder paste226. Solder paste226can be printed onto substrate212or discrete components224prior to picking and placing the discrete components onto the substrate. Reflowing solder paste226physically and electrically couples discrete components224to contact pads of conductive layer216. After mounting of semiconductor die104, discrete components224, and any other desired electrical components onto substrate212, the components are encapsulated by encapsulant or molding compound228. Encapsulant228is deposited over substrate212, semiconductor die104, and discrete components224using paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable applicator. Encapsulant228can be polymer composite material, such as epoxy resin, epoxy acrylate, or polymer with or without a filler. Encapsulant228is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. Openings are formed through encapsulant228to expose contact pads of conductive layers216. The openings are filled with a conductive material using any suitable metal deposition technique to form conductive vias230. The openings for conductive vias230can be formed by mechanical drilling, chemical etching, laser drilling, or any other suitable process. The conductive material can be Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive vias230provide vertical interconnect between first layer210and subsequently formed layers of semiconductor package200. In other embodiments, conductive vias230are formed on substrate212as conductive pillars, solder bumps, copper-clad solder bumps (CCSB), PCB units, modular interconnect units, or any other suitable interconnect structure prior to deposition of encapsulant228. When conductive vias230are formed prior to deposition of encapsulant228, the encapsulant undergoes a backgrinding process to expose the conductive vias if necessary. Substrate212and encapsulant228in combination with the enclosed components are a panel of multiple devices connected together, of whichFIG.2ashows only a single one. After encapsulation with encapsulant228, the panel is optionally singulated into the individual devices using a saw blade, laser cutting tool, water cutting tool, or other suitable implement, which exposes side surfaces of the encapsulant and substrate212for each individual unit. The units remain in place for further processing or can be moved to another carrier to allow for additional spacing between units. In other embodiments, no singulation occurs until all or a portion of the desired layers are completed. Forming subsequent layers while the underlying layers remain as a strip or panel of units, rather than individual units, will make molding the subsequent layers easier for some manufacturing processes. In one embodiment, packages200are kept as an unsingulated panel until after a final layer is fully formed but before forming a final shielding layer so that the final shielding layer provides shielding for the side surfaces of all layers. A conductive material is sputtered over first layer210to form a shielding layer246. Shielding layer246is formed using any suitable metal deposition technique, e.g., chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable material. Shielding layer246completely covers exposed surfaces of encapsulant228, substrate212, and conductive vias230. In particular, all four side surfaces and the top surface of encapsulant228are covered by shielding layer246to surround the encapsulated components. All side surfaces of substrate212are covered by shielding layer246. Shielding layer246is typically not formed on the bottom surface of substrate212because the sputtering process deposits metal molecules from above. Shielding layer246is not formed on the top surface of substrate212due to the presence of encapsulant228. In other embodiments, the top surface of substrate212is partially exposed from encapsulant228to allow shielding layer246to contact the top surface. Conductive layer216can be exposed at sides of substrate212to connect shielding layer246to ground through the substrate. Bumps248are formed on the bottom surface of substrate212at any stage in the manufacturing process. Bumps248are similar to and formed in a similar manner to bumps114on semiconductor die104. While one specific package type is shown for first layer210, the first layer can be formed in any suitable package type, such as an embedded wafer-level ball-grid array (eWLB) or a double-sided SiP module where both sides of substrate212have encapsulated components. FIG.2bshows first layer210in a perspective view fully covered by shielding layer246. The positions of conductive vias230under shielding layer246are indicated by dotted lines. Only four conductive vias230are illustrated, but typically many more conductive vias would be formed as needed to transmit power, ground, data, address, clock, and any other desired signal between layers. InFIG.2c, formation of a second layer250is begun by using laser252to pattern shielding layer246into a plurality of contact pads256a, conductive traces256b, and any other desired conductive structures. Laser252can be a diode-pumped solid-state (DPSS) laser, an excimer laser, a CO2laser, or a neodymium (Nd), erbium (Eb), or ytterbium (Yb) doped Yttrium aluminum garnet (YAG) laser. Laser252can emit light in the ultraviolet, visible light, or infrared spectra. Pulsed laser patterning can be performed with a pulse on the order of microseconds (μs), nanoseconds (ns), or femtoseconds (fs). Any other suitable types of laser and patterning processes are used in other embodiments. Any suitable etching means can be used as desired. Laser252selectively removes shielding layer246. The areas where shielding layer246is removed result in encapsulant228being exposed. The areas where shielding layer246is not removed by laser252remain as contact pads256a, conductive traces256b, and any other desired conductive structures. Contact pads256aare distributed as desired for connection to underlying vias230, for subsequent mounting of semiconductor components, and for subsequent interconnect to overlying layers if additional layers are to be formed. For example, arrays of contact pads256aremain for application of flip-chip or surface mount integrated circuits. A contact pad pair is left for mounting of a discrete passive device. Contact pads256aremain on conductive vias230to connect second layer250to the underlying components of first layer210. Conductive traces256bconnect contact pads256ato each other as necessary to implement the desired electrical functionality of package200. In some embodiments, portions of shielding layer246are left to operate as EMI shielding. While only the portion of shielding layer246on the top surface of encapsulant228is illustrated as being patterned, laser252can also be used to pattern the sidewalls of the shielding layer if desired. FIG.2dshows semiconductor die262, eWLB package264, WLCSP266, and discrete capacitor268mounted onto contact pads256a. The mounted components are disposed over first layer210using any suitable process, such as with a pick-and-place machine. Solder bumps or paste reflowed between contact pads of the mounted components262-268and contact pads256aprovide both a mechanical and an electrical coupling. A mold underfill can be deposited between the components and first layer210. Any desired electrical components can be mounted onto shielding layer246as part of second layer250after patterning the shielding layer. The components can be any discrete passive or active device, a bare die, a WLCSP, or a single or double-side molded SiP module. Any of the components optionally have their own shielding layers formed over or within the individual components in addition to shielding formed as part of package200. InFIG.2e, encapsulant270is deposited over mounted components262-268to provide a package body for second layer250. Encapsulant270is similar to encapsulant228, i.e., deposited in a similar process and formed of a similar material. Encapsulant270can be formed using a mold to keep the encapsulant contained over the footprint of the singulated first layer210units. In another embodiment, encapsulant270is deposited between individual first layer210units and then removed. A preformed sheet of encapsulant270can be laminated over a plurality of first layer210units to allow the encapsulant to cover multiple units without flowing down between the units over shielding layer246. The preformed sheet of encapsulant270can be partially cured in advance to allow the encapsulant to envelop devices mounted as part of second layer250without being fully liquid. In embodiments where first layer210remains as an unsingulated panel or strip, liquid encapsulant can be deposited without issues related to encapsulant270flowing between units of the first layer. Conductive vias272are formed through encapsulant270in a similar manner to conductive vias230above. Conductive vias272can be formed directly over conductive vias230or at other locations depending on the desired functionality of package200. Conductive vias272are optional and may not be formed in embodiments where there is no need for additional vertical routing beyond second layer250. Instead of using conductive vias230and272, vertical routing can be provided by patterning the sidewalls of the shielding layers. FIG.2fshows shielding layer276formed over second layer250of package200. Shielding layer276is formed in a similar manner to and of similar materials as shielding layer246. Shielding layer276contacts and fully covers the top surface and all side surfaces of encapsulant270. Shielding layer276physically contacts the exposed top surfaces of conductive vias272, which electrically connect shielding layer276to contact pads256a, conductive traces256b, and the components mounted thereon as part of second layer250. Shielding layer276is also formed over the sides of first layer210where shielding layer246still remains exposed. Therefore, first layer210now includes a double shielding layer of both shielding layer246and shielding layer276completely surrounding the first layer. InFIG.2g, shielding layer276is patterned into any desired conductive structures, again using laser252or another suitable process.FIG.2gshows an array of patch antennae280formed out of shielding layer276over encapsulant270. Any type of micro-strip line or patch antenna can be formed. Any suitable patch shape can be used, such as rectangular, circular, triangular, U-shaped, or E-shaped. In one embodiment, package200is a 5G transceiver and shielding layer276is formed into an antenna suitable for 5G transmissions. Antennae280are electrically coupled to the underlying components of first layer210and second layer250by conductive vias272, conductive traces256b, conductive vias230, and conductive layer216. FIG.2gshows a perspective view of completed package200, whileFIG.2hshows a cross-sectional view. Package200includes two layers of components, first layer210and second layer250. Shielding layer246formed on first layer210is patterned to operate as a redistribution layer for second layer250. Shielding layer276formed on second layer250is patterned to operate as an antenna or to serve any other desired purpose. Utilizing a patterned shielding layer as a redistribution layer or antenna reduces package size, allows a higher density package, improves device performance, and allows a wider variety of part functionality to be integrated into a single package. In some embodiments, shielding layer276is patterned into a plurality of contact pads as with shielding layer246so that a board-to-board (B2B) connector or other components can be mounted onto package200. Patterning shielding layers246and276using laser252provides circuit design flexibility, including formation of redistribution layers and antenna patterns. Any portion of shielding layers246and276can have a connection to ground to have an EMI shielding effect. Each package layer can have its respective shielding layer pattern formed either embossed over or engraved into the top surface of its respective encapsulant.FIGS.3a-3cshow forming a shielding layer embossed, whileFIGS.4a-4dshow forming a shielding layer engraved.FIG.3ashows first layer210after encapsulation. Shielding layer246is applied over flat surfaces of encapsulant228inFIG.3b. InFIG.3c, shielding layer246is patterned with laser252. The remaining portions246a-246dof shielding layer246have a height over the top surface of encapsulant228equivalent to the thickness of the shielding layer. The thickness of portions246a-246dinFIG.3cis exaggerated for illustration. While only four squares are illustrated, any suitable pattern can be formed for any desired purpose. Alternatively, the shielding layer246pattern can be embedded or engraved into the top surface of encapsulant228rather than embossed over.FIG.4aagain shows first layer210after encapsulation but before formation of a shielding layer. InFIG.4b, the desired pattern for shielding layer246is first etched into encapsulant228. The etching can be any suitable etching process, such as chemical etching, laser etching, or mechanical etching. Etching forms cavities290into the top surface of encapsulant228corresponding to the contact pads, conductive traces, and other structures desired for the final patterned form of shielding layer246. InFIG.4c, shielding layer246is formed over encapsulant228and cavities290. Shielding layer246is formed as a conformal coating that conforms to the shape of cavities290in one embodiment. In another embodiment, shielding layer246completely fills cavities290. InFIG.4d, shielding layer246is removed from the remaining top surface of encapsulant228outside of cavities290. Shielding layer246is removed using laser patterning with laser252in one embodiment. A two-step process can be used by first hatching and then peeling shielding layer246. In other embodiments, the desired portions of shielding layer246can be removed by mechanically grinding the top of first layer210. Shielding layer246remains conformally coated over the side and bottom surfaces within cavities290. In some embodiments, shielding layer246remains completely filling cavities290. Any of the shielding layers disclosed herein for any package layer can have its patterning done either embossed or engraved. FIGS.5aand5bshow a process whereby the redistribution layers are formed by printing instead of laser etching.FIG.5ashows first layer210with encapsulant228deposited but without shielding layer246. Instead of forming shielding layer246over the entire package and then patterning the shielding layer into the desired electrical structures, a redistribution layer is simply printed on the top surface of encapsulant228.FIG.5bshows an inkjet or electrohydrodynamic (EHD) jet nozzle300depositing conductive material over encapsulant228to print the desired circuit pattern302. Circuit printing allows a finer line width compared to laser etching, while still being able to form any of the same conductive structures. In one embodiment, hole formation for conductive vias230is done using laser252, and then the holes are filled by inkjet nozzle300. Any package layer can be formed as shown inFIG.5b, including the top layer. FIG.6shows stacking additional layers indefinitely to any suitable number of layers. While the embodiments above show only two layers210and250, additional layers can continue being formed indefinitely. Shielding layer276is patterned to accommodate any desired electrical components for the third layer, followed by being encapsulated, shielded, and then having the shielding layer patterned. The process of patterning, component mounting, molding or partial molding, and then metal deposition or EMI shielding can be repeated indefinitely until the desired top layer310is formed. Top layer310can have antennae or terminals for a B2B connector formed thereon. FIGS.7aand7billustrate incorporating the above-described packages, e.g., package200with first layer210and second layer250, into an electronic device400.FIG.7aillustrates a partial cross-section of package200mounted onto a printed circuit board (PCB) or other substrate402as part of electronic device400. Bumps248are formed on conductive layer216on the bottom of substrate212. Conductive bumps248can be formed at any stage of the manufacturing process, e.g., prior to molding encapsulant228, prior to singulation, or after forming and patterning shielding layer276. Bumps248are reflowed onto conductive layer404of PCB402to physically attach and electrically connect package200to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between package200and PCB402. Semiconductor die104is electrically coupled to conductive layer404through substrate212and bumps248. FIG.7billustrates electronic device400with a plurality of semiconductor packages mounted on a surface of PCB402, including package200. Electronic device400can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device400can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device400can be a subcomponent of a larger system. For example, electronic device400can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device400can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, and other semiconductor die or electrical components. InFIG.7b, PCB402provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces404are formed over a surface or within layers of PCB402using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces404provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces404also provide power and ground connections to the semiconductor packages as needed. In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB402. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB402. For the purpose of illustration, several types of first level packaging, including bond wire package406and flipchip408, are shown on PCB402. Additionally, several types of second level packaging, including ball grid array (BGA)410, bump chip carrier (BCC)412, land grid array (LGA)416, multi-chip module (MCM)418, quad flat non-leaded package (QFN)420, quad flat package422, and eWLB424are shown mounted on PCB402along with package200. Conductive traces404electrically couple the various packages and components disposed on PCB402to package200, giving use of the components within package200to other components on the PCB. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB402. In some embodiments, electronic device400includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers. While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims. | 30,920 |
11862573 | DETAILED DESCRIPTION Generally, a 3D electronic device may be considered to be a device formed by a process that combines multiple levels of electronic devices (e.g., one device formed over another) using planar formations (e.g., multiple devices on a single level). Since multiple levels in 3D devices may use approximately the same area on a substrate, an overall density of devices (e.g., memory devices) can be increased in relation to the number of levels. Generally discussed herein are three-dimensional (3D) memories, memory cells, and methods of making and using the same. As will be discussed, to prevent the lifting of a stack of conductive and insulating films (e.g., an ONON stack), the disclosed embodiments describe the use of “dummy” pillars that are etched in combination with active channel pillars. While active pillars terminate on a plug (e.g., a tungsten plug), the dummy pillars are etched deep into the silicon base substrate, thus strengthening the connection between the stack and the substrate. Alternatively, or in conjunction with the foregoing, the plugs below active pillars are partially inset into the substrate to increase skin friction and distribute the load of the pillar throughout the substrate. FIG.1illustrates a memory system184having a controller190that accesses data stored in a memory device192, in accordance with some embodiments. In one example, memory array120a three-dimensional (3D) memory array. In some embodiments, multiple memory arrays120can be used. Memory system184can be, for instance, a solid state drive (SSD), multimedia card (MMC), USB flash drive, compact flash card (CF), universal flash storage device (UFS), or other storage device, and can include a host interface188, controller190(e.g., a processor and/or other control circuitry), and memory device192(e.g., solid state memory devices such as NAND flash devices), which provides a storage volume for the memory system184. Memory device192can include one or more memory array(s)120. In a number of embodiments, the controller190, the memory device192, and/or the host interface188can be physically located on a single die or within a single package (e.g., a managed NAND application). In some embodiments, the controller190, the memory device192, and/or the host interface188are included in a stack of dice within a package. In one example, the stacked dice include through silicon vias for communicating power and signals to each die. In some embodiments, the controller190, the memory device192, and/or the host interface188are soldered to a printed circuit board (PCB). The controller190, the memory device192, and/or the host interface188can be packaged, for example, in a BGA module, M.2 module, mSATA module, slimSATA module, flash memory card, embedded USB card, small form factor (SFF) disk format (e.g., SFF-2.5, SFF-1.8, etc.), or other form-factor. Memory device192includes drivers121that are used to apply signals to word-line tiers of memory array120. In one embodiment, controller190accesses data stored in a first block of memory array120using a first word line. One of drivers121, under control of controller190, is used to access the data by applying a signal to the first word line. The word line signal is applied to corresponding tiers of the left block portion and right block portion of the first block. These two tiers logically correspond to the first word line. In one embodiment, each pair of corresponding tiers is connected by a conductive connector as described above. The controller190can be coupled to the host interface188and to the memory device192via one or more channels and can be used to transfer data between the memory system184and a host182. Host interface188can be in the form of a standardized interface. For example, when the memory system184is used for data storage in a computing system, the host interface188can be a serial advanced technology attachment (SATA), Serial Attached SCSI (SAS), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among other connectors and interfaces. In general, however, host interface188can provide an interface for passing control, address, data, and other signals between the memory system184and host182(e.g., a host computing device having compatible receptors for the host interface188). Host182can be a host system such as a personal laptop computer, a desktop computer, a server, an embedded computer, a digital camera, a mobile telephone, a memory card reader, or other electronic device controlled by a processor, among various other types of hosts. Host182can include a system motherboard and/or backplane and can include a number of memory access devices (e.g., a number of processors). Host182can be coupled to the host interface188by a communication channel186. The controller190can communicate with the memory device192to control data read, write, and erase operations, among other operations, including equalization, discharge, and string driver operations. The controller190can include, for example, a number of components in the form of hardware and/or firmware (e.g., one or more integrated circuits), and/or software for controlling access to the memory device192and/or for facilitating data transfer between the host182and the memory device192. In some embodiments, multiple memory devices can be used. The memory device192can include a number of arrays of memory cells. The arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. The memory cells can be grouped, for instance, into a number of blocks including a number of physical pages. A number of blocks can be included in a plane of memory cells, and an array can include a number of planes. In some embodiments, host182can be a computer (e.g., mobile phone or other computing device) having one or more central processing units (CPUs) to which computer peripheral devices, such as the memory system184, may be attached via an interconnect, such as a computer bus. The memory system184can be used to store data for the host182. Examples of memory system184include solid state drives, USB flash drives, multimedia cards (MMC), compact flash cards (CF), universal flash storage devices (UFS), memory cards, flash memory, or other memory devices. Controller190can run firmware104to perform operations responsive to the communications from the host182. Firmware in general is a type of computer program that provides control, monitoring, and data manipulation of engineered computing devices. InFIG.1, the firmware104controls the operations of the controller190in operating the memory system184, such as translating a logical address to a physical address for storing and accessing data in the memory device192. In one example, the controller190is an internal controller of a managed NAND device that stores data in TLC NAND flash memory. An example of non-volatile storage media used in memory array120is memory cells (e.g., SLC, TLC, QLC) in an integrated circuit. The storage media is non-volatile in that no power is required to maintain the data/information stored in the non-volatile storage media, which data/information can be retrieved after the non-volatile storage media is powered off and then powered on again. The memory cells may be implemented using various memory types, such as NAND gate based flash memory, phase-change memory (PCM), magnetic memory (MRAM), resistive random-access memory, and 3D XPoint, such that the storage media is non-volatile and can retain data stored therein without power for days, months, and/or years. In one embodiment, during operation, controller109receives various commands from host182. These commands can include a read command or a write command. In one example, a read command includes a logical address, and is received from host182to access stored data in non-volatile storage media of memory array120. In one example, controller190receives a logical address and determines a physical address. The physical address that is determined is used to read that portion of stored data that corresponds to the received logical address. Controller190then sends the read data to host182. In some instances, the controller190has multiple processors, each having its own in-processor cache memory. The memory system184can be used in various computing systems, such as a cloud computing system, an edge computing system, a fog computing system, and/or a standalone computer. In a cloud computing system, remote computer servers are connected in a network to store, manage, and process data. An edge computing system optimizes cloud computing by performing data processing at the edge of the computer network that is close to the data source and thus reduces data communications with a centralize server and/or data storage. At least some embodiments of the disclosures herein can be implemented using computer instructions executed by the controller190, such as the firmware104. In some instances, hardware circuits can be used to implement at least some of the functions of the firmware104. The firmware104can be initially stored in the non-volatile storage media of memory array120, or another non-volatile device, and loaded into volatile memory (not shown) and/or in-processor cache memory for execution by the controller190. A non-transitory computer storage medium can be used to store instructions of the firmware104. When the instructions are executed by the controller190of the memory system184, the instructions cause the controller190or other processing device(s) to perform methods as discussed herein. In one embodiment, a local manager (not shown) of memory system184receives data access commands. A data access request (e.g., read, write) from the host182identifies an LBA address to read, write, or erase data from a memory unit identified by the LBA address. The local manager translates the logical address to a physical address. In one embodiment, a controller is implemented by one or more processing devices. The processing device can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, an embedded processor, an embedded controller, a graphics processor, etc. The processing device can be, for example, a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), etc.), or another suitable processor. The processing device may be composed of a single processor with a single processing core, a single processor with multiple processing cores, or multiple processors. In some embodiments, the controller includes a host I/O management component, a flash translation layer (FTL), and a memory unit management component. In embodiments in which the memory (e.g., non-volatile storage media) includes a number of arrays of memory cells, the arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. The memory cells can be grouped, for instance, into a number of blocks, which are erased together as a group and can store a number of pages of data per block. A number of blocks can be included in a plane of memory cells and an array can include a number of planes. As used herein, a “page of data” refers to an amount of data that the controller is configured to write/read to/from the non-volatile storage media as part of a single write/read operation and can be referred to as a “flash page”. As an example, a memory device may have a page size of 8 KB (kilobytes) and may be configured to store 128 pages of data per block, 2048 blocks per plane, and 16 planes per device. Unlike with traditional hard disk drives, data stored in flash arrays cannot be directly overwritten. That is, a block of flash cells must be erased prior to rewriting data thereto (e.g., a page at a time). In some embodiments, the controller can manage data transferred between the host processor and the flash arrays via a logical-to-physical mapping scheme. For instance, a flash translation layer can employ a logical addressing scheme (e.g., logical block addressing (LBA)). As an example, when new data received from the host processor is to replace older data already written to the flash array, the controller can write the new data in a new location on the non-volatile storage media and the logical-to-physical mapping of the FTL can be updated such that the corresponding logical address(es) associated with the new data being written indicates (e.g., points to) the new physical location. The old location, which no longer stores valid data, will be erased prior to being written again. FIG.2Ais a diagram illustrating a memory exhibiting block lifting according to some embodiments of the disclosure. In the illustrated embodiment, an alternating stack of conductive and insulating materials (202) is situated above a source plate (212) and a silicon oxide layer (206). In one embodiment, the stack (202) comprises a stack of memory cells having a plurality of charge storage structures (e.g., floating gates, charge traps or the like), a stack of alternating control gates and insulating or insulating materials, and charge blocking materials disposed between the charge storage structures (mostly referred to by example as floating gates hereinafter) and the adjacent control gates. An oxide material, such as silicon oxide, is conventionally used as the insulating material. The charge blocking material may be an inter-poly insulating (IPD) material, such as oxide-nitride-oxide (ONO) material. In the illustrated embodiment, a plurality of pillars (204) are etched into the stack (202) terminating at a respective plug (208). In the illustrated embodiment, the pillars (204) extend into the stack (202) from the upper portion of the stack (202) to a level adjacent to the upper surface of the silicon oxide layer (206). Each of the pillars (204) may have a high aspect ratio. An aspect ratio of a pillar is defined as a ratio of a depth of the opening to a diameter of the opening. For example, the depth (e.g., the length) of an opening of a pillar may be about 2 μm, and the diameter of the opening of a pillar may be about 60-100 nm. In some embodiments, the opening of a pillar may have an isolation liner (not illustrated) formed (e.g., deposited) on an inside wall of the pillar. Therefore, the high aspect ratio of the opening may be e.g., between about 20 and 33. In some embodiments, the isolation liner may include oxide material or nitride material. In the illustrated embodiment, the silicon oxide layer (206) on the bottom of stack (202) includes a plurality of plugs (e.g., tungsten plugs) (208). In the illustrated embodiment, the plugs (208) function as an etch-landing layer to stop further etch during a process of forming the device, and may also function as a conductive contact to provide an electrical contact between a poly-silicon channel formed in the stack (202) and a subsequent poly-silicon channel in the stack (202) when the device is operating. In the illustrated embodiment, an air gap (210) exists between the silicon oxide layer (206) and the source plate (212). In the illustrated embodiment, this gap (210) is generating during the manufacturing of the memory wafer. Specifically, when the number of alternating layers of the stack (202) is increased, a punch etch procedure (or similar etching procedure) used to connect the pillars to the substrate and/or source plate (212) is unable to reach the substrate and/or source plate (212), which results in pillars that are lifted off the substrate and/or source plate (212). When lifted from the substrate and/or source plate (212), the transistors formed in the pillars (204) are inoperable. In addition, the placement of plugs (208) inFIG.2a, even when not “lifted” from the substrate and/or source plate (212) exhibit negative stress characteristics around the plugs (208), which are described briefly below in connection withFIGS.2B and2C. As illustrated inFIG.2B, the stress distribution is terminated at the end of the pillar and distributed directly at the interface of the silicon oxide layer (206) and the substrate and/or source plate (212). Additionally, as depicted inFIG.2C, skin friction is exerted from the surrounding silicon oxide layer (206) on the plug (208) itself. In addition to the foregoing, the stress distribution of the plugs (208) also contributes to the lifting of the ONON stack (202) from the source plate (212).FIGS.2B and2Care block diagrams illustrating stress distributions on a tungsten plug flush with a silicon oxide base layer according to some embodiments of the disclosure. As illustrated inFIG.2B, the stress of the pillar (208) is terminated at the end of the pillar and distributed directly on the upper surface of the silicon oxide layer (206). Additionally, some stress is perpendicularly deposited on the surfaces of the silicon oxide layer (206) surrounding the plug (208). Additionally, as depicted inFIG.2C, skin friction pressure is exerted from the surrounding silicon oxide layer (206) and on the plug (208) itself. The result is a net force pushing the plug (208) and silicon oxide layer (206) away from the source plate (212). FIG.3A through3Gare cross-sectional views illustrating a fabrication process for creating a semiconductor device. The specific number of steps illustrated inFIGS.3A through3Gare exemplary and more steps may be employed as will be discussed. FIG.3Aillustrates a source plate (302). In the illustrated embodiment, source plate (302) comprises a silicon substrate and one or more fabricated layers forming a source gate for a string of transistor elements. The source plate (302) comprises a silicon substrate that undergoes various fabrication processes to form the source lines. The specific steps used to form the source lines are not intended to be limiting. As an example, in some embodiments, a layer of tungsten silicide (WSix) may be deposited on top of the source plate (302). Next, a layer of polysilicon may be deposited on top of the WSix. Then a photoresist may be layered on top of the polysilicon. The WSix and polysilicon may then be dry- or wet-etched using the photoresist to form the source lines in the source plate (302). In general, any fabrication technique known in the art used to generate select gates (SGS) may be employed in the source plate (302) fabrication. Notably, the embodiment inFIG.3Adoes not explicitly illustrate the various layers of, for example, polysilicon or WSix used to form source lines. InFIG.3B, a layer of silicon oxide (304) is next deposited on the fully formed source plate (302). In some embodiments, the silicon oxide layer (304) is formed using tetraethyl orthosilicate (TEOS) deposition. InFIG.3C, a photoresist layer (316) is deposited on top of the silicon oxide layer (304). The photoresist layer (316) may comprise a photopolymeric, photodecomposing, photocrosslinking photoresist or other suitable photoresist. InFIG.3C, a mask pattern is placed on top of the photoresist layer. As will be discussed, the mark is patterned to produce a plurality of holes spaced throughout the photoresist. Next, inFIG.3D, a plurality of “holes” (314) are formed into the silicon oxide layer (304) via the photoresist (316). Notably, the photolithography used inFIGS.3C and3Dis configured to only etch plugs below where active columns of the 3D NAND array will be present. InFIG.3E, after etching the plug locations (314), tungsten (W) is used to fill the etched cavities, forming plugs (306). In some embodiments, tungsten plug chemical mechanical polishing (WCMP) may additionally be applied after forming the tungsten plugs. In some embodiments, conductive materials other than tungsten may be employed. At the conclusion of the processing stage depicted inFIG.3E, a plurality of plugs (306) are formed on the source plate (302), each plug (306) positioned below an active pillar of the resulting 3D NAND devices. InFIG.3F, a plurality of conductive and insulating layers are deposited atop the silicon oxide layer (304) to form a stack (312). In one embodiment, the conductive layers comprise silicon nitride layers and the insulating layers comprise silicon oxide layers. In the illustrated embodiment, a first insulating layer is deposited on the silicon oxide layer (304), followed by a second conductive layer, followed by a second insulating layer, etc. In some embodiments, alternating layers of silicon oxide and silicon nitride are referred to as an “ONON” stack. As known in the art, the ONON stack (312) can be used to form individual memory cells or transistors via a punch etch or tunnel etch. InFIG.3G, after depositing the stack (312), multiple pillars (308,310) are etched into the stack (312). In one embodiment, a hard mask is deposited on the top of the stack (312). In some embodiments, the hard mask comprises a pillar pattern (illustrated in more detail inFIG.4). In general, the pillar pattern defines a plurality of circular openings where pillars (308,310) are located. In some embodiments, the pillar openings are separated by larger gaps which form the gaps between sub-blocks of the transistor matrix. Once the hardmask is applied, a high aspect ratio (HAR) etch is performed to etch the pillars (308,310) into the stack (312). In some embodiments, the conductive (e.g., nitride) layers of the stack may be removed and a tungsten is applied via an inside-out tungsten deposition process. If the nitride layers of an ONON stack are removed in this manner, an OWOW stack may be used in lieu of an ONON stack. In the illustrated embodiment, in contrast to existing etches, the embodiment includes additional “dummy” pillars (310). In the illustrated embodiment, a first set of pillars (308) is etched and terminates at respective plugs (306). In the illustrated embodiment, the plugs (306) comprise tungsten plugs. In contrast, dummy pillars (310) terminate deep in the source plate (302). In the illustrated embodiment, the dummy pillars (310) terminate at a distance D from the upper surface of the source plate. Since the dummy pillars (310) are not positioned above the plugs (306), the HAR etch penetrates through the stack (312) and partially into the source plate (302). In contrast, the use of the tungsten plugs (306) prevents the higher power HAR etch from penetrating into the substrate, thus forming the saw-toothed pillar formation depicted inFIG.3G. In subsequent steps, dummy pillars (310) are further formed identical to the active pillars (308). That is, in some embodiments, both sets of pillars (308,310) are lined with a polysilicon coating and subsequently filled with silicon dioxide. However, since the dummy pillars (310) are not used for storing information, the dummy pillars to not affect the operation of the active pillars (308). Each of the materials described herein may be applied, deposited, or otherwise formed according to techniques and methods known independently in the art. The techniques and methods can include one or more deposition activities, such as chemical vapor deposition (CVD), atomic level deposition (ALD), physical vapor deposition (PVD), or other techniques. Forming multiple materials in various levels may be accomplished via stacked deposition operations. Although the process acts and operations described herein may refer to particular conductor, semiconductor, or insulating materials, such as silicon, silicon dioxide, silicon nitride, or others, a person of ordinary skill in the art and familiar with this disclosure will recognize that other conductor, semiconductor, and insulating materials may be substituted and still be within a scope of the disclosed subject matter. Thus, the material choices and selections presented are merely provided as an aid in understanding one example of a fabrication process. For example, various types of semiconductor materials, (e.g., single-crystal or amorphous silicon, germanium, other elemental semiconductor materials, compound semiconductor materials, etc.) may be used as an alternative for or in conjunction with other types of semiconductor material. Additionally, various types of insulating materials, such as tantalum pentoxide (Ta2O5), silicon nitride (SixNy), aluminum oxide (Al2O3), hafnium oxide (HfO2), and a variety of other organic or inorganic insulating materials, may be used as an alternative to or in conjunction with others of the materials described. Also, various other combinations of materials may also be substituted or included. For example, in certain applications, described semiconductor materials may be substituted with conductor materials including, for example, silver (Ag), copper (Cu), Aluminum (Al), zinc (Zn), platinum (Pt), tungsten (W), titanium (Ti), or tantalum (Ta). Further, various formation, process, and other discussions that follow may refer to one material placed, for example, “over,” “above,” or “atop” another material. Such descriptors are relative terms only and obviously depend upon an exact orientation of any resulting device. However, a person of ordinary skill in the art will readily understand the context of such relative terms upon reading and understanding the disclosure provided herein in conjunction with the respective drawings. FIG.4Ais a logical view of a memory block according to some embodiments of the disclosure. In the illustrated embodiment, the view presented inFIG.4Acomprises a cross-sectional view of a memory block. In the illustrated embodiment, a given memory block (400a) is situated in series with a plurality of other memory blocks (402a,404a). The memory blocks (400a,402a,404b) are substantially similar in design. A given memory block (400a) includes a plurality of bit lines (BL0-BL3). The specific number of bitlines is not intended to be limiting. In the illustrated embodiment, the bit lines are formed via stacks of conductive-insulating layers as described in FIGS.3A through3G and5A through5G. In the illustrated embodiment, a source plate of a given block (400a) includes a shared select gate source (SGS1) and a write line (WL1). As illustrated, a plurality of bit lines share a single SGS in contrast to memories where each bit line includes a dedicated SGS and WL transistor structure. Thus, the block (400a) comprises a “merged block” wherein a single SGS layer controls access to a plurality of bitlines (BL0-BL3). As in existing memories, write line WL1enables writing to transistors cormed in the bitlines (BL0-BL3). Additionally, as illustrated, each bit line (BL0-BL3) has a dedicated select gate drain (SGD0-SGD3) transistor to enable output of the bitlines (BL0-BL3) to a word line. In the illustrated embodiment, each bitline (BL0-BL3) comprises a plurality of vertically formed transistor elements. As described previously, these bitlines may be formed by layering conductive and insulating materials and etching transistors via a pillar etch. Details of this fabrication process are described previously and not repeated herein. In the illustrated embodiment, blocks (400a,402a,404a) are separated to form logical divisions of memory cells. In the illustrated embodiment, the blocks (400a,402a,404a) are separated by slots (406a). In one embodiment, these slots comprise an un-etched conductive-insulating stack. For example, turning toFIG.3F, the stack (312) may simply not be etched to provide segmentation between memory blocks. By contrast, individual bitlines (BL0-BL3) are separated by slits (408a). In one embodiment, the slits (408a) correspond to pillars (310). In the illustrated embodiment, the slits (408a) are formed via a punch etch at the same time the pillars used to form transistors in a given bitline are formed. However, the aforementioned plug layer is used to vary the depths of the pillars during formation. Details of this fabrication process have been described and are described more herein. FIG.4Bis a top-down view of a portion of a semiconductor structure according to some embodiments of the disclosure. In the illustrated embodiment,FIG.4Bprovides a top down view of a larger surface area that includes the cross-sectional memory blocks ofFIG.4A. In the illustrated embodiment, a single block (400a) (e.g., merged block ofFIG.4A) of bitlines (402b) is depicted while portions of other blocks (402a,404a) are partially depicted. The block (400a) is separated from other blocks via slots (406a). Slits (408a) provide column-separation between bitlines (402b) of a merged block (400a). As described in the process depicted inFIGS.3A through3G, channel columns are etched through a stack of conductive-insulating layers to form bitlines (402b). As discussed, each of these columns terminates on a plug formed atop the a source plate. In contrast, interleaved sets of dummy pillars (408a) are etched deep into the substrate and do not terminate on a plug. FIG.5A through5Dillustrate a fabrication process for creating a 3D NAND Flash memory. FIG.5Aillustrates a source plate (302). In the illustrated embodiment, source plate (302) comprises a silicon substrate and one or more fabricated layers forming a source gate for a string of transistor elements. The source plate (302) comprises a silicon substrate that undergoes various fabrication processes to form the source lines. The specific steps used to form the source lines are not intended to be limiting. As an example, in some embodiments, a layer of tungsten silicide (WSix) may be deposited on top of the source plate (302). Next, a layer of polysilicon may be deposited on top of the WSix. Then a photoresist may be layered on top of the polysilicon. The WSix and polysilicon may then be etched using the photoresist to form the source lines in the source plate (302). In general, any fabrication technique known in the art used to generate select gates (SGS) may be employed in the source plate (302) fabrication. Notably, the embodiment inFIG.3Adoes not explicitly illustrate the various layers of, for example, polysilicon or WSix used to form source lines. InFIG.5B, a layer of silicon oxide (304) is deposited on the fully formed source plate (302). In some embodiments, the silicon oxide layer (304) is formed using tetraethyl orthosilicate (TEOS) deposition. InFIG.5c, a photoresist layer (316) is deposited on top of the silicon oxide layer (304). The photoresist layer (316) may comprise a photopolymeric, photodecomposing, photocrosslinking photoresist or other suitable photoresist. InFIG.3C, a mask pattern is placed on top of the photoresist layer. As will be discussed, the mark is patterned to produce a plurality of holes spaced throughout the photoresist. Next, a plurality of “holes” are etched into the silicon oxide layer (304) and into the source plate (302) via the photoresist patterning and via dry etch processing. These holes (502) are situated where plugs (506) are illustrated. Notably, in one embodiment, the photolithography used in this sub-stage is configured to only etch plugs below where active columns of the 3D NAND array will be present. InFIG.5E, after etching the plug locations, in the next stage illustrated inFIG.5C, tungsten is used to fill the etched cavities, forming plugs (506). In some embodiments, tungsten plug chemical mechanical polishing (WCMP) may additionally be applied after forming the tungsten plugs. In some embodiments, conductive materials other than tungsten may be employed. InFIG.5F, a plurality of conductive and insulating layers are deposited atop the silicon oxide layer (304) to form a stack (312). In one embodiment, the conductive layers comprise silicon nitride layers and the insulating layers comprise silicon oxide layers. In the illustrated embodiment, a first insulating layer is deposited on the silicon oxide layer (304), followed by a second conductive layer, followed by a second insulating layer, etc. In some embodiments, alternating layers of silicon oxide and silicon nitride are referred to as an “ONON” stack. As known in the art, the ONON stack (312) can be used to form individual memory cells or transistors via a punch etch or tunnel etch. Finally, inFIG.5G, the stack (312) and pillars (308,310) are etched. In the illustrated embodiment, this process is performed as described inFIG.3Gand that discussion is not repeated herein. As noted, however, the active pillars (308) are situated on the partially inset plugs (506). As described in the discussion ofFIGS.6A and6B, this partially inset plug design may be optional, which moves the stress distribution path at the end of the pillars from the interface of the silicon oxide layer (304) and the substrate and/or source plate (302) into the substrate and/or source plate (302) and prevent lifting in combination with the dummy pillars. Further, in some embodiments, dummy pillars may not be used at all and only the partially inset plugs may be used to strengthen the active pillars. Each of the materials described herein may be applied, deposited, or otherwise formed according to techniques and methods known independently in the art. The techniques and methods can include one or more deposition activities, such as chemical vapor deposition (CVD), atomic level deposition (ALD), physical vapor deposition (PVD), or other techniques. Forming multiple materials in various levels may be accomplished via stacked deposition operations. Although the process acts and operations described herein may refer to particular conductor, semiconductor, or insulating materials, such as silicon, silicon dioxide, silicon nitride, or others, a person of ordinary skill in the art and familiar with this disclosure will recognize that other conductor, semiconductor, and insulating materials may be substituted and still be within a scope of the disclosed subject matter. Thus, the material choices and selections presented are merely provided as an aid in understanding one example of a fabrication process. For example, various types of semiconductor materials, (e.g., single-crystal or amorphous silicon, germanium, other elemental semiconductor materials, compound semiconductor materials, etc.) may be used as an alternative for or in conjunction with other types of semiconductor material. Additionally, various types of insulating materials, such as tantalum pentoxide (Ta2O5), silicon nitride (SixNy), aluminum oxide (Al2O3), hafnium oxide (HfO2), and a variety of other organic or inorganic insulating materials, may be used as an alternative to or in conjunction with others of the materials described. Also, various other combinations of materials may also be substituted or included. For example, in certain applications, described semiconductor materials may be substituted with conductor materials including, for example, silver (Ag), copper (Cu), Aluminum (Al), zinc (Zn), platinum (Pt), tungsten (W), titanium (Ti), or tantalum (Ta). Further, various formation, process, and other discussions that follow may refer to one material placed, for example, “over,” “above,” or “atop” another material. Such descriptors are relative terms only and obviously depend upon an exact orientation of any resulting device. However, a person of ordinary skill in the art will readily understand the context of such relative terms upon reading and understanding the disclosure provided herein in conjunction with the respective drawings. FIGS.6A and6Bare block diagrams illustrating stress distributions on an inset tungsten plug according to some embodiments of the disclosure. As illustrated inFIG.6A, when the plug (506) is inserted further into source plate (302) and through silicon oxide layer (304), the downward stress distribution is distributed within the substrate itself, thus anchoring the pillar firmly within the substrate itself. Further, as illustrated inFIG.6B, the skin friction exerted on the plug (506) is also distributed in both the silicon oxide layer (304) and the source plate (302) which further retains the plug and pillar situated above the plug. The disclosure includes various devices which perform the methods and implement the systems described above, including data processing systems which perform these methods, and computer readable media containing instructions which when executed on data processing systems cause the systems to perform these methods. The description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in certain instances, well-known or conventional details are not described in order to avoid obscuring the description. References to one or an embodiment in the present disclosure are not necessarily references to the same embodiment; and, such references mean at least one. Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments. In this description, various functions and operations may be described as being performed by or caused by software code to simplify description. However, those skilled in the art will recognize what is meant by such expressions is that the functions result from execution of the code by one or more processors, such as a microprocessor, Application-Specific Integrated Circuit (ASIC), graphics processor, and/or a Field-Programmable Gate Array (FPGA). Alternatively, or in combination, the functions and operations can be implemented using special purpose circuitry (e.g., logic circuitry), with or without software instructions. Embodiments can be implemented using hardwired circuitry without software instructions, or in combination with software instructions. Thus, the techniques are not limited to any specific combination of hardware circuitry and software, nor to any particular source for the instructions executed by a computing device. While some embodiments can be implemented in fully functioning computers and computer systems, various embodiments are capable of being distributed as a computing product in a variety of forms and are capable of being applied regardless of the particular type of machine or computer-readable media used to actually effect the distribution. At least some aspects disclosed can be embodied, at least in part, in software. That is, the techniques may be carried out in a computing device or other system in response to its processor, such as a microprocessor, executing sequences of instructions contained in a memory, such as ROM, volatile RAM, non-volatile memory, cache or a remote storage device. Routines executed to implement the embodiments may be implemented as part of an operating system, middleware, service delivery platform, SDK (Software Development Kit) component, web services, or other specific application, component, program, object, module or sequence of instructions referred to as “computer programs.” Invocation interfaces to these routines can be exposed to a software development community as an API (Application Programming Interface). The computer programs typically comprise one or more instructions set at various times in various memory and storage devices in a computer, and that, when read and executed by one or more processors in a computer, cause the computer to perform operations necessary to execute elements involving the various aspects. A machine readable medium can be used to store software and data which when executed by a computing device causes the device to perform various methods. The executable software and data may be stored in various places including, for example, ROM, volatile RAM, non-volatile memory and/or cache. Portions of this software and/or data may be stored in any one of these storage devices. Further, the data and instructions can be obtained from centralized servers or peer to peer networks. Different portions of the data and instructions can be obtained from different centralized servers and/or peer to peer networks at different times and in different communication sessions or in a same communication session. The data and instructions can be obtained in entirety prior to the execution of the applications. Alternatively, portions of the data and instructions can be obtained dynamically, just in time, when needed for execution. Thus, it is not required that the data and instructions be on a machine readable medium in entirety at a particular instance of time. Examples of computer-readable media include but are not limited to recordable and non-recordable type media such as volatile and non-volatile memory devices, read only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, magnetic disk storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROMs), Digital Versatile Disks (DVDs), etc.), among others. The computer-readable media may store the instructions. In general, a tangible or non-transitory machine readable medium includes any mechanism that provides (e.g., stores) information in a form accessible by a machine (e.g., a computer, mobile device, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). In various embodiments, hardwired circuitry may be used in combination with software and firmware instructions to implement the techniques. Thus, the techniques are neither limited to any specific combination of hardware circuitry and software nor to any particular source for the instructions executed by a computing device. Various embodiments set forth herein can be implemented using a wide variety of different types of computing devices. As used herein, examples of a “computing device” include, but are not limited to, a server, a centralized computing platform, a system of multiple computing processors and/or components, a mobile device, a user terminal, a vehicle, a personal communications device, a wearable digital device, an electronic kiosk, a general purpose computer, an electronic document reader, a tablet, a laptop computer, a smartphone, a digital camera, a residential domestic appliance, a television, or a digital music player. Additional examples of computing devices include devices that are part of what is called “the internet of things” (IOT). Such “things” may have occasional interactions with their owners or administrators, who may monitor the things or modify settings on these things. In some cases, such owners or administrators play the role of users with respect to the “thing” devices. In some examples, the primary mobile device (e.g., an Apple iPhone) of a user may be an administrator server with respect to a paired “thing” device that is worn by the user (e.g., an Apple watch). In some embodiments, the computing device can be a computer or host system, which is implemented, for example, as a desktop computer, laptop computer, network server, mobile device, or other computing device that includes a memory and a processing device. The host system can include or be coupled to a memory sub-system so that the host system can read data from or write data to the memory sub-system. The host system can be coupled to the memory sub-system via a physical host interface. In general, the host system can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections. In some embodiments, the computing device is a system including one or more processing devices. Examples of the processing device can include a microcontroller, a central processing unit (CPU), special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or another suitable processor. Although some of the drawings illustrate a number of operations in a particular order, operations which are not order dependent may be reordered and other operations may be combined or broken out. While some reordering or other groupings are specifically mentioned, others will be apparent to those of ordinary skill in the art and so do not present an exhaustive list of alternatives. Moreover, it should be recognized that the stages could be implemented in hardware, firmware, software or any combination thereof. In the foregoing specification, the disclosure has been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. | 45,562 |
11862574 | DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. The shape and size of constituent elements in the drawings may be exaggerated or reduced for clarity. Electronic Device FIG.1is a schematic block diagram of an example of an electronic device system. Referring toFIG.1, an electronic device1000may accommodate a main board1010therein. In the main board1010, chip-related components1020, network-related components1030, other components1040, and the like may be physically and/or electrically connected to one another, and may also be combined with other components to be described later to thus form various signal lines1090. Examples of the chip-related components1020may include a memory chip such as a volatile memory, for example, a dynamic random access memory (DRAM), a non-volatile memory, for example, a read only memory (ROM), a flash memory, and the like; an application processor chip such as a central processor, for example, a central processing unit (CPU), a graphics processor, for example, a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, and the like; a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), and the like; and the like, but are not limited thereto. Thus, different types of chip-related components may also be included therein. In addition, the chip-related components1020may also be combined with each other. Examples of the network-related components1030may include Wi-Fi (IEEE 802.11 family and the like), WiMAX (IEEE 802.16 family and the like), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and other optional wireless and wired protocols provided thereafter, but are not limited thereto. In addition, any ones of a number of other wireless or wired standards or protocols may be included therein. Further, the network-related components1030may also be combined with the chip-related components1020. Examples of other components1040may include a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, low temperature co-firing ceramics (LTCC), an electro-magnetic interference (EMI) filter, and a multilayer ceramic condenser (MLCC), and the like, but are not limited thereto. In addition, passive components having various other usages, and the like, may be included therein. In addition, other components1040may also be combined with the chip-related components1020and/or the network-related components1030. Depending on the type of the electronic device1000, the electronic device1000may include other components that may or may not be physically and/or electrically connected to the main board1010. Examples of other components may include, for example, a camera1050, an antenna1060, a display1070, a battery1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a large capacity storage device, for example a hard disk drive (not shown), a compact disc (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), and the like, but are not limited thereto. In addition, other components used for various usages, and the like, may be included therein, depending on the type of the electronic device1000. The electronic device1000may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop computer, a netbook computer, a television set, a video game, a smartwatch, an automotive component, or the like, but is not limited thereto. In addition, other optional electronic devices for the processing of data may also be used. FIG.2is a schematic perspective view of an example of an electronic device. Referring toFIG.2, a semiconductor package may be used in various electronic devices as described above, for various usages. For example, a motherboard1110may be accommodated within a body1101of a smartphone1100, and various components1120may be physically and/or electrically connected to the motherboard1110. In addition, other components, such as a camera1130and the like, which may or may not be physically and/or electrically connected to the motherboard1110, may be accommodated within the body1101. A portion of the components1120may be chip-related components, for example, a semiconductor package1121, but are not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may also be another electronic device as described above. Semiconductor Package A semiconductor chip generally has a large number of microelectronic circuits integrated therein, but may not serve as a finished semiconductor product in itself and may be damaged by external physical or chemical impacts. Thus, a semiconductor chip itself may not be used as it is, but may be packaged and used in electronic devices and the like in a package state. Semiconductor packaging may be required due to a difference in circuit widths between a semiconductor chip and a main board of an electronic device in terms of electrical connectivity. In detail, in the case of the semiconductor chip, the size of a connection pad and a distance between the connection pads are very fine, while in the case of the main board used in electronic devices, the size of a component mounting pad and a distance between component mounting pads may be significantly large, as compared to the scale of the semiconductor chip. Thus, it may be difficult to directly mount a semiconductor chip on such a main board, and thus, a packaging technology in which a difference in circuit widths thereof may be reduced may be required. Semiconductor packages manufactured in such a packaging technique may be classified as fan-in semiconductor packages and fan-out semiconductor packages, depending on structures and usage thereof. Hereinafter, a fan-in semiconductor package and a fan-out semiconductor package will be described in more detail with reference to the accompanying drawings. Fan-in Semiconductor Package FIGS.3A and3Bare schematic cross-sectional views of a fan-in semiconductor package before and after packaging. FIG.4is a schematic cross-sectional view of a packaging process of a fan-in semiconductor package. With reference toFIGS.3A to4, a semiconductor chip2220may be an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like, a connection pad2222formed on one surface of the body2221and including a conductive material of aluminum (Al) or the like, and a passivation film2223, such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least a portion of the connection pad2222. In this case, since the connection pad2222is significantly small, the integrated circuit (IC) may be difficult to be mounted on a medium-sized printed circuit board (PCB) as well as on a main board of an electronic device and the like. Thus, a connection member2240may be formed on the semiconductor chip2220, to comply with a size of the semiconductor chip2220, to redistribute the connection pad2222. The connection member2240may be formed by forming an insulating layer2241using an insulating material such as a photoimageable dielectric (PID) resin on the semiconductor chip2220, forming a via hole2243hexposing the connection pad2222, and then forming a distribution pattern2242and a via2243. Then, a passivation layer2250may be formed to protect the connection member2240, an opening2251may be formed, and then, an under-bump metal layer2260and the like may be formed. In detail, through a series of processes, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the under-bump metal layer2260may be manufactured. As described above, the fan-in semiconductor package may be a package type in which connection pads of a semiconductor chip, for example, input/output (I/O) terminals are all disposed inside the device, and the fan-in semiconductor package may have appropriate electrical characteristics and relatively low manufacturing costs. Thus, a number of devices for smartphones have been manufactured in the form of a fan-in semiconductor package, and in detail, fan-in semiconductor packages are being developed to realize compactness and fast signal transmission. However, in the case of the fan-in semiconductor package, space limitations, meaning that all of I/O terminals should be disposed inside the semiconductor chip, may be problematic. Thus, such a structure may be difficult to be applied to a semiconductor chip having a relatively large number of I/O terminals or a semiconductor chip having a relatively small size. In addition, due to such vulnerability, the fan-in semiconductor package may not be directly mounted on a main board of an electronic device. For example, even in a case in which the size of and distance between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size and the distance therebetween may not be enough to be directly mounted on an electronic device main board. FIG.5is a schematic cross-sectional view of a case for a fan-in semiconductor package mounted on a ball grid array (BGA) substrate to ultimately be mounted on a main board of an electronic device. FIG.6is a schematic cross-sectional view of a case for a fan-in semiconductor package embedded in a BGA substrate to ultimately be mounted on a main board of an electronic device. Referring toFIGS.5and6, in the case of a fan-in semiconductor package2200, connection pads2222of a semiconductor chip2220, for example, I/O terminals, may be redistributed through a BGA substrate2301, and resultantly, the fan-in semiconductor package2200may be mounted on a main board2500of an electronic device in a state in which the fan-in semiconductor package2200is mounted on the BGA substrate2301. In this case, a solder ball2270and the like may be fixed by an underfill resin2280or the like, and an outer portion thereof may be covered with a molding material2290or the like. Alternatively, the fan-in semiconductor package2200may be embedded in a separate BGA substrate2302, and in the embedding state of the fan-in semiconductor package2200, the connection pads2222of the semiconductor chip2220, for example, the I/O terminals, may again be redistributed by the BGA substrate2302, and may ultimately be mounted on the main board2500of the electronic device. As such, since the fan-in semiconductor package is difficult to directly mount on the main board of the electronic device, the fan-in semiconductor package needs to be mounted on a separate BGA substrate and then remounted on a main board of an electronic device via re-passing through a packaging process, or may be mounted on a main board of an electronic device and used in a state in which the fan-in semiconductor package is embedded in a BGA substrate. Fan-Out Semiconductor Package FIG.7is a schematic cross-sectional view of a fan-out semiconductor package. With reference toFIG.7, in the case of a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and a connection pad2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may further be formed on the connection member2140, and further, an under-bump metal layer2160may be formed in an opening of the passivation layer2150. A solder ball2170may further be formed on the under-bump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, a connection pad2122, a passivation film (not shown), and the like. The connection member2140may include an insulating layer2141, a redistribution layer2142formed on the insulating layer2141, and a via2143electrically connecting the connection pad2122, the redistribution layer2142and the like to each other. As described above, the fan-out semiconductor package may be formed in a form in which I/O terminals are redistributed to the outside of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of I/O terminals of the semiconductor chip should be disposed inside the semiconductor chip, and thus, if the element size is reduced, ball size and pitch need to be reduced. Thus, a standardized ball layout may not be used. On the other hand, in the fan-out semiconductor package, the I/O terminals may be redistributed to the outside of the semiconductor chip through the connection member formed on the semiconductor chip, and thus, a standardized ball layout may be used as it is, even in the case in which the size of the semiconductor chip is reduced. Thus, the fan-out semiconductor package may be mounted on a main board of an electronic device without using a separate BGA substrate as will be described later. FIG.8is a schematic cross-sectional view of a case for a fan-out semiconductor package mounted on a main board of an electronic device. Referring toFIG.8, a fan-out semiconductor package2100may be mounted on a main board2500of an electronic device through solder balls2170or the like. For example, as described above, in the case of the fan-out semiconductor package2100, a connection member2140may be disposed on a semiconductor chip2120, to allow connection pads2122to be redistributed to a fan-out region exceeding a size of the semiconductor chip2120, and thus, a standardized ball layout may be used as it is, and as a result, the fan-out semiconductor package2100may be mounted on the main board2500of the electronic device without a separate BGA substrate or the like. As such, since the fan-out semiconductor package may be mounted on the main board of the electronic device without a separate BGA substrate, a thickness of the fan-out semiconductor package may be reduced as compared to that of the fan-in semiconductor package using the BGA substrate. Thus, the miniaturization and slimness of a semiconductor package may be implemented. In addition, the fan-out semiconductor package may have relatively excellent thermal characteristics and electrical characteristics to be suitable for mobile products. In addition, the fan-out semiconductor package may be implemented more compactly than a general package-on-package (POP) type using a printed circuit board (PCB), and may be implemented to prevent the occurrence of warpage and problems caused thereby. On the other hand, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on a main board of an electronic device, or the like, and for protecting a semiconductor chip from external impacts, and is based on a technology different from that of a printed circuit board (PCB), such as an BGA substrate or the like, including a fan-in semiconductor package embedded therein, in terms of the scale, the usage, and the like. Hereinafter, a fan-out semiconductor package capable of effectively preventing the occurrence of warpage will be described with reference to the drawings. FIG.9is a schematic cross-sectional view of an example of a fan-out semiconductor package. FIG.10is a schematic cutaway plan view of the fan-out semiconductor package, taken along line I-I′ ofFIG.9. Referring toFIGS.9and10, a fan-out semiconductor package100A according to an exemplary embodiment may include a core member110including a through hole110H, one or more dummy structures125disposed in the core member110, a semiconductor chip120disposed in the through hole110H of the core member110and having an active surface on which a connection pad122is disposed and an inactive surface disposed to oppose the active surface, an encapsulant130filling at least a portion of the through hole110H while sealing at least a portion of each of the core member110and the semiconductor chip120, a connection member140including a redistribution layer142disposed on the core member110and the active surface of the semiconductor chip120and electrically connected to the connection pad122, a passivation layer150disposed on the connection member140, an under-bump metal layer160disposed on an opening of the passivation layer150, and an electrical connection structure170disposed on the passivation layer150and connected to the under-bump metal layer160. On the other hand, in the case of a semiconductor package, a plurality of packages may be manufactured using a wafer or a panel for mass production, or the like, and individual packages may be obtained by a sawing process or the like. However, if a difference in unit warpage occurs within the panel for manufacturing of a package, due to a difference in physical properties such as thermal expansion coefficients, or the like, of various materials in the package, or due to a hardening shrinkage, or the like, of a layer including a resin component such as an encapsulant, in manufacturing a plurality of packages, it may be difficult to manufacture products of the same quality due to problematic warpage. Further, panel-level warpage as well as package warpage may also be problematic. Meanwhile, in the fan-out semiconductor package100A according to an exemplary embodiment, since the core member110having the through hole110H may be disposed in a sealing region of the semiconductor chip120, warpage of the fan-out semiconductor package100amay be controlled by the core member110. In addition, various types of distribution may be performed as compared with the case of designing distribution layers112a,112b,112cand112din the core member110. In addition, one or more dummy structures125may be disposed inside the core member110. In detail, as described above, a relatively high degree of rigidity may be provided, as compared to that in a case in which the dummy structure125is not disposed in a fan-out region, based on the semiconductor chip120. Further, various warpage control efforts may be more effectively performed through control of a thermal expansion coefficient or the like. The dummy structure125may include a semiconductor material in a manner similar to that of the semiconductor chip120. In detail, the dummy structure125may be a silicon-based die, for example, a silicon die, including silicon (Si). For example, the dummy structure125may be a silicon piece without an integrated circuit. For another example, the dummy structure125may be a silicon piece without a functional integrated circuit. For another example, the dummy structure125may be a silicon piece without connection pads. For another example, the dummy structure125may be a silicon piece covered by an insulating material. In this case, warpage occurring locally in a package region may offset each other, and thus, a difference in thermal expansion coefficients in the package may be significantly reduced, to be relatively effective for control of warpage. On the other hand, the dummy structure125may be signal-disconnected from the semiconductor chip120. In addition, the dummy structure125may also be signal-disconnected from the redistribution layer142of the connection member140or the distribution layers112ato112dof the core member110. In detail, the expression “dummy” used in the present disclosure basically indicates that signals are not exchanged with the semiconductor chip120in a circuit. Hereinafter, respective configurations included in the fan-out semiconductor package100A in an example will be described in more detail. The core member110may further improve rigidity of the fan-out semiconductor package100A depending on a detailed material of the core member, and may serve to secure uniformity of thickness of the encapsulant130, or the like. For example, when the distribution layers112a,112b,112cand112dand vias113a,113band113care formed in the core member110as illustrated inFIG.9, the fan-out semiconductor package100A may be used as a package-on-package (POP)-type package. The core member110may include the through hole110H. In the through hole110H, the semiconductor chip120may be disposed to be spaced apart from the core member110by a predetermined distance. A periphery of a side surface of the semiconductor chip120may be surrounded by the core member110, which is merely provided by way of example. Thus, various modifications thereof may be provided, and other functions may be performed according to a form thereof. One or more dummy structures125may be disposed inside the core member110, and thus, warpage may be controlled relatively effectively. The core member110may include a first insulating layer111a, a first distribution layer112aand a second distribution layer112bdisposed on two surfaces of the first insulating layer111a, a second insulating layer111bdisposed on the first insulating layer112aand covering the first distribution layer112a, a third distribution layer112cdisposed on the second insulating layer111b, a third insulating layer111cdisposed on the first insulating layer111ato cover the second distribution layer112bdisposed on the first insulating layer111a, and a fourth distribution layer112ddisposed on the third insulating layer111c. The first to fourth distribution layers112a,112b,112cand112dmay be electrically connected to a connection pad122. Since the core member110includes a relatively large number of distribution layers112a,112b,112cand112d, the redistribution layer142of the connection member140may be further simplified. Thus, a reduction in yield due to defects occurring in a process of forming the connection member140may be prevented. The first to fourth distribution layers112a,112b,112cand112dmay be electrically connected to each other, via first to third vias113a,113band113cpenetrating through the first to third insulating layers111a,111band111c, respectively. The first insulating layer111amay have one or more cavities111ah, and a dummy structure125may be disposed in each of the cavities111ah. The dummy structure125may be disposed on the second insulating layer111band may be covered with the third insulating layer111c, which is merely an example. Thus, the arrangement form of the dummy structure125may be modified. For example, a cavity may be formed in the second insulating layer111bor the third insulating layer111c, and the dummy structure125may be disposed thereon, or the dummy structure125may be disposed in various combinations. For example, when the core member110and the dummy structure125are cut into planes parallel to the inactive surface of the semiconductor chip120, in detail, when viewed in plan view, as illustrated inFIG.10, a planar area occupied by the dummy structure125may be greater than a planar area of the core member110, for example, greater than an entire planar area occupied by the first insulating layer111a, the second insulating layer111b, and the first via113ainFIG.10. As described above, as the planar area occupied by the dummy structure125is increased, an effect of disposing the dummy structure125may be further increased, and thus, control of warpage may be further effective. The first insulating layer111amay have a thickness greater than that of the second insulating layer111band that of a portion of the third insulating layer111cdisposed on the first insulating layer111a. The first insulating layer111amay have a relatively great thickness to maintain basic rigidity, and the second insulating layer111band the third insulating layer111cmay be formed to have a relatively large number of distribution layers112cand112d. The first insulating layer111amay include an insulating material different from those of the second insulating layer111band the third insulating layer111c. For example, the first insulating layer111amay be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second insulating layer111band the third insulating layer111cmay be an ABF film or a photoimageable dielectric (PID) film including a filler and an insulating resin, but are not limited thereto. Similarly, the first via113apenetrating through the first insulating layer111amay have a diameter greater than that of each of the second and third vias113band113cpenetrating the second and third insulating layers111band111c. A lower surface of the third distribution layer112cof the core member110may be disposed to be lower than a lower surface of the connection pad122of the semiconductor chip120. Further, a distance between the redistribution layer142of the connection member140and the third distribution layer112cof the core member110may be less than a distance between the redistribution layer142of the connection member140and the connection pad122of the semiconductor chip120. The third distribution layer112cmay be disposed on the second insulating layer111bto have a protruding form, and as a result, may come into contact with the connection member140. The first distribution layer112aand the second distribution layer112bof the core member110may be positioned on a level between the active surface and the inactive surface of the semiconductor chip120. The core member110may be formed to correspond to a thickness of the semiconductor chip120, and the first distribution layer112aand the second distribution layer112bformed in the core member110may be disposed on a level between the active surface and the inactive surface of the semiconductor chip120. A thickness of each of the distribution layers112a,112b,112cand112dof the core member110may be greater than a thickness of the redistribution layer142of the connection member140. Since the core member110is usually manufactured through a substrate process, the distribution layers112a,112b,112cand112dmay also be formed to have a relatively large size. On the other hand, since the connection member140is usually manufactured through a semiconductor process, the redistribution layer142may be formed to have a relatively small size to be thinned. As a material of the insulating layer111, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin mixture provided by mixing such resins with an inorganic filler or a resin formed by impregnating such resins in a core material such as a glass fiber, a glass cloth, a glass fabric, or the like, together with an inorganic filler, for example, a prepreg resin, Ajinomoto Build-up Film (ABF) resin, FR-4 resin, Bismaleimide Triazine (BT) resin, or the like, may be used. For example, when a high rigidity material such as a prepreg resin including a glass fiber or the like is used, the core member110may be used as a support member for rigidity of the fan-out semiconductor package100A. The distribution layers112a,112b,112cand112dmay serve to redistribute the connection pads122of the semiconductor chip120. As a material of formation of the distribution layers112a,112b,112cand112d, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof or the like, may be used. The distribution layers112a,112b,112cand112dmay perform various functions according to a design of a relevant layer. For example, the distribution layers112a,112b,112cand112dmay include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like. In this case, the signal S pattern may include various signals, except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal or the like. Further, a via pad, a wire pad, an electrical connection structure pad, and the like may be included therein. The vias113a,113band113cmay electrically connect the distribution layers112a,112b,112cand112dformed as different layers, to each other, thereby forming an electrical path in the core member110. As a material of formation of the vias113a,113band113c, a conductive material may also be used. The vias113aand113bmay be fully filled with a conductive material, or may be formed by allowing a conductive material to be formed along a wall surface of a via hole. Further, the vias113a,113band113cmay have any shapes known in the art, such as a cylindrical shape, an hourglass shape or the like, as well as a tapered shape. The semiconductor chip120may be an integrated circuit (IC) in which hundreds to millions or more devices are integrated into one chip. The integrated circuit may be a processor chip, such as a central processor, for example, a CPU, a graphics processor, for example, a GPU, a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, and the like, in detail, may be an application processor (AP), but is not limited thereto. For example, the integrated circuit may be a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), and the like, or may be a memory chip such as a volatile memory, for example, a DRAM, a nonvolatile memory, for example, a ROM, a flash memory, and the like. Further, the circuits may also be disposed to be combined with each other. The semiconductor chip120may be formed, based on an active wafer. In this case, a semiconductor material, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, may be used as a base material of a body121. Various circuits may be formed in the body121. The connection pad122may be provided to electrically connect the semiconductor chip120to other components. As a material thereof, a conductive material such as aluminum (Al) or the like may be used without any particular limitation. A passivation film123exposing the connection pad122may be formed on the body121. The passivation film123may be an oxide film or a nitride film, or may be a double layer of an oxide film and a nitride film. A lower surface of the connection pad122may have a step with respect to a lower surface of an encapsulant130through the passivation film123, and thus, the encapsulant130may fill at least a portion of a space between the passivation film123and the connection member140. In this case, the encapsulant130may be prevented from bleeding to the lower surface of the connection pad122, to some extent. An insulating film (not shown) or the like may also be further disposed on other required positions. The semiconductor chip120may be a bare die, and the connection pad122may be in directly physical contact with a via143of the connection member140. The dummy structures125may respectively be formed, based on an active wafer. A semiconductor material, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs) or the like, may be used as a base material. For example, the dummy structures125may respectively be a silicon base dummy structure, and in this case, when a base material of the body121of the semiconductor chip121of the semiconductor chip120is silicon (Si), a balance thereof may be matched. For another example, the dummy structures125may be made of the same material constituting the body121of the semiconductor chip120. For another example, the dummy structures125may be made of substantially the same material constituting the body121of the semiconductor chip120and may be covered by an insulating material. The dummy structure125may be electrically insulated from the semiconductor chip120. For example, the dummy structure125may also be electrically insulated from the redistribution layer142of the connection member140. The encapsulant130may protect the core member110, the semiconductor chip120, and the like. A sealing form thereof is not particularly limited, and any form covering at least a portion of the core member110, the semiconductor chip120, and the like may be used. For example, the encapsulant130may cover the core member110and the inactive surface of the semiconductor chip120, and may fill a space between the wall surface of the through hole110H and a side surface of the semiconductor chip120. The encapsulant130may also fill at least a portion of the space between the passivation film123of the semiconductor chip120and the connection member140. By filling the through hole110H with the encapsulant130, buckling may be reduced while performing an adhesive function depending on a detailed material. A material of the encapsulant130is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin mixture provided by mixing such resins with an inorganic filler or a resin formed by impregnating such resins in a core material such as a glass fiber, a glass cloth, a glass fabric, or the like, together with an inorganic filler, for example, a prepreg resin, Ajinomoto Build-up Film (ABF) resin, FR-4 resin, Bismaleimide Triazine (BT) resin, or the like, may be used. A photoimageable encapsulant (PIE) resin may be used as required. The connection member140may redistribute the connection pads122of the semiconductor chip120. The connection pads122of dozens to hundreds of semiconductor chips120having various functions may be redistributed through the connection member140, and may be physically and/or electrically connected to external devices via the electrical connection structure170, depending on functions thereof. The connection member140may include an insulating layer141disposed on the core member110and the active surface of the semiconductor chip120, the redistribution layer142disposed on the insulating layer141, and the via143connecting the connection pad122and the redistribution layer142to each other while penetrating through the insulating layer141. Although the connection member140is illustrated as respectively being comprised of one insulating layer, a redistribution layer, and a via layer in the drawings, the connection member140may also be comprised of a relatively large number of insulating layers, redistribution layers, and via layers. As a material of the insulating layer141, an insulating material may be used. In this case, in addition to the above-described insulating material, a photoimageable dielectric material such as a PID resin may be used. For example, the insulating layer141may be a photoimageable dielectric layer. For example, when the insulating layer141has photoimageable properties, the insulating layer141may be formed to have a reduced thickness, and a fine pitch of the via143may be obtained relatively easily. The insulating layer141may be a photoimageable dielectric layer including an insulating resin and an inorganic filler. For example, when the insulating layer141is comprised of multiple layers, materials of multiple layers may be the same as each other, and as necessary, may be different from each other. When the insulating layer141is comprised of multiple layers, boundaries thereof may be unclear. The redistribution layer142may serve to redistribute the connection pads122, and as a material of the redistribution layer142, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof or the like, may be used. The redistribution layer142may perform various functions according to a design of a relevant layer. For example, the redistribution layer142may include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like. In this case, the signal S pattern may include various signals, for example, data signals, except for a ground (GND) pattern, a power (PWR) pattern, and the like. In addition, a via pad pattern, an electrical connection structure pad pattern, and the like may be included therein. The via143may electrically connect the redistribution layer142, the connection pads122, and the like, formed in different layers, to each other, thereby forming an electrical path in the fan-out semiconductor package100A. As a material of the via143, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The via143may be fully filled with a conductive material, or may be formed by allowing a conductive material to be formed along a wall of a via hole. In addition, any shape known in the art, such as a tapered shape, may be employed. The passivation layer150may protect the connection member140from external physical chemical damage or the like. The passivation layer150may have an opening exposing at least a portion of the redistribution layer142of the connection member140. The opening may be formed as several tens to several thousands of openings in the passivation layer150. A material of the passivation layer150is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin mixture provided by mixing such resins with an inorganic filler or a resin formed by impregnating such resins in a core material such as a glass fiber, a glass cloth, a glass fabric, or the like, together with an inorganic filler, for example, a prepreg resin, Ajinomoto Bulid-up Film (ABF) resin, FR-4 resin, Bismaleimide Triazine (BT) resin, or the like, may be used. Alternatively, a solder resist may also be used. The under-bump metal layer160may improve connection reliability of the electrical connection structure170, and thus, may improve board level reliability of the fan-out semiconductor package100A. The under-bump metal layer160may be connected to the redistribution layer142of the connection member140, exposed through the opening of the passivation layer150. The under-bump metal layer160may be formed in the opening of the passivation layer150using a conductive material, for example, a metal, known in the art, via a metallization method known in the art, but is not limited thereto. The electrical connection structure170may physically and/or electrically connect the fan-out semiconductor package100A to external devices. For example, the fan-out semiconductor package100A may be mounted on a main board of an electronic device via the electrical connection structure170. The electrical connection structure170may be formed of a conductive material, for example, a solder or the like, which is merely provided by way of example. The material thereof is not particularly limited. The electrical connection structure170may be a land, a ball, a pin, or the like. The electrical connection structure170may be formed of multiple layers or a single layer. For example, when the electrical connection structure170is formed of multiple layers, the electrical connection structure170may include a copper pillar and a solder. When the electrical connection structure170is formed of a single layer, the electrical connection structure170may include a tin-silver solder or copper, which is merely provided by way of example, without particular limitation. The number, spacing, arrangement type, and the like of the electrical connection structure170are not particularly limited, and may be sufficiently modified according to design specifications. For example, the number of electrical connection structures170may be in a range of tens to thousands, depending on the number of connection pads122, and may be more or less thereof. For example, when the electrical connection structure170is a solder ball, the electrical connection structure170may cover a side surface of the under-bump metal layer160, formed to extend on one surface of the passivation layer150. In the electrical connection structure170, at least one electrical connection structure170may be disposed in a fan-out region. The fan-out region refers to a region outside a region in which the semiconductor chip120is disposed. A fan-out package may have excellent reliability as compared to that of a fan-in package, may implement a plurality of I/O terminals, and may facilitate 3D interconnection. In addition, the fan-out package may be manufactured to have a reduced thickness, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, and thus, may have excellent price competitiveness. Though not illustrated in the drawings, a metal thin film may be formed on a wall surface of the through hole110H, to radiate heat and/or shield electromagnetic waves, as required. In addition, a plurality of semiconductor chips120performing the same or different functions may be disposed in the through hole110H, as required. Further, a separate passive component, such as an inductor, a capacitor or the like, may be disposed in the through hole110H, as required. In addition, a surface mounting (SMT) component including a passive component, such as an inductor, a capacitor or the like, may also be disposed on a surface of the passivation layer150, as required. FIGS.11A to11Dare schematic views of processes of a method of manufacturing the fan-out semiconductor package ofFIG.9. Referring toFIG.11A, a first insulating layer111amay first be prepared. The first insulating layer111amay be prepared using a copper clad laminate (CCL) provided with copper foils112pformed on two surfaces thereof. Next, a hole may be formed in the first insulating layer111a, using laser drilling and/or mechanical drilling and/or sand blasting, or the like, and then the copper foil112pmay be used as a seed layer to be electrolyzed and/or electroless plated, such that first and second distribution layers112aand112band a first via113amay be formed. Subsequently, a cavity111ahmay be formed in the first insulating layer111a. The cavity111ahmay also be formed using laser drilling and/or mechanical drilling and/or sand blasting, or the like. Next, an adhesive film211may be attached to a lower side of the first insulating layer111a. The adhesive film211may be a tape or the like, including an epoxy resin. Then, one or more dummy structures125may be attached onto the adhesive film211of the cavity111ah. With reference toFIG.11B, a third insulating layer111cmay be formed on the adhesive film211by a laminating method, a coating method, or the like, to cover the dummy structure125and the like. Further, a via hole may be formed in the third insulating layer111cusing laser drilling and/or mechanical drilling and/or sand blasting, or the like, and then a fourth distribution layer112dand a third via113cmay be formed by an electrolytic and/or an electroless plating process. Next, the adhesive film211may be removed. Subsequently, a second insulating layer111bmay be formed on a lower side of the first insulating layer111afrom which the adhesive film211has been removed, by a laminating method, a coating method, or the like. Then, a via hole may be formed in the second insulating layer111b, using laser drilling and/or mechanical drilling and/or sand blasting, or the like, and then, a third distribution layer112cand a second via113bmay be formed in an electrolytic and/or electroless plating process. The core member110may be prepared through a series of processes. Next, a through hole110H may be formed in the core member110using laser drilling and/or mechanical drilling and/or sand blasting, or the like. Referring toFIG.11C, subsequently, an adhesive film212may be attached to a lower side of the core member110. The adhesive film212may be tape or the like, including an epoxy resin. Next, a semiconductor chip120may be attached to the adhesive film212of the through hole110H in a face-down manner. Next, an encapsulant130may be formed on the adhesive film212by a laminating method, a coating method, or the like, to seal the semiconductor chip120and the like. Referring toFIG.11D, next, the adhesive film212may be removed. Then, a connection member140may be formed on a lower side of the core member110from which the adhesive film212has been removed. The connection member140may be formed by forming an insulating layer141using a PID laminating method or a coating method, forming a via hole in the insulating layer141using a photolithography method, and forming a redistribution layer142and a via143using electrolytic plating or electroless plating. Then, a passivation layer150, an under-bump metal layer160, an electrical connection structure170, and the like may be formed on the connection member140, in a manner known in the art, as required. Further, an opening may be formed in an upper portion of the encapsulant130. On the other hand, a series of processes may be performed at a panel level, and in this case, when a dicing process is modified, a plurality of the fan-out semiconductor packages100A may be manufactured in a single process. FIG.12is a schematic cross-sectional view of another example of a fan-out semiconductor package. FIG.13is a schematic cutaway plan view of the fan-out semiconductor package, taken along line II-II′ ofFIG.12. Referring toFIGS.12and13, in a fan-out semiconductor package100B according to another example, a core member110may include a first insulating layer111a, a first distribution layer112aembedded in the first insulating layer111ain such a manner that a lower surface of the first distribution layer112ais exposed, a second distribution layer112bdisposed on a side of the first insulating layer111a, opposing a side of the first insulating layer111ain which the first distribution layer112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second distribution layer112b, and a third distribution layer112cdisposed on the second insulating layer111b. The first to third distribution layers112a,112band112cmay be electrically connected to a connection pad122. The first and second distribution layers112aand112b, and the second and third distribution layers112band112c, may be electrically connected to each other, through first and second vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively. A dummy structure125may be disposed on the first insulating layer111aand may be covered with the second insulating layer111b, which is merely an example. Thus, an arrangement form of the dummy structure125may be changed. For example, the dummy structure125may be embedded in the first insulating layer111a, in such a manner that one surface thereof is exposed, and the dummy structure125may also be disposed in various combinations. For example, when the first distribution layer112ais embedded in the first insulating layer111a, a step generated due to a thickness of the first distribution layer112amay be significantly reduced, and thus, an insulating distance of a connection member140may be constant. For example, a difference between a distance from a redistribution layer142of the connection member140to a lower surface of the first insulating layer111a, and a distance from the redistribution layer142of the connection member140to the connection pad122of a semiconductor chip120, may be less than a thickness of the first distribution layer112a. Thus, a high-density distribution design of the connection member140may be facilitated. A lower surface of the first distribution layer112aof the core member110may be located to be higher than a lower surface of the connection pad122of the semiconductor chip120. A distance between the redistribution layer142of the connection member140and the first distribution layer112aof the core member110may be greater than a distance between the redistribution layer142of the connection member140and the connection pad122of the semiconductor chip120. For example, the lower surface of the first distribution layer112amay have a step with respect to the lower surface of the first insulating layer111a. As described above, for example, when the first distribution layer112ais recessed into the first insulating layer111ato form a step between the lower surface of the first insulating layer111aand the lower surface of the first distribution layer112a, the first distribution layer112amay be prevented from being contaminated due to bleeding of a material of formation of an encapsulant130. The second distribution layer112bof the core member110may be positioned on a level between an active surface and an inactive surface of the semiconductor chip120. The core member110may be formed to have a thickness corresponding to a thickness of the semiconductor chip120, and thus, the second distribution layer112bformed in the core member110may be disposed on a level between the active surface and the inactive surface of the semiconductor chip120. A thickness of each of the distribution layers112a,112band112cof the core member110may be greater than a thickness of the redistribution layer142of the connection member140. The core member110may be manufactured using a general substrate process, and the connection member140may be manufactured using a general semiconductor process. A material of the insulating layers111aand111bis not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin mixture provided by mixing such resins with an inorganic filler or a resin formed by impregnating such resins in a core material such as a glass fiber, a glass cloth, a glass fabric, or the like, together with an inorganic filler, for example, a prepreg resin, Ajinomoto Bulid-up Film (ABF) resin, FR-4 resin, Bismaleimide Triazine (BT) resin, or the like, may be used. A photoimageable dielectric (PID) resin may be used as required. The first to third distribution layers112a,112band112cmay serve to redistribute the connection pads122of the semiconductor chip120. As a material of formation of the first to third distribution layers112a,112band112c, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof or the like, may be used. The first to third distribution layers112a,112band112cmay perform various functions depending on a design of a relevant layer. For example, the first to third distribution layers112a,112band112cmay include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like. In this case, the signal S pattern may include various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, may include data signals and the like. Further, a via pad, a wire pad, an electrical connection structure pad, and the like may be included therein. The first and second vias113aand113bmay electrically connect the first to third distribution layers112a,112band112cformed in different layers, thereby forming an electrical path in the core member110. As a material of formation of the first and second vias113aand113b, a conductive material may be used. The first and second vias113aand113bmay be completely filled with a conductive material, or may be formed by allowing a conductive material to be formed along a wall surface of a via hole. Further, as a shape of the first and second vias113aand113b, any shape known in the art, such as a cylindrical shape or the like, may be used as well as a tapered shape. For example, when a hole for formation of the first via113ais formed, a portion of pads of the first distribution layer112amay serve as a stopper. The first via113amay have a tapered shape in which a width of an upper portion thereof is greater than a width of a lower portion thereof in terms of positive process characteristics. In this case, the first via113amay be integrated with a pad pattern of the second distribution layer112b. In addition, when a hole for the second via113bis formed, a portion of pads of the second distribution layer112bmay serve as a stopper. The second via113bmay have a tapered shape in which a width of an upper portion thereof is greater than a width of a lower portion thereof in terms of positive process characteristics. In this case, the second via113bmay be integrated with a pad pattern of the third distribution layer112c. Other configurations are substantially the same as those described above with respect to the fan-out semiconductor package100A and the like, and thus, a detailed description will be omitted. FIGS.14A to14Dare schematic views of processes of a method of manufacturing the fan-out semiconductor package ofFIG.12. Referring toFIG.14A, first, a carrier substrate220formed by disposing copper foils222on two surfaces of a support layer221may be prepared. Each copper foil222may be comprised of a plurality of layers. Next, a first distribution layer112amay be formed by using the copper foil222of the carrier substrate220as a seed layer via electrolytic or electroless plating. Then, a first insulating layer111amay be formed using a laminating method or a coating method, a hole may be formed in the first insulating layer111ausing laser drilling and/or mechanical drilling and/or sand blasting, or the like, and then, a second distribution layer112band a first via113amay be formed in an electrolytic and/or electroless plating process. Next, one or more dummy structures125may be disposed on the first insulating layer111a. Referring toFIG.14B, a second insulating layer111bmay be formed on the first insulating layer111ausing a laminating method or a coating method, to cover the dummy structures125and the like, a hole may be formed in the second insulating layer111busing laser drilling and/or mechanical drilling and/or sand blasting, or the like, and then, a third distribution layer112cand a second via113bmay be formed in an electrolytic and/or electroless plating process. Next, a core member110manufactured from the carrier substrate220may be separated therefrom. Separating the core member110may correspond to an operation in which the copper foil222comprised of a plurality of layers is separated. After the separation, the copper foil222remaining on a lower surface of the first insulating layer111amay be removed by etching. At this time, a lower side of the first distribution layer112amay be partially removed, in such a manner that a lower surface of the first insulating layer111aand a lower surface of the first distribution layer112amay have a step therebetween. Next, a through hole110H may be formed in the core member110. The through hole110H may be formed using laser drilling and/or mechanical drilling and/or sand blasting, or the like. Referring toFIG.14C, an adhesive film231may be attached to a lower side of the core member110. The adhesive film231may be a tape or the like, including an epoxy resin. Next, a semiconductor chip120may be attached to the adhesive film231of the through hole110H in a face-down manner. Next, an encapsulant130may be formed on the adhesive film231by a laminating method, a coating method, or the like, to seal the semiconductor chip120and the like. Referring toFIG.14D, next, the adhesive film231may be removed. Then, a connection member140may be formed on a lower side of the core member110from which the adhesive film231has been removed. The connection member140may be formed by forming an insulating layer141using a PID lamination method or a coating method, forming a via hole in the insulating layer141using a photolithography method, and forming a redistribution layer142and a via143using electrolytic plating or electroless plating. Then, a passivation layer150, an under-bump metal layer160, an electrical connection structure170, and the like may be formed on the connection member140, in a manner known in the art, as required. Further, an opening may be formed in an upper portion of the encapsulant130. On the other hand, a series of processes may be performed at a panel level, and in this case, when a dicing process is modified, a plurality of the fan-out semiconductor packages100B may be manufactured in a single process. FIG.15is a schematic cross-sectional view of another example of a fan-out semiconductor package. FIG.16is a schematic cutaway plan view of the fan-out semiconductor package, taken along line III-III′ ofFIG.15. Referring toFIGS.15and16, in a fan-out semiconductor package100C according to another example, in a manner similar to the fan-out semiconductor package100B according to the foregoing example, a core member110may include a first insulating layer111a, a first distribution layer112aembedded in the first insulating layer111ain such a manner that a lower surface of the first distribution layer112ais exposed, a second distribution layer112bdisposed on a side of the first insulating layer111a, opposing a side of the first insulating layer111ain which the first distribution layer112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second distribution layer112b, and a third distribution layer112cdisposed on the second insulating layer111b. The first to third distribution layers112a,112band112cmay be electrically connected to a connection pad122. The first and second distribution layers112aand112b, and the second and third distribution layers112band112c, may be electrically connected to each other, through first and second vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively. On the other hand, in the case of a dummy structure125, the dummy structure125may be disposed on the connection member140and may be covered with the first insulating layer111a. For example, the dummy structure125may be embedded in the first insulating layer111ain a manner in which one surface thereof is exposed. Other configurations are substantially the same as those described above with respect to the fan-out semiconductor packages100A and100B, and the like, and thus, detailed descriptions will be omitted. As set forth above, according to an exemplary embodiment, a fan-out semiconductor package having a novel structure, in which a warpage problem may be effectively solved, may be provided. In the present disclosure, the lower side, the lower side, the lower surface, and the like refer to a direction toward a mounting surface of the fan-out semiconductor package, based on a cross section of the drawing for convenience, and the upper side, the upper portion, the upper surface and the like are used in the opposite direction. However, such descriptions are merely for the sake of convenience of description, and the scope of claims is not particularly limited by the description of such directions. The meaning of being connected in the present disclosure encompasses not only a direct connection, but also includes an indirect connection through an adhesive layer or the like. In addition, the term “electrically connected” means a concept including both a physical connection and non-connection. Further, the expressions of the first, second, and the like are used to distinguish one component from another, and do not limit the order and/or importance of the components. In some cases, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The expression, an example, used in this disclosure does not mean the same embodiment, but is provided for emphasizing and explaining different unique features. However, the above-mentioned examples do not exclude being implemented in combination with the features of other examples. For example, although the description in the specific example is not described in another example, it may be understood as an explanation related to another example, unless otherwise described or contradicted by the other example. The terms used in this disclosure are only used to illustrate an example and are not intended to limit the present disclosure. The singular expressions include plural expressions unless the context clearly dictates otherwise. While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims. | 60,746 |
11862575 | DETAILED DESCRIPTION FIG.1is a top view illustrating a seal-ring structure200of a semiconductor device100according to one embodiment of the present disclosure. Referring toFIG.1, the semiconductor device100according to this embodiment of the present disclosure may include the seal-ring structure200surrounding a circuit region CA in for example but not limited to a frame shape. The seal-ring structure200may in general have a closed loop shape disposed close to the edges of the semiconductor device100. Corner portions of the seal-ring structure200may have a chamfered shape. The seal-ring structure200may have a function of preventing and detecting a crack or a peeling of the semiconductor device100. FIG.2is an enlarged top view of region A ofFIG.1. Referring toFIG.2, the seal-ring structure200according to one embodiment of the present disclosure includes an inner seal-ring210surrounding the circuit region CA, an intermediate seal-ring220, and an outer seal-ring230, a crack detection ring250, an inner trench ring270, and an outer trench ring280. The crack detection ring250may surround the inner seal-ring210, the intermediate seal-ring220may surround the crack detection ring250, the inner trench ring270may surround the intermediate seal-ring220, the outer seal-ring230may surround the inner trench ring270, and the outer trench ring280may surround the outer seal-ring230. For example, the crack detection ring250may be disposed between the inner seal-ring210and the intermediate seal-ring220. The inner seal-ring210, the intermediate seal-ring220, the outer seal-ring230, the inner trench ring270, and the outer trench ring280may have a closed loop structure. The crack detection ring250may be an open loop structure. In other embodiments, the intermediate seal-ring220, the outer seal-ring230, the inner trench ring270, and the outer trench ring280may be optionally omitted. The seal-ring structure200may further include a connection part215. The connection part215may electrically connect a first end of the crack detection ring250to the inner seal-ring210. In another embodiment, the first end of the crack detection ring250may be electrically connected to the intermediate seal-ring220. That is, the connection part215may electrically connect the first end of the crack detection ring250to the intermediate seal-ring220. In another embodiment, the first end of the crack detection ring250may be electrically connected to both the inner seal-ring210and the intermediate seal-ring220. The seal-ring structure200may further include an extension part251and an input pad255as a structure for detecting a crack. A second end of the crack detection ring250may be connected to the input pad255through the extension part251. The extension part251may cross the inner seal-ring210. The extension part251and the inner seal-ring210may be not directly connected. The input pad255may be disposed in the circuit region CA. Voltage or current may be provided from the input pad255to the crack detection ring250through the extension part251. The voltage or current passing through the crack detection ring250may be provided to the inner seal-ring210or to the intermediate seal-ring220through the connection part215. The voltage or current passing through the inner seal-ring210or the intermediate seal-ring220may be grounded. FIG.3is a longitudinal cross-sectional view taken along line I-I′ ofFIG.2. Referring toFIG.3, the inner seal-ring210according to one embodiment of the present disclosure may include an inner doped region11, a multilayer of inner via patterns12ato12d, and a multilayer of inner wiring patterns13ato13d. The inner doped region11may be formed in an upper substrate111. The upper substrate111may include a monocrystalline silicon layer. In one embodiment, the upper substrate111may be a silicon layer on which a photodiode of an image sensor is formed. The inner doped region11may include N-type ions or P-type ions. The inner doped region11may be formed at the same level as a common source region of the image sensor. The inner wiring patterns13ato13dformed in the upper interlayer insulating layer115formed on a surface of the upper substrate111may be disposed to extend parallel to each other in a horizontal direction. The inner via patterns12ato12dmay extend parallel to each other in a vertical direction so as to electrically connect the inner wiring patterns13ato13dto each other. The inner via patterns12ato12dmay include first to fourth inner via patterns12ato12dwhich are vertically aligned, and the inner wiring patterns13ato13dmay include first to fourth inner wiring patterns13ato13d. Each of the inner via patterns12ato12dand the inner wiring patterns13ato13dmay include metal. The inner doped region11and the inner wiring patterns13ato13dmay extend in a horizontal direction in the shape of a parallel rail or lines. The inner doped region11, the inner via patterns12ato12d, and the inner wiring patterns13ato13dmay form a mesh shape. The inner seal-ring210may be surrounded with the upper interlayer insulating layer115. The upper interlayer insulating layer115may include an insulating material such as silicon oxide or silicon nitride. In one embodiment, the semiconductor device100may further include an inner grid wiring19. The inner grid wiring19may be disposed on an upper surface of the semiconductor device100, for example, on an upper surface of the upper substrate111. The inner grid wiring19may be parallel to the inner seal-ring210. For example, the inner grid wiring19and the inner seal-ring210may vertically overlap. The inner grid wiring19may include the same material as a grid pattern dividing unit pixels of an image sensor device. The inner grid wiring19and the grid pattern may be formed at the same level. Some of the fourth inner via patterns12dand the fourth inner wiring patterns13dmay be omitted so that the extension part251may be disposed. FIG.4is a longitudinal cross-sectional view taken along line II-II′ ofFIG.2. Referring toFIG.4, the crack detection ring250according to one embodiment of the present disclosure may have a serpentine concatenate. The crack detection ring250may include a crack detection doped region51, crack detection via patterns52ato52d, and crack detection pad patterns53ato53d. The crack detection doped region51may be formed in the upper substrate111. The crack detection doped region51may include N-type ions or P-type ions. For example, the crack detection via patterns52ato52dmay include first to fourth crack detection via patterns52ato52dwhich are vertically aligned. The crack detection pad patterns53ato53dmay include first to fourth crack detection pad patterns53ato53d. The crack detection via patterns52ato52dand the crack detection pad patterns53ato53dmay each include a metal. The crack detection via patterns52ato52dand the crack detection pad patterns53ato53dmay provide a vertical and electrical connection. The crack detection doped regions51and the fourth crack detection pad pattern53dat the lowermost level among the crack detection pad patterns53ato53dmay provide horizontal electrical connection. Each of the crack detection doped regions51may horizontally and electrically connect two adjacent first crack detection via patterns52a. Each of the fourth crack detection pad patterns53dspaced apart from the upper substrate111may horizontally and electrically connect two adjacent fourth crack detection via patterns52d. For example, each of the first crack detection via patterns52amay vertically and electrically connect the crack detection doped region51to the first crack detection pad pattern53a. Each of the second crack detection via patterns52bmay vertically and electrically connect the first crack detection pad pattern53ato the second crack detection pad pattern53b. Each of the third crack detection via patterns52cmay vertically and electrically connect the second crack detection pad pattern53bto the third crack detection pad pattern53c. Each of the fourth crack detection via patterns52dmay vertically and electrically connect the third crack detection pad pattern53cto the fourth crack detection pad pattern53d. In another embodiment, the number of the crack detection via patterns52ato52dand the crack detection pad patterns53ato53dmay be greater than the number illustrated in the drawings. The crack detection via patterns52ato52dand the crack detection pad patterns53ato53dmay be filled with the upper interlayer insulating layer115. Since the crack detection ring250can have an open loop structure, the fourth crack detection pad patterns53dmay not horizontally connect the adjacent fourth crack detection via patterns52din some regions. In another embodiment, the crack detection doped region51may not horizontally connect adjacent first crack detection via patterns52ain some regions. FIGS.5A to5Eare longitudinal cross-sectional views taken along line III-III′ ofFIG.2. Referring toFIGS.5A to5E, the seal-ring structure200according to one embodiment of the present disclosure may include an inner seal-ring210, an intermediate seal-ring220, and a crack detection ring250. As described above, the inner seal-ring210may include an inner doped region11, inner via patterns12ato12d, and inner wiring patterns13ato13d. The intermediate seal-ring220may include an intermediate doped region21, intermediate via patterns22ato22d, and intermediate wiring patterns23ato23d. A plurality of intermediate via patterns22ato22dmay be disposed at the same level, respectively. The plurality of intermediate via patterns22ato22dmay be commonly connected to the same intermediate wiring patterns23ato23ddisposed at the upper and lower portions, respectively. The inner via patterns12ato12dand the intermediate via patterns22ato22dmay form a plurality of multi-level pillar shapes. The inner wiring patterns13ato13dand the intermediate wiring patterns23ato23dmay form a plurality of multi-level bar shapes parallel to a horizontal direction. Accordingly, in a top view, the inner via patterns12ato12dand the intermediate via patterns22ato22dmay have the shape of islands arranged in a lattice structure, and the inner wiring patterns13ato13dand the intermediate wiring patterns23ato23dmay have a long stripe or beltway shape. Referring toFIG.5A, the inner doped region11and the crack detection doped region51may be electrically connected. For example, the connection part215amay electrically connect the inner doped region11and the crack detection doped region51. In another embodiment, the connection part215amay be omitted. For example, the inner doped region11and the crack detection doped region51may be electrically connected through the upper substrate111. Referring toFIG.5B, the first inner wiring pattern13aand the first crack detection pad pattern53amay be electrically connected. For example, the connection part215bmay electrically connect the first inner wiring pattern13aand the first crack detection pad pattern53a. Referring toFIG.5C, the second inner wiring pattern13band the second crack detection pad pattern53bmay be electrically connected. For example, the connection part215cmay electrically connect the second inner wiring pattern13band the second crack detection pad pattern53b. Referring toFIG.5D, the third inner wiring pattern13cand the third crack detection pad pattern53cmay be electrically connected. For example, the connection part215dmay electrically connect the third inner wiring pattern13cand the third crack detection pad pattern53c. Referring toFIG.5E, the fourth inner wiring pattern13dand the fourth crack detection pad pattern53dmay be electrically connected. For example, the connection part215emay electrically connect the fourth inner wiring pattern13dand the fourth crack detection pad pattern53d. The inventive concepts of the present disclosure illustrated inFIGS.5A to5Emay be applied exclusively or selectively. In one embodiment, two or more technical features of the present disclosure shown inFIGS.5A to5Emay be combined. As mentioned above, in other embodiments, the first to fourth intermediate wiring patterns23ato23dmay be selectively and electrically connected to the first to fourth crack detection pad patterns53ato53d, respectively. FIG.6is a longitudinal cross-sectional view taken along line IV-IV′ ofFIG.2. Referring toFIG.6, the crack detection ring250according to one embodiment of the present disclosure may be electrically connected to the input pad255. For example, the fourth crack detection pad pattern53dand the input pad255may be connected through the extension part251. In some areas, the fourth inner via patterns12dand the fourth inner wiring patterns13dof the inner seal-ring210may be partially removed for the extension part251. Referring toFIGS.1to6, the voltage or current provided from the input pad255may be provided to the upper substrate111through the crack detection ring250and the inner seal-ring210and may be grounded through the upper substrate111. Accordingly, a crack or peeling of the semiconductor device100may be detected by measuring the voltage or current discharged from the input pad255to the upper substrate111. When a crack or a peel in the semiconductor device100occurs, a current supplied to the semiconductor device100has to flow around the cracked or peeled area disrupting the voltage distributions from a non-cracked or non-peeled structure. Deviations of the measured voltage distributions from a normal condition (i.e., that is deviations from a non-cracked or non-peeled structure) provide a way to detect the presence of a crack or a peel in the semiconductor device100. In addition, by measuring the levels of voltage or current from the normal condition, the degree of a crack and peeling may also be predicted. FIG.7is a longitudinal cross-sectional view taken along line V-V′ ofFIG.2. Referring toFIG.7, the seal-ring structure200of the semiconductor device100according to one embodiment of the present disclosure may include the inner seal-ring210, the intermediate seal-ring220, and the outer seal-ring230, the crack detection ring250, the inner trench ring270, and the outer trench ring280. The intermediate seal-ring220and the outer seal-ring230may have the same vertical cross-sectional structure as the inner seal-ring210. For example, the outer seal-ring230may include an outer doped region31, outer via patterns32ato32d, and outer wiring patterns33ato33d. Further referring back toFIGS.5A to5EandFIG.6, the fourth via patterns22dand32d, and the fourth wiring patterns23dand33dof the intermediate seal-ring220and the outer seal-ring230may be not omitted. Therefore, the semiconductor device100may further include an intermediate grid wiring29which is vertically aligned to the intermediate seal-ring220, and may include an outer grid wiring39which is vertically aligned to the outer seal-ring230. The inner trench ring270and the outer trench ring280may each have a plurality of full deep trench isolation (FDTI) structures. The FDTI structure may include trenches, inside of which is filled with an insulating material, completely penetrating from a top to bottom surface of the upper substrate111. The inner trench ring270and the outer trench ring280may absorb and block physical and chemical attack, e.g., propagation of cracks, applied to the upper substrate111. Accordingly, the inner trench ring270and the outer trench ring280may prevent and mitigate cracking of the upper substrate111. FIG.8is a top view showing the electrical connection of a seal-ring structure200B according to one embodiment of the present disclosure. The inner trench ring270and the outer trench ring280ofFIG.2have been omitted to better explain technical features of the present disclosure. Referring toFIG.8, the seal-ring structure200B according to one embodiment of the present disclosure includes an inner seal-ring210, an intermediate seal-ring220, an outer seal-ring230, and a crack detection ring250, and a plurality of crack detection structures60ato60d. The crack detection ring250may have a closed loop structure. Referring toFIG.2andFIGS.5A to5E, the crack detection ring250and the inner seal-ring210, or the crack detection ring250and the intermediate seal-ring220may be electrically connected. In another embodiment, the crack detection ring250and the inner seal-ring210, or the crack detection ring250and the intermediate seal-ring220may not be electrically connected. For example, it is shown that the seal-ring structure200B has first to fourth crack detection structures60ato60dconnected to four sides (i.e., the upper side, the lower side, the left side, and the right side) of the crack detection ring250, respectively. Each of the first to fourth crack detection structures60ato60dmay independently provide voltage or current to the crack detection ring250. Each of the first to fourth crack detection structures60ato60dmay independently detect and measure voltage or current from the crack detection ring250. In one embodiment, the first to fourth crack detection structures60ato60dmay be spaced apart from each other at equal or otherwise predetermined intervals. The seal-ring structure200B may selectively include two or more of the crack detection structures60ato60d. In another embodiment, the seal-ring structure200B may include more crack detection structures than crack detection structures60ato60dshown in the drawing. FIG.9is a longitudinal cross-sectional view illustrating a semiconductor device100according to one embodiment of the present disclosure having the seal-ring structure200B ofFIG.8. Referring toFIG.9, the semiconductor device100according to this embodiment of the present disclosure may include an inner seal-ring210, an intermediate seal-ring220, an outer seal-ring230, and a crack detection ring250, inner and outer trench rings270and280, and a crack detection structure60. The crack detection structure60may be formed on a lower substrate112. The crack detection structure60may include a control unit for providing voltage or an operation unit for detecting voltage. Accordingly, the crack detection structure60may include a plurality of transistors. In addition, the crack detection structure60may be electrically connected to the input pad255by a through via plug259. The through via plug259may vertically penetrate a lower interlayer insulating layer116and a bonding insulating layer117to electrically connect the lower substrate112and the input pad255. The lower substrate112may include a monocrystalline silicon layer. The lower interlayer insulating layer116may include an insulating material such as for example a silicon oxide or a silicon nitride. The bonding insulating layer117may include silicon oxide such as for example a high-density plasma oxide (HDP oxide). With further reference toFIG.8, a crack detection operation for detecting and estimating the crack location may include operating one of the first to fourth crack detection structures60ato60din a voltage providing mode and operating three of the first to fourth crack detection structures60ato60din an operation and measurement mode. For example, the crack detection operation may selectively perform a first crack detection operation, a second crack detection operation, a third crack detection operation, a fourth crack detection operation. The first crack detection operation uses the first crack detection structure60aas a voltage provider and uses the second to fourth crack detection structures60bto60das a voltage meter. The second crack detection operation uses the second crack detection structure60bas a voltage provider and uses the first, third, and fourth crack detection structures60a,60c, and60das a voltage meter. The third crack detection operation uses the third crack detection structure60cas a voltage provider and uses the first, second, and fourth crack detection structures60a,60b, and60das a voltage meter. The fourth third crack detection operation uses the fourth crack detection structure60das a voltage provider and uses the first to third crack detection structures60ato60cas a voltage meter. For example, in the operation and measurement mode, the first to fourth crack detection structures60ato60dmay operate as comparators. Accordingly, the first to fourth crack detection structures60ato60dmay have a voltage providing function and a voltage measuring function. For example, each of the first to fourth crack detection structures60ato60dmay include a pull-up transistor for providing a voltage and a comparator for measuring a voltage. The crack detection operation may include at least two or more of the first to fourth crack detection operations. For example, the location of the crack may be detected or estimated by only two crack detection operations. FIG.10is a three-dimensional circuit diagram conceptually illustrating the crack detection ring250and the crack detection structures60ato60dofFIGS.8and9. Referring toFIG.10, the crack detection ring250may have a closed loop structure, and crack detection circuits60ato60dmay be connected to four points of the crack detection ring250, respectively. The first to fourth crack detection structures60ato60dofFIG.8may include respective control units61ato61d(i.e., that is respective controllers or control circuits) and respective operation units62ato62d(i.e., that is respective operators or operator circuits). As described above, the control units61ato61dmay include a transistor connected to the power supply unit V to provide voltage or current to the crack detection ring250. A pull-up transistor may include one or more of PMOS or NMOS. For example, it is assumed that each of the control units61ato61dincludes one NMOS transistor. The operation units62ato62dmay include comparators for detecting and measuring voltage or current from the crack detection ring250. For example, each of the comparators may include a positive (+) input terminal receiving a reference voltage or a reference current, a negative (−) input terminal receiving a detection voltage or a detection current from the crack detection ring250, and an output terminal. Accordingly, a difference between the reference voltage and the detection voltage received from the crack detection ring250or a difference between the reference current and the detection current received from the crack detection ring250may be output at the output terminal. In addition, the first to fourth crack detection structures60ato60dmay further include first to fourth load resistors Ra to Rd connected between the negative (−) input terminals of the comparator and the ground. The first to fourth load resistors Ra to Rd may have the same resistance value or otherwise known resistance values. For example, the crack location may be estimated through the following operations. Performing First Crack Detection Operation The first control unit61a: turn-on, the first operation unit62a: turn-off The second control unit61b: turn-off, the second operation unit62b: turn-on The third control unit61c: turn-off, the third operation unit62c: turn-on The fourth control unit61d: turn-off, the fourth operation unit62d: turn-on Voltage or current may be provided to the crack detection ring250from the power supply unit V by turning-on the first control unit61a. The voltage or the current passed through the crack detection ring250may be measured by turning on the second to fourth operation units62bto62d. By comparing measured values, the location of the crack may be estimated. For example, if the voltage or current measured at the second operation unit62bis higher than the voltage or current measured at the fourth operation unit62d, it may be estimated that a crack has occurred in region (a) of the crack detection ring250disposed between the first crack detection structure (60a;61a,62a) and the fourth crack detection structure (60d;61b,62d) or in a region (c) of the crack detection ring250disposed between the second crack detection structure (60b;61b,62b) and the third crack detection structure (60c;61c,62c). If a crack has occurred in the region (a) of the crack detection ring250, the voltage or current passed through the region (b) of the crack detection ring250will be measured at the second operation unit62band the voltage or current passed through regions (b), (c), and (d) of the crack detection ring250will be measured at the fourth operation unit62d. Thus, the voltage or current measured at the fourth operation unit62dmay be lower than the voltage or current measured at the second operation unit62b. If a crack occurs in a region (c) of the crack detection ring250, the second operation unit62bwill measure the voltage or current that has passed through the region (b) of the crack detection ring250, and the voltage or current measured at the fourth operation unit62dwill be lower than the voltage or current measured at the second operation unit62bbecause the fourth operation unit62dneeds to provide voltage or current toward the third operation unit62c. Performing Second Crack Detection Operation The first control unit61a: turn-off, the first operation unit62a: turn-on The second control unit61b: turn-on, the second operation unit62b: turn-off The third control unit61c: turn-off, the third operation unit62c: turn-on The fourth control unit61d: turn-off, the fourth operation unit62d: turn-on The second control unit61bmay be turned on to provide voltage or current from the power supply unit V to the crack detection ring250. The first, third, and fourth operation units62a,62c, and62dmay be turned on to measure the voltage or current that has passed through the crack detection ring250. By comparing the measured values, the location of a crack may be more accurately estimated. For example, if the voltage or current measured at the first operation unit62ais higher than the voltage or current measured at the third operation unit62c, it may be estimated that a crack has occurred in the region (a) of the crack detection ring250between the first crack detection structure (60a;61a,62a) and the fourth crack detection structure (60d;61d,62d). If a crack has occurred in the region (a) of the crack detection ring250, the voltage or current that has passed through the area (b) of the crack detection ring250will be measured in the first operation unit62a. Because the third operation unit62cneeds to provide voltage or current toward the fourth operation unit62d, the voltage or current measured at the third operation unit62cwill be lower than the voltage or current measured at the first operation unit62a. Conversely, it may be estimated that a crack has occurred in the region (c) of the crack detection ring250between the second crack detection structure (60b;61b,62b) and the third crack detection structure (60c;61c,62c) if the voltage or current measured at the third operation unit62cis higher than the voltage or current measured at the first operation unit62a. The crack location may be more accurately estimated by further performing the third and fourth crack detection operations. The crack location may be accurately estimated by this measurement principle. In particular, the size of a crack generated may be further estimated according to the voltage or current detected because a comparator is used in the technical feature of the present disclosure. FIG.11is a top view illustrating the electrical connection of a seal-ring structure200C according to another embodiment of the present disclosure. The inner trench ring270and the outer trench ring280ofFIG.2have been omitted. Referring toFIG.11, the seal-ring structure200C according to this embodiment of the present disclosure may include an inner seal-ring210, an intermediate seal-ring220, an outer seal-ring230, and a crack detection ring250, and a plurality of crack detection structures61ato61dand62ato62d. For example, the plurality of crack detection structures61ato61dand62ato62dmay include first to fourth control units61ato61dand first to fourth operation units62ato62d. In one embodiment, the first to fourth control units61ato61dand the first to fourth operation units62ato62dmay be spaced apart from each other at equal intervals or at otherwise known intervals. Each of the first to fourth control units61ato61dmay independently provide voltage or current to the crack detection ring250and may independently detect voltage or current from the crack detection ring250. In another embodiment, the plurality of crack detection structures61ato61dand62ato62dmay include at least four control units61ato61dand at least four operation units62ato62d. FIG.12is a three-dimensional circuit diagram conceptually illustrating the crack detection ring250and the crack detection structures61ato61dand62ato62dofFIG.11. Referring toFIG.12, the crack detection ring250may have a closed loop structure. The first to fourth control units61ato61dand the first to fourth operation units62ato62dmay be connected to multiple points of the crack detection ring250, respectively. Connection points between the first to fourth control units61ato61dand the crack detection ring250and connection points between the first to fourth operation units62ato62dand the crack detection ring250may be alternately arranged at equal intervals. That is, in one embodiment, the distance between the connection points may be the same. As described above, the control units61ato61dmay provide voltage or current from the power supply unit V to the crack detection ring250. For example, it is assumed that each of the control units61ato61dincludes one NMOS transistor. In another embodiment, the control units61ato61dmay include a PMOS transistor. The operation units62ato62dmay include comparators for detecting and measuring voltage or current from the crack detection ring250. For example, the comparators may include a positive (+) input terminal to which a reference voltage is input, a negative (−) input terminal to which a voltage is input from the crack detection ring250, and output terminals out1to out4from which a compared value is output. In addition, the operation units62ato62dmay further include the load resistors Ra to Rd connected to the crack detection ring250and the negative (−) input terminals. The load resistors Ra to Rd may have the same resistance value, and may be grounded. The crack detection ring250illustrated inFIG.12may include eight divided regions a1, a2, b1, b2, c1, c2, d1, and d2between the control units61ato61dand the operation units62ato62d. The crack detection operation may include selectively performing the first to fourth crack detection operations. For example, the first crack detection operation may include applying voltage or current to the crack detection ring250by turning on the first control unit61aand turning off the second to fourth control units61bto61dand measuring the voltage or current by turning on the first to fourth operation units62ato62d. The second crack detection operation may include applying voltage or current to the crack detection ring250by turning on the second control unit61band turning off the first, third, and fourth control units61a,61c, and61dand measuring the voltage or current by turning on the first to fourth operation units62ato62d. The third crack detection operation may include applying voltage or current to the crack detection ring250by turning on the third control unit61cand by turning off the first, second, and fourth control units61a,61b, and61dand measuring the voltage or current by turning on the first to fourth operation units62ato62d. The fourth crack detection operation may include applying voltage or current to the crack detection ring250by turning on the fourth control unit61dand turning off the first to third control units61ato61cand measuring the voltage or current by turning on the first to fourth operation units62ato62d. For example, a crack location may be detected or estimated performing the operations described below. Performing First Crack Detection Operation The first control unit61a: turn-on The second to the fourth control units61bto61d: turn-off The first to fourth operation units62ato62d: turn-on If the voltage or current measured at the first operation unit62ais greater than the voltage or current measured at the fourth operation unit62d, it may be estimated that a crack has occurred in a region (a2), region (b1), or region (d2) of the crack detection ring250. Alternatively, if the voltage or current measured at the first operation unit62ais lower than the voltage or current measured at the fourth operation unit62d, it may be estimated that a crack has occurred in a region (a1), region (c2), or region (d1). Performing Second Crack Detection Operation The second control unit61b: turn-on The first, third, and fourth control units61a,61c, and61d: turn-off The first to fourth operation units62ato62d: turn-on If the voltage or current measured at the first operation unit62ais greater than the voltage or current measured at the fourth operation unit62din the first crack detection operation and the voltage or current measured at the first operation unit62ais greater than the voltage or current measured at the second operation unit62bin the second crack detection operation, it may be estimated that a crack has occurred in the region (b1) or region (d2) of the crack detection ring250. In other words, it may be estimated that no crack has occurred in the region (a). Alternately, if the voltage or current measured at the first operation unit62ais greater than the voltage or current measured at the fourth operation unit62din the first crack detection operation, and the voltage or current measured at the first operation unit62ais lower than the voltage or current measured at the second operation unit62b, it may be estimated that a crack has occurred in the region (a2) of the crack detection ring250. Performing Third Crack Detection Operation The third control unit61c: turn-on The first, second, and fourth control units61a,61b, and61d: turn-off The first to fourth operation units62ato62d: turn-on If the voltage or current measured at the first operation unit62ais greater than the voltage or current measured at the fourth operation unit62din the first crack detection operation, the voltage or current measured at the first operation unit62agreater than the voltage or current measured at the second operation62bin the second crack detection operation, and the voltage or current measured in the second operation unit62bis greater than the voltage or current measured at the third operation unit62cin the third crack detection operation, it may be estimated that a crack has occurred in the region (b1) of the crack detection ring. Alternatively, after performing the second crack detection operation, the third crack detection operation may be omitted and the fourth crack detection operation may be performed. Performing Fourth Crack Detection Operation The fourth control unit61d: turn-on The first to third control units61ato61c: turn-off The first to fourth operation units62ato62d: turn-on If the voltage or current measured at the first operation unit62ais greater than the voltage or current measured at the fourth operation unit62din the first crack detection operation, the voltage and current measured at the first operation unit62ais greater than the voltage or current measured at the second operation unit62bin the second crack detection operation, and the voltage or current measured at the third operation unit62cis lower than the voltage or current measured at the fourth operation unit62d, it may be estimated that a crack has occurred in the region (d2) of the crack detection ring. Even when a crack occurs in multiple locations, an accurate crack location may be estimated by comparing the voltages or currents measured at the first to fourth operation units62ato62daccording to the crack detection operations described above. FIG.13is a three-dimensional circuit diagram conceptually illustrating the crack detection ring250and the crack detection structures61ato61dand62ato62dofFIG.11. Referring toFIG.13, the semiconductor device100may further include a decoding unit61for controlling the first to fourth control units61ato61dand selectors65for providing reference voltage to the positive (+) input terminal of the first to fourth operation units62ato62d. The decoding unit61may independently turn on and turn off each of the four control units61ato61dby receiving a control signal of two bits. The decoding unit may reduce the number of routing wires for independently controlling the control units61ato61d. The selectors65may variously adjust the levels of the reference voltage provided to the operation units62ato62d, for example, the positive (+) input terminals of the comparators. FIG.14is a circuit diagram conceptually illustrating the selectors65ofFIG.13. Referring toFIG.14, the selector65may include a resistance string66and an active transistor67, switches SW and a switch controller68, and a self-bias transistor69. The resistance string66and the active transistor67may be connected in series between the power supply unit V and the ground. The resistance string66may include a plurality of resistance elements R0to R5. The resistance string66may divide the power supply voltage into a plurality of levels. The active transistor67may be turned on to activate the selector65. For example, when the active transistor67is turned on, voltage or current may be provided to the resistance elements R0to R5of the resistance string66, and nodes between the resistance elements R0to R5may have multiple voltage levels. The switches SW may be connected to the nodes between the resistance elements R0to R5of the resistance string66, respectively. The switch controller68may selectively turn on the switches SW. Accordingly, various voltage levels of the nodes between the resistance elements R0to R5of the resistance strings66may be selectively provided to the positive (+) input terminal of the operation unit62. The switch controller68may also perform a decoding operation. Accordingly, the number of wiring routings for turning on the switches SW may be minimized. The gate electrode of the self-bias transistor69may be electrically connected to one of the nodes between the resistance elements R0-R5of the resistance string66. For example, gate electrode of the self-bias transistor69may be connected to a node between the base resistance element R0and the first resistance element R1. A first source/drain electrode of the self-bias transistor69may be connected to the current source node of the operation unit62, and a second source/drain electrode of the self-bias transistor69may be grounded. Accordingly, reference voltage of various levels may be input to the positive (+) input terminal of the operation unit62, and an output of the operation unit62may have one of a plurality of voltage levels. That is, the operation unit62according to the present disclosure may perform an analog operation. Although the present invention has been specifically described according to the above-described preferred embodiments, it should be noted that the above-described embodiments are for the purpose of explanation and not for the limitation thereof. In addition, it will be appreciated by person having ordinary skill in the art that various embodiments are possible within the scope of the present invention. | 39,442 |
11862576 | DETAILED DESCRIPTION Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure. Also, the terms “connected to” or “connected with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “connects” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect connecting, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. Disclosed aspects can be implemented by changing the top metal layer by adding Cu or other metal such as aluminum metal features which function to reduce wafer warpage, where the metal features comprise the top metal layer, and/or the metal features are on a dielectric layer that is on the top metal layer. The metal features are located in positions to be electrically isolated from the top metal layer, and any other metal that may be in other metal layers that is connected to circuitry on the semiconductor die being electrically isolated minimizes (or essentially eliminate) the possible effect of the metal features on the electrical performance of the semiconductor die. The disclosed metal features are generally shaped as strips meaning being rectangular in shape, or related shapes including elliptical excluding circular or an X or another shape, as long as the length direction of the metal features are at least essentially perpendicular to the primary orientation of the top metal layer to counteract the direction of warpage. Essentially perpendicular as used herein means the metal features have their length direction oriented at an angle of 90°±5° thus being perpendicular or essentially perpendicular to the primary orientation (length direction) of the top metal layer, to thus be positioned to help prevent the warpage curvature of the wafer during assembly thermal processing, and thus the semiconductor die on the wafer. Disclosed metal features when they utilize the top metal layer itself can be produced by modifying the reticle design for the top metal layer. In this arrangement, there is no additional processing needed to add disclosed metal features. Another disclosed option for the metal features is to form the metal features on another metal layer that is on top of a dielectric layer which is on the top metal layer, such as for a WCSP die on the upper PI layer above the top of the RDL. Metal features above the top metal layer can be implemented by adding an additional photolithography and a plating process to position the metal features after RDL deposition (plating) on the upper PI layer. The disclosed metal features functioning as warpage prevention structures can reduce wafer-level warpage without any process modification. Moreover, the metal features are electrically isolated from the interconnect levels which means that they will not measurably affect the electrical performance of the semiconductor die. For forming WCSP die a standard PI process and a standard copper plating process can be used with only modification of the RDL design to add metal features functioning as warpage prevention structures. As used herein, the term primary orientation is defined as a top metal orientation that collectively represents at least 50% of the total length of all of the top metal lines. It is recognized herein that most semiconductor die have top metal lines configured in a primary orientation. To implement disclosed aspects there is generally an initial evaluation of the top metal layer to determine its primary orientation, where the direction of wafer warpage which has been found to be at an angle of about 90° relative to the primary orientation, where 90° relative to the primary orientation may be considered a wafer warpage direction. By placing disclosed metal features so that they are essentially perpendicular (90°±5°) to the primary orientation, the metal features are thus parallel to the wafer warpage direction which has been found to counteract these stresses in the wafer warpage direction, thus reducing wafer warpage. FIG.1is a cross-sectional view of an example semiconductor die100comprising a substrate105comprising circuitry180including disclosed metal features. There is a metal stack125on a surface of the substrate105, and a top metal layer130shown damascened into a top dielectric layer141. Alternatively, such as in the case that the top metal layer130comprises aluminum, although not shown, the top dielectric layer141can be formed on the top metal layer130. The metal stack125generally represents a plurality of metal interconnect layers above semiconductor surface of the substrate105each including metal layer and a dielectric layer, generally having filled vias through these dielectric layers that are below the top metal layer130. The top metal layer130includes a bond pad130a. On top of the bond pad130athere is bonding feature136comprising a pillar that may comprise copper. Alternatively, for the bonding feature, a UBM layer can further include a solder ball thereon. There are metal features135on the same level as the top metal layer130positioned lateral to the top metal layer130. There are also metal features138shown positioned above the top dielectric layer141shown positioned lateral to the top metal layer130. Although not shown, the respective metal features135,138are generally positioned over gaps (being only over the anterior level dielectric (ILD)) in the metal stack125. FIG.2is a cross-sectional view of a WCSP die200comprising a substrate105including circuitry180, having a metal stack225on a top surface of the substrate105, further comprising a top-level metal layer comprising an RDL230that is between a bottom dielectric layer243and a top dielectric layer245, that may both comprise PI, and there are disclosed metal features235and238, according to an example aspect. The metal features238are shown on the top dielectric layer245and having a rectangular shape, and the metal features235that are part of the RDL230can also have a rectangular shape. The metal features238generally have a minimum thickness of 6 μms. There is a die bond pad226formed from the metal layer at the top of the metal stack225. The RDL230extends laterally to a bump area that includes a UBM layer261over the RDL230having a solder bump263over the UBM layer261. FIGS.3A-Fshows successive cross-sectional views of a top layer of an in-process semiconductor die involved in forming disclosed metal features functioning as warpage prevention structures corresponding to results following steps in an example method that comprises a one pass integration for forming the warpage prevention structures using the top metal layer.FIG.3Ashows the results after photoresist coating provide a photoresist layer351on a wafer comprising a plurality of semiconductor die comprising a substrate105having circuitry180and a metal stack thereon315that does not include the semiconductor die's top metal layer formed later in the process as described below.FIG.3Bshows the results after an exposure step for exposing the photoresist layer351to provide first photoresist regions351afor the top metal layer which will be connected to the circuitry180and second photoresist regions351bfor the metal features positioned lateral to the top metal layer portions that will be connected to the circuitry180. A customized reticle having a disclosed metal features may be used for the exposure step. FIG.3Cshows results after a develop step that patterns the photoresist layer351to provide first regions356a(generally on top of a via of the metal stack315that has a top dielectric layer thereover which is not shown) and second regions356bthat have a length direction that is essentially perpendicular to the primary orientation of the top metal layer described relative toFIG.3D.FIG.3Dshows results after plating a metal to form a top metal layer, such as copper, in the first regions shown as335that includes an electrical connection to the circuitry180, and in the second regions which are on the top dielectric layer where there are disclosed metal features shown as338. The forming of a seed layer may proceed the plating step.FIG.3Eshows results after stripping the photoresist351. FIG.4A-Ishows successive cross-sectional views of a top layer of a wafer including a plurality of in-process ICs involved in forming disclosed metal features functioning as electrically isolated warpage prevention structures corresponding to results following steps in another example method that comprises a two-pass integration for forming a semiconductor die having warpage prevention structures positioned above the substrate surface. FIG.4Ashows the results after photoresist coating form a photoresist layer451on the substrate105including circuitry180and a metal stack thereon not yet including its top metal layer shown collectively as415.FIG.4Bshows the results after an exposure step for exposing the photoresist layer451provide a photoresist regions451afor defining the top metal layer which will be connected by the metal stack415to the circuitry180. A customized reticle having a disclosed metal features may be used for the exposure step.FIG.4Cshows results after a develop step to provide patterned photoresist451including open regions456.FIG.4Dshows results shows results after plating a metal to form a top metal layer, such as copper, in the open regions456, shown as top metal region435. As noted above a seed layer may be deposited before the plating. The photoresist layer451is then stripped off and then a dielectric layer461is then formed, such as being deposited, shown positioned over the top metal region435. The dielectric layer461provides electric isolation between the top metal region435and the metal features that are formed as described below.FIG.4Eafter shows the results after coating a photoresist layer457including over the dielectric layer461.FIG.4Fshows results after exposing the photoresist layer457to form exposed regions457a.FIG.4Gshows results after developing off of the exposed regions to provide open regions476. The open regions476although due to the cross-section view are shown over the top metal region435, where the open regions are not over the top metal regions435.FIG.4Hshows results after plating form the metal features438in the open regions476.FIG.4Ishows the results after stripping off the photoresist457. FIGS.5A and5Bshow both options for the metal features showing a top metal layer being a copper on anything (COA) layer520having disclosed metal features535inFIG.5A and538inFIG.5B, all having their length direction oriented 90° relative to an orientation of the lines of the COA layer520shown. For the metal features535, the same metal level as the COA layer520is used. For metal features538that are on a dielectric layer557, a separate metallization step, such as plating, is used to form the metal features538. Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different semiconductor packages and related products. The semiconductor package can comprise single IC die or multiple IC die, such as configurations comprising a plurality of stacked IC die, or laterally positioned IC die. A variety of package substrates may be used. The IC die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the IC die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS. Those skilled in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions, and modifications may be made to the above-described aspects without departing from the scope of this Disclosure. | 12,676 |
11862577 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIGS.1A through1Jillustrate cross-sectional views of intermediate steps during a process for forming a device package100, in accordance with some embodiments.FIGS.4A through4Billustrate cross-sectional views of intermediate steps during a process for forming a device package101, in accordance with other some embodiments. A first package region10A and a second package region10B are illustrated, and a package structure100A,101A,103,105,107or109(seeFIGS.2,3B,5B and6) is formed in each of the first package region10A and the second package region10B. The packages100A,101A,103,105,107and109may also be referred to as integrated fan-out (InFO) packages. Referring toFIG.1A, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. The carrier substrate102may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate102may be a wafer, such that multiple packages may be formed on the carrier substrate102simultaneously. The release layer104may be formed of a polymer-based material, which may be removed along with the carrier substrate102from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer104is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer104may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer104may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate102, or may be the like. The top surface of the release layer104may be leveled and may have a high degree of planarity. Referring toFIG.1A, conductive pillars116are formed on the release layer104in fan-out areas FA. In some embodiments, before the conductive pillars116are formed, a back-side redistribution structure106may be formed on the release layer104as shown inFIG.7A. The back-side redistribution structure104is optional. In some embodiments, only a bottom dielectric layer108is formed on the release layer104as shown inFIG.9A. The back-side redistribution structure106is omitted in this embodiment as shown inFIG.1A. As an example to form the conductive pillars116, a seed layer is formed over the release layer104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. For example, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the conductive pillars116. Referring toFIG.1A, integrated circuit dies126are adhered to the release layer104in die areas DA by an adhesive128. The integrated circuit dies126may be logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. Also, in some embodiments, the integrated circuit dies126may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the integrated circuit dies126may be the same size (e.g., same heights and/or surface areas). Before being adhered to the release layer104, the integrated circuit dies126may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit dies126. For example, the integrated circuit dies126each include a semiconductor substrate130, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate130and may be interconnected by interconnect structures132formed by, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate130to form an integrated circuit. The integrated circuit dies126further comprise pads134, such as aluminum pads, to which external connections are made. The pads134are on what may be referred to as respective active sides of the integrated circuit dies126. Passivation films136are on the integrated circuit dies126and on portions of the pads134. Openings extend through the passivation films136to the pads134. Die connectors138, such as conductive pillars (for example, comprising a metal such as copper), extend through the openings in the passivation films136and are mechanically and electrically coupled to the respective pads134. The die connectors138may be formed by, for example, plating, or the like. The die connectors138electrically couple the respective integrated circuits of the integrated circuit dies126. A dielectric material140is on the active sides of the integrated circuit dies126, such as on the passivation films136and the die connectors138. The dielectric material140laterally encapsulates the die connectors138, and the dielectric material140is laterally coterminous with the respective integrated circuit dies126. The dielectric material140may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like. The adhesive128is on back-side surfaces of the integrated circuit dies126and adheres the integrated circuit dies126to the release layer104. In some embodiments, the first surfaces may be referred to as first surfaces or non-active surfaces. The back-side surfaces are opposite to front-side surfaces, the first surfaces are opposite to second surfaces, and the non-active surfaces are opposite to active side surfaces. The adhesive128may be applied to the back-side surfaces of the integrated circuit dies126before singulating to separate the integrated circuit dies126. The adhesive128may be any suitable adhesive, epoxy, die attach film (DAF), or the like. In some embodiments, the adhesive128may be similar to the material of a warpage control material172. The adhesive128may include a base material (such as epoxy). The adhesive128may further include a plurality of fillers in the base material. The average filler size of the filler may be, for example, less than 10 μm. In some embodiments, the content of the fillers in the adhesive128is greater than 50 wt %, such as 50 wt % to 80 wt % or more, based on the total weight of the adhesive128. The CTE of the adhesive128is greater than the CTE of the integrated circuit dies126. For example, the CTE of the adhesive128is less than 50 ppm/° C. in a temperature range. The Young's Modulus of adhesive128is less than the Young's Modulus of the integrated circuit dies126. Although one integrated circuit die126is illustrated as being adhered in each of the first package region10A and the second package region10B, it should be appreciated that more integrated circuit dies126may be adhered in each package region. For example, multiple integrated circuit dies126may be adhered in each region. Further, the integrated circuit dies126may vary in size. In some embodiments, the integrated circuit die126may be dies with a large footprint, such as system-on-chip (SoC) devices. Referring toFIG.1A, an encapsulant142is formed on the various components. After formation, the encapsulant142laterally encapsulates the conductive pillars116and integrated circuit dies126. In some embodiments, the encapsulant142includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, the encapsulant142includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, the encapsulant142includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. In some embodiments, the encapsulant142includes a composite material including a base material (such as polymer) and a plurality of fillers in the base material. The filler may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the fillers are spherical particles, or the like. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the fillers include solid fillers, but the disclosure is not limited thereto. In some embodiments, a small portion of the fillers may be hollow fillers. The filler size and filler content of the encapsulant142are controlled in a suitable range, and suitable base material and additives are selected to form the encapsulant142, such that the encapsulant142has a good property to provide the encapsulation of the integrated circuit dies126. For example, the average filler size of the filler may be less than 30 μm. In some embodiments, the content of the fillers in the encapsulant142is greater than 70 wt %, such as 70 wt % to 90 wt % or more, based on the total weight of the encapsulant142. In some embodiments, the CTE of the encapsulant142is greater than the CTE of the integrated circuit dies126and the adhesive128. The thermal expansion coefficient (CTE) of the encapsulant142is less than 20 ppm/° C. in a temperature range under glass transition temperature (Tg), and 40 ppm/° C. to 80 ppm/° C. in a temperature range higher than Tg, for example. The viscosity of the encapsulant142is greater than the viscosity of the adhesive128. The viscosity of the encapsulant142is less than 50 Pa·s at room temperature. In some embodiments, the Young's Modulus of the encapsulant142is greater than the Young's Modulus of the adhesive128, and less than the Young's Modulus of the integrated circuit dies126. The Young's Modulus of the encapsulant142ranges from 10 Gpa to 20 Gpa at room temperature. The encapsulant142may be applied by compression molding, transfer molding, spin-coating, lamination, deposition, or similar processes, and may be formed over the carrier substrate102such that the conductive pillars116and/or the integrated circuit dies126are buried or covered. The encapsulant142is then cured. The conductive pillars116penetrate the encapsulant142, and the conductive pillars116are sometimes referred to as through vias116or through integrated fan-out vias (TIVs)116. Referring toFIG.1B, a planarization process is then performed on the encapsulant142to remove a portion of the encapsulant142, such that the top surfaces of the through vias116and the die connectors138are exposed. In some embodiments in which the top surfaces of the through vias116and the front-side surfaces of the integrated circuit dies126are not coplanar (as shown inFIG.1A), portions of the through vias116or/and portions of the dielectric material140may also be removed by the planarization process. In some embodiments, top surfaces of the through vias116, the die connectors138, the dielectric material140, and the encapsulant142are substantially coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, for example, if the through vias116and die connectors138are already exposed. Referring toFIG.1C, a front-side redistribution structure144is formed over front-side surfaces of the through vias116, front-side surfaces of the encapsulant142, and front-side surfaces of the integrated circuit dies126. The front-side redistribution structure144includes dielectric layers146,150,154, and158; metallization patterns148,152, and156; and under bump metallurgies (UBMs)160. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure144is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure144. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated. As an example to form the front-side redistribution structure144, the dielectric layer146is deposited on the encapsulant142, the through vias116, and the die connectors138. In some embodiments, the dielectric layer146is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer146may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer146is then patterned. The patterning forms openings exposing portions of the through vias116and the die connectors138. The patterning may be by an acceptable process, such as by exposing the dielectric layer146to light when the dielectric layer146is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer146is a photo-sensitive material, the dielectric layer146may be developed after the exposure. The metallization pattern148is then formed. The metallization pattern148includes conductive lines CL on and extending along the top surface of the dielectric layer146. The metallization pattern148further includes conductive vias V extending through the dielectric layer146to be physically and electrically connected to the through vias116and the integrated circuit dies126. The sidewalls of the conductive vias V and the conductive lines CL may be straight or inclined. In some embodiments, the conductive via V has inclined sidewall and is tapered toward the integrated circuit dies126. To form the metallization pattern148, a seed layer is formed over the dielectric layer146and in the openings extending through the dielectric layer146. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern148. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern148. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The dielectric layers150,154,158, and the metallization patterns152,156are formed alternately. The dielectric layer150,154, and158may be formed in a manner similar to the dielectric layer146, and may be formed of the same material as the dielectric layer146. The metallization patterns152and156may include conductive lines CL on the underlying dielectric layer and conductive vias V extending through the underlying dielectric layer respectively. The metallization patterns152and156may be formed in a manner similar to the metallization pattern148, and may be formed of the same material as the metallization pattern148. The UBMs160are optionally formed on and extending through the dielectric layer158. The UBMs160may be formed in a manner similar to the metallization pattern148, and may be formed of the same material as the metallization pattern148. Referring toFIG.1C, conductive connectors162are formed on the UBMs160. The conductive connectors162may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors162comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. In another embodiment, the conductive connectors162may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors162are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow process may be performed in order to shape the material into the desired bump shapes. During the reflow process, under the thermal impact, the device package50may become warped owing to the CTE mismatch between the integrated circuit dies126. Referring toFIGS.1D and1E, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the encapsulant142and the adhesive128to form a device package50. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer104so that the release layer104decomposes under the heat of the light and the carrier substrate102may be removed. The device package50is then flipped over and placed on a tape (not shown). In some embodiments, after the device package50is flipped, a package structure50A of the device package50has a convex shape (so called crying-shape) as shown inFIGS.2and6. In alternative embodiments, after the device package50is flipped, a package structure50A′ of the device package50has a “M” shape as shown inFIGS.11and16. Referring toFIG.1F, conductive pastes163are formed to contact the through vias116. In some embodiments, the conductive pastes163comprise a conductive paste such as solder paste, silver paste, or the like, and are dispensed in a printing process. In other some embodiments, the conductive pastes163comprise flux and are formed in a flux dipping process. In some embodiments, the conductive pastes163are formed in a manner similar to the conductive connectors162, and may be formed of the same material as the conductive connectors162. The conductive pastes163may be dispensed in a printing process. In some embodiments, the conductive pastes163is formed by the following process: a stencil ST1is placed over the adhesive128in the die areas DA. The stencil ST1may be a two-dimensional stencil. The stencil ST1has a plurality of apertures AP1. A location of the apertures AP1of the stencil ST1corresponds to the through vias116in the fan-out areas FA. A shape of the apertures AP1of the stencil ST1corresponds to a shape of the through vias116. In some embodiments, a profile of the apertures AP1is conformal with a profile of the through vias116. In some embodiments, the apertures AP1of the stencil ST1is smaller than or equal to the size of the through vias116. In some embodiments, the stencil ST1is placed over the die areas DA such that the apertures AP1and the through vias116are coaxial. Referring toFIG.1F, the conductive pastes163are applied onto the exposed portions of the through vias116. For example, the conductive pastes163are applied onto the stencil ST1by a dispenser (not shown). Subsequently, a squeegee (not shown) may be adapted to scrape the conductive pastes163into the apertures AP1of the stencil ST1. In other words, the conductive pastes163is filled into the apertures AP1of the stencil ST1. The stencil ST1is then removed. Referring toFIGS.1G and3A, after the conductive pastes163are formed, the warpage control material172is formed on designed areas. In some embodiments in which the package structure50A has the convex shape as shown inFIG.2, the designed areas may be the entire die areas DA. The entire surface of the integrated circuit dies126is cover by the warpage control material172. In other some embodiments, the designed areas may be portions of the die areas DA such as center portions of the die areas DA (not shown). The warpage control material172has, for example, a block shape from a top view. A material of the warpage control material172is different from a material of the adhesive128. The warpage control material172has a coefficient of thermal expansion (CTE) in a suitable range to reduce the CTE mismatch between the CTE of the integrated circuit dies126and the encapsulant142. In some embodiments, the CTE of the warpage control material172is greater than the CTEs of the integrated circuit dies126, the adhesive128, the encapsulant142and a protection layer174(shown inFIGS.1H and3A). Therefore, the presence of the warpage control material172may help reduce the CTE mismatch and thus avoiding or reducing warpage caused by the CTE mismatch. For example, the CTE of the encapsulant142is less than 20 ppm/° C. in a temperature range under glass transition temperature (Tg), and 40 ppm/° C. to 80 ppm/° C. in a temperature range higher than Tg. The CTE of the warpage control material172is 10 ppm/° C. to 40 ppm/° C. in a temperature range under glass transition temperature (Tg), and 40 ppm/° C. to 200 ppm/° C. in a temperature range higher than Tg. However, the disclosure is not limited thereto. The warpage control material172has a Young's Modulus in a suitable range to reduce warpage of the device package50. In some embodiments, the Young's Modulus of the warpage control material172is greater than the Young's Modulus of the adhesive128, the protection layer174and the encapsulant142, and less than the Young's Modulus of the integrated circuit dies126. For example, the Young's Modulus of the warpage control material172ranges from 10 Gpa to 30 Gpa at room temperature. The warpage control material172may a glue, a liquid, a paste, a film or a combination thereof. In some embodiments, the viscosity of the warpage control material172is greater than the viscosities of the protection material174, the encapsulate142and the adhesive128at room temperature or a temperature range of 50° C. to 100° C. The viscosity of the warpage control material172ranges from 100 Pa·s to 200 Pa·s at room temperature. In some embodiments, the warpage control material172is a single layer structure, but the disclosure is not limited thereto. In alternative embodiments, the warpage control material172is a multi-layer structure. The warpage control material172may include one or more material selected from epoxy, resin, glass fiber, prepreg (which comprises epoxy, resin, and/or glass fiber), polyimide, combinations thereof, or multi-layers thereof. In some embodiments, the warpage control material172includes a composite material including a base material (such as epoxy) and a plurality of fillers in the base material. The filler may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the fillers are spherical particles, or the like. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the fillers include solid fillers, but the disclosure is not limited thereto. In some embodiments, a small portion of the fillers may be hollow fillers. The filler size and filler content of the warpage control material172are controlled in a suitable range, and suitable base material and additives are selected to form the warpage control material172, such that the warpage control material172has a good property to reduce warpage of the device package50. For example, the average filler size of the filler may be less than 30 μm. In some embodiments, the content of the fillers in the warpage control material172is greater than 50 wt %, such as 50 wt % to 90 wt % or more, based on the total weight of the warpage control material172. In some embodiments, the average filler size and filler content of the filler in the warpage control material172is less than the average filler size and filler content of the filler in the encapsulate142. The materials of the warpage control material172described above are merely for illustration, and the disclosure is not limited thereto. The warpage control material172may be formed in a printing process. In some embodiments, the warpage control material172is formed by the following process: a stencil ST2is placed over the conductive pastes163and the encapsulant142. The stencil ST2may be a tree-dimensional stencil. The stencil ST2has a plurality of ring recess R and a plurality of apertures AP2. In some embodiments, locations of the ring recesses R of the stencil ST2correspond to locations of the fan-out areas FA around the die areas DA. Locations of the apertures AP2of the stencil ST2correspond to locations of the die areas DA. The ring recess R has a depth greater than a height of the conductive pastes163, so that a space of the ring recess R may accommodate the conductive pastes163. The shape of the apertures AP2of the stencil ST2correspond to the shape of the adhesive128. For example, both of the apertures AP2and the adhesive128may have a square or elongated shape from a top view. In some embodiments, a profile of the apertures AP2is conformal with a profile of the adhesive128. In some embodiments, the apertures AP2of the stencil ST2is smaller than or equal to the size of the adhesive128. In some embodiments, the stencil ST2is placed over the fan-out areas FA such that the apertures AP2and the integrated circuit dies126are coaxial. As illustrated inFIG.1G, the apertures AP2expose at least a portion of each adhesive128. Referring toFIG.1G, the warpage control material172is applied onto the exposed portion of the adhesive128. For example, the warpage control material172is applied onto the stencil ST2by a dispenser (not shown). Subsequently, a squeegee (not shown) may be adapted to scrape the warpage control material172into the apertures AP2of the stencil ST2. In other words, the warpage control material172is filled into the apertures AP2of the stencil ST2. In some embodiments, the square or elongated shape nature of the apertures AP2shapes the warpage control material172filled therein to have square or elongated shape from a top view. Referring toFIG.1GandFIG.1H, the stencil ST2is then removed. The forming method of the warpage control material172described above is merely for illustration, and the disclosure is not limited thereto. In some other embodiments, the warpage control material172may be formed by dispensing or lamination processes. Still referring toFIG.1G, the warpage control material172may have a thickness T1greater than 50 μm, such as in a range of 50 μm to 150 μm, but the disclosure is not limited thereto. In some embodiments, the warpage control material172may have substantially uniform thickness across a top surface of the adhesive128. In alternative embodiments, the warpage control material172may have different thicknesses in different regions over the adhesive128. In some embodiments, a warpage degree of the package in a first region of the die areas DA is greater than a warpage degree of the package in a second region of the die areas DA. The warpage control material172formed in the first region may be thicker than the warpage control material172formed in the second regions. Referring toFIG.1H, a reflow process may be performed. The reflow process includes performing a thermal heating process at a reflow temperature, so that the conductive pastes163turns into a melted state or a semi-melted state to form conductive connectors164. The reflow temperature of the conductive pastes163is required to be higher than a melting point of the conductive pastes163. In some embodiments, the conductive pastes163have a melting temperature higher than about 200° C., and may be in the range of from about 215° C. to about 230° C. The power of a reflow oven for the reflow process may be adjusted to obtain a particular heating rate and peak temperature. In an embodiment, the peak temperature is in a range of from about 240° C. to about 250° C. InFIGS.1H and3A, the protection material174is formed on the fan-out areas FA. A material of the protection material174may be different from a material of the warpage control material172, a material of the encapsulant142and a material of the adhesive128. In some embodiments, the protection material174is a single layer structure, but the disclosure is not limited thereto. In alternative embodiments, the protection material174is a multi-layer structure. In some embodiments, the material of the protection material174may be the same as the materials of the dielectric layers146,150,154, or158. The protection material174includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, the protection material174includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. In alternative embodiments, the protection material174may be similar to the material of warpage control material172. The protection material174may include a base material (such as epoxy). The protection material174may further include a plurality of fillers in the base material or does not include any filler in the base material. In some embodiments, the average filler size and filler content of the filler in the protection material174is less than the average filler sizes and filler contents of the filler in the warpage control material172and the encapsulate142. The materials of the warpage control material172described above are merely for illustration, and the disclosure is not limited thereto. In some embodiments, the protection material174is a comparable CTE material having a coefficient of thermal expansion (CTE) in a suitable range. The protection material174may be used to reduce the CTE mismatch. In some embodiments, the CTE of the protection material174is greater than the CTEs of the integrated circuit dies126and the adhesive128, and less than the CTEs of the encapsulant142and the warpage control material172. Therefore, the presence of the protection material174may help reduce the CTE mismatch and thus avoiding or reducing warpage. For example, the CTE of the encapsulant142is less than 20 ppm/° C. in a temperature range under glass transition temperature (Tg), and 40 ppm/° C. to 80 ppm/° C. in a temperature range higher than Tg. The CTE of the warpage control material172is 10 ppm/° C. to 40 ppm/° C. in a temperature range under glass transition temperature (Tg), and 40 ppm/° C. to 200 ppm/° C. in a temperature range higher than Tg. The CTE of the protection material174is less than 60 ppm/° C. in a temperature range under glass transition temperature (Tg), and less than 200 ppm/° C. in a temperature range higher than Tg. In some embodiments, the Young's Modulus of the protection material174is greater than the Young's Modulus of the adhesive128, and less than the Young's Modulus of the integrated circuit dies126, the warpage control material172, and the encapsulant142. The Young's Modulus of the protection material174is less than 10 Gpa at room temperature. The protection material174may a glue, a liquid, a paste, a film or a combination thereof. The viscosity of the protection material174is greater than the viscosity of the adhesive128, and less than the viscosities of the warpage control material172and the encapsulate142at room temperature or a temperature range of 50° C. to 100° C. The viscosity of the protection material174is less than 10 Pa·s at room temperature. In some embodiments, the protection material174is formed in a printing process as the following: a stencil ST3is placed over the device package50. The stencil ST3may be a tree-dimensional stencil having an aperture AP3. A location of the aperture AP3of the stencil ST3corresponds to the locations of the die areas DA and the fan-out areas FA. A shape of the apertures AP3of the stencil ST3corresponds to a shape of the device package100. In some embodiments, a profile of the apertures AP3is conformal with a profile of the device package50. In some embodiments, the apertures AP3of the stencil ST3is smaller than or equal to the size of the device package100. Referring toFIG.1HandFIG.3A, the protection material174is applied onto the exposed portion of the conductive connectors164, the through vias116and the encapsulant142. For example, the protection material174is applied onto the stencil ST3by a dispenser (not shown). Subsequently, a squeegee (not shown) may be adapted to scrape the protection material174into the apertures AP3of the stencil ST3. Referring toFIG.1I, the stencil ST3is then removed. In some embodiments, the protection material174may cover the top surfaces and the sidewalls of the conductive connectors164, the top surfaces of the through vias116and the top surface of the encapsulant142in the fan-out areas FA, and expose top surfaces of the warpage control material172in the die areas DA as shown inFIGS.1I and3A. The protection material174may have a thickness T2in a range of 50 μm to 160 μm. In some embodiments, the thickness T2of the protection material174is the same as the thickness T1of the warpage control material172. the top surfaces of the protection material174and the top surfaces the warpage control material172are coplanar, and bottom surface of the protection material174and bottom surfaces the warpage control material172are coplanar. In other some embodiments, the bottom surface of the protection material174and the bottom surfaces the warpage control material172are coplanar, and the thickness T2of the protection material174is greater than the thickness T1of the warpage control material172as shown inFIGS.4A and5A. The protection material174covers the top surfaces and the sidewalls of the conductive connectors164, the top surfaces of the through vias116and the encapsulant142in the fan-out areas FA, and the top surfaces of the warpage control material172in the die areas DA. The protection material174may have the thickness T2in a range of 60 μm to 160 μm. The protection material174is cured. In some embodiments, the curing process of the protection material174may include performing a thermal heating process or thermal treatment at a curing temperature higher than about 200° C. The forming method of the protection material174described above is merely for illustration, and the disclosure is not limited thereto. In some other embodiments, the protection material174may be formed by dispensing or lamination processes. Referring toFIGS.1J and3B, andFIGS.4B and5B, openings190are formed through the protection material174to expose the top surfaces of the conductive connectors164. The openings190may be formed, for example, using laser drilling, laser trimming, etching, or the like. At this stage, device packages100and101are substantially completed. Referring toFIGS.1J and3B, in the device package100, the remaining protection material174is in contact with portion surfaces of the conductive connectors164, the top surface of the encapsulate142in the fan-out areas FA and sidewalls of the warpage control material172. In other words, the remaining protection material174separates the warpage control material172from the conductive connectors164, and separates two adjacent conductive connectors164. Referring toFIGS.4B and5B, in the device package101, the remaining protection material174is in contact with portion surfaces of the conductive connectors164, the top surface of the encapsulate142in the fan-out areas FA and sidewalls of the warpage control material172, and further in contact with the top surfaces of the warpage control material172in the die areas DA. Referring toFIGS.2and6, after the warpage control material172and the protection material174are formed, the warpages of the package structure100A of the device package100and the package structure101A of the device package101are reduced. FIGS.7A through7Dare schematic cross-sectional views illustrating a method of manufacturing a device package according to some embodiments of the disclosure.FIG.8is schematic cross-sectional view illustrating a device package according to some embodiments of the disclosure. Referring toFIG.7A, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. In embodiments where the integrated circuit die126have a large footprint, the space available for the conductive pillars116in the package regions may be limited. Use of a back-side redistribution structure106allows for an improved interconnect arrangement when the package regions have limited space available for the conductive pillars116. Therefore, before conductive pillars116are formed, the back-side redistribution structure106is formed on the release layer104in the die areas DA and the fan-out areas FA. The back-side redistribution structure106may include a bottom dielectric layer108, a metallization pattern110, and a top dielectric layer112. The bottom dielectric layer108is formed on the release layer104. The bottom surface of the bottom dielectric layer108may be in contact with the top surface of the release layer104. In some embodiments, the bottom dielectric layer108is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer108is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer108may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. The metallization pattern110may also be referred to as redistribution layers or redistribution lines. The metallization pattern110is formed on the bottom dielectric layer108. As an example to form the metallization pattern110, a seed layer is formed over the bottom dielectric layer108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern110. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern110. The top dielectric layer112is formed on the metallization pattern110and the bottom dielectric layer. In some embodiments, the top dielectric layer112is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the top dielectric layer112is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The top dielectric layer112may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The top dielectric layer112is then patterned to form openings114exposing portions of the metallization pattern110. The patterning may be by an acceptable process, such as by exposing the top dielectric layer112to light when the dielectric layer112is a photo-sensitive material or by etching using, for example, an anisotropic etch. It should be appreciated that the back-side redistribution structure106may include any number of dielectric layers and metallization patterns. Additional dielectric layers and metallization patterns may be formed by repeating the processes for forming the metallization pattern and dielectric layer. The metallization patterns may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization patterns by forming the seed layer and conductive material of the metallization patterns in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically couple the various conductive lines. The conductive pillars116are formed on the top dielectric layer112and in contact with the metallization pattern110exposed by the openings (not shown) in the top dielectric layer112. The integrated circuit dies126are adhered to the top dielectric layer112by an adhesive128. The adhesive128may be applied to back-side surfaces of the integrated circuit dies126or may be applied over the surface of the back-side redistribution structure106. Referring toFIG.7B, after an encapsulant142, a front-side redistribution structure144, UBMs160and conductive connectors162are formed, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the back-side redistribution structure106, e.g., the dielectric layer108to form a device package52. The device package52is then flipped over and placed on a tape (not shown). Referring toFIG.7C, openings (not shown) are formed through the bottom dielectric layer108to expose portions of the metallization pattern110. The openings may be formed, for example, using laser drilling, laser trimming, etching, or the like. Conductive pastes163are formed extending through the bottom dielectric layer108to contact the metallization pattern110. Referring toFIGS.7D and8, a warpage control material172is formed on the dielectric layer108in a designed region such as die areas DA. After a reflow process is performed, a protection material174is formed on fan-out areas FA (shown in7D) or further formed on the warpage control material172in the die areas DA (shown in8). The protection material174is cured, and openings190are formed through the protection material174to expose the top surfaces of the conductive connectors164. At this stage, device packages103and105are substantially completed. Referring toFIGS.7D and8, the warpage control material172is formed on and in contact with the surface of the bottom dielectric layer108in the designed region such as the die areas DA. The back-side redistribution structure106and the adhesive128separate the warpage control material172and the integrated circuit dies126. Referring toFIG.7D, in the device package103, bottom surface of the protection material174and bottom surface of the warpage control material172are coplanar. The remaining protection material174covers and is in contact with the top surfaces of the conductive connectors164, the top surface of the bottom dielectric layer108in the fan-out area FA and sidewalls of the warpage control material172in the die areas DA. Further, the remaining protection material174separates the warpage control material172from the conductive connectors164, and separates two adjacent conductive connectors164. Referring toFIG.8, in the device package105, bottom surface of the protection material174and bottom surface of the warpage control material172are coplanar. The protection material174covers and is in contact with the top surfaces of the conductive connectors164, the top surface of the bottom dielectric layer108in the fan-out area FA and sidewalls of the warpage control material172in the die areas DA, and further covers and is in contact with the top surface of the warpage control material172in the die areas DA. FIGS.9A through9Dare schematic cross-sectional views illustrating a method of manufacturing a device package according to some embodiments of the disclosure.FIG.10is schematic cross-sectional view illustrating a device package according to some embodiments of the disclosure. Referring toFIG.9A, in alternative embodiments, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. Before conductive pillars116are formed, a bottom dielectric layer108is formed on the release layer104. Referring toFIG.9B, after an encapsulant142, a front-side redistribution structure144, UBMs160and conductive connectors162are formed, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the dielectric layer108to form a device package53. The device package53is then flipped over and placed on a tape (not shown). Referring toFIG.9C, openings (not shown) are formed through the bottom dielectric layer108to expose portions of the conductive pillars116. The openings may be formed, for example, using laser drilling, laser trimming, etching, or the like. Conductive pastes163are formed extending through the bottom dielectric layer108to contact the conductive pillars116. Referring toFIGS.9D and10, a warpage control material172is formed on a designed region such as die areas DA. After a reflow process is performed, a protection material174is formed in fan-out areas FA (as shown inFIG.9D) or further formed on the warpage control material172in die areas DA (as shown inFIG.10). The protection material174is cured, and openings190are formed through the protection material174to expose the top surfaces of the conductive connectors164. At this stage, device packages107and109are substantially completed. Referring toFIGS.9D and10, the warpage control material172is formed on and in contact with the surface of the bottom dielectric layer108in the designed region such as the die areas DA. The bottom dielectric layer108and the adhesive128separate the warpage control material172and the integrated circuit dies126. Referring toFIG.9D, in the device package107, bottom surface of the protection material174and bottom surface of the warpage control material172are coplanar. The remaining protection material174covers and is in contact with the top surfaces of the conductive connectors164, the top surface of the bottom dielectric layer108in the fan-out area FA and sidewalls of the warpage control material172in the die areas DA. Further, the remaining protection material174separates the warpage control material172from the conductive connectors164, and separates two adjacent conductive connectors164. Referring toFIG.10, in the device package109, bottom surface of the protection material174and bottom surface of the warpage control material172are coplanar. The protection material174covers and is in contact with top surfaces of the conductive connectors164, the top surface of the bottom dielectric layer108in the fan-out area FA and sidewalls of the warpage control material172in the die areas DA, and further covers and is in contact with the top surface of the warpage control material172in the die areas DA. FIG.11is a schematic cross-sectional view illustrating package structures50A′ and100A′ according to alternative embodiments of the disclosure.FIG.16is a schematic cross-sectional view illustrating package structures50A′ and101A′ according to some embodiments of the disclosure. Referring toFIGS.11and16, a package structure50A′ is a portion of the device package50(shown inFIG.1E). A structure of the package structure50A′ is similar to a structure of the package structure50A (shown inFIGS.2and6), and the difference is that the package structure50A′ has the “M” shape. In some embodiments, the topmost surface of the package structure50A′ is located in an interface between a die area DA and a fan-out area FA, or in the die area DA adjacent to the interface, or in the fan-out area FA adjacent to the interface. FIGS.12A through12C, and14A through14Bare schematic cross-sectional views illustrating methods of manufacturing device packages100′ and101′ according to alternative embodiments of the disclosure.FIGS.13A through13B and15A through15Bare schematic top views illustrating methods of manufacturing device packages100′ and101′ according to other some embodiments of the disclosure.FIGS.17,18,19and20are schematic cross-sectional views illustrating device packages103′,105′,107′ and109′ according to some embodiments of the disclosure. The methods of manufacturing the device packages100′,101′,103′,105′,107′, and109′ are similar to the methods manufacturing the device packages100,101,103,105,107, and109, and differ in that warpage control materials172and protection materials174are disposed at different positions. In some embodiments, the warpage control material172is disposed in the interfaces between the die areas DA and the fan-out areas FA as shown inFIGS.12A,14A,17,18,19and20. The warpage control material172is disposed to partially cover the adhesive128, which is disposed on the integrated circuit dies126, in the die areas DA, and the encapsulate142in the fan-out areas FA, and exposes a portion of the adhesive128in the die areas DA and a portion of the encapsulate142in the fan-out areas FA. In some embodiments, the warpage control material172may be spaced apart from conductive pastes163. The warpage control material172may has, for example, a ring shape from a top view as shown inFIGS.13A,13B,15A and15B. The protection material174is at least disposed on the portion of the die areas DA and the portion of the fan-out areas FA, where is not covered by the warpage control material172, as shown inFIGS.12B,12C,14A,14B,17,18,19and20. The protection material174is in contact with portion surfaces of the conductive connectors164, a top surface of the encapsulate142in the fan-out areas FA, and sidewalls of the warpage control material172. The protection material174is further in contact with an adhesive128in the die area DA (as shown inFIGS.12B and14B), or a bottom dielectric layer108(as shown inFIGS.17to20). The warpage control material172and the conductive connectors164are separated by the protection material174. Bottom surface of the protection material174and bottom surface of the warpage control material172may be coplanar as shown inFIGS.11,12C,14B,16,17,18,19and20. In some embodiments, top surfaces of the protection material174and top surfaces the warpage control material172may be coplanar as shown inFIGS.11,12C,17, and19. In alternative embodiments, the top surfaces the warpage control material172is cover by the protection material174as shown inFIGS.14B,16,18, and20. Openings190are formed through the protection material174to expose the top surfaces of the conductive connectors164as shown inFIGS.12C,13B,14B,15B,18,19, and20. Referring toFIGS.11and16, after the warpage control material172and the protection material174are formed, the warpages of the package structure100A′ of the device package100′ and the package structure101A′ of the device package101′ are reduced. The warpages of the package structures of the device packages103′,105′,107′ and109′ may also be reduced (not shown). In the embodiments of the disclosure, the warpage control material is formed on the design area such as the die areas or the interfaces between the die areas and the fan-out areas to reduce the CTE mismatch and thus avoiding or reducing warpage. The protection material at least covers and protects the surfaces of the fan-out areas and thus avoiding or reducing damage. In accordance with some embodiments of the disclosure, a package structure, includes a die, a plurality of through vias, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulates the die and the plurality of through vias. The plurality of first connectors are electrically connected to a first surface of the plurality of through vias. The warpage control material is disposed over the die. The protection material is disposed over the encapsulant, around the plurality of first connectors and the warpage control material. A Young's modulus of the warpage control material is greater than a Young's modulus of the encapsulant, and the Young's modulus of the encapsulant is greater than a Young's modulus of the protection material. In accordance with alternative embodiments of the disclosure, a package structure, includes a die, a plurality of through vias, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulates the die and the plurality of through vias. The plurality of first connectors are electrically connected to the plurality of through vias. The warpage control material is disposed over a first surface of the die. The protection material is disposed over a first surface of the encapsulant and a top surface of the warpage control material, around the plurality of first connectors and the warpage control material. A Young's modulus of the warpage control material is greater than a Young's modulus of the encapsulant, and the Young's modulus of the encapsulant is greater than a Young's modulus of the protection material. In accordance with some embodiments of the disclosure, a method of fabricating a package structure includes the following processes. A plurality of through vias are formed around a die. An encapsulant is formed a to laterally encapsulate the die and the plurality of through vias. A plurality of connectors are formed to electrically connect to the plurality of through vias. A warpage control material is formed over a first surface of the die. A protection material is formed over a first surface of the encapsulant, around the plurality of first connectors and the warpage control material. A Young's modulus of the warpage control material is greater than a Young's modulus of the encapsulant, and the Young's modulus of the encapsulant is greater than a Young's modulus of the protection material. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 61,197 |
11862578 | DETAILED DESCRIPTION OF THE INVENTION The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by reference to the appended claims. The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention. FIG.1Ais a cross-sectional view of a semiconductor package structure100a, in accordance with some embodiments of the disclosure.FIG.1Cis a plan view of an arrangement of holes in a substrate101of the semiconductor package structure100ashown inFIG.1A, andFIG.1Ais a cross-sectional view of the semiconductor package structure100aalong line I-I′ ofFIG.1C. Additional features can be added to the semiconductor package structure100a. Some of the features described below can be replaced or eliminated for different embodiments. To simplify the diagram, only a portion of the semiconductor package structure100ais depicted inFIGS.1A and1C. In some embodiments, the semiconductor package structure100amay include a wafer-level semiconductor package, for example, a flip-chip semiconductor package. Referring toFIG.1A, the semiconductor package structure100amay be mounted on a base (not shown). In some embodiments, the semiconductor package structure100amay be a system-on-chip (SOC) package structure. Moreover, the base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). In some embodiments, the base may include a package substrate. The semiconductor package structure100ais mounted on the base by a bonding process. For example, the semiconductor package structure100aincludes bump structures111. In some embodiments, the bump structures111may be conductive ball structures (such as ball grid array (BGA)), conductive pillar structures, or conductive paste structures that are mounted on and electrically coupled to the base in the bonding process. In the embodiment, the semiconductor package structure100aincludes a substrate101. The substrate101has a wiring structure therein. In some embodiments, the wiring structure in the substrate101is a fan-out structure, and may include one or more conductive pads103, conductive vias105, conductive layers107and conductive pillars109. In such cases, the wiring structure in the substrate101may be disposed in one or more inter-metal dielectric (IMD) layers. In some embodiments, the IMD layers may be formed of organic materials, which include a polymer base material, non-organic materials, which include silicon nitride (SiNx), silicon oxide (SiOx), grapheme, or the like. For example, the IMD layers are made of a polymer base material. It should be noted that the number and configuration of the IMD layers, the conductive pads103, the conductive vias105, the conductive layers107and the conductive pillars109shown in Figures and only some examples and are not limitations to the present invention. Moreover, the semiconductor package structure100aalso includes a first semiconductor die115aand a second semiconductor die115bbonded onto the substrate101through a plurality of conductive structures119. The substrate101has a first surface101aand a second surface101bopposite thereto, the first surface101ais facing the first semiconductor die115aand the second semiconductor die115b, and the second surface101bis facing the above-mentioned base. The conductive structures119are disposed over the first surface101aand below the first semiconductor die115aand the second semiconductor die115b, and the bump structures111are disposed over the second surface101bof the substrate101. In some embodiments, the first semiconductor die115aand the second semiconductor die115bare electrically coupled to the bump structures111through the conductive structures119and the wiring structure in the substrate101. In addition, the conductive structures119may be controlled collapse chip connection (C4) structures. It should be noted that the number of semiconductor dies integrated in the semiconductor package structure100ais not limited to that disclosed in the embodiment. In some embodiments, the first semiconductor die115aand the second semiconductor die115bare active devices. For example, the first semiconductor die115aand the second semiconductor die115bmay be logic dies including a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller or any combination thereof. In some other embodiments, one or more passive devices are also bonded onto the substrate101. The first semiconductor die115aand the second semiconductor dies115bare arranged side-by-side. In some embodiments, the first semiconductor die115aand the second semiconductor dies115bare separated by a molding material117. The molding material117surrounds the first semiconductor die115aand the second semiconductor die115b, and adjoins the sidewalls of the first semiconductor die115aand the second semiconductor die115b. In some embodiments, the molding material117includes a nonconductive material such as an epoxy, a resin, a moldable polymer, or another suitable molding material. In some embodiments, the molding material117is applied as a substantial liquid, and then is cured through a chemical reaction. In some other embodiments, the molding material117is an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid, and then is cured through a UV or thermal curing process. The molding material117may be cured with a mold (not shown). In some embodiments, the surfaces of the first semiconductor die115aand the second semiconductor dies115bfacing away from the first surface101aof the substrate101are exposed by the molding material117, such that a heat dissipating device (not shown) can directly attached to the surfaces of the first semiconductor die115aand the second semiconductor dies115b. As a result, the heat-dissipation efficiency of the semiconductor package structure100acan be improved, particularly for a large semiconductor package structure, such as 50 mm×50 mm, which is preferred for high-power applications. The semiconductor package structure100aalso includes a polymer material121disposed under the molding material117, the first semiconductor die115aand the second semiconductor die115b, and between the conductive structures119. The semiconductor package structure100afurther includes an underfill layer123interposed between the first surface101aof the substrate101and the polymer material121. In some embodiments, the first semiconductor die115a, the second semiconductor dies115band the molding material117are surrounded by the underfill layer123. The polymer material121and the underfill layer123are disposed to compensate for differing coefficients of thermal expansion (CTEs) between the substrate101, the conductive structures119, the first semiconductor die115aand the second semiconductor dies115b. In addition, the semiconductor package structure100aincludes a frame113attached to the first surface101aof the substrate101through an adhesive layer112. The first semiconductor die115aand the second semiconductor die115bare surrounded by the frame113and the adhesive layer112. In some embodiments, the frame113and the adhesive layer112are separated from the underfill layer121by a gap. The substrate101has a first edge101E1and a second edge101E2opposite thereto. In some embodiments, the first edge101E1and the second edge101E2are coplanar with sidewalls of the frame113and the adhesive layer112. Still referring toFIG.1A, the substrate101of the semiconductor package structure100aincludes a first hole110aand a second hole110bformed on the second surface101b. In some embodiments, at least one of the first hole110aand the second hole110bpenetrates through the substrate101from the first surface101ato the second surface101b. Although the first hole110aand the second hole110bshown inFIG.1Apenetrate through the substrate101, in some other embodiments, both the first hole110aand the second hole110bdo not penetrate through the substrate101from the first surface101ato the second surface101b. In some embodiments, the first hole110ais covered by the first semiconductor die115a, and the second hole110bis covered by the second semiconductor die115b. In other words, the first hole110ais located within the projection of the first semiconductor die115aon the substrate101, and the second hole110bis located within the projection of the second semiconductor die115bon the substrate101. Specifically, the first semiconductor die115aand the second semiconductor die115bhave a center line C-C′ between them. The first hole110ais disposed closer to the center line C-C′ than the first edge101E1of the substrate101, and the second hole110bis disposed closer to the center line C-C′ than the second edge101E2of the substrate101. Although there are only two holes in the substrate101shown inFIG.1A, it should be noted that there is no limitation on the number of the holes formed in the substrate101. In some embodiments, the first hole110aand the second hole110bare formed by a laser drilling process or another suitable process. It should be noted that the first hole110aand the second hole110bmay be formed by the same forming process for the conductive pillars109in the wiring structure of the substrate101. Moreover, the first semiconductor die115aand the second semiconductor die115bare bonded to the substrate101after forming the holes in the substrate101. Therefore, the damage of the first semiconductor die115aand the second semiconductor die115bcan be prevented. Referring toFIG.1C, which is a plan view of an arrangement of holes in a substrate101of the semiconductor package structure100ashown inFIG.1A, andFIG.1Ais a cross-sectional view of the semiconductor package structure100aalong line I-I′ ofFIG.1C. It should be noted thatFIG.1Cis the plan view from the bottom of the semiconductor package structure100a. In other words,FIG.1Cis the plan view from the second surface101bof the substrate101, which the bump structures111are disposed on. In particular, the bump structures111are omitted for brevity. As shown inFIG.1C, the substrate101includes more than two holes. In particular, the substrate101further includes a third hole110cand the fourth hole110dformed on the second surface101b. The third hole110cis covered by the first semiconductor die115a, and the fourth hole110dis covered by the second semiconductor die115b. It should be noted that the substrate101has a center101C, and the first hole101a, the second hole101b, the third hole110c, and the fourth hole110dare disposed closer to the center101C than the first edge101E1and the second edge101E2of the substrate101. The holes formed in the substrate101, for example, the first hole110a, the second hole110b, the third hole110cand the fourth hole110d, are designed to release the stress in the substrate101, especially the stress concentrated in the region below the interface between two semiconductor dies (i.e. the first semiconductor die115aand the second semiconductor die115b). Since the semiconductor package structure100amay be highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate101and the semiconductor dies, the holes formed in the substrate101can solve the warping or cracking problems caused by mismatched CTEs. As a result, the electrical connection within the semiconductor package structure100amay not be damaged, and the reliability of the semiconductor package structure100amay be increased. FIG.1Bis a cross-sectional view of a semiconductor package structure100b, in accordance with some other embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference toFIG.1Aare omitted for brevity. As shown inFIG.1B, the semiconductor package structure100bincludes a stress buffer layer125filled in the first hole110aand the second hole110b. The stress buffer layer125is made of a polymer material, such as a silicone resin or rubber. In some embodiments, the stress buffer layer125is made of an organic resin, such as Ajinomoto Build-up Film (ABF). Moreover, the stress buffer layer125may be formed by a spin coating process. In some other embodiments, a material of the stress buffer layer125may be dispensed in the first hole110aand the second hole110b, and an excess portion of the material of the stress buffer layer125may be removed. In some embodiments, the stress buffer layer125may be formed before bonding the first semiconductor die115aand the second semiconductor die115bto the substrate101. In some embodiments, the stress buffer layer125may filled up the first hole110aand the second hole110b, and the surfaces of the stress buffer layer125are level with the second surface101bof the substrate101. In some other embodiments, the surfaces of the stress buffer layer125may not be level with the second surface101bof the substrate101according to the actual manufacturing processes. Filling the first hole110aand the second hole110bwith the stress buffer layer125may offer advantages like preventing the impurities and dust from dropping into the first hole110aand the second hole110bduring the process of handling the substrate101. In addition, the warping or cracking caused by mismatched coefficients of thermal expansion in the semiconductor package structure100bcan be solved by the holes (including the first hole110aand the second hole110b) and the stress buffer layer125formed in the substrate101. Accordingly, the electrical connection within the semiconductor package structure100bmay not be damaged, and the lifespan of the semiconductor package structure100bmay be increased. FIG.2Ais a plan view showing shapes of holes in a substrate201A of a semiconductor package structure200a, andFIG.2Bis a plan view showing shapes of holes in a substrate201B of a semiconductor package structure200b, in accordance with some embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference toFIG.1Care omitted for brevity. Referring toFIG.2A, the semiconductor package structure200ahas holes A, B, C, D, E, F, G, H, I, J, K and L in the substrate201A, and the number of holes in the substrate201A is much more than that in the substrate101of the semiconductor package structure100a. As shown inFIG.2A, the holes A, B, C, D, E and F are covered by the first semiconductor die115a, and the holes G, H, I, J, K and L are covered by the second semiconductor die115b. In other words, the holes A-F are located within the projection of the first semiconductor die115aon the substrate201A, and the holes G-L are located within the projection of the second semiconductor die115bon the substrate201A. Specifically, the holes A, B and C are arranged in a first array, the holes D, E and F are arranged in a second array, the holes G, H and I are arranged in a third array, and the holes J, K and L are arranged in a fourth array. The first array, the second array, the third array and the fourth array are parallel to the center line C-C′ of the first semiconductor die115aand the second semiconductor die115b. Referring toFIG.2B, the substrate201B in the semiconductor package structure200bhas holes a, b, c, d, e, f, g, h, i, j, k and l, which are arranged in the same way as the holes A-L of the substrate201A in the semiconductor package structure200a. The difference between the substrate201A and the substrate201B is that the holes a-l have circular shapes in the plan view. Compared with the holes A-L in the substrate201A, which have rectangular shapes in the plan view, the problems of stress concentrated at the corners of the holes A-L can be prevented in the substrate201B due to the round shapes of the holes a-l. Therefore, the probability that the cracking problem occurs in the substrate201B of the semiconductor package structure200bcan be more decreased. In some embodiments, stress buffer layers may be optionally formed in the holes A-L of the semiconductor package structure200aand in the holes a-l of the semiconductor package structure200b. It should be noted that the holes A-L are symmetrically located about the center line C-C′ in the plan view ofFIG.2A, and the holes a-l are symmetrically located about the center line C-C′ in the plan view ofFIG.2B. In some other embodiments, the holes A-L are symmetrically located about the center201C of the substrate201A in the plan view ofFIG.2A, and the holes a-l are symmetrically located about the center201C′ of the substrate201B in the plan view ofFIG.2B. FIG.3Ais a plan view showing arrangements of holes in a substrate301A of a semiconductor package structure300a, andFIG.3Bis a plan view showing arrangements of holes in a substrate301B of a semiconductor package structure300b, in accordance with some embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference toFIG.2Aare omitted for brevity. Referring toFIG.3A, the semiconductor package structure300ahas holes A, B, C, D, E, and F in the substrate301A. The holes A, B and C are covered by the first semiconductor die115a, and the holes D, E and F are covered by the second semiconductor die115b. In other words, the holes A-C are located within the projection of the first semiconductor die115aon the substrate301A, and the holes D-F are located within the projection of the second semiconductor die115bon the substrate301A. It should be noted that the holes A-F are arranged radially around the center301C of the substrate301A. In some other embodiments, the holes A-F are arranged radially around a center, and the center is located between the first semiconductor die115aand the second semiconductor die115b. Compared with the semiconductor substrate200aofFIG.2A, the stress in the substrate301A of the semiconductor package structure300a, which has holes A-F arranged radially, can be released more efficiently. In other words, in order to obtain the same stress releasing effect as in the semiconductor package structure200a, the number of the holes in the substrate301A of the semiconductor package structure300acan be less than the number of the holes in the substrate201A of the semiconductor package structure200a. However, the substrate201A of the semiconductor package structure200a, which has holes A-L arranged parallel to the center line C-C′, is more easily to be manufactured than the substrate301A of the semiconductor package structure300a, which has holes A-F arranged radially. Referring toFIG.3B, the substrate301B in the semiconductor package structure300bhas holes a, b, c, d, e, f, g, h, i, j, k, l, m and n arranged staggered in the substrate301B. Specifically, the holes a-g are covered by the first semiconductor die115aand staggered disposed along the direction of the center line C-C′, and the holes h-n are covered by the second semiconductor die115band staggered disposed along the direction of the center line C-C′. Compared with the semiconductor package structure200ainFIG.2Aand the semiconductor package structure300ainFIG.3A, the substrate301B of the semiconductor package structure300bcan combine the above-mentioned benefits of the hole arrangements of the substrate201A in the semiconductor package structure200aand the substrate301A of the semiconductor package structure300a. Specifically, the holes a-n in the substrate301B can be manufactured easily, and the stress in the substrate301B can be released efficiently. In some embodiments, stress buffer layers may optionally be formed in the holes A-F of the semiconductor package structure300aand the holes a-n of the semiconductor package structure300b. It should be noted that the holes A-F are symmetrically located about the center line C-C′ in the plan view ofFIG.3A, and the holes a-n are symmetrically located about the center line C-C′ in the plan view ofFIG.3B. In some other embodiments, the holes A-F are symmetrically located about the center301C of the substrate301A in the plan view ofFIG.3A, and the holes a-n are symmetrically located about the center301C′ of the substrate301B in the plan view ofFIG.3B. FIG.4Ais a plan view showing locations of holes in a substrate401A of a semiconductor package structure400a, andFIG.4Bis a plan view showing locations of holes in a substrate401B of a semiconductor package structure400b, in accordance with some embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference toFIG.2Aare omitted for brevity. Referring toFIG.4A, the substrate401A in the semiconductor package structure400ahas holes A, B, C, D, E, F, G, H, I, J, K and L arranged in the same way as the holes A-L of the substrate201A in the semiconductor package structure200ashown inFIG.2A. The holes A-L are arranged parallel to the center line C-C′ in the substrate401A. The difference betweenFIGS.2A and4Ais that the holes A-L in the substrate401A are located closer to the center401C of the substrate401A than the holes A-L in the substrate201A. Since the maximum stress is likely to be concentrated at the center401C of the substrate401A, the stress in the substrate401A of the semiconductor package structure400a, which has holes A-L located closer to the center401C of the substrate401A, can be released more efficiently than the semiconductor package structure200a. Referring toFIG.4B, the substrate401B in the semiconductor package structure400bhas holes a, b, c, d, e, f, g, h, i and j located along the peripheral edge of the substrate401B. In other words, the holes a-j are located far from the center401C′ of the substrate401B to reserve space in the middle of the substrate401B for routing. Compared with the semiconductor substrate400aofFIG.4A, the semiconductor substrate400bofFIG.4Bcan provide a better routing capability for the substrate401B. In some embodiments, stress buffer layers may optionally be formed in the holes A-L of the semiconductor package structure400aand the holes a-j of the semiconductor package structure400b. It should be noted that the holes A-L are symmetrically located about the center line C-C′ in the plan view ofFIG.4A, and the holes a-j are symmetrically located about the center line C-C′ in the plan view ofFIG.4B. In some other embodiments, the holes A-L are symmetrically located about the center401C of the substrate401A in the plan view ofFIG.4A, and the holes a-j are symmetrically located about the center401C′ of the substrate401B in the plan view ofFIG.4B. FIG.5is a cross-sectional view of a semiconductor package structure500a, in accordance with some other embodiments of the disclosure. It should be noted that the semiconductor package structure500amay include the same or similar portions as that of the semiconductor package structures100aand100b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure500aincludes a substrate101, a first semiconductor die115a, a second semiconductor die115band a frame113. As shown inFIG.5, the semiconductor package structure500afurther includes a heat sink130and a plurality of passive components140, wherein the heat sink130is disposed on the first semiconductor die115aand the second semiconductor die115b, and the passive components140is disposed adjacent to one of the first semiconductor die115aand the second semiconductor die115b. In the present embodiment, the heat sink130is configured to dissipate the heat generated by the first semiconductor die115aand the second semiconductor die115bduring operation. In some embodiments, the heat sink130is in direct contact with the first semiconductor die115aand the second semiconductor die115b, such that the heat may be dissipated rapidly. In some other embodiments, a bonding layer (not shown) is disposed between the heat sink130and the first semiconductor die115a, the second semiconductor die115bin order to arrange the heat sink130more stably. In addition, the bonding layer may also help for eliminating the interstice (if present) between the heat sink and the semiconductor dies115a,115b, such that the thermal dissipation may also be improved. As shown inFIG.5, the upper surface of the frame113is lower than the upper surface of the semiconductor dies115a,115b. In other words, there is a gap between the frame113and the heat sink130. It should be appreciated that the term “upper surface” of an element disposed over the substrate101is defined as a surface that is away from the substrate101. In other words, the upper surface of the element is opposite to an surface that faces or contacts the first surface101aof the substrate101. Generally, the upper surface is substantially perpendicular to the center line C-C′. In addition, the terms “higher” and “lower” are referred to different positions along the center line C-C′. If an element or a portion is higher than another element or portion, the element or a portion is located farther away from the first surface101athan the another element or portion, and vice versa. As viewed in a direction that is perpendicular to the upper surface of the semiconductor dies115a,115b, the heat sink130overlaps with the frame113and the semiconductor dies115a,115b. The above arrangement of the frame113may ensure the semiconductor dies115a,115bto contact the heat sink130. A plurality of passive components140are disposed on the substrate101, and located between the frame113and the semiconductor dies115a,115b. It is noted that the passive components140are designed according to functional purposes of the semiconductor package structure500a, and those skilled in the art may adjust the arrangement of the passive components140as required. For the sake of simplicity, the detailed description will not be provided herein. FIG.6is a cross-sectional view of a semiconductor package structure500b, in accordance with some other embodiments of the disclosure, andFIG.7is a top view of the semiconductor package structure500bshown inFIG.6.FIG.6is illustrated along line A-A′ shown inFIG.7. It should be noted that the semiconductor package structure500bmay include the same or similar portions as that of the semiconductor package structure500a, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure500bincludes a substrate101, a frame113, semiconductor dies115a,115band a heat sink130. As shown inFIG.6, the semiconductor package structure500bfurther includes a buffer layer150which is disposed on the substrate101and located between the frame113and the semiconductor dies115a,115b. In the present embodiment, upper surfaces of the frame113, the buffer layer150and the semiconductor dies115a,115bare located on the same imaginary plane. That is, the upper surface of the frame113is substantially level with the upper surfaces of the frame113and the semiconductor dies115a,115b. In the present embodiment, the passive components140may be surrounded by the buffer layer150. For example, the buffer layer150includes polymer materials, but it is not limited thereto. Thanks to the arrangement of the buffer layer150, the passive components140may be protected and the thermal dissipation may be further improved since the thermal conductivity of the buffer layer150is greater than that of air. In addition, the warpage issue of the semiconductor package structure500amay also be reduced since the substrate101may be supported by the frame113and/or the buffer layer150. FIG.8is a cross-sectional view of a semiconductor package structure500c, in accordance with some other embodiments of the disclosure. It should be noted that the semiconductor package structure500cmay include the same or similar portions as that of the semiconductor package structure500b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure500cincludes a substrate101, a frame113, semiconductor dies115a,115b, a heat sink130, and a buffer layer150. In the present embodiment, the buffer layer150is separated from the frame113and the semiconductor dies115a,115b, reducing the difficulty of forming the buffer layer150. In addition, there is a gap between the heat sink130and the frame113, the buffer layer150. As set forth above, the frame113and the buffer layer150may not interfere the bonging between the semiconductor dies115a,115band the heat sink130. FIG.9is a cross-sectional view of a semiconductor package structure500d, in accordance with some other embodiments of the disclosure. It should be noted that the semiconductor package structure500cmay include the same or similar portions as that of the semiconductor package structure500b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure500cincludes a substrate101, semiconductor dies115a,115b, a heat sink130, and a buffer layer150. In the present embodiment, the frame113is omitted and replaced by the buffer layer150, such that the manufacturing process of the semiconductor package structure500dmay be simplified, reducing the required time and cost of the manufacturing process. It should be noted that the buffer layer150may provide sufficient support so as to reduce the warpage issue of the semiconductor package structure500d. In the present embodiment, the heat sink130is disposed directly above the semiconductor dies115a,115band the buffer layer150. FIG.10is a cross-sectional view of a semiconductor package structure500e, in accordance with some other embodiments of the disclosure. It should be noted that the semiconductor package structure500cmay include the same or similar portions as that of the semiconductor package structure500b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure500cincludes a substrate101, a frame113, semiconductor dies115a,115b, a heat sink130, and a buffer layer150. In the present embodiment, the buffer layer150covers the upper surface of the frame113. As a result, the frame113may not directly contact the heat sink130(namely, the frame113may be separated from the heat sink130), and the buffer layer150contacts the heat sink130instead. Since the flatness of the surface formed by the buffer layer150may be higher than the flatness of the surface formed by the frame113, a flatter interface between the buffer layer150and the heat sink150. Accordingly, the contact between the semiconductor dies115a,115band the heat sink150may be created, enhancing the thermal dissipation of the semiconductor dies115a,115b. According to the foregoing embodiments, the holes formed in the substrate are designed to release the stress in the substrate, especially the stress concentrated in the region below the interface between two semiconductor dies. Since the semiconductor package structure may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate and the semiconductor dies, the holes formed in the substrate can solve the warping or cracking problems caused by mismatched CTEs. As a result, the electrical connection within the semiconductor package structure may not be damaged, and the reliability and the lifespan of the semiconductor package structure may be increased. In addition, in some embodiment of the present disclosure, the buffer layer formed on the substrate may help to reduce warpage of the semiconductor package structure and/or enhance the thermal dissipation of the semiconductor dies. In the foregoing embodiments, the semiconductor dies115aand115bmay be formed in the same package, for example, the semiconductor dies115aand115bare disposed on a fan-out package interposer, the fan-out package interposer is a rewiring laminate structure. In addition, the semiconductor dies115aand115bcould be disposed on a Chip-on-Wafer-on-Substrate (CoWoS) structure with a package interposer, the package interposer has multiple through silicon vias (TSVs) as interconnection between the semiconductor dies and the substrate101. In other embodiments, the semiconductor dies115aand115bmay be formed in different packages, for example, the semiconductor die115acould be a flip-chip (FC) package, while the semiconductor die115bcould be a fan-out structure. The package construction may be varied to achieve different technical purposes. Many variations and/or modifications can be made to embodiments of the disclosure. The semiconductor package structures in accordance with some embodiments of the disclosure can be used to form a three-dimensional (3D) package, a 2.5D package, a fan-out package, or another suitable package. In addition, the arrangements, the shapes, and the locations of the holes in the substrate can be adjusted according to the types of the application. While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. | 34,129 |
11862579 | DETAILED DESCRIPTION In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with semiconductor dies, lead frames, and semiconductor packages have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the various embodiments provided herein. Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.” Further, the terms “first,” “second,” and similar indicators of sequence are to be construed as being interchangeable unless the context clearly dictates otherwise. Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments of the present disclosure. As used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its broadest sense, that is, as meaning “and/or” unless the context clearly dictates otherwise. The present disclosure is generally directed to semiconductor devices, packages, and methods of forming semiconductor devices and packages in which one or more surfaces of a substrate are processed to improve adhesion between the substrate and an encapsulant material, such as a mold compound or an epoxy mold compound. An immersion porous copper adhesion promoter (IPC-AP) process is performed on the substrate, which may be a copper substrate or lead frame, and the process utilizes microbeads in an electroless copper plating process. The microbeads become embedded during deposition of a layer of copper on the copper substrate. The microbeads may be soluble, and can be removed by any solvent, thereby leaving behind a roughened surface in the copper layer. The roughened surface promotes better adhesion with the mold compound, which reduces or prevents delamination between the mold compound and the substrate. FIG.1is a cross-sectional view illustrating a semiconductor package10in accordance with one or more embodiments of the present disclosure. In some embodiments, the package10may be a QFN semiconductor package, as shown, however embodiments of the present disclosure are not limited thereto. In some embodiments, the package10may be a QFN multi-row (QFN-mr) package having a plurality of rows of exposed leads or lead pads. The package10includes a die pad12and a plurality of leads14that are spaced apart from the die pad12in a lateral direction (e.g., in the horizontal direction as shown inFIG.1). The package10may include an array of leads14around the die pad12. A semiconductor die16is positioned on the die pad12. The semiconductor die16may be any semiconductor die including one or more electrical components, such as integrated circuits. The semiconductor die16is made from a semiconductor material, such as silicon, and includes an active surface17in which integrated circuits are formed. The integrated circuits may be analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the semiconductor die16and electrically interconnected according to the electrical design and function of the semiconductor die16. In some embodiments, the semiconductor die16is secured to an inner surface of the die pad12by an adhesive material18. The adhesive material18may be any material suitable to mechanically and/or electrically couple the semiconductor die16to the die pad12, such as conductive glue, paste, tape, or the like. In one or more embodiments, the adhesive material18may be a die attach film suitable to attach the semiconductor die16to the die pad12. The semiconductor die16is secured to the die pad12with the active surface17of the semiconductor die16facing away from the inner surface of the die pad12, as shown inFIG.1. Conductive wires20electrically couple the semiconductor die16to the leads14. For example, the conductive wires20may electrically couple respective bond pads on the active surface17of the semiconductor die16to respective leads14, and the conductive wires20may extend between the active surface17of the semiconductor die16and inner surfaces of the leads14. A layer of encapsulation material22is formed over the semiconductor die16, and covers the semiconductor die16and the conductive wires20. The encapsulation material22has a first surface23(e.g., an upper surface as shown inFIG.1) and a second surface25(e.g., a lower surface as shown inFIG.1) that is opposite the first surface23. The second surface25extends between the die pad12and the leads14. The first surface23and the second surface25may be exposed surfaces which form parts of an exterior of the semiconductor package10. The die pad12and the leads14may be formed of a same material. For example, the die pad12and the leads14may be provided as part of a same lead frame, which in some embodiments may be a QFN lead frame. In some embodiments, the die pad12and the leads14may be formed of copper, such as a copper lead frame. The die pad12and the leads14have a plurality of surfaces, and a plurality of cavities32may extend into the die pad12or the leads14from at least one of the plurality of surfaces. For example, as shown in the enlarged view of a region A inFIG.1, the leads14may include a plurality of cavities32which extend into leads14from a side surface31. Inner surfaces of the cavities32may be rounded, as shown, which may increase a surface area of the cavities32, thereby promoting increased contact and adhesion with the encapsulant material22. In some embodiments, the cavities32may be semi-spherical shaped cavities. However, embodiments of the present disclosure are not limited thereto, and in various embodiments, the cavities32may have various other shapes. The lead frame, which may include both the die pad12and the leads14, may have a multilayer structure. For example, as shown in the region A, the lead14may include a first layer14aand a second layer14bthat is disposed on the first layer14a. The first and second layers14a,14bmay be formed of a same material, e.g., copper. For example, the second layer14bmay be a layer of copper that is deposited on the first layer14a, which also may be copper. As will be discussed in further detail herein with respect toFIGS.2A to2C, the cavities32may be formed by inclusion of microstructures (such as microbeads, or the like) during deposition of the second layer14b. The microstructures are subsequently removed (e.g., by dissolution), leaving behind the cavities32in the second layer14b. The cavities32may therefore have various different sizes and shapes, depending on the size and shape of the microstructures. In some embodiments, the second layer14bmay have a thickness within a range from 0.5 μm to 10 μm, inclusive. In some embodiments, the second layer14bmay have a thickness within a range from 1 μm to 5 μm, inclusive, and in some embodiments, the second layer14bmay have a thickness within a range from 1 μm to 2 μm, inclusive. The cavities32may have a width (e.g., extending into the second layer14b) that is less than the thickness of the second layer14b, so that the cavities32do not extend into the first layer14a. In some embodiments, the cavities32may have a width that is within a range from 0.5 μm to 5 μm, inclusive, and in some embodiments, the width of the cavities32is within a range from 0.5 μm to 2 μm, inclusive. That is, the cavities32may extend into the second layer14bto a depth that is within a range from 0.5 μm to 5 μm in some embodiments, and may extend to a depth that is within a range from 0.5 μm to 2 μm in some embodiments. In embodiments in which the cavities32are spherical or semi-spherical in shape, the cavities32may have a radius that is within a range from 0.25 μm to 1 μm, inclusive. While the enlarged region A is shown as being a region at a side surface of the lead14, it will be readily appreciated that the same structure may be provided at any of the surfaces of the die pad12or the leads14. For example, one or more surfaces of the die pad12may include first and second layers of lead frame material (e.g., copper layers), and cavities32may extend into the second layer of the material due to inclusion of microstructures during formation of the second layer, which microstructures are subsequently removed to leave the cavities. In various embodiments, some or all of the surfaces of the die pad12and the leads14may be exposed during formation of cavities32and may include the cavities32. As shown in the enlarged region A ofFIG.1, the encapsulant material22substantially fills the cavities32. For example, the encapsulant material22may contact the lead14(e.g., the second layer14b) within the cavities32. Additionally, the encapsulant material22may contact the surface31of the lead14. By filling the cavities32, as well as contacting the lead14at the surface31, adhesion between the encapsulant material22and the leads14is improved. More particularly, mechanical interlock is provided at the interface between the leads14(or the die pad12) and the encapsulant material22and the surface area is increased for increased interfacial interaction between the leads14or die pad12and the encapsulant material22. In some embodiments, one or more of an upper surface11of the die pad12(e.g., a surface of the die pad12that faces the semiconductor die16), a lower surface13of the die pad12(e.g., an exposed surface of the die pad12), and side surfaces15of the die pad12may include a plurality of cavities32. In some embodiments, the die pad12may include recessed portions19which may include cavities32at the surface thereof. For example, the recessed portions19may be formed as recesses which extend into the die pad12from the lower surface13of the die pad12at side edges of the die pad12. The recessed portions19further increase a surface area of contact between the die pad12and the encapsulant material22, thereby increasing the adhesion of the encapsulant material22to the die pad12. As shown inFIG.1, the leads14may similarly include recessed portions which are substantially similar to the recessed portions19of the die pad12and which increase adhesion between the encapsulant material22and the leads14. In some embodiments, the second surface25of the encapsulation material22is an exposed surface which forms a part of an exterior (e.g., part of the bottom surface) of the package10along with outer surfaces of the die pad12(e.g., the lower surface13of the die pad12) and the leads14(e.g., lower and outer side surfaces of the leads14). The encapsulation material22may substantially fill any spaces or gaps between the various components in the package10. As shown inFIG.1, in some embodiments, the encapsulation material22is formed on inner surfaces of the die pad12and the leads14. The encapsulation material22may thus fill or substantially fill the cavities32formed at any of the various surfaces of the die pad12and the leads14. The encapsulation material22is an electrically insulating material that protects the semiconductor die16, conductive wires20, and any other electrical components or wiring from damage, such as corrosion, physical damage, moisture damage, or other causes of damage to electrical devices and materials. Additionally, the encapsulation material22provides structural support to the die pad12and the leads14. In one or more embodiments, the encapsulation material22is a molding compound or an epoxy mold compound, which may include, for example, a polymer resin. The exposed bottom or outer surfaces of the leads14, which may be referred to as lands of the package10, as well as the exposed lower surface13of the die pad12, are configured to electrically or mechanically couple the package10to external circuitry or to another device or board, such as to an external printed circuit board. In some embodiments, a plated conductive layer30may be formed on one or more surfaces of the lead14. For example, the plated conductive layer30may be formed on upper surfaces of the lead14, to which the conductive wires20are bonded. The plated conductive layer30may be resistant to the formation of copper (e.g., when the second layer of material is formed including the microstructures which result in the cavities32), and thus, the plated conductive layer30may remain substantially smooth and free of cavities, thereby providing a suitable conductive surface for bonding with the conductive wires20. The plated conductive layer30may include any electrically conductive material. In some embodiments, the plated conductive layer30includes a plurality of metal layers. In some embodiments, the plated conductive layer30is a multilayer structure including a first layer of nickel (Ni), a second layer of palladium (Pd), and a third layer of gold (Au). The plated conductive layer30may be substantially thinner than the leads14. In some embodiments, the plated conductive layer30may have a thickness less than about 50 μm. FIGS.2A to2Care cross-sectional views showing various stages of a method of forming cavities in a substrate, such as a copper lead frame or a copper substrate, in accordance with one or more embodiments. The method of forming cavities may be referred to herein as an immersion porous copper adhesion promoter (IPC-AP) process. As shown inFIG.2A, a substrate112is provided. The substrate112may be, for example, a copper lead frame which forms the die pad12and the leads14of the semiconductor package10illustrated inFIG.1. The substrate112may have a substantially planar surface111, for example, at an upper surface as shown inFIG.2A. In some embodiments, the method includes pre-treating the substrate112to provide the clean, substantially planar surface111. The pre-treatment may include, for example, degreasing of the substrate112to remove organic surface contaminants or the like. The pre-treatment may further include removal of oxides at the surface111, for example, by microetching or the like. As shown inFIG.2B, a conductive layer112bis formed on the substrate112. The conductive layer112bmay be formed of a same material as the substrate112. For example, the conductive layer112bmay be a copper layer that is formed on the copper substrate112. In some embodiments, the conductive layer112bmay be formed by an electroless or autocatalytic copper deposition or plating process in which the copper substrate112is immersed in a copper bath which forms a plating or a thin layer of the conductive layer112bon the substrate112. In various embodiments, the conductive layer112bmay have a thickness within a range from 0.5 μm to 10 μm, inclusive, a thickness within a range from 1 μm to 5 μm, inclusive, or a thickness within a range from 1 μm to 2 μm, inclusive. As shown inFIG.2B, a plurality of microstructures142are formed concurrently with the formation of the conductive layer112b, so that the microstructures142are at least partially embedded in the conductive layer112b. The microstructures142may be any soluble microstructures which can be removed by exposure to a suitable solvent. In some embodiments, the microstructures142may be polymer microbeads. In some embodiments, the microstructures142may be microbeads formed of or including at least one of polystyrene or polydimethylsiloxane. The microstructures142may have any shape. In some embodiments, the microstructures142may have at least partially rounded exterior portions, so that the cavities are formed to have at least partially rounded shapes. In some embodiments, the microstructures142may be semi-spherical shaped microstructures. The microstructures142may have a width W that is less than the thickness of the conductive layer112b, and the microstructures142may be spaced apart from the substrate112(e.g., the microstructures142do not extend into the substrate112). In some embodiments, the microstructures142may have a width W that is within a range from 0.5 μm to 2 μm, inclusive. In embodiments in which the microstructures142are spherical or semi-spherical in shape, the microstructures142may have a radius that is within a range from 0.25 μm to 1 μm, inclusive. In various embodiments, the sizes and shapes of the microstructures142may be different from one another, depending, for example, on a desired size and shape of resulting cavities to be formed in the lead frame (e.g., the die pad12or leads14). As previously noted, the conductive layer112band the microstructures142may be concurrently formed or plated on the substrate112by an electroless copper deposition or plating process. In some embodiments, the electroless copper deposition or plating process includes immersing the substrate112(e.g., a copper substrate) in a plating bath that includes copper ions (e.g., Cu2+) and the microstructures142. The microstructures142may be an active component of the chemistry in the plating bath, for example, by bonds which may form between the microstructures142and one or more components of the plating bath. In some embodiments, the plating bath may include copper ions (e.g., Cu2+), the microstructures142, and one or more of a reducing agent, an additive, and a complexant. In such embodiments, the microstructures142may be selected to bond with the reducing agent, the additive, or the complexant. Accordingly, the microstructures142may become an active component of the plating bath and may be included as part of the growth or deposition of the conductive layer112b. The electroless copper deposition or plating process may implement or facilitate an autocatalytic reaction of the Cu2+ions in the plating bath with the exposed copper surface of the substrate112, thus affecting only the exposed copper surfaces. Accordingly, in various embodiments, an entire lead frame (e.g., including the die pad12and the leads14shown inFIG.1) may be immersed in the plating bath, and only exposed copper portions of the lead frame may be reacted with the plating bath in order to grow or deposit the conductive layer112bthereon, while non-exposed surfaces (such as surfaces of the leads14covered by the plated conductive layer30) may be protected from reaction and thus cavities may not form on the non-exposed surfaces. In this way, the bonding surfaces (e.g., the plated conductive layer30on the leads14) may not be affected by the IPC-AP process, thereby retaining a substantially smooth surface suitable for wire bonding. As shown inFIG.2B, portions of the microstructures142may extend outwardly beyond an upper surface of the conductive layer112b. This facilitates exposure of the microstructures142with a solvent in order to remove the microstructures142and form the cavities, as will be discussed in further detail with respect toFIG.2C. As shown inFIG.2C, cavities132are formed in the conductive layer112bby removing the microstructures142. In some embodiments, the microstructures142are removed by exposure to a suitable solvent. The solvent may be any solvent which is capable of dissolving the microstructures142, which may be formed of any soluble material. In some embodiments, the solvent includes one or more of acetone, diethyl ether, or dioxane. The solvent may be applied to the microstructures142by any suitable technique, including, for example, immersion of the conductive layer112band microstructures142in a solvent bath, spraying or otherwise introducing the solvent to an upper surface of the structure shown inFIG.2B(e.g., onto the exposed portions of the microstructures142and to upper surfaces of the conductive layer112b), or any other suitable technique. In some embodiments, the entire structure shown inFIG.2B(e.g., including the substrate112, the conductive layer112b, and the microstructures142) may be immersed in a bath of the solvent in order to remove the microstructures142. After removal of the microstructures142, the cavities132are formed and extend into the substrate (e.g., into the conductive layer112bof the substrate112) from a surface131of the substrate. The cavities132provide increased surface area for bonding with an encapsulant material22, and the rounded or semi-spherical shape of the cavities132provide for increased mechanical interlock with the encapsulant material22. FIGS.3A-3Eare cross-sectional views showing various stages of a method of manufacturing semiconductor packages, such as the semiconductor package10ofFIG.1, in accordance with one or more embodiments. As shown inFIG.3A, a substrate or a lead frame is provided that includes a die pad12and a plurality of leads14. A plated conductive layer30may be formed on surfaces (e.g., upper surfaces) of each of the leads14. A plurality of cavities32(seeFIG.1) is formed in exposed surfaces of the die pad12or the leads14. The cavities may be formed at any of the exposed surfaces of the die pad12or the lead14, i.e., at any of the upper, lower, or side surfaces of the die pad12and at any of the lower or side surfaces of the leads14. The upper surfaces of the leads14may be protected from formation of cavities due to the presence of the plated conductive layer30. The cavities may be substantially the same as the cavities32described with respect toFIG.1or the cavities132described with respect toFIG.2C. The substrate (e.g., which forms the die pad12and the leads14) may be any suitable substrate in which the cavities may be formed. In some embodiments, the substrate is a metal substrate, such as a lead frame. In some embodiments, the substrate is a copper substrate. The plurality of cavities may be formed by any suitable techniques, including, for example, according to the method of forming cavities described herein with respect toFIGS.2A to2C. For example, the cavities may be formed by immersing the exposed surfaces of the die pad12and the leads14in an electroless copper deposition or plating bath which includes microstructures142. The microstructures142may thus be embedded in a conductive layer112b, and the microstructures142may subsequently be removed by a solvent leaving behind the cavities132, for example, as described with respect toFIG.2A to2C. In some embodiments, the die pad12or the leads14may include recessed portions19which may be exposed surfaces in which the cavities may be formed. For example, the recessed portions19may be formed as recesses which extend into the die pad12or the leads14from lower surfaces of the die pad12or the leads14. The recessed portions19further increase a surface area of contact between the die pad12or the leads14and the encapsulant material22(which is later formed), thereby increasing the adhesion of the encapsulant material22to the die pad12or the leads14. The plated conductive layer30on the leads14may include any electrically conductive material. In some embodiments, the plated conductive layer30is formed of an electrically conductive material that is resistant to the chemistry in the electroless copper deposition or plating bath, so that cavities are not formed in the plated conductive layer30. In some embodiments, the plated conductive layer30is a multilayer structure including a first layer of nickel (Ni), a second layer of palladium (Pd), and a third layer of gold (Au). The plated conductive layer30may be formed by any suitable technique, including, for example, deposition, electroplating, or the like. As shown inFIG.3B, a semiconductor die16is attached to the die pad12, and wire bonds or conductive wires20are formed between an active surface17of the semiconductor die16and the plated conductive layer30on the leads14. The semiconductor die16may be attached to a surface11(e.g. upper surface) of the die pad12by an adhesive material18. The adhesive material18may be any material suitable to mechanically and/or electrically couple the semiconductor die16to the die pad12, such as conductive glue, paste, tape, or the like. In one or more embodiments, the adhesive material18is a die attach film suitable to attach the semiconductor die16to the die pad12. In some embodiments, the surface11of the die pad12includes cavities formed, for example, by the method illustrated inFIGS.2A to2C. That is, a plurality of cavities may extend into the die pad12from the surface11. In such embodiments, the adhesive material18may extend into, and may be substantially fill, the cavities in the surface11of the die pad12, thereby promoting improved adhesion between the die pad12and the adhesive material18, which also improves adhesion between the die pad12and the semiconductor die16. The conductive wires20may be formed, for example by wire bonding, and the conductive wires20electrically couple bond pads on the active surface17of the semiconductor die16to the leads14. As shown inFIG.3C, a carrier tape340may be applied to the assembly ofFIG.3B(e.g., including the die pad12, leads14, semiconductor die16, and conductive wires20). More particularly, the carrier tape340may be applied to lower surfaces of the die pad12and the leads14. The carrier tape340facilitates transport of the assembly, for example, to a mold cavity for forming the encapsulant22. In some embodiments, the carrier tape340may be omitted. As shown inFIG.3D, the encapsulation material22is formed over the semiconductor die16, and covers the semiconductor die16and the conductive wires20. The encapsulation material22further covers the plated conductive layer30, portions of the surface11of the die pad12, as well as exposed side surfaces of the die pad12and the leads14. The encapsulation material22may further fill the recessed portions19of the die pad12and the leads14. The encapsulation material22substantially fills the plurality of cavities which are formed in surfaces of the die pad12or the leads14, as shown, for example, in the enlarged region A ofFIG.1. Accordingly, improved adhesion and mechanical interlock is provided between the surfaces of the die pad12or the leads14and the encapsulation material22. The encapsulation material22has a first surface23and a second surface25that is opposite the first surface23. The second surface25extends between the die pad12and the leads14. The first surface23and the second surface25may be exposed surfaces which form parts of an exterior of the semiconductor package10. The encapsulation material22may be formed by any conventional techniques, such as by a molding process. For example, the molding process may include positioning the assembly shown inFIG.3C(e.g., including the die pad12, leads14, semiconductor die16, and conductive wires20) into a mold and injecting a molding material, such as a molding compound, an epoxy mold compound, a polymer resin, or the like. The injected material is then hardened, which may involve a curing step. As shown inFIG.3E, the carrier tape340is removed after the encapsulation material22is formed. The carrier tape340may be removed by any suitable technique, including by mechanical separation, cutting, etching, or the like. This encapsulation material22provides suitable structural support to the die pad12and the leads14so that the die pad12and the leads14may generally retain their shape and structure after the carrier tape340has been removed. The completed semiconductor package10is formed after the carrier tape340has been removed, as shown inFIG.3E. By removing the carrier tape340, outer surfaces of the die pad12and the leads14are exposed, and the die pad12and leads14, as well as the second surface25of the encapsulation material22, form exterior surfaces of the semiconductor package10. The exposed outer surfaces of the leads14and the die pad12may be electrically and/or mechanically coupled, for example, to another device or board, such as a printed circuit board. FIG.4shows an electronic device400including a semiconductor package described herein, such as the semiconductor package10. The semiconductor package10is electrically coupled to a microprocessor402. The microprocessor402may be any circuit configured to receive or send electrical signals to the semiconductor package10. The electronic device400may further include a power source404configured to provide electric power for the device400. The power source404, which may be a battery, may be coupled to the microprocessor402. The electric device400may also include a memory406coupled to or incorporated in the microprocessor402. In one or more embodiments, the electronic device400may be a cell phone, smartphone, tablet, camera, and/or wearable computing device that may be located in clothing, shoes, watches, glasses or any other wearable structures. In some embodiments, the electronic device400, or the semiconductor package10itself, may be located in a vehicle, such as boat and car, a robot, or any other moveable structure or machinery. As has been described with respect to various embodiments of semiconductor devices, packages, and methods provided herein, one or more surfaces of a substrate (e.g., a copper lead frame) are processed to improve adhesion between the substrate and an encapsulant material, such as a mold compound or an epoxy mold compound. An electroless copper deposition or plating process is performed on the substrate, in which microstructures such as microbeads are embedded in a deposited or plated copper layer formed on a surface of the substrate. The microbeads may soluble, and may be removed by any solvent, thereby leaving behind a roughened surface in the copper layer. The roughened surface is a surface in which a plurality of cavities are formed and which extend into the substrate from a surface thereof. The roughened surface (e.g., the plurality of cavities) promotes better adhesion with the mold compound, which reduces or prevents delamination between the mold compound and the substrate (e.g., the die pad or the leads). The increased adhesion between the mold compound and the die pad or leads provided by various embodiments of the present disclosure is advantageous over other potential methodologies to increase adhesion. For example, introduction of an oxide layer to the die pad or leads may be employed to increase adhesion, since the functional groups in the mold compound may have preferential interaction with an oxide as compared with unoxidized copper. However, copper oxides (e.g., Cu2O) may be metastable oxides having a tendency to further oxidize (e.g., forming CuO), which is a brittle material susceptible to fracture. This may result in delamination between the mold compound and the die pad or the leads. On the other hand, solutions provided by the present disclosure (e.g., forming cavities in which the mold compound is filled) avoid such formation of oxides and thereby avoid delamination. Moreover, embodiments provided herein provide the increased adhesion between the mold compound and the die pad and leads without mechanically roughening surfaces of the die pads and leads. Mechanical roughening, for example, may disadvantageously result in roughened surfaces of the leads which are bonded by the wire bonds. On the other hand, embodiments of the present disclosure facilitate formation of the cavities by chemical processes, and the bonding surface of the leads (e.g., the plated conductive layer) may be resistant to formation of cavities so that wire bonding problems are avoided. That is, the substantially smooth bonding surface of the leads may be retained after other surfaces of the die pad or leads are roughened (e.g., cavities are formed therein) for increased adhesion with the encapsulation material. The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. | 32,895 |
11862580 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIG.1andFIG.2schematically illustrate a top view and a bottom of a semiconductor package in accordance of some embodiments of the disclosure. Referring toFIGS.1and2, a semiconductor package100includes a wiring substrate110, a semiconductor component120, conductor terminals130, a bottom stiffener140and a top stiffener150. The wiring substrate110has a first, top surface that is the surface shown inFIG.1and a second, bottom surface that is the surface shown inFIG.2. The semiconductor component120and the top stiffener150are disposed on the first surface of the wiring substrate110as shown inFIG.1. The conductor terminals130and the bottom stiffener140are disposed on the second surface of the wiring substrate110. For illustration purpose, the semiconductor component120and the top stiffener150are also presented inFIG.2by using dash lines. The bottom stiffener140and the top stiffener150each has a quadrangular ring-like shape in the plane views such as the top view or the bottom view. In some embodiments, the pattern of the bottom stiffener140and the top stiffener150may be designed based on the various design. For example, the bottom stiffener140or the top stiffener150may have a linear shape, L shape, U shape, dot shape, etc. According to the arrangements of the components shown in the plane views, the bottom stiffener140surrounds the semiconductor component120and the top stiffener150surrounds the bottom stiffener140. The bottom stiffener140may partially or completely overlap the semiconductor component120while the top stiffener150may not overlap the semiconductor component120. In some embodiments, the bottom stiffener140does not overlap the top stiffener150. The bottom stiffener140and the top stiffener150both have higher Young's modulus than the wiring substrate110so that the mechanical property of the wiring substrate110is reinforced and a warpage of the semiconductor package100is mitigated or avoided. InFIG.2, the bottom stiffener140may keep a distance from the semiconductor component120, but the disclosure is not limited thereto. In some embodiments, the bottom stiffener140may overlap the periphery of the semiconductor component120. The wiring substrate110includes a dielectric core layer, build-up or laminated dielectric layers stacked over opposite surfaces of the dielectric core layer, conductive wiring layers embedded in the build-up or laminated dielectric layers, conductive vias penetrating through the dielectric core layer and the build-up or laminated dielectric layers. The semiconductor component120is mounted on the first surface of the wiring substrate110. The semiconductor component120includes at least one semiconductor die, and related connection devices and is electrically connected to the conductive wirings of the wiring substrate110. In some embodiments, the semiconductor component120may include a molding material (not shown) laterally encapsulating the semiconductor die(s) and an interposer (not shown) disposed between the semiconductor die(s) and the wiring substrate110. The conductor terminals130are formed on the second surface of the wiring substrate110and electrically connected to the bottommost (farthest from the semiconductor component120) conductive wiring layer of the wiring substrate110. The conductor terminals130are arranged in an array to form a ball-grid array (BGA) and are used for electrically connecting the semiconductor package100to an external device such as a circuit board (for example, a printed circuit board). Each of the conductor terminals130may include a eutectic material such as solder, although any suitable materials may alternatively be used. The bottom stiffener140is disposed beside the conductor terminals130. In some embodiments, the bottom stiffener140is located between the conductor terminals130. Specifically, the bottom stiffener140has a ring-like shape. Some of the conductor terminals130are positioned within the region surrounded by the ring-like bottom stiffener140and some of the conductor terminals130are position outside the ring-like bottom stiffener140. The conductor terminals130are electrically connected to the semiconductor component120at the first surface of the wiring substrate110through the conductive wiring layers formed in the wiring substrate110. The top stiffener150is disposed beside the semiconductor component120and is made of a material such as metal, stainless steel, steel, etc. The top stiffener150is a bulk metallic structure that involves desirable heat dissipation effect and mechanical property. The bottom stiffener140and the top stiffener150on opposite surfaces of the wiring substrate110form no electric connection to the wiring substrate110, the semiconductor component120and the conductor terminals130. The paths of electrical signals of the semiconductor component120may not pass through either the bottom stiffener140or the top stiffener150. The bottom stiffener140is positioned between the top stiffener150and the semiconductor component120. Specifically, the top stiffener150keeps a gap150G from the semiconductor component120and the bottom stiffener140may be positioned overlapping the gap150G without overlapping the top stiffener150such that the top stiffener150is laterally spaced further away from the semiconductor component120than the bottom stiffener140, but the disclosure is not limited thereto. In some embodiments, a width W140of the bottom stiffener140is smaller than a width W150of the top stiffener150. In the disclosure, the widths of two elements that are compared with each other are measured in the same measure line crossing through the two elements. Alternatively, the widths of two elements that are compared with each other are measured in the same cross section of the semiconductor package100that is taken along a straight linear line. In some embodiments, the width W150of the top stiffener150may be greater than 3 mm and smaller than a width difference of the semiconductor package100and the semiconductor component120. In some embodiments, the width W140of the bottom stiffener140may be smaller than 1 mm and may be similar to the dimeter of the conductor terminals130. In some embodiments, the semiconductor component120has a coefficient of thermal expansion (CTE) smaller than the wiring substrate110. For example, the semiconductor component120may include at least one semiconductor die having a CTE of about 3 ppm and the wiring substrate110may have an effective CTE of about 14 ppm. The mismatch of CTE between the semiconductor component120and the wiring substrate110would result in additional stress in the semiconductor package100under temperature changes. The bottom stiffener140and the top stiffener150both have a Young's modulus higher than the wiring substrate110so that the mechanical property of the wiring substrate110is reinforced to bear the stress caused by the mismatch of CTE between the semiconductor component120and the wiring substrate110. For example, the wiring substrate110is prevented from warpage under the temperature changes, which improves yield and reliability of the semiconductor package100. The bottom stiffener140has a Young's modulus greater than about 100 Gpa and less than about 1,200 Gpa. The bottom stiffener140has a CTE less than about 10 ppm and greater than about 1 ppm. In some embodiments, a material of the bottom stiffener140includes, for example, silicon, silicon carbide, tungsten, tungsten carbide, etc. In some embodiments, the material of the bottom stiffener140is different from a material of the top stiffener150. The material of the top stiffener150may include copper, stainless steel, steel, metal alloy, or the like. Both the bottom stiffener140and the top stiffener150reinforce the mechanical property of the semiconductor package100and thus the yield and the reliability of the semiconductor package100are improved. FIG.3schematically illustrates a cross sectional view of a semiconductor package taken along line I-I ofFIG.1. The semiconductor package100is similar to the semiconductor package depicted inFIGS.1and2and includes the wiring substrate110, the semiconductor component120, the conductor terminals130, the bottom stiffener140and the top stiffener150that are described in the descriptions forFIG.1andFIG.2. Specifically,FIG.3further presents at least a portion of the details of the semiconductor component120and the connection relationship of the wiring substrate110, the semiconductor component120, the conductor terminals130, the bottom stiffener140and the top stiffener150in a cross sectional view. The semiconductor component120includes at least one singulated structure SS, conductive bumps BP and an underfill UF. The singulated structure SS may include semiconductor die (not shown), a molding material (not shown) surrounding and encapsulating the semiconductor die, and an interposer (not shown) carrying the encapsulated semiconductor die(s). In some embodiments, the singulated structure SS may be singulated from a packaged wafer. The conductive bumps BP are formed on the singulated structure SS at the surface facing the wiring substrate110. Specifically, the semiconductor component120is mounted onto the first surface112of the wiring substrate110through the conductive bumps BP by performing a wafer-level bumping process. The underfill UF is disposed between the singulated structure SS and the wiring substrate110to fill gaps between the conductive bumps BP. The semiconductor package100may be a Chip-on-Wafer-on-Substrate (CoWoS) package. The bottom stiffener140is adhered onto the second surface114of the wiring substrate110through an adhesive142and the top stiffener150is adhered onto the first surface112of the wiring substrate110through an adhesive152. In some embodiments, the material of the adhesive142may be the same as the adhesive152. The top stiffener150keeps the gap150G from the semiconductor component120. In some embodiments, the underfill UF may be formed after the top stiffener150being adhered onto the wiring substrate110and the gap150G facilitates the proceeding of forming the underfill UF. The width of the gap150G may be sufficient to allow the formation of the underfill UF, but the disclosure is not limited thereto. The wiring substrate110may divide into a center region110A, a first peripheral region110B surrounding the center region110A and a second peripheral region110C surrounding the first peripheral region110B. The semiconductor component120is disposed on the first surface112of the wiring substrate110at the center region110A. In some embodiments, an orthogonal projection of the semiconductor component120onto the wiring region100A defines the center region110A. The top stiffener150is disposed on the first surface112of the wiring substrate110at the second peripheral region110C. The top stiffener150defines the second peripheral region110C of the wiring substrate110. The first peripheral region110B is corresponding the gap150G between the semiconductor component120and the top stiffener150. In the embodiment, a boundary BB is formed between the first peripheral region110B and the second peripheral region110C. The top stiffener150is disposed on the wiring substrate110away from the semiconductor component120from the boundary BB between the first peripheral region110B and the second peripheral region110C. The bottom stiffener140is located at least partially in the first peripheral region110B without exceeding the boundary BB. In some embodiments, the bottom stiffener140is completely located within the area demarked by the boundary BB. Alternatively, the bottom stiffener140may be completely located outside the second peripheral region110C. In some embodiments, the bottom stiffener140may partially or completely locate within the center region110A so that the bottom stiffener140may at least partially overlap the semiconductor component120while not overlapping the top stiffener150. In some embodiments, the bottom stiffener140may keep a distance from the edge of the semiconductor component120as presented inFIG.1. A distal surface T140of the bottom stiffener140away from the wiring substrate110is leveled between the second surface114of the wiring substrate110and a distal surface T130of one conductor terminal130away from the wiring substrate110. In other words, the distal surface T140of the bottom stiffener140keeps a distance H140from the second surface114of the wiring substrate110, the distal surface T130of the conductor terminal130keeps a distance H130from the second surface114of the wiring substrate110, and the distance H130is not smaller than the distance H140. Usually, the distance H140is smaller than the distance H130. The conductor terminal130is relatively protruded further from the wiring substrate110than the bottom stiffener140so that the conductor terminal130may be connected to and in contact with an external device without difficulty. In some embodiments, the width W140of the bottom stiffener140in the cross section ofFIG.3may be proximate to a width W130of one conductor terminal130. A top surface T150of the top stiffener150is leveled between the first surface112of the wiring substrate110and a top surface T120of the semiconductor component120away from the first surface112of the wiring substrate110. In other words, the top surface T120of the semiconductor component120is further from the first surface112than the top surface T150of the top stiffener150. In some embodiments, another component such as a heat sink may be attached to the semiconductor component120on the top surface T120without difficulty. The wiring substrate110and the semiconductor component120have different CTEs. For example, a semiconductor die in the semiconductor component120may have a CTE of 3 ppm and the wiring substrate110may have an effective CTE of 14 ppm. The material of the bottom stiffener140has low CTE and high Young's modulus. The bottom stiffener140located proximate to and/or overlapping the semiconductor component120helps to reinforce the mechanical property of the semiconductor package100so that the damage caused by the CTE mismatch between the wiring substrate110and the semiconductor component120may be mitigated or prevented. The width W140of the bottom stiffener140is smaller than a width W150of the top stiffener150. In some embodiments, a volume of the bottom stiffener140is less than a volume of the top stiffener150. The material of the top stiffener150may include copper, stainless steel, steel, metal alloy or the like. The bulk metallic top stiffener150also helps to enhance the mechanical property of the semiconductor package100so that the damage caused by the CTE mismatch between the wiring substrate110and the semiconductor component120may be mitigated or prevented. FIG.4schematically illustrates a cross sectional view of a semiconductor package taken in accordance with some embodiments. The semiconductor package200includes the wiring substrate110, the semiconductor component120, the conductor terminals130, the bottom stiffener140and the top stiffener150that are described in above and further includes a heat sink260. The structures, the disposition relationships, the materials and the properties of the wiring substrate110, the semiconductor component120, the conductor terminals130, the bottom stiffener140and the top stiffener150may refer to the previous embodiments depicted in at least one ofFIGS.1to3and are not reiterated here. In the embodiment, the heat sink260is attached onto the top surface T120of the semiconductor component120through a thermal interface material (TIM)262. The heat sink260is thermally coupled to the top surface T120of the semiconductor component120and thermally coupled to the top surface T150of the top stiffener150through the thermal interface material262. The thermal interface material262include a portion262A on the top surface T120of the semiconductor component120and a portion262B on the top surface T150of the top stiffener150. The heat sink260has a planar coupling surface S260facing the wiring substrate110. A distance D260between the coupling surface S260of the heat sink260and the first surface112of the wiring substrate110is identical at the center region110A, the first peripheral region110B and the second peripheral region110C. In some embodiments, a thickness of the portion262B of the thermal interface material262is greater than a thickness of the portion262A of the thermal interface material262. The portion262B of the thermal interface material262and the portion262A of the thermal interface material262are made of the material having desirable heat dissipation effect. The material of the heat sink260may include copper, aluminum, cobalt, copper coated with nickel, stainless steel, tungsten, silver diamond, aluminum silicon carbide or the like. The material of the thermal interface material262may include metallic TIM, such as indium (In) sheet or film, indium foil, indium solder, silver (Ag) paste, silver alloy or combination thereof. The thermal interface material262may also be polymer-based TIM with thermal conductive fillers. Applicable thermal conductive filler materials may include aluminum oxide, boron nitride, aluminum nitride, aluminum, copper, silver, indium, a combination thereof, or the like. The thermal interface material262may include film-based or sheet-based material such as sheet with synthesized carbon nano-tube (CNT) structure integrated into the sheet, thermal conductive sheet with vertically oriented graphite fillers or the like. FIG.5schematically illustrates a package structure in accordance with some embodiments of the disclosure. A package structure300includes the semiconductor package200and a circuit board370(e.g., a printed circuit board) is illustrated. The semiconductor package200is disposed on and electrically connected to the circuit board370through the conductor terminals130, such that the semiconductor component120in the semiconductor package200is electrically connected to the circuit board370through the wiring substrate110and the conductor terminals130. In the embodiment, the semiconductor package200may be similar to that described in above, the same or similar reference numbers indicated in these embodiments may refer as similar or the same elements and the details of those elements may refer to the above descriptions and not reiterated here. The conductor terminals130and the bottom stiffener140in the semiconductor package200are located between the wiring substrate110and the circuit board370. The bottom stiffener140keeps a gap G140from the circuit board370. In other words, the bottom stiffener140is not in contact with the circuit board370. Therefore, the disposition of the bottom stiffener140does not limit the contact between the conductor terminals130and the circuit board370. The reliability of the physical and electrical connection between conductor terminals130and the circuit board370is ensured. In some embodiments, a further underfill380is formed between the wiring substrate110and the circuit board370, and laterally encapsulates the conductor terminals130and the bottom stiffener140. FIG.6andFIG.7schematically illustrate a top view and a bottom of a semiconductor package in accordance of some embodiments of the disclosure. Referring toFIGS.6and7, a semiconductor package400includes a wiring substrate110, a semiconductor component420, conductor terminals130, a bottom stiffener140and a top stiffener150. The semiconductor package400shown inFIGS.6and7is substantially similar to the semiconductor package100shown inFIGS.1and2, and the same and similar reference numbers depicted in these figures present the same or similar components. Specifically, the wiring substrate110, as described in above, includes a dielectric core layer, build-up or laminated dielectric layers stacked over opposite surfaces of the dielectric core layer, conductive wiring layers embedded in the build-up or laminated dielectric layers, conductive vias penetrating through the dielectric core layer and the build-up or laminated dielectric layers. The semiconductor component420and the top stiffener150are disposed on and attached to the first, top surface of the wiring substrate110shown inFIG.6and the conductor terminals130and the bottom stiffener140are disposed on the second, bottom surface of the wiring substrate110shown inFIG.7. InFIG.7, the top stiffener150and the semiconductor component420are presented by using dash lines for illustration purpose though the semiconductor component420is actually disposed on the first surface of the wiring substrate110. InFIG.6, the semiconductor component420includes two semiconductor dies422A and422B and a molding material424surrounding and encapsulating the semiconductor dies422A and422B. In some embodiments, the semiconductor component420may include one single semiconductor die or more that two semiconductor dies. The top stiffener150forms a ring-like shape surrounding the periphery of the semiconductor package400. The outer edge of the top stiffener150may be substantially overlapped and aligned with the outer edge of the wiring substrate110so thatFIG.6does not show the outer edge of the wiring substrate110. The top stiffener150is spaced from the semiconductor component420by a gap150G without overlapping the semiconductor component420. In some embodiments, a width W150of the top stiffener150may be 3 mm or more and the gap150G may be smaller than the width W150. InFIG.7, the conductor terminals130are arranged in an array over the second, bottom surface of the wiring substrate110to form a ball grid array (BGA) and each of the conductor terminals130may include a eutectic material such as solder, although any suitable materials may alternatively be used. The bottom stiffener140is located between the conductor terminals130. The bottom stiffener140has a ring-like shape surrounding an area where the semiconductor component420is, but the disclosure is not limited thereto. In some embodiments, the bottom stiffener140may have a linear shape, an L shape, a U shape, or other shapes and a quantity of the bottom stiffener140be multiple. A width W140of the bottom stiffener140measured along a direction perpendicular to the elongation of the linear portion of the bottom stiffener140is proximate to a width W130of the conductor terminals130. In some embodiments, the width W140of the bottom stiffener140may be not greater than 1 mm. In some embodiments, the stress subjected by the wiring substrate110may be generated due to the CTE mismatch between the semiconductor dies422A and422B and the wiring substrate110. For example, the semiconductor dies422A and422B may have a CTE of 3 ppm and the wiring substrate110may have an effective CTE of 14 ppm. In the case the semiconductor package400suffers a temperature change during operation or testing, certain stress would be generated due to such CTE mismatch between the semiconductor dies422A and422B and the wiring substrate110. In the embodiment, the bottom stiffener140and the top stiffener150provide a reinforce effect to mitigate the warpage of the wiring substrate110to achieve a desired reliability and yield. In the embodiment, a die gap DG is formed between the semiconductor dies422A and422B so as to laterally space the semiconductor dies422A and422B from each other and a virtual extension line VL of the die gap DG would intersect with the an elongation portion E140of the bottom stiffener140. The bottom stiffener140has lower CTE and higher Young's modulus than the wiring substrate110. Therefore, the arrangement of the bottom stiffener140helps to prevent the warpage of the wiring substrate110. Similarly, the top stiffener150also has suitable mechanical property to prevent from the warpage of the wiring substrate110. The semiconductor package400has improved yield and reliability since the bottom stiffener140and the top stiffener150reinforce the mechanical property of the wiring substrate110. In some embodiments, the interesting of the virtual extension line VL and the elongation portion E140may prevent from a warpage of the wiring substrate110bending about the virtual extension line VL. FIG.8schematically illustrates a cross sectional view of a semiconductor package taken along line II-II ofFIG.6. The semiconductor package400as described inFIGS.6and7includes the wiring substrate110, the semiconductor component420, the conductor terminals130, the bottom stiffener140and the top stiffener150. The same or similar reference numbers indicated inFIGS.6to8refer to the same or similar elements and the descriptions forFIGS.6and7may be incorporated in the embodiment ofFIG.8. The wiring substrate110has a first surface112and a second surface114opposite to the first surface112. The semiconductor component420and the top stiffener150are disposed on the first surface112of the wiring substrate110. The conductor terminals130and the bottom stiffener140are disposed on the second surface114of the wiring substrate110. The wiring substrate110includes a dielectric core layer, build-up or laminated dielectric layers stacked over opposite surfaces of the dielectric core layer, conductive wiring layers embedded in the build-up or laminated dielectric layers, conductive vias penetrating through the dielectric core layer and the build-up or laminated dielectric layers. The semiconductor component420is mounted on the first surface112of the wiring substrate110through a wafer-level bumping process and is electrically connected to the wiring substrate110. The conductor terminals130are formed on the second surface114of the wiring substrate110. The top stiffener150is adhered onto the first surface112of the wiring substrate110. The bottom stiffener140is adhered onto the second surface114of the wiring substrate110. The semiconductor component420may include two semiconductor dies422A and422B, a molding material424laterally surrounding and encapsulating the semiconductor dies422A and422B, and at least one interposer426carrying the semiconductor dies422A and422B. Each of the semiconductor dies422A and422B has electrical circuitry formed therein and may include electrical components, contact structures and wirings for electrically connecting the electrical components to form required electrical circuitry. For example, the electrical components may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and/or the like, interconnected to perform one or more functions, wherein the functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. The above examples are provided for illustrative purposes only to further explain applications of some illustrative embodiments and are not meant to limit the disclosure. The semiconductor component420is oriented that the active surfaces of the semiconductor dies422A and422B face the wiring substrate110. In some embodiments, one of the semiconductor dies422A and422B includes logic dies, System-on-Chip (SoC) dies or other suitable semiconductor dies, and the other of the semiconductor dies422A and422B includes High Bandwidth Memory (HBM) cubes each having stacked memory dies or other suitable semiconductor dies. The interposer426may be a silicon interposer wafer including multiple silicon interposers or other suitable semiconductor interposer wafer. The interposer426may include a substrate426S, and conductor structures426C forming electric transmission paths penetrating through the substrate426S. First bump pads426P1are disposed on an upper surface of the substrate426S, second bump pads426P2are disposed on a lower surface of the substrate426S, and the first bump pads426P1are electrically connected to the corresponding second bump pads426P2through the conductor structures426C. In some embodiments, the conductor structures426C may include at least one through via that extends from the upper surface of the substrate426S to the lower surface of the substrate426S. The semiconductor dies422A and422B are connected to the interposer426through conductive bumps BP1. Specifically, the semiconductor dies422A and422B are formed with bump pads422P and the conductive bumps BP1are disposed between the first bump pads426P1on the interposer426and the bump pads422P on the semiconductor dies422A and422B. The conductive bumps BP1may be formed through a wafer-level bumping process. In some embodiments, the conductive bumps BP1include micro bumps. The conductive bumps BP1may each include a copper (Cu) pillar covered by a nickel (Ni) cap, and the nickel (Ni) cap may be electrically connected to the first bump pads426P1through solder material. For example, the solder material includes Sn—Ag solder material or other suitable solder material. An underfill UF1is formed over the interposer426to fill gaps between the semiconductor die422A and the interposer426as well as gaps between the semiconductor die422B and the interposer426. The underfill UF1laterally encapsulates the conductive bumps BP1so that the conductive bumps BP1are sealed by the underfill UF1. The underfill UF1is made of dielectric material without electrical connecting to the conductive bumps BP1. The material of the underfill UF1includes polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. The molding material424is disposed on the interposer426and laterally encapsulates the underfill UF1and the semiconductor dies422A and422B. The top surface T422A of the semiconductor die422A, the top surface T422B of the semiconductor die422B, and the top surface T424of the molding material424are leveled with each other to define the top surface T420of the semiconductor component420. The molding material424may be formed by an over-molding process or a deposition process followed by a removal process to form the top surface T420. In some embodiments, an insulating material such as epoxy resin is formed on the interposer426to cover the back surfaces and sidewalls of the semiconductor dies422A and422B through an over-molding process, and a grinding process, a chemical mechanical polishing (CMP) process or other suitable removal process is then performed to remove portions of the epoxy resin until the semiconductor dies422A and422B are revealed without damaging the circuit elements formed in the semiconductor dies422A and422B. In some alternative embodiments, an insulating material such as tetraethoxysilane (TEOS) formed oxide is formed on the interposer426to cover back surfaces and sidewalls of the semiconductor dies422A and422B through a chemical vapor deposition (CVD) process, and a grinding process, a CMP process or other suitable removal process is then performed to remove portions of the TEOS formed oxide until the semiconductor dies422A and422B are revealed. without damaging the circuit elements formed in the semiconductor dies422A and422B Accordingly, the top surface T422A of the semiconductor die422A, the top surface T422B of the semiconductor die422B, and the top surface T424of the molding material424are leveled with each other to construct the top surface T420of the semiconductor component420. Conductive bumps BP2are formed on the second bump pads426P2of the interposer426. The semiconductor component420is mounted onto the first surface112of the wiring substrate110through the conductive bumps BP2by performing a wafer-level bumping process. In other words, the conductive bumps BP2may be formed by performing wafer-level bumping process. The conductive bumps BP2include micro bumps. The conductive bumps BP2may each include a copper (Cu) pillar covered by a nickel (Ni) cap, and the nickel (Ni) cap may be electrically connected to the pads on the wiring substrate110through solder material. For example, the solder material includes Sn—Ag solder material or other suitable solder material. An underfill UF2is further disposed between the interposer426and the wiring substrate110to fill gaps between the conductive bumps BP2. The underfill UF2laterally encapsulates the conductive bumps BP2so that the conductive bumps BP2are sealed by the underfill UF2. The underfill UF2is made of dielectric material without electrical connecting to the conductive bumps BP2. The material of the underfill UF2includes polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. The semiconductor package400including the wiring substrate110and the singulated structure of the semiconductor dies422A and422B disposed on the interposer426may be a Chip-on-Wafer-on-Substrate (CoWoS) package. The bottom stiffener140is adhered onto the second surface114of the wiring substrate110through an adhesive142and the top stiffener150is adhered onto the first surface112of the wiring substrate110through an adhesive152. In some embodiments, the material of the adhesive142may be the same as the adhesive152. The bottom stiffener140has a Young modulus higher than 100 Gpa and a CTE lower than 10 ppm. A material of the bottom stiffener140includes, for example, silicon, silicon carbide, tungsten, tungsten carbide, etc. The top stiffener150has desirable mechanical properties such as good thermal conductivity and may be made of a material of copper, stainless steel, steel, metal alloy, or the like so as to provide a heat dissipation effect. As shown inFIGS.6to8, the top stiffener150keeps a gap150G from the semiconductor component420. The bottom stiffener140extends along the periphery of the semiconductor component420and may be partially overlapped with the semiconductor component420. In some embodiments, the bottom stiffener140may not overlap the top stiffener150. The arrangements of the bottom stiffener140and the top stiffener150help to prevent the wiring substrate110from warpage caused by the stress due to the CTE mismatch between the semiconductor dies422A and422B and the wiring substrate110so as to improve reliability of the semiconductor package400and achieve desired yield. The semiconductor package400may be combined with a heat sink and may be bonded to a circuit board as shown inFIG.9. A package structure500may include the semiconductor package400depicted inFIGS.6to8, a heat sink260and a circuit board370. The heat sink260is attached to the semiconductor package400through the thermal interface material262. The thermal interface material262includes a portion262A formed on the top surface T420of the semiconductor component420of the semiconductor package400and a portion262B formed on the top stiffener150. The coupling surface S260of the heat sink260facing the wiring substrate110may keep a constant distance from the wiring substrate110at the region where the semiconductor component420is and the region where the top stiffener150is. In other words, the coupling surface S260of the heat sink260is a planar surface without a staggered structure. The semiconductor package400is disposed on and electrically connected to the circuit board370through the conductor terminals130. The circuit board370includes dielectric layers and conductor metal layer between the dielectric layers. The bottom stiffener140may keep a distance from the circuit board370without contacting with the circuit board, which helps to ensure the bonding reliability between the conductor terminals130and the circuit board370. In addition, a further underfill380is formed between the wiring substrate110and the circuit board370, and laterally encapsulates the conductor terminals130and the bottom stiffener140. FIG.10schematically illustrates a bottom view of a semiconductor package in accordance with some embodiments. For illustration purpose,FIG.10though presents the bottom view of the semiconductor package, also shows the elements of the semiconductor package that is disposed on the top surface of the semiconductor package by using dash lines. A semiconductor package600includes a wiring substrate110, a semiconductor component420, conductor bumps130, bottom stiffeners640A and640B, and a top stiffener150. The structure, the disposition, the material and the property of each of the wiring substrate110, the semiconductor component420, the conductor terminals130and the top stiffener150may refer to the description in the above embodiment ofFIGS.6to8. Specifically, the semiconductor package600may be modified from the semiconductor package400by disposing multiple bottom stiffener640A and640B on the wiring substrate110. Therefore, the same elements in the semiconductor package400and the semiconductor package600are not reiterated here. The bottom stiffener640A may be arranged in a manner similar to the bottom stiffener140described in the previous embodiment. The bottom stiffener640A has a ring-like shape that surrounds the semiconductor component420having multiple semiconductor dies422A and422B. The bottom stiffener640A forms a ring-like shape. The bottom stiffener640B is located within the area circled by the bottom stiffener640A. The bottom stiffener640B may be completely located within the projection area of the semiconductor component420on the wiring substrate110. The material of the bottom stiffener640A and the bottom stiffener640B may be the same or different. Both the bottom stiffener640A and the bottom stiffener640B have a CTE smaller than 10 ppm and a Young's modulus greater than 100 Gpa. A material for the bottom stiffeners640A and640B may be selected from at least one of silicon, silicon carbide, tungsten, tungsten carbide, etc. The bottom stiffener640A and the bottom stiffener640B form a dual ring pattern, but the disclosure is not limited thereto. In some embodiments, one or both of the bottom stiffener640A and the bottom stiffener640B may have linear shape, diamond shape, other polygonal shape, cross shape, or the like. In some embodiments, the semiconductor package600may have more bottom stiffeners. FIG.11schematically illustrates a bottom view of a semiconductor package in accordance with some embodiments. A semiconductor package700is similar to the semiconductor package400described in the above embodiment ofFIGS.6to8. Specifically, the semiconductor package700may be modified from the semiconductor package400by replacing the bottom stiffener140with multiple bottom stiffeners740A and740B. Therefore, the same elements in the semiconductor package400and the semiconductor package700are not reiterated here. The bottom stiffener740A includes a bar portion B740A and two finger portion F740A connected to two opposite terminal of the bar portion B740A. Similarly, the bottom stiffener740B includes a bar portion B740B and two finger portions F740B connected to two opposite terminal of the bar portion B740B. Accordingly, the bottom stiffener740A and the bottom stiffener740B each has a U-like shape and the U-like shape of the bottom stiffener740A and the U-like shape of the bottom stiffener740B are arranged opposite to each other to surround the semiconductor component420. In some embodiments, one or both of the bottom stiffener740A and the bottom stiffener740B may include more finger portions or only one single finger portion. In some embodiments, the finger portions of the bottom stiffener740A may be connected to the finger portions of the bottom stiffener740B. The semiconductor component420has semiconductor dies422A and422B that are separated from each other by a die gap DG. The elongation of the bar portions B740A and B740B may intersect with a virtual extension line of the die gap DG. Accordingly, the warpage of the wiring substrate110bending about the virtual extension line of the die gap DG may be prevented by the reinforcement of the bottom stiffeners740A and740B. FIG.12schematically illustrates a bottom view of a semiconductor package in accordance with some embodiments. A semiconductor package800is similar to the semiconductor package700described in the above embodiment ofFIG.11. Specifically, the semiconductor package800may be modified from the semiconductor package700by changing the shapes of the bottom stiffeners840A and840B. Therefore, the same elements in the semiconductor package700and the semiconductor package800are not reiterated here. The bottom stiffener840A and the bottom stiffener840B both have a bar-like shape. The semiconductor component420has semiconductor dies422A and422B that are separated from each other by a die gap DG. The elongations of the bar-like shape of the bottom stiffener840A and the bar-like shape of the bottom stiffener840B may intersect with a virtual extension line of the die gap DG. Accordingly, the warpage of the wiring substrate110bending about the virtual extension line of the die gap DG may be prevented by the reinforcement of the bottom stiffeners840A and840B. In some embodiments, the quantity of the bottom stiffeners840A and840B may be one, or more than two. In some embodiments, the bar-like shaped bottom stiffeners may not be parallel to each other. FIG.13schematically illustrates a bottom view of a semiconductor package in accordance with some embodiments. A semiconductor package900includes a wiring substrate110, a semiconductor component920, conductor terminals130, and a bottom stiffener940and is similar to the semiconductor package400described in the above embodiment ofFIGS.6to8. Specifically, the semiconductor package900may be modified from the semiconductor package400by changing the numbers of the semiconductor dies and changing the shape of the bottom stiffener. Therefore, the same elements in the semiconductor package400and the semiconductor package900are not reiterated here. In the embodiment, the semiconductor component920includes three semiconductor dies922A,922B and922C. A die gap DG1separates the semiconductor die922A from the semiconductor die922B and the semiconductor die922C and a die gap DG2separates the semiconductor die922B from the semiconductor die922C. The die gap DG1and the die gap DG2extends along different direction and are connected to each other. The die gap DG1and the die gap DG2may form a T-like shaped gap, but the disclosure is not limited thereto. The bottom stiffener940has a U-like shape and includes a bar portion B940and two finger portions F940connected to two opposite terminal of the bar portion B940. The elongations of the finger portions F940may intersect with a virtual extension line of the die gap DG1and the elongation of the bar portion B940may intersect with a virtual extension line of the die gap DG2. The semiconductor package in accordance with some embodiments includes a bottom stiffener disposed on the bottom side of the semiconductor package where the conductor terminals are disposed. The bottom stiffener has low CTE and high Yong modulus so as to enhance the mechanical property of the semiconductor package. The semiconductor package has improved reliability under the reinforcement of the bottom stiffener. In some embodiments, the bottom stiffener is shorter than the conductor terminals in the thickness direction so that the connection of the conductor terminals to an external device such as a circuit board is ensured without blocking by the bottom stiffener. In accordance with some embodiments of the disclosure, a semiconductor package includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener. In some embodiments, the bottom stiffener partially overlaps the semiconductor component. In some embodiments, the top stiffener keeps a gap from the semiconductor component and the bottom stiffener is positioned overlapping the gap. In some embodiments, the semiconductor component includes semiconductor dies with a die gap between each other and a virtual extension line of the die gap intersects with an elongation of the bottom stiffener. In some embodiments, a material of the bottom stiffener is different from a material of the top stiffener. In some embodiments, a distal surface of the bottom stiffener away from the wiring substrate is leveled between the wiring substrate and a distal surface of one conductor terminal away from the wiring substrate. In some embodiments, a top surface of the top stiffener is leveled between the wiring substrate and a top surface of the semiconductor component away from the wiring substrate. In accordance with some other embodiments of the disclosure, a semiconductor package includes a wiring substrate, a semiconductor component, a bottom stiffener, and a top stiffener. The wiring substrate has a center region, a first peripheral region and a second peripheral region, wherein the first peripheral region surrounds the center region and the second peripheral region surrounds the first peripheral region. The semiconductor component is disposed on the wiring substrate at the center region. The bottom stiffener is disposed on the wiring substrate between the semiconductor component and a boundary between the first peripheral region and the second peripheral region. The top stiffener is disposed on the wiring substrate away from the semiconductor component from the boundary between the first peripheral region and the second peripheral region. In some embodiments, the semiconductor component and the top stiffener are disposed at a first surface of the wiring substrate, and the bottom stiffener is disposed at a second, opposite surface of the wiring substrate. In some embodiments, the bottom stiffener is adhered onto the wiring substrate. In some embodiments, a heat sink is further attached onto the semiconductor component. In some embodiments, the heat sink has a planer coupling surface attaching to the semiconductor component. In some embodiments, the heat sink is attached to the semiconductor component through a thermal interface material. In some embodiments, a conductor terminal is further disposed on the wiring substrate beside the bottom stiffener, wherein a distal surface of the bottom stiffener away from the wiring substrate is leveled between the wiring substrate and a distal surface of one conductor terminal away from the wiring substrate. In some embodiments, a width of the bottom stiffener is smaller than a width of the top stiffener. In some embodiments, a coefficient of thermal expansion of the bottom stiffener is lower than an effective coefficient of thermal expansion of the wiring substrate. In accordance with some other embodiments of the disclosure, a semiconductor package includes a wiring substrate, a semiconductor component, conductor terminals, and a bottom stiffener. The wiring substrate has a first surface and a second, opposite, surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals, wherein a distal surface of the bottom stiffener away from the wiring substrate is leveled between the wiring substrate and a distal surface of one conductor terminal away from the wiring substrate. In some embodiments, the bottom stiffener overlaps the semiconductor component and a coefficient of thermal expansion of the bottom stiffener is lower than an effective thermal expansion coefficient of the wiring substrate. In some embodiments, a top stiffener is further disposed on the first surface of the wiring substrate, wherein a top surface of the top stiffener is leveled between the wiring substrate and a top surface of the semiconductor component away from the wiring substrate. In some embodiments, the bottom stiffener extends along a periphery of the semiconductor component. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 51,563 |
11862581 | DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. The shape and size of constituent elements in the drawings may be exaggerated or reduced for clarity. Electronic Device FIG.1is a schematic block diagram illustrating an example of an electronic device system. Referring toFIG.1, an electronic device1000may accommodate a main board1010therein. The main board1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to other components, as described below, to form various signal lines1090. The chip related components1020may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components1020are not limited thereto, and may also include other types of chip related components. In addition, the chip related components1020may be combined with each other. The network related components1030may include components implementing protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access plus (HSPA+), high speed downlink packet access plus (HSDPA+), high speed uplink packet access plus (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols designated after the abovementioned protocols. However, the network related components1030are not limited thereto, and may include a variety of other wireless or wired standards or protocols. In addition, the network related components1030may be combined with each other, together with the chip related components1020described above. Other components1040may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components1040are not limited thereto, and may also include passive components used for various other purposes, or the like. In addition, other components1040may be combined with each other, together with the chip related components1020or the network related components1030described above. Depending on a type of the electronic device1000, the electronic device1000may include other components that may or may not be physically or electrically connected to the main board1010. These other components may include, for example, a camera module1050, an antenna1060, a display device1070, a battery1080, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, and may also include other components used for various purposes depending on a type of electronic device1000, or the like. The electronic device1000may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device1000is not limited thereto, but may be any other electronic device processing data. FIG.2is a schematic perspective view illustrating an example of an electronic device. Referring toFIG.2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the main board1010, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above. Semiconductor Package Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in itself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip may not be used by itself, but is instead packaged and used in an electronic device or the like in a package state. The reason why semiconductor packaging is commonly used is that there is generally a difference in a circuit width between the semiconductor chip and a main board of the electronic device in terms of electrical connection. In detail, a size of contact pads of the semiconductor chip and an interval between the contact pads of the semiconductor chip are very fine, but a size of component mounting pads of the main board used in the electronic device and an interval between the component mounting pads of the main board are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and use of packaging technology for buffering a difference in a circuit width between the semiconductor and the main board is thus advantageous. A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof. The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings. Fan-In Semiconductor Package FIGS.3A and3Bare schematic cross-sectional views illustrating a fan-in semiconductor package before and after being packaged, andFIG.4shows a series of schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package. Referring toFIGS.3A,3B and4, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, contact pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the contact pads2222. In this case, since the contact pads2222are significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the main board of the electronic device, or the like. Therefore, depending on a size of the semiconductor chip2220, a connection member2240may be formed on the semiconductor chip2220in order to redistribute the contact pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimageable dielectric (PID) resin, forming via holes2243opening on to the contact pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, and an opening2251may be formed to have an underbump metal layer2260, or the like, extending therethrough. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes. As described above, the fan-in semiconductor package may have a package form in which all of the contact pads, for example, input/output (I/O) terminals, of the semiconductor chip, are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size. However, since all I/O terminals generally need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has a large spatial limitation. Therefore, it may be difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantages described above, the fan-in semiconductor package may not be directly mounted and used on the main board of the electronic device. The reason is that even in the case that a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the main board of the electronic device. FIG.5is a schematic cross-sectional view illustrating a fan-in semiconductor package mounted on an interposer substrate that is ultimately mounted on a main board of an electronic device, andFIG.6is a schematic cross-sectional view illustrating a fan-in semiconductor package embedded in an interposer substrate that is ultimately mounted on a main board of an electronic device. Referring toFIGS.5and6, in a fan-in semiconductor package2200, contact pads2222(i.e., I/O terminals) of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a main board2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an external surface of the semiconductor chip2220may be covered with an encapsulant2290, or the like. Alternatively, as shown inFIG.6, the fan-in semiconductor package2200may be embedded in an interposer substrate2302. The contact pads2222(i.e., I/O terminals) of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a main board2500of an electronic device. As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the main board (e.g.,2500) of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate (e.g.,2301or2302) and be then mounted on the main board of the electronic device through a packaging process or may be mounted and used on the main board of the electronic device in a state in which the fan-in semiconductor package is embedded in the interposer substrate. Fan-Out Semiconductor Package FIG.7is a schematic cross-sectional view illustrating a fan-out semiconductor package. Referring toFIG.7, in a fan-out semiconductor package2100, for example, an external surface of a semiconductor chip2120may be protected by an encapsulant2130, and contact pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may be further formed on the connection member2140, and an underbump metal layer2160may be further formed in openings of the passivation layer2150. Solder balls2170may be further formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the contact pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the contact pads2122and the redistribution layers2142to each other. In the present manufacturing process, the connection member2140may be formed after the encapsulant2130is formed outside the semiconductor chip2120. In this case, a process for forming the connection member2140is performed to form the via(s) connecting the redistribution layers and the contact pads2122of the semiconductor chip2120to each other and the redistribution layers2142, and the vias2143may thus have a width reduced toward the semiconductor chip2120(see an enlarged region). As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip2120through the connection member2140formed on the semiconductor chip2120. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip generally need to be disposed inside the semiconductor chip (e.g., within the footprint of the semiconductor chip on the package). Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls generally need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip2120are redistributed and disposed outwardly of the semiconductor chip2120(e.g., outwardly from the footprint of the semiconductor chip) through the connection member2140formed on the semiconductor chip as described above. Therefore, even in the case that a size of the semiconductor chip2120is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the main board of the electronic device without using a separate interposer substrate, as described below. FIG.8is a schematic cross-sectional view illustrating a fan-out semiconductor package mounted on a main board of an electronic device. Referring toFIG.8, a fan-out semiconductor package2100may be mounted on a main board2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the contact pads2122to a fan-out region that is outside of an area/footprint of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the main board2500of the electronic device without using a separate interposer substrate, or the like. As described above, since the fan-out semiconductor package may be mounted on the main board of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem caused by the occurrence of a warpage phenomenon. Meanwhile, the fan-out semiconductor package refers to a packaging technology for mounting the semiconductor chip on the main board of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts. The fan-out semiconductor package is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein. FIG.9is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment in the present disclosure, andFIG.10is a plan view of the semiconductor package, taken along line I-I′ inFIG.9. Referring toFIGS.9and10, a semiconductor package100according to an exemplary embodiment may include a support frame110having first and second surfaces110A and110B opposing each other and including a cavity110H connecting the first surfaces110A and the second surfaces110B, a semiconductor chip120disposed in the cavity110H and having an active surface on which contact pads122are arranged, a connection member140disposed on the second surface110B of the support frame110and the active surface of the semiconductor chip120, and an encapsulant131encapsulating the semiconductor chip120disposed in the cavity110H. The semiconductor chip120employed in the exemplary embodiment may include a RDL pattern125extending from the contact pad122, together with a first insulating film123and a second insulating film124, in a passivation structure. The RDL pattern125may be a conductive pattern relocating a connection region CA connected to an external circuit, for example, a redistribution layer145. The RDL pattern125and the first and second insulating films123and124may have been formed in a wafer level process for manufacturing the semiconductor chip120. FIG.11is an enlarged cross-sectional view illustrating portion A of the semiconductor package ofFIG.9. Referring toFIG.11together withFIG.9, the first insulating film123may be disposed on the active surface of the semiconductor chip120, and may be configured to expose the contact pad122. The first insulating film123may include at least one of an oxide or a nitride. In some embodiments, the first insulating film123may be a silicon oxide film or a silicon nitride film. In some other embodiments, the first insulating film123may include a first film formed of a silicon oxide film or a silicon nitride film, and a second film formed of an organic insulating material such as polyimide (PI). The RDL pattern125may be connected to the contact pad122and may extend onto the first insulating layer123. This RDL pattern125allows, the connection region CA to be connected to the redistribution layer145, to be relocated on another required position of the active surface of the semiconductor chip120. For example, the RDL pattern125may be formed of copper (Cu). The second insulating film124may be disposed on the active surface and may have a first opening O1as viewed from direction B as shown inFIG.11, i.e. as viewed from a passivation layer150) defining the connection region CA of the RDL pattern125. The first opening O1may be a boundary line between the second insulating film124and another layer connected to the second insulating film124and created by exposing the connection region CA wherein another layer is the layer deposited on one of the surface of the second insulating film124and facing to the passivation layer150. The second insulating film124may include an organic insulating material such as polyimide (PI). The semiconductor package100according to this embodiment may further include a conductive crack preventing layer135disposed on the connection region CA and extending to a portion of the second insulating film124around the first opening O1. In this specification, a portion of the conductive crack preventing layer135extending to the portion of the second insulating film124around the first opening O1may be referred to as an “outer peripheral region135R”. The connection member140may be disposed on the second surface110B of the support frame110and on the active surface of the semiconductor chip120, and may further include an insulating layer141having a second opening O2, as viewed from direction B as shown inFIG.11, i.e. as viewed from a passivation layer150), exposing the connection region CA, and the redistribution layer145may be connected to the connection region CA through the second opening O2. The second opening O2may be a boundary line between the insulating layer141and another layer connected to the insulating layer141and created by exposing the connection region CA wherein another layer is the layer deposited on one of the surface of the insulating film141and facing to the passivation layer150. The redistribution layer145may include the RDL pattern142disposed on the insulating layer141, and a RDL via143penetrating through the insulating layer141to be connected to the connection region CA and the like. The insulating layer141may be formed of various insulating materials. For example, the insulating layer141may include a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as polyimide. In a specific example, the insulating layer141may include a prepreg resin, Ajinomoto Build-up Film (ABF), FR-4 resin, bismaleimide-triazine (BT) resin, or a photoimageable dielectric (PID) resin such as polybenzoxazole. The insulating layer141may be formed of an insulating material different from that of the second insulating film124. For example, the second insulating film124may include a non-photoimageable dielectric material, and the insulating layer141may include a photoimageable dielectric material. In another example, the second insulating film124may include a photoimageable dielectric material, and the insulating layer141may include non-photoimageable dielectric material. The outer peripheral region135R of the conductive crack preventing layer135may be located between the insulating layer141and the second insulating film124. The arrangement of the conductive crack preventing layer135may prevent crack propagation to improve reliability of the semiconductor package100. In detail, referring toFIG.11, at a point indicated by “TP”, a metal such as Cu, for example, the redistribution layer145, may be in contact with an insulating material, for example, the second insulating film124and the insulating layer141. At the contact point of these dissimilar materials, stress due to a difference in thermal expansion coefficient may be concentrated, and thus, cracks C may occur. However, such a crack C may be prevented from propagating in a direction toward the semiconductor chip120and from damaging the RDL pattern125or the semiconductor chip120, by the conductive crack preventing layer135. The conductive crack preventing layer135may be formed of a conductive material such as a metal having excellent adhesion. For example, the conductive crack preventing layer135may include at least one of titanium (Ti) or tungsten (W). In this embodiment, as illustrated inFIG.11, in the case in which the redistribution layer145includes a seed layer145S and a plating layer145P disposed on the seed layer145S, the conductive crack preventing layer135may be formed of the same material as that of the seed layer145S. For example, the conductive crack preventing layer135and the seed layer145S may be a Ti/W layer or a Ti/Cu layer. A thickness “t” of the conductive crack preventing layer135may be 50 nm or more, in detail, 100 nm or more to obtain sufficient stress and crack propagation preventing effect, and the conductive crack preventing layer135may be formed to have a thickness of 1 μm or less, similarly to a thickness of the seed layer145S, but the thickness thereof is not limited thereto. In one embodiment, the thickness of the conductive crack preventing layer135may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, or 900 nm. FIG.12is a plan view of a portion of the semiconductor package ofFIG.11when viewed in direction B. Referring to the plan view ofFIG.12, the second opening O2of the insulating layer141has an area larger than an area of the first opening O1, and may be disposed around the first opening O1, in such a manner that an outer peripheral region of the conductive crack preventing layer135, a hatched portion inFIG.12, may be exposed. This arrangement is to precisely align the second opening O2of the insulating layer such that the connection region CA of the first opening O1is sufficiently exposed. As a result, the above-described contact point TP may inevitably occur, and disadvantageous propagation of stress or cracks occurring at the contact point TP may be prevented by the conductive crack preventing layer135. As illustrated inFIG.12, a center C1of the first opening O1and a center C2of the second opening O2may not exactly coincide with each other. In consideration of this alignment error, the outer peripheral region may be designed to have a sufficient width “d.” The width d is a distance between an edge of the conductive crack preventing layer135and O1measured along a line passing through C1and C2. For example, a width “d” of the outer peripheral region may be at least 5 μm. In one embodiment, the width of the outer peripheral region is 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm. The outer peripheral region of the conductive crack preventing layer135may be formed to be prevented from extending to another connection region of the RDL pattern125. For example, the conductive crack preventive layer135may be formed by performing deposition on an entire surface and then by performing a selective etching process using photolithography such that a required region, for example, a connection region and a periphery thereof, may only remain. As shown inFIG.9, the semiconductor package100according to this embodiment may include a passivation layer150disposed on a lower surface of the connection member140. The passivation layer150may have a plurality of openings exposing a portion of the redistribution layer145. An underbump metallurgy (UBM) layer160may be disposed in the opening of the passivation layer150, and may be connected to the redistribution layer145. An electrical connection structure170may be formed on the UBM layer160, to be connected to an external circuit such as a mother board or the like. Hereinafter, main components of the semiconductor package100according to the exemplary embodiment will be described in more detail. The semiconductor chip120may be formed, based on an active wafer. A body of the semiconductor chip120may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The contact pad122is used to electrically connect the semiconductor chip120to other components, and a metal such as aluminum (Al) may be used as a material of the contact pad122. As described above, the RDL pattern125redistributing the contact pad122and a passivation structure having the first and second insulating films123and124may be formed on the body. The semiconductor chip120may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. For example, the semiconductor chip120may be a processor, such as a central processor, for example, a CPU, a graphics processor, for example, a GPU, a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, and the like, in detail, may be an application processor (AP), but is not limited thereto. For example, the semiconductor chip120may be a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), and the like, or may be a memory chip such as a volatile memory, for example, a DRAM, a nonvolatile memory, for example, a ROM, a flash memory, and the like. Further, these devices may also be disposed to be combined with each other. The support frame110may maintain rigidity of the package according to a detailed material, and may serve to ensure uniformity of thickness of the encapsulant131. The package may be used in a package-on-package (POP) structure by the support frame110. The support frame110includes a plurality of wiring patterns112a,112band112c, may redistribute the contact pads122of the semiconductor chip120in various ways, and may simplify a redistribution layer of another region, for example, the connection member140. In the cavity110H, the semiconductor chip120is disposed to be spaced apart from the support frame110by a predetermined distance. A side surface of the semiconductor chip120may be surrounded by the support frame110. A separate passive component such as a capacitor or an inductor may be further disposed in the cavity110H as required, and may be electrically connected to the semiconductor chip120by the redistribution layer145or the like. The support frame110employed in this embodiment may include a first insulating layer111a, a first wiring pattern112aconnected to the redistribution layer145of the connection member140and embedded in the first insulating layer111a, a second wiring pattern112bdisposed on a side of the first insulating layer111a, opposite to a side thereof, in which the first wiring pattern112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second wiring pattern112b, and a third wiring pattern112cdisposed on the second insulating layer111b. The first to third wiring patterns112a,112band112cmay be electrically connected to the contact pad122. The first and second wiring patterns112aand112band the second and third wiring patterns112band112cmay be electrically connected to each other through first and second vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively. As described above, by implementing the multilayer wiring patterns112a,112band112cin the support frame110, the redistribution layer145of the connection member140may be further simplified. Thus, not only a yield reduction due to defects occurring in a complex redistribution layer formation process of the connection member140may be reduced, but also a thickness of the package may be reduced. As illustrated inFIG.9, the first wiring pattern112amay be recessed into the first insulating layer111a, such that a lower surface of the first insulating layer111aand a lower surface of the first wiring pattern112amay have a step. For example, in this embodiment, by the step, a material of the encapsulant131may be prevented from bleeding and contaminating the first wiring pattern112ain a process of forming the encapsulant131. The support frame110may be formed to have a thickness substantially corresponding to a thickness of the semiconductor chip120, and the second wiring pattern112bof the support frame110may be located between an active surface and an inactive surface of the semiconductor chip120. The support frame110may be formed by a general substrate process since a thickness of the support frame110may correspond to a thickness of the semiconductor chip120without any limitations, while the redistribution layer145of the connection member140may be formed by a fine pattern forming technique using photolithography to be further thinned. Thus, the thickness of the first to third wiring patterns112a,112band112cof the support frame110may be greater than the thickness of the redistribution layer145of the connection member140. As a material of the first and second insulating layers111aand111bof the support frame110, for example, an insulating resin mixed with an inorganic filler may be used. For example, a resin containing a reinforcing material such as an inorganic filler of silica, alumina or the like may be used together with a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. In detail, the insulating layers111aand111bof the support frame110may be formed using Ajinomoto Build-up Film (ABM), FR-4 resin, Bismaleimide Triazine (BT) resin, a photoimageable dielectric (PID) resin, BT resin, or the like, and may be formed using a material such as a prepreg resin or the like, in which a thermosetting resin or a thermoplastic resin is impregnated with a core material such as glass fiber (glass cloth, glass fabric), together with an inorganic filler, as required. The first to third wiring patterns112a,112band112cof the support frame110may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. The first to third wiring patterns112a,112band112cmay perform various functions according to a design of a relevant layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, and a signal (S) pattern may be used. In this case, the signal S pattern includes various signals, except for a ground (GND) pattern, a power (PWR) pattern and the like, for example, a data signal or the like. Further, a via pad pattern, a connection terminal pad pattern, and the like may be used. As a material of the first and second vias113aand113bof the support frame110, a conductive material may be used. The first and second vias113aand113bmay be entirely filled with a conductive material, or may be formed as a conductive material is formed along a wall surface of a via hole. A portion of pad patterns of the first and second wiring patterns112aand112bmay serve as a stopper when forming holes for the first and second vias113aand113b, and the first and second vias113aand113bmay have a tapered shape in which a width of an upper surface thereof is greater than that of a lower surface. In this case, the first and second vias113aand113bmay be integrated with a portion of the second and third wiring patterns112band112c. Although not illustrated in the drawings, a metal layer may be further disposed on a side wall of the cavity110H, as required. The metal layer may serve to effectively dissipate heat generated from the semiconductor chip120and/or to shield electromagnetic waves. The cavity110H may be a plurality of cavities110H, and the semiconductor chip120or a passive component may be disposed in each of the plurality of cavities110H. Additionally, structures known in the art may also be applied. The encapsulant131may protect the semiconductor chip120. An encapsulating method is not particularly limited, and any method may be used as long as at least a portion of the semiconductor chip120can be covered. For example, the encapsulant131may cover at least a portion of the inactive surface of the semiconductor chip120and the first surface110A of the support frame110, and may fill at least a portion of a space between a side surface of the cavity110H and a side surface of the semiconductor chip120. A detailed material of the encapsulant131is not particularly limited, and for example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with a reinforcing material such as an inorganic filler, such as ABF, FR-4 resin, BT resin, a PID resin or the like, may be used. As the encapsulant131, a known molding material such as EMC may be used. As required, a resin in which a thermosetting resin or a thermoplastic resin is impregnated with a core material of a glass fiber or the like together with an inorganic filler, may be used. The connection member140may redistribute the contact pads122of the semiconductor chip120. Tens to hundreds of contact pads122having various functions may be redistributed through the connection member140, and may be physically and/or electrically connected externally through the electrical connecting structure170according to functions thereof. The connection member140includes the redistribution layer145connected to the connection region CA of the semiconductor chip120and extending to a lower surface of the support frame110. The redistribution layer145of the connection member140may be connected to the connection region CA of the semiconductor chip120and the first wiring pattern112adisposed in a recessed portion of the support frame110, to electrically connect the semiconductor chip120and the wiring structure of the support frame110. The redistribution layer145may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Similar to the first to third wiring patterns112a,112band112c, the redistribution layer145may perform various functions according to a design of a relevant layer. For example, the redistribution layer145may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The passivation layer150may be configured to protect the connection member140from external physical chemical damage or the like. The passivation layer150may have tens to thousands of openings exposing at least portions of the redistribution layers145of the connection member140. A material of the passivation layer150is not particularly limited, and for example, a photoimageable dielectric material such as a photoimageable dielectric resin, or a solder resist, may be used. Alternatively, the passivation layer150may be formed using an insulating resin mixed with an inorganic filler, for example, ABF or the like. In this case, the insulating layer141of the connection member140may also include an insulating resin mixed with an inorganic filler. The electrical connection structure170may be used as a connection terminal to physically and/or electrically connecting the semiconductor package100externally. The electrical connection structure170may be formed using a conductive material, for example, a low melting point alloy such as Sn—Al—Cu. The electrical connection structure170may be a land, a ball, a pin, or the like. The electrical connection structure170may be formed of multiple layers or a single layer. The number, spacing, arrangement type, and the like of the electrical connection structure170are not particularly limited, and may be sufficiently modified according to the design specifications of an engineer in the art. For example, the number of the electrical connection structures170may be provided in an amount of several tens to several thousands, depending on the number of the contact pads122of the semiconductor chip120, and may be more or less. At least one of the electrical connection structures170is disposed in a fan-out region. The fan-out region indicates a region outside the area in which the semiconductor chip120is disposed. Such a fan-out package may be more reliable than a fan-in package, may implement a plurality of I/O terminals, and may facilitate3D interconnection. Unlike a ball grid array (BGA) package and a land grid array (LGA) package, the fan-out package may be mounted on electronic devices without a separate substrate, and thus, has positive attributes in terms of slimming as well as price competitiveness. Hereinafter, with reference toFIGS.13A to13F, a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure will be described. Various features and advantages of a semiconductor package according to an exemplary embodiment may be understood in detail in describing the method of manufacturing a semiconductor package. Referring toFIG.13A, a support frame110having first and second surfaces110A and110B opposing each other and having a cavity110H penetrating through the first and second surfaces110A and110B may be prepared. In detail, the support frame110is prepared by preparing a carrier film (not illustrated) on which a metal film is formed, forming a first wiring pattern112ausing a metal film as a seed layer, forming a first insulating layer111aon the metal film to cover the first wiring pattern112a, forming a second wiring pattern112bon the first insulating layer111a, forming a second insulating layer111bon the first insulating layer111ato cover the second wiring pattern112b, and forming a third wiring pattern112con the second insulating layer111b. Next, after the support frame110is separated from the carrier film, the metal film remaining on the first wiring pattern112amay be removed to obtain the support frame110illustrated inFIG.13A. A recessed portion may be formed in the support frame110when the metal film is removed. The first to third wiring patterns112a,112band112cmay be formed by performing patterning using a dry film or the like and then filling a pattern in a plating process known in the art. The first and second insulating layers111aand111bmay be formed by a known lamination method or a coating and curing method. The formation of the cavity110H may be performed using a laser drilling and/or mechanical drilling and/or sandblast method or the like. Subsequently, referring toFIG.13B, the second surface110B of the support frame110may be attached to an adhesive film200, and a semiconductor chip120may be disposed in the cavity110H of the support frame110. As the adhesive film200, any material may be used as long as it can fix the support frame110, and a known tape or the like may be used in an example without limitations. Examples of a known tape include a thermosetting adhesive tape, an ultraviolet ray-curable adhesive tape, and the like. The semiconductor chip120may be attached onto the adhesive film200in the cavity110H. The semiconductor chip120may be disposed in a face-down manner such that an active surface on which the contact pad122is disposed is attached to the adhesive film200. The semiconductor chip120includes a RDL pattern125connected to the contact pad122, and first and second insulating films123and124disposed on the active surface. The semiconductor chip120may have a connection region exposed through an opening of the second insulating film124. Next, referring toFIG.13C, the semiconductor chip120is encapsulated using the encapsulant131. The encapsulant131may be disposed to encapsulate the semiconductor chip120disposed in the cavity110H. In the exemplary embodiment, the encapsulant131may cover the first surface110A of the support frame110and the inactive surface of the semiconductor chip120, and may fill at least a portion of a space in the cavity110H. The encapsulant131may be formed by a method known in the art. For example, the encapsulant131may be formed by laminating and then curing a precursor. Alternatively, a liquid resin for the encapsulant131may be coated on the adhesive film200, to encapsulate the semiconductor chip120, followed by curing. Referring toFIG.13D, the adhesive film200may be removed, and a conductive crack preventing layer135may be formed on the second insulating film124of the semiconductor chip120. The adhesive film200may be peeled, after a heat treatment is applied or ultraviolet irradiation is applied depending on the kind thereof to reduce adhesive force. The conductive crack preventing layer135extending to a portion of the second insulating film124around the first opening O1may be formed on the connection region CA. The conductive crack preventing layer135may be formed by depositing a required metal on an entire surface and then by selectively etching a remaining region except a connection region and a portion of the second insulating film on a periphery thereof, using photolithography. For a sufficient stress and crack propagation preventing effect, a thickness of the conductive crack preventing layer135may be in the range from 50 nm to 1 μm. In one embodiment, the thickness of the conductive crack preventing layer135is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, or 900 nm. The conductive crack preventing layer135may be formed of a conductive material such as a metal, having excellent adhesion. For example, the conductive crack preventing layer135may include at least one of titanium (Ti) or tungsten (W). In a specific example, the conductive crack preventing layer135may be formed of the same material as that of a seed layer of the redistribution layer145to be formed in a subsequent process. For example, the conductive crack preventing layer135may be a Ti/W layer or a Ti/Cu layer. Next, referring toFIG.13E, a connection member140may be formed on the second surface110B of the support frame110from which the adhesive film200has been removed and on an active surface of the semiconductor chip120. An insulating layer may be formed on the second surface110B of the support frame110and the active surface of the semiconductor chip120, and a second opening O2may be formed to expose the connection region CA. The second opening O2may be formed to have an area larger than an area of a first opening O1such that the connection region CA is exposed, in consideration of an alignment error. The conductive crack preventing layer135may be exposed by the second opening. The insulating layer141may be formed of various insulating materials. For example, the insulating layer141may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide. In a specific example, the insulating layer141may include a prepreg resin, Ajinomoto Build-up Film (ABF), FR-4 resin, BT resin, or a photoimageable dielectric (PID) resin. The insulating layer141may be formed of a different insulating material from a material of the second insulating film124. For example, the second insulating film124may include a nonphotoimageable dielectric material, and the insulating layer141may include a photoimageable dielectric material. The redistribution layer145may be formed to be electrically connected to the connection region CA through the conductive crack preventing layer135exposed through the second opening O2. The redistribution layer145may be formed in a recessed portion of the support frame110to be connected to the first wiring pattern112aof the support frame110. The redistribution layer145as described above may be formed by forming a seed layer and then forming a plating layer such as a Cu layer on the seed layer. In a structural aspect, the redistribution layer145may include a RDL pattern142disposed on the insulating layer141, and a RDL via143penetrating through the insulating layer141to be connected to the connection region CA and the like, distinguished from each other. Referring toFIG.13F, a passivation layer150may be formed on the connection member140, and a UBM layer160connected to the redistribution layer145and an electrical connection structure170are formed. The passivation layer150may be formed by laminating a precursor and then curing the precursor, or by applying a liquid resin and then curing the liquid resin. The passivation layer150may be formed with an opening exposing a portion of the redistribution layer145of the connection member140. The UBM layer160may be formed on the exposed region of the redistribution layer145by a metallization method known in the art, and the electrical connection structure170may be formed on the UBM layer160. The above-described processes are performed in a large-scale panel unit, and the package may be singulated into individual semiconductor packages using a sawing process after the above-described process is completed. The exemplary embodiments of the present disclosure may be modified and implemented in various forms.FIGS.14and15are schematic cross-sectional views of a semiconductor package according to various embodiments. Referring toFIG.14, a semiconductor package100A according to an exemplary embodiment may have a structure similar to the structure shown inFIGS.9and10, except for a wiring structure of a support frame110′ and a redistribution layer structure of a connection member140′. The description of components of this exemplary embodiment may be referred to the description of the same or similar components of the semiconductor package100illustrated inFIGS.9and10, unless in detail explained otherwise. The wiring structure of the support frame110′ employed in the exemplary embodiment may include first and second wiring patterns112aand112bdisposed on two surfaces of a first insulating layer111a, respectively, a third wiring pattern112cdisposed on a second insulating layer111b, a fourth wiring pattern112ddisposed on a third insulating layer111c, a first via113apenetrating through the first insulating layer111ato connect the first and second wiring patterns112aand112b, a second via113bpenetrating through the second insulating layer111bto connect the first and third wiring patterns112aand112c, and a third via113cpenetrating through the third insulating layer111cto connect the second and fourth wiring patterns112band112d. The connection member140′ employed in the exemplary embodiment has two levels of redistribution structures, for example, includes first and second redistribution layers145aand145b, disposed on the first and second insulating films141aand141b, respectively. The first redistribution layer145aincludes a first RDL pattern142adisposed on the first insulating film141a, and a first via143apenetrating through the first insulating film141ato be connected to the first RDL pattern142aand a connection region. The second redistribution layer145bincludes a second RDL pattern142bdisposed on the second insulating film141b, and a second via143bpenetrating through the second insulating film141bto connect the first and second RDL patterns142aand142b. As described above, although the connection member140′ is illustrated as having a two-level redistribution structure having the first redistribution layer142aand the second redistribution layer142bby way of example, an exemplary embodiment thereof is not limited thereto. For example, the connection member140′ may be implemented by a structure having three or more redistribution layers. Referring toFIG.15, a semiconductor package100B according to an exemplary embodiment may have a structure similar to the structure shown inFIGS.9and10, except that a RDL pattern is not introduced into a passivation structure of a semiconductor chip120′. The description of components of this exemplary embodiment may be referred to the description of the same or similar components of the semiconductor package100shown inFIGS.9and10, unless in detail explained otherwise. The semiconductor chip120′ employed in this embodiment may include a first insulating film123disposed on the active surface and exposing a contact pad122, and a second insulating film124disposed on the first insulating film123and having a first opening O1exposing a connection region CA of the contact pad122. A conductive crack preventing layer135may be disposed on the connection region CA and extend to a portion of the second insulating film124around the first opening O1. The connection member140may be disposed on a second surface110B of a support frame110and on an active surface of the semiconductor chip120′. An insulating layer141of the connection member140may have a second opening O2exposing the connection region CA and having an opening size greater than that of the first opening O1. A redistribution layer145may be connected to the connection region CA through the second opening O2. The second opening O2may have an area larger than an area of the first opening O1when viewed from above, and the conductive crack preventing layer135may extend between the insulating layer141and the second insulating film124. The conductive crack preventing layer135may prevent stress or cracks from propagating in a direction toward the semiconductor chip120′, even in a case in which high stress or cracks occur at a contact point (the insulating layer141and the redistribution layer145and the second insulating film124) between dissimilar materials located along a rim of the second opening O2, thereby significantly increasing reliability of the package. As set forth above, according to an exemplary embodiment, by introducing the conductive crack preventing layer into the passivation structure of the semiconductor chip, the occurrence of stress and cracks due to a difference in thermal expansion coefficients with the redistribution layer formed on a pad region of the semiconductor chip may be effectively prevented. The meaning of being connected in the present disclosure encompasses not only a direct connection, but also includes an indirect connection through an adhesive layer or the like. In addition, the term “electrically connected” is a concept including both a physical connection and non-connection. Further, the expressions of the first, second, and the like are used to distinguish one component from another, and do not limit the order and/or importance of the components. In some cases, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The expression, an example, used in this disclosure does not mean the same embodiment, but is provided for emphasizing and explaining different unique features. However, the above-mentioned examples do not exclude being implemented in combination with the features of other examples. For example, although the description in the specific example is not described in another example, it may be understood as an explanation related to another example, unless otherwise described or contradicted by the other example. The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The singular forms include plural expressions unless the context clearly is otherwise indicated. While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims. | 55,185 |
11862582 | DETAILED DESCRIPTION There may be a need for a package with high reliability and high performance. According to an exemplary embodiment, a package is provided which comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side (or a bottom main face) at a first vertical level, at least one lead electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at said bottom side of the encapsulant, and a functional structure at said bottom side extending up to a second vertical level being different from (for instance being displaced downwardly or upwardly with respect to) said first vertical level. According to another exemplary embodiment, an electronic device is provided which comprises a package having the above mentioned features, and a mounting base on which the package is mounted and being electrically coupled with the at least one lead. According to yet another exemplary embodiment, a method of manufacturing a package is provided, wherein the method comprises mounting an electronic component on a carrier, electrically coupling at least one lead with the electronic component, encapsulating at least part of the electronic component and at least part of the carrier by an encapsulant which has a bottom side at a first vertical level, encapsulating only a first lead portion of the at least one lead in the encapsulant so that a second lead portion of the at least one lead extends out of (and in particular vertically beyond) the encapsulant at said bottom side of the encapsulant, and forming a functional structure at said bottom side extending up to a second vertical level which is different from said first vertical level. According to an exemplary embodiment, a package with an encapsulated electronic component mounted on a carrier is provided, wherein one or more leads electrically connecting said encapsulated electronic component may be configured as elevated lead(s) extending downwardly beyond a bottom main surface of the encapsulant. Such a lead configuration may ensure a highly reliable electric connection of the package with a mounting base (such as a printed circuit board) below, because the elevated one or more leads are highly appropriate for establishing a reliable electric connection with a connection medium (such as a solder connection medium) over a large connection area. For instance, a downwardly elevated lead may be covered with connection medium along its entire circumference and also at its bottom surface. As a result, a highly reliable electric and mechanical connection between package and mounting base can be ensured, which may yield a high performance of the package. Furthermore, an elevated lead design may keep electric paths short, and may thereby reduce signal losses and energy consumption of the package. Advantageously, an additional functional structure (which may comprise one or more functional sub-structures such as one or more extensions and/or one or more recesses) may be formed at a bottom side of the encapsulant to functionally cooperate with the elevated lead(s). Said functional structure may extend up to a vertical level which differs from another vertical level up to which the bottom main surface of the encapsulant extends. By such a functional structure, the properties of the package may be fine-tuned, in particular in terms of creepage distance adjustment and/or adjustment of connection medium wetting properties at the bottom side of the encapsulant. Thanks to such a functional structure, undesired creepage currents (for instance between different elevated leads and/or between an elevated lead and the carrier) may be strongly suppressed. It may also be possible to inhibit an unintentional solder flow into undesired regions of the package surface. In the following, further exemplary embodiments of the package, the electronic device, and the method will be explained. In the context of the present application, the term “package” may particularly denote an electronic member which may comprise one or more electronic components mounted on a carrier. Said constituents of the package may be optionally encapsulated at least partially by an encapsulant. For example, many packages may be manufactured simultaneously as a batch before being separated into individual packages. In the context of the present application, the term “carrier” may particularly denote a support structure which serves as a mechanical support for the one or more electronic components to be mounted thereon. In other words, the carrier may fulfil a mechanical support function. Additionally or alternatively, a carrier may also fulfill an electrical connection function. A carrier may comprise or consist of a single part, multiple parts joined via encapsulation or other package components, or a subassembly of carriers. For instance, the carrier may be a die paddle. In the context of the present application, the term “electronic component” may in particular encompass a semiconductor chip (in particular a power semiconductor chip), an active electronic device (such as a transistor), a passive electronic device (such as a capacitance or an inductance or an ohmic resistance), a sensor (such as a microphone, a light sensor or a gas sensor), an actuator (for instance a loudspeaker), and a microelectromechanical system (MEMS). In particular, the electronic component may be a semiconductor chip having at least one integrated circuit element (such as a diode or a transistor) in a surface portion thereof. The electronic component may be a naked die or may be already packaged or encapsulated. Semiconductor chips implemented according to exemplary embodiments may be formed for example in silicon technology, gallium nitride technology, silicon carbide technology, etc. In the context of the present application, the term “lead” may in particular denote an electrically conductive (for instance strip shaped) element (which may be straight or bent) which may serve for contacting the electronic component with respect to an exterior of the package. For instance, a lead may be partially encapsulated and partially exposed with respect to an encapsulant. In the context of the present application, the term “encapsulant” may particularly denote a substantially electrically insulating and preferably thermally conductive material surrounding at least part of an electronic component and at least part of a carrier, as well as a part of the lead(s). For instance, the encapsulant may be a mold compound and may be created for example by transfer molding. In the context of the present application, the term “bottom side” of the encapsulant may particularly denote a lower side of the encapsulant corresponding to a main surface of the encapsulant at which the package is mounted on a mounting base beneath. Hence, the bottom side is the side of the encapsulant through which the one or more leads extend for downwardly protruding beyond the encapsulant. Thus, the bottom side of the encapsulant corresponds to the electric connection side of the package. In the context of the present application, the term “vertical level” may particularly denote a height level along a mounting direction of the constituents of the package and their arrangement during use of the package or the electronic device. In particular, the electronic component may be mounted on top of the carrier, and leads and/or the carrier of the package may be mounted on the mounting base. On the basis of or relative to this mounting or stacking direction, the various vertical levels may be defined. More specifically, the bottom side corresponding to the lower main surface of the encapsulant defines the first vertical level, whereas a bottom surface of the at least one bottom-sided exposed lead extends vertically below the first vertical level. Each functional sub-structure of the functional structure may extend up to a second vertical level which may be higher or lower than the first vertical level. In the context of the present application, the term “functional structure” may particularly denote at least one structural feature at a bottom side of the encapsulant which may have an impact on the function of the package as a whole, and in particular an impact on the at least one elevated lead. For instance, the functional structure may be an electrically non-conductive structure, such as a dielectric protrusion or a recess. The functional structure may comprise one or more functional sub-structures such as one or more extensions and/or one or more recesses. In particular, said functional structure may have an electric function, a mechanical function and/or a thermal function. An example of an electric function of the functional structure is a prolongation of a creepage distance of a parasitic creepage current along a bottom surface of the encapsulant. An example of a combined mechanical and electrical function of the functional structure is the provision of a non-wettable surface portion along a bottom surface of the encapsulant on which a connection medium such as a solder material does not adhere. An example of a thermal function is the provision of a highly thermally conductive functional structure at a bottom side of the encapsulant which contributes to heat removal out of the package. One or more sub-structures of the functional structure with the same and/or different functions may be provided at the bottom side of the encapsulant. In the context of the present application, the term “mounting base” may in particular denote a support body on which the package may be assembled, for instance together with one or more further packages. In particular, such a support body may be mechanically and electrically coupled with the package(s). In particular, the mounting base may be a plate-shaped electronic mounting base, such as a printed circuit board (PCB). An electric connection between mounting base and package may be established by a connection medium, such as a solder or sinter material. In an embodiment, the package comprises a plurality of leads each electrically coupled with the electronic component and each comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at a bottom side of the encapsulant. The encapsulated lead portions may conduct electric signals between an inside and an outside of the encapsulant, whereas the exposed portions may be configured for forming an electric and mechanically connection with a mounting base below the package. By the extension of the lead(s) out of the encapsulant at the bottom side rather than laterally, the connection length between the package and the mounting base may be reduced, which reduces signal losses and energy consumption. Furthermore, the downside elevation of the lead(s) may provide a large connection area between lead(s) and solder or sinter material. In an embodiment, the functional structure comprises at least one extension extending downwardly from said bottom side or bottom main surface of the encapsulant. In other words, the second vertical level may be lower than the first vertical level. The extension may be a physical body protruding vertically beyond the bottom main surface of the encapsulant. In such a configuration, the functional structure may act for enlarging the isolation distance to inhibit creepage current flowing unintentionally along an exterior surface of the encapsulant. Hence, the functional structure may enlarge the isolation distance, meaning it may enlarge the distance from one electrode (for instance a lead) to another electrode (for instance another lead or a carrier) along the mold compound surface. In an embodiment, the second lead portion of the at least one lead protrudes downwardly beyond the at least one extension. By configuring the at least one downwardly protruding functional structure to extend vertically not up to a lower end of the at least one downwardly elevated lead, any undesired interaction (for instance in terms of mounting the package on a mounting base) between the downwardly protruding lead(s) and the downwardly protruding functional structure may be avoided. In an embodiment, the at least one extension forms part of said encapsulant. In other words, the at least one extension-type functional structure may be integrally formed with the encapsulant. In particular, the at least one extension-type functional structure may be made of the same material as the encapsulant. For instance, the functional structure may be configured as a mold protrusion or mold body extension of a mold-type encapsulant. This embodiment has advantages: On the one hand, the extension-type functional structure may be manufactured simultaneously with the encapsulation process, thereby rendering a separate manufacturing process dispensable for forming the functional structure. Furthermore, the mechanical integrity of the package is particularly stable if the functional structure is formed as part of the encapsulant rather than providing it as a separate piece. Thirdly, the intrinsic material properties of mold compounds used for encapsulating one or more electronic components of the package are highly appropriate for extending a creepage distance while being simultaneously non-wettable by solder. In another embodiment, the at least one extension is made of another material and/or may be another body than said encapsulant, in particular may be made of a solder resist or other epoxy based material. An extension-type functional structure in form of a separate body made of another material than the encapsulant may be freely designed in accordance with its desired function. For instance, such an extension may be made of a highly thermally conductive material (for instance having a thermal conductivity of at least 5 W/mK or even at least 50 W/mK) for enhancing a cooling of the encapsulated electronic component. Also a solder resist is particularly well-suited as material of a separate extension body for reliably avoiding wetting by solder. In yet another embodiment, the functional structure comprises at least one recess extending upwardly into the encapsulant from said bottom side or bottom main surface of the encapsulant. In such an embodiment, the second vertical level is located above the first vertical level. Forming a blind hole in the encapsulant at its bottom side may also extend a length of a trajectory along which a creepage current must flow between different electrically conductive elements of the package, and may therefore improve the electric reliability of the package. Furthermore, such a recess may inhibit a flow of solder material into undesired regions of the package. In an embodiment, the package comprises a plurality of leads each electrically coupled with the electronic component and each comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at said bottom side of the encapsulant. In particular, all leads of the package may extend out of the bottom of the encapsulant. This may contribute to a compact design of the package and may ensure short electric paths, thus low loss operation and low energy consumption of the package. In an embodiment, at least one sub-structure of the functional structure is arranged laterally between different ones of the leads. Hence, the functional structure may spatially separate adjacent leads and may thereby promote the dielectric decoupling between said leads. This may contribute to an extension of a creepage length for thereby increasing the electric reliability of the package. Also an unintentional adhesion of solder at a bottom side of the encapsulant apart from the leads may be prevented by interposing a non-wettable functional structure between neighboured leads. Preferably, isolation by the functional structure is not only provided to the carrier (for instance die paddle), i.e. between carrier and lead(s), but also between the leads. In an embodiment, the carrier comprises a first carrier portion being encapsulated in the encapsulant and a second carrier portion extending out of the encapsulant at said bottom side of the encapsulant. When a part of the carrier facing the electronic component is arranged within the encapsulant, this may contribute to the electric reliability of the package. If however another part of the carrier extends out of the encapsulant, this has the following additional advantages: Firstly, the exposed carrier part may remove heat out of the package to thereby improve the thermal performance. Secondly, the exposed carrier part may be directly electrically connected with a mounting base, for instance by a solder connection. This keeps electric paths short and losses and energy consumption of the package small. In an embodiment, at least one sub-structure of the functional structure is arranged laterally between the carrier and the at least one lead. Advantageously, a functional structure between an exposed part of the carrier and an exposed part of a lead may suppress creepage currents and may avoid unintentional wetting of non-soldered surface areas of the package. In an embodiment, at least one sub-structure of the functional structure is configured for extending a creepage distance along an exterior surface of the encapsulant. An increased creepage distance may denote an increased length of a shortest path between two conductive materials (in particular between leads or between lead and carrier) measured along the surface of an isolator (in particular the encapsulant) that separates the conductors. Advantageously, the functional structure may prolong the creepage distance and may render a creepage trajectory more complex, thereby increasing the protection of the package against short-circuiting due to creepage current flow. Descriptively speaking, a creepage current flowing for instance between different leads at the bottom side of the encapsulant or flowing between such an elevated lead and an exposed portion of a metallic carrier may be extended by the functional structure, since that creepage current may then be forced to flow along an additional path along the functional structure. In an embodiment, the functional structure is made of a material being non-wettable by solder material. For instance, a solder resist is highly appropriate for this purpose. In particular, such a solder resist may be a thin lacquer-like layer of polymer that may be applied in form of an elevated functional structure to prevent formation of solder bridges between closely spaced solder pads, leads and/or exposed areas of a metallic carrier. In this context, a solder bridge may denote an unintentional electrical connection between two conductors by solder material. In an embodiment, the functional structure is a wall-shaped structure. For example, the functional structure may be of linear (for example straight) shape and may take the form of a ridge or barrier which must be overcome by a flow of solder, flux, sinter material, conductive or non-conductive glue or anisotropic adhesive into undesired surface regions at the bottom side of the encapsulant. In an embodiment, the functional structure is an annular structure. In particular, a circular or rectangular arrangement of a mold elevation in ring form, surrounding the leads, may be advantageous, for instance at least one mold ring. When the functional structure circumferentially surrounds an inner bottom area of the encapsulant due to its closed ring shape, said area can be reliably protected by the functional structure with regard to the intrusion of undesired materials, such as flowable solder or moisture. In an embodiment, the second lead portion extends out of the encapsulant exclusively at said bottom side. Thus, both the top side as well as the sidewalls of the encapsulant may be free of leads extending therethrough. All leads of the package may extend out of the bottom main surface of the encapsulant, and preferably all protruding beyond it. The entire electric connection of the package may then be accomplished at the bottom side, which further promotes the compact design of the package. The entire package apart from its bottom side may be continuously delimited by dielectric material of the encapsulant. In an embodiment, the second lead portion, in particular the entire at least one lead, extends substantially vertically (preferably straight, rather than being three-dimensionally bent and comprising horizontal and vertical sections). The completely vertical extension of the one or more leads keeps electric connection paths short, limits losses and keeps the energy consumption of the package small. In an embodiment, the second lead portion tapers from the bottom side of the encapsulant towards a bottom surface of the second lead portion. This may be the result of a manufacture of a bottom portion of the leads by an etching process, in particular an anisotropic etching process. In particular an inwardly curved or concave shape of the second lead portion may increase its connection area with solder or sinter material, thereby promoting a reliable and strong solder, glue or sinter connection. In an embodiment, the carrier is electrically coupled with the electronic component. Hence, apart from serving as a mechanical carrier, the carrier may also establish an electric connection with the electronic component. This may allow to directly electrically connect a portion of the carrier extending beyond the encapsulant with a pad of the mounting base. For instance, the carrier may be metallic. In an embodiment, a bottom surface of the at least one lead and a bottom surface of the carrier are coplanar, i.e. lie within the same plane. This promotes a proper mounting of the package on a flat mounting base, such as a printed circuit board (PCB). In an embodiment, a top surface of the at least one lead and a top surface of the carrier are coplanar, i.e. lie within the same plane. Such a configuration allows to manufacture the carrier and the leads out of a metal plate which may only need to be patterned to form carrier and leads. In another embodiment, a top surface of the at least one lead protrudes beyond a top surface of the carrier, in particular so that the top surface of the at least one lead is coplanar with a top surface of the electronic component, i.e. lie within the same plane. Preferably, the protrusion of a top surface of the one or more leads beyond a top side of the carrier may be identical or substantially identical to a thickness of the electronic component. With such a configuration, a planar electrically conductive connection element, in particular at least one clip, may be used for electrically coupling the top surface of the at least one lead with a top surface of the electronic component without the need of balancing out a height discrepancy. Such a clip may then be flat and may be connected to both a top side of the electronic component and a top side of the one or more leads. This results in a simple manufacturability and a compact design of the package. In an embodiment, the carrier and the at least one lead form part of a common patterned metal sheet. Correspondingly, the method may comprise forming the carrier and the at least one lead by patterning a planar metal sheet, in particular by etching. Advantageously, the carrier and the at least one lead may be formed by a first partial etching of a top side of the metal sheet (preferably carried out before component assembly and encapsulation) and a second partial etching of a bottom side of the metal sheet (preferably carried out after encapsulation). Such a continuous metal sheet may firstly be half-etched at a top side before assembly of the component and before encapsulation. Thereafter, the metal sheet may be half-etched at a bottom side to thereby separate the metal plate into the carrier and the lead(s). In an embodiment, the package comprises at least one electrically conductive connection element, in particular at least one bond wire or at least one clip, electrically coupling the electronic component with the at least one lead and being at least partially encapsulated by the encapsulant. As an alternative to a bond wire, it is also possible to use a bond ribbon. In an embodiment, the at least one lead is pillar-shaped. This simplifies a wetting of the elevated lead portion with a solder or sinter material along the entire lead perimeter to thereby achieve a high electric connection area. In an embodiment, the package is configured as leadless package. In a leaded package, all leads or terminals of the carrier may protrude laterally out of the encapsulant. In contrast to this, a leadless package does not have laterally extending leads, but connects the package at its bottom side to pads of a mounting base. In an embodiment, the electronic device comprises an electrically conductive connection medium, in particular solder material, by which the mounting base is electrically coupled with the at least one lead. The connection medium between the package and the mounting base may for instance be a solder structure (in particular for diffusion soldering), a sinter structure (for instance comprising silver sinter material), or an adhesive (in particular an electrically conductive glue). In an embodiment, the method comprises forming at least one top-side recess in an upper main surface of a metal sheet, thereafter mounting the electronic component on the metal sheet, thereafter encapsulating an upper portion of the metal sheet and at least part of the electronic component, and thereafter forming at least one bottom-side recess in a lower main surface of the metal sheet so that the at least one top-side recess and the at least one bottom-side recess are connected to form at least one through hole separating the metal sheet into the carrier and the at least one lead. Such a method is for instance illustrated inFIG.4toFIG.6and allows manufacturing the package in a simple way, by synergistically combining two half-etch processes to remove material of the metal plate at a top side and thereafter from a bottom side. In an embodiment, the method comprises forming the at least one top-side recess with a tapering or stepped profile, at least partially filling said profile with encapsulant during encapsulating to thereby form the functional structure that as at least one extension of the encapsulant, and exposing the at least one extension by forming said at least one bottom-side recess. With a stepped and (towards a bottom side) spatially narrowing configuration of the top-sided recess in the metal plate, an extension-type functional structure may be integrally formed with the encapsulant protruding beyond its bottom main surface. Correspondingly, the extension-type functional structure or appendix may also be a tapering structure, for instance with a conical shape or as a truncated cone. In an embodiment, the package comprises a plurality of electronic components mounted on the carrier or on different carriers. Thus, the package may comprise one or more electronic components (for instance at least one passive component, such as a capacitor, and at least one active component, such as a semiconductor chip). In an embodiment, the electronic device comprises a mounting base on which the package is mounted and being electrically coupled with the lead(s) and/or with the carrier. Such a mounting base may be an electronic board serving as mechanical base for the package and being electrically couple-able with the lead(s) of the package. In an embodiment, the carrier forms part of a metal plate or forms part of a leadframe. However, it is also possible that the carrier comprises a stack composed of a central electrically insulating and thermally conductive layer (such as a ceramic layer) covered on both opposing main surfaces by a respective electrically conductive layer (such as a copper layer or an aluminium layer, wherein the respective electrically conductive layer may be a continuous or a patterned layer). In particular, the carrier may be a Direct Copper Bonding (DCB) substrate or a Direct Aluminium Bonding (DAB) substrate. However, the carrier may also be configured as Active Metal Brazing (AMB) substrate, or as patterned metal plate (for example a leadframe). Preferably, the at least one electronic component is a power semiconductor chip. For instance, a corresponding power semiconductor application may be realized by the chip(s), wherein integrated circuit elements of such a power semiconductor chip may comprise at least one transistor (in particular a field effect transistor such as a MOSFET (metal oxide semiconductor field effect transistor) or a bipolar transistor such as an IGBT (insulated gate bipolar transistor)), at least one diode, etc. It is also possible that the at least one electronic component comprises a controller circuit, a driver circuit, etc. One or more of these and/or other circuits may be integrated into one semiconductor chip, or separately in different chips. In particular, packages fulfilling a half-bridge function, a full-bridge function, etc., may be manufactured. In another embodiment, the at least one electronic component may be a logic die. In an embodiment, the package is configured as power converter, in particular one of an AC/DC power converter and a DC/DC power converter. However, also other electronic applications, such as inverters, etc., may be possible. As substrate or wafer for the semiconductor chips, a semiconductor substrate, in particular a silicon substrate, may be used. Alternatively, a silicon oxide or another insulator substrate may be provided. It is also possible to implement a germanium substrate or a III-V-semiconductor material. For instance, exemplary embodiments may be implemented in GaN or SiC technology. Furthermore, exemplary embodiments may make use of standard semiconductor processing technologies such as appropriate etching technologies (including isotropic and anisotropic etching technologies, particularly plasma etching, dry etching, wet etching, laser removal), patterning technologies (which may involve lithographic masks), deposition technologies (such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.). The above and other objects, features and advantages will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings, in which like parts or elements are denoted by like reference numbers. The illustration in the drawing is schematically and not to scale. Before exemplary embodiments will be described in more detail referring to the figures, some general considerations will be summarized based on which exemplary embodiments have been developed. According to an exemplary embodiment, a chip package is equipped with elevated lead(s) extending downwardly at the bottom side out of an encapsulant, wherein the latter is provided with a functional structure at said bottom side. The at least one downwardly protruding elevated lead may ensure a short electric path between the package and a mounting base supporting the package at its bottom mechanically and also providing an electrical coupling thereof. Consequently, the package may be manufactured in a simple and compact way. The functional structure extending for instance vertically (upwardly and/or downwardly) from the bottom side of the encapsulant fulfills at least one additional task which may be correlated with the elevated lead design without adding any noteworthy complexity neither to the package design nor the manufacturing method. In particular, the at least one additional functional structure provided at the bottom side of the encapsulant and thus of the package may serve as a creepage distance extender. Additionally or alternatively, the functional structure may also have non-wetting properties in relation to solder material, thereby concentrating solder material to one or more wettable regions where a solder connection shall be established. Hence, the functional structure may reliably suppress undesired electrically conductive paths at the bottom side of the package. Preferably, an extension-type functional structure may be manufactured as an encapsulant appendix (for instance embodied as a mold barrier). Such a functional encapsulant appendix may be formed for example by partial etching processes applied to a metal plate. In particular, such an encapsulant appendix may be formed on the basis of a stepped mold profile. In another embodiment, a recess-type functional structure may be manufactured as an indentation extending into the encapsulant. According to exemplary embodiments, a metal (in particular copper) sheet may be used as a basis for a chip package. The metal sheet may be structured by etching, for instance by half etching from an upper side or from a lower side. For example, the etching may be done from the bottom side for ease of etch chemistry flow. Thereafter, a (in particular chip-type) electronic component may be mounted on the metal sheet. The obtained arrangement may be wire bonded for electrically coupling the electronic component with the metal plate, and may be encapsulated (in particular molded). The metal sheet may then be structured from the other side, in particular by a further half etching process. By the second half etching process, the metal sheet may be separated into a carrier (functioning as die paddle) and into one or a plurality of downwardly extending leads. This may be accomplished by connecting top-sided recesses (formed by the first half etching) with bottom-sided recesses (formed by the second half etching) to thereby create through holes. Thus, the patterned sheet may form elevated or vertically extending leads for the semiconductor package. Advantageously, the patterned metal sheet may be encapsulated by a mold-type encapsulant and may for instance have an extended mold body extension on the bottom side. Leadless packages are typically providing better electrical performance and smaller dimensions than leaded packages. A reason for this are shorter interconnects. On the other hand, the leads of a leadless package may be less reliable on board level. This causes many users to rely on leaded packages rather than on leadless packages, accepting the mentioned disadvantages. In order to overcome such and/or other shortcomings of conventional packages, an exemplary embodiment provides a package which may be configured as leadless package, and which allows to improve the board level reliability. Furthermore, reliability of a solder interconnect of a leadless package may be an issue. The fillet of the solder may wet the bottom side of the pad as well as the side wall of the package (for lead tip inspection (LTI)). The solder is therefore embedding the lead from bottom and one side only. Solder fatigue is thus a typical failure mode of board level testing. The low flexibility of the lead as well as the small interconnect area is providing a shortened board level reliability compared to other, for example leaded, packages. As a result, it may conventionally happen that only a small part of the pad is embedded in solder. An exemplary embodiment provides a process flow enabling to manufacture elevated leads for a leadless package. Such elevated leads may be formed as pillars which may be embedded completely in solder. In particular, the lead may be supported from all five exposed sides by solder, leading to better board level reliability than for conventional leads. A manufacturing method according to an exemplary embodiment may generate the elevated lead(s) for a large number of different leadless package outlines, like SON (Small-outline No-lead) Package, QFN (Quad Flat No Leads) Package, VQFN (Very Thin Quad Flat Non-Leaded) Package, etc. In conventional approaches, the removal of the sidewall wetting may have a negative impact on reliability. The sidewall wetting can be artificially suppressed, and the resulting thermal cycling on board (TCoB) performance may drop significantly. Increasing the number of embedded sidewalls may therefore allow to improve the board level performance. A gist of an exemplary embodiment is a process flow for a leadless package which results in elevated leads providing an improved board level reliability for leadless packages. As a result, compact leadless packages with improved electrical performance (due to shorter interconnect length) may be obtained which can replace leaded packages whenever the board level reliability is limiting the use of conventional leadless packages. FIG.1illustrates a cross-sectional view of a package100according to an exemplary embodiment. The illustrated package100comprises a carrier102. An electronic component104is mounted on the carrier102. Furthermore, an encapsulant106is provided which encapsulates the electronic component104and part of the carrier102. The encapsulant106has a bottom side114at a first vertical level182. A lead108is electrically coupled with the electronic component104and has a first lead portion110being encapsulated in the encapsulant106and a second lead portion112extending out of the encapsulant106at said bottom side114of the encapsulant106. Moreover, a functional structure180is formed at said bottom side114of the encapsulant106and extends up to a second vertical level184which is different from said first vertical level182. FIG.2illustrates a flowchart200of a method of manufacturing a package100according to an exemplary embodiment. The reference signs used for the following description of said manufacturing method relate to the embodiment ofFIG.1. Referring to a block202, the method comprises mounting an electronic component104on a carrier102. Referring to a block204, the method further comprises electrically coupling a lead108with the electronic component104. Referring to a block206, the method further comprises encapsulating the electronic component104and part of the carrier102by an encapsulant106which has a bottom side114at a first vertical level182. Referring to a block208, only a first lead portion110of the lead108is encapsulated in the encapsulant106. A second lead portion112of the lead108extends out of the encapsulant106at said bottom side114of the encapsulant106. Referring to a block210, a functional structure180is formed at said bottom side114and extends up to a second vertical level184which is different from said first vertical level182. FIG.3illustrates a cross-sectional view of an electronic device150comprising a package100according to an exemplary embodiment and being mounted on a substrate or mounting base152at a bottom side. In the illustrated embodiment, package100is configured in a leadless package architecture. The electronic device150is assembled in SMD technology and is composed of the semiconductor chip package100and the mounting base152at the bottom side of the electronic device150and below the package100. The mounting base152may be embodied as a printed circuit board (PCB). The package100is mounted, for instance by soldering, on the mounting base152so that electrically conductive pads164of the mounting base162are electrically coupled with free ends of electrically conductive leads108extending downwardly beyond a mold-type encapsulant106of the package100. An electrically conductive connection medium, such as solder structures, between the pads164on the one hand and the leads108and carrier102on the other hand, is shown inFIG.3with reference signs118. The leads108are configured as vertically extending pillars and can therefore be wetted by the solder material fully circumferentially as well as at a free bottom surface116. This ensures a proper electric and mechanical connection between the package100and the mounting base152. The electrically conductive leads108(for instance made of copper or aluminum) of the package100are electrically coupled with pads170of an electronic component104of the package100by electrically conductive connection elements128. In the shown embodiment, the electrically conductive connection elements128are bond wires, but may be alternatively bond ribbons or clips (see for exampleFIG.12) in other embodiments. It is possible that the carrier102and the leads108form part of a common patterned metal plate, for instance in a leadframe configuration. In particular, carrier102may be partially or entirely electrically conductive. Contact areas of the leads108being electrically coupled with the mounting base152are all arranged on a lower side of the package100. As already mentioned, the carrier102and the leads108may be formed on the basis of a common planar metal plate. Alternatively, the carrier102may be a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. Electronic component104is mounted with its bottom pad170on one main surface (which may be denoted as a mounting surface) of the carrier102, which is an upper main surface according toFIG.3. For instance, the electronic component104may be a semiconductor chip, for example a power semiconductor chip. Said power semiconductor chip may comprise at least one integrated circuit element in a semiconductor body. Such at least one integrated circuit element may for example provide the function of a transistor (for instance of a MOSFET or an IGBT). As shown, the package100may further comprise encapsulant106encapsulating the electronic component104, the electrically conductive connection elements128, part of the leads108, and part of the carrier102. However, another part of the leads108is exposed with respect to the encapsulant106to be electrically couplable with the mounting base152, as shown and described above. Furthermore, another part of the carrier102is exposed with respect to the encapsulant106so as to be electrically coupled with the mounting base152as well. Preferably, encapsulant106is electrically insulating. For example, the encapsulant106may be a mold compound (or alternatively a soft encapsulant). The encapsulant106has a bottom main surface or bottom side114which is arranged at a first vertical level182. This is indicated at a vertical axis199shown inFIG.3and being directed upwardly. Moreover, a functional structure180is formed at said bottom side114in form of two elevations130which extend from the bottom side114downwardly up to a second vertical level184which is below said first vertical level182. As already mentioned, the functional structure180is embodied, according toFIG.3, as extensions130extending downwardly from said bottom side114of the encapsulant106and protruding vertically beyond it. As shown, the second vertical level184is below the first vertical level182. According toFIG.3, the extensions130are separate from the encapsulant106and may be made of another material than said encapsulant106. In the shown embodiment, at least the exposed surface of the extensions130may comprise a solder resist which functions as an anti-wetting surface on which solder material of the electrically conductive connection medium118cannot adhere. The extensions130are positioned in through holes160of a metal plate being patterned for separating the carrier102with respect to the leads108. As can be taken fromFIG.3, each of the leads108is electrically coupled with the electronic component104by bond wire-type electrically conductive connection elements128and comprises a first lead portion110being encapsulated in the encapsulant106and a second lead portion112extending out of the encapsulant106at said bottom side114of the encapsulant106. Hence, the second lead portions112are exposed with respect to the encapsulant106. Free end portions of the leads108protrude vertically downwardly even beyond the extensions130up to a third vertical level186which is lower than the first vertical level182and lower than the second vertical level184. As a result, the extensions130do not disturb a process of connecting the leads108and the carrier100to the mounting base152by soldering. As illustrated, the second lead portions112of all leads108extend out of the encapsulant106exclusively at said bottom side114and substantially vertically. The sidewalls of the package100are therefore exclusively constituted by the encapsulant106and are free of electrically conductive material. This further improves the electric reliability of the package100. More specifically, the second lead portions112slightly taper from the bottom side114of the encapsulant106towards the bottom surface116of the second lead portions112. This tapering forms a curved or concave geometry at sidewalls120of the leads108which may increase the wetting area of the solder. As shown as well, the extensions130of the functional structure180are arranged laterally between different ones of the leads108for acting as a barrier for preventing an undesired migration of medium between different leads108. In particular, liquid or moisture may be prevented from flowing between leads108and avoids short-circuiting. Thus, the functional structure180may function as a barrier against creepage current and may render a creepage distance larger as well as a creepage path more complex. Apart from this, the barrier function of the functional structure108also suppresses an undesired solder flow away from the leads108. As can be taken fromFIG.3as well, the carrier102comprises a first carrier portion122being encapsulated in the encapsulant106and a second carrier portion124extending out of the encapsulant106at said bottom side114of the encapsulant106. In the shown embodiment, both carrier portions122,124form part of the same metal plate. Advantageously, the elevations130of the functional structure180are arranged laterally between the carrier102and the leads108for acting as barrier for suppressing a parasitic migration of medium between a respective lead108and the carrier102. For instance, it may be avoided that humidity short-cuts a lead108and the carrier102so that the functional structure108serves as barriers inhibiting creepage current flow. In addition, the barrier function of the functional structure180also avoids a flow of solder between the leads108and the carrier102. Since the carrier102and the leads108are formed on the basis of a flat metal plate being patterned by a half etching process from the top side followed by a further half etching process from the bottom side (in a similar way as shown inFIG.4andFIG.6) during the manufacturing process, bottom surface116of the leads108and a bottom surface117of the carrier102are coplanar and both lie within a horizontal plane. Correspondingly, a top surface126of the leads108and a top surface127of the carrier102are coplanar as well and both lie within another horizontal plane. This patterned plate design contributes to the compactness of the package100. Simulations have shown that the embodiment ofFIG.3may achieve a reduction of the accumulation of creep strain (wherein a volume may be averaged over control volumes) during a last thermal cycle by for instance 60% compared to a conventional lead configuration. FIG.4toFIG.6show cross-sectional views of structures obtained during carrying out a method of manufacturing a package100, shown inFIG.6, according to another exemplary embodiment. Referring toFIG.4, a metal sheet154may be used as a starting point for the manufacturing process. Optionally, selective plating (for instance silver plating) can be performed on the metal sheet154in order to prepare areas where wire bonding is later performed on the leadframe-type metal sheet154. Afterwards, the metal sheet154may be structured from the top side, for instance by structured wet etching. More specifically, a structured copper etch may be carried out from the top side only. As a result, a plurality of top-side recesses156are formed in an upper main surface of the flat metal sheet154, for instance a copper plate. This may be accomplished by a first half etching process. This way, a central die paddle or carrier102as well as leads108for the wire bonds (for example silver pre-plated) or clip bonds may be generated as top-sided elevations in the metal sheet154. The bottom of the metal sheet154remains unchanged at the present stage of the manufacturing process, especially remains a closed layer with a planar lower surface. Referring toFIG.5, die attach, wire bonding and molding processes may be carried out. More specifically, an electronic component104(such as a power semiconductor chip, for instance a field effect transistor chip) may be mounted on a central portion of the half-etched metal plate154which will later form the carrier102. Hence, a die-type electronic component104may be attached to the patterned metal sheet154on the portion functioning as die paddle. This can be done for example by solder paste print and die attach and a following reflow, or by other die attach methods like glue die attach, sinter die attach or diffusion soldering. Thereafter, the lateral portions of the patterned metal plate154which will later form the leads108may be electrically coupled with the electronic component104by connecting electrically conductive connection elements128, which are here embodied as bond wires. Also a clip for source pad or source pad and gate pad can be attached, e. g. by soldering. In case of implementing a source clip only, the gate contact can be wire bonded. For wire bonded interconnects, a selective plating may be carried out on the leadframe-type metal plate154. For instance, this can be the layer which has been applied before the first copper etch. Now the drain, source and gate of the die may be connected to the patterned metal sheet154. After that, the electronic component104, the electrically conductive connection elements128, and an upper portion of the patterned metal plate154which will later constitute the carrier102and the leads108may be encapsulated by an encapsulant106. A bottom side114of the encapsulant106is defined by the bottom surface of the blind hole-type recesses156and is located at first vertical level182(compareFIG.6) of the readily manufactured package100. For instance, a molding process (in particular map molding, compression molding) may be performed for encapsulation. The created encapsulant106may embed the die(s) constituting the at least one electronic component104and the wires and/or clips on the metal sheet154. Referring toFIG.6, a bottom side structured copper etch may be carried out, optionally accompanied by electroless plating for promoting wettability. More specifically, the manufacturing method may be continued for forming bottom-sided recesses158in a lower main surface of the metal sheet154. The bottom-sided recesses158may be formed at positions ensuring that the top-side recesses156and the bottom-side recesses158are connected to form through holes160separating the metal sheet154into the carrier102and the leads108. Hence, the carrier102and the leads108may be created by patterning planar metal sheet154by etching, more specifically by two subsequent half etching processes carried out from the top side and subsequently from the bottom side of the metal sheet154. Thus, the bottom side of the metal sheet154is structured for separating carrier102and leads108. This can be done by using an etch resist and selective copper etching. Advantageously, the copper is not removed at the positions of the leads108, leading to elevated leads108in form of second level copper pillars. These pillar-type leads108are protruding out of the mold body constituting the encapsulant106. Advantageously, said pillar-type leads108may be completely embedded in solder paste during board level assembly and may be completely embedded in solder after the second level assembly. In order to achieve particularly pronounced wettability, the leads108can be optionally plated with a noble pad finish, such as tin (Sn) or palladium (Pd) or nickel-gold (NiAu). Also the leads108can be coated with an organic surface protect (OSP). After that, it may be possible to form recesses131as functional structure180at said bottom side114of the encapsulant106extending upwardly up to a second vertical level184being above said first vertical level182. More specifically, the empty recesses131extend upwardly from the bottom side114into the encapsulant106. In comparison with the embodiment ofFIG.3, the package100according toFIG.6does not implement downwardly protruding extensions130as functional structure180, but in contrast to this upwardly protruding recesses131. Recesses131may for instance be formed by etching, laser processing or mechanically drilling for removing material of the encapsulant108starting from its bottom side114. FIG.7toFIG.9show cross-sectional views of structures obtained during carrying out a method of manufacturing a package100, shown inFIG.9, according to still another exemplary embodiment. Referring toFIG.7, the top-side recesses156are formed in metal plate154with a stepped profile162which narrows towards or at a bottom188of the stepped recesses156. This can be accomplished by correspondingly designing the half etching process of treating the metal plate154at its top side. Referring toFIG.8, said stepped profile162is filled with material of encapsulant106during encapsulating to thereby form narrowed extensions130as bottom-sided appendices of the (for instance mold-type) encapsulant106. Encapsulation is carried out after component assembly on a preform of carrier102and after connection of the assembled electronic component104with the preforms of the leads108by electrically conductive contact elements128, as described above referring toFIG.5. Referring toFIG.9, said mold extensions130may be exposed by forming said bottom-side recesses158by half etching of the metal plate154from its bottom side. In the preferred embodiment of package100according toFIG.9, the extensions130form part of and are integrally formed with said encapsulant106. Hence, the extensions130according toFIG.9may also be denoted as mold body extensions. The shown functional structure180embodied as extensions130protruding vertically beyond the bottom side114of the encapsulant106but not up to the bottom surface116of the leads108spatially separate the carrier102with respect to the leads108and also spatially separate the leads108from each other without causing an undesired interaction with the solder connection between the second lead portions112and the mounting base152by solder-type electrically conductive connection medium118. The dielectric mold extensions130can be manufactured substantially without additional manufacturing effort and are intrinsically rigidly connected with the rest of the encapsulant106. Furthermore, the mold extensions130increase the creepage distance between carrier102and leads108as well as between different leads108and also function as non-wettable solder barrier. For example, the extensions130may be straight or curved walls extending into the paper plane ofFIG.9or may be a circumferentially closed annular structure. The preferred embodiment ofFIG.9shows an advantageous package100with a mold body being extended at a bottom side114. In this embodiment, the base leadframe in form of the metal plate154is structured in a way that more than one depth level (at leadframe top side) will result in the illustrated extended mold body structure after bottom side structuring of the metal plate154. The elevated mold body material in form of the extensions130may serve as barrier in between adjacent pads or leads108, which may be an enabler for a higher creepage distance on the one side, and which may simultaneously ensure a robust device mounting quality, as the extended mold body advantageously disables solder shortage. The extended mold body may result in an enhanced creepage distance and an improved barrier for solder shortage between adjacent leads108or pads. FIG.10toFIG.12show cross-sectional views of structures obtained during carrying out a method of manufacturing a package100, shown inFIG.12, according to still another exemplary embodiment. Referring toFIG.10, metal plate154is patterned on its upper side by forming top-sided recesses156by half etching, similar as inFIG.4but with a different pattern. Referring toFIG.11, a planar clip is attached as flat electrically conductive connection element128on top of the patterned metal plate154after assembly of electronic component104on the patterned metal plate154. After encapsulation and now referring toFIG.12, the carrier102and the leads108are separated from the metal plate154by half etching from its back side. Furthermore, two wall-shaped or one annular extension130may be inserted in a recess formed in the bottom side114of the encapsulant106as a creepage current inhibitor and/or as a solder wetting barrier. The package100according toFIG.12differs from the package100according toFIG.3in particular that, in the embodiment ofFIG.12, a flat planar clip is implemented as electrically conductive connection element128for electrically coupling the leads108with the electronic component104. Due to the patterning according toFIG.10, a top surface126of the leads108protrudes vertically beyond a top surface127of the carrier102so that the top surface126of the leads108are coplanar with a top surface129of the electronic component104. This allows to implement an electrically conductive connection element128embodied as flat clip for electrically coupling the top surface126of the leads108with the top surface129of the electronic component104. The embodiment according toFIG.12may hence be denoted as clip-attached die configuration. FIG.13illustrates an exploded view of part of an electronic device150comprising a package100with elevated lead108according to an exemplary embodiment and to be mounted on a mounting base152used as a basis for a simulation. Improvements which may be achieved with an elevated lead108have been investigated by said simulation. The simulation has been performed for demonstrating that an elevated lead108, protruding for instance by 100 μm downwardly, is reducing the accumulation of creep strain (volume averaged over control volumes) during a last thermal cycle by 60% compared to a conventional lead. As a result, a package100with improved reliability may be obtained. FIG.14andFIG.15show images of a solder connection between a package100with elevated leads108and a mounting base152according to exemplary embodiments.FIG.14andFIG.15show two investigated versions. According toFIG.14, the sidewall is wetted. InFIG.15, the sidewall wetting was suppressed. The result of the board level reliability is that removing sidewall wetting may lead to a reduction of reliability by for instance 25%. A strong improvement can therefore be obtained by embedding leads108from all four sides in solder. FIG.16illustrates a bottom view of a package100according to an exemplary embodiment. According toFIG.16, the functional structure180comprises an annular structure surrounding the carrier102. Furthermore, the functional structure180ofFIG.16is integrally formed with the encapsulant106, i.e. is embodied as mold protrusion(s). Functional structure180may comprise a rectangular wall, but may alternatively comprise a circular wall. Another rectangular or circular mold protrusion may surround a respective lead108, also forming part of functional structure180. It should be noted that the term “comprising” does not exclude other elements or features and the “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. | 60,634 |
11862583 | DETAILED DESCRIPTION The present technology will now be described with reference to the figures, which in general, relate to a semiconductor wafer thinned by a stealth lasing process, and semiconductor dies cut therefrom. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by focusing a laser at discrete points in the wafer substrate beneath the surface of the wafer. The discrete focal points of the laser are provided in one or more planes parallel to the front and back surfaces of the wafer. Upon completion of stealth lasing in one or more planar layers in the substrate, a portion of the substrate may be removed, leaving the wafer thinned to a desired final thickness. In embodiments, the wafer may then undergo a polishing step, and may thereafter be diced into individual semiconductor dies. It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details. The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal,” and forms thereof, as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±5 um An embodiment of the present technology will now be explained with reference to the flowchart ofFIG.1, and the views ofFIGS.2-10. Referring initially to the flowchart ofFIG.1, a semiconductor wafer100may start as an ingot of wafer material, which may be formed in step200. In one example, the ingot from which the wafers100are formed may be monocrystalline silicon grown according to either a Czochralski (CZ) or floating zone (FZ) process. However, wafer100may be formed of other materials and by other processes in further embodiments. In step204, the semiconductor wafer100may be cut from an ingot and polished on both the first major surface102(FIG.2), and second major surface104(FIG.4) opposite surface102, to provide smooth surfaces. In step206, the first major surface102may undergo various processing steps to divide the wafer100into respective semiconductor dies106(one of which is numbered inFIG.2), and to form integrated circuits of the respective semiconductor dies106on and/or in the first major surface102. FIG.3is a cross-sectional side view of an exemplary semiconductor die106of the wafer100showing the integrated circuit layer110formed in a silicon substrate112. Integrated circuit layer110may in general include integrated circuits114electrically coupled to surface die bond pads116by metallization layers118. The integrated circuits114may be formed by various processes including for example deposition, patterning and doping of metals, metal oxides and silicon. After formation of the integrated circuits114, metallization layers118may be defined including metal interconnects120and vias124layered sequentially in a dielectric film128. As is known in the art, the metal interconnects120, vias124and dielectric film128may be formed for example by damascene processes a layer at a time using photolithography and thin-film deposition. The metal interconnects120and vias124may be used to form conductive nodes for transferring signals and voltages between the die bond pads116and integrated circuits114. A passivation layer130may be formed on top of the upper dielectric film layer128. The passivation layer130may be etched to expose the die bond pads116. In embodiments, the semiconductor dies106may for example be flash memory dies such as 2D NAND flash memory or 3D BiCS (Bit Cost Scaling), V-NAND or other 3D flash memory, but other types of dies106may be used. These other types of semiconductor dies include but are not limited to RAM, a controller, an SOC (system on a chip), a processor or other types of semiconductor dies. It is known to create a single integrated memory die module comprised of a first semiconductor die including the memory array, and a second semiconductor die including the logic circuit such as CMOS integrated circuits. An example of such an integrated memory die module is disclosed in Published U.S. Patent Application No. U.S. 2019/0341375, entitled “Bifurcated Memory Die Module Semiconductor Device.” Dies106may further be from a wafer of such bifurcated memory array semiconductor dies, or from a wafer of such bifurcated CMOS logic circuit dies. The number of dies106shown on wafer100inFIG.2is for illustrative purposes, and wafer100may include more semiconductor dies106than are shown in further embodiments. Similarly, the number of bond pads116on each semiconductor die106is shown for illustrative purposes, and each die106may include more die bond pads than are shown in further embodiments. After formation of the integrated circuit layer110in step206, a layer of tape may be laminated onto the active, major surface102in step210. The wafer100may then be turned over and thinned in step212. In accordance with aspects of the present technology, the second surface may be lased by performing a stealth lasing step to thin the wafer as will now be explained with reference toFIGS.4-9. Referring to the perspective view ofFIG.4, the wafer100may be supported on a chuck or other support surface (not shown) with the laminated active surface102facing the chuck and the second major surface104facing upward. A laser150may then emit a pulsed laser beam152at a wavelength that transmits through the second major surface104of the wafer100, for example at infrared or near-infrared wavelengths. The pulsed laser beam may be focused to a point beneath the wafer's surface104using an optical system, for example including one or more collimating lenses156. Referring now to the cross-sectional edge view ofFIG.5, when the laser beam152hits the second major surface104, the beam refracts due to light in the laser beam slowing as it passes into the silicon substrate112. The amount of refraction may vary depending on the refractive index of the substrate112material.FIG.6is an enlarged view of a section of substrate112within the dashed oval ofFIG.5. As shown inFIGS.5and6, the collimating lens154causes the beam152to converge to a focal point160where the energy of the laser beam152is most concentrated. When the laser beam152hits a peak power density at the focal point160, the substrate112absorbs the energy, and the area around the focal point is vaporized, creating a void162around the focal point. In particular, as the beam152converges above the focal point160, and diverges below the focal point160, the beam will be sufficiently concentrated, and the energy high enough, above and below the focal point to vaporize the substrate material along a predefined height. That height is shown by H in the perspective view of a single void162inFIG.7. In the laser beam152above and below the void162, the energy of the laser beam152is sufficiently defocused so as to leave the substrate112intact. The void162will also have a diameter, D, which is a function of the void height, H, and the convergence angle of the laser beam152in the substrate112, after refraction. The dimensions H and D of a void162may be controlled by a variety of factors, including laser150peak power intensity, laser beam152diameter, the convergence angle created by the collimating lens156and the angle of refraction of the substrate112. The peak power and beam area together define the peak power density of laser150: Peak power density W/m2=peak power (W)/beam area (m2). In one example, the peak power of laser150may be 2 W, and the beam diameter≈2˜4 μm. These values are by way of example only, and may vary in further embodiments. In one example, the collimating lens156may create an angle of convergence, θ, of laser beam152of ˜50°. This angle may change upon entering the substrate112to a refractive angle, ϕ, of ˜80°. The angle of refraction will depend on the incoming collimating lens angle θ, and the relative permittivity, εr, of the substrate112. In embodiments, the substrate112may have a relative permittivity, εr, of between 11.0 and 12.0. These angles and relative permittivity values are by way of example only, and may vary in further embodiments. With such parameters, the void162may have a height, H, of 1.4˜2 μm, and a diameter, D, of 2˜4 μm. Again, these dimensions are by way of example only. Moreover, while the void162is shown as being generally cylindrical inFIG.7, the voids162may have other shapes in further embodiments, including ovoid, spherical, or a combination of cylindrical, ovoid and/or spherical. Referring again toFIG.5, the voids162may be formed in one or more planar layers164. The one or more planar layers of voids define a modified zone166in the wafer substrate112where the wafer will separate upon completion of the stealth lasing process. The planar layers164in the modified zone166may be parallel to each other and the first and second major surfaces102,104of the wafer100. In one example, there may be four layers164of voids162formed, but there may be 1 layer, 2 layers, 3 layers or more than 4 layers in further embodiments. A higher number of layers facilitates easier separation of the substrate112. The position of each layer164relative to the second planar surface104may be controlled by a variety of parameters, including the peak power density of the laser150, the height of the collimating lens156above surface104, and the collimator and refractive angles, θ and ϕ. Examples of the laser peak power density, collimator angle and refractive angle are provided above. With the above parameters being constant, the height of each layer164beneath the surface104of wafer100(also referred to as the defocus height) may vary by changing a position of the collimating lens156above the surface. In examples, the collimating lens156may move between 181 μm and 186 μm above the surface104of wafer100to create the different layers164. Another parameter which may be controlled when performing the stealth lasing step212is the spacing between voids162in a layer164. A pattern of higher density voids162will remove more material from the modified zone166where the voids are formed making it easier to separate the substrate112. Spacing between voids162, also referred to as pulse interval, is given by: Pulse interval (μm)=laser feed rate (mm/s)/laser pulse frequency (kHz). In one example, the laser150may move at a rate of 300 mm/s relative to the surface104of wafer100, and the pulse frequency may be 90 kHz. Thus: Pulse interval≈3.3 μm. It is understood that the feed rate may be other values, such as for example 250 mm/s, and the pulse frequency may be other values, in further examples. FIG.8is an edge view showing the wafer100after the laser150has formed the multiple layers164of the modified zone166in the substrate112. In one example, the wafer may have a total thickness of 760 μm. The modified zone166may be about 20-25 um thick. In one example, the thickness, Tw, of the finished wafer may be 32 μm. Thus, the thickness, Ts, of the removed substrate112may be between 703 μm and 708 μm. Again, these values are by way of example only and each may vary in further embodiments. For example, the thickness of the finished wafer100may be 25 μm or thinner. Where the finished wafer100is 25 μm, the thickness of the removed substrate, Ts, may be between 710 μm and 715 μm. FIG.9is an edge view showing removal of a portion of the substrate112, specifically portion112a, at the modified zone166after the stealth lasing step212. A portion of the substrate112, specifically substrate112b, remains as part of the wafer100. The portion112athat was severed may be discarded. The new second major (back) surface104is the surface of substrate112adefined by removal of the portion112b. In embodiments, after stealth lasing step212, the back surface104may undergo a polishing step214, using for example a Z3 polishing wheel rotating against the back surface. In further embodiments, it is conceivable that the parameters of stealth lasing step212be controlled such that polishing step214may be omitted. After completion of the stealth lasing step212and polishing step214(where included), a layer of die attach film (DAF) adhered to a flexible dicing tape may be applied onto the second major surface104of the wafer100in step218. The wafer100may then be turned over and supported on a chuck or other support surface, and the lamination tape on the active, first major surface102of the wafer100may be removed in step220. Thereafter, the wafer100may be diced in step222. Dicing of the wafer may be performed for example using a known cutting blade. It is also known to dice wafers using a stealth dicing process in which a laser forms layers of voids in vertical planes (orthogonal to surfaces102,104) around the outline of each semiconductor die106in wafer100. The stealth dicing process is distinguishable from the stealth lasing process of the present technology to thin the wafer in several respects. For example, stealth dicing may use a narrow diameter beam which forms impact points in vertical planes of the wafer. The stealth dicing impact points do not cut the wafer. Instead, after creation of the impact points, stresses on the wafer are generated which propagate the impact points along vertical crystalline planes to sever the individual semiconductor dies. Other dicing methods may be used. After dicing step222, the flexible dicing tape may be stretched along orthogonal axes to separate the individual semiconductor dies106in step224. Thereafter, in step226, individual semiconductor dies106may be removed by a pick and place robot for inclusion in a semiconductor package. Stealth lasing to thin the wafer100as described above provides several advantages. As noted in the Background, conventional backgrinding processes may generate cracks in semiconductor wafers, especially those that are currently made at thin, fragile thicknesses. Stealth dicing according to the present technology eliminates wafer cracking due to the backgrinding processes. Elimination of such cracks improves wafer and die yields, and does away with the need for additional screening/inspection steps. Additionally, conventional backgrinding processes generate debris and foreign materials that can cause cracks and otherwise impair the assembly process. Elimination of the backgrinding process prevents the generation of this debris and foreign material, thus further improving yield and die quality. Moreover, the multiple backgrinding wheels needed for conventional wafer thinning add significant time, expense and complexity to the packaging process. Omission of the backgrinding wheels in accordance with the present technology improves each of these packaging parameters. It is a further advantage of the present technology that the laser beam152has sufficiently diverged, or defocused, by the time it reaches the integrated circuit layer110. Thus, the stealth lasing may be provided to thin the wafer without damaging the integrated circuit layer110. FIG.10shows an exemplary semiconductor die106after separation from wafer100. The die106includes die bond pads116at the first major surface102of the die106. The die106includes a lased, second major surface formed by the stealth lasing process described above. A DAF layer176is also shown on the second major surface104. In summary, an example of the present technology relates to a semiconductor die, comprising: a first major surface; a plurality of integrated circuits formed in the first major surface of the wafer; a lased, second major surface opposed to the first major surface; a die attach film layer covering the lased, second major surface. In another example, the present technology relates to a semiconductor wafer, comprising: a first major surface; a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer; and a lased, second major surface opposed to the first major surface. In a further example, the present technology relates to a semiconductor wafer, comprising: a first major surface; a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer; a second major surface opposed to the first major surface; wherein the second major surface is defined by means for severing a first portion of the wafer from a second portion of the wafer. The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto. | 18,150 |
11862584 | It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements. DETAILED DESCRIPTION A method and apparatus are described for fabricating circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process by using a first ceramic build process to form a bottom high dielectric constant (e.g., k=5.8−6.8) glass carrier having an integrated differential pair to waveguide launcher in package (LIP) structure and an air cavity structure formed in the waveguide short back, and by using a second ceramic build process to form a top high dielectric constant glass carrier having a patterned ceramic/glass structure to provide waveguide matching and reduced insertion loss performance. Specifically, during the packaging process, a high-k bottom glass carrier substrate is processed with a ceramic build process to form one or more ceramic regions in an intended waveguide region and to form an air cavity in the one or more ceramic regions. Either before or after forming the air cavity, conductive layers are formed on the high-k bottom glass carrier substrate, including a differential pair radiating element located on a first carrier substrate surface adjacent to the air cavity, a reflector interface layer located on a second carrier substrate surface, and a conductive via wall or ring structure located in the one or more ceramic regions that surrounds the intended waveguide region and connects the reflector interface layer to the first carrier substrate surface. In addition, a singulated die is attached on the high-k bottom glass carrier substrate, followed by optionally covering the air cavity with a substrate cap sheet; applying a molding compound over the die, substrate cap sheet, and differential pair radiating element; and forming a conductive via wall or ring structure in the molding compound to surround the intended waveguide region. In addition, a high-k top glass carrier substrate is processed with a ceramic build process to form a patterned ceramic structure in an intended waveguide region that is surrounded by a conductive via wall or ring structure, thereby providing waveguide matching and reduced insertion loss performance when attached to the high-k bottom glass carrier substrate. In this way, a circuit waveguide interface is formed in the high-k bottom and top glass carriers with conductive via wall or ring structures formed around the patterned ceramic layer structure in the intended waveguide region. By forming the differential pair radiating element on the first carrier substrate surface of the high-k bottom glass carrier (instead of in the circuit waveguide interface), the LIP transition loss may be significantly reduced to 1.0 dB while also relaxing tolerance control requirements for alignment of critical elements. The embodiments described herein use WSDP processes to both form the package and form a circuit waveguide interface integrated with the package, and thus can facilitate the formation of the circuit waveguide interface with both relatively high precision and relatively low cost and complexity. In WSDP processes, singulated die are arranged on a wafer-like carrier panel for processing and packaging. The singulated die on the carrier panel are then covered with molding compound that will harden to provide the bodies of the packages of the die on the carrier panel. Photolithography and other wafer-type processing techniques are used to form one or more metallization layers (e.g., copper) that provide connections from the die to outside the package. In WSDP processing, these connections can be formed on the top and bottom sides of the molded die, and can include interconnects between metallization layers. For example, metallization layers on one side can be formed for die-to-die connections, and metallization layers on the other side can be formed to provide landing pad arrays. The molded die on the panel is then singulated into discrete packages. As will be described in greater detail below, the embodiments herein provide a technique for forming a circuit waveguide interface during such a wafer-scale die packaging process. Turning now toFIGS.1A and1B, a top view10A and cross-sectional side view1B (through lineFIG.1B-FIG.1BofFIG.1A) are illustrated of a glass wafer11with one or more first patterned ceramic regions12A-D at a first stage of a package fabrication process in accordance with selected embodiments of the present disclosure. The glass wafer11may be initially formed as a “photo-structurable glass” with a high-k dielectric material having a high dielectric constant (e.g., k>3.9). In selected embodiments, the glass wafer11may be formed with an APEX® Glass wafer containing special sensitizers that allow unique anisotropic 3D features to be formed through a simple exposure step. Using standard IC processing tools, patterned ceramic regions12may be formed in the glass wafer11at predetermined locations. For example, the glass wafer11may be exposed to a first mask pattern and then baked to convert the exposed regions of the glass11into patterned ceramic regions12which extend through the glass wafer11. By defining the locations of the mask openings, a first set of patterned ceramic regions12A may be positioned outside of the intended die region13and a second set of patterned ceramic regions12B-C may be positioned inside the intended die region13. In addition, a third set of patterned ceramic regions12D may be positioned around the periphery of an intended waveguide region14. Turning now toFIGS.2A and2B, a top view20A and cross-sectional side view (through lineFIG.2B-FIG.2BofFIG.2A) are illustrated of a glass wafer11with one or more patterned openings21at a stage of a package fabrication process afterFIG.1. While any suitable etch process may be used, the patterned openings21may be formed by applying a wet etch to remove the patterned ceramic regions12, thereby leaving the patterned openings21which extend through the glass wafer11. As formed, the patterned openings21may include a first set of patterned openings21A positioned outside of the intended die region13and a second set of patterned openings21B-C positioned inside the intended die region13. In addition, a third set of patterned openings21D may be positioned around the periphery of an intended waveguide region14. Turning now toFIGS.3A and3B, a top view30A and cross-sectional side view (through lineFIG.3B-FIG.3BofFIG.3A) are illustrated of a glass/ceramic carrier11with one or more second patterned ceramic regions31for the intended waveguide region14at a stage of a package fabrication process afterFIG.2. At this point in the fabrication process when the glass/ceramic carrier11already has the patterned openings21D formed in the intended waveguide region14, the patterned ceramic region(s)31may be formed by exposing the glass/ceramic carrier11to a second mask pattern and then applying a second bake process to convert the exposed region(s) of the glass11into one or more second patterned ceramic regions31which extend through the glass/ceramic carrier11. By defining the locations of the openings in the second mask, the second patterned ceramic region(s)31may be positioned to encompass and include the intended waveguide region14and to extend into the intended die region13. Turning now toFIGS.4A and4B, a top view40A and cross-sectional side view (through lineFIG.4B-FIG.4BofFIG.4A) are illustrated of a glass/ceramic carrier11with patterned conductive vias41formed at a stage of a package fabrication process afterFIG.3. At this point in the fabrication process when patterned openings21are already formed in the glass/ceramic carrier11, the patterned conductive vias41may be formed with one or more conductive layers, such as by depositing (e.g., vapor deposition, electroplating, sputtering) one or more conductive materials (e.g., copper) to fill the patterned openings21and then applying a polish or etch process to remove the conductive layer(s) from the first and second carrier substrate surfaces. As formed, the patterned conductive vias41may include a first set of patterned conductive vias41A positioned outside of the intended die region13and a second set of patterned conductive vias41B-C positioned inside the intended die region13. In addition, a third set of patterned conductive vias41D may be positioned around the periphery of an intended waveguide region14except for any location which will overlap with a subsequently-formed differential pair to waveguide launcher in package (LIP) structure. Turning now toFIGS.5A and5B, a top view50A and cross-sectional side view50B (through lineFIG.5B-FIG.5BofFIG.5A) are illustrated of a glass/ceramic carrier11with patterned redistribution layers (RDLs)51,52, including a radiating element51B-C in the intended waveguide region14, at a stage of a package fabrication process afterFIG.4. At this point in the fabrication process, the patterned top RDLs51and/or bottom RDLs52may be formed directly on the first and second carrier substrate surfaces using any suitable process for depositing and patterning one or more conductive layers. For example, the patterned top RDLs51may be formed in openings of a patterned RDL dielectric layer53formed on the first carrier substrate surface by sputter depositing a seed layer in the openings of the patterned RDL dielectric layer53, forming a patterned photoresist mask with defined RDL openings corresponding to the desired RDL features, electroplating one or more conformal conductive layers in the RDL openings, stripping the patterned photoresist mask, and then etching the exposed seed layer from the surface of the patterned RDL dielectric layer53to define the top RDLs51. As formed, the top RDLs may include one or more IC trace or connection lines51A which are positioned to overlap with and connect selected patterned conductive vias41A (positioned outside of the intended die region13) with selected patterned conductive vias41B-C (positioned inside the intended die region13). In addition, the top RDLs may include a separately defined loop layer which includes a pair of parallel waveguide feed lines51B (which are positioned to extend from the intended die region13to the intended waveguide region14) and a radiating element51C (which is positioned in the intended waveguide region14to connect the pair of parallel waveguide feed lines51B in a loop). In addition, the top RDLs may include a separately defined outer waveguide ring layer51D which has an open interior space and which is positioned around the periphery of the intended waveguide region14except for a gap where the waveguide feed lines51B are located. Thus formed, the waveguide feed lines51B and radiating element51form a differential pair to waveguide launcher in package (LIP) structure on the top carrier substrate surface which is positioned to extend from the intended die region13to the interior location surrounded of the intended waveguide region by the waveguide ring layer51D while leaving space for a subsequently-formed air cavity. In similar fashion, the patterned bottom RDLs52may be formed by using any suitable process for depositing and patterning one or more conductive layers on the bottom carrier substrate surface. As formed, the bottom RDL layer(s) may define a waveguide reflector interface layer which is positioned on the bottom carrier substrate surface to overlap with the outer waveguide ring layer51D, including its interior space so as to cover the entire area of the intended waveguide region14. Though the top RDL layers51-53are illustrated for simplicity as a single conductive layer being formed on the first and second carrier substrate surfaces, it will be appreciated that a multi-layer conductive routing structure can be built up with successive levels of dielectric layers and patterned RDL conductive routing or trace lines that are formed on the carrier substrate surfaces of the glass/ceramic wafer structure. InFIG.5B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.5B-FIG.5B) at the intended die region13and waveguide region14. As a result, there is no patterned conductive via41D depicted in Figure at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.5B-FIG.5B) is positioned in alignment with the underlying waveguide feed lines51B. However, the positions of the next adjacent patterned conductive vias41D at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. Turning now toFIGS.6A and6B, a top view60A and cross-sectional side view (through lineFIG.6B-FIG.6BofFIG.6A) are illustrated of a glass/ceramic carrier11with a partially etched air cavity61in the intended waveguide region at a stage of a package fabrication process afterFIG.5. While any suitable recess etch process may be used, the air cavity61may be formed by applying a solder mask to cover the first and second carrier substrate surfaces except for an exposed area in the patterned ceramic region31where the air cavity61will be formed, and the performing a recess etch of the exposed ceramic region31using a timed anisotropic etch to form the air cavity61. The process parameters and timing of the recess etching should be controlled to etch a specified depth which leaves a thin layer of the patterned ceramic region31below the air cavity61at the bottom ceramic carrier substrate surface, thereby defining a waveguide short back below the differential pair to waveguide LIP structure51B/C. In addition, a patterned mask and etch process may be controlled so that the air cavity61is positioned inside the intended waveguide region14and adjacent to the differential pair to waveguide LIP structure51B/C. As will be appreciated, the recess etching control process parameters may require a specified minimum thickness of the glass/ceramic carrier11in order to guarantee the required thickness parameters for the waveguide back short. InFIG.6B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.6B-FIG.6B) at the intended die region13and waveguide region14, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.6B-FIG.6B) is positioned in alignment with the underlying waveguide lines51B. However, the positions of the next adjacent patterned conductive vias41D at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. Turning now toFIGS.7A and7B, a top view70A and cross-sectional side view (through lineFIG.7B-FIG.7BofFIG.7A) are illustrated of a glass/ceramic carrier11with one or more attached die72at a stage of a package fabrication process afterFIG.6. In accordance with the embodiments described herein, the fabricated IC die72may include one or more radio frequency (RF) devices that are to be coupled to a waveguide through a waveguide interface. As will be appreciated, the die72may include an active side on the bottom where fabricated electronic circuits and electrical contacts are formed, and an inactive side on the top side opposite to the active side. Using any suitable bonding or attachment mechanism, a plurality of contact pads71is used to electrically connect the electrical contacts on the bottom active side of the die72over the top RLD layers51A and to the underlying patterned conductive vias41A-C. In WSDP processes, a plurality of singulated die are arranged for placement and attachment over a corresponding plurality of intended die regions13of the glass/ceramic carrier11for processing and packaging. InFIG.7B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.7B-FIG.7B) at the intended die region13and waveguide region14, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.7B-FIG.7B) is positioned in alignment with the underlying waveguide lines51B. However, the positions of the next adjacent patterned conductive vias41D at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. Turning now toFIGS.8A-C, a top view80A and cross-sectional side view80B (through lineFIG.8B/C-FIG.8B/C ofFIG.8A) are illustrated of a top glass/ceramic carrier81-85along with a cross-sectional side view80C of the glass/ceramic carrier11shown inFIGS.7A-Bafter attaching the top glass/ceramic carrier81-85in accordance with selected embodiments of the present disclosure. As disclosed herein, any suitable ceramic build process can be used to form the top glass/ceramic carrier81-85. For example, an initial glass wafer81may be provided as a wafer of “photo-structurable glass” with a high-k dielectric material having a high dielectric constant (e.g., k>3.9). In selected embodiments, the glass wafer81may be an APEX® Glass wafer containing special sensitizers that allow unique anisotropic 3D features to be formed through a simple exposure step. Using standard IC processing tools, patterned conductive wall rings83,85are formed on the first and second carrier substrate surfaces of the top glass/ceramic carrier81along with conductive vias84formed in the top glass/ceramic carrier81to electrically connect the patterned conductive wall rings83,85. In addition, a patterned ceramic layer82is formed on a first carrier substrate surface to provide a waveguide region in the top glass/ceramic carrier81, and a recessed die cavity86is also formed in a second carrier substrate surface of the top glass/ceramic carrier81. For example, the top glass carrier wafer81may be sequentially exposed to one or more first patterned masks and then baked to convert the exposed regions of the top glass carrier wafer81into patterned ceramic regions which are then removed with a suitable etch process, such as a wet etch, to form patterned openings in the top glass carrier wafer81which are then filled with one or more conductive layers to form the patterned conductive features83-85, such as by depositing (e.g., vapor deposition, electroplating, sputtering) one or more conductive materials (e.g., copper) to fill the patterned openings and then applying a polish or etch process to remove the conductive layer(s) from the first and second carrier substrate surfaces. As formed, the patterned conductive wall rings83,85and conductive vias84may be positioned around the periphery of an intended waveguide region except for any location which will overlap with a subsequently-formed differential pair to waveguide launcher in package (LIP) structure. After forming the patterned openings in the top glass carrier wafer81which define the patterned conductive wall rings83,85and conductive vias84in the top glass/ceramic carrier81, the patterned ceramic region(s)82may be formed by exposing the top glass/ceramic carrier81to a second patterned mask and then applying a second bake process to convert the exposed region(s) of the top glass carrier wafer81into one or more second patterned ceramic regions82which extend through the top glass carrier wafer81. By defining the locations of the openings in the second mask, the second patterned ceramic region(s)82may be positioned to encompass and include the intended waveguide region and to extend into the intended die region. In similar fashion, the recessed die cavity86may be formed in the second carrier substrate surface of the top glass/ceramic carrier81using any suitable recess etch process. For example, a patterned etch mask may be formed on the second carrier substrate surface of the top glass/ceramic carrier81with an opening at the intended die cavity area, followed by performing a timed anisotropic recess etch to partially etch or recess the exposed portion of the top glass/ceramic carrier81. The process parameters and timing of the recess etch process should be controlled to etch the die cavity86to a specified depth which is sufficient to fit the attached IC die72. As will be appreciated, the patterned masks and etch mask are removed from the top glass/ceramic carrier81using any suitable mask removal or etch process. As formed, the second patterned ceramic region(s)82may extend completely through the top glass carrier wafer81as a single continuous layer. Alternatively, an optional solid thin layer of glass (not shown) may be defined on the topmost or first carrier substrate surface of the top glass/ceramic carrier81. For example, by controlling the timing and/or temperature of the baking process used to convert the exposed portion of the top glass carrier wafer81into the patterned ceramic region(s)82, a remnant layer of un-converted glass may be formed on the topmost or first carrier substrate surface of the top glass/ceramic carrier81. Turning now toFIG.8C, a cross-sectional side view80C is illustrated of the top glass/ceramic carrier81-85being mounted or attached to the bottom glass/ceramic carrier11shown inFIG.7Bto form a packaged semiconductor device in accordance with selected embodiments of the present disclosure. In the depicted example, the top glass/ceramic carrier81-85assembly is affixed to the bottom glass/ceramic carrier using suitable attachment mechanisms, such as an adhesive or bonding layer, a compression mounting technique, or other similar lamination bonding processes. For example, a lamination bonding process may join two or more flexible packaging webs together using a bonding agent, such as by applying an adhesive to the less absorbent substrate web, after which the second web is pressed against it to produce a duplex, or two-layer, laminate. When attached together, the die cavity86in the top glass/ceramic carrier81-85is aligned to receive the IC die72, and the second or bottom carrier substrate surface of the top glass/ceramic carrier81-82is attached to the RDL layers51,53formed on the first or top carrier substrate surface of the bottom glass/ceramic carrier11In addition, the patterned conductive features83-85in the top glass/ceramic carrier81-85are aligned for electrical connection to the waveguide ring layer51D formed on the first or top carrier substrate surface of the bottom glass/ceramic carrier11, thereby forming a waveguide interface perimeter that surrounds the patterned ceramic layer82, radiating element51C, and air cavity61. After attaching the top and bottom glass/ceramic carriers, the resulting packaged semiconductor device may be mounted to and external waveguide structure using an array of conductors. For example, a conductive ball grid array (BGA) may be affixed or attached to the first or top carrier substrate surface of the top glass/ceramic carrier. When making such a coupling, the conductive BGA can be arranged to follow the perimeter of the waveguide interface interior in alignment with the conductive wall ring85. Such use of a conductive BGA can effectively extend the circuit waveguide interface outside the packaged semiconductor device to connect to a circuit board interface. In accordance with the present disclosure, variations on the ceramic build process may be used to construct top and bottom glass/ceramic carriers with an integrated circuit waveguide interface. For example, reference is now made toFIGS.9A and9Bwhich depict a top view90A and cross-sectional side view90B (through lineFIG.9B-FIG.9BofFIG.9A) of the glass/ceramic carrier92after attaching a substrate cavity cap sheet91to cover the air cavity61at a stage of a package fabrication process afterFIG.8. The disclosed substrate cavity cap sheet91may be formed with any suitable laminate or non-conductive bonding attachment process for forming a low loss dielectric to reduce the transition loss. For example, Rogers Corporation makes RT/duroid5880laminates having low dielectric constant and low dielectric loss properties that are well suited for high frequency/broadband applications. As attached, the substrate cavity cap sheet91will prevent the air cavity61from being filled by any subsequently formed molding compound material. However, in embodiments where an air cavity is formed internally within the patterned ceramic region31, then there is no need for the protective substrate cavity cap sheet91. InFIG.9B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.9B-FIG.9B) at the intended die region13and waveguide region14, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.9B-FIG.9B) is positioned in alignment with the underlying waveguide lines51B. However, the positions of the next adjacent patterned conductive vias41D at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. Turning now toFIGS.10A and10B, a top view100A and cross-sectional side view100B (through lineFIG.10B-FIG.10BofFIG.10A) are illustrated of an encapsulated glass/ceramic carrier11with a mold compound101formed over the die72and cavity cap sheet91at a stage of a package fabrication process afterFIG.9. Formed with any suitable molding compound deposit process, the molding compound101has a first (top) side and a second (bottom) side which is attached to the RDL layers51,53formed on the first or top carrier substrate surface of the bottom glass/ceramic carrier11. For example, in WSDP processing, the molding compound is typically applied in a liquid or semi-liquid state to cover the arrangement of IC die72and associated other components on the bottom glass/ceramic carrier11. The applied molding compound may then be subjected to vacuum to extract bubbles that could otherwise create voids in the molding compound, and then cured and (optionally) planarized after curing. As indicated above, the cavity cap sheet91prevents the molding compound material101from filling the air cavity61in the intended waveguide region14. After forming the molding compound101, conductive vias102and wall rings103are formed in the molding compound101around the intended waveguide region using any suitable sequence of IC fabrication steps. For example, a patterned array of via openings may be formed in the molding compound101and positioned around the periphery of an intended wave guide region14using any suitable processing steps (e.g., pattern and etch, laser drilling, etc.), and then filled with one or more conductive layers and optionally polished or planarized. Thus constructed, the filled vias form a first array of conductive vias102that will define a waveguide interface perimeter in the molding compound101which is positioned around the periphery of the intended wave guide region14except for a gap where the waveguide lines51B are located. Alternatively the first array of conductive vias102can be formed with a single conductive ring which is positioned around the periphery of the intended wave guide region14except for a gap where the waveguide lines51B are located. After forming the first array of conductive vias102in the mold compound101, a patterned wall ring103may be formed on the molding compound101to make direct electrical connect to the conductive vias102using any suitable process for depositing and patterning one or more conductive layers. For example, the patterned wall ring103may be formed by forming the vias in mold compound using a laser drilling process to form blind vias and the plating a metal layer (e.g., copper) along the via sidewalls. Alternatively, the patterned wall ring103may be formed by applying a patterned etch process to selectively etch a wall ring opening in the first (top) side of the molding compound101, and then sputter depositing a seed layer over the wall ring opening in the molding compound101, forming a patterned photoresist mask with defined mask openings corresponding to the desired ring pattern, electroplating one or more conformal conductive layers in the mask opening, stripping the patterned photoresist mask, and then etching the exposed seed layer from the surface of the molding compound101to define the patterned wall ring103which has an open interior space and which is positioned around the periphery of the intended wave guide region14. Having formed the conductive vias102by etching vias and filling the vias with conductive material, the conductive vias102each extend from a first (bottom) side of the molding compound101to a second (top) side of the molding compound101, thereby defining a first waveguide interface perimeter surrounding a first waveguide interface interior. The patterned wall ring103is also formed on the upper surface of the molding compound101in alignment with the conductive vias102to further define the first waveguide interface perimeter surrounding the first waveguide interface interior. InFIG.10B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.10B-FIG.10B) at the intended die region13and waveguide region14, and while there are no patterned conductive vias41D positioned in alignment with the underlying waveguide lines51B, the positions of the next adjacent patterned conductive vias41D at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. As disclosed herein, the conductive vias102may be formed by depositing and curing the molding compound101, etching vias in the molding compound, and then filling the vias with conductive materials. However, this this is just one example technique. In other embodiments, the conductive vias102can be formed by arranging pre-formed conductive studs on the glass/ceramic carrier and then covering the conductive studs with molding compound. In such embodiments, the conductive studs would typically be placed on the glass/ceramic carrier concurrently with the placement of the die72, either before or after attaching the cavity cap sheet91. Then, the deposited molding compound101would cover both the die72and the conductive studs. Thus, this technique can simplify the formation of the conductive vias102that are used to define the waveguide interface perimeter. In other embodiments, the conductive vias102can be formed with a conductive ring. In this embodiment, the conductive ring would typically be placed on the glass/ceramic carrier concurrently with the placement of die. Then, the deposited molding compound would cover both the die72and the ring. Turning now toFIGS.11A-C, a top view110A and cross-sectional side view110B (through lineFIG.11B/C-FIG.11B/C ofFIG.11A) are illustrated of a top glass/ceramic carrier111-115along with a cross-sectional side view110C of the encapsulated glass/ceramic carrier116shown inFIGS.10A-Bafter attaching the top glass/ceramic carrier111-115in accordance with selected embodiments of the present disclosure. As disclosed herein, any suitable ceramic build process can be used to form the top glass/ceramic carrier111-115. For example, an initial glass wafer111may be provided as a high-k dielectric wafer of “photo-structurable glass” (e.g., an APEX® Glass wafer) which contains special sensitizers that allow unique anisotropic 3D features to be formed through a simple exposure step. Using standard IC processing tools such as described above with reference toFIG.8, patterned conductive wall rings113,115are formed on the first and second carrier substrate surfaces of the top glass/ceramic carrier111along with conductive vias114formed in the top glass/ceramic carrier111to electrically connect the patterned conductive wall rings113,115. In addition, a patterned ceramic layer112is formed on a first carrier substrate surface to provide a waveguide region in the top glass/ceramic carrier111. As formed, the patterned conductive wall rings113,115and conductive vias114may be positioned around the periphery of an intended waveguide region except for any location which will overlap with a subsequently-formed differential pair to waveguide launcher in package (LIP) structure. In addition, the second patterned ceramic region(s)112is positioned to encompass and include the intended waveguide region and to extend into the intended die region. However, there is no requirement to form a die cavity in the top glass/ceramic carrier111since the encapsulated glass/ceramic carrier116has a planar top surface on the molding compound101. As formed, the second patterned ceramic region(s)112may extend completely through the top glass carrier wafer111as a single continuous layer. Alternatively, an optional solid thin layer of glass (not shown) may be defined on the topmost or first carrier substrate surface of the top glass/ceramic carrier111. For example, by controlling the timing and/or temperature of the baking process used to convert the exposed portion of the top glass carrier wafer111into the patterned ceramic region(s)112, a remnant layer of un-converted glass may be formed on the topmost or first carrier substrate surface of the top glass/ceramic carrier111. Turning now toFIG.11C, a cross-sectional side view110C is illustrated of the top glass/ceramic carrier111-115being mounted or attached to the encapsulated glass/ceramic carrier116to form a packaged semiconductor device in accordance with selected embodiments of the present disclosure. In the depicted example, the top glass/ceramic carrier111-115assembly is affixed to the encapsulated glass/ceramic carrier116using suitable attachment mechanisms, such as an adhesive or bonding layer, a compression mounting technique, or other lamination processes. When attached together, the second or bottom carrier substrate surface of the top glass/ceramic carrier111-115is attached to the RDL layers51,53formed on the first or top carrier substrate surface of the encapsulated glass/ceramic carrier116. In addition, the patterned conductive features113-115in the top glass/ceramic carrier111-115are aligned for electrical connection to the waveguide ring layer51D formed on the first or top carrier substrate surface of the encapsulated glass/ceramic carrier116, thereby forming a waveguide interface perimeter that surrounds the patterned ceramic layer112, radiating element51C, and air cavity61. InFIG.11B, it is noted that the patterned conductive vias41A-D,102are depicted at the intersection with the through line (FIG.11B-FIG.11B) at the intended die region and waveguide region, and while there are no patterned conductive vias41D,102in alignment with the underlying waveguide lines51B, the positions of the next adjacent patterned conductive vias41D,102at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. After attaching the top and bottom glass/ceramic carriers, the resulting packaged semiconductor device may be mounted to and external waveguide structure using an array of conductors. For example, a conductive ball grid array (BGA) may be affixed or attached to the first or top carrier substrate surface of the top glass/ceramic carrier. When making such a coupling, the conductive BGA can be arranged to follow the perimeter of the waveguide interface interior in alignment with the conductive wall ring115. Such use of a conductive BGA can effectively extend the circuit waveguide interface outside the packaged semiconductor device to connect to a circuit board interface. Turning now toFIGS.12A and12B, a top view120A and cross-sectional side view120B (through lineFIG.12B-FIG.12BofFIG.12A) are illustrated of the top and bottom glass/ceramic carriers being attached to form a packaged semiconductor device with an external waveguide123attached to the to the top glass/ceramic carrier111-115at a stage of a package fabrication process afterFIG.11. While any suitable package terminations or connections may be attached to the packaged mold compound111, selected embodiments of the present disclosure may be implemented by adding electrical leads to the package. For example, a ball grid array (BGA)121or other leads can be attached to the patterned wall ring103around the perimeter of the circuit waveguide interface for use in connecting the circuit waveguide interface to a waveguide or other element. Specifically, a ball grid array (BGA) of balls121is shown attached to the patterned wall ring103on the top surface of the mold compound111. In general, the conductor balls121are coupled to the patterned wall ring103to overlap and follow the perimeter of the circuit waveguide interface that surrounds the first waveguide interface interior, thereby extending the circuit waveguide interface to outside the molding compound111for use in coupling the circuit waveguide interface to an external waveguide123. Though not required, an additional structural layer122is shown as being formed on the mold compound111with a non-conductive material to surround the BGA121(underfill) and to enable stable attachment of an external waveguide123. In accordance with selected embodiments of the present disclosure, the external waveguide123may be formed with an external waveguide metal layer123that is formed in a ring or cylinder to define and surround an external waveguide opening124. In addition or in the alternative, the external waveguide123may be formed or attached with solder material by using a reflow process. InFIG.12B, it is noted that the patterned conductive vias41A-D,102are depicted at the intersection with the through line (FIG.12B-FIG.12B) at the intended die region and waveguide region, and while there are no patterned conductive vias41D,102in alignment with the underlying waveguide lines51B, the positions of the next adjacent patterned conductive vias41D,102at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. Turning now toFIGS.12A and12B, a top view120A and cross-sectional side view120B (through lineFIG.12B-FIG.12BofFIG.12A) are illustrated of a glass/ceramic wafer11and mold compound91with a conformal electromagnetic isolation (EMI) gasket ring121at a stage of a package fabrication process afterFIG.10. Formed to provide an attachment mechanism for an external waveguide, the conformal EMI gasket ring121may be implemented as a thin layer of conductive material that is bonded onto the molding compound91at the waveguide interface location to make electrical contact with the patterned wall ring102. In such embodiments, the conformal EMI gasket ring121may be attached using compression to maintain contact with mating surfaces of the patterned wall ring102. In addition, the conformal EMI gasket ring121may be formed with metallic or metal-coated particles in EMI silicones that conduct electricity to/from the patterned wall ring102. In other embodiments, the conformal EMI gasket ring121may be implemented as a 3D printed EMI O-ring formed with a conductive silicone to provide conductive contact between interfaces under compression. In such embodiments, the EMI O-ring “bounces back” when the force is removed. In general, the conformal EMI gasket ring121is coupled to the patterned wall ring102to overlap and follow the perimeter of the circuit waveguide interface that surrounds the first waveguide interface interior, thereby extending the circuit waveguide interface to outside the molding compound91for use in coupling the circuit waveguide interface to an external waveguide. As illustrated, the conformal EMI gasket ring121is formed in a ring or cylinder to define and surround an external waveguide opening122. InFIG.12B, it is noted that the patterned conductive vias41A-D,101are depicted at the intersection with the through line (FIG.12B-FIG.12B) at the intended die region13, and while there are no patterned conductive vias41D,101in alignment with the underlying waveguide lines51B, the positions of the next adjacent patterned conductive vias41D,101at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity. To further illustrate selected embodiments of the present disclosure, reference is now made toFIG.13which is a simplified flow chart130illustrating an example fabrication method for forming a packaged semiconductor device. In describing the fabrication methodology, the description is intended merely to facilitate understanding of various exemplary embodiments and not by way of limitation. Unless otherwise indicated, the steps may be provided in any desired order. Since the steps illustrated inFIG.13and described below are provided by way of example only, it will be appreciated that the sequence of illustrated steps may be modified, reduced or augmented in keeping with the alternative embodiments of the disclosure so that the method may include additional steps, omit certain steps, substitute or alter certain steps, or perform certain steps in an order different than that illustrated inFIG.13. Thus, it will be appreciated that the methodology of the present invention may be thought of as performing the identified sequence of steps in the order depicted, though the steps may also be performed in parallel, in a different order, or as independent operations that are combined. Once the methodology starts, a blank glass wafer is exposed with a first mask and baked to form glass/ceramic carrier having a first patterned set of one or more ceramic regions at step131. For example, a blank APEX® glass wafer may be patterned to form ceramic regions by coating, exposing, and developing a layer of photoresist material over the glass wafer to define PR mask openings over areas where the first patterned set of one or more ceramic regions is to be formed. After forming the PR mask with any suitable photoresist pattern process, the masked glass wafer layer may be baked at a suitable temperature to alter the properties of exposed glass wafer to form the first patterned set of one or more ceramic regions which extend through the entire width of the glass/ceramic wafer. At step132, an etch process is applied to remove the first patterned set of one or more ceramic regions from the glass wafer, thereby forming patterned openings that extend through the entire width of the glass wafer. While any suitable etch process may be used, an example process may remove the first patterned set of one or more ceramic regions by using a plasma-based ash process and/or wet etch chemistry which selectively removes the patterned ceramic regions without etching the remaining glass wafer. The resulting patterned openings may be used to form through glass vias (TGV) which provide thermal and/or conductive structures through the glass/ceramic wafer. At step133, the glass/ceramic carrier is exposed with a second mask and baked to form a second patterned set of one or more ceramic regions using any suitable steps, such as coating, exposing, and developing a layer of photoresist material over the glass/ceramic carrier to define PR mask openings over areas where the second patterned set of one or more ceramic regions is to be formed. Subsequently, the masked glass/ceramic carrier may be baked at a suitable temperature to form the second patterned set of one or more ceramic regions which extend through the entire width of the glass/ceramic wafer. By defining the locations of the openings in the second mask, the second patterned set of one or more ceramic regions may be positioned to encompass at least the intended wave guide region, and may also extend into the intended die region. At step134, the patterned openings in the glass/ceramic carrier are filled with conductive material to form patterned conductive vias. In selected embodiments, the patterned openings are plated and filled with a metal, such as copper, to form the patterned conductive vias, and may optionally also be planarized or polished to remove excess metal. So constructed, the filled patterned openings form conductive vias (e.g., vias41inFIGS.4A-B), including a first array of conductors41D that will define a waveguide interface perimeter in the glass/ceramic carrier. At step135, redistribution lines (RDL) layers are formed on the top and bottom of the glass/ceramic carrier, including a differential radiating element extending partway into the intended waveguide area. In selected embodiments, the RDL layers may be formed by depositing, patterning, and etching top and bottom RDL layers top differential radiating element extending partway into a waveguide area. For example, one or more top RDL layers (e.g.,51inFIG.5B) may be formed by sputter depositing a seed layer over the glass/ceramic carrier, forming a patterned photoresist mask with one or more RDL openings which overlap with the patterned conductive vias, electroplating one or more conformal conductive layers in the RDL opening(s), stripping the patterned photoresist mask, and then etching the exposed seed layer from the surface of the glass/ceramic carrier to define the top RDL layers. The resulting top RDL layers may include one or more IC lines which are positioned to overlap with and connect to selected patterned conductive vias. The resulting top RDL layers may also include a separately defined loop layer which includes a pair of parallel waveguide feed lines and a radiating element to connect the pair of parallel waveguide feed lines in a loop. The loop layer is connected as an excitation element that is positioned in the intended waveguide region. In addition, the resulting top RDL layers may include a separately defined outer waveguide ring layer which has an open interior space and which is positioned around the periphery of the intended wave guide region. Thus formed, the waveguide feed lines and radiating element form a differential pair to waveguide launcher in package (LIP) structure on the top glass/ceramic carrier surface which is positioned to extend from the intended die region to the interior location of the intended waveguide region surrounded by the waveguide ring layer while leaving space for a subsequently-formed air cavity. In similar fashion, the resulting bottom RDL layers may be formed by using any suitable process for depositing, patterning, and etching one or more conductive layers on the bottom surface of the glass/ceramic carrier. As formed, the bottom RDL layer(s) may define a waveguide reflector interface layer which is positioned on the bottom carrier substrate surface to overlap with the intended waveguide region. At step136, a solder mask layer is applied to cover the top and bottom glass/ceramic carrier surfaces with an air cavity opening over area in the second patterned ceramic region(s) of the glass/ceramic carrier where the air cavity will be formed. At step137, an air cavity is formed in or on top of the second patterned ceramic regions(s) so as to be positioned adjacent to the differential radiating element and within the intended waveguide region. While any suitable process may be used to form the air cavity, the air cavity may be formed by performing a recess etch of the second patterned ceramic region exposed by the solder mask layer using a timed anisotropic etch to partially etch the second patterned ceramic region. The process parameters and timing of the recess etch process should be controlled to etch a specified depth which leaves a thin layer of the second patterned ceramic region below the air cavity at the bottom glass/ceramic carrier surface, thereby forming a waveguide short back that is defined by the bottom metal plane of the patterned waveguide region. In addition, a patterned mask and etch process may be controlled so that the air cavity is positioned inside the intended waveguide region and adjacent to the differential pair to waveguide LIP structure. At step138, one or more die are attached with their active sides facing the top of the glass/ceramic carrier. While any suitable die attach process may be used, the die may be attached as a flip-chip integrated circuit die to the pattern of conductive bumps or pillars formed on the top surface of the glass/ceramic carrier. Thus, the die may be attached and electrically connected to the top RDL layers forming the IC lines and the parallel waveguide lines using any suitable die attach technique for making electrical connection therebetween. Thus connected, the die may be connected over the waveguide lines to the radiating element to control the differential pair to waveguide launcher in package (LIP) structure on the top glass/ceramic carrier surface. In addition, the die may be attached and electrically connected to control the waveguide ring layer formed on the on the top surface of the glass/ceramic carrier to define the intended waveguide region. With the foregoing steps131-138, the bottom high-k glass carrier is formed with a first ceramic build process to include an integrated differential pair to waveguide launcher in package (LIP) structure and an air cavity structure formed in the waveguide short back. In addition, a second ceramic build process may be used to form a top high dielectric constant glass carrier having a patterned ceramic/glass structure to provide waveguide matching and reduced insertion loss performance. In selected embodiments, the second ceramic build process begins at step139by forming a top glass carrier substrate to include a die cavity positioned for alignment with the attached die on the bottom glass carrier, and to also include a patterned ceramic structure positioned for alignment with an external waveguide interface. For example, an initial glass wafer of high-k dielectric “photo-structurable glass” may be processed using a pattern and bake process to form a patterned ceramic layer in the top glass carrier substrate that is positioned to provide a waveguide region in the top glass carrier substrate. Additional pattern and etch processing steps may also be applied to form recessed die cavity in the top glass/ceramic carrier substrate. In other embodiments, the second ceramic build process begins at step140by attaching a substrate cap sheet to cover the air cavity on the glass wafer, followed by depositing a mold compound to encapsulate the die and substrate cap sheet. In selected embodiments, the substrate cavity cap sheet may be formed with any suitable laminate or non-conductive bonding attachment process for forming a low loss dielectric to reduce the transition loss. For example, a laminate sheet having low dielectric constant and low dielectric loss properties may be attached to cover the air cavity and prevent it from being filled by molding compound material. In depositing the mold compound, selected WSDP processing embodiments may apply the molding compound in a liquid or semi-liquid state to cover the arrangement of attached dies and associated other elements formed on the top glass/ceramic carrier substrate in a protective package. A vacuum may then be applied to the molding compound to extract bubbles that could otherwise create voids in the molding compound. The molding compound would then be cured, and optionally planarized after curing. At step141, conductive vias are formed in the molding compound to define a perimeter of the circuit waveguide interface. As disclosed herein, the conductive vias may be formed by selectively etching via openings in the molding compound using any suitable etch processing, including selective or patterned etching and laser drilling. The via openings are then filled with conductive layers, such as metal, to form the conductive vias to provide a waveguide wall or ring. The waveguide wall or ring may be formed with one or more electroplating layers, diffusion barrier layers, adhesion layers, conductive layers, and the like. In selected embodiments, the conductive vias are formed in the via openings by first depositing conductive liners formed of titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. On the conductive liner layers, conductive layers may be formed with any suitable conductive material, such as copper, a copper alloy, silver, gold, tungsten, aluminum, or the like. In selected embodiments, the conductive layers may be formed by blanket depositing a liner in the via openings, followed by depositing a thin seed layer of copper or copper alloy over the liner, and filling the rest of via openings with metallic material, such as by using electro-plating, electro-less plating, deposition, or the like. A planarization process, such as chemical mechanical planarization (CMP) may then be performed to level the surface of conductive lines and to remove excess conductive materials from the top surface of the mold compound. Subsequently, a masked etch process may be applied to pattern the conductive layers. As constructed, the conductive layers form a perimeter array of conductors around the waveguide interface that will define a waveguide interface perimeter in the molding compound. In addition or in the alternative, the conductive layers may form a conductive ring structure around the waveguide interface that will define a waveguide interface perimeter in the molding compound. At step142, a top glass carrier substrate is formed to include a patterned ceramic structure positioned for alignment with an external waveguide interface, but without a die cavity. For example, an initial glass wafer of high-k dielectric “photo-structurable glass” may be processed using a pattern and bake process to form patterned ceramic layer in the top glass carrier substrate that is positioned to provide a waveguide region in the top glass carrier substrate. At step143, via openings are formed in the top glass carrier substrate to define a perimeter of the circuit waveguide interface. As disclosed herein, the via openings can be formed with any suitable processing, including selective or patterned etching and laser drilling. For example, an initial glass wafer of high-k dielectric “photo-structurable glass” may be processed using pattern and etch processing to form the via openings. At step144, the via openings in the top glass carrier substrate may be filled with one or more conductive layers, such as metal, to form the perimeter of the waveguide interface as a waveguide wall or ring. The waveguide wall or ring may be formed with one or more electroplating layers, diffusion barrier layers, adhesion layers, conductive layers, and the like. In selected embodiments, the conductive layers are formed in the via openings of the top glass carrier substrate by first depositing conductive liners formed of titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. On the conductive liner layers, conductive layers may be formed with any suitable conductive material, such as copper, a copper alloy, silver, gold, tungsten, aluminum, or the like. In selected embodiments, the conductive layers may be formed by blanket depositing a liner in the via openings, followed by depositing a thin seed layer of copper or copper alloy over the liner, and filling the rest of via openings with metallic material, such as by using electro-plating, electro-less plating, deposition, or the like. A planarization process, such as chemical mechanical planarization (CMP) may then be performed to level the surface of conductive lines and to remove excess conductive materials from the top surface of the top glass carrier substrate. Subsequently, a masked etch process may be applied to pattern the conductive layers. As constructed, the conductive layers form a perimeter array of conductors around the waveguide interface that will define a waveguide interface perimeter in the top glass carrier substrate. In addition or in the alternative, the conductive layers may form a conductive ring structure around the waveguide interface that will define a waveguide interface perimeter in the top glass carrier substrate. At step145, the top glass/ceramic carrier substrate is affixed or mounted to the glass wafer in alignment with the attached die and waveguide area. As will be appreciated, the top glass/ceramic carrier substrate may be affixed to the bottom glass/ceramic wafer using any suitable attachment mechanisms, such as an adhesive or bonding layer, a compression mounting technique, or other lamination processes. When attached together, the bottom surface of the top glass/ceramic carrier is attached to the top surface of the glass wafer with the waveguide wall/ring in the top glass/ceramic carrier substrate aligned for electrical connection to the conductive vias formed in the mold compound and/or the patterned conducive vias formed in the glass wafer, thereby forming a waveguide interface perimeter that surrounds the patterned ceramic layer, radiating element, and air cavity. At step146, an external waveguide is attached with package terminations or connections to the waveguide wall or ring formed in the top glass/ceramic carrier substrate of the packaged semiconductor device. In selected embodiments, a ball grid array (BGA) or other leads can be attached to the waveguide wall or ring formed in the top glass/ceramic carrier substrate around the perimeter of the waveguide interface. In other embodiments, a conformal conductive attachment ring can be attached to the waveguide wall or ring formed in the top glass/ceramic carrier substrate around the perimeter of the waveguide interface. These package terminations around the perimeter of the circuit waveguide interface effectively extend the circuit waveguide interface outside the package, and thus can be used to connect the circuit waveguide interface to a waveguide or other element. At step147, one or more additional backend of line (BEOL) and/or package processing steps are performed on the packaged semiconductor device. In selected embodiments, the processing at step147includes processing and singulating the packaged semiconductor device, molded compound, dies, and circuit waveguide interfaces into individual molded packages. This would typically be accomplished using a suitable sawing or scribing technique. So constructed, each package could include one or more IC dies and one or more associated circuit waveguide interfaces. After completion of the BEOL and/or package processing steps, the fabrication method ends. The fabrication method130illustrates an example technique that facilitates the formation of a circuit waveguide interface during a WSDP process that is used to package a semiconductor device. The use of the WSDP process can allow the integration of a radiating element having short feed line with an adjacent air cavity formed in the high-k glass/ceramic carrier to address millimeter design challenges and to maximize the performance enhancement by providing an air cavity structure in waveguide short back that is designed to provide electrical matching and to reduce insertion loss to lower than 1.0 dB. Additionally, the use of the WSDP process can allow the formation of a packaged die and circuit waveguide interface with relatively little cost and process complexity (e.g., without requiring additional machining of the waveguide interface or an external waveguide adapter). And by forming a high-k top glass/ceramic carrier substrate with a waveguide wall or ring formed around the perimeter of a ceramic layer, the resulting waveguide interface provides improved waveguide matching and reduced insertion loss performance. Examples of embodiments and applications for the waveguide interface include millimeter wave (mmW) and radio frequency (RF) applications. The embodiments described herein can provide circuit waveguide interfaces for semiconductor devices with both relatively high performance and low cost. In general, the embodiments described herein provide a differential pair to waveguide exciting element with a short feed line formed on the glass/ceramic carrier to connect to the attached die, thereby significantly reducing insertion loss. And by forming the waveguide interface with a high-k ceramic region of a glass/ceramic carrier which includes an air cavity that is adjacent to the waveguide exciting element, high frequency performance is improved for millimeter wave and radio frequency applications. Specifically, during the packaging process, photolithography and other wafer-type processing techniques are used to form one or more metallization layers (e.g., copper) in a wafer-like glass/ceramic panel, including a radiating element that is connected over a short feed line to a die attach area and a surrounding conductive via/ring pattern at the periphery of a circuit waveguide region. Subsequently, singulated die are arranged and attached on the wafer-like glass/ceramic panel, either before or after forming a partially recessed air cavity adjacent to the radiating element in the circuit waveguide region. After covering air cavity with a laminate sheet, a molding compound may be injected or deposited over the die and radiating element to form an encapsulating package. In addition, a high-k top glass/ceramic carrier substrate having a waveguide wall or ring formed around the perimeter of a ceramic layer is attached to the molding compound to provide improved waveguide matching. A circuit waveguide interface is formed in the encapsulating package and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization. By now it should be appreciated that there has been provided a method for making a package assembly, such as a wafer-scale die packaging device (WSDP) device. In the disclosed method, a first high-k dielectric glass carrier substrate is provided. In selected embodiments, the first high-k dielectric glass carrier substrate is provided as a glass wafer formed with a material having a dielectric constant k of at least approximately k=5.8. The disclosed method also includes forming a first ceramic region in the first high-k dielectric glass carrier substrate which includes a defined waveguide area and which extends to a defined die attach area. In addition, the disclosed method includes forming a plurality of conductive patterns on a first surface of the first high-k dielectric glass carrier substrate. The conductive patterns include a differential waveguide launcher disposed over the first ceramic region and formed with a radiating element connected to a pair of signal lines extending from the defined waveguide area to the defined die attach area. In addition, conductive patterns include a patterned array of one or more conductors disposed over the first ceramic region in a waveguide conductor ring positioned in the defined waveguide area to surround the radiating element on at least three sides. In selected embodiments, the conductive patterns may be formed by electroplating one or more conformal conductive layers over the first surface of the first high-k dielectric glass carrier substrate, and then selectively etching the one or more conformal conductive layers to form the differential waveguide launcher and the patterned array of one or more conductors as coplanar layers on the first surface of the first high-k dielectric glass carrier substrate. The disclosed method also includes forming an air cavity in the first ceramic region that is positioned in the defined waveguide area to be adjacent to the radiating element and surrounded on at least three sides by the patterned array of one or more conductors. In addition, the disclosed method includes attaching a semiconductor die to the first high-k dielectric glass carrier substrate at the defined die attach area to make electrical connection to the differential waveguide launcher. The disclosed method also includes providing a second high-k dielectric glass carrier substrate having a top surface and a bottom surface. As disclosed, the second high-k dielectric glass carrier substrate includes a second ceramic region in a defined waveguide area surrounded by a waveguide interface perimeter of one or more conductors that are positioned for alignment with the patterned array of one or more conductors. In selected embodiments, the second high-k dielectric glass carrier substrate is provided by exposing the second high-k dielectric glass carrier substrate to a mask pattern having a mask opening over at least the defined waveguide area, and then baking the second high-k dielectric glass carrier substrate to convert the second high-k dielectric glass carrier substrate exposed by the mask opening to the second ceramic region which extends from the bottom surface to the top surface the second high-k dielectric glass carrier substrate. In other embodiments, the second high-k dielectric glass carrier substrate is provided by exposing the second high-k dielectric glass carrier substrate to a mask pattern having a mask opening over at least the defined waveguide area, and then baking the second high-k dielectric glass carrier substrate to convert the second high-k dielectric glass carrier substrate exposed by the mask opening to the second ceramic region which extends from the bottom surface while leaving a thin layer of glass at the top surface the second high-k dielectric glass carrier substrate. In other embodiments, the second high-k dielectric glass carrier substrate is provided by patterning and etching a bottom surface of the second high-k dielectric glass carrier substrate to form a die cavity positioned for alignment with the semiconductor die attached to the first high-k dielectric glass carrier substrate. In addition, the disclosed method includes mounting the second high-k dielectric glass carrier substrate to the first high-k dielectric glass carrier substrate by affixing the bottom surface of the second high-k dielectric glass carrier substrate to the plurality of conductive patterns on the first surface of the first high-k dielectric glass carrier substrate so that the first ceramic region in the first high-k dielectric glass carrier substrate is aligned with the second ceramic region in the defined waveguide area. In selected embodiments, the disclosed method may also include forming a molding compound over the first high-k dielectric glass carrier substrate that covers the semiconductor die and the plurality of conductive patterns, the molding compound having a first side attached to the first high-k dielectric glass carrier substrate and a second side opposite the first side. In the molding compound, a first array of conductors is formed that are positioned for alignment with the plurality of conductive patterns. As formed, the first array of conductors extend from the molding compound first side to the molding compound second side. In addition, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior. In selected embodiments, the second high-k dielectric glass carrier substrate is provided by exposing the second high-k dielectric glass carrier substrate to a mask pattern on the bottom surface having a mask opening over at least the defined waveguide area; baking the second high-k dielectric glass carrier substrate to convert the second high-k dielectric glass carrier substrate exposed by the mask opening to the second ceramic region; and forming the one or more conductors in the second high-k dielectric glass carrier substrate to surround the second ceramic region at the waveguide interface perimeter, the one or more conductors being positioned for alignment with the patterned array of one or more conductors in the first high-k dielectric glass carrier substrate. In another form, there is provided a wafer-scale packaged semiconductor device and associated method of manufacture. The disclosed semiconductor package device includes a bottom carrier device attached to a top carrier device. The bottom carrier device includes a first high-k glass substrate layer surrounding a first patterned ceramic layer in which a first waveguide region is located; a semiconductor die attached to a top surface of the first high-k glass substrate layer over a die region; and a first array of conductors formed on a top surface of the first patterned ceramic layer to define a waveguide ring positioned to substantially surround the first waveguide region and to define a separate excitation element positioned to extend from the die region to a first interior side of the first waveguide region to be substantially surrounded by the waveguide ring. In selected embodiments, the separate excitation element is a differential pair to waveguide launcher in package structure which may include one or more waveguide feed lines positioned to extend from the die region to the first interior side of the first waveguide region, and a radiating element connected to the one or more waveguide feed lines and positioned on the first interior side of the first waveguide region to be substantially surrounded by the separate waveguide ring. In selected embodiments, the bottom carrier device may also include a molding compound formed over the first high-k dielectric glass substrate layer and first patterned ceramic layer to cover the semiconductor die and the first array of conductors, with a first side of the molding compound attached to the first high-k glass substrate layer and with a second side opposite the first side. In the molding compound, a second array of conductors is formed and positioned for alignment with the waveguide ring so that the second array of conductors extend from the first side of the molding compound to the second side of the molding compound, thereby defining a first waveguide interface perimeter surrounding a first waveguide interface interior. In selected embodiments, the bottom carrier device may also include an air cavity formed at the top surface of the first patterned ceramic layer and positioned in the first waveguide region to be adjacent to the separate excitation element and surrounded on at least three sides by the waveguide ring. In such embodiments, the air cavity may be sized and positioned in the first high-k glass substrate layer to provide electrical matching for an external waveguide and to reduce insertion loss to 1.0 dB or lower. The top carrier device includes a second high-k glass substrate layer surrounding a second patterned ceramic layer in which a second waveguide region is located and surrounded by a waveguide interface perimeter of one or more conductors that are positioned for alignment with the waveguide ring. In selected embodiments, the top carrier device may include a thin glass layer formed on top of the second patterned ceramic layer. In selected embodiments, the first and second high-k dielectric glass substrate layers are each formed with a material having a dielectric constant k of at least approximately k=5.8. In addition, the top carrier device may include a die cavity formed in a bottom surface of the second high-k glass substrate layer and positioned for fitted alignment with the semiconductor die when the bottom carrier device is attached to the top carrier device. The disclosed semiconductor package device also includes an adhesive or bonding layer which attaches the bottom carrier device to the top carrier device with the first waveguide region formed in the first patterned ceramic layer of the bottom carrier device aligned with the second waveguide region formed in the second patterned ceramic layer of the top carrier device. In selected embodiments, the disclosed semiconductor package device may also include an array of conductive balls attached to the waveguide interface perimeter of one or more conductors at a top surface of the top carrier device, and an external waveguide physically coupled to the array of conductive balls. In selected embodiments, the disclosed semiconductor package device may also include a conductive layer formed at a bottom surface of the first high-k glass substrate layer to define a waveguide reflector interface layer. In yet another form, there is provided a method for making a packaged semiconductor device, such as a wafer-scale die packaging device (W SDP) device. The disclosed method includes providing a first high-k dielectric carrier substrate comprising a first glass layer surrounding a first patterned ceramic layer in which a first millimeter waveguide region is located. In selected embodiments, the first high-k dielectric carrier substrate may be provided by providing the first glass layer as a photo-structurable glass substrate; exposing the photo-structurable glass substrate to a mask pattern having a mask opening over at least the first millimeter waveguide region; and baking the photo-structurable glass substrate to convert a portion of the photo-structurable glass substrate exposed by the mask opening to the first patterned ceramic layer which extends from a bottom surface while leaving a thin layer of glass at the top surface the first high-k dielectric carrier substrate. The disclosed method also includes forming a first array of conductors in the first high-k dielectric carrier substrate to define a conductive first waveguide interface perimeter that is positioned to substantially surround the first millimeter waveguide region. In this way, the top carrier device is formed from the first high-k dielectric carrier substrate and the first array of conductors. In addition, the disclosed method includes providing a bottom carrier device having a second high-k dielectric carrier substrate in which a second glass layer surrounds a second patterned ceramic layer in which a second millimeter waveguide region is located. As provided, the bottom carrier device includes a semiconductor die attached to a top surface of the second high-k dielectric carrier substrate over a die region, and also includes a second array of conductors formed on a top surface of the second patterned ceramic layer to define a waveguide ring positioned to substantially surround the second millimeter waveguide region and a separate excitation element positioned to extend from the die region to a first interior side of the second millimeter waveguide region to be substantially surrounded by the waveguide ring. The disclosed method also includes positioning the top carrier device and the bottom carrier device in alignment so that the first millimeter waveguide region formed in the first patterned ceramic layer of the top carrier device is aligned with the second millimeter waveguide region formed in the second patterned ceramic layer of the bottom carrier device. Finally, the disclosed method includes attaching the bottom carrier device to the top carrier device by applying an adhesive or bonding layer to the bottom carrier device and/or top carrier device, thereby forming the wafer-scale die packaging device. While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the present disclosure, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents. The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description. The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first,” “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context. The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematics shown in the figures depict several exemplary arrangements of elements, additional intervening elements, devices, features, or components may be present in other embodiments of the depicted subject matter. While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. | 80,295 |
11862585 | Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION The following disclosure provides for many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation or disposal of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features are formed or disposed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Due to the demand for electronic devices with high performance and multifunction, a semiconductor package substrate is required to have larger surface area and more complicated electrical circuitry to install more semiconductor devices. The size of the semiconductor substrate becomes larger while the yield decreases. Partitioned substrates, which collectively provide a complete circuit function as a single semiconductor package substrate, are smaller in size and easier to produce than the semiconductor package substrate, and therefore, they may be used to replace a large-size semiconductor package substrate in many applications. FIG.1is a cross-sectional view of a semiconductor package structure1in accordance with some embodiments of the present disclosure. The semiconductor package structure1includes a first substrate11and a second substrate12. The first substrate11and the second substrate12may be partitioned substrates each of which includes circuit with incomplete function. The first substrate11has a first surface11aand a second surface11bopposite to the first surface11a. The second substrate12has a first surface12aand a second surface12bopposite to the first surface12a. The first surface11aand12amay be electrically connected a semiconductor chip or die and thus may be referred to as “chip side” or “chip-side surface.” The second surface11band12bmay be electrically connected a solder ball or bump and thus may be referred to as “ball side” or “ball-side surface.” The first surface11amay include conductive traces having an L/S less than an L/S of the conductive traces of the second surface11b. The first surface12amay include conductive traces having an L/S less than an L/S of the conductive traces of the second surface12b. Though not shown inFIG.1, the first substrate11and the second substrate12may have one or more embedded circuit layers112and/or conductive vias111as illustrated inFIG.2. In the manufacture process of the semiconductor package structure1, the first substrate11and the second substrate12may be disposed on a carrier10. The carrier10may be removed after the manufacture of the semiconductor package structure1. The first surface11aof the first substrate11and the first surface12aof the second substrate12face away the carrier10. An encapsulant50is disposed on the carrier10and covers the first surface11aof the first substrate11and the first surface12aof the second substrate12. A conductive layer15, which may include pads and/or conductive traces, is disposed on the encapsulant50and may be electrically connected to a semiconductor chip or die (not shown). Conductive pillars14are disposed within the encapsulant50to electrically connect the first substrate11and the second substrate12to the conductive layer15. The first substrate11and the second substrate12may be electrically connected to each other through the conductive pillars14and the conductive layer15to provide a complete circuit function as required. However, the position of the first substrate11and the second substrate12may be shifted during the filling of a molding compound for preparing the encapsulant50, and therefore, the conductive pillars14may not be precisely connected to the first surfaces11aand12a. In addition, the ball pads (not shown) on the second surfaces11band12bmay not be precisely connected to a printed circuit board (PCB). In addition, tall conductive pillars increases the length of electrical path and the electrical performance of the semiconductor package structure1may be deteriorated. The present disclosure provides a semiconductor package structure including two or more substrates disposed side-by-side. The substrates may be partitioned substrates and are electrically connected to each other through a pad layer without the use of conductive pillars. As compared to the embodiments in accordance withFIG.1, since it is unnecessary to form conductive pillars, a distance of two adjacent substrates can be reduced. In some embodiments (especially those illustrated inFIG.2,FIG.3,FIG.4,FIG.5andFIG.6), the pad layer is pre-formed on a carrier and the pads of the pad layer function as alignment marks so the substrates can be disposed on the pad layer precisely. In some embodiments, the semiconductor package structure includes a conductive bonding layer or structure which is helpful to fix the position of the substrates, and therefore, the position shift of the substrates due to the filling of an encapsulant can be further improved. FIG.2is a cross-sectional view of a semiconductor package structure2in accordance with some embodiments of the present disclosure. The semiconductor package structure2includes a first substrate11, a second substrate12and a pad layer20. The second substrate12is disposed side-by-side with the first substrate11on a carrier10. The carrier may be removed after the manufacture of the semiconductor package structure2. The first substrate11and the second substrate12may be partitioned substrates each of which includes circuit with incomplete function. The first substrate11has a first surface11aand a second surface11bopposite to the first surface11a. The second substrate12has a first surface12aand a second surface12bopposite to the first surface12a. The first surface11aand12amay be electrically connected a semiconductor chip or die and thus may be referred to as “chip side” or “chip-side surface.” The second surface11band12bmay be electrically connected a solder ball or bump and thus may be referred to as “ball side” or “ball-side surface.” The first surface11amay include conductive traces having an L/S less than an L/S of the conductive traces of the second surface11b. The first surface12amay include conductive traces having an L/S less than an L/S of the conductive traces of the second surface12b. The first substrate11and the second substrate12may have one or more embedded circuit layers112, conductive vias (e.g., through vias111), pads or contacts. The circuit layers, conductive vias, pads or contacts may be made of nickel, copper, gold, platinum or other suitable metal or alloy. The pad layer20includes a plurality of pads and is disposed on the second surface11bof the first substrate11and the second surface12bof the second substrate12. A conductive bonding layer or structure30is disposed between the pad layer20and the second surface11bof the first substrate11and the second surface12bof the second substrate12. In some embodiments, the conductive bonding layer or structure30is in contact with the pad layer20, the first substrate11and the second substrate12, and more specifically, the conductive bonding layer or structure30is in direct contact with the pad layer20and the second surfaces11band12bof the first substrate11and the second substrate12. In some embodiments, the pad layer20is bonded and electrically connected to the second surface11bof the first substrate11and the second surface12bof the second substrate12through the conductive bonding layer or structure30. The first substrate11and the second substrate12may be electrically connected to each other through the pad layer20and the conductive bonding layer or structure30to provide a complete circuit function as required. The pad layer20may be made of nickel, copper, gold, platinum or other suitable metal or alloy. The conductive bonding layer or structure30may be, or include, a solder. The conductive bonding layer or structure30may be formed by applying a solder paste or solder material on the pads of the pad layer20. During the reflow process, self-alignment of the solder paste or solder material occurs, and therefore, the alignment of the substrates to the pad layer can be further improved. The semiconductor package structure1may further include an encapsulant50. The encapsulant50encloses or covers the first substrate11, the second substrate12and the pad layer20. In some embodiments, the first surface11aof the first substrate11and the first surface12aof the second substrate12may be exposed from a surface50aof the encapsulant50and electrically connected to a semiconductor die or chip (not shown). In some embodiments, the pads of the pad layer20may be exposed from a surface of the encapsulant50opposite to the surface50aand electrically connected to a PCB. FIG.3is a cross-sectional view of a semiconductor package structure3in accordance with some embodiments of the present disclosure. The semiconductor package structure3has a similar structure to that of the semiconductor package structure2ofFIG.2except the conductive bonding layer or structure. In the embodiments illustrated inFIG.3, the conductive bonding layer or structure31may be or include an anisotropic conductive film (ACF), an anisotropic conductive adhesive (ACA) or an anisotropic conductive paste (ACP) which provides unidirectional electrical conductivity in the vertical direction and insulation in the horizontal direction via conductive particles311. FIG.4is a cross-sectional view of a semiconductor package structure4in accordance with some embodiments of the present disclosure. The semiconductor package structure4has a similar structure to that of the semiconductor package structure2ofFIG.2except the conductive bonding layer or structure. In the embodiments illustrated inFIG.4, the conductive bonding layer or structure may be a metal layer or an intermetallic layer40or the conductive bonding layer or structure may include a part of the pad layer. In the manufacture process of the semiconductor package structure4, the first substrate11and the second substrate12is disposed on the pad layer20and the conductive vias111(or pads or electrical contacts) of the first substrate11and the second substrate12are in direct contact with the pad layer20. The pad layer20and the conductive vias111(or pads or electrical contacts) of the first substrate11and the second substrate12may be made of the same material or different material. In some embodiments, for example, those illustrated inFIG.4, the pad layer20and the conductive vias111(or pads or electrical contacts) of the first substrate11and the second substrate12form a metal layer or an intermetallic layer or at a contact surface (i.e., interface) therebetween. The metal layer or intermetallic layer40may result from, for example, the reaction occurring at the interface or the migration of atoms from the pad layer20and/or the conductive vias111. The metal layer or intermetallic layer40enhances the adhesion of the pad layer and the conductive vias (or pads or electrical contacts) of the first and second substrate. In some embodiments, there is no visible intermetallic layer or metal layer at the contact surface and the pad layer is directly bonded to the conductive vias (or pads or electrical contacts) without additional bonding material including a solder, an ACF, an ACA or ACP. In these embodiments, the pad layer per se functions as a conductive bonding layer, or a part of the pad layer which is adjacent to the contact surface between the pad layer and the conductive vias (or pads or electrical contacts) of the first and second substrates may be viewed as a conductive bonding layer. The bonding of the pad layer to the conductive vias (or pads or electrical contacts) may be implemented by metal-to-metal bonding techniques. In some embodiments, the pad layer and the conductive vias (or pads or electrical contacts) are made of copper and Cu-to-Cu bonding technique are adopted to bond the pad layer to the conductive vias (or pads or electrical contacts). As illustrated inFIG.4, the plurality of pads the pad layer20includes a pad205in contact with the second surfaces11band12bof the first substrate11and the second substrate12, and therefore, the first substrate11can be electrically connected to the second substrate12through the pad layer20. FIG.5is a cross-sectional view of a semiconductor package structure5in accordance with some embodiments of the present disclosure. The semiconductor package structure5has a similar structure to that of the semiconductor package structure4ofFIG.4except that the pad layer20of the semiconductor package structure5does not include a pad connecting both of the second surfaces11band12b. In the embodiments illustrated inFIG.5, the plurality of the pads of the pad layer20includes a first pad201in direct contact with the second surface11bof the first substrate11and a second pad202in direct contact with the second surface12bof the second substrate12. The pad layer20may further include a third pad203. The semiconductor package structure may include one or more wires41. The first pad201and the second pad202may be connected to each other through the wire41, and therefore, the first substrate11can be electrically connected to the second substrate12through the pad layer20and the wire41. In some embodiments, the first pad201and the second pad202may be electrically connected to each other via a single wire. In some embodiments, the first pad201and the second pad202may be electrically connected to each other by two or more wires, for example, by a wire connecting to the first pad201and the third pad203and a wire connecting to the second pad202and the third pad203. In some other embodiments, the first pad201and the second pad202may be electrically connected to each other by conductive traces of the pad layer20instead of the wire41. FIG.6is a cross-sectional view of a semiconductor package structure6in accordance with some embodiments of the present disclosure. The semiconductor package structure6includes a first substrate11, a second substrate12and a pad layer20. The second substrate12is disposed side-by-side with the first substrate11on a carrier10. The carrier may be removed after the manufacture of the semiconductor package structure2. The pad layer20is disposed on the second surface11bof the first substrate11and the second surface12bof the second substrate12. The pad layer20is electrically connected to the first substrate11and the second substrate20. As showed inFIG.6, a lateral surface of the first substrate11includes a vertical recess extending from the first surface11ato the second surface11band a lateral surface of the first substrate12includes a vertical recess extending from the first surface12ato the second surface12b. A solder is filled within the vertical recess. In some embodiments, a solder in a vertical recess of the first substrate11can be combined with another solder in a vertical recess of the second substrate12adjacent to the vertical recess of the first substrate11and forms a conductive bonding structure32. The conductive bonding structure32is in contact with the pad layer20, the first substrate11and the second substrate12and can enhance the adhesion therebetween. As a result, the position of the first substrate and the second substrate can be further secured. Other details of the first substrate11and second substrate12have been discussed above with respect to the embodiments illustrated inFIG.2. The semiconductor package structure6may further include an encapsulant50. The encapsulant50encloses or covers the first substrate11, the second substrate12and the pad layer20. In some embodiments, the first surface11aof the first substrate11aand the first surface12aof the second substrate12may be exposed from a surface50aof the encapsulant50and electrically connected to a semiconductor die or chip (not shown). In some embodiments, the pads of the pad layer20may be exposed from a surface opposite to the surface50aof the encapsulant50and electrically connected to a PCB. FIG.7is a cross-sectional view of a semiconductor package structure7in accordance with some embodiments of the present disclosure. The semiconductor package structure7has a similar structure to that of the semiconductor package structure6ofFIG.6except that the pad layer21of the semiconductor package structure7is disposed on the first surfaces11aand12aof the first substrate11and the second substrate12. FIG.8is a cross-sectional view of a semiconductor package structure8in accordance with some embodiments of the present disclosure. In addition to the first substrate11, the second substrate12, the pad layer20and the encapsulant50which have been discussed above, the semiconductor package structure8further includes a redistribution layer (RDL) structure61, one or more electronic devices70and71, and a plurality of solder balls60. The RDL structure61is disposed on the first surface11aof the first substrate11and the first surface12aof the second substrate12. The RDL structure61may include one or more redistribution layers and insulation material(s) or dielectric material(s) encapsulating the one or more redistribution layers. The RDL structure61may include conductive trace(s), pad(s), contact(s) and/or via(s) for electrical connection. The electronic devices70and71are disposed on the RDL structure61and electrically connected to the first substrate11or the second substrate12through the RDL structure61. A further encapsulant51is provided to encapsulate or cover the electronic devices70and71and the RDL structure61. FIG.9A,FIG.9B,FIG.9C,FIG.9DandFIG.9Eillustrate various stages of a method for manufacturing a semiconductor package structure2in accordance with some embodiments of the present disclosure. Referring toFIG.9A, a carrier10is provided. A patterned metal layer is formed on the carrier10. The patterned metal layer20includes a plurality of pads. In some embodiments, the patterned metal layer20is an redistribution layer (RDL) which includes conductive traces and a plurality of pads. The patterned metal layer20is referred to as a pad layer in the embodiments of the present disclosure. Referring toFIG.9B, a solder30′ is disposed on the pad layer20and covers a respective pad of the pad layer20. Referring toFIG.9C, a first substrate21and a second substrate22are singulated from one or more mother substrates. In some embodiments, the first substrate21and the second substrate22are partitioned substrates each of which includes circuit with incomplete function. The first substrate11has a first surface11aand a second surface11bopposite to the first surface11a. The second substrate12has a first surface12aand a second surface12bopposite to the first surface12a. The first substrate21and the second substrate22are disposed side-by side on the solder30′. The conductive via111(or the pad or electrical contact) exposed from the second surfaces11band12bof the first substrate11and the second substrate12contacts the solder30′. The pad201of the pad layer20is connected to the first substrate11through the solder30′ located between the pad201and the first substrate11and the pad202of the pad layer20is connected to the second substrate12through the solder30′ located between the pad202and the second substrate12. Since the pad layer20is pre-formed on the carrier10, the pads of the pad layer20function as alignment marks so the first substrate21and the second substrate22can be disposed on the pad layer precisely. Referring toFIG.9D, a reflow process is carried to form a conductive bonding layer30from the solder30′. In addition, since the distance between the pad201and the pad202is relatively small, the solder30′ on the pad201and the solder30′ on the pad202can be melted and combine with each other during the reflow process so that the first substrate11can be electrically connected to the second substrate12through the pad layer20and the conductive bonding layer30. During the reflow process, self-alignment of the solder30′ occurs, and therefore, the alignment of the first substrate21and the second substrate22to the pad layer20can be further improved. Referring toFIG.9E, an encapsulant50is formed on the carrier10and encapsulates the first substrate11and the second substrate12by filling an encapsulant material (e.g., a molding compound). The encapsulant50also encapsulates the pad layer20and the conductive bonding layer30. In this step, since the conductive bonding layer30is formed prior to the filling of the encapsulant material and can effectively fix the position of the first substrate21and the second substrate22, the position shift issue can be further improved. Referring toFIG.9F, the encapsulant50is ground to expose the first surfaces11aand12aof the first substrate11and the second substrate12. FIG.10A,FIG.10B,FIG.10C,FIG.10DandFIG.10Eillustrate various stages of a method for manufacturing a semiconductor package structure3in accordance with some embodiments of the present disclosure. Referring toFIG.10A, a pad layer20is formed on a carrier10as illustrated inFIG.9A. Referring toFIG.10B, a conductive bonding layer31is formed by applying an anisotropic conductive film (ACF), an anisotropic conductive adhesive (ACA) or an anisotropic conductive paste (ACP) on the carrier10. The conductive bonding layer30covers the pad layer20. Referring toFIG.10C, a first substrate21and a second substrate22are disposed side-by-side on the conductive bonding layer31. The first substrate11can be electrically connected to the second substrate12through the pad layer20and the conductive bonding layer31. The conductive particles311are connected with each other to provide unidirectional electrical conductivity in the vertical direction. Referring toFIG.10D, an encapsulant50is formed on the carrier10and encapsulates the first substrate11and the second substrate12. The encapsulant50also encapsulates the pad layer20and the conductive bonding layer31. Referring toFIG.10E, the encapsulant50is ground to expose the first surfaces11aand12aof the first substrate11and the second substrate12. FIG.11A,FIG.11BandFIG.11Cillustrate various stages of a method for manufacturing a semiconductor package structure4in accordance with some embodiments of the present disclosure. Referring toFIG.11A, a pad layer20is formed on a carrier10as illustrated inFIG.9A. Referring toFIG.11B, a first substrate21and a second substrate22are disposed side-by-side on the pad layer20. The conductive vias111(or the pads or electrical contacts) of the first substrate11and the second substrate12are in direct contact with the pad layer20where a pad205of the pad layer20is in direct contact with the second surfaces11band12bof the first substrate11and the second substrate12to electrically connect the first substrate11to the second substrate12. The contact of the conductive vias111(or the pads or electrical contacts) and the the pad layer20are carried out by metal-to-metal bonding techniques. In some embodiments, there is a metal layer or intermetallic layer40formed at the interface during the operation of metal-to-metal bonding. Referring toFIG.11C, an encapsulant50is formed on the carrier10and encapsulates the first substrate11, the second substrate12and the pad layer20. In addition, the encapsulant50is ground to expose the first surfaces11aand12aof the first substrate11and the second substrate12. FIG.12A,FIG.12B,FIG.12C,FIG.12D,FIG.12E,FIG.12FandFIG.12Gillustrate various stages of a method for manufacturing a semiconductor package structure7in accordance with some embodiments of the present disclosure. Referring toFIG.12A, a substrate11is provided. The substrate11includes substrate units11′ and12′. The substrate units11′ and12′ may include a circuit with incomplete function. Referring toFIG.12B, one or more through holes110are formed around the periphery of the substrate units11′ and12′, for example, by laser drilling. Referring toFIG.12C, the through holes110are filled with solder material32′. Referring toFIG.12D, a singulation process is carried out, e.g., by laser dicing, along the periphery of the substrate units11′ and12′ and through the through holes110to singulate the substrate units11′ and12′. After singulation, partitioned substrates11and12are formed and include a solder material32′ disposed within a vertical recess located at a lateral surface thereof. As illustrated inFIG.12D, the solder material32′ may have a rough lateral surface after singulation. Referring toFIG.12E, the partitioned substrates11and12is disposed side-by-side on a carrier10. Referring toFIG.12F, a reflow process is carried out to form a conductive bonding layer32from the solder material32′. During the reflow process, the solder material32′ is melted, and since the distance between the partitioned substrates11and12can be controlled, the solder material32′ located at a lateral surface of the partitioned substrate11can be combine with the solder material32′ located at a lateral surface of the partitioned substrate12to form a conductive bonding layer32. An encapsulant50is then formed on the carrier10and encapsulates the partitioned substrates11and12. The encapsulant50may be ground to expose the surfaces11aand12aof the partitioned substrates11and12. Referring toFIG.12G, a patterned metal layer21is formed on the surface11aof the partitioned substrate11and the surface12aof the partitioned substrate12. The patterned metal layer21includes a plurality of pads. In some embodiments, the patterned metal layer21is an redistribution layer (RDL) which includes conductive traces and a plurality of pads. The patterned metal layer21is referred to as a pad layer in the embodiments of the present disclosure. The conductive vias111(or the pads or electrical contacts) exposed from the surface11aof the partitioned substrate11and the surface12aof the partitioned substrate12contact the pad layer21. A pad205of the pad layer21contacts the second surfaces11band12bof the first substrate11and the second substrate12to electrically connect the first substrate11to the second substrate12. In some embodiments, an L/S of the surface11aof the partitioned substrate11is less than an L/S of the surface11bof the partitioned substrate11and an L/S of the surface12aof the partitioned substrate12is less than an L/S of the surface12bof the partitioned substrate12. FIG.12A,FIG.12B,FIG.12C,FIG.12D,FIG.12H,FIG.12IandFIG.12Jillustrate various stages of a method for manufacturing a semiconductor package structure6in accordance with some embodiments of the present disclosure. Partitioned substrates11and12are prepared as discussed above with respect toFIG.12A,FIG.12B,FIG.12CandFIG.12D. InFIG.12H, a carrier10is provided and a pad layer20is formed on a carrier10as illustrated inFIG.9A. The partitioned substrates11and12are disposed side-by-side on the pad layer20. The conductive vias111(or the pads or electrical contacts) of the partitioned substrate11and the partitioned substrate12are in direct contact with the pad layer20where a pad205of the pad layer20is in direct contact with the surfaces11band12bof the partitioned substrate11and the partitioned substrate12to electrically connect the partitioned substrate11to the partitioned substrate12. In some embodiments, an L/S of the surface11aof the partitioned substrate11is less than an L/S of the surface11bof the partitioned substrate11and an L/S of the surface12aof the partitioned substrate12is less than an L/S of the surface12bof the partitioned substrate12. Referring toFIG.12I, a reflow process is carried out to form a conductive bonding layer32from the solder material32′. During the reflow process, the solder material32′ is melted, and since the distance between the partitioned substrates11and12can be controlled, the solder material32′ located at a lateral surface of the partitioned substrate11can be combine with the solder material32′ located at a lateral surface of the partitioned substrate12to form a conductive bonding layer32. Referring toFIG.12J, an encapsulant50is then formed on the carrier10and encapsulates the partitioned substrates11and12and the pad layer. The encapsulant50may be ground to expose the surfaces11aand12aof the partitioned substrates11and12and the surface32aof the conductive bonding layer32. FIG.13A,FIG.13B,FIG.13C,FIG.13D,FIG.13EandFIG.13Fillustrate various stages of a method for manufacturing a semiconductor package structure8in accordance with some embodiments of the present disclosure. Referring toFIG.13A, a semiconductor package structure5is provided. Though the a semiconductor package structure5is illustrated inFIG.13A, other semiconductor package structure, such as the semiconductor package structure2,3,4or6may be used. Referring toFIG.13B, an RDL structure61is formed on the surface11aof the substrate11, the surface12aof the substrate12and the surface50aof the encapsulant50. Referring toFIG.13C, electronic devices70and71are disposed on the RDL structure61. Referring toFIG.13D, an encapsulant51is disposed on the structure made inFIG.13Cto encapsulate the RDL structure61and the electronic devices70and71. The encapsulant51may contact the encapsulant50. In some embodiments, the encapsulant51may be ground to expose the surface70aof the electronic device70and the surface71aof the electronic device71as illustrated inFIG.13E. Referring toFIG.13F, the carrier10is removed and solder balls60are bonded to respective pads of the pad layer20. As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature. Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. As used herein, spatially relative terms, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present. As used herein, the term “vertical” is used to refer to these upward and downward directions, whereas the term “horizontal” refers to directions transverse to the vertical directions. As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be deemed to be substantially flat if a displacement between the highest point and the lowest point of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit, and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure. | 36,722 |
11862586 | DETAILED DESCRIPTION Embodiments will now be explained with reference to the accompanying drawings. InFIGS.1to33, the same configurations are denoted by the same reference symbols and repeated description is omitted. In one embodiment, a semiconductor device includes a first insulator, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided on the first pad in the second insulator. Furthermore, the first insulator includes a first film that is in contact with the first pad and the second insulator, and a second film provided at an interval from the first pad and the second insulator, and including a portion provided at a same height as at least a portion of the first pad. First Embodiment FIG.1is a cross-sectional view showing a structure of a semiconductor device of a first embodiment. The semiconductor device ofFIG.1is for example three-dimensional memory, and is manufactured by bonding an array wafer including an array region1to a circuit wafer including a circuit region2as described later. The array region1is provided with a memory cell array11including a plurality of memory cells, an insulator12on the memory cell array11, and an inter layer dielectric13under the memory cell array11. The insulator12is for example a silicon oxide film (SiO2film) or a silicon nitride film (SiN film). The inter layer dielectric13is for example a silicon oxide film or a laminated film including a silicon oxide film and another insulator. The inter layer dielectric13is an example of the second insulator (or the first insulator). The circuit region2is provided under the array region1. The reference symbol S denotes an interface (bonded face) between the array region1and the circuit region2. The circuit region2is provided with an inter layer dielectric14and a substrate15under the inter layer dielectric14. The inter layer dielectric14is for example a silicon oxide film or a laminated film including a silicon oxide film and another insulator. The inter layer dielectric14is an example of the first insulator (or the second insulator). The substrate15is for example a semiconductor substrate such as a silicon (Si) substrate. FIG.1indicates an X direction and a Y direction that are parallel to a surface of the substrate15and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate15. In the present specification, a +Z direction is considered to be an upper direction, and −Z direction is considered to be a lower direction. The −Z direction may and may not correspond to the direction of gravity. Although the semiconductor device ofFIG.1is in a state that the circuit region2is under the array region1, the semiconductor device ofFIG.1may be in a state that the array region1is under the circuit region2. The array region1is provided with a plurality of word lines WL as a plurality of electrode layers inside the memory cell array11, and a source line SL.FIG.1shows a stepped structure portion21of the memory cell array11. Each of the word lines WL is electrically connected to the word interconnect layer23via a contact plug22. Each of columnar portions CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug24, and electrically connected to the source line SL. The source line SL includes a lower layer SL1which is a semiconductor layer, and an upper layer SL2which is a metal layer. The circuit region2is provided with a plurality of transistors31. Each of the transistors31includes a gate electrode32provided on the substrate15via a gate insulator, and a source diffusion layer and a drain diffusion layer (not illustrated) provided in the substrate15. The circuit region2includes a plurality of contact plugs33provided on the gate electrodes32, the source diffusion layers, or the drain diffusion layers of these transistors31, an interconnect layer34provided on these contact plugs33and including a plurality of interconnects, and an interconnect layer35provided on the interconnect layer34and including a plurality of interconnects. The circuit region2further includes an interconnect layer36provided on the interconnect layer35and including a plurality of interconnects, a plurality of via plugs37provided on the interconnect layer36, and a plurality of metal pads38provided on these via plugs37. The metal pads38are for example metal layers including Cu (copper) layers. The metal pads38are examples of the first pad (or the second pad). The circuit region2functions as a control circuit (logic circuit) that controls operation of the array region1. The control circuit is configured with the transistors31and the like, and electrically connected to the metal pads38. The array region1includes a plurality of metal pads41provided on the metal pads38, and a plurality of via plugs42provided on the metal pads41. The array region1includes an interconnect layer43provided on these via plugs42and including a plurality of interconnects, and an interconnect layer44provided on the interconnect layer43and including a plurality of interconnects. The metal pads41are for example metal layers including Cu layers. The metal pads41are examples of the second pad (or the first pad). The bit line BL is included in the interconnect layer44. The control circuit is electrically connected to the memory cell array11via the metal pads41,38and the like and controls operation of the memory cell array11via the metal pads41,38and the like. The array region1further includes a plurality of via plugs45provided on the interconnect layer44, a metal pad46provided on these via plugs45and the insulator12, and a passivation film47provided on the metal pad46and the insulator12. The metal pad46is for example a metal layer including a Cu layer, and functions as an external connection pad (bonding pad) of the semiconductor device inFIG.1. The passivation film47is for example an insulator such as a silicon oxide film, and has an opening portion P that exposes an upper face of the metal pad46. The metal pad46is connectible to a mounting substrate and other devices with a bonding wire, a solder ball, a metal bump and the like through the opening portion P. FIG.2is a cross-sectional view showing a structure of the columnar portion CL of the first embodiment.FIG.2shows one of the plurality of columnar portions CL shown inFIG.1. As shown inFIG.2, the memory cell array11includes the plurality of word lines WL and the plurality of insulating layers51alternately stacked on the inter layer dielectric13(FIG.1). The word lines WL are for example W (tungsten) layers. The insulating layers51are for example silicon oxide films. The columnar portion CL includes a block insulator52, a charge storage layer53, a tunnel insulator54, a channel semiconductor layer55, and a core insulator56in this order. The charge storage layer53is for example an insulator such as a silicon nitride film, and formed on a lateral face of the word lines WL and the insulating layers51via the block insulator52. The charge storage layer53may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer55is for example a polysilicon layer, and formed on a lateral face of the charge storage layer53via the tunnel insulator54. The block insulator52, the tunnel insulator54, and the core insulator56are for example silicon oxide films or metal insulators. FIGS.3and4are cross-sectional views showing a method of manufacturing the semiconductor device of the first embodiment. FIG.3shows an array wafer W1including a plurality of array regions1and a circuit wafer W2including a plurality of circuit regions2. The array wafer W1is also referred to as a “memory wafer” and the circuit wafer W2is also referred to as a “CMOS wafer”. An orientation of the array wafer W1inFIG.3is opposite to an orientation of the array region1inFIG.1. In the present embodiment, the semiconductor device is manufactured by bonding the array wafer W1to the circuit wafer W2.FIG.3shows the array wafer W1before inversion of the orientation for bonding, andFIG.1shows the array region1after inversion of the orientation for bonding, bonding, and dicing. InFIG.3, a reference sign51denotes an upper face of the array wafer W1, and a reference sign S2denotes an upper face of the circuit wafer W2. The array wafer W1includes a substrate16provided under the insulator12. The substrate16is for example a semiconductor substrate such as a silicon substrate. The substrate15is an example of the first substrate (or the second substrate), and the substrate16is an example of the second substrate (or the first substrate). In the present embodiment, first, the memory cell array11, the insulator12, the inter layer dielectric13, the stepped structure portion21, the metal pads41and the like are formed on the substrate16of the array wafer W1, and the inter layer dielectric14, the transistors31, the metal pads38and the like are formed on the substrate15of the circuit wafer W2as shown inFIG.3. For example, the via plugs45, the interconnect layer44, the interconnect layer43, the via plugs42and the metal pads41are formed in this order on the substrate16. The contact plugs33, the interconnect layer34, the interconnect layer35, the interconnect layer36, the via plugs37and the metal pads38are formed in this order on the substrate15. Next, the array wafer W1is bonded to the circuit wafer W2by mechanical pressure as shown inFIG.4. As a result, the inter layer dielectric13and the inter layer dielectric14are joined. Next, the array wafer W1and the circuit wafer W2are annealed. As a result, the metal pads41and the metal pads38are joined. Thereafter, the substrate15is thinned by CMP (Chemical Mechanical Polishing), the substrate16is removed by CMP, and then the array wafer W1and the circuit wafer W2are cut into a plurality of chips. As described above, the semiconductor device ofFIG.1is manufactured. The metal pad46and the passivation film47are for example formed on the insulator12after thinning of the substrate15and removal of the substrate16. Although the array wafer W1is bonded to the circuit wafer W2in the present embodiment, the array wafer W1may also be bonded to the array wafer W1as an alternative. The description given above with reference toFIGS.1to4and the description given below with reference toFIGS.5A to33may also be applied to bonding between array wafers W1. AlthoughFIG.1shows an interface between the inter layer dielectric13and the inter layer dielectric14and interfaces between the metal pads41and the metal pads38, these interfaces typically become unobservable after the annealing. However, the positions at which these interfaces were present may be estimated by detecting, for example, inclination of lateral faces of the metal pads41and lateral faces of the metal pads38, and positional shift between the lateral faces of the metal pads41and the metal pads38. Hereinafter, with reference toFIGS.5A to15B, further details of the semiconductor device of the present embodiment are described. FIGS.5A to5Care cross-sectional views showing the structure of a semiconductor device of a first embodiment. FIG.5Ais a vertical cross-sectional view showing one pair among a plurality of pairs of metal pads38,41shown inFIG.1. InFIG.5A, the metal pad38is provided on the via plug37in the inter layer dielectric14, and the metal pad41is provided under the via plug42in the inter layer dielectric13.FIG.5Bis a lateral cross-sectional view taken along an A-A′ line shown inFIG.5Ashowing an X-Y cross section of the metal pad41.FIG.5Cis a lateral cross-sectional view taken along a B-B′ line shown inFIG.5Ashowing an X-Y cross section of the metal pad38. Hereinafter, further details of the metal pads38,41and the inter layer dielectrics14,13shown inFIG.5Aare described. The description refers toFIGS.5B and5Cas appropriate. As shown inFIG.5A, the metal pad38includes a barrier metal layer38aand a pad material layer38b. The barrier metal layer38ais formed on a lateral face and an upper face of the inter layer dielectric14, and the pad material layer38bis formed in the inter layer dielectric14via the barrier metal layer38a. Similarly, the metal pad41includes a barrier metal layer41aand a pad material layer41b. The barrier metal layer41ais formed on a lateral face and a lower face of the inter layer dielectric13, and the pad material layer41bis formed in the inter layer dielectric14via the barrier metal layer41a. The barrier metal layers38a,41aare for example metal layers containing a Ti (titanium) element or a Ta (tantalum) element. The pad material layers38b,41bare for example metal layers including Cu layers. Therefore, the metal pads38,41are also referred to as “Cu pads”. The inter layer dielectric14of the present embodiment includes an insulator14aand an insulator14b. The insulator14ais in contact with the metal pad38and the inter layer dielectric13, and arranged in a lateral direction, a lower direction and the like of the metal pad38. On the other hand, the insulator14bis in contact with neither the metal pad38nor the inter layer dielectric13, and arranged in a lateral direction of the metal pad38. In other words, the insulator14bis arranged at intervals from the metal pad38and the inter layer dielectric13. In the present embodiment, since a thickness of the insulator14bis smaller than a thickness of the metal pad38, the insulator14bis entirely positioned at the same height as a portion of the metal pad38. Therefore, a B-B′ line parallel to the XY plane passes through both the metal pad38and the insulator14b. The insulator14ais an example of the first film (or the second film), and the insulator14bis an example of the second film (or the first film). A reference for the “height” is for example the interface S. The reference for the “height” may also be the upper face of the substrate15. This also applies to the term “height” used in the following. The insulator14aand the insulator14bof the present embodiment are both SiO2films. Note that the insulator14aof the present embodiment is formed by using for example dTEOS (densified tetraethyl orthosilicate). On the other hand, the insulator14bof the present embodiment is formed by using for example PSZ (polysilazane). Therefore, the insulator14bincludes an N (nitrogen) atom as an impurity atom, and an N atom concentration in the insulator14bis higher than an N atom concentration in the insulator14a. Furthermore, the insulator14bis shrunk in a thermal process during manufacture of the semiconductor device. During manufacture of the semiconductor device of the present embodiment, the metal pads38and the metal pads41may be suitably joined by leveraging such a characteristic of the insulator14bas described later. The insulator14bof the present embodiment may also be another SiO2film (for example an NSG (None-doped Silicate Glass) film) that is shrunk in the thermal process during manufacture of the semiconductor device. The insulators14a,14bof the present embodiment may be other than the SiO2films. The inter layer dielectric13of the present embodiment includes an insulator13aand an insulator13b. The insulator13ais in contact with the metal pad41and the inter layer dielectric14, and arranged in a lateral direction, an upper direction and the like of the metal pad41. On the other hand, the insulator13bis in contact with neither the metal pad41nor the inter layer dielectric14, and arranged in a lateral direction of the metal pad41. In other words, the insulator13bis arranged at an interval from the metal pad41and the inter layer dielectric14. In the present embodiment, since a thickness of the insulator13bis smaller than a thickness of the metal pad41, the insulator13bis entirely positioned at the same height as a portion of the metal pad41. Therefore, an A-A′ line parallel to the XY plane passes through both the metal pad41and the insulator13b. The insulator13ais an example of the third film (or the fourth film), and the insulator13bis an example of the fourth film (or the third film). The insulator13aand the insulator13bof the present embodiment are both SiO2films. Note that the insulator13aof the present embodiment is formed by using for example dTEOS. On the other hand, the insulator13bof the present embodiment is formed by using for example PSZ. Therefore, the insulator13bincludes an N atom as an impurity atom, and an N atom concentration in the insulator13bis higher than an N atom concentration in the insulator13a. Furthermore, the insulator13bis shrunk in a thermal process during manufacture of the semiconductor device. During manufacture of the semiconductor device of the present embodiment, the metal pads38and the metal pads41may be suitably joined by leveraging such a characteristic of the insulator13bas described later. The insulator13bof the present embodiment may also be another SiO2film (for example an NSG film) that is shrunk in the thermal process during manufacture of the semiconductor device. The insulators13a,13bof the present embodiment may be other than the SiO2films. The insulator13aof the present embodiment includes a portion P1provided between the lateral face of the metal pad41and a lateral face of the insulator13bas shown inFIG.5A. Therefore, the insulator13bis not in contact with the metal pad41. The portion P1is an example of the second portion (or the first portion). Similarly, the insulator14aof the present embodiment includes a portion P2provided between the lateral face of the metal pad38and a lateral face of the insulator14b. Therefore, the insulator14bis not in contact with the metal pad38. The portion P2is an example of the first portion (or the second portion). FIG.5Bshows an X-Y cross section of the portion P1of the insulator13a. The portion P1of the present embodiment has a circular planar shape surrounding the metal pad41as shown inFIG.5B. The portion P1is further surrounded in a circular shape by the insulator13b. FIG.5Cshows an X-Y cross section of the portion P2of the insulator14a. The portion P2of the present embodiment has a circular planar shape surrounding the metal pad38as shown inFIG.5C. The portion P2is further surrounded in a circular shape by the insulator14b. FIGS.6A to6Bare cross-sectional views showing two examples of the structure of the semiconductor device of the first embodiment. FIG.6Ashows a first example of the structure of the semiconductor device of the present embodiment.FIG.6Ais a lateral cross-sectional view showing a broader range thanFIG.5B. In this example, each metal pad41has a solid rectangular planar shape, and the portion P1surrounding each metal pad41has a hollow rectangular planar shape. In this example, one insulator13bsurrounds the plurality of metal pads41individually via the plurality of portions P1. FIG.6Bshows a second example of the structure of the semiconductor device of the present embodiment.FIG.6Bis, similarly toFIG.6A, a lateral cross-sectional view showing a broader range thanFIG.5B, showing a different structure from the structure shown inFIG.6A. In this example, each metal pad41has a solid hexagonal planar shape, and the portion P1surrounding each metal pad41has a hollow and substantially hexagonal planar shape. Specifically, each portion P1has a circular planar shape which is a combination of a plurality (six in this example) of hexagons, each of these hexagons being in the same size as one metal pad41. Similarly, the insulator13balso has a circular planar shape which is a combination of a plurality of hexagons, each of these hexagons being in the same size as one metal pad41. As described above, the planar shapes of the metal pad41, the portion P1, and the insulator13bof this example are in a honeycomb structure. In this example as well, one insulator13bsurrounds the plurality of metal pads41individually via the plurality of portions P1. The planar shapes of the metal pad38, the portion P2, and the insulator14bin the first example are the same as the planar shapes of the metal pad41, the portion P1, and the insulator13brespectively. The planar shapes of the metal pad38, the portion P2, and the insulator14bin the second example are the same as the planar shapes of the metal pad41, the portion P1, and the insulator13brespectively. FIGS.7A to7Care cross-sectional views showing a structure of a semiconductor device of a first modification of the first embodiment.FIGS.7A to7Ccorrespond toFIGS.5A to5C, respectively. The insulator14bof the present modification is, similarly to that of the first embodiment, not in contact with the metal pad38and the inter layer dielectric13, and arranged in a lateral direction and the like of the metal pad38. Similarly, the insulator13bof the present modification is not in contact with the metal pad41nor the inter layer dielectric14, and arranged in a lateral direction and the like of the metal pad41. However, a thickness of the insulator14bof the present modification is greater than a thickness of the metal pad38, and the insulator14bis only partially positioned at the same height as a portion of the metal pad38. Therefore, the insulator14bof the present modification includes, not only a portion at a higher position than a lower face of the metal pad38, but also a portion at a lower position than the lower face of the metal pad38. Similarly, a thickness of the insulator13bof the present modification is greater than a thickness of the metal pad41, and the insulator13bis only partially positioned at the same height as a portion of the metal pad41. Therefore, the insulator13bof the present modification includes, not only a portion at a lower position than an upper face of the metal pad41, but also a portion at a higher position than the upper face of the metal pad41. According to the present modification, due to the insulators14b,13bhaving such shapes, the metal pads38and the metal pads41may be suitably joined. The thickness of the insulator14bof the present modification may be smaller than the thickness of the metal pad38, and the thickness of the insulator13bof the present modification may be smaller than the thickness of the metal pad41. FIGS.8A to8Care cross-sectional views showing a structure of a semiconductor device of a second modification of the first embodiment.FIGS.8A to8Ccorrespond toFIGS.5A to5C, respectively. The inter layer dielectric14of the present modification includes insulators14a,14bhaving the same shapes as the insulators14a,14bof the first modification. On the other hand, the inter layer dielectric13of the present modification includes the insulator13abut not the insulator13b. According to the present modification, due to the insulator14bhaving such a shape, the metal pads38and the metal pads41may be suitably joined. FIGS.9A to9Care cross-sectional views showing a structure of a semiconductor device of a third modification of the first embodiment.FIGS.9A to9Ccorrespond toFIGS.5A to5C, respectively. The inter layer dielectric13of the present modification includes insulators13a,13bhaving the same shapes as the insulators13a,13bof the first modification. On the other hand, the inter layer dielectric14of the present modification includes the insulator14abut not the insulator14b. According to the present modification, due to the insulator13bhaving such a shape, the metal pads38and the metal pads41may be suitably joined. FIGS.10A to10Care cross-sectional views showing an outline of the method of manufacturing the semiconductor device of the first embodiment.FIGS.10A to10Cshow details of the method shown inFIGS.3and4. FIG.10Ashows the array region1(array wafer W1) before bonding to the circuit region2(circuit wafer W2). InFIG.10A, the upper face of the metal pad38is recessed in a lower direction with respect to the upper face of the inter layer dielectric14, and the lower face of the metal pad41is recessed in an upper direction with respect to the lower face of the inter layer dielectric13. These recesses are referred to as dishing, and generated during, for example, flattening of the surfaces of the inter layer dielectrics14,13by CMP. Even when the array region1is bonded to the circuit region2, the metal pads41and the metal pads38may not be suitably joined due to these recesses. FIG.10Bshows the array region1after bonding to the circuit region2and before annealing for joining the metal pads38,41. InFIG.10B, a gap is caused between the metal pad41and the metal pad38due to the aforementioned recesses. Without filling the gap, joining defect between the metal pads41and the metal pads38is likely. FIG.10Cshows the array region1after bonding to the circuit region2and after annealing for joining the metal pads38,41. InFIG.10C, the gap between the metal pad41and the metal pad38is filled and the metal pad41and the metal pad38are suitably joined. This is due to thermal expansion of the metal pads41,38by the annealing, and action of the insulators14b,13bby the annealing. The action of the insulators14b,13bof the present embodiment is described hereinafter. The insulators14b,13bof the present embodiment are formed by using for example PSZ (polysilazane). Therefore, during annealing of the metal pads41,38, the insulators14b,13bare heated and shrunk. As a result, a compressive stress is applied from the insulators14b,13bto the metal pads41,38, and facilitates approach between the metal pad41and the metal pad38. Therefore, according to the present embodiment, due to the thermal expansion of the metal pads41,38and the action of the insulators14b,13b, it is made possible to suitably join the metal pads41and the metal pads38. A thickness of the insulator14bof the present embodiment is reduced by, for example, greater than 9% and no greater than 25% by the shrinkage during the annealing. When the thickness of the insulator14bbefore the shrinkage is denoted by “T1” and the thickness of the insulator14bafter the shrinkage is denoted by “T2”, a relationship T1×0.75≤T2<T1×0.91 is satisfied. Similarly, a thickness of the insulator13bof the present embodiment is reduced by, for example, greater than 9% and no greater than 25% by the shrinkage during the annealing. This makes it possible to generate a sufficient compressive stress and to sufficiently suitably join the metal pad41and the metal pad38. The metal pads41,38of the present embodiment include for example Cu layers. Therefore, the annealing of the metal pads41,38is preferably carried out at no greater than 400° C. in order to suppress a negative influence of the annealing to the Cu layers. Therefore, the thickness of the insulator14bof the present embodiment is preferably reduced by greater than 9% and no greater than 25% by the annealing at no greater than 400° C. Such an insulator14bcan be realized by, for example, forming the insulator14bby using PSZ. This also applies to the insulator13b. The inter layer dielectric14of the present embodiment preferably includes not only the insulator14bformed by using PSZ and the like, but also the insulator14aformed by using dTEOS and the like. This is because, immediately after forming a PSZ film on the substrate15, the PSZ film has a characteristic close to liquid and a process (for example, CPM) of the PSZ film is difficult. FIGS.11A to15Bare cross-sectional views showing details of the method of manufacturing the semiconductor device of the first embodiment.FIGS.11A to15Bshow details of the method shown inFIGS.10A to10C. FIG.11Ashows a portion of the circuit region2(circuit wafer W2). When forming the circuit region2, an insulator14a1is formed on an upper side of the substrate15, the via plug37is formed in the insulator14a1, and an insulator14a2is formed on the insulator14a1and the via plug37(FIG.11A). The insulators14a1,14a2are parts of the insulator14a, and formed by, for example, CVD (Chemical Vapor Deposition) by using dTEOS as a source gas. Next, a concave portion H1is formed in the insulator14a2by lithography and RIE (Reactive Ion Etching) (FIG.11B). Next, the insulator14bis formed in the concave portion H1(FIG.12A). The insulator14bis formed by, for example, a coating method using PSZ. The insulator14bof the present embodiment may be formed to have, for example, either a planar shape shown inFIG.5CandFIG.6Aor a planar shape shown inFIG.6B. Next, the insulator14a3is formed on the insulators14a2,14b(FIG.12B). The insulator14a3is a portion of the insulator14a, and formed by, for example, CVD by using dTEOS. Next, a concave portion H2is formed in the insulators14a2,14a3by lithography and RIE (FIG.13A). As a result, an upper face of the via plug37is exposed in the concave portion H2. The concave portion H2is used as a pad groove in which the metal pad38is to be embedded. Next, a barrier metal layer38ais formed on the via plug37and the insulators14a1,14a2,14a3(FIG.13B). The barrier metal layer38ais for example a metal layer containing a Ti element or a Ta element, and is formed by CVD. Next, the pad material layer38bis formed on the via plug37and the insulators14a1,14a2,14a3, via the barrier metal layer38a(FIG.14A). The pad material layer38bis for example a Cu layer and formed by a plating method. Next, the surface of the pad material layer38bis flattened by CMP (FIG.14B). As a result, the barrier metal layer38aand the pad material layer38boutside the concave portion H2are removed, and the metal pad38is formed in the concave portion H2. The metal pad38of the present embodiment is formed in a position in contact with the insulators14a1,14a2,14a3, and not in contact with the insulator14b. InFIG.14B, a thickness of the insulator14bis smaller than a thickness of the metal pad38, and the insulator13bis entirely positioned at the same height as a portion of the metal pad38. FIG.15Ashows a portion of the array region1(array wafer W1). The array region1shown inFIG.15Ais formed by the steps shown inFIGS.11A to14B, similarly to the circuit region2. However, the substrate16, the insulators13a1,13a2,13a3in the insulator13a, the insulator13b, the via plug42, the barrier metal layer41a, the pad material layer41band the like are respectively processed similarly to the substrate15, the insulators14a1,14a2,14a3in the insulator14a, the insulator14b, the via plug37, the barrier metal layer38a, the pad material layer38band the like. Next, the substrate15is bonded to the substrate16such that the metal pads41are arranged on the metal pads38, and the insulator13a1(inter layer dielectric13) is arranged on the insulator14a1(inter layer dielectric14) (FIG.15B). Specifically, by bonding the inter layer dielectric14to the inter layer dielectric13by mechanical pressure, the inter layer dielectric14and the inter layer dielectric13are joined. Furthermore, by annealing the metal pads38,41, the inter layer dielectrics14,13and the like, the metal pads41and the metal pads38are joined. By the shrinkage of the insulators14b,13bduring this annealing, joining of the metal pads38,41can be promoted. Thereafter, the substrate15is thinned by CMP, the substrate16is removed by CMP, and then the array wafer W1and the circuit wafer W2(seeFIG.4) are cut into a plurality of chips. As described above, the semiconductor device of the present embodiment shown inFIGS.5A to5Cand the like is manufactured. The insulators14b,13bformed by the method shown inFIGS.11A to15Bmay have the shape of any one of the first to third modifications of the present embodiment. The shape of the insulator14bcan be controlled by adjusting the shape of the concave portion H1. Similarly, the shape of the insulator13bcan also be controlled by adjusting the shape of a concave portion corresponding to the concave portion H1. As described above, the semiconductor device of the present embodiment includes the inter layer dielectric14including not only the insulator14abut also the insulator14b, and the inter layer dielectric13including not only the insulator13abut also the insulator13b. The insulators14a,13aare formed by using dTEOS for example. The insulators14b,13bare formed by using PSZ for example. Therefore, according to the present embodiment, due to the action of the insulators14b,13b, it is made possible to suitably join the metal pads38and the metal pads41. Second Embodiment FIG.16is a cross-sectional view showing a structure of a semiconductor device of the second embodiment. Similarly toFIG.5A,FIG.16is a vertical cross-sectional view showing one pair among a plurality of pairs of metal pads38,41shown inFIG.1. InFIG.16, the metal pad38is provided on the via plug37in the inter layer dielectric14, and the metal pad41is provided under the via plug42in the inter layer dielectric13. Furthermore, the via plug37is provided on the interconnect layer36in the inter layer dielectric14, and the via plug42is provided under the interconnect layer43in the inter layer dielectric13. Hereinafter, further details of the metal pads38,41and the inter layer dielectrics14,13shown inFIG.16are described. In the description, as for aspects in common with the metal pads38,41and the inter layer dielectrics14,13shown inFIG.5A, description is omitted as appropriate. The inter layer dielectric14of the present embodiment includes a plurality of insulators14a, an insulator14c, and an insulator14das illustrated inFIG.16. Each of the insulators14ais an SiO2film formed by using dTEOS for example. The insulator14cis provided in a lateral direction of the via plug37and interposed between two insulators14a. The insulator14cis for example an SiCN film (silicon carbonitride film). The insulator14dis provided on an upper face of the interconnect layer36and interposed between two insulators14a. The insulator14dis for example a SiN film. Similarly, the inter layer dielectric13of the present embodiment includes a plurality of insulators13a, an insulator13c, and an insulator13d. Each of the insulators13ais an SiO2film formed by using dTEOS for example. The insulator13cis provided in a lateral direction of the via plug42and interposed between two insulators13a. The insulator13cis for example an SiCN film. The insulator13dis provided on a lower face of the interconnect layer43and interposed between two insulators13a. The insulator13dis for example a SiN film. The semiconductor device of the present embodiment further includes a metal layer39provided in the uppermost insulator14a. The metal layer39is positioned in a lateral direction of the via plug37and in contact with the via plug37. In addition, the metal layer39is positioned in a lower direction of the metal pad38and in an upper direction of the interconnect layer36, and in contact with neither the metal pad38nor the interconnect layer36. In other words, the metal layer39is arranged at an interval from the metal pad38and the interconnect layer36. The metal layer39of the present embodiment has a circular planar shape surrounding the via plug37. The metal layer39is an example of the first layer (or the second layer) and the first metal layer (or the second metal layer). In the present embodiment, since a thickness of the metal layer39is smaller than a thickness of the via plug37, the metal layer39is entirely positioned at the same height as a portion of the via plug37. Therefore, an upper face of the metal layer39is positioned at a height lower than the upper face of the via plug37, and a lower face of the metal layer39is positioned at a height higher than a lower face of the via plug37. In addition, the thickness of the metal layer39of the present embodiment is smaller than the thickness of the metal pad38, and for example no less than 5% and no greater than 30% of the thickness of the metal pad38. When the thickness of the metal pad38is denoted by “T3” and the thickness of the metal layer39is denoted by “T4”, a relationship T3×0.05≤T4≤T3×0.30 is satisfied. The metal layer39of the present embodiment has a linear expansion coefficient greater than a linear expansion coefficient of the pad material layer38bof the metal pad38. Therefore, in the thermal process during manufacture of the semiconductor device, a thermal expansion rate of the metal layer39is greater than a thermal expansion rate of the pad material layer38b. During manufacture of the semiconductor device of the present embodiment, the metal pads38and the metal pads41may be suitably joined by leveraging such a characteristic of the metal layer39as described later. For example, the pad material layer38bis a Cu (copper) layer, and the metal layer39is an Al (aluminum) layer or a Zn (zinc) layer. At the same temperature, aluminum and zinc have linear expansion coefficients greater than that of copper. For example, the linear expansion coefficients at 20° C. of copper, aluminum, and zinc are 16.5×10−6/° C., 23.1×10−6/° C., and 30.2×10−6/° C. respectively. Further detail of the linear expansion coefficient is described later. The semiconductor device of the present embodiment further includes a metal layer48provided in the lowermost insulator13a. The metal layer48is positioned in a lateral direction of the via plug42and in contact with the via plug42. In addition, the metal layer48is positioned in an upper direction of the metal pad41and in a lower direction of the interconnect layer43, and in contact with neither the metal pad41nor the interconnect layer43. In other words, the metal layer48is arranged at an interval from the metal pad41and the interconnect layer43. The metal layer48of the present embodiment has a circular planar shape surrounding the via plug42. The metal layer48is an example of the second layer (or the first layer) and the second metal layer (or the first metal layer). In the present embodiment, since a thickness of the metal layer48is smaller than a thickness of the via plug42, the metal layer48is entirely positioned at the same height as a portion of the via plug42. Therefore, a lower face of the metal layer48is positioned at a height higher than the lower face of the via plug42, and an upper face of the metal layer48is positioned at a height lower than an upper face of the via plug42. In addition, the thickness of the metal layer48of the present embodiment is smaller than the thickness of the metal pad41, and for example no less than 5% and no greater than 30% of the thickness of the metal pad41. The metal layer48of the present embodiment has a linear expansion coefficient greater than a linear expansion coefficient of the pad material layer41bof the metal pad41. Therefore, in the thermal process during manufacture of the semiconductor device, a thermal expansion rate of the metal layer48is greater than a thermal expansion rate of the pad material layer41b. During manufacture of the semiconductor device of the present embodiment, the metal pads38and the metal pads41may be suitably joined by leveraging such a characteristic of the metal layer48as described later. For example, the pad material layer41bis a Cu layer, and the metal layer48is an Al layer or a Zn layer. The semiconductor device of the present embodiment may include a non-metal layer having a linear expansion coefficient greater than that of the pad material layer38binstead of the metal layer39, and may include a non-metal layer having a linear expansion coefficient greater than that of the pad material layer41binstead of the metal layer48. In this case, the metal pads38and the metal pads41may be suitably joined by leveraging such characteristics of the non-metal layers. These non-metal layers may be formed from either an inorganic substance or an organic substance. FIG.17is a cross-sectional view showing a structure of a semiconductor device of a first modification of the second embodiment. The metal layer39of the present modification is in contact with not only the via plug37but also the metal pad38. Similarly, the metal layer48of the present modification is in contact with not only the via plug42but also the metal pad41. According to the present modification, similarly to the second embodiment, by leveraging the property of greatly expanding of the metal layers39,48, the metal pads38and the metal pads41may be suitably joined. FIG.18is a cross-sectional view showing a structure of a semiconductor device of a second modification of the second embodiment. The metal layer39of the present modification surrounds the via plug37in a circular shape in a state of being spaced apart from the via plug37, and is not in contact with the via plug37. Similarly, the metal layer48of the present modification surrounds the via plug42in a circular shape in a state of being spaced apart from the via plug42, and is not in contact with the via plug42. According to the present modification, similarly to the second embodiment, by leveraging the property of greatly expanding of the metal layers39,48, the metal pads38and the metal pads41may be suitably joined. FIG.19is a cross-sectional view showing a structure of a semiconductor device of a third modification of the second embodiment. The semiconductor device of the present modification includes the metal layer39having the same shape as the metal layer39of the first embodiment, but not the metal layer48. According to the present modification, by leveraging the property of greatly expanding of the metal layer39, the metal pads38and the metal pads41may be suitably joined. FIG.20is a cross-sectional view showing a structure of a semiconductor device of a fourth modification of the second embodiment. The semiconductor device of the present modification includes the metal layer48having the same shape as the metal layer48of the first embodiment, but not the metal layer39. According to the present modification, by leveraging the property of greatly expanding of the metal layer48, the metal pads38and the metal pads41may be suitably joined. FIGS.21A to21Care cross-sectional views showing an outline of a method of manufacturing the semiconductor device of the second embodiment.FIGS.21A to21Cshow details of the method shown inFIGS.3and4. FIG.21Ashows the array region1(array wafer W1) before bonding to the circuit region2(circuit wafer W2) similarly toFIG.10A. Also inFIG.21A, the upper face of the metal pad38is recessed in a lower direction with respect to the upper face of the inter layer dielectric14, and the lower face of the metal pad41is recessed in an upper direction with respect to the lower face of the inter layer dielectric13. Even when the array region1is bonded to the circuit region2, the metal pads41and the metal pads38may not be suitably joined due to these recesses. FIG.21Bshows the array region1after bonding to the circuit region2and before annealing for joining the metal pads38,41, similarly toFIG.10B. Also inFIG.21B, a gap is caused between the metal pad41and the metal pad38due to the aforementioned recesses. Without filling the gap, joining defect between the metal pads41and the metal pads38is likely. FIG.21Cshows the array region1after bonding to the circuit region2and after annealing for joining the metal pads38,41, similarly toFIG.10C. Also inFIG.21C, the gap between the metal pad41and the metal pad38is filled and the metal pad41and the metal pad38are suitably joined. This is due to thermal expansion of the metal pads41,38by the annealing, and action of the metal layers39,48by the annealing. The action of the metal layers39,48of the present embodiment is described hereinafter. The pad material layers38b,41bin the metal pads38,41of the present embodiment are for example Cu layers. On the other hand, the metal layers39,48of the present embodiment are for example Al layers or Zn layers. Therefore, the linear expansion coefficients of the metal layers39,48are greater than the linear expansion coefficients of the pad material layers38b,41b. As a result, when the metal pads38,41and the metal layers39,48are annealed, the thermal expansion rates of the metal layers39,48are greater than the thermal expansion rates of the pad material layers38b,41b, whereby the metal layers39,48greatly expand. As a result, a compressive stress is applied from the metal layers39,48to the metal pads41,38, and facilitates approach between the metal pad41and the metal pad38. Therefore, according to the present embodiment, due to the thermal expansion of the metal pads41,38and further thermal expansion of the metal layers39,48, it is made possible to suitably join the metal pads41and the metal pads38. The annealing of the metal pads41,38of the present embodiment is preferably carried out at no greater than 400° C. in order to suppress a negative influence of the annealing to the Cu layers. FIGS.22A to27Bare cross-sectional views showing details of the method of manufacturing the semiconductor device of the second embodiment.FIGS.22A to27Bshow details of the method shown in FIGS.21A to21C. FIG.22Ashows a portion of the circuit region2(circuit wafer W2). When forming the circuit region2, an insulator14a4is formed on an upper side of the substrate15(FIG.21A). The insulator14a4is a portion of the insulator14a, and formed by, for example, CVD by using dTEOS as a source gas. In the following description, description of the insulators14c,14din the inter layer dielectric14(FIG.16) is omitted. Next, a concave portion H3is formed in the insulator14a4by lithography and RIE (FIG.22B). Next, the metal layer39is formed in the concave portion H3(FIG.23A). The metal layer39is for example an Al layer or a Zn layer. The metal layer39of the present embodiment is formed by depositing the metal layer39inside and outside the concave portion H3by CVD, and removing the metal layer39outside the concave portion H3by CMP. Next, an insulator14a5is formed on the insulator14a4and the metal layer39(FIG.23B). The insulator14a5is a portion of the insulator14a, and formed by, for example, CVD by using dTEOS. Next, a concave portion H4is formed in the insulators14a4,14a5and the metal layer39by lithography and RIE (FIG.24A). As a result, an upper face of the interconnect layer36, which is not illustrated, is exposed in the concave portion H4. The concave portion H4is formed to penetrate the metal layer39and used as a via hole in which the via plug37is to be embedded. Next, a material for the via plug37is formed on the interconnect layer36, which is not illustrated, and the insulator14a5(FIG.24B). The material may be either the same as the material for the metal plug38or different from the material for the metal plug38. In the former case, the via plug37is formed to include for example a Cu layer. In the latter case, the via plug37is formed to include for example a W (tungsten) layer. Next, the surface of the material is flattened by CMP (FIG.25A). As a result, the material outside the concave portion H4is removed, and the via plug37is formed in the concave portion H4by the single damascene process. InFIG.25A, the via plug37is in contact with the metal layer39and surrounded in a circular shape by the metal layer39. Furthermore, inFIG.25A, a thickness of the metal layer39is smaller than a thickness of the via plug37, and the metal layer39is entirely positioned at the same height as a portion of the via plug37. Next, an insulator14a6is formed on the insulator14a5and the via plug37(FIG.25B). The insulator14a6is a portion of the insulator14a, and formed by, for example, CVD by using dTEOS. Next, a concave portion H5is formed in the insulator14a6by lithography and RIE (FIG.26A). As a result, an upper face of the via plug37is exposed in the concave portion H5. The concave portion H5is used as a pad groove in which the metal pad38is to be embedded. Next, the barrier metal layer38ais formed on the via plug37and the insulators14a5,14a6(FIG.26B). The barrier metal layer38ais for example a metal layer containing a Ti element or a Ta element, and is formed by CVD. Next, the pad material layer38bis formed on the via plug37and the insulators14a5,14a6via the barrier metal layer38a(FIG.27A). The pad material layer38bis for example a Cu layer and formed by a plating method. Next, the surface of the pad material layer38bis flattened by CMP (FIG.27B). As a result, the barrier metal layer38aand the pad material layer38boutside the concave portion H5are removed, and the metal pad38is formed in the concave portion H5by the single damascene process. The metal pad38of the present embodiment is formed in a position in contact with the via plug37, and not in contact with the metal layer39. FIG.28Ashows a portion of the array region1(array wafer W1). The array region1shown inFIG.28Ais formed by the steps shown inFIGS.22A to27B, similarly to the circuit region2. However, the substrate16, the insulators13a4,13a5,13a6in the insulator13a, the via plug42, the barrier metal layer41a, the pad material layer41b, the metal layer48and the like are respectively processed similarly to the substrate15, the insulators14a1,14a2,14a3in the insulator14a, the insulator14b, the via plug37, the barrier metal layer38a, the pad material layer38b, the metal layer39and the like. InFIG.28A, illustration of the insulators13c,13din the inter layer dielectric13(FIG.16) is omitted. Next, the substrate15is bonded to the substrate16such that the metal pads41are arranged on the metal pads38, and the insulator13a1(inter layer dielectric13) is arranged on the insulator14a1(inter layer dielectric14) (FIG.28B). Specifically, by bonding the inter layer dielectric14to the inter layer dielectric13by mechanical pressure, the inter layer dielectric14and the inter layer dielectric13are joined. Furthermore, by annealing the metal pads38,41, the inter layer dielectrics14,13and the like, the metal pads41and the metal pads38are joined. By the expansion of the metal layers39,48during this annealing, joining of the metal pads38,41can be promoted. Thereafter, the substrate15is thinned by CMP, the substrate16is removed by CMP, and then the array wafer W1and the circuit wafer W2(seeFIG.4) are cut into a plurality of chips. As described above, the semiconductor device of the present embodiment shown inFIGS.21A to21Cand the like is manufactured. The metal layers39,48formed by the method shown inFIGS.22A to28Bmay have the shape of any one of the first to fourth modifications of the present embodiment. The shape of the metal layer39can be controlled by adjusting the shape of the concave portion H3. Similarly, the shape of the metal layer38can also be controlled by adjusting the shape of a concave portion corresponding to the concave portion H3. FIGS.29A to32Bare cross-sectional views showing details of another method of manufacturing the semiconductor device of the second embodiment. First, the steps shown inFIGS.22A to25Bare carried out. However, the steps related to the via plug37(FIGS.23A to25A) are omitted.FIG.29Ashows the circuit region2(circuit wafer W2) after carrying out the step shown inFIG.25B. Next, a concave portion H5is formed in the insulator14a6by lithography and RIE (FIG.29B). Next, a concave portion H4is formed in the insulators14a5,14a4and the metal layer39positioned below the concave portion H5by lithography and RIE (FIG.30A). As a result, an upper face of the interconnect layer36, which is not illustrated, is exposed in the concave portion H4. Next, the barrier metal layer38ais formed on the interconnect layer36, which is not illustrated, and the insulators14a5,14a6(FIG.30B). The barrier metal layer38ais for example a metal layer containing a Ti element or a Ta element, and is formed by CVD. Next, the pad material layer38bis formed on the interconnect layer36, which is not illustrated, and the insulators14a5,14a6via the barrier metal layer38a(FIG.31A). The pad material layer38bis for example a Cu layer and formed by a plating method. Next, the surface of the pad material layer38bis flattened by CMP (FIG.31B). As a result, the barrier metal layer38aand the pad material layer38boutside the concave portions H4, H5are removed, and the metal pad38and the via plug37are respectively formed in the concave portions H4, H5by the dual damascene process. In this case, the via plug37is formed of the barrier metal layer38aand the pad material layer38bsimilarly to the metal pad38. FIG.32Ashows a portion of the array region1(array wafer W1). The array region1shown inFIG.32Ais formed by the steps shown inFIGS.29A to31B, similarly to the circuit region2. However, the substrate16, the insulators13a4,13a5,13a6in the insulator13a, the via plug42, the barrier metal layer41a, the pad material layer41b, the metal layer48and the like are respectively processed similarly to the substrate15, the insulators14a1,14a2,14a3in the insulator14a, the insulator14b, the via plug37, the barrier metal layer38a, the pad material layer38b, the metal layer39and the like. Next, the substrate15is bonded to the substrate16such that the metal pads41are arranged on the metal pads38, and the insulator13a1(inter layer dielectric13) is arranged on the insulator14a1(inter layer dielectric14) (FIG.32B). Specifically, by bonding the inter layer dielectric14to the inter layer dielectric13by mechanical pressure, the inter layer dielectric14and the inter layer dielectric13are joined. Furthermore, by annealing the metal pads38,41, the inter layer dielectrics14,13and the like, the metal pads41and the metal pads38are joined. By the expansion of the metal layers39,48during this annealing, joining of the metal pads38,41can be promoted. Thereafter, the substrate15is thinned by CMP, the substrate16is removed by CMP, and then the array wafer W1and the circuit wafer W2(seeFIG.4) are cut into a plurality of chips. As described above, the semiconductor device of the present embodiment shown inFIGS.21A to21Cand the like is manufactured. The metal layers39,48formed by the method shown inFIGS.29A to32Bmay have the shape of any one of the first to fourth modifications of the present embodiment. The shape of the metal layer39can be controlled by adjusting the shape of the concave portion H3. Similarly, the shape of the metal layer38can also be controlled by adjusting the shape of a concave portion corresponding to the concave portion H3. FIG.33is a graph for illustrating materials of the semiconductor device of the second embodiment. FIG.33shows temperature dependence of the linear expansion coefficients of silicon (Si), copper (Cu), aluminum (Al), and zinc (Zn). As shown inFIG.33, magnitude of the linear expansion coefficients of these substances at the same temperature is in a relationship Zn>Al>Cu>Si, with almost all of the temperatures shown inFIG.33. Therefore, in the present embodiment, by configuring the pad material layers38b,41bin the metal pads38,41as Cu layers and configuring the metal layers39,48as Al layers or Zn layers, the linear expansion coefficients of the metal layers39,48can be made greater than the linear expansion coefficients of the pad material layers38b,41bin the metal pads38,41. As described in the foregoing, in the semiconductor device of the present embodiment, the metal layer39is provided in the circuit region2and the metal layer48is provided in the array region1. For example, the metal pads38,41include Cu layers, while the metal layers39,48are Al layers or Zn layers. Therefore, according to the present embodiment, due to the action of the metal layers39,48, it is made possible to suitably join the metal pads38and the metal pads41. The embodiments described above may be implemented as below. (Appendix 1) A method of manufacturing a semiconductor device, including:forming a first insulator on a first substrate;forming a first plug in the first insulator;forming a first pad on the first plug in the first insulator;forming, in the first insulator, a first layer having a linear expansion coefficient greater than a linear expansion coefficient of the first pad, and including a portion provided at a same height as at least a portion of the first plug;forming a second insulator on a second substrate;forming a second plug in the second insulator;forming a second pad on the second plug in the second insulator; andbonding the first substrate to the second substrate such that the second insulator is arranged on the first insulator, and the second pad is arranged on the first pad. (Appendix 2) The method of Appendix 1, wherein the first layer is formed before the first plug is formed. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 56,923 |
11862587 | DETAILED DESCRIPTION Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement. The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In a semiconductor package structure according to the present disclosure, a second semiconductor device such as a decoupling capacitor, inductor or the like is directly bonded to a first semiconductor device such as a digital processor. With the bonding configuration, electrical losses and impedance through a semiconductor package structure are reduced or minimized. By comparison, in some existing approaches, intermediate or interconnection layers that may include solders and redistribution structures exist between a digital processor and a decoupling capacitor. Relatively high losses and impedance associated with a transmission path going through these layers may thus occur. In some embodiments according to the present disclosure, by placing discrete components such as the decoupling capacitor and interconnection structures closer to a digital processor, the transmission path is shortened while the resistivity of materials is reduced or minimized, thereby enhancing the performance. As a result, with the bonding configuration and closely arranged components to be decoupled, powering and grounding the first semiconductor device and the second semiconductor device may be accomplished in a relatively short path, resulting in less electrical loss. FIG.1is a cross-sectional view of a semiconductor package structure100in accordance with an embodiment of the present disclosure. Referring toFIG.1, the semiconductor package structure100includes a first semiconductor device11and a second semiconductor device12, which are sealed in an encapsulating layer31. The first semiconductor device11has a first surface11a(the “active surface”) and a second surface11b(the “backside surface”) opposite to the first surface11a, and includes a plurality of conductive pads119at the first surface11a, a plurality of conductive pillars112(the “conductive elements”) and a plurality of studs115. The conductive pillars112(the “conductive elements”) and the studs115for electrical connection are disposed on the conductive pads119. The conductive pillars112(the “conductive elements”) are disposed over the first surface11a(the “active surface”) of first semiconductor device11and outside the second semiconductor device12. Thus, the first semiconductor device11is electrically connected to the redistribution structure40via the conductive pillars112(the “conductive elements”). The second semiconductor device12includes conductive studs125bonded onto the conductive studs115of the first semiconductor device11, forming bonded joints135between the first semiconductor device11and the second semiconductor device12. The semiconductor package structure100also includes a redistribution structure40, which further includes a dielectric layer42and a conductive layer45. In addition, electrical contacts81are mounted on a surface42aof the redistribution structure40. As shown inFIG.1, the electrical contacts81are disposed on a conductive layer45of the redistribution structure40. The redistribution structure40and the electrical contacts81function to provide electrical connection of the first semiconductor device11to an external structure that may include other semiconductor devices or components. For example, the semiconductor package structure100may be attached via the electrical contacts81to a substrate, an interposer or a printed circuit board (PCB). In an embodiment, the first semiconductor device11includes a digital processing device, while the second semiconductor device12includes a decoupling capacitor. Moreover, the digital processing device may include one or more general-purpose processing devices such as an application processor, a microprocessor, a central processing unit or a controller. Alternatively, the digital processing device may include one or more special-purpose processing devices such as a digital signal processor (DSP), a graphics processing unit, an application specific integrated circuit (ASIC) or a field programmable gate array (FGA). Furthermore, the digital processing device may include a network processor that further includes a core unit and multiple microengines. Additionally, the digital processing device may include any combination of general-purpose processing devices and special-purpose processing devices. Furthermore, the decoupling capacitor functions to alleviate noise. A decoupling capacitor is a capacitor used to decouple one part of an electrical network or circuit from another. Noise caused by other circuit elements is shunted through the capacitor, reducing the effect it has on the rest of the circuit. In an embodiment according to the present disclosure, the Q value of the decoupling capacitor is tied to the materials used and the thickness (volume) thereof. When the thickness is reduced along with the downsizing trend, attention is paid to reduce the impedance by, for example, reducing the path between the digital processor (the first semiconductor device11) and the decoupling capacitor (the second semiconductor device12) and the portion of the circuit to be decoupled by the decoupling capacitor. The electrical contacts81may include solder balls, which may be arranged in a ball grid array (BGA). Alternatively, the electrical contacts81may include metal pads arranged in a land grid array (LGA). Additionally, the electrical contacts81may include leads arranged in a pin grid array (PGA). Moreover, the electrical contacts81may include controlled collapse chip connection (C4) bumps, which include lead based or lead-free bumps or balls. When the semiconductor package structure100is attached to an external structure such as a PCB, the first semiconductor device11is oriented “face-down” with its active surface11afacing towards the PCB. In such configuration, a significant portion of the encapsulating layer31that surrounds the second semiconductor device12is disposed between the first semiconductor device11and the PCB, which provides desirable mechanical reliability. Moreover, by bonding the first semiconductor device11and the second semiconductor device12, the transmission path is shortened while the resistivity of materials due to intermediate layers that would otherwise exist in some existing approaches is reduced or minimized. In addition, direct connection between the first semiconductor device11and the second semiconductor device12through the bonded joints135helps alleviate parasitic effects and thus reduces electrical losses, as will be discussed below by reference toFIGS.2A and2B. FIG.1Ais a cross-sectional view of a semiconductor package structure100ain accordance with an embodiment of the present disclosure. Referring toFIG.1A, the semiconductor package structure100ais similar to the semiconductor package structure100described and illustrated with reference toFIG.1except that, for example, the second semiconductor device12afurther includes a plurality of conductive vias126. The conductive vias126are disposed in the second semiconductor device12a, and electrically connect the conductive studs125and the conductive layer45. In some embodiments, the conductive vias126may be TSVs (through silicon vias). FIG.2Ais a schematic diagram showing a relatively short path for powering the first semiconductor device11and the second semiconductor device12in the semiconductor package structure100illustrated inFIG.1. Referring toFIG.2A, when the semiconductor package structure100is attached to an external structure such as a PCB, a voltage V from the PCB that serves as an operation voltage is provided to the first semiconductor device11via one (labeled “81P”) of the electrical contacts81, a wiring route (not shown) in the RDL structure40, a first conductive pillar112, a first bonded joint “135P” between the first semiconductor device11and the second semiconductor device12, and then a second bonded joint135P, forming a powering path (shown in solid lines). The first bonded joint135P is formed by a conductive stud125and a corresponding conductive stud115, and thus is common to the first semiconductor device11and the second semiconductor device12. The powering path is relatively short for powering the first semiconductor device11and the second semiconductor device12in the semiconductor package structure100on PCB. FIG.2Bis a schematic diagram showing by comparison a relatively long path for powering a first and a second semiconductor devices in a different semiconductor package structure150. In the semiconductor package structure100according to the present disclosure, a first semiconductor device11and a second semiconductor device12are disposed on a same side of a redistribution structure40. In particular, the second semiconductor device12is disposed between the first semiconductor device11and the redistribution structure40. Referring toFIG.2B, the semiconductor package structure150includes semiconductor devices and components similar to those of the semiconductor package structure100. However, in the semiconductor package structure150, a first semiconductor device211and a second semiconductor device212are disposed on different sides of a redistribution structure240. In particular, the redistribution structure240is disposed between the first semiconductor device211and the second semiconductor device212. As to the powering path, a voltage V is provided from the PCB via a first electrical contacts81P, a first wiring route (not shown) on the RDL structure240, a first conductor125P, the second semiconductor device212, and then a second conductor125P, a second wiring route (not shown) in the RDL structure240, and a first conductive stud115P towards the first semiconductor device211, forming a powering path. The powering path, as compared to that described and illustrated inFIG.2A, is relatively long for powering the first semiconductor device211in the semiconductor package structure150on PCB. The semiconductor package structure150described and illustrated with reference toFIG.2Bmay employ one of advanced solutions: using a wafer redistribution (RDL) line fabrication process to create an application processor substrate, which may have lower losses due to smaller via sizes, lower dielectric materials and thinner layers. The challenge is that a bottom decoupling capacitor may still have solder balls and I/Os still have to travel through RDL layers to get to the application processor die disposed atop the bottom decoupling capacitor. Lots of losses occur in this path, reducing performance. In addition, the connections between bottom/top additional packages may be limited due to pitch. From the perspective of a circuit, a decoupling capacitor is placed in front of a power input node of a load such as a processor, and functions to bypass noise and reduce instances of current spikes or starvation in an associated power supply rail. Placing a decoupling capacitor farther away from an associated power or ground pin may result in unwanted inductance and resistance, and hence electrical losses. In contrast, placing a decoupling capacitor closer to an associated power or ground pin may bypass more inductance, and hence result in less electrical loss. In the semiconductor package structure100according to the present disclosure, the second semiconductor device12(playing the role of a decoupling capacitor) is directly bonded to the first semiconductor device11(the processor) without routing for electrical connection to each other through additional intermediate semiconductor structures or components that would otherwise be required in some existing approaches, including the semiconductor package structure150. A person having ordinary skill in the art can readily understand that the relatively long path in the semiconductor package structure150illustrated inFIG.2Bmay incur more parasitic effects than the relatively short path in the semiconductor package structure100illustrated inFIG.2A. As a result, the electrical losses can be significantly reduced in the semiconductor package structure100. FIG.3Ais a cross-sectional view of a semiconductor package structure200in accordance with another embodiment of the present disclosure. Referring toFIG.3A, the semiconductor package structure200includes a first semiconductor device11, a second semiconductor device12and a substrate50(the “interposer”), which are all sealed in an encapsulating layer31. The encapsulating layer31has a first surface31aand a second surface31bopposite to the first surface31a. The substrate50substantially surrounds the first semiconductor device11and the second semiconductor device12, and supports signal transmission in the semiconductor package structure200. In an embodiment, the substrate50includes a coreless substrate51. Alternatively, the substrate50may include a wafer-based redistribution structure instead of a coreless substrate to suit different design rules, and a direct redistribution layer (RDL) plating technology for copper vias may be used. In the case of a coreless substrate as in the present embodiment, the coreless substrate51includes wiring layers and micro vias in electrical connection with the wiring layers. Furthermore, first conductive pads55(the upper pads) and second conductive pads58(the lower pads) of the coreless substrate51serve as input/output (I/O) pads for electrical connection of the wiring layers to other semiconductor devices, components or structures. As shown inFIG.3A, the first conductive pads55are disposed adjacent to the first surface31aof the encapsulating layer31, and in electrical connection with the first redistribution structure40. Communication throughout the wiring layers is accomplished by micro vias instead of plated through holes. The coreless substrate51may be used as direct pass through for signal transmission in a substantially vertical direction. Moreover, the coreless substrate51may facilitate additional routing for signal transmission via different wiring layers in a substantially transverse direction. Furthermore, passive devices may be embedded in the wiring layers of the coreless substrate51so that the coreless substrate51can be used with desirable area efficiency. In some embodiments, the coreless substrate51takes the form of a continuous ring or a continuous rectangle.FIG.4Ais a schematic top view of an exemplary coreless substrate51having a continuous, rectangular shape. The continuous rectangle may be formed by preparing a complete, rectangle coreless substrate in a separate manufacturing process, and then removing a center portion thereof for accommodation of a first semiconductor device11by using, for example, a laser cutting process. In other embodiments, the coreless substrate51includes separate sections that collectively form a ring or rectangular contour.FIG.4Bis a schematic top view of an exemplary coreless substrate51including discrete sections501,502,503. These sections501,502,503may be formed in a separate manufacturing process, and then are individually attached onto the carrier21(FIG.7). Referring back toFIG.3A, the semiconductor package structure200also includes a first redistribution structure40(the “redistribution structure”) disposed on the first surface31aof the encapsulating layer31, and a second redistribution structure60(the “first additional redistribution structure”) disposed on the second surface31bof the encapsulating layer31. The first redistribution structure40may include several dielectric layers and conductive layers. For convenience, only a dielectric layer42and a conductive layer45are shown. Likewise, the second redistribution structure60includes a dielectric layer62and a conductive layer65, even though it may include several dielectric layers and conductive layers. As shown inFIG.3A, the second conductive pads58are disposed adjacent to the second surface31bof the encapsulating layer31, and in electrical connection with the second redistribution structure60(the “first additional redistribution structure”). The semiconductor package structure200further includes one or more third semiconductor devices70, which are attached to the first redistribution structure40. Each of the third semiconductor devices70includes conductive vias75and I/O pads78for signal transmission. In the present embodiment, the third semiconductor devices70are arranged in a stack. In an embodiment, the third semiconductor device70includes a memory, for example, a wide I/O memory such as a high bandwidth memory (HBM). A wide I/O memory may include more than six hundred (600) I/O counts, for example, 2,000 to 5,000 I/O counts. Communication between the first semiconductor device11and the third semiconductor device70is accomplished by an electrical path routing from the first semiconductor device11via a conductive pillar112, a conductive layer45in the first redistribution structure40, and an I/O pad78towards the third semiconductor device70, and vice versa. The semiconductor package structure200also includes electrical contacts82mounted on the second redistribution structure60for electrical connection to, for example, an external device, component or structure such as a substrate, an interposer, a PCB or the like. Communication between the first semiconductor device11and the external device is accomplished by an electrical path routing from the first semiconductor device11via a conductive pillar112, a conductive layer45in the first redistribution structure40, an upper pad55of the coreless substrate51in electrical connection with the conductive layer45, wiring layers in the coreless substrate51, a conductive layer65in the second redistribution structure60, an electrical contact82, and an electrical connection with the conductive layer65towards the PCB, and vice versa. In the semiconductor package structure200, the second semiconductor device12is directly bonded to the first semiconductor device11. Like the semiconductor package structure100described and illustrated with reference toFIG.1, by bonding the first semiconductor device11and the second semiconductor device12, the transmission path is shortened while the resistivity of materials due to intermediate layers that would otherwise exist in some existing approaches is minimized. Moreover, by placing components, which may include the first redistribution structure40and the third semiconductor devices70, to be served (to be decoupled) by the second semiconductor device12(a decoupling capacitor) closer to the first semiconductor device11, likewise the transmission path is shortened and the impedance is reduced. In addition, powering the first semiconductor device11and the second semiconductor device12is accomplished in a relatively short path. As a result, the semiconductor package structure200also benefits from the bonding configuration and may ensure less electrical loss. Furthermore, in the semiconductor package structure200, the first semiconductor device11is placed “face-up” with the first surface11a(the active surface) facing towards the third semiconductor device70. Such configuration, with the help of the conductive pillars112, facilitates routing between the first semiconductor device11and the third semiconductor device70disposed above the first semiconductor device11. The face-up first semiconductor device11directly communicates with the second semiconductor device12though the bonded joints135, and communicates with the third semiconductor device70through the first redistribution structure40. FIG.3Bis a cross-sectional view of a semiconductor package structure300in accordance with yet another embodiment of the present disclosure. Referring toFIG.3B, the semiconductor package structure300is similar to the semiconductor package structure200described and illustrated with reference toFIG.3Aexcept that, for example, the first semiconductor device11is placed “face-down” with the first surface11a(the active surface) facing towards the electrical contacts82. When the semiconductor package structure300is attached to an external structure such as a PCB via the electrical contacts82, a significant portion of the encapsulating layer31that surrounds the second semiconductor device12is disposed between the first semiconductor device11and the PCB, which provides desirable mechanical reliability. In addition, direct connection between the first semiconductor device11and the second semiconductor device12through the bonded joints135helps alleviate parasitic effects and thus reduces electrical losses. FIG.3Cis a cross-sectional view of a semiconductor package structure200ain accordance with yet another embodiment of the present disclosure. Referring toFIG.3C, the semiconductor package structure200ais similar to the semiconductor package structure200described and illustrated with reference toFIG.3Aexcept that, for example, the coreless substrate51is replaced by a pre-molded carrier51a. The pre-molded carrier51aincludes a main body52a, a plurality of through vias53aand at least one routing layer54a. A material of the main body52amay be a molding compound. The through vias53aextend through the main body52a. A bottom portion of the through via53amay be electrically connected to the second conductive pad58. The routing layer54amay be disposed on the main body52a, and may electrically connect the through vias53aand the first conductive pads55. Since materials of the encapsulating layer31and the main body52aof the pre-molded carrier51amay be both molding compounds, their coefficients of thermal expansion (CTEs) may be the same or be very close, thus, when the pre-molded carrier51ais sealed in the encapsulating layer31, a warpage of the encapsulating layer31is reduced. In addition, the Dk/Df electrical properties are improved. FIG.3Dis a cross-sectional view of a semiconductor package structure300ain accordance with yet another embodiment of the present disclosure. Referring toFIG.3D, the semiconductor package structure300ais similar to the semiconductor package structure300described and illustrated with reference toFIG.3Bexcept that, for example, the coreless substrate51is replaced by a pre-molded carrier51a. The pre-molded carrier51aincludes a main body52a, a plurality of through vias53aand at least one routing layer54a. A material of the main body52amay be a molding compound. The through vias53aextend through the main body52a. A bottom portion of the through via53amay be electrically connected to the second conductive pad58. The routing layer54amay be disposed on the main body52a, and may electrically connect the through vias53aand the first conductive pads55. Since materials of the encapsulating layer31and the main body52aof the pre-molded carrier51amay be both molding compounds, their coefficients of thermal expansion (CTEs) may be the same or be very close, thus, when the pre-molded carrier51ais sealed in the encapsulating layer31, a warpage of the encapsulating layer31is reduced. In addition, the Dk/Df electrical properties are improved. FIG.5Ais a cross-sectional view of a semiconductor package structure400in accordance with an embodiment of the present disclosure. Referring toFIG.5A, the semiconductor package structure400includes a first semiconductor device11, a second semiconductor device12bonded to the first semiconductor device11, a coreless substrate51, a first redistribution structure40(the “second additional redistribution structure”), a second redistribution structure60(the “first additional redistribution structure”) and a third redistribution structure90(the “redistribution structure”). The first semiconductor device11and the coreless substrate51are sealed in a first encapsulating layer31(the “additional encapsulating layer”). Moreover, the first semiconductor device11, the first encapsulating layer31(the “additional encapsulating layer”), the second semiconductor device12and the conductive pillars (including the first conductive pillars812and the second conductive pillars822) are sealed in a second encapsulating layer32(the “encapsulating layer”). The first semiconductor device11includes conductive pads119at a first surface11a. The first redistribution structure40includes a conductive layer45, which further includes a first portion451disposed on the conductive pads119of the first semiconductor device11, and a second portion452disposed on second conductive pads58of the coreless substrate51. The first conductive pads55and the second conductive pads58are substantially flush with the first surface11aand the second surface11bof the first semiconductor device11, respectively. In the present embodiment, the first semiconductor device11may include densely spaced I/O's with a relatively tight spacing. For example, the conductive pads119of the first semiconductor device11are arranged at a finer pitch than the conductive studs125of the second semiconductor device12, or are arranged at a finer pitch than the conductive layer95in the third redistribution structure90. The first portion451of the conductive layer45is disposed on the conductive pads119of the first semiconductor device11to facilitate fan-out of the I/O's on the conductive pads119. Furthermore, first conductive pillars812are disposed on the first portion451to help the fan-out. In addition, the semiconductor package structure400includes second conductive pillars822disposed on the second portion452to provide electrical connection between the first redistribution structure40and the third redistribution structure90. The second conductive pillars822may help signal fan-out, which is desirable for a first semiconductor device11that has a relatively tight spacing. The semiconductor package structure400further includes one or more third semiconductor devices70, which are attached to the third redistribution structure90. Communication between the first semiconductor device11and the third semiconductor devices70is accomplished by an electrical path routing from the first semiconductor device11via the first portion451of the conductive layer45in the first redistribution structure40, a first conductive pillar812on the first portion451, a conductive layer95in the third redistribution structure90, and an I/O pad78towards the third semiconductor device70, and vice versa. The second redistribution structure60, disposed on the second surface11bof the first semiconductor device11, includes a dielectric layer62and a conductive layer65. Electrical contacts82such as solder balls are disposed on the second redistribution structure60for electrical connection of the first semiconductor device11to an external device such as a PCB. Communication between the first semiconductor device11and the PCB is accomplished by an electrical path routing from the first semiconductor device11via the first portion451of the conductive layer45in the first redistribution structure40, a first conductive pillar812on the first portion451, the conductive layer95in the third redistribution structure90, a second conductive pillar822on the coreless substrate51, a second portion452of the conductive layer45on the coreless substrate51, wiring layers in the coreless substrate51, a first pad55of the coreless substrate51, a conductive layer65in the second redistribution structure60, and an electrical contact82towards the PCB, and vice versa. In the semiconductor package structure400, the second semiconductor device12is directly bonded to the first semiconductor device11. Like the semiconductor package structure100described and illustrated with reference toFIG.1, by bonding the first semiconductor device11and the second semiconductor device12, the transmission path is shortened while the resistivity of materials due to intermediate layers that would otherwise exist in some existing approaches is minimized. Moreover, by placing components, which may include the first redistribution structure40, the third semiconductor devices70and the third redistribution structure90, to be served (to be decoupled) by the second semiconductor device12(a decoupling capacitor) closer to the first semiconductor device11, likewise the transmission path is shortened and the impedance is reduced. In addition, powering the first semiconductor device11and the second semiconductor device12is accomplished in a relatively short path. As a result, the semiconductor package structure400also benefits from the direct bonding configuration and may ensure less electrical loss. Furthermore, in the semiconductor package structure400, the first semiconductor device11is placed “face-up” with the first surface11a(the active surface) facing towards the third semiconductor device70. Such configuration, with the help of the first conductive pillars812and the second conductive pillars822, facilitates routing between the first semiconductor device11and the third semiconductor device70disposed above the first semiconductor device11. The face-up first semiconductor device11directly communicates with the second semiconductor device12through the bonded joints135, and communicates with the third semiconductor device70through the first redistribution structure40and the third redistribution structure90. FIG.5Bis a cross-sectional view of a semiconductor package structure500in accordance with an embodiment of the present disclosure. Referring toFIG.5B, the semiconductor package structure500is similar to the semiconductor package structure400described and illustrated with reference toFIG.5Aexcept that, for example, the first semiconductor device11is placed “face-down” with the first surface11a(the active surface) facing towards the electrical contacts82. When the semiconductor package structure500is attached to an external structure such as a PCB via the electrical contacts82, a significant portion of the second encapsulating layer32that surrounds the second semiconductor device12is disposed between the first semiconductor device11and the PCB, which provides desirable mechanical reliability. In addition, direct connection between the first semiconductor device11and the second semiconductor device12through the bonded joints135helps alleviate parasitic effects and thus reduces electrical losses. FIG.6is a cross-sectional view of a semiconductor package structure600in accordance with still another embodiment of the present disclosure. Referring toFIG.6, the semiconductor package structure600includes a first semiconductor device11, a second semiconductor device12, a first redistribution structure40and a second redistribution structure60. The first semiconductor device11is sealed in a first encapsulating layer31. In addition, the second semiconductor device12and the first encapsulating layer31are sealed in a second encapsulating layer32. The first semiconductor device11includes conductive pads119at a first surface11a. The first redistribution structure40, disposed on the first surface11aof the first semiconductor device11and a first surface31aof the first encapsulating layer31, includes a conductive layer45. A first portion451of the conductive layer45is disposed on the conductive pads119at the first surface11aof the first semiconductor device11. A second portion452of the conductive layer45is disposed on the first surface31aof the first encapsulating layer31and is separate from the first portion451. The second semiconductor device12is bonded to the first semiconductor device11, forming bonded joints135therebetween. Similar to the embodiment described and illustrated with reference to inFIG.5A, in the present embodiment, the first semiconductor device11may include densely spaced I/O's with a relatively tight spacing. Specifically, the conductive pads119of the first semiconductor device11are arranged at a finer pitch than those of the second semiconductor device12. The first portion451of the conductive layer45is disposed on the conductive pads119of the first semiconductor device11to facilitate fan-out of the I/O's on the conductive pads119. Moreover, the semiconductor package structure600includes first conductive pillars812disposed on the first portion451and extending between the first redistribution structure40and the second redistribution structure60to provide electrical connection for the first semiconductor device11. The semiconductor package structure600also includes second conductive pillars822disposed on the second portion452and extending between the first redistribution structure40and the second redistribution structure60to help fan-out. In the semiconductor package structure600, the second semiconductor device12is directly bonded to the first semiconductor device11. Like the semiconductor package structure100described and illustrated with reference toFIG.1, by bonding the first semiconductor device11and the second semiconductor device12, the transmission path is shortened while the resistivity of materials due to intermediate layers that would otherwise exist in some existing approaches is minimized. Moreover, powering the first semiconductor device11and the second semiconductor device12is accomplished in a relatively short path. As a result, the semiconductor package structure600benefits from the direct bonding configuration and may ensure less electrical loss. Moreover, a significant portion of the second encapsulating layer32that surrounds the second semiconductor device12is disposed between the first semiconductor device11and an external device such as a PCB, which provides desirable mechanical reliability. FIG.7AthroughFIG.7Fare cross-sectional views each illustrating one or more stages of a method of manufacturing the semiconductor package structure100as described and illustrated with reference toFIG.1, in accordance with an embodiment of the present disclosure. Referring toFIG.7A, a first semiconductor device11, which has a first surface11aand a second surface11bopposite to the first surface11a, is formed on a wafer. Conductive pillars112and conductive studs115for electrical connection to other devices, components or structures are formed on conductive pads119at the first surface11a(the “active surface”). Thus, the conductive pillars112are formed over the first surface11a(the “active surface”) of the first semiconductor device11. As described earlier, the first semiconductor device11includes a digital processing device. Suitable materials for the conductive pillars112and conductive studs115may include copper (Cu), gold (Au), aluminum (Al), palladium (Pd) or solder, or an alloy thereof. Referring toFIG.7B, a second semiconductor device12is provided. The second semiconductor device12, prepared in another manufacturing process, includes conductive studs125formed on a first surface121thereof. The second semiconductor device12is placed face-down towards the first surface11aof the first semiconductor device11so that the conductive studs125correspond in position to the conductive studs115. Subsequently, the second semiconductor device12is bonded to the first semiconductor device11(an arrow showing the movement). As described earlier, the second semiconductor device12includes a decoupling capacitor. Suitable materials for the conductive studs125may include copper (Cu), gold (Au), aluminum (Al), palladium (Pd) or solder, or an alloy thereof. In some embodiments, the conductive studs115and125contact each other directly. For example, the conductive studs115and125are bonded to each other in a copper-to-copper (Cu-to-Cu) directly bonding process, as will be discussed in detail with reference toFIGS.8A to8H. Alternatively, the conductive studs115and125may be bonded to each other in a solder-joint bonding process, as will be discussed in detail with reference toFIGS.10A to10E. The first semiconductor device11bonded with the second semiconductor device12is then separated from other semiconductor devices in a wafer dicing process. Referring now toFIG.7C, a carrier21with a release film210is provided. The first semiconductor device11, currently in the form of a semiconductor die or chip after wafer dicing, is attached at the second surface11bthereof onto the release film210. The carrier21functions to support semiconductor components, devices or structures to be subsequently formed or disposed thereon. In an embodiment, the carrier21includes organic materials, for example, Bismaleimide Triazine (BT), polyimide (PI), Ajinomoto build-up film (ABF), or other suitable materials. Alternatively, the carrier21includes inorganic materials, for example, silicon, glass, or other suitable materials. The release film210functions to facilitate release of the carrier21from a semiconductor structure temporarily held by the carrier21. In an embodiment, the release film210includes non-metallic materials, for example, PI, ABF, epoxy, molding compound, solder mask ink, or other suitable materials. Additionally, the release film210is optional and thus may be omitted. Referring toFIG.7D, an encapsulating layer310is formed on the carrier21, covering the first semiconductor device11and the second semiconductor device12. The encapsulating layer310may include a molding compound. Referring toFIG.7E, the encapsulating layer310is then reduced in height by, for example, a grinding process such as a mechanical polishing process, resulting in a reduced encapsulating layer31. The reduced encapsulating layer31exposes the conductive pillars112. The carrier21together with the release film210is then removed. In some embodiments, the carrier21includes a glass carrier, which may be removed in a laser debonding process. Next, referring toFIG.7F, a redistribution structure40is formed on the reduced encapsulating layer31. The redistribution structure40functions to provide interconnection and may include a dielectric layer42and a conductive layer45. The redistribution structure40is in electrical connection with the first semiconductor device11via the conductive elements (the conductive pillars112). In an embodiment, the dielectric layer42includes organic materials, for example, a molding compound, polyamide (PA), polyimide (PI), polybenzoxazole (PBO) or an epoxy-based material. In another embodiment, the dielectric layer42includes inorganic materials, for example, silicon oxide (SiOx), silicon nitride (SiNx) or tantalum oxide (TaOx). In addition, the conductive layer45includes titanium (Ti), a titanium-tungsten alloy (TiW), nickel (Ni), copper (Cu), a titanium-copper alloy (TiCu), silver (Ag), gold (Au) or other suitable conductive materials. Subsequently, referring back toFIG.1, electrical contacts81are mounted on a surface42aof the redistribution structure40over the reduced encapsulating layer31. The electrical contacts81provide electric connection between the first semiconductor device11and an external structure (not shown). In an embodiment, the electrical contacts81may include solder balls, which may be arranged in a ball grid array “BGA”. In another embodiment, the electrical contacts81may include metal pads arranged in a land grid array (LGA). In yet another embodiment, the electrical contacts81may include leads arranged in a pin grid array (PGA). Moreover, the electrical contacts81may include controlled collapse chip connection (C4) bumps, which include lead based or lead-free bumps or balls. FIG.8AthroughFIG.8Hare cross-sectional views each illustrating one or more stages of an exemplary method of forming a bonded joint135between a first semiconductor device11and a second semiconductor device12in the semiconductor package structure100as described and illustrated with reference toFIG.1. The exemplary method includes forming a conductive stud on an input/output (I/O) pad of the first semiconductor device11in a copper-to-copper (Cu-to-Cu) directly bonding process, and separately forming a conductive stud on an I/O pad of the second semiconductor device12in a hybrid bonding process, as will be discussed below. Referring toFIG.8A, for the first semiconductor device11, initially a dielectric layer161is formed on a first surface11aof a substrate160of the first semiconductor device11by, for example, a chemical vapor deposition (CVD) process. The first semiconductor device11includes I/O pads119at the surface11aof the substrate160. The dielectric layer161may include oxide, for example, silicon oxide (SiOx). Next, a patterned photoresist layer162is formed on the dielectric layer161, exposing portions of the dielectric layer161through openings168. These exposed portions correspond in position to the I/O pads119of the first semiconductor device11. Referring toFIG.8B, the exposed portions of the dielectric layer161are removed by, for example, an etching process, resulting in a patterned dielectric layer171. The patterned dielectric layer171exposes the I/O pads119through the openings168. The patterned photoresist layer162is then removed. Referring toFIG.8C, a first conductive layer163is formed on the patterned dielectric layer171and the exposed I/O pads119in, for example, a sputtering process. The first conductive layer163is substantially conformal to the topology of the patterned dielectric layer171, and serves as a seed layer for a subsequent conductive layer to be formed thereon. In an embodiment, the first conductive layer163includes a titanium (Ti) layer and a copper layer stacked on the titanium layer. Next, referring toFIG.8D, a second conductive layer164, a third conductive layer165and a fourth conductive layer166are formed in sequence on the first conductive layer163by using, for example, a plating process. Specifically, the second conductive layer164is conformally formed on the first conductive layer163, the third layer165is conformally formed on the second conductive layer164, and the fourth conductive layer166fills up the openings168while being formed on the third conductive layer165. In an embodiment, the second conductive layer164includes copper, the third conductive layer165includes nickel (Ni), and the fourth conductive layer166includes solder, for example, an alloy of tin and silver (SnAg). As such, the second conductive layer164, a copper layer, ensures desirable conductivity. In addition, the fourth conductive layer166, an SnAg layer, provides desirable fusibility that facilitates creating a bond. Moreover, the third conductive layer165, a nickel layer, prevents electrochemical corrosion between the copper layer164and the SnAg layer166so as to ensure the desired conductivity and a robust bond. Referring now toFIG.8E, the first, second, third and fourth conductive layers163,164,165and166are patterned by using, for example, a grinding process such as a chemical mechanical polishing (CMP) process, resulting in a patterned first, second, third and fourth conductive layer173,174,175and176, which together constitute a conductive stud115as illustrated inFIG.1. The patterned dielectric layer171is exposed and planarized after the grinding process, which facilitates bonding between the conductive stud115and a corresponding conductive stud125. As to the second semiconductor device12, referring toFIG.8F, a patterned first, second, third and fourth conductive layer273,274,275and276, which together constitute a conductive stud125as illustrated inFIG.1, are formed on an I/O pad129at a first surface121of a substrate260of the second semiconductor device12in a similar fashion as described and illustrated with reference toFIGS.8A to8E. As a result, a patterned dielectric layer271on the substrate260is exposed and planarized. Referring toFIG.8G, the second semiconductor device12is bonded to the first semiconductor device11. Specifically, the conductive stud125of the second semiconductor device12are bonded to their corresponding conductive studs115of the first semiconductor device11in a “hybrid bonding” process. “Hybrid bonding” combines a dielectric bond with embedded metal to form an interconnection. Initially, a dielectric bond between the dielectric layers271and171, when come in contact with each other, is formed by Van der Waals force at room temperature, resulting in a bonded dielectric layer371, as illustrated inFIG.8H. Next, a thermal process is conducted to force the patterned second conductive layers274and174to form a bonded joint135. The exemplary bonding process as described and illustrated with reference toFIGS.8A to8Hmay be conducted at a wafer level stage. Subsequently, a first semiconductor device11, with a second semiconductor device12bonded thereto, is singulated in a wafer dicing process. FIG.9Ais a cross-sectional view illustrating a method of forming a bonded joint between a first semiconductor device11and a second semiconductor device12in the semiconductor package structure100as described and illustrated with reference toFIG.1, in accordance with another embodiment of the present disclosure. The method is similar to that described and illustrated with reference toFIGS.8A through8Hexcept, for example, conductive studs525of the second semiconductor device12. Specifically, conductive studs515of the first semiconductor device11are identical with or similar to the conductive studs115ofFIG.8G. The conductive studs525of the second semiconductor device12may only include the patterned first conductive layer273and a patterned second conductive layer574. To form a bonded joint, similarly, a dielectric bond between the dielectric layers271and171is formed at room temperature, and subsequently a metal bond is formed by the patterned second conductive layers174and574by using a thermal process. FIG.9Bis a cross-sectional view illustrating a method of forming a bonded joint between a first semiconductor device11and a second semiconductor device12in the semiconductor package structure100as described and illustrated with reference toFIG.1, in accordance with yet another embodiment of the present disclosure. The method is similar to that described and illustrated with reference toFIGS.8A through8Hexcept, for example, conductive studs515of the first semiconductor device11. Specifically, conductive studs525of the second semiconductor device12are identical with or similar to the conductive studs125ofFIG.8F. The conductive studs515of the first semiconductor device11may only include the patterned first conductive layer173and a patterned second conductive layer674. To form a bonded joint, similarly, a dielectric bond between the dielectric layers271and171is formed at room temperature, and subsequently a metal bond is formed by the patterned second conductive layers674and274by using a thermal process. FIG.9Cis a cross-sectional view illustrating a method of forming a bonded joint between a first semiconductor device11and a second semiconductor device12in the semiconductor package structure100as described and illustrated with reference toFIG.1, in accordance with still yet another embodiment of the present disclosure. Referring toFIG.9C, the conductive studs515of the first semiconductor device11may only include the patterned first conductive layer173and a patterned second conductive layer674. In addition, the conductive studs525of the second semiconductor device12may only include the patterned first conductive layer273and a patterned second conductive layer574. To form a bonded joint, similarly, a dielectric bond between the dielectric layers271and171is formed at room temperature, and subsequently a metal bond is formed by the patterned second conductive layers574and674by using a thermal process. FIG.10AthroughFIG.10Eare cross-sectional views each illustrating one or more stages of another method of forming a bonded joint135between a first semiconductor device11and a second semiconductor device12in the semiconductor package structure100as described and illustrated with reference toFIG.1. Referring toFIG.10A, a patterned dielectric layer181is formed on a first surface11aof the first semiconductor device11by using, for example, a photolithographic process, exposing I/O pads119from openings188. The patterned dielectric layer181may include polyimide. Referring toFIG.10B, a patterned conductive layer115is formed on the patterned dielectric layer181and the conductive pads119by using a plating process followed by an etching process. The patterned conductive layer115includes conductive studs to bond with conductive studs of a second semiconductor device12. Subsequently, referring toFIG.10C, conductive pillars112are formed on I/O pads119in a fashion similar to forming the conductive studs115. Referring toFIG.10D, a second semiconductor device12is provided. The second semiconductor device12includes a patterned conductive layer125formed on a patterned dielectric layer281and I/O pads129. The patterned conductive layer125includes conductive studs to bond with the conductive studs115of the first semiconductor device11. Next, the conductive studs125of the second semiconductor device12are bonded to the conductive studs115of the first semiconductor device11with the help of, for example, solder681, resulting in bonded joints135as illustrated inFIG.10E. FIG.11AthroughFIG.11Eare cross-sectional views each illustrating one or more stages of a method of manufacturing the semiconductor package structure200as described and illustrated with reference toFIG.3A, in accordance with yet another embodiment of the present disclosure. Referring toFIG.11A, similar to the operation described and illustrated with reference toFIG.7C, a carrier21with a release film210is provided. Subsequently, a first semiconductor device11bonded with a second semiconductor device12is attached at a second surface11bthereof onto the release film210. Furthermore, a substrate51is attached to the release film210. The substrate51may include a coreless substrate. Referring toFIG.11B, an encapsulating layer310is formed on the carrier21, covering the first semiconductor device11, the second semiconductor device12and the coreless substrate51. Afterwards, referring toFIG.11C, the encapsulating layer310is reduced in height by, for example, a grinding process such as a mechanical polishing process, resulting in a reduced encapsulating layer31. The reduced encapsulating layer31exposes from a first surface31athereof the conductive pillars112of the first semiconductor device11and the upper pads55of the coreless substrate51. Referring toFIG.11D, the carrier21together with the release film210is then removed, exposing from a second surface31bof the reduced encapsulating layer31the second surface11bof the first semiconductor device11and the lower pads58of the coreless substrate51. The second surface31bis opposite to the first surface31aof the reduced encapsulating layer31. Subsequently, a first redistribution structure40is formed on the first surface31aof the reduced encapsulating layer31. The first redistribution structure40functions to provide electrical connection and may include several dielectric layers and conductive layers. For convenience, only a dielectric layer42and a conductive layer45are shown. Referring toFIG.11E, a second redistribution structure60is formed on the second surface31bof the reduced encapsulating layer31and the second surface11bof the first semiconductor device11. Similarly, the second redistribution structure60functions to provide electrical connection, and may include several dielectric layers and conductive layers. For convenience, only a dielectric layer62and a conductive layer65are shown. Suitable materials for the second dielectric layer62and the second conductive layer65are similar to or the same as those for the dielectric layer42and the conductive layer45, respectively, as described with reference toFIG.7F, and thus are not further discussed. Next, referring back toFIG.3A, a stack of third semiconductor devices70is attached on the first redistribution structure40. The third semiconductor device70includes a high bandwidth memory (HBM). In addition, electrical contacts82are mounted on the second redistribution structure60. Suitable materials and deployment for the electrical contacts82are similar to or the same as the electrical contacts81as described with reference toFIG.1, and thus are not further discussed. The semiconductor package structure300ofFIG.3Bmay be manufactured by a method similar to that described and illustrated with reference toFIGS.11A to11Eexcept that, for example, in the operation ofFIG.11Ea stack of third semiconductor devices70is attached on the second redistribution structure60, and electrical contacts82are mounted on the first redistribution structure40. FIG.12AthroughFIG.12Care cross-sectional views each illustrating one or more stages of a method of manufacturing the semiconductor package structure200as described and illustrated with reference toFIG.3A, in accordance with another embodiment of the present disclosure. Referring toFIG.12A, the first semiconductor device11is similar to that described and illustrated with reference toFIG.3Aexcept that, for example, conductive pillars512are taller than the conductive pillars112. As a result, by setting the conductive pillars512as a grinding stop, after a grinding process as conducted inFIG.11Cto reduce the encapsulating layer310, the conductive pillars512are exposed from the reduced encapsulating layer31, while the coreless substrate51is still covered by the reduced encapsulating layer31. Next, referring toFIG.12B, the reduced encapsulating layer31is patterned by, for example, a laser drilling process, exposing upper pads55of the coreless substrate51through openings57. Subsequently, referring toFIG.12C, a first redistribution structure40is formed on the first surface31aof the patterned, reduced encapsulating layer31. During forming the first redistribution structure40, a conductive layer45fills in the openings57and electrically connects the upper pads55and the conductive pillars512. The remaining operations are similar to or the same as those described and illustrated with reference toFIGS.11E and3Aand thus are not further discussed. FIG.13AthroughFIG.13Dare cross-sectional views each illustrating one or more stages of a method of manufacturing the semiconductor package structure200as described and illustrated with reference toFIG.3A, in accordance with yet another embodiment of the present disclosure. Referring toFIG.13A, the structure is similar to that described and illustrated with reference toFIG.11Aexcept that, for example, additional pillars522are formed on the upper pads55of the coreless substrate51. The additional pillars522of the coreless substrate51are substantially flush with the conductive pillars112of the first semiconductor device11. Referring toFIG.13B, an encapsulating layer310is formed on the carrier21, covering conductive pillars112of the first semiconductor device11, the second semiconductor device12and the additional pillars522of the coreless substrate51. Afterwards, referring toFIG.13C, the encapsulating layer310is reduced in height by, for example, a grinding process such as a mechanical polishing process, resulting in a reduced encapsulating layer31. The reduced encapsulating layer31exposes from a first surface31athereof the conductive pillars112of the first semiconductor device11and the additional pillars522of the coreless substrate51. Subsequently, referring toFIG.13D, a first redistribution structure40is formed on the first surface31aof the reduced encapsulating layer31. During forming the first redistribution structure40, a conductive layer45electrically connects the additional pillars522of the coreless substrate51and the conductive pillars112of the first semiconductor device11. The remaining operations are similar to or the same as those described and illustrated with reference toFIGS.11E and3Aand thus are not further discussed. FIG.14AthroughFIG.14Jare cross-sectional views each illustrating one or more stages of a method of manufacturing the semiconductor package structure400as described and illustrated with reference toFIG.5A, in accordance with an embodiment of the present disclosure. Referring toFIG.14A, a first carrier21with a first release film210is provided. Subsequently, a first semiconductor device11is attached at a first surface11athereof onto the first release film210. The first semiconductor device11includes conductive pads119at the first surface11a. In addition, a coreless substrate51is also attached to the first release film210. The coreless substrate51includes first pads55and second pads58. In attaching the first semiconductor device11, the conductive pads119of the first semiconductor device11and the second pads58of the coreless substrate51are attached to the first release film210. Referring toFIG.14B, a first encapsulating layer310is formed on the release film210, covering the first semiconductor device11and the coreless substrate51. The first carrier21together with the first release film210is then removed, exposing the first surface11aand the conductive pads119of the first semiconductor device11, and the second pads58of the coreless substrate51. Next, referring toFIG.14C, a first redistribution structure40is formed on the first surface11aof the first semiconductor device11. The first redistribution structure40includes a conductive layer45, which further includes a first portion451disposed on the conductive pads119of the first semiconductor device11and a second portion452disposed on the second pads58of the coreless substrate51. Afterwards, first pillars812are formed on the first portion451of conductive layer45, and second pillars822are formed on the second portion452of conductive layer45. Suitable materials for the first and second pillars812,822are similar to or the same as those for the conductive pillars112as described with reference toFIG.3A. Subsequently, referring toFIG.14D, a second semiconductor device12is bonded to the first semiconductor device11, forming bonded joints135therebetween. Referring toFIG.14E, the first encapsulating layer310is reduced in thickness by a grinding process, resulting in a reduced first encapsulating layer31. The reduced first encapsulating layer31exposes the second surface11bof the first semiconductor device11and the first pads55of the coreless substrate51. Then, referring toFIG.14F, a second carrier22with a second release film220is provided. The package structure as illustrated in inFIG.14Eis attached at the second surface11bonto the second release film220. Thereafter, a second encapsulating layer320is formed on the second release film220, covering the package structure, including the reduced first encapsulating layer31that seals the first semiconductor device11and the coreless substrate51, and the second semiconductor device12. The second carrier22together with the second release film220is then removed, exposing the second surface11band the first pads55of the coreless substrate51. Referring now toFIG.14G, a second redistribution structure60is formed on the second surface11bof the first semiconductor device11and the first pads55of the coreless substrate51. The second redistribution structure60includes a second dielectric layer62and a second conductive layer65. Portions of the second conductive layer65form electrical connection with the first pads55of the coreless substrate51. Next, referring toFIG.14H, the second encapsulating layer320is reduced in height by a grinding process, resulting in a reduced second encapsulating layer32. The reduced second encapsulating layer32exposes from a first surface32athereof the first and second conductive pillars812,822. Referring toFIG.14I, a third redistribution structure90is then formed on the first surface32aof the reduced second encapsulating layer32. The third redistribution structure90includes a third dielectric layer92and a third conductive layer95. Portions of the conductive layer95form electrical connection with the first and second conductive pillars812and822, which in turn are electrically connected with the first portion451and the second portion452of the conductive layer45, respectively. Suitable materials for the third dielectric layer92and the third conductive layer95are similar to or the same as those for the dielectric layer42and the conductive layer45, respectively, as described with reference toFIG.7F. Subsequently, referring toFIG.14J, electrical contacts82are mounted on the second redistribution structure60for electrical connection of the first semiconductor device11to, for example, a PCB. Now referring back toFIG.5A, a stack of third semiconductor devices70is attached on the third redistribution structure90. The third semiconductor device70includes a high bandwidth memory (HBM). The semiconductor package structure500ofFIG.5Bmay be manufactured by a method similar to that described and illustrated with reference toFIGS.14A to14Iexcept that, for example, after the operation ofFIG.14Ia stack of third semiconductor devices70is attached on the second redistribution structure60, and electrical contacts82are mounted on the first redistribution structure40. FIG.15AthroughFIG.15Hare cross-sectional views each illustrating one or more stages of a method of manufacturing the semiconductor package structure600as described and illustrated with reference toFIG.6, in accordance with an embodiment of the present disclosure. Referring toFIG.15A, a first carrier21with a first release film210is provided. Subsequently, a first semiconductor device11is attached at a first surface11athereof onto the first release film210. The first semiconductor device11includes conductive pads119at the first surface11a. Referring toFIG.15B, a first encapsulating layer310is formed on the release film210, covering the first semiconductor device11. The first carrier21together with the first release film210is then removed, exposing the first surface11aand the conductive pads119of the first semiconductor device11. Next, referring toFIG.15C, a first redistribution structure40is formed on the first surface11aof the first semiconductor device11. The first redistribution structure40includes a conductive layer45, which further includes a first portion451and a second portion452separate from the first portion451. Thereafter, first and second conductive pillars812,822are formed on the conductive layer45to provide electrical connection for the conductive pads119of the first semiconductor device11. Subsequently, referring toFIG.15D, a second semiconductor device12is bonded to the first semiconductor device11. Referring toFIG.15E, the first encapsulating layer310is reduced in thickness by a grinding process, resulting in a reduced first encapsulating layer31. The reduced first encapsulating layer31exposes a second surface11bof the first semiconductor device11and the first surface31aof the reduced first encapsulating layer31. Next, referring toFIG.15F, a second carrier22with a second release film220is provided. The package structure as illustrated in inFIG.15Eis attached at the second surface11bonto the second release film220. Optionally, a passive device88such as an inductor may also be attached onto the second release film220. Thereafter, a second encapsulating layer320is formed on the second release film220, covering the passive device88, if any, the package structure including the reduced first encapsulating layer31that seals the first semiconductor device11, and the second semiconductor device12. After the second encapsulating layer320is formed, the second carrier22together with the second release film220is removed, exposing the second surface11band the first surface31aof the reduced first encapsulating layer31. Referring toFIG.15G, the second encapsulating layer320is reduced in height by a grinding process, resulting in a reduced second encapsulating layer32. The reduced second encapsulating layer32exposes from a first surface32athereof the first and second conductive pillars812,822. Subsequently, referring toFIG.15H, a second redistribution structure60is formed on the first surface32aof the reduced second encapsulating layer32. The second redistribution structure60includes a second dielectric layer62and a second conductive layer65. Portions of the second conductive layer65form electrical connection with the first and second conductive pillars812and822. Now referring back toFIG.6, electrical contacts82are mounted on the second redistribution structure60. The second redistribution structure60and the electrical contacts82function to provide electrical connection of the first semiconductor device11to, for example, a PCB. As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure. | 68,686 |
11862588 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In accordance with various embodiments, redistribution lines are formed over a semiconductor substrate, and UBMs are formed coupled to the redistribution lines. The UBMs are formed to a large width such that they overlap multiple underlying redistribution lines, optionally including underlying redistribution lines to which the UBMs are not coupled (e.g., dummy redistribution lines or other functional redistribution lines). Forming the UBMs to a large size allows for a greater contact area (which may reduce contact resistance) and allows for greater flexibility in the routing of the redistribution lines. FIGS.1through7are cross-sectional views of intermediate stages in the manufacturing of an integrated circuit die50, in accordance with some embodiments. The integrated circuit die50will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die50may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), the like, or combinations thereof. The integrated circuit die50may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die50may be processed according to applicable manufacturing processes to form integrated circuits. InFIG.1, a semiconductor substrate52is provided. The semiconductor substrate52may be silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52has an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a back side. Devices are formed at the active surface of the semiconductor substrate52. The devices may be active devices (e.g., transistors, diodes, etc.) or passive devices (e.g., capacitors, inductors, resistors, etc.). The inactive surface may be free of devices. An interconnect structure54is formed over the active surface of the semiconductor substrate52, and is used to electrically connect the devices of the semiconductor substrate52to form an integrated circuit. The interconnect structure54may include one or more dielectric layer(s) and respective metallization pattern(s) in the dielectric layer(s). Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide, aluminum oxide, or the like; nitrides such as silicon nitride; carbides such as silicon carbide; combinations thereof; or the like. The dielectric layer(s) may be formed of low-k (LK) dielectrics such as carbon doped oxides, extremely low-k (ELK) dielectrics such as porous carbon doped silicon dioxide, or the like. Other acceptable dielectric materials include photosensitive polymers such as polyimide, polybenzoxazole (PBO), a benzocyclobutene (BCB) based polymer, combinations thereof, or the like. The metallization patterns may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate52. The metallization patterns may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure54may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. Contact pads56are formed at the front side of the integrated circuit die50. The contact pads56may be pads, conductive pillars, or the like, to which external connections are made. The contact pads56are in and/or on the interconnect structure54. For example, the contact pads56may be part of an upper metallization pattern of the interconnect structure54. When the contact pads56are part of the upper metallization pattern of the interconnect structure54, the upper metallization pattern can have a feature density of at least 20%. The contact pads56can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. A dielectric layer58is at the front side of the integrated circuit die50. The dielectric layer58is in and/or on the interconnect structure54. For example, the dielectric layer58may be an upper dielectric layer of the interconnect structure54. The dielectric layer58laterally surrounds the contact pads56. The dielectric layer58may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer58may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments (not separately illustrated), the integrated circuit die50is a stacked device that includes multiple semiconductor substrates52. For example, the integrated circuit die50may be a memory device that includes multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In such embodiments, the integrated circuit die50includes multiple semiconductor substrates52interconnected by through-substrate vias (TSVs), such as through-silicon vias. Each of the semiconductor substrates52may (or may not) have an interconnect structure54. One or more passivation layer(s)60are formed on the dielectric layer58and the contact pads56(e.g., on the interconnect structure54). In the illustrated embodiment, the passivation layer(s)60include a first passivation layer60A on the interconnect structure54, and a second passivation layer60B on the first passivation layer60A. The passivation layer(s)60may be formed of one or more acceptable dielectric materials, such as silicon oxide, silicon nitride, low-k (LK) dielectrics such as carbon doped oxides, extremely low-k (ELK) dielectrics such as porous carbon doped silicon dioxide, combinations thereof, or the like. Other acceptable dielectric materials include photosensitive polymers such as polyimide, polybenzoxazole (PBO), a benzocyclobutene (BCB) based polymer, combinations thereof, or the like. The passivation layer(s)60may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, or the like. Passive devices62are optionally formed among the passivation layer(s)60(e.g., between the first passivation layer60A and the second passivation layer60B). The passive devices62include capacitors, inductors, resistors, and the like. In some embodiments, the passive devices are metal-insulator-metal (MIM) devices, such as super high density MIM (SHDMIM) devices. As an example to form the passivation layer(s)60and the passive devices62, the first passivation layer60A may be deposited and recesses may be patterned in the first passivation layer60A, such as by using an acceptable etching process. Once the recesses have been patterned in the first passivation layer60A, a series of metal layers and insulating layers may be deposited within the recesses and over the first passivation layer60A to form a three dimensional corrugated stack of metal layers separated by the insulating layers. The corrugated stack forms MIM devices. Contacts may be formed through the layers of the corrugated stack, electrically connecting the metal layers of the MIM devices to the metallization patterns of the interconnect structure54(e.g., to some of the contact pads56). The passive devices62may thus be electrically coupled to the devices of the semiconductor substrate52. The second passivation layer60B may then be deposited on the passive devices62and the first passivation layer60A. InFIG.2, openings64are patterned in the passivation layer(s)60to expose portions of the contact pads56. The patterning may be formed by an acceptable process, such as by exposing the passivation layer(s)60to light when they are formed of photosensitive material(s) or by etching the passivation layer(s)60using, for example, an anisotropic etch. If the passivation layer(s)60are formed of photosensitive material(s), they can be developed after the exposure. When the passive devices62are formed, the openings64can be patterned around the passive devices62, such that the openings64are disposed between adjacent passive devices62. InFIG.3, redistribution lines66are formed. The redistribution lines66have trace portions66T on and extending along the top surface of the passivation layer(s)60(e.g., the top surface of the second passivation layer60B). For example, the trace portions66T are conductive lines that extend lengthwise parallel to a major surface of the semiconductor substrate52. At least some of the redistribution lines66also have one or more via portions66V in respective ones of the openings64(e.g., extending through the passivation layer(s)60) that are physically and electrically coupled to the contact pads56. Some of the redistribution lines66are functional redistribution lines66F (seeFIG.11) and some redistribution lines66are dummy redistribution lines66D (seeFIG.11). The functional redistribution lines66F are electrically coupled to devices (e.g., the passive devices62and/or the devices of the semiconductor substrate52), and may have both trace portions66T and via portions66V. The dummy redistribution lines66D are not electrically coupled to devices (e.g., the passive devices62and/or the devices of the semiconductor substrate52), and may have only trace portions66T and may not have via portions66V. The dummy redistribution lines66D may provide mechanical support for under bump metallizations (UBMs) that will be subsequently formed over the dummy redistribution lines66D. As an example to form the redistribution lines66, a seed layer66S is formed on the top surface of the passivation layer(s)60and in the openings64(e.g., on the exposed portions of the contact pads56). In some embodiments, the seed layer66S is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer66S includes a titanium layer and a copper layer over the titanium layer. The seed layer66S may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist (not separately illustrated) is then formed and patterned on the seed layer66S. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the redistribution lines66. The patterning forms openings through the photoresist to expose the seed layer66S. A conductive material66C is then formed in the openings of the photoresist and on the exposed portions of the seed layer66S. The conductive material66C may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material66C may include a metal, such as copper, silver, cobalt, titanium, tungsten, aluminum, combinations thereof, or the like. For example, the conductive material66C may be copper, a copper-silver alloy, or a copper-cobalt alloy, plated using the seed layer66S. Then, the photoresist and portions of the seed layer66S on which the conductive material66C is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer66S are removed, such as by using an acceptable etching process. The remaining portions of the seed layer66S and conductive material66C form the redistribution lines66. The redistribution lines66may have any type of top surfaces, given the application of the integrated circuit die50to be formed. In the illustrated embodiment the redistribution lines66have convex top surfaces. In another embodiment, the redistribution lines66can have flat top surfaces, concave top surfaces, or polygonal top surfaces. The trace portions66T may also have any type of sidewalls, given the application of the integrated circuit die50to be formed. In the illustrated embodiment the trace portions66T have substantially vertical sidewalls that are spaced apart by a constant width. In another embodiment, the trace portions66T have sidewalls that are spaced apart by a tapering width that decreases in a direction extending away from the semiconductor substrate52. InFIG.4, a dielectric layer72and/or a dielectric layer74are formed. One or both of the dielectric layers72,74may be formed. In the embodiment described forFIG.4, both of the dielectric layers72,74are formed. In another embodiment (subsequently described forFIG.12), the dielectric layer74is formed and the dielectric layer72is omitted. In yet another embodiment (subsequently described forFIG.13), the dielectric layer72is formed and the dielectric layer74is omitted. The dielectric layer72is formed on the redistribution lines66and the top surface of the passivation layer(s)60. The dielectric layer72may be formed of one or more acceptable dielectric materials such as silicon oxide, silicon nitride, low-k (LK) dielectrics such as carbon doped oxides, extremely low-k (ELK) dielectrics such as porous carbon doped silicon dioxide, combinations thereof, or the like. Other acceptable dielectric materials include photosensitive polymers such as polyimide, polybenzoxazole (PBO), a benzocyclobutene (BCB) based polymer, combinations thereof, or the like. The dielectric layer72may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, or the like. In some embodiments, the dielectric layer72is a passivation layer. The dielectric layer72is formed to a thickness T1(seeFIG.11), which can be in the range of about 0.3 μm to about 3 μm. The dielectric layer74is formed on the dielectric layer72(if present) or on the redistribution lines66and the top surface of the passivation layer(s)60(when the dielectric layer72is not present). The dielectric layer74may be formed of one or more acceptable dielectric materials, such as photosensitive polymers, such as polyimide, polybenzoxazole (PBO), a benzocyclobutene (BCB) based polymer, combinations thereof, or the like. Other acceptable dielectric materials include silicon oxide, silicon nitride, low-k (LK) dielectrics such as carbon doped oxides, extremely low-k (ELK) dielectrics such as porous carbon doped silicon dioxide, combinations thereof, or the like. The dielectric layer74may be formed by spin coating, lamination, deposition (e.g., CVD), combinations thereof, or the like. After the dielectric layer74is formed, it may be planarized, such as by chemical mechanical polishing (CMP), so that the front side of the integrated circuit die50is planar. The dielectric layer74is formed to a thickness T2(seeFIG.11), which can be in the range of about 5 μm to about 21 μm. In some embodiments, the dielectric layer72is formed by a process that has good gap-filling properties. For example, the dielectric layer72may be formed of an oxide or a nitride by CVD or ALD, which can have step coverage in the range of about 20% to about 95%. In some embodiments, the dielectric layer74is formed by a process that has a low cost. For example, the dielectric layer74may be formed of a polyimide by spin coating. Forming both of the dielectric layers72,74may allow the areas (e.g., gaps76) between the redistribution lines66to be substantially filled, such that no voids remain between the redistribution lines66, while low manufacturing costs are maintained. InFIG.5, openings78are patterned in the dielectric layer72and/or the dielectric layer74to expose portions of the redistribution lines66. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer72and/or the dielectric layer74to light when they are formed of photosensitive material(s) or by etching the dielectric layer72and/or the dielectric layer74using, for example, an anisotropic etch. If the dielectric layer72and/or the dielectric layer74are formed of photosensitive material(s), they can be developed after the exposure. In some embodiments, the openings78are formed by an acceptable etch, such as an anisotropic etch, even when the dielectric layer72and/or the dielectric layer74are formed of photosensitive material(s). The widths of the openings78will be subsequently described in greater detail. InFIG.6, UBMs82are formed for external connection to the integrated circuit die50. The UBMs82may be controlled collapse chip connection (C4) bumps, micro bumps, conductive pillars, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The UBMs82have bump portions82B on and extending along the top surface of the dielectric layer74(if present) or the dielectric layer72(if present). The UBMs82also have via portions82V in the openings78(e.g., extending through the dielectric layer74(if present) and/or the dielectric layer72(if present)) that are physically and electrically coupled to the redistribution lines66. As a result, the UBMs82are electrically coupled to devices (e.g., the passive devices62and/or the devices of the semiconductor substrate52). The UBMs82may be formed of the same material(s) as the redistribution lines66. In some embodiments, the UBMs82have a different size than the redistribution lines66. As will be subsequently described in greater detail, the UBMs82are formed to a large size, such that they overlap a plurality of the redistribution lines66. As an example to form the UBMs82, a seed layer82S is formed on the top surface of the dielectric layer74(if present) or the dielectric layer72(if present) and in the openings78(e.g., on the exposed portions of the redistribution lines66). In some embodiments, the seed layer82S is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer82S includes a titanium layer and a copper layer over the titanium layer. The seed layer82S may be formed using, for example, PVD or the like. A photoresist (not separately illustrated) is then formed and patterned on the seed layer82S. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the UBMs82. The patterning forms openings through the photoresist to expose the seed layer82S. A conductive material82C is then formed in the openings of the photoresist and on the exposed portions of the seed layer82S. The conductive material82C may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material82C may include a metal, such as copper, titanium, tungsten, aluminum, gold, cobalt, or the like, plated using the seed layer82S. Then, the photoresist and portions of the seed layer82S on which the conductive material82C is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer82S are removed, such as by using an acceptable etching process. The remaining portions of the seed layer82S and conductive material82C form the UBMs82. In some embodiments, a metal cap layer is formed on the top surfaces of the UBMs82. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. The UBMs82may have any desired quantity of via portions82V and may be coupled to any desired quantity of underlying redistribution lines66, given the application of the integrated circuit die50to be formed. In the illustrated embodiment, a UBM82has a plurality of via portions82V, with each via portion82V of the UBM being physically and electrically coupled to a corresponding underlying redistribution line66, while other underlying redistribution lines66are physically and electrically separated from the UBM82by the dielectric layers72,74. In another embodiment, a UBM82has a single via portion82V that is physically and electrically coupled to a single underlying redistribution line66, such that other underlying redistribution lines66are physically and electrically separated from the UBM82by the dielectric layers72,74. In yet another embodiment, UBMs82with diverse quantities of via portions82V are formed. For example, a first subset of the UBMs82may have a first quantity of via portions82V (e.g., one via portion82V), and a second subset of the UBMs82may have a second quantity of via portions82V (e.g., more than one via portions82V), with the first quantity being different from the second quantity. As will be subsequently described in greater detail, each via portion82V of a UBM82is disposed directly over a via portion66V of the corresponding underlying redistribution line66. When a UBM82is coupled to multiple underlying redistribution lines66, those redistribution lines66may each be coupled to a same contact pad56(as illustrated) or to different contact pads56(not separately illustrated). Further, the UBMs82may be coupled to underlying redistribution lines66that are routed in any manner, given the application of the integrated circuit die50to be formed. In the illustrated embodiment, a UBM82is physically and electrically coupled to underlying redistribution lines66that are routed adjacent to one another. In another embodiment, a UBM82is physically and electrically coupled to underlying redistribution lines66that are not routed adjacent to one another. For example, the UBM82may be physically and electrically coupled to first redistribution lines66, and the first redistribution lines66may be separated from one another by a second redistribution line66, with the UBM82not being physically and electrically coupled to the second redistribution line66. Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the UBMs82. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die50. CP testing may be performed on the integrated circuit die5oto ascertain whether the integrated circuit die5ois a known good die (KGD). Thus, only integrated circuit dies50, which are KGDs, undergo subsequent processing (e.g., are packaged), and devices, which fail the CP testing, do not undergo subsequent processing (e.g., are not packaged) in some embodiments. After testing, the solder regions may be removed. InFIG.7, conductive connectors84are formed on the UBMs82. The conductive connectors84may be ball grid array (BGA) connectors, solder balls, or the like. The conductive connectors84may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors84are formed by initially forming a layer of solder material on the UBMs82through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder material has been formed on the UBMs82, a reflow may be performed in order to shape the solder material into desired bump shapes. Additional processing may be performed to complete formation of the integrated circuit die50. For example, when the integrated circuit die50is formed in a wafer that includes different device regions, the device regions may be singulated to form a plurality of integrated circuit dies50. The singulation process may include sawing along scribe line regions, e.g., between the device regions of the wafer. The sawing singulates device regions of the wafer from one another, and the resulting integrated circuit die50is from one of the device regions. Referring toFIGS.8A through11, additional features of the integrated circuit die50are described.FIGS.8A,8B,9A,9B,10A, and10Bare top-down views of integrated circuit dies50, in accordance with various embodiments.FIG.11is a detailed view of a region50R fromFIG.7, showing additional details of the integrated circuit die50, in accordance with some embodiments. Some features of the integrated circuit dies50are omitted from these figures for illustration clarity. As noted above, the UBMs82may be one of several types of bumps. In some embodiments, the UBMs82are micro bumps. In some embodiments, the UBMs82are C4 bumps. Integrated circuit dies50may have different features depending whether the UBMs82are micro bumps or C4 bumps. The trace portions66T of the redistribution lines66extend lengthwise along the top surface of the passivation layer(s)60, such as in the Y-direction. The trace portions66T of the redistribution lines66have a width W1in the X-direction and a length in the Y-direction, with the length being greater than the width W1. When the UBMs82are micro bumps, the width W1can be in the range of about 1.5 μm to about 10 μm. When the UBMs82are C4 bumps, the width W1can be in the range of about 5 μm to about 45 μm. The trace portions66T of the redistribution lines66have a height H1in the Z-direction. When the UBMs82are micro bumps, the height H1can be in the range of about 3 μm to about 6 μm. When the UBMs82are C4 bumps, the height H1can be in the range of about 3 μm to about 6 μm. The via portions66V of the redistribution lines66can have the same width W2in the X-direction and the Y-direction, or can have different widths W2in the X-direction and the Y-direction. When the UBMs82are micro bumps, the width W2in the X-direction can be in the range of about 1 μm to about 2.7 μm, and the width W2in the Y-direction can be in the range of about 1 μm to about 4.5 μm. When the UBMs82are C4 bumps, the width W2in the X-direction can be in the range of about 1.8 μm to about 2.7 μm, and the width W2in the Y-direction can be in the range of about 1.8 μm to about 4.5 μm. In some embodiments, different redistribution lines66of a same integrated circuit die50have via portions66V of different widths W2. The trace portions66T of the redistribution lines66are spaced apart by a spacing distance S1in the X-direction, and the via portions66V of the redistribution lines66are spaced apart by a spacing distance S2in the X-direction. The spacing distance S1can be greater than or equal to the width W1, and the spacing distance S2can be greater than or equal to the width W2. When the UBMs82are micro bumps, the spacing distance S1can be in the range of about 0.2 μm to about 5 μm and the spacing distance S2can be in the range of about 2 μm to about 6 μm. When the UBMs82are C4 bumps, the spacing distance S1can be in the range of about 0.5 μm to about 15 μm and the spacing distance S2can be in the range of about 2 μm to about 20 μm. The trace portions66T of the redistribution lines66can have a feature density in the range of about 55% to about 85%. The UBMs82are formed to a large size, such that they overlap a plurality of the redistribution lines66. The UBMs82overlap the redistribution lines66in a direction (e.g., the X-direction) that is perpendicular to the lengthwise direction of the redistribution lines66(e.g., the Y-direction). The UBMs82have a width W3in the X-direction, which is greater than the sum of the width W1of each underlying redistribution line66and the spacing distance S1between each underlying redistribution line66. When the UBMs82are micro bumps, the width W3can be in the range of about 5 μm to about 22 μm. When the UBMs82are C4 bumps, the width W3can be in the range of about 20 μm to about 90 μm. Forming the UBMs82to a large size allows for a greater contact area (which may reduce contact resistance) and allows for greater flexibility in the routing of the redistribution lines66. In various embodiments, the UBMs82may only overlap the redistribution lines66to which they are coupled (as shown byFIGS.8A and8B); the UBMs82may overlap the redistribution lines66to which they are coupled and only partially overlap adjacent redistribution lines66(as shown byFIGS.9A and9B); or the UBMs82may overlap the redistribution lines66to which they are coupled and fully overlap adjacent redistribution lines66(as shown byFIGS.10A and10B). Further, the UBMs82may only overlap the via portions66V of the redistribution lines66to which they are coupled (as shown byFIGS.8A and8B); the UBMs82may overlap the via portions66V of the redistribution lines66to which they are coupled and may only partially overlap the via portions66V of adjacent redistribution lines66(as shown byFIGS.9A and9B); or the UBMs82may overlap the via portions66V of the redistribution lines66to which they are coupled and may fully overlap the via portions66V of adjacent redistribution lines66(as shown byFIGS.10A and10B). As noted above, some redistribution lines66are functional redistribution lines66F and some redistribution lines66are dummy redistribution lines66D. A UBM82is coupled to one or more functional redistribution lines66F, and thus overlaps at least those redistribution lines66. When the UBM82overlaps but is not coupled to adjacent redistribution lines66, those adjacent redistribution lines66may be functional redistribution lines66F (which are coupled to other UBMs82) or may be dummy redistribution lines66D (which are not coupled to other UBMs82). Forming a UBM82to overlap dummy redistribution lines66D may provide mechanical support for the UBM82when no functional redistribution lines66F are available for placement beneath the UBM82. Each via portion82V of a UBM82is disposed directly over a via portion66V of the corresponding underlying redistribution line66, such that the centers of each corresponding pair of via portions66V,82V are laterally aligned with one another along the X-direction and the Y-direction. The strength of the connections between layers may thus be increased. Various features may be aligned along the Y-direction or may be disposed at different locations along the Y-direction. In various embodiments, the via portions66V,82V are laterally aligned with the center of their corresponding bump portion82B along the Y-direction (as shown byFIGS.8A,9A, and10A); or the via portions66V,82V are laterally offset from the center of their corresponding bump portion82B along the Y-direction (as shown byFIGS.8B,9B, and10B). When the UBMs82are micro bumps, the via portions66V,82V may be laterally aligned with or laterally offset from the center of their corresponding bump portion82B along the Y-direction. When the UBMs82are C4 bumps, via portions66V,82V are laterally offset from the center of their corresponding bump portion82B along the Y-direction, and are not laterally aligned with the center of their corresponding bump portion82B along the Y-direction. Although a single UBM82and a single conductive connector84are illustrated, it should be appreciated that a plurality of UBMs82and a plurality of conductive connectors84are formed. The UBMs82can have a uniform pitch, or can have diverse pitches. When the UBMs82are micro bumps, they can have a uniform or diverse pitches, with the pitch(es) being in the range of about 10 μm to about 50 μm. When the UBMs82are C4 bumps, they can have a uniform pitch, with the pitch being in the range of about 40 μm to about 140 μm. The via portions82V of the UBMs82have upper widths W4(corresponding to the target widths of the openings78, seeFIG.5), and lower width W5(also referred to as the critical dimensions of the via portions82V). The upper widths W4may be greater than the lower width W5, particularly in embodiments where the dielectric layer74is formed. The via portions82V have different widths W4, W5in the X-direction and the Y-direction. Specifically, the widths W4, W5in the X-direction are less than the widths W4, W5in the Y-direction. When the UBMs82are micro bumps, the widths W4, W5in the X-direction can be in the range of about 0 μm to about 22 μm, and the widths W4, W5in the Y-direction can be in the range of about 0 μm to about 36 μm. When the UBMs82are C4 bumps, the width W4in the X-direction can be in the range of about 8 μm to about 78 μm, the widths W4in the Y-direction can be in the range of about 20 μm to about 40 μm, the width W5in the X-direction can be in the range of about 6 μm to about 79 μm, and the width W5in the Y-direction can be in the range of about 6 μm to about 79 μm. The via portions82V of the UBMs82have a height H2in the Z-direction. The height H2depends on which of the dielectric layers72,74are formed, but at least is greater than or equal to the thickness T1and is less than the thickness T2. When the UBMs82are micro bumps, the height H2can be in the range of about 2 μm to about 15 μm. When the UBMs82are C4 bumps, the height H2can be in the range of about 2 μm to about 15 μm. The bump portions82B of the UBMs82may have substantially vertical sidewalls, while the via portions82V of the UBMs82may have slanted sidewalls. The sidewalls of each via portion82V form an angle θ1with the top surface of the dielectric layer74, and form an angle θ2with the top surface of the underlying redistribution line66. The angle θ1is greater than the angle θ2. When the UBMs82are micro bumps, the angle θ1can be in the range of about 10 degrees to about 180 degrees, and the angle θ2can be in the range of about 10 degrees to about 90 degrees. When the UBMs82are C4 bumps, the angle θ1can be in the range of about 10 degrees to about 180 degrees, and the angle θ2can be in the range of about 10 degrees to about 90 degrees. In the illustrated embodiments, the bump portions82B of the UBMs82have octagonal shapes in the top-down views. The bump portions82B of the UBMs82may have other shapes in the top-down views, such as rounded shapes (e.g., circular shapes, oval shapes, etc.) or other polygon shapes (e.g., hexagon shapes, quadrilateral shapes, etc.) FIG.12is a cross-sectional view of an integrated circuit die50, in accordance with some embodiments. This embodiment is similar to the embodiment ofFIG.7, except the dielectric layer74is formed and the dielectric layer72is omitted. The manufacturing complexity of the integrated circuit die50may thus be reduced. Omitting the dielectric layer72may be possible when the dielectric layer74is formed by a process that has good gap-filling properties. For example, the dielectric layer74may be formed of an oxide or a nitride by CVD. As a result, the areas (e.g., gaps76) between the redistribution lines66may still be substantially filled, even when the dielectric layer72is omitted. The integrated circuit die50may have any of the features previously described forFIGS.8A through11. FIG.13is a cross-sectional view of an integrated circuit die50, in accordance with some embodiments. This embodiment is similar to the embodiment ofFIG.7, except the dielectric layer72is formed and the dielectric layer74is omitted. The manufacturing complexity of the integrated circuit die50may thus be reduced. Omitting the dielectric layer74allows the UBMs82to also be formed with extension portions82X in a subset of the areas (e.g., gaps76) between the redistribution lines66. The bottom surfaces of the extension portions82X are disposed closer to the semiconductor substrate52than the bottom surfaces of the via portions82V. By forming the extension portions82X, the UBMs82may interface with more surfaces in different planes, decreasing the risk of the UBMs82delaminating. The reliability of the integrated circuit die50may thus be increased. Further, the areas (e.g., gaps76) between the redistribution lines66may still be substantially filled (e.g., by the extension portions82X), even when the dielectric layer74is omitted. The integrated circuit die50may have any of the features previously described forFIGS.8A through11. FIG.14is a cross-sectional view of an integrated circuit package150, in accordance with some embodiments. The integrated circuit package150is formed by bonding an integrated circuit die50to a package substrate100. The bonding process may be, e.g., a flip-chip bonding process. The integrated circuit package150is illustrated for the integrated circuit die50ofFIG.7, but it should be appreciated that any of the integrated circuit dies50described herein may be packaged to form the integrated circuit package150. After the integrated circuit die50is formed, it is flipped and attached to a package substrate100using the conductive connectors84. The package substrate100may be an interposer, a printed circuit board (PCB), or the like. The package substrate100includes a substrate core102and bond pads104over the substrate core102. The substrate core102may be formed of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate core102may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate core102is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other PCB materials or films. Build up films such as Ajinomoto Build-up Film (ABF) or other laminates may be used for substrate core102. The substrate core102may include active and/or passive devices (not separately illustrated). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional designs for the device stack. The devices may be formed using any suitable methods. The substrate core102may also include metallization layers and vias (not separately illustrated), with the bond pads104being physically and/or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate core102is substantially free of active and passive devices. In some embodiments, the conductive connectors84are reflowed to attach the integrated circuit die50to the bond pads104. The conductive connectors84electrically and/or physically couple the package substrate100, including metallization layers in the substrate core102, to the integrated circuit die50. In some embodiments, a solder resist106is formed on the substrate core102. The conductive connectors84may be disposed in openings in the solder resist106to be electrically and mechanically coupled to the bond pads104. The solder resist106may be used to protect areas of the package substrate100from external damage. The conductive connectors84may have an epoxy flux (not separately illustrated) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the integrated circuit die50is attached to the package substrate100. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors84. In some embodiments, an underfill (not separately illustrated) may be formed between the integrated circuit die50and the package substrate100, surrounding the conductive connectors84. The underfill may be formed by a capillary flow process after the integrated circuit die50is attached or may be formed by a suitable deposition method before the integrated circuit die50is attached. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not separately illustrated) may also be attached to the integrated circuit die50(e.g., to the UBMs82) or to the package substrate100(e.g., to the bond pads104). For example, the passive devices may be bonded to a same surface of the integrated circuit die50or the package substrate100as the conductive connectors84. The passive devices may be attached to the integrated circuit die50prior to mounting the integrated circuit die50to the package substrate100, or may be attached to the package substrate100prior to or after mounting the integrated circuit die50to the package substrate100. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. Embodiments may achieve advantages. As noted above, the UBMs82are formed to a large width such that they overlap multiple underlying redistribution lines66, possibly including underlying redistribution lines66to which the UBMs82are not coupled (e.g., dummy redistribution lines66D or other functional redistribution lines66F). Forming the UBMs82to a large size allows for a greater contact area (which may reduce contact resistance) and allows for greater flexibility in the routing of the redistribution lines66. Further, in some embodiments, the UBMs82are formed with extension portions82X in areas between the underlying redistribution lines66. By forming the extension portions82X, the UBMs82may interface with more surfaces in different planes, decreasing the risk of the UBMs82delaminating. The reliability of the integrated circuit die50may thus be increased. In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line. In some embodiments of the device, the first redistribution line and the second redistribution line extend lengthwise along the passivation layer in a first direction, and the bump portion fully overlaps the first redistribution line and partially overlaps the second redistribution line in a second direction, the second direction perpendicular to the first direction. In some embodiments of the device, the first redistribution line and the second redistribution line extend lengthwise along the passivation layer in a first direction, and the bump portion fully overlaps the first redistribution line and fully overlaps the second redistribution line in a second direction, the second direction perpendicular to the first direction. In some embodiments of the device, the second redistribution line is a functional redistribution line, and the first dielectric layer is disposed between the under bump metallization and the functional redistribution line. In some embodiments of the device, the second redistribution line is a dummy redistribution line, and the first dielectric layer is disposed between the under bump metallization and the dummy redistribution line. In some embodiments of the device, the under bump metallization has a second via portion, the second via portion extending through the first dielectric layer to be physically and electrically coupled to the second redistribution line. In some embodiments of the device, the first redistribution line has a trace portion and a second via portion, the trace portion disposed on and extending along the passivation layer, the second via portion extending through the passivation layer, a center of the first via portion laterally aligned with a center of the second via portion. In some embodiments of the device, a center of the bump portion is laterally aligned with the center of the first via portion and the center of the second via portion. In some embodiments of the device, a center of the bump portion is laterally offset from the center of the first via portion and the center of the second via portion. In an embodiment, a device includes: a first passivation layer on a semiconductor substrate; a first redistribution line on and extending along the first passivation layer, the first redistribution line having a first width; a second redistribution line on and extending along the first passivation layer, the second redistribution line having a second width, the second redistribution line separated from the first redistribution line by a first distance; a first dielectric layer on the first redistribution line, the second redistribution line, and the first passivation layer; and an under bump metallization on the first dielectric layer, the under bump metallization coupled to the first redistribution line and the second redistribution line, the under bump metallization having a third width, the third width being greater than the sum of the first width, the second width, and the first distance. In some embodiments, the device further includes: a second passivation layer between the first passivation layer and the semiconductor substrate; and a passive device between the second passivation layer and the first passivation layer. In some embodiments of the device, the first dielectric layer includes an oxide or a nitride, and the device further includes: a second dielectric layer between the first dielectric layer and the under bump metallization, the second dielectric layer including a polyimide, the first dielectric layer and the second dielectric layer filling an area between the first redistribution line and the second redistribution line. In some embodiments of the device, the first dielectric layer includes a polyimide, and the device further includes: a second dielectric layer between the first dielectric layer and the first passivation layer, the second dielectric layer including an oxide or a nitride, the first dielectric layer and the second dielectric layer filling an area between the first redistribution line and the second redistribution line. In some embodiments of the device, the under bump metallization has a bump portion and an extension portion, the bump portion disposed on the first dielectric layer, the extension portion disposed between the first redistribution line and the second redistribution line, the first dielectric layer and the extension portion filling an area between the first redistribution line and the second redistribution line. In some embodiments, the device further includes: a package substrate; and a conductive connector bonding the package substrate to the under bump metallization. In an embodiment, a method includes: depositing a first passivation layer on a semiconductor substrate; forming a first redistribution line and a second redistribution line on and extending along the first passivation layer; forming a first dielectric layer on the first redistribution line and the second redistribution line; patterning a first opening and a second opening in the first dielectric layer, the first opening exposing the first redistribution line, the second opening exposing the second redistribution line; and forming an under bump metallization in the first opening and the second opening, the under bump metallization overlapping the first redistribution line and the second redistribution line. In some embodiments of the method, forming the first redistribution line and the second redistribution line includes: patterning a third opening and a fourth opening in the first passivation layer; and plating the first redistribution line in the third opening and the second redistribution line in the fourth opening, where a center of the first opening is laterally aligned with a center of the third opening, and where a center of the second opening is laterally aligned with a center of the fourth opening. In some embodiments of the method, the under bump metallization is further plated in an area between the first redistribution line and the second redistribution line. In some embodiments, the method further includes: forming a second dielectric layer on the first dielectric layer, the under bump metallization plated on the second dielectric layer, the first opening and the second opening further patterned in the second dielectric layer, where forming the first dielectric layer includes depositing an oxide or a nitride, and where forming the second dielectric layer includes spinning on a polyimide. In some embodiments, the method further includes: forming a second dielectric layer on the first passivation layer, the first dielectric layer formed on the second dielectric layer, the first opening and the second opening further patterned in the second dielectric layer, where forming the first dielectric layer includes spinning on a polyimide, where forming the second dielectric layer includes depositing an oxide or a nitride. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 53,226 |
11862589 | DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS FIG.1Ais a schematic cross-sectional view of a wafer-level semiconductor package according to some example embodiments of the inventive concepts.FIG.1Bis a schematic cross-sectional view of a wafer-level semiconductor package according to some example embodiments of the inventive concepts. Referring toFIG.1A, a wafer-level semiconductor package100amay include a semiconductor chip110, a mold layer120, a first passivation layer130, a redistribution layer140, a second passivation layer150, an under bump metal (UBM) layer160, and/or a solder bump170. For example, the wafer-level semiconductor package100amay be a fan-out wafer-level semiconductor. The semiconductor chip110may be, for example, a memory chip, a logic chip, or the like. When the semiconductor chip110is a memory chip or a logic chip, the semiconductor chip110may be variously designed considering operations to be performed. When the semiconductor chip110is a memory chip, the memory chip may be, for example, a non-volatile memory chip or a volatile memory chip. The non-volatile memory chip may be a flash memory chip, for example, a NAND flash memory chip, a NOR flash memory chip, or the like. The volatile memory chip may be dynamic random access memory (DRAM), static RAM (SRAM), or embedded RAM but is not limited thereto. When the semiconductor chip110is a logic chip, the logic chip may include a central processing unit (CPU) or a graphics processing unit (GPU). The semiconductor chip110may include a connection pad112. The connection pad112may be disposed on a first surface110aof the semiconductor chip110(a bottom surface of the semiconductor chip110on the basis ofFIG.1A). As shown inFIG.1A, the connection pad112may be disposed in the semiconductor chip110or disposed on the bottom surface of the semiconductor chip110. AlthoughFIG.1Aillustrates a case in which four connection pads112are formed, the inventive concepts are not limited thereto. The connection pad112may include a conductive material such as aluminum (Al) or the like. The mold layer120may cover a sidewall of the semiconductor chip110and expose the first surface110aon which the connection pad112is disposed. The mold layer120may cover a second surface110bof the semiconductor chip110, but the inventive concepts are not limited thereto. For example, the mold layer120may include an epoxy molding compound (EMC). The mold layer120may be formed to have a greater thickness than the semiconductor chip110on the outside of the semiconductor chip110and cover the second surface110bof the semiconductor chip110, but the inventive concepts are not limited thereto, and the mold layer120may have the same thickness as the semiconductor chip110on the outside of the semiconductor chip110and expose the second surface110bthe semiconductor chip110. Alternatively, the mold layer120may be formed to have a smaller thickness than the semiconductor chip110and may not cover a portion of the sidewall of the semiconductor chip110. The first passivation layer130may be disposed under the semiconductor chip110. The first passivation layer130may cover the first surface110aof the semiconductor chip110and a bottom surface of the mold layer120. A first trench T1may be formed in the first passivation layer130to expose at least a portion of the connection pad112. The first passivation layer130may include an insulating material configured to protect a lower portion of the semiconductor chip110. For example, the first passivation layer130may include at least one of an oxide film or a nitride film. The redistribution layer140extends on the first surface110aand a bottom surface of the mold layer120. The redistribution layer140may be disposed under the first passivation layer130. The redistribution layer140may partially cover a surface of the first passivation layer130. One end and the other end of the redistribution layer140may extend in both outward directions of the first trench T1along a bottom surface of the first passivation layer130. In some example embodiments, the one end of the redistribution layer140may extend lengthwise from the semiconductor chip110toward the mold layer120. One side portion of the redistribution layer140may have a different length from the other side portion thereof. The redistribution layer140may be in contact with the connection pad112through the first trench T1. The redistribution layer140may be electrically connected to the connection pad112. The redistribution layer140may be formed of a conductive material, e.g., copper, nickel, a copper alloy, or the like, so that the connection pad112may be electrically connected to the UBM layer160. The second passivation layer150may be disposed under the first passivation layer130and the redistribution layer140. The second passivation layer150may be formed of the same material as the first passivation layer130, but the inventive concepts are not limited thereto. A second trench T2may be formed in the second passivation layer150to expose at least a portion of the redistribution layer140. The UBM layer160may be disposed inside the second trench T2under the redistribution layer140. The UBM layer160may extend outwardly downward from the second trench T2and be in contact with a bottom surface of the second passivation layer150. The UBM layer160may be disposed to be collinear with the redistribution layer140and the connection pad112in a sectional view thereof. In some example embodiments, one end of the redistribution layer140may extend lengthwise toward the mold layer120, and the UBM layer160may be in contact with the lengthwise extended portion of the redistribution layer140and thus, a center of the UBM layer160may deviate from a center of the connection pad112in a top view thereof. That is, the UBM layer160may be disposed in a position that does not overlap the connection pad112. The UBM layer160may be in contact with the redistribution layer140through the second trench T2of the second passivation layer150. The UBM layer160may be electrically connected to the semiconductor chip110through the redistribution layer140and the connection pad112. For example, the UBM layer160may be formed by depositing various metals, such as copper (Cu), chromium (Cr), nickel (Ni), titanium-tungsten (TiW), nickel-vanadium (NiV), and the like, by using a sputtering process. The solder bump170may be disposed on the UBM layer160. The solder bump170may completely cover an exposed surface of the UBM layer160. That is, the solder bump170may cover a bottom surface, both outer side surfaces, and both inner side surfaces of the UBM layer160. The solder bump170may include a tin-silver (Sn—Ag)-based material. Referring toFIG.1B, a wafer-level semiconductor package100bmay include a semiconductor chip210, a connection pad112, a first passivation layer130, a redistribution layer140, a second passivation layer150, a UBM layer160, and/or a solder bump170. For example, the wafer-level semiconductor package100bmay be a fan-in wafer-level semiconductor package. In the present specification, descriptions of the fan-out wafer-level semiconductor package100aofFIG.1Amay be applied likewise to the fan-in wafer-level semiconductor package100bofFIG.1B. FIGS.2,3, and5to9are enlarged views of region A ofFIG.1Aaccording to some example embodiments.FIG.4is an enlarged view of region B ofFIG.3according to some example embodiments. Example embodiments related to region A ofFIG.1A, which are illustrated inFIGS.2,3, and5to9, may be applied likewise to region A′ ofFIG.1B. InFIGS.1A to9, the same reference numerals are used to denote the same components, and repeated descriptions thereof will be omitted below for brevity. Referring toFIGS.2,3, and5to9, a thickness H1of the UBM layer160may be in the range of 10% to 50% of a thickness H2of the solder bump170. The thickness H1of the UBM layer160may be in the range of 40% to 50% of the thickness H2of the solder bump170. For example, the thickness H2of the solder bump170refers to a maximum vertical distance from a surface of the second passivation layer150to an outer circumferential surface of the solder bump170. Further, inFIGS.1A to9, the thickness H1of the UBM layer160refers to a maximum vertical distance from the surface of the second passivation layer150to a bottom surface of the UBM layer160. When the wafer-level semiconductor package100ais mounted on a main board by means of the solder bump170, stress may be applied to the solder bump170due to a difference in coefficient of thermal expansion between the wafer-level semiconductor package100aand the main board. For example, a coefficient of thermal expansion of a package may be in the range of about 3 PPM to 4 PPM, and a coefficient of thermal expansion of a main board may be about 20 PPM. A coefficient of thermal expansion of the UBM layer160may be in the range of about 16 PPM to 17 PPM. When stress is concentrated on the wafer-level semiconductor package100a, cracks may occur in the solder bump170in the vicinity of the UBM layer160such as to cause failures in products. The cracks may be mainly formed in the solder bump170along the surface of the UBM layer160. For example, since a wafer-level package (e.g., a fan-out wafer-level package or a fan-in wafer-level package) has a smaller thickness than a main board and a lower coefficient of thermal expansion than the main board, stress may tend to concentrate on the wafer-level package. Therefore, in the inventive concepts, the thickness H1of the UBM layer160may be increased so that the bottom surface of the UBM layer160may be disposed in the vicinity of a diameter of the solder bump170. Since the solder bump170has a largest sectional area in the vicinity of the diameter of the solder bump170, stress may be dispersed, and propagated areas of cracks may be increased. As a result, reliability degradation of products due to a difference in coefficient of thermal expansion may be solved. Referring toFIGS.3and4, the solder bump170may further include a contact surface S1in contact with the bottom surface of the second passivation layer150. For instance, the contact surface S1may be formed when the amount of the solder bump170is sufficient as compared to the thickness H1of the UBM layer160. Alternatively, the contact surface S1may be formed by applying pressure to the solder bump170from a lower end of the solder bump170toward the UBM layer160. Referring toFIG.5, both outer side surfaces S2of the UBM layer160that are in contact with the solder bump170may be inclined toward an inside of the solder bump170with respect to the bottom surface of the second passivation layer150. When both of the outer side surfaces S2of the UBM layer160are inclined toward the inside of the solder bump170, the amount of the solder bump170formed outside both of the outer side surfaces S2may be larger than when both of the outer side surfaces S2are perpendicular to the bottom surface of the second passivation layer150, and the propagated areas of the cracks may be increased. Referring toFIGS.6and7, At least one of the outer side surfaces of the UBM layer160may include a curved side surface. Both outer side surfaces S3and S4of the UBM layer160in contact with the solder bump170may include curved surfaces. For example, as shown inFIG.6, both of the outer side surfaces S3of the UBM layer160may have convex shapes toward an outside of the UBM layer160. As shown inFIG.7, both of the outer side surfaces S4of the UBM layer160may have concave shapes toward an inside of the UBM layer160. Referring toFIG.8, the UBM layer160may include a first UBM layer161and a second UBM layer162. A top surface of the first UBM layer161may be in contact with the redistribution layer140. Further, the first UBM layer161may be in contact with the surface of the second passivation layer150. The second UBM layer162may be in contact with a bottom surface of the first UBM layer161. The first UBM layer162may have a different thickness from the second UBM layer162. The second UBM layer162may have a width smaller than that of the first UBM layer161. Thus, a first outer side surface OS1of the first UBM layer161and a second outer side surface OS2of the second UBM layer162may be formed to have a step D1at both side portions of the UBM layer160that are in contact with the solder bump170. Furthermore, a lowest surface of the first UBM layer161and a lowest surface of the second UBM layer162may be formed to have a step D1. Referring toFIG.9, at least one of the first outer side surface OS1and the second outer side surface OS2may be inclined toward the inside of the solder bump170with respect to the surface of the second passivation layer150. In the case ofFIGS.6to9, as shown inFIG.5, the amount of the solder bump170formed on both outer sides of the UBM layer160may be increased more than in the case ofFIG.2, and propagated areas of cracks may be increased. In the case ofFIGS.7to9, the amount of the solder bump170formed on both of the outer sides of the UBM layer160may be larger than the amount of the solder bump170formed on both of the outer sides of the UBM layer160ofFIG.5, and the propagated areas of the cracks may be further increased. FIG.10Ais a schematic cross-sectional view of a case in which a wafer-level semiconductor package according to some example embodiments of the inventive concepts is mounted on a main board of an electronic device.FIG.10Bis a schematic cross-sectional view of a case in which a wafer-level semiconductor package according to some example embodiments of the inventive concepts is mounted on a main board of an electronic device.FIGS.11,12, and14to16are enlarged cross-sectional views of region C ofFIG.10Aaccording to some example embodiments.FIG.13is an enlarged cross-sectional view of region D ofFIG.10Aaccording to some example embodiments. The example embodiment illustrated inFIGS.11,12, and14to16may be applied likewise to region C′ ofFIG.10B. InFIGS.1A to16, the same reference numerals are used to denote the same components, and repeated descriptions thereof will be omitted below for brevity. Referring toFIGS.10A and10B, the wafer-level semiconductor package100aor100bmay be mounted on a main board200of an electronic device through a solder bump175or the like. The mounted wafer-level semiconductor package100aor100band the main board200may constitute a wafer-level semiconductor package module. For example, the wafer-level semiconductor package100aor100bmay be a fan-out semiconductor package100aor a fan-in semiconductor package100b. The inventive concepts are applied to a wafer-level semiconductor package, which may be mounted on the main board200of the electronic device without an additional interposer substrate or the like. Although only the fan-out wafer-level semiconductor package100aand the fan-in wafer-level semiconductor package100bare illustrated inFIGS.10A and10B, the inventive concepts may be applied to other types of wafer-level packages. Referring toFIGS.10A and11, a thickness H3of the UBM layer160may be 50% of a thickness H4of the solder bump175. For example, inFIGS.10A to16, the thickness H4of the solder bump175refers to a vertical distance from a surface of the second passivation layer150to a surface of a terminal210that is in contact with the solder bump175on the main board200. Further, inFIGS.10A to16, the thickness H3of the UBM layer160refers to a maximum vertical distance from the surface of the second passivation layer150to a bottom surface of the UBM layer160. Referring toFIGS.12and13, in a similar manner to that described with reference toFIGS.3and4, the solder bump175may further include a contact surface S12which is in contact with a bottom surface of the second passivation layer150. For example, the contact surface S12may be formed by pressing the solder bump175against the bottom surface of the second passivation layer150with pressure applied to the solder bump175when the wafer-level semiconductor package100ais mounted on the main board200. Referring toFIG.14, outer side surfaces S22of both outer side portions of the UBM layer160may be inclined toward an inside of the UBM layer160with respect to the bottom surface of the second passivation layer150. Although the outer side surfaces S22of the UBM layer160are illustrated as straight lines inFIG.14, the outer side surfaces S22may have a curved shape as inFIGS.6and7. Referring toFIG.15, both outer side portions of the UBM layer160may have a first outer side surface OS1and a second outer side surface OS2which have a step D2. Referring toFIG.16, at least one of the first outer side surface OS1and the second outer side surface OS2may be inclined with respect to a surface of the second passivation layer150. FIGS.17to25are cross-sectional views illustrating a method of manufacturing a wafer-level package according to some example embodiments of the inventive concepts. InFIGS.1A to25, the same reference numerals are used to denote the same components, and repeated descriptions thereof will be omitted below for brevity. Only one wafer-level package is illustrated in each cross-sectional view for brevity. In an actual manufacturing process, each of the following processes may be performed simultaneously on a plurality of wafer-level packages that are individually separated from a wafer. Referring toFIG.17, a semiconductor chip110and a mold layer120configured to surround a portion of a surface of the semiconductor chip110may be formed. For example, a first surface110aof the semiconductor chip110may be adhered to a support frame (not shown) through tape. The mold layer120may be formed to cover a side surface and/or a second surface110bof the semiconductor chip110. The mold layer120may be formed by molding and curing an epoxy molding compound (EMC). The mold layer120and the semiconductor chip110may be separated from the tape, and the first surface110aof the semiconductor chip110and a connection pad112disposed on the first surface110amay be exposed. The mold layer120may have a sufficient thickness, and thus, the bending of the semiconductor chip110may be reduced or prevented when the mold layer120and the semiconductor chip110are separated from the tape. Alternatively, the support frame may be removed using a back-grinding process, and the tape may be removed using a heating process. A process of individualizing the mold layer120and the semiconductor chip11from the support frame and the tape may be performed after a UBM layer160to be described below is formed. Referring toFIG.18, a first passivation layer130may be formed on the semiconductor chip110and the mold layer120. A first trench T1may be formed in the first passivation layer130to expose the connection pad112of the semiconductor chip110. A redistribution layer140may be formed inside the first trench T1and brought into contact with the connection pad112. The redistribution layer140may be exposed outside the first trench T1and partially cover the first passivation layer130. The first passivation layer130in which the first trench T1is formed may be formed using a photolithography process including an exposure process and a developing process. Referring toFIG.19, a second passivation layer150may be formed to cover the first passivation layer130and the redistribution layer140. The second passivation layer150may be partially removed to form a second trench T2. A mask pattern155may be formed on the second passivation layer150to have an open region OP partially corresponding to the redistribution layer140, and the second passivation layer150may be etched through the open region OP to form the second trench T2. A top surface of the redistribution layer140may be partially exposed through the second trench T2. Referring toFIG.20, the mask pattern155may be removed, and a first photoresist pattern157may be formed on the second passivation layer150. The first photoresist pattern157may be formed to have a first contact hole CH1having a greater width than the second trench T2in a region corresponding to the second trench T2. The top surface of the redistribution layer140may be exposed through the first contact hole CH1and the second trench T2. A top surface of the second passivation layer150may be partially exposed through the first contact hole CH1. A UBM layer160may be formed inside the first contact hole CH1and the second trench T2. For example, the UBM layer160may be formed using an electroless plating method or an electroplating method. When the electroless plating method or the electroplating method is used, a seed layer (not shown) may be further formed between the redistribution layer140and the UBM layer160. However, a method of forming the UBM layer160according to the inventive concepts is not limited thereto, and a metal layer may be formed and patterned using an etching process. Referring toFIG.21, the first photoresist pattern157may be removed. The first photoresist pattern157may be removed using a dry or wet etching process. The first photoresist pattern157may be removed to expose both side surfaces of the UBM layer160and the top surface of the second passivation layer150. Referring toFIGS.22and23, a second photoresist pattern163may be formed on the second passivation layer150. The second photoresist pattern163may be disposed on both sides of the UBM layer160, and a second contact hole CH2may be formed to expose a top surface and both side surfaces of the UBM layer160. A distance W1between one side surface of the UBM layer160and one side surface of the second photoresist pattern163may range from 1 μm to 50 μm. A preliminary solder layer165may be formed inside the second contact hole CH2to cover the UBM layer160. The preliminary solder layer165may include a metal material. For example, the preliminary solder layer165may include tin-silver (Sn—Ag)-based metal material. Flux may be provided to the preliminary solder layer165. The preliminary solder layer165may completely cover the exposed top surface and both side surfaces of the UBM layer160. A thickness of the preliminary solder layer165may range from 1 μm to 50 μm. That is, a thickness of a portion of the preliminary solder layer165may correspond to a distance W1between one side surface of the UBM layer160and one side surface of the second photoresist pattern163. A thickness of another portion of the preliminary solder layer165may be greater than the distance W1. For instance, the preliminary solder layer165may be formed using an electroplating method or an electroless plating method. When the electroplating method or the electroless plating method is used, a seed layer (not shown) may be further formed on the second photoresist pattern163and the UBM layer160. In an embodiment, the preliminary solder layer165may be solder paste. The solder paste may include solder powder and flux. For example, when the preliminary solder layer165is solder paste, the second photoresist pattern163may be omitted. Referring toFIGS.24and25, a solder ball169may be provided to the preliminary solder layer165to form a solder bump175. The solder ball169may include the same component as the preliminary solder layer165. For example, the solder ball169may include a Sn—Ag-based material. However, the inventive concepts are not limited thereto, and the solder ball169may further include other components. The solder bump175may be formed on the preliminary solder layer165to which flux is provided by means of a ball drop process using a ball-attaching device180and185. The ball-attaching device180and185by which the solder bump175is formed on the UBM layer160may include an ejection pin185configured to transfer the solder ball169and an attaching plate180including a plurality of holes having a greater width than the solder ball169. The wafer-level package in which the UBM layer160and the preliminary solder layer165disposed on the UBM layer160are formed may be disposed below the attaching plate180, and the plurality of holes of the attaching plate180may be aligned with the preliminary solder layer165. The solder ball169may be picked up by the ejection pin185and transferred onto the hole of the attaching plate180. Thereafter, the ejection pin185may release the pick-up of the solder ball169and drop the solder ball169on the preliminary solder layer165that is aligned with the solder ball169below the solder ball169. The preliminary solder layer165and the solder ball169dropped on the preliminary solder layer165may be heated to a melting point or higher and reflowed, thereby forming the solder bump175. While the preliminary solder layer165completely covering the UBM layer160is being melted together with the solder ball169, the solder bump175may be formed to completely cover a surface of the UBM layer160. Subsequently, the wafer in which the solder bump175is formed on the UBM layer160may be singulated into individual wafer level packages, thereby completing the manufacture of a plurality of wafer-level packages shown inFIG.1A. According to some example embodiments of the inventive concepts, since a thick UBM layer is provided, stress caused when a wafer-level package is mounted on a main board can be reduced to improve board level reliability (BLR). While some example embodiments of the inventive concepts have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the inventive concepts and without changing essential features thereof. Therefore, the above-described example embodiments should be considered in a descriptive sense only and not for purposes of limitation. | 25,670 |
11862590 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various embodiments provide methods applied to, but not limited to, the formation of an integrated circuit package that includes a first integrated circuit device bonded to a second integrated circuit device (e.g., to form a logic device), and a memory device. A total thickness of the first integrated circuit device and the second integrated circuit device is smaller than a thickness of the memory device, and the integrated circuit package further includes a support substrate over the first integrated circuit device and the second integrated circuit device. The total thickness of the first integrated circuit device, the second integrated circuit device and the support substrate is equal to or greater than the thickness of the memory device. Advantageous features of one or more embodiments disclosed herein may include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate and the memory device) and help improve heat dissipation efficiency in the integrated circuit package. In addition, the support substrate used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. FIG.1is a cross-sectional view of an integrated circuit device10, in accordance with some embodiments. The integrated circuit device10may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or a combination thereof. The integrated circuit device10is formed in a wafer (not shown), which includes different device regions. In some embodiments, multiple wafers will be stacked to form a wafer stack, which is singulated in subsequent processing to form multiple die stacks. In some embodiments, a wafer is singulated to form a plurality of integrated circuit devices10, which are stacked in subsequent processing to form multiple die stacks. The integrated circuit device10may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit device10may include a semiconductor substrate12, an interconnect structure14, conductive vias16, die connectors22, and a dielectric layer24. The semiconductor substrate12may be silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate12may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate12has an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a back side. Devices may be formed at the active surface of the semiconductor substrate12. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free from devices. An inter-layer dielectric (ILD) is over the active surface of the semiconductor substrate12. The ILD surrounds and may cover the devices. The ILD may include one or more dielectric layers formed of materials such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. The interconnect structure14is over the active surface of the semiconductor substrate12. The interconnect structure14interconnects the devices at the active surface of the semiconductor substrate12to form an integrated circuit. The interconnect structure14may be formed by, for example, metallization patterns in dielectric layers. The metallization patterns include metal lines and vias formed in one or more dielectric layers. The metallization patterns of the interconnect structure14are electrically coupled to the devices at the active surface of the semiconductor substrate12. The conductive vias16are formed extending into the interconnect structure14and/or the semiconductor substrate12. The conductive vias16are electrically coupled to metallization patterns of the interconnect structure14. As an example to form the conductive vias16, recesses can be formed in the interconnect structure14and/or the semiconductor substrate12by, for example, etching, milling, laser techniques, a combination thereof, and/or the like. A thin dielectric material may be formed in the recesses, such as by using an oxidation technique. A barrier layer18may be conformally deposited in the openings, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and/or the like. The barrier layer18may be formed from an oxide, a nitride, or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and/or the like. A conductive material20may be deposited over the barrier layer18and in the openings. The conductive material20may be formed by an electro-chemical plating process, CVD, PVD, a combination thereof, and/or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and/or the like. Excess of the conductive material20and the barrier layer18is removed from the surface of the interconnect structure14and/or the semiconductor substrate12by, for example, a chemical-mechanical polish (CMP). Remaining portions of the barrier layer18and the conductive material20form the conductive vias16. In the embodiment illustrated, the conductive vias16are not yet exposed at the back side of the integrated circuit device10. Rather, the conductive vias16are buried in the semiconductor substrate12. As will be discussed in greater detail below, the conductive vias16will be exposed at the back side of the integrated circuit device10in subsequent processing. After exposure, the conductive vias16can be referred to as through-silicon vias or through-substrate vias (TSVs). The die connectors22are at a front side of the integrated circuit device10. The die connectors22may be conductive pillars, pads, or the like, to which external connections are made. The die connectors22are in and/or on the interconnect structure14. The die connectors22can be formed of a metal, such as copper, titanium, aluminum, the like, or a combination thereof, and can be formed by, for example, plating, or the like. The dielectric layer24is at the front side of the integrated circuit device10. The dielectric layer24is in and/or on the interconnect structure14. The dielectric layer24laterally encapsulates the die connectors22, and the dielectric layer24is laterally coterminous (within process variations) with sidewalls of the integrated circuit device10. The dielectric layer24may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer24may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the dielectric layer24is formed after the die connectors22, and may bury the die connectors22such that the top surface of the dielectric layer24is above the top surfaces of the die connectors22. In some embodiments, the die connectors22after formed after the dielectric layer24, such as by a damascene process, e.g., single damascene, dual damascene, or the like. After formation, the die connectors22and the dielectric layer24can be planarized using, e.g., a CMP process, an etch back process, the like, or combinations thereof. After planarization, the top surfaces of the die connectors22and dielectric layer24are coplanar (within process variations) and are exposed at the front side of the integrated circuit device10. In another embodiment, the die connectors22are formed after the dielectric layer24, such as by a plating process, and are raised connectors (e.g., microbumps) such that the top surfaces of the die connectors22extend above the top surface of the dielectric layer24. FIGS.2A through2Fare cross-sectional views of intermediate steps during a process for forming a memory cube50, in accordance with some embodiments. Unless specified otherwise, like reference numerals inFIGS.2A through2F(as well as subsequent Figures) represent like components in the embodiment shown inFIG.1formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. As will be discussed in greater detail below,FIGS.2A through2Fillustrate a process in which a memory cube50is formed by stacking multiple wafers that include first integrated circuit devices on a carrier substrate52. The first integrated circuit devices may each have a structure similar to the integrated circuit device10discussed above with reference toFIG.1, and in an embodiment may be memory devices. Subsequently, the first integrated circuit devices may also be referred to as memory devices11. Stacking of wafers to form a memory cube50in one device region52A of the carrier substrate52is illustrated, but it should be appreciated that the carrier substrate52may have any number of device regions, and a memory cube50may be formed in each device region. The memory cube50is formed in a top-down (or reverse) manner by wafer-on-wafer (WoW) stacking, where a wafer for the top layer of the memory cube50is provided, and wafers for underlying layers of the memory cube50are subsequently stacked on the top wafer. The wafer stack is singulated to form multiple memory cubes50. The memory cubes50are tested after formation to reduce or prevent subsequent processing of known bad memory cubes50. Subsequently, the memory cube50may be used in the formation of a high bandwidth memory (HBM) device100(shown subsequently inFIG.3D). Specifically, as will be discussed in greater detail below, the memory cube50can be further stacked on a second integrated circuit device to form a HBM device. The second integrated circuit device may have a structure similar to the integrated circuit device10discussed above with reference toFIG.1, and in an embodiment may be a logic device. Subsequently, the second integrated circuit device may be referred to as logic device13. InFIG.2A, a carrier substrate52is provided, and a release layer54is formed on the carrier substrate52. The carrier substrate52may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate52may be a wafer, such that multiple memory cubes50can be formed on the carrier substrate52simultaneously. The release layer54may be formed of a polymer-based material, which may be removed along with the carrier substrate52from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer54is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer54may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer54may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate52, or may be the like. The top surface of the release layer54may be leveled and may have a high degree of planarity. A wafer56A is stacked on the carrier substrate52. The wafer56A comprises multiple integrated circuit devices, such as a memory device11A in the device region52A. The memory device11A will be singulated in subsequent processing to be included in the memory cube50. The memory device11A includes a semiconductor substrate12A, an interconnect structure14A, conductive vias16A, and a dielectric layer24A, but does not include die connectors in the dielectric layer24A at this step of processing. The wafer56A is stacked face-down on the carrier substrate52so that a major surface of the dielectric layer24A faces/contacts the carrier substrate52. As will be discussed in greater detail below, the memory cube50is attached to another integrated circuit device after singulation. Reflowable connectors are used to attach the memory cube50to the other integrated circuit device. In some embodiments, die connectors may be formed in the dielectric layer24A (see below,FIG.2E). The die connectors are formed after wafer stacking is completed, to prevent damage to the die connectors during wafer stacking. InFIG.2B, the wafer56A is thinned. The thinning may be by a CMP process, a grinding process, an etch back process, the like, or combinations thereof, and is performed on the inactive surface of the semiconductor substrate12A. The thinning exposes the conductive vias16A. After the thinning, surfaces of the conductive vias16A and the inactive surface of the semiconductor substrate12A are coplanar (within process variations). As such, the conductive vias16A are exposed at the back side of the memory device11A. InFIG.2C, a wafer56B is stacked over the carrier substrate52. In particular, the front side of the wafer56B is attached to the back side of the wafer56A. The wafer56B comprises multiple integrated circuit devices, such as a memory device11B in the device region52A. The memory device11B will be singulated in subsequent processing to be included in the memory cube50. The memory device11B includes a semiconductor substrate12B, an interconnect structure14B, conductive vias16B, die connectors22B, and a dielectric layer24B. The wafer56A and the wafer56B are back-to-face bonded, e.g., are directly bonded in a back-to-face manner by hybrid bonding, such that the back side of the wafer56A is bonded to the front side of the wafer56B. Specifically, dielectric-to-dielectric bonds and metal-to-metal bonds are formed between the wafer56A and the wafer56B. In the illustrated embodiment, a dielectric layer58and die connectors60are formed at the back side of the wafer56A and are used for hybrid bonding. The dielectric layer58is formed at the back side of the wafer56A, such as on the semiconductor substrate12A. The dielectric layer58is laterally coterminous (within process variations) with sidewalls of the memory device11A. The dielectric layer58may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer58may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments (discussed in greater detail below), the semiconductor substrate12A is recessed before forming the dielectric layer58so that the dielectric layer58surrounds the conductive vias16A. The die connectors60are formed at the back side of the wafer56A, and are in physical contact with the conductive vias16A. The die connectors60may be conductive pillars, pads, or the like, to which external connections are made. The die connectors60can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The die connectors60are electrically connected to integrated circuits of the memory device11A by the conductive vias16A. After formation, the dielectric layer58and the die connectors60are planarized using, e.g., a CMP process, an etch back process, the like, or combinations thereof. After planarization, the top surfaces of the die connectors60and dielectric layer58are coplanar (within process variations) and are exposed at the back side of the wafer56A. The dielectric layer58is bonded to the dielectric layer24B through dielectric-to-dielectric bonding, without using any adhesive material (e.g., die attach film), and the die connectors60are bonded to the die connectors22B through metal-to-metal bonding, without using any eutectic material (e.g., solder). The bonding may include a pre-bonding and an annealing. During the pre-bonding, a small pressing force is applied to press the wafer56B against the wafer56A. The pre-bonding is performed at a low temperature, such as room temperature, such as a temperature in the range of 15° C. to 30° C., and after the pre-bonding, the dielectric layer24B and the dielectric layer58are bonded to each other. The bonding strength is then improved in a subsequent annealing step, in which the dielectric layer24B and the dielectric layer58are annealed at a high temperature, such as a temperature in the range of 140° C. to 500° C. After the annealing, bonds, such as fusions bonds, are formed bonding the dielectric layer24B and the dielectric layer58. For example, the bonds can be covalent bonds between the material of the dielectric layer58and the material of the dielectric layer24B. The die connectors22B and the die connectors60are connected to each other with a one-to-one correspondence. The die connectors22B and the die connectors60may be in physical contact after the pre-bonding, or may expand to be brought into physical contact during the annealing. Further, during the annealing, the material of the die connectors22B and the die connectors60(e.g., copper) intermingles, so that metal-to-metal bonds are also formed. Hence, the resulting bonds between the wafer56A and the wafer56B are hybrid bonds that include both dielectric-to-dielectric bonds and metal-to-metal bonds. In another embodiment, the die connectors60are omitted. The dielectric layer58is bonded to the dielectric layer24B through dielectric-to-dielectric bonding, without using any adhesive material (e.g., die attach film), and the conductive vias16A are bonded to the die connectors22B through metal-to-metal bonding, without using any eutectic material (e.g., solder). In yet another embodiment, the dielectric layer58and the die connectors60are omitted. The semiconductor substrate12A may be bonded to the dielectric layer24B through dielectric-to-dielectric bonding, without using any adhesive material (e.g., die attach film), and the conductive vias16A may be bonded to the die connectors22B through metal-to-metal bonding, without using any eutectic material (e.g., solder). For example, an oxide, such as a native oxide, a thermal oxide, or the like, may be formed on the inactive surface of the semiconductor substrate12A, and may be used for the dielectric-to-dielectric bonding. InFIG.2D, the steps described above are repeated so that wafers56C,56D,56E,56F,56G,56H are stacked over the carrier substrate52. The wafers56C,56D,56E,56F,56G,56H each comprise multiple integrated circuit devices, such as, respectively, memory devices11C,11D,11E,11F,11G,11H in the device region52A. The memory devices11C,11D,11E,11F,11G,11H will be singulated in subsequent processing to be included in the memory cube50. Each of the wafers56C,56D,56E,56F,56G,56H is directly bonded to, respectively, the wafers56B,56C,56D,56E,56F,56G in a back-to-face manner by hybrid bonding. The last wafer that is stacked, e.g., the wafer56H, may not be thinned, such that conductive vias16H of the wafer56H remain electrically insulated. InFIG.2E, a carrier substrate debonding is performed to detach (or “debond”) the carrier substrate52from the wafer stack, e.g., the wafer56A. In accordance with some embodiments, the debonding includes projecting a light such as a laser light or an UV light on the release layer54so that the release layer54decomposes under the heat of the light and the carrier substrate52can be removed. Removing the carrier substrate52exposes the major surface of the upper memory device (e.g., the memory device11A) of the memory cube50. The wafer stack is then flipped over and placed on a tape (not shown). Die connectors22A are then formed for the top layer of the memory cube50, e.g., at a front side of the wafer56A. The die connectors22A are used to subsequently connect the memory cube to another device such as e.g. a wafer102(see below,FIG.3C). The die connectors22A may be formed of a similar material and by a similar method as the die connectors60as described above in respect toFIG.2C. The die connectors60are electrically connected to integrated circuits of the memory device11A by the conductive vias16A. After formation, the dielectric layer24A and the die connectors22A are planarized using, e.g., a CMP process, an etch back process, the like, or combinations thereof. After planarization, the top surfaces of the die connectors22A and dielectric layer24A are coplanar (within process variations) and are exposed at the front side of the wafer56A. InFIG.2F, a singulation process is performed along scribe line regions, e.g., between the device region52A and adjacent device regions. The singulation may be by sawing, laser cutting, or the like. The singulation process can be performed before or after the die connectors22A are formed. The singulation separates the device region52A from adjacent device regions. The resulting, singulated memory cube50is from the device region52A. The memory devices of the memory cube50are laterally coterminous (within process variations) after singulation. It should be appreciated that the memory cube50may include any number of layers. In the embodiment shown, the memory cube50includes eight layers. In another embodiment, the memory cube50includes more or less than eight layers, such as two layers, four layers, sixteen layers, thirty two layers, or the like. After formation of the memory cube50is complete (e.g., after formation of the die connectors22A and singulation of the memory cube50), the resulting memory cube50is tested by use of a probe62. The probe62is physically and electrically connected to the die connectors22A. The die connectors22A are used to test the memory cube50, such that only known good memory cubes are used for further processing. The testing may include testing of the functionality of the memory devices11A,11B,11C,11D,11E,11F,11G,11H, or may include testing for known open or short circuits that may be expected based on the design of the memory devices. During the testing, all of the memory devices of the memory cube50may be tested in a daisy-chain manner. FIGS.3A through3Dare cross-sectional views of intermediate steps during a process for forming a HBM device100, in accordance with some embodiments. As will be discussed in greater detail below,FIGS.3A through3Dillustrate a process in which the HBM device100is formed by stacking the memory cube50on a second integrated circuit device (e.g., the logic device13L, seeFIG.3A). The second integrated circuit device is a bare die, which can be formed in a wafer102. Formation of the HBM device100in one device region102A of the wafer102is illustrated, but it should be appreciated that the wafer102may have any number of device regions, and a HBM device100may be formed in each device region. InFIG.3Athe wafer102is obtained. The wafer102comprises a logic device13L in the device region102A. The logic device13L will be singulated in subsequent processing to be included in the HBM device100. The logic device13L can be an interface device, buffer device, controller device, or the like for the memory devices of the memory cube50. In some embodiments, the logic device13L provides the input/output (I/O) interface for the HBM device100. The logic device13L includes a semiconductor substrate12L, an interconnect structure14L, conductive vias16L, die connectors22L, and a dielectric layer24L. The die connectors22L are used for connections to other devices, such as devices in an integrated circuit package in which the HBM device100can be implemented. In some embodiments, the die connectors22L are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer24L. The die connectors22L may have substantially vertical sidewalls (within process variations). In the illustrated embodiment, the die connectors22L are formed through the dielectric layer24L to couple the metallization patterns of the interconnect structure14L. As an example to form the die connectors22L, openings are formed in the dielectric layer24L, and a seed layer is formed over the dielectric layer24L and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the die connectors22L. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the die connectors22L. InFIG.3B, the wafer102is thinned. The thinning may be by a CMP process, a grinding process, an etch back process, the like, or combinations thereof, and is performed on the inactive surface of the semiconductor substrate12L. The thinning exposes the conductive vias16L. After the thinning, surfaces of the conductive vias16L and the inactive surface of the semiconductor substrate12L are coplanar (within process variations). As such, the conductive vias16L are exposed at the back side of the logic device13L. A dielectric layer104is then formed over the wafer102, e.g., at the back side of the logic device13L. The dielectric layer104may be formed of a similar material and by a similar method as the dielectric layer58described with respect toFIG.2C. Die connectors106are then formed extending through the dielectric layer104. The die connectors106may be formed of a similar material and by a similar method as the die connectors22A described with respect toFIG.2E. For example, the die connectors106may be conductive pillars, pads, or the like that are suitable for use with metal-to-metal bonding, without using any eutectic material (e.g., solder). The die connectors106are physically connected to the conductive vias16L, and are electrically connected to integrated circuits of the logic device13L by the conductive vias16L. InFIG.3C, a memory cube50is attached to the wafer102, e.g., to the back side of the logic device13L. The wafer102and the memory cube50are back-to-face bonded, e.g., are directly bonded in a back-to-face manner by hybrid bonding, such that the back side of the wafer102is bonded to the front side of the memory cube50. Specifically, dielectric-to-dielectric bonds are formed between the dielectric layer104of the wafer102and the dielectric layer24A of the memory cube50, and metal-to-metal bonds are formed between the die connectors106of the wafer102and the die connectors22A of the memory cube50. The hybrid bonding of the wafer102and the memory cube50may be performed using similar methods as described above for the hybrid bonding of the wafer56A and the wafer56B in respect toFIG.2C. InFIG.3D, an encapsulant112is formed on and around the various components. After formation, the encapsulant112encapsulates the memory cube50and contacts a top surface of the dielectric layer104and each memory device of the memory cube50. The encapsulant112may be a molding compound, epoxy, or the like. The encapsulant112may be applied by compression molding, transfer molding, or the like, and may be formed over the wafer102such that the memory cube50is buried or covered. The encapsulant112may be applied in liquid or semi-liquid form and then subsequently cured. A planarization process is optionally performed on the encapsulant112to expose the memory cube50. After the planarization process, top surfaces of the memory cube50and the encapsulant112are coplanar (within process variations). The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, for example, if the memory cube50is already exposed. A singulation process is then performed along scribe line regions, e.g., around the device region102A. The singulation may be by sawing, laser cutting, or the like. The singulation process separates the device region102A (comprising the logic device13L) from adjacent device regions to form an HBM device100comprising the logic device13L. The singulated logic device13L has a greater width than each memory device of the memory cube50. After singulation, the logic device13L and the encapsulant112are laterally coterminous (within process variations). Conductive connectors114are formed on the die connectors22L. The conductive connectors114may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors114may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors114are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors114comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. The conductive connectors114may be formed before or after the singulation process. The conductive connectors114will be used for external connection (discussed further below). FIGS.4A through4Iare cross-sectional views of intermediate steps during a process for forming an integrated circuit package1000, in accordance with some embodiments.FIGS.4A through4Dshow cross-sectional views of the formation of a bottom wafer250A.FIGS.4E through4Gshow cross-sectional views of intermediate steps in the formation of a stack200.FIG.4Eshows the bonding of the bottom wafer250A to a top die250B, in accordance with embodiments. Each bottom wafer250A may comprise a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die). The bottom wafer250A may include different die regions that are singulated in subsequent steps to form a plurality of die regions. InFIG.4A, a semiconductor substrate252, and an interconnect structure254over the semiconductor substrate252are shown. The semiconductor substrate252may be a substrate of silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate252may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate252has an active surface253(e.g., the surface facing upward inFIG.4A) and an inactive surface (e.g., the surface facing downward inFIG.4A). The active surface253may also be referred to as the active device layer253. Devices are at the active surface253of the semiconductor substrate252. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free from devices. The interconnect structure254is over the active surface253of the semiconductor substrate252, and is used to electrically connect the devices of the semiconductor substrate252to form an integrated circuit. The interconnect structure254may include one or more dielectric layer(s) and respective metallization layer(s) in the dielectric layer(s). Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like. Other dielectric materials may also be used, such as a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobuten (BCB) based polymer, or the like. The metallization layer(s) may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate252. The metallization layer(s) may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure254may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, a contact pad251may be formed in the interconnect structure254to which external connections are made to the interconnect structure254and the devices of the active layer253. The contact pad251is disposed over the active surface253. The contact pad251may comprise copper, aluminum (e.g.,28K aluminum), or another conductive material. The contact pad251may not be explicitly shown in subsequent figures. InFIG.4B, a support substrate255is bonded to the inactive surface of the semiconductor substrate252. The support substrate255may include a bulk substrate or a wafer, and may be formed of a material such as silicon, ceramic, heat conductive glass, a metal such as copper or iron, or the like. The support substrate255may be free of any active or passive devices. In an embodiment, the support substrate255may include metallization layer(s) on a top surface of the support substrate255. In some embodiments, the support substrate is formed of a material that produces a low amount of residue during CMP, such as silicon. The support substrate255is bonded to the inactive surface of the semiconductor substrate252using a suitable technique such as fusion bonding, or the like. For example, in various embodiments, the support substrate255may be bonded to the semiconductor substrate252using bonding layers227a/bon the surfaces of and support substrate255and the semiconductor substrate252, respectively. In some embodiments, the bonding layers227a/bmay each comprise silicon oxide formed on the surfaces of the support substrate255and the semiconductor substrate252, respectively by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In other embodiments, the bonding layers227a/bmay be formed by the thermal oxidation of silicon surfaces on the support substrate255and the semiconductor substrate252, respectively. Prior to bonding, at least one of the bonding layers227a/bmay be subjected to a surface treatment. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water, or the like) that may be applied to one or both bonding layers227a/b. The support substrate255is then aligned with the semiconductor substrate252and the two are pressed against each other to initiate a pre-bonding of the support substrate255to the semiconductor substrate252. The pre-bonding may be performed at room temperature (between about 21 degrees and about 25 degrees). The bonding time may be shorter than about 1 minute, for example. After the pre-bonding, the semiconductor substrate252and the support substrate255are bonded to each other. The bonding process may be strengthened by a subsequent annealing step. For example, this may be done by heating the semiconductor substrate252and the support substrate255to a temperature in a range from 140° C. to 500° C. The bonding layers227a/bmay not be shown in subsequent figures. FIG.4Cshows a thinning process applied to the support substrate255after the support substrate255and the semiconductor substrate252are bonded as shown previously inFIG.4B. The thinning process may include grinding or CMP processes, or other acceptable processes performed on a surface of the support substrate255in order to reduce the thickness of the support substrate255. After the thinning process, the support substrate255may have a first substrate height S1. InFIG.4D, conductive connectors256are shown which may be in and/or on the interconnect structure254of the bottom wafer250A. For example, the conductive connectors256may be part of an upper metallization layer of the interconnect structure254. The conductive connectors256can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors256may be conductive pillars, pads, or the like, to which external connections are made. A dielectric layer258is in and/or on the interconnect structure254. For example, the dielectric layer258may be an upper dielectric layer of the interconnect structure254. The dielectric layer258laterally encapsulates the conductive connectors256. The dielectric layer258may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer258may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. Initially, the dielectric layer258may bury the conductive connectors256, such that the top surface of the dielectric layer258is above the top surfaces of the conductive connectors256. The conductive connectors256may be exposed through the dielectric layer258by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors256. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors256and the dielectric layer258are coplanar (within process variations). In an embodiment, a first height H1between a top surface of the dielectric layer258and a bottom surface of the semiconductor substrate252is less than or equal to 780 μm. InFIG.4E, the top die250B is bonded to the bottom wafer250A to form a system-on-integrated-chip (SoIC) device. It should be appreciated that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages. The top die250B may be formed in a wafer, which may include different die regions that are then singulated to form a plurality of top dies250B. The top die250B includes a semiconductor substrate252, an interconnect structure254, and may include an active surface253, which are similar to those described forFIG.4A. In addition, the top die250B may comprise conductive connectors259, and a dielectric layer260which may be in and/or on the interconnect structure254of the top die250B. The conductive connectors259may be formed using like processes and like materials as the conductive connectors256. The dielectric layer260may be formed using like processes and like materials as the dielectric layer258. In some embodiments, the top die250B is a logic die, and the bottom wafer250A is used as an interface to bridge the logic die to memory devices (e.g., memory devices11of the HBM device100shown inFIG.4I), and to translate commands between the logic die and the memory devices. In some embodiments, the top die250B and the bottom wafer250A are bonded such that the active surfaces253are facing each other (e.g., are “face-to-face” bonded). Conductive vias262may be formed through the top die250B to allow external connections to be made to the stack200(shown subsequently inFIG.4G). The conductive vias262may be through-substrate vias (TSVs), such as through-silicon vias or the like. The conductive vias262extend through the semiconductor substrate252of the top die250B, to be physically and electrically connected to the metallization layer(s) of the interconnect structure254. The bottom wafer250A is bonded to the top die250B, for example, using a hybrid bonding process that may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. The hybrid bonding process directly bonds the dielectric layer258of the bottom wafer250A to the dielectric layer260of the top die250B through fusion bonding. In an embodiment, the bond between the dielectric layer258and the dielectric layer260may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors256of the bottom wafer250A and the conductive connectors259of the top die250B through direct metal-to-metal bonding. Thus, the bottom wafer250A and the top die250B are electrically connected. InFIG.4F, insulating material264is formed over the bottom wafer250A and the top die250B. The insulating material264surrounds the top die250B and may comprise a dielectric material such as a silicon oxide, or the like, formed by a CVD or PECVD process. A planarization step such as CMP, or the like, may then be performed to level top surfaces of the insulating material264with a top surface of the top die250B. The planarization step may further expose the conductive vias262of the top die250B. FIG.4Gshows the formation of contact pads268and a dielectric layer266over the stack200. The dielectric layer266may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer266may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The contact pads268may be used for connections to other devices. In some embodiments, the contact pads are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer266. In the illustrated embodiment, the contact pads268are formed through the dielectric layer266. As an example to form the contact pads268, openings are formed in the dielectric layer266, and a seed layer is formed over the dielectric layer266and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads268. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the contact pads268. In an embodiment, a second height H2between a top surface of the dielectric layer266and a bottom surface of the dielectric layer260may be in a range from 15 μm to 30 μm. After the formation of the contact pads268, conductive connectors270are formed on the contact pads268. The conductive connectors270may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors270may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors270are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors270comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. Advantages can be achieved as a result of the formation of the integrated circuit package1000that includes the top die250B bonded to the bottom wafer250A (e.g., to form a logic device), and the HBM device100. The integrated circuit package1000further includes the support substrate255over the top die250B and the bottom wafer250A. The total thickness of the top die250B, the bottom wafer250A and the support substrate255is equal to or greater than the thickness of the HBM device100. These advantages include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate255and the HBM device100) to help improve heat dissipation efficiency in the integrated circuit package1000. The support substrate255also functions as a heat spreader and dissipates heat from the stack200. In addition, the support substrate255used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. InFIG.4H, the stack200and HBM device100are bonded to a structure310using the conductive connectors270and the conductive connectors114, respectively. The structure310may comprise a redistribution structure. The structure310includes dielectric layers312and metallization layers314(sometimes referred to as redistribution layers or redistribution lines) among the dielectric layers312. For example, the structure310may include a plurality of metallization layers314separated from each other by respective dielectric layers312. The metallization layers314of the structure310are connected to the memory devices11of the HBM device100, and the top die250B and bottom wafer250A of the stack200through the conductive connectors114and the conductive connectors270, respectively. The conductive connectors270and the conductive connectors114may be bonded to redistribution lines370of the structure310by reflowing the conductive connectors270and the conductive connectors114using a flip chip bonding process. In some embodiments, the dielectric layers312are formed of a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, and may be patterned using a lithography mask. In other embodiments, the dielectric layers312are formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layers312may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The metallization layers314each include conductive vias and/or conductive lines. The conductive vias extend through the dielectric layers312, and the conductive lines extend along the dielectric layers312. The conductive vias and the conductive lines may comprise a conductive material that may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Conductive connectors382are formed on the structure310. The conductive connectors382may be connected to metallization layers314of the structure310. For example, the conductive connectors382may be formed on under-bump metallizations (UBMs)316of the structure310. The conductive connectors382may comprise solder balls and/or bumps, such as controlled collapse chip connection (C4) bumps, or the like. The conductive connectors382may be formed of a conductive material that is reflowable, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors382are formed by initially forming a layer of solder through methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the conductive connectors382into desired bump shapes. In accordance with an alternate embodiment, the structure310may comprise an interposer, and a redistribution structure on the interposer. The stack200and HBM device100may be bonded to topmost redistribution lines of the redistribution structure using the conductive connectors270and the conductive connectors114, respectively. In this way, the bottom wafer250A and the top die250B of the stack100, and the memory devices11of the HBM device100may be electrically connected to conductive vias of the interposer through the conductive connectors270, the conductive connectors114and the redistribution structure. InFIG.4I, an encapsulant272is then formed on and around the various components. After formation, the encapsulant272encapsulates the stack200and the HBM device100. The encapsulant272also surrounds the conductive connectors270and the conductive connectors114. The encapsulant272may be a molding compound, epoxy, or the like. The encapsulant272may be applied by compression molding, transfer molding, or the like, and may be formed such that the stack100and the HBM device100are buried or covered. The encapsulant272may be applied in liquid or semi-liquid form and then subsequently cured. A planarization process may then be performed on the encapsulant272to expose a top surface of the HBM device100and a top surface of the support substrate255. After the planarization process, top surfaces of the HBM device100, the support substrate255and the encapsulant272are coplanar (within process variations). The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In an embodiment, a third height H3of the HBM device100may be larger than 900 μm. In an embodiment, the sum of the first height H1, the second height H2, and the first substrate height S1is equal to or larger than the third height H3. In an embodiment, a top surface of the support substrate255is at the same level as a top surface of the HBM device100. In an embodiment, the top surface of the support substrate255is higher than the top surface of the HBM device100. The support substrate255acts as a heat spreader and dissipates heat from the stack200. Because of the exposed top surface of the support substrate255, a larger amount of heat can be dissipated through the support substrate255and the reliability of the stack200is improved. In accordance with an alternate embodiment, an underfill may formed between the structure310, and the HBM device100and the stack200prior to forming the encapsulant272. The underfill may surround the conductive connectors270and the conductive connectors114and may reduce stress and protect the joints resulting from the reflowing of the conductive connectors270and the conductive connectors114. The underfill316may be formed by a capillary flow process after the HBM device100and the stack100are attached, or may be formed by a suitable deposition method before the HBM device100and the stack100are attached. The material of the underfill may be a liquid epoxy, deformable gel, silicon rubber, the like, or a combination thereof. However, any suitable material may be used for the underfill. Still referring toFIG.4I, the integrated circuit package1000is then mounted on a package substrate386using the conductive connectors382. The package substrate386includes a substrate core384and bond pads388over the substrate core384. The substrate core384may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate core384may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate core384is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for substrate core384. The substrate core384may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The devices may be formed using any suitable methods. The substrate core384may also include metallization layers and vias (not shown), with the bond pads388being physically and/or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate core384is substantially free of active and passive devices. In some embodiments, the conductive connectors382are reflowed to attach the conductive connectors382to the bond pads488. The conductive connectors382electrically and/or physically couple the package substrate386, including metallization layers in the substrate core384, to the integrated circuit package1000. In some embodiments, a solder resist is formed on the substrate core384. The conductive connectors382may be disposed in openings in the solder resist to be electrically and mechanically coupled to the bond pads388. The solder resist may be used to protect areas of the substrate core384from external damage. In some embodiments, an underfill may be formed between the integrated circuit package1000and the package substrate386and surrounding the conductive connectors382, to reduce stress and protect the joints resulting from the reflowing of the conductive connectors382. The underfill may be formed by a capillary flow process after the integrated circuit package1000is attached or may be formed by a suitable deposition method before the integrated circuit package1000is attached. The conductive connectors382may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the integrated circuit package1000is attached to the package substrate386. This remaining epoxy portion may act as the underfill. The integrated circuit package1000that comprises the HBM device100and the stack100is an example a three-dimensional integrated circuit (3DIC) package. The embodiments described herein may be applied to, but are not limited to, embodiments that include a chip-on-wafer (CoW) package, a chip-on-wafer-on-substrate (CoWoS) package, an integrated fan-out (InFO) package, or the like. FIG.5Aillustrates a cross-sectional view of an integrated circuit package2000, in which a stack400and a HBM device100are shown bonded and electrically connected to a structure310using conductive connectors270and conductive connectors114, respectively.FIGS.5B through5Hillustrate cross-sectional views of intermediate steps in the forming of the stack400, in accordance with an alternate embodiment. Unless specified otherwise, like reference numerals in the integrated circuit package2000, (and subsequently discussed embodiments) represent like components in the integrated circuit package1000ofFIGS.4A through4I, that are formed by like processes, and unless specified otherwise, like reference numerals in the stack400, (and subsequently discussed embodiments) represent like components in the stack200ofFIGS.4A through4I, that are formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. InFIG.5B, a semiconductor substrate252, and an interconnect structure254over the semiconductor substrate252are shown, similar to those shown previously inFIG.4A. InFIG.5C, a support substrate255is bonded to an inactive surface of the semiconductor substrate252. The support substrate255may include a bulk substrate or a wafer, and may be formed of a material such as silicon, ceramic, heat conductive glass, a metal such as copper or iron, or the like. The support substrate255may be free of any active or passive devices. In an embodiment, the support substrate255may include metallization layer(s) on a top surface of the support substrate255. In some embodiments, the support substrate is formed of a material that produces a low amount of residue during CMP, such as silicon. The support substrate255is bonded to the inactive surface of the semiconductor substrate252using a suitable technique such as hybrid bonding, or the like. For example, a dielectric layer274is formed over the support substrate255and a dielectric layer276is formed over the semiconductor substrate252. The dielectric layer274and the dielectric layer276may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layers274and276may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The dielectric layers274and276may then be patterned and openings formed in the dielectric layers274and276. Conductive connectors280are then formed in the dielectric layer276and conductive connectors278are formed in the dielectric layer274. The conductive connectors270and280are formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors278and280may comprise conductive pillars, pads, or the like, to which external connections are made. The conductive connectors278may be exposed through the dielectric layer274by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors278, and the conductive connectors280may be exposed through the dielectric layer276by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors280. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors278and the dielectric layer274are coplanar (within process variations), and top surfaces of the die connectors280and the dielectric layer276are coplanar (within process variations). The hybrid bonding process then directly bonds the dielectric layer274of the support substrate255to the dielectric layer276of the semiconductor substrate252through fusion bonding. In an embodiment, the bond between the dielectric layer274and the dielectric layer276may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors278of the support substrate255and the conductive connectors280of the semiconductor substrate252through direct metal-to-metal bonding. The hybrid bonding process may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. FIG.5Dshows a thinning process applied to the support substrate255after the support substrate255and the semiconductor substrate252are bonded as shown previously inFIG.5C. The thinning process may include grinding or CMP processes, or other acceptable processes performed on a surface of the support substrate255in order to reduce the thickness of the support substrate255. After the thinning process, the height between a top surface of the support substrate255and a bottom surface of the dielectric layer274may be a second substrate height S2. InFIG.5E, conductive connectors256are formed in and/or on the interconnect structure254to form a bottom wafer450A. For example, the conductive connectors256may be part of an upper metallization layer of the interconnect structure254. The conductive connectors256can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors256may be conductive pillars, pads, or the like, to which external connections are made. A dielectric layer258is in and/or on the interconnect structure254. For example, the dielectric layer258may be an upper dielectric layer of the interconnect structure254. The dielectric layer258laterally encapsulates the conductive connectors256. The dielectric layer258may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer258may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. Initially, the dielectric layer258may bury the conductive connectors256, such that the top surface of the dielectric layer258is above the top surfaces of the conductive connectors256. The conductive connectors256may be exposed through the dielectric layer258by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors256. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors256and the dielectric layer258are coplanar (within process variations). In an embodiment, a fourth height H4between a top surface of the dielectric layer258and a bottom surface of the dielectric layer276may be less than or equal to 780 μm. InFIG.5F, a top die450B is bonded to the bottom wafer450A to form a system-on-integrated-chip (SoIC) device. It should be appreciated that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages. The top die450B may be formed in a wafer, which may include different die regions that are then singulated to form a plurality of top dies450B. The top die450B includes a semiconductor substrate252, an interconnect structure254, and may include an active surface253, which are similar to those described forFIG.4A. In addition, the top die450B may comprise conductive connectors259, and a dielectric layer260which may be in and/or on the interconnect structure254of the top die450B. The conductive connectors259may be formed using like processes and like materials as the conductive connectors256. The dielectric layer260may be formed using like processes and like materials as the dielectric layer258. In some embodiments, the top die450B is a logic die, and the bottom wafer450A is used as an interface to bridge the logic die to memory devices (e.g., memory devices11of the HBM device100shown inFIG.5A), and to translate commands between the logic die and the memory devices. In some embodiments, the top die450B and the bottom wafer450A are bonded such that the active surfaces253are facing each other (e.g., are “face-to-face” bonded). Conductive vias262may be formed through the top die450B to allow external connections to be made to the stack400(shown subsequently inFIG.5H). The conductive vias262may be through-substrate vias (TSVs), such as through-silicon vias or the like. The conductive vias262extend through the semiconductor substrate252of the top die450B, to be physically and electrically connected to the metallization layer(s) of the interconnect structure254. The bottom wafer450A is bonded to the top die450B, for example, using a hybrid bonding process that may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. The hybrid bonding process directly bonds the dielectric layer258of the bottom wafer450A to the dielectric layer260of the top die450B through fusion bonding. In an embodiment, the bond between the dielectric layer258and the dielectric layer260may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors256of the bottom wafer450A and the conductive connectors259of the top die450B through direct metal-to-metal bonding. Thus, the bottom wafer450A and the top die450B are electrically connected. InFIG.5G, insulating material264is formed over the bottom wafer450A and the top die450B. The insulating material264surrounds the top die450B and may comprise a dielectric material such as a silicon oxide, or the like, formed by a CVD or PECVD process. A planarization step such as CMP, or the like, may then be performed to level top surfaces of the insulating material264with a top surface of the top die450B. The planarization step may further expose the conductive vias262of the top die450B. FIG.5Hshows the formation of contact pads268and a dielectric layer266over the stack400. The dielectric layer266may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer266may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The contact pads268may be used for connections to other devices. In some embodiments, the contact pads are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer266. In the illustrated embodiment, the contact pads268are formed through the dielectric layer266. As an example to form the contact pads268, openings are formed in the dielectric layer266, and a seed layer is formed over the dielectric layer266and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads268. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the contact pads268. In an embodiment, a fifth height H5between a top surface of the dielectric layer266and a bottom surface of the dielectric layer260may be in a range from 15 μm to 30 μm. In an embodiment, the sum of the fourth height H4, the fifth height H5, and the second substrate height S2is equal to or larger than the third height H3. In an embodiment, a top surface of the support substrate255is at the same level as a top surface of the HBM device100. In an embodiment, the top surface of the support substrate255is higher than the top surface of the HBM device100. After the formation of the contact pads268, conductive connectors270are formed on the contact pads268. The conductive connectors270may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors270may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors270are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors270comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. Advantages can be achieved as a result of the formation of the integrated circuit package2000that includes the top die450B bonded to the bottom wafer450A (e.g., to form a logic device), and the HBM device100. The integrated circuit package2000further includes the support substrate255over the top die450B and the bottom wafer450A. The total thickness of the top die450B, the bottom wafer450A and the support substrate255is equal to or greater than the thickness of the HBM device100. These advantages include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate255and the HBM device100) to help improve heat dissipation efficiency in the integrated circuit package2000. The support substrate255also functions as a heat spreader and dissipates heat from the stack400. Because of the exposed top surface of the support substrate255, a larger amount of heat can be dissipated through the support substrate255and the reliability of the stack400is improved. In addition, the support substrate255used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. FIG.6Aillustrates a cross-sectional view of an integrated circuit package3000, in which a stack500and a HBM device100are shown bonded and electrically connected to a structure310using conductive connectors270and conductive connectors114, respectively.FIGS.6B through6Gillustrate cross-sectional views of intermediate steps in the forming of the stack500, in accordance with an alternate embodiment. Unless specified otherwise, like reference numerals in the integrated circuit package3000, (and subsequently discussed embodiments) represent like components in the integrated circuit package1000ofFIGS.4A through4I, that are formed by like processes, and unless specified otherwise, like reference numerals in the stack500, (and subsequently discussed embodiments) represent like components in the stack200ofFIGS.4A through4I, that are formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. FIG.6Bshows a cross-sectional view of a bottom wafer550A. Each bottom wafer550A may comprise a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die). The bottom wafer550A may include different die regions that are singulated in subsequent steps to form a plurality of die regions. InFIG.6B, a semiconductor substrate252, and an interconnect structure254over the semiconductor substrate252are shown. The semiconductor substrate252may be a substrate of silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate252may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate252has an active surface253(e.g., the surface facing upward inFIG.6B) and an inactive surface (e.g., the surface facing downward inFIG.6B). The active surface253may also be referred to as the active device layer253. Devices are at the active surface253of the semiconductor substrate252. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free from devices. The interconnect structure254is over the active surface253of the semiconductor substrate252, and is used to electrically connect the devices of the semiconductor substrate252to form an integrated circuit. The interconnect structure254may include one or more dielectric layer(s) and respective metallization layer(s) in the dielectric layer(s). Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like. Other dielectric materials may also be used, such as a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobuten (BCB) based polymer, or the like. The metallization layer(s) may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate252. The metallization layer(s) may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure254may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, a contact pad251may be formed in the interconnect structure254to which external connections are made to the interconnect structure254and the devices of the active layer253. The contact pad251is disposed over the active surface253. The contact pad251may comprise copper, aluminum (e.g.,28K aluminum), or another conductive material. The contact pad251may not be explicitly shown in subsequent figures. Conductive vias262may be formed through the bottom wafer550A to allow external connections to be made to the stack500(shown subsequently inFIG.6G). The conductive vias262may be through-substrate vias (TSVs), such as through-silicon vias or the like. The conductive vias262extend through the semiconductor substrate252of the bottom wafer550A, to be physically and electrically connected to the metallization layer(s) of the interconnect structure254. Still referring toFIG.6B, conductive connectors259are shown which may be in and/or on the interconnect structure254of the bottom wafer550A. For example, the conductive connectors259may be part of an upper metallization layer of the interconnect structure254. The conductive connectors259can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors259may be conductive pillars, pads, or the like, to which external connections are made. A dielectric layer260is in and/or on the interconnect structure254. For example, the dielectric layer260may be an upper dielectric layer of the interconnect structure254. The dielectric layer260laterally encapsulates the conductive connectors259. The dielectric layer260may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer260may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. Initially, the dielectric layer260may bury the conductive connectors259, such that the top surface of the dielectric layer260is above the top surfaces of the conductive connectors259. The conductive connectors259may be exposed through the dielectric layer260by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors259. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors259and the dielectric layer260are coplanar (within process variations). InFIG.6C, a top die550B is bonded to the bottom wafer550A to form a system-on-integrated-chip (SoIC) device. It should be appreciated that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages. The top die550B may be formed in a wafer, which may include different die regions that are then singulated to form a plurality of top dies550B. The top die550B includes a semiconductor substrate252, an interconnect structure254, and may include an active surface253, which are similar to those described forFIG.6B. In addition, the top die550B may comprise conductive connectors256, and a dielectric layer258which may be in and/or on the interconnect structure254of the top die550B. The conductive connectors256may be formed using like processes and like materials as the conductive connectors259(described previously inFIG.6B). The dielectric layer258may be formed using like processes and like materials as the dielectric layer260(described previously inFIG.6B). In an embodiment, the top die550B has a sixth height H6that may be less or equal to 780 μm. In some embodiments, the top die550B is a logic die, and the bottom wafer550A is used as an interface to bridge the logic die to memory devices (e.g., memory devices11of the HBM device100shown inFIG.6A), and to translate commands between the logic die and the memory devices. In some embodiments, the top die550B and the bottom wafer550A are bonded such that the active surfaces253are facing each other (e.g., are “face-to-face” bonded). The bottom wafer550A is bonded to the top die550B, for example, using a hybrid bonding process that may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. The hybrid bonding process directly bonds the dielectric layer260of the bottom wafer550A to the dielectric layer258of the top die550B through fusion bonding. In an embodiment, the bond between the dielectric layer260and the dielectric layer258may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors259of the bottom wafer550A and the conductive connectors256of the top die550B through direct metal-to-metal bonding. Thus, the bottom wafer550A and the top die550B are electrically connected. InFIG.6D, insulating material222is formed over the bottom wafer550A and the top die550B. The insulating material222surrounds the top die550B and may comprise a dielectric material such as a silicon oxide, or the like, formed by a CVD or PECVD process. A planarization step such as CMP, or the like, may then be performed to level top surfaces of the insulating material222with a top surface of the top die550B. InFIG.6E, a support substrate255is bonded to top surfaces of the insulating material222, and the inactive surface of the semiconductor substrate252of the top die550B. The support substrate255may include a bulk substrate or a wafer, and may be formed of a material such as silicon, ceramic, heat conductive glass, a metal such as copper or iron, or the like. The support substrate255may be free of any active or passive devices. In an embodiment, the support substrate255may include metallization layer(s) on a top surface of the support substrate255. In some embodiments, the support substrate is formed of a material that produces a low amount of residue during CMP, such as silicon. In an embodiment, the height of the support substrate255may be a third substrate height S3. The support substrate255is bonded to the top surfaces of the insulating material222, and the inactive surface of the semiconductor substrate252of the top die550B using a suitable technique such as fusion bonding, or the like. For example, in various embodiments, the support substrate255may be bonded to the semiconductor substrate252and the insulating material222using bonding layer227aon the surface of the support substrate255and bonding layer227bon the surfaces of the semiconductor substrate252, and the insulating material222. In some embodiments, the bonding layers227a/bmay each comprise silicon oxide formed on the surfaces of the semiconductor substrate252, the insulating material222, and the support substrate255by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In other embodiments, a portion of the bonding layer227bon the semiconductor substrate252and the bonding layer227aon the support substrate255may be formed by the thermal oxidation of silicon surfaces on the semiconductor substrate252and the support substrate255, respectively. Prior to bonding, at least one of the bonding layers227a/bmay be subjected to a surface treatment. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water, or the like) that may be applied to at least one of the bonding layers227a/b. The support substrate255is then aligned with the semiconductor substrate252and the insulating material222, and pressed against each other to initiate a pre-bonding of the support substrate255to the semiconductor substrate252and the insulating material222. The pre-bonding may be performed at room temperature (between about 21 degrees and about 25 degrees). The bonding time may be shorter than about 1 minute, for example. After the pre-bonding, the semiconductor substrate252and the insulating material222are bonded to the support substrate255. The bonding process may be strengthened by a subsequent annealing step. For example, this may be done by heating the semiconductor substrate252, insulating material222, and the support substrate255to a temperature in a range from 140° C. to 500° C. The bonding layers227a/bmay not be shown in subsequent figures. InFIG.6F, a planarization step such as CMP, or the like, may then be performed to expose the conductive vias262of the bottom wafer550A. After the planarization step, a top surface of the semiconductor substrate252of the bottom wafer550A is level with top surfaces of the conductive vias262. FIG.6Gshows the formation of contact pads268and a dielectric layer266over the stack500. The dielectric layer266may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer266may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The contact pads268may be used for connections to other devices. In some embodiments, the contact pads are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer266. In the illustrated embodiment, the contact pads268are formed through the dielectric layer266. As an example to form the contact pads268, openings are formed in the dielectric layer266, and a seed layer is formed over the dielectric layer266and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads268. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the contact pads268. In an embodiment, a seventh height H7between a bottom surface of the dielectric layer260and a top surface of the dielectric layer266may be in a range from 15 μm to 30 μm. In an embodiment, the sum of the sixth height H6, the seventh height H7, and the third substrate height S3is equal to or larger than the third height H3. In an embodiment, a top surface of the support substrate255is at the same level as a top surface of the HBM device100. In an embodiment, the top surface of the support substrate255is higher than the top surface of the HBM device100. Advantages can be achieved as a result of the formation of the integrated circuit package3000that includes the top die550B bonded to the bottom wafer550A (e.g., to form a logic device), and the HBM device100. The integrated circuit package3000further includes the support substrate255over the top die550B and the bottom wafer550A. The total thickness of the top die550B, the bottom wafer550A and the support substrate255is equal to or greater than the thickness of the HBM device100. These advantages include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate255and the HBM device100) to help improve heat dissipation efficiency in the integrated circuit package3000. The support substrate255also functions as a heat spreader and dissipates heat from the stack500. Because of the exposed top surface of the support substrate255, a larger amount of heat can be dissipated through the support substrate255and the reliability of the stack500is improved. In addition, the support substrate255used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. FIG.7Aillustrates a cross-sectional view of an integrated circuit package4000, in which a stack600and a HBM device100are shown bonded and electrically connected to a structure310using conductive connectors270and conductive connectors114, respectively.FIGS.7B through7Gillustrate cross-sectional views of intermediate steps in the forming of the stack600, in accordance with an alternate embodiment. Unless specified otherwise, like reference numerals in the integrated circuit package4000, (and subsequently discussed embodiments) represent like components in the integrated circuit package1000ofFIGS.4A through4I, that are formed by like processes, and unless specified otherwise, like reference numerals in the stack600, (and subsequently discussed embodiments) represent like components in the stack200ofFIGS.4A through4I, that are formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. FIG.7Bshows a cross-sectional view of a bottom wafer650A. The bottom wafer650A may include different die regions that are singulated in subsequent steps to form a plurality of die regions. The bottom wafer650A and the bottom wafer550A shown previously inFIG.6Bmay be essentially the same, with like reference numerals representing like components. Accordingly, the process steps and applicable materials may not be repeated herein. InFIG.7C, a top die650B is bonded to the bottom wafer650A to form a system-on-integrated-chip (SoIC) device. It should be appreciated that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages. The top die650B may be formed in a wafer, which may include different die regions that are then singulated to form a plurality of top dies650B. The top die650B and the top die550B shown previously inFIG.6Bmay be essentially the same, with like reference numerals representing like components. Accordingly, the process steps and applicable materials may not be repeated herein. In some embodiments, the top die650B is a logic die, and the bottom wafer650A is used as an interface to bridge the logic die to memory devices (e.g., memory devices11of the HBM device100shown inFIG.7A), and to translate commands between the logic die and the memory devices. In some embodiments, the top die650B and the bottom wafer650A are bonded such that the active surfaces253are facing each other (e.g., are “face-to-face” bonded). The bottom wafer650A is bonded to the top die650B, for example, using a hybrid bonding process that may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. The hybrid bonding process directly bonds the dielectric layer260of the bottom wafer650A to the dielectric layer258of the top die650B through fusion bonding. In an embodiment, the bond between the dielectric layer260and the dielectric layer258may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors259of the bottom wafer650A and the conductive connectors256of the top die650B through direct metal-to-metal bonding. Thus, the bottom wafer650A and the top die650B are electrically connected. InFIG.7D, insulating material222is formed over the bottom wafer650A and the top die650B. The insulating material222surrounds the top die650B and may comprise a dielectric material such as a silicon oxide, or the like, formed by a CVD or PECVD process. A planarization step such as CMP, or the like, may then be performed to level top surfaces of the insulating material222with a top surface of the top die650B. Still referring toFIG.7D, a dielectric layer276is formed over top surfaces of the insulating material222and the top die650B. The dielectric layer276and the may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer276may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The dielectric layer276may then be patterned and openings formed in the dielectric layer276. Conductive connectors280are then formed in the dielectric layer276. The conductive connectors280are formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors280may comprise conductive pillars, pads, or the like, to which external connections are made. The conductive connectors280may be exposed through the dielectric layer276by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors278. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors280and the dielectric layer276are coplanar (within process variations). In an embodiment, an eighth height H8between a top surface of the dielectric layer276and a bottom surface of the dielectric layer258may be equal or less than 780 μm. InFIG.7E, a support substrate255is bonded to the insulating material222and the inactive surface of the semiconductor substrate252of the top die650B. The support substrate255may include a bulk substrate or a wafer, and may be formed of a material such as silicon, ceramic, heat conductive glass, a metal such as copper or iron, or the like. The support substrate255may be free of any active or passive devices. In an embodiment, the support substrate255may include metallization layer(s) on a top surface of the support substrate255. In some embodiments, the support substrate is formed of a material that produces a low amount of residue during CMP, such as silicon. The support substrate255is bonded to the inactive surface of the semiconductor substrate252of the top die650B and the insulating material222using a suitable technique such as hybrid bonding, or the like. For example, a dielectric layer274is formed over the support substrate255. The dielectric layer274may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer274may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The dielectric layer274may then be patterned and openings formed in the dielectric layer274. Conductive connectors278are then formed in the dielectric layer274. The conductive connectors278are formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors278may comprise conductive pillars, pads, or the like, to which external connections are made. The conductive connectors278may be exposed through the dielectric layer274by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors278. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors278and the dielectric layer274are coplanar (within process variations). The hybrid bonding process then directly bonds the dielectric layer274of the support substrate255to the dielectric layer276of the semiconductor substrate252and the insulating material222through fusion bonding. In an embodiment, the bond between the dielectric layer274and the dielectric layer276may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors278of the support substrate255to the conductive connectors280of the semiconductor substrate252and the insulating material222through direct metal-to-metal bonding. The hybrid bonding process may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. In an embodiment, the height between a top surface of the support substrate255and a bottom surface of the dielectric layer274may be a fourth substrate height S4. InFIG.7F, a planarization step such as CMP, or the like, may then be performed to expose the conductive vias262of the bottom wafer650A. After the planarization step, a top surface of the semiconductor substrate252of the bottom wafer650A is level with top surfaces of the conductive vias262. FIG.7Gshows the formation of contact pads268and a dielectric layer266over the stack600. The dielectric layer266may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer266may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The contact pads268may be used for connections to other devices. In some embodiments, the contact pads are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer266. In the illustrated embodiment, the contact pads268are formed through the dielectric layer266. As an example to form the contact pads268, openings are formed in the dielectric layer266, and a seed layer is formed over the dielectric layer266and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads268. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the contact pads268. In an embodiment, a ninth height H9between a bottom surface of the dielectric layer260and a top surface of the dielectric layer266may be in a range from 15 μm to 30 μm. In an embodiment, the sum of the eighth height H8, the ninth height H9, and the fourth substrate height S4is equal to or larger than the third height H3. In an embodiment, a top surface of the support substrate255is at the same level as a top surface of the HBM device100. In an embodiment, the top surface of the support substrate255is higher than the top surface of the HBM device100. Advantages can be achieved as a result of the formation of the integrated circuit package4000that includes the top die650B bonded to the bottom wafer650A (e.g., to form a logic device), and the HBM device100. The integrated circuit package4000further includes the support substrate255over the top die650B and the bottom wafer650A. The total thickness of the top die650B, the bottom wafer650A, and the support substrate255is equal to or greater than the thickness of the HBM device100. These advantages include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate255and the HBM device100) to help improve heat dissipation efficiency in the integrated circuit package4000. The support substrate255also functions as a heat spreader and dissipates heat from the stack600. Because of the exposed top surface of the support substrate255, a larger amount of heat can be dissipated through the support substrate255and the reliability of the stack600is improved. In addition, the support substrate255used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. FIG.8Aillustrates a cross-sectional view of an integrated circuit package5000, in which a stack700and a HBM device100are shown bonded and electrically connected to a structure310using conductive connectors270and conductive connectors114, respectively.FIGS.8B through8Fillustrate cross-sectional views of intermediate steps in the forming of the stack700, in accordance with an alternate embodiment. Unless specified otherwise, like reference numerals in the integrated circuit package5000, (and subsequently discussed embodiments) represent like components in the integrated circuit package1000ofFIGS.4A through4I, that are formed by like processes, and unless specified otherwise, like reference numerals in the stack700, (and subsequently discussed embodiments) represent like components in the stack200ofFIGS.4A through4I, that are formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. FIG.8Bshows a cross-sectional view of a bottom wafer750A. Each bottom wafer750A may comprise a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die). The bottom wafer750A may include different die regions that are singulated in subsequent steps to form a plurality of die regions. InFIG.8B, a semiconductor substrate252, and an interconnect structure254over the semiconductor substrate252are shown. The semiconductor substrate252may be a substrate of silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate252may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate252has an active surface253(e.g., the surface facing upward inFIG.8B) and an inactive surface (e.g., the surface facing downward inFIG.8B). The active surface253may also be referred to as the active device layer253. Devices are at the active surface253of the semiconductor substrate252. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free from devices. The interconnect structure254is over the active surface253of the semiconductor substrate252, and is used to electrically connect the devices of the semiconductor substrate252to form an integrated circuit. The interconnect structure254may include one or more dielectric layer(s) and respective metallization layer(s) in the dielectric layer(s). Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like. Other dielectric materials may also be used, such as a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobuten (BCB) based polymer, or the like. The metallization layer(s) may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate252. The metallization layer(s) may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure254may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, a contact pad251may be formed in the interconnect structure254to which external connections are made to the interconnect structure254and the devices of the active layer253. The contact pad251is disposed over the active surface253. The contact pad251may comprise copper, aluminum (e.g.,28K aluminum), or another conductive material. The contact pad251may not be explicitly shown in subsequent figures. Conductive vias262may be formed through the bottom wafer750A to allow external connections to be made to the stack700(shown subsequently inFIG.8F). The conductive vias262may be through-substrate vias (TSVs), such as through-silicon vias or the like. The conductive vias262extend through the semiconductor substrate252of the bottom wafer750A, to be physically and electrically connected to the metallization layer(s) of the interconnect structure254. Still referring toFIG.8B, conductive connectors259are shown which may be in and/or on the interconnect structure254of the bottom wafer750A. For example, the conductive connectors259may be part of an upper metallization layer of the interconnect structure254. The conductive connectors259can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors259may be conductive pillars, pads, or the like, to which external connections are made. A dielectric layer260is in and/or on the interconnect structure254. For example, the dielectric layer260may be an upper dielectric layer of the interconnect structure254. The dielectric layer260laterally encapsulates the conductive connectors259. The dielectric layer260may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer260may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. Initially, the dielectric layer260may bury the conductive connectors259, such that the top surface of the dielectric layer260is above the top surfaces of the conductive connectors259. The conductive connectors259may be exposed through the dielectric layer260by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors259. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors259and the dielectric layer260are coplanar (within process variations). InFIG.8C, a top wafer750B is bonded to the bottom wafer750A to form a system-on-integrated-chip (SoIC) device. It should be appreciated that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages. The top wafer750B may include different die regions that are singulated in subsequent steps to form a plurality of die regions. The top wafer750B includes a semiconductor substrate252, an interconnect structure254, and may include an active surface253, which are similar to those described forFIG.8B. In addition, the top wafer750B may comprise conductive connectors256, and a dielectric layer258which may be in and/or on the interconnect structure254of the top wafer750B. The conductive connectors256may be formed using like processes and like materials as the conductive connectors259(described previously inFIG.8B). The dielectric layer258may be formed using like processes and like materials as the dielectric layer260(described previously inFIG.8B). In an embodiment, the top wafer750B has a tenth height H10that may be equal to or less than 780 μm. In some embodiments, the top wafer750B comprises a logic die, and the bottom wafer750A is used as an interface to bridge the logic die to memory devices (e.g., memory devices11of the HBM device100shown inFIG.8A), and to translate commands between the logic die and the memory devices. In some embodiments, the top wafer750B and the bottom wafer750A are bonded such that the active surfaces253are facing each other (e.g., are “face-to-face” bonded). The bottom wafer750A is bonded to the top wafer750B, for example, using a hybrid bonding process that may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. The hybrid bonding process directly bonds the dielectric layer260of the bottom wafer750A to the dielectric layer258of the top wafer750B through fusion bonding. In an embodiment, the bond between the dielectric layer260and the dielectric layer258may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors259of the bottom wafer750A and the conductive connectors256of the top wafer750B through direct metal-to-metal bonding. Thus, the bottom wafer750A and the top wafer750B are electrically connected. InFIG.8D, a support substrate255is bonded to a top surface of the inactive surface of the semiconductor substrate252of the top wafer750B. The support substrate255may include a bulk substrate or a wafer, and may be formed of a material such as silicon, ceramic, heat conductive glass, a metal such as copper or iron, or the like. The support substrate255may be free of any active or passive devices. In an embodiment, the support substrate255may include metallization layer(s) on a top surface of the support substrate255. In some embodiments, the support substrate is formed of a material that produces a low amount of residue during CMP, such as silicon. In an embodiment, the height of the support substrate255may be a fifth substrate height S5. The support substrate255is bonded to the top surfaces of the inactive surface of the semiconductor substrate252of the top wafer750B using a suitable technique such as fusion bonding, or the like. For example, in various embodiments, the support substrate255may be bonded to the semiconductor substrate252using bonding layers227a/bon the surfaces of the support substrate255and the semiconductor substrate252, respectively. In some embodiments, the bonding layers227a/bmay each comprise silicon oxide formed on the surfaces of the support substrate255and the semiconductor substrate252, respectively by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In other embodiments, the bonding layers227a/bon the support substrate255and the semiconductor substrate252may be formed by the thermal oxidation of silicon surfaces on the support substrate255and the semiconductor substrate252, respectively. Prior to bonding, one or more of the bonding layers227a/bmay be subjected to a surface treatment. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water, or the like) that may be applied to at least one of the bonding layers227a/b. The support substrate255is then aligned with the semiconductor substrate252, and pressed against each other to initiate a pre-bonding of the support substrate255to the semiconductor substrate252. The pre-bonding may be performed at room temperature (between about 21 degrees and about 25 degrees). The bonding time may be shorter than about 1 minute, for example. After the pre-bonding, the semiconductor substrate252is bonded to the support substrate255. The bonding process may be strengthened by a subsequent annealing step. For example, this may be done by heating the semiconductor substrate252and the support substrate255to a temperature in a range from 140° C. to 500° C. The bonding layers227a/bmay not be shown in subsequent figures. InFIG.8E, a planarization step such as CMP, or the like, may then be performed to expose the conductive vias262of the bottom wafer750A. After the planarization step, a top surface of the semiconductor substrate252of the bottom wafer750A is level with top surfaces of the conductive vias262. FIG.8Fshows the formation of contact pads268and a dielectric layer266over the stack700. The dielectric layer266may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer266may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The contact pads268may be used for connections to other devices. In some embodiments, the contact pads are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer266. In the illustrated embodiment, the contact pads268are formed through the dielectric layer266. As an example to form the contact pads268, openings are formed in the dielectric layer266, and a seed layer is formed over the dielectric layer266and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads268. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the contact pads268. In an embodiment, an eleventh height H11between a bottom surface of the dielectric layer260and a top surface of the dielectric layer266may be in a range from 15 μm to 30 μm. In an embodiment, the sum of the tenth height H10, the eleventh height H11, and the fifth substrate height S5is equal to or larger than the third height H3. In an embodiment, a top surface of the support substrate255is at the same level as a top surface of the HBM device100. In an embodiment, the top surface of the support substrate255is higher than the top surface of the HBM device100. Advantages can be achieved as a result of the formation of the integrated circuit package5000that includes the top wafer750B bonded to the bottom wafer750A (e.g., to form a logic device), and the HBM device100. The integrated circuit package5000further includes the support substrate255over the top wafer750B and the bottom wafer750A. The total thickness of the top wafer750B, the bottom wafer750A, and the support substrate255is equal to or greater than the thickness of the HBM device100. These advantages include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate255and the HBM device100) to help improve heat dissipation efficiency in the integrated circuit package5000. The support substrate255also functions as a heat spreader and dissipates heat from the stack700. Because of the exposed top surface of the support substrate255, a larger amount of heat can be dissipated through the support substrate255and the reliability of the stack700is improved. In addition, the support substrate255used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. FIG.9Aillustrates a cross-sectional view of an integrated circuit package6000, in which a stack800and a HBM device100are shown bonded and electrically connected to a structure310using conductive connectors270and conductive connectors114, respectively.FIGS.9B through9Gillustrate cross-sectional views of intermediate steps in the forming of the stack800, in accordance with an alternate embodiment. Unless specified otherwise, like reference numerals in the integrated circuit package6000, (and subsequently discussed embodiments) represent like components in the integrated circuit package1000ofFIGS.4A through4I, that are formed by like processes, and unless specified otherwise, like reference numerals in the stack800, (and subsequently discussed embodiments) represent like components in the stack200ofFIGS.4A through4I, that are formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. FIG.9Bshows a cross-sectional view of a bottom wafer850A. The bottom wafer850A may include different die regions that are singulated in subsequent steps to form a plurality of die regions. The bottom wafer850A and the bottom wafer750A shown previously inFIG.8Bmay be essentially the same, with like reference numerals representing like components. Accordingly, the process steps and applicable materials may not be repeated herein. InFIG.9C, a top wafer850B is bonded to the bottom wafer850A to form a system-on-integrated-chip (SoIC) device. It should be appreciated that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages. The top wafer850B may include different die regions that are singulated in subsequent steps to form a plurality of die regions. The top wafer850B and the top wafer750B shown previously inFIG.8Cmay be essentially the same, with like reference numerals representing like components. Accordingly, the process steps and applicable materials may not be repeated herein. In some embodiments, the top wafer850B comprises a logic die, and the bottom wafer850A is used as an interface to bridge the logic die to memory devices (e.g., memory devices11of the HBM device100shown inFIG.9A), and to translate commands between the logic die and the memory devices. In some embodiments, the top wafer850B and the bottom wafer850A are bonded such that active surfaces253are facing each other (e.g., are “face-to-face” bonded). The bottom wafer850A is bonded to the top wafer850B, for example, using a hybrid bonding process that may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. The hybrid bonding process directly bonds the dielectric layer260of the bottom wafer850A to the dielectric layer258of the top wafer850B through fusion bonding. In an embodiment, the bond between the dielectric layer260and the dielectric layer258may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors259of the bottom wafer850A and the conductive connectors256of the top wafer850B through direct metal-to-metal bonding. Thus, the bottom wafer850A and the top wafer850B are electrically connected. InFIG.9D, a dielectric layer276is formed over top surfaces of the top wafer850B. The dielectric layer276and the may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer276may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The dielectric layer276may then be patterned and openings formed in the dielectric layer276. Conductive connectors280are then formed in the dielectric layer276. The conductive connectors280are formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors280may comprise conductive pillars, pads, or the like, to which external connections are made. The conductive connectors280may be exposed through the dielectric layer276by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors278. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors280and the dielectric layer276are coplanar (within process variations). In an embodiment, a twelfth height H12between a top surface of the dielectric layer276and a bottom surface of the dielectric layer258may be less than or equal to 780 μm. InFIG.9E, a support substrate255is bonded to an inactive surface of the semiconductor substrate252of the top wafer850B. The support substrate255may include a bulk substrate or a wafer, and may be formed of a material such as silicon, ceramic, heat conductive glass, a metal such as copper or iron, or the like. The support substrate255may be free of any active or passive devices. In an embodiment, the support substrate255may include metallization layer(s) on a top surface of the support substrate255. In some embodiments, the support substrate is formed of a material that produces a low amount of residue during CMP, such as silicon. The support substrate255is bonded to the inactive surface of the semiconductor substrate252of the top wafer850B using a suitable technique such as hybrid bonding, or the like. For example, a dielectric layer274is formed over the support substrate255. The dielectric layer274may be an oxide, a nitride, a carbide, a polymer, the like, or a combination thereof. The dielectric layer274may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The dielectric layer274may then be patterned and openings formed in the dielectric layer274. Conductive connectors278are then formed in the dielectric layer274. The conductive connectors278are formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, plating, or the like. The conductive connectors278may comprise conductive pillars, pads, or the like, to which external connections are made. The conductive connectors278may be exposed through the dielectric layer274by a removal process that can be applied to the various layers to remove excess materials over the conductive connectors278. The removal process may be a planarization process such as a chemical mechanical polish (CMP), an etch-back, combinations thereof, or the like. After the planarization process, top surfaces of the die connectors278and the dielectric layer274are coplanar (within process variations). The hybrid bonding process then directly bonds the dielectric layer274of the support substrate255to the dielectric layer276of the semiconductor substrate252through fusion bonding. In an embodiment, the bond between the dielectric layer274and the dielectric layer276may be an oxide-to-oxide bond. The hybrid bonding process further directly bonds the conductive connectors278of the support substrate255to the conductive connectors280of the semiconductor substrate252through direct metal-to-metal bonding. The hybrid bonding process may be similar to that described previously for the bonding of wafer56A to the wafer56B inFIG.2Cabove. In an embodiment, the height between a top surface of the support substrate255and a bottom surface of the dielectric layer274may be a sixth substrate height S6. InFIG.9F, a planarization step such as CMP, or the like, may then be performed to expose the conductive vias262of the bottom wafer850A. After the planarization step, a top surface of the semiconductor substrate252of the bottom wafer850A is level with top surfaces of the conductive vias262. FIG.9Gshows the formation of contact pads268and a dielectric layer266over the stack800. The dielectric layer266may be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; the like; or a combination thereof. The dielectric layer266may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The contact pads268may be used for connections to other devices. In some embodiments, the contact pads are conductive bumps that are suitable for use with reflowable connectors, such as microbumps, extending through the dielectric layer266. In the illustrated embodiment, the contact pads268are formed through the dielectric layer266. As an example to form the contact pads268, openings are formed in the dielectric layer266, and a seed layer is formed over the dielectric layer266and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads268. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the contact pads268. In an embodiment, a thirteenth height H13between a bottom surface of the dielectric layer260and a top surface of the dielectric layer266may be in a range from 15 μm to 30 μm. In an embodiment, the sum of the twelfth height H12, the thirteenth height H13, and the sixth substrate height S6is equal to or larger than the third height H3. In an embodiment, a top surface of the support substrate255is at the same level as a top surface of the HBM device100. In an embodiment, the top surface of the support substrate255is higher than the top surface of the HBM device100. Advantages can be achieved as a result of the formation of the integrated circuit package6000that includes the top wafer850B bonded to the bottom wafer850A (e.g., to form a logic device), and the HBM device100. The integrated circuit package6000further includes the support substrate255over the top wafer850B and the bottom wafer850A. The total thickness of the top wafer850B, the bottom wafer850A, and the support substrate255is equal to or greater than the thickness of the HBM device100. These advantages include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate255and the HBM device100) to help improve heat dissipation efficiency in the integrated circuit package6000. The support substrate255also functions as a heat spreader and dissipates heat from the stack800. Because of the exposed top surface of the support substrate255, a larger amount of heat can be dissipated through the support substrate255and the reliability of the stack800is improved. In addition, the support substrate255used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. The embodiments of the present disclosure have some advantageous features. The embodiments include the formation of an integrated circuit package that includes a first integrated circuit device bonded to a second integrated circuit device (e.g., to form a logic device), and a memory device. A total thickness of the first integrated circuit device and the second integrated circuit device is smaller than a thickness of the memory device, and the integrated circuit package further includes a support substrate over the first integrated circuit device and the second integrated circuit device. The total thickness of the first integrated circuit device, the second integrated circuit device and the support substrate is equal to or greater than the thickness of the memory device. one or more embodiments disclosed herein may include allowing for a more even surface that can be used to implement thermal solutions (e.g. a heat spreader may be attached to top surfaces of the support substrate and the memory device) to help improve heat dissipation efficiency in the integrated circuit package. In addition, the support substrate used can be of any thickness to accommodate different types of memory devices that may have different thicknesses. In accordance with an embodiment, a semiconductor package includes a redistribution structure; a first device and a second device attached to the redistribution structure, the first device includes a first die; a substrate bonded to a first surface of the first die; and a second die bonded to a second surface of the first die opposite the first surface, includes a total height of the first die and the second die is less than a first height of the second device, and includes a top surface of the substrate is at least as high as a top surface of the second device; and an encapsulant over the redistribution structure and surrounding the first device and the second device. In an embodiment, the bond between the substrate and the first die includes a fusion bond between a first bonding layer on the substrate and a second bonding layer on the first die. In an embodiment, the substrate includes silicon, ceramic, heat conductive glass, or a metal. In an embodiment, the second device includes a memory device. In an embodiment, a top surface of the encapsulant is coplanar with the top surface of the substrate. In an embodiment, a second height of the first device is larger than 900 μm. In an embodiment, the substrate includes a metallization layer on the top surface of the substrate. In an embodiment, the semiconductor package further includes a package substrate attached to an opposite side of the redistribution structure as the first device and the second device; and an underfill between the redistribution structure and the package substrate. In accordance with an embodiment, a method includes forming a first device, where forming the first device includes bonding a first surface of a first die to a substrate; thinning the substrate to reduce the thickness of the substrate to a first thickness; and bonding a second surface of the first die to a second die; attaching the first device and a second device to a redistribution structure; encapsulating the first device and the second device with an encapsulant; and thinning the encapsulant until a top surface of the encapsulant is coplanar with a top surface of the substrate. In an embodiment, the substrate includes silicon, ceramic, heat conductive glass, or a metal. In an embodiment, the top surface of the substrate is at the same height or higher than a top surface of the second device. In an embodiment, the first device is a logic device and the second device is a memory device. In an embodiment, bonding the first surface of the first die to the substrate includes fusion bonding a first bonding layer on the substrate to a second bonding layer on the first die. In an embodiment, bonding the first surface of the first die to the substrate includes directly bonding a first dielectric layer on the first die to a second dielectric layer on the substrate; and directly bonding first conductive connectors on the first die to second conductive connectors on the substrate. In accordance with an embodiment, a method includes forming a first device, where forming the first device includes bonding a first surface of a first die to a second die; bonding a substrate to a top surface of the second die, where the substrate is free of active or passive devices; and attaching the first device and a second device to a redistribution structure; encapsulating the first device and the second device with an encapsulant; and thinning the encapsulant until a top surface of the substrate is exposed. In an embodiment, the method further includes thinning a second surface of the first die to expose conductive vias; surrounding the second die with an insulating material; and bonding the substrate to a top surface of the insulating material. In an embodiment, bonding the substrate to top surfaces of the insulating material and the second die includes directly bonding a first bonding layer on the substrate to a second bonding layer on the insulating material and the second die. In an embodiment, bonding the substrate to top surfaces of the insulating material and the second die includes directly bonding a first dielectric layer on the substrate to a second dielectric layer on the insulating material and the second die, and directly bonding first conductive connectors on the substrate to second conductive connectors on the insulating material and the second die. In an embodiment, the method further includes thinning the substrate to reduce the thickness of the substrate. In an embodiment, the method further includes attaching a package substrate to an opposite side of the redistribution structure as the first device and the second device; and forming an underfill between the redistribution structure and the package substrate. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 141,221 |
11862591 | DETAILED DESCRIPTION Specific details of several embodiments of conductive buffer layers for semiconductor die assemblies, and associated systems and methods are described below. The term “semiconductor device or die” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices (or dies) include logic devices or dies, memory devices or dies, controllers, or microprocessors (e.g., central processing unit (CPU), graphics processing unit (GPU)), among others. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. Further, the term “semiconductor device or die” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished functional device. Depending upon the context in which it is used, the term “substrate” may include a semiconductor wafer, a package substrate, an interposer, a semiconductor device or die, or the like. Suitable steps of the methods described herein can be performed with processing steps associated with fabricating semiconductor devices (wafer-level and/or die-level) and/or manufacturing semiconductor packages. Various computing systems or environments, e.g., high-performance computing (HPC) systems, require high bandwidth and low power consumption. Certain schemes of forming interconnects between semiconductor dies (e.g., a direct bonding scheme) may facilitate satisfying the requirements, as well as providing form-factors suitable for scaling physical dimensions (e.g., heights) of semiconductor die assemblies of the HPC systems. The direct bonding scheme includes individual conductive components (e.g., copper pads, conductive pads, bond pads) of a first semiconductor die (or a first wafer including the first semiconductor die) aligned and directly bonded to corresponding one of conductive components of a second semiconductor die (or a second wafer including the second semiconductor die). Further, a dielectric material surrounding each of the conductive pads of the first semiconductor die can be directly bonded to another dielectric material surrounding each of the conductive pads of the second semiconductor die. In other words, the bonding interface includes two or more dissimilar materials of the first semiconductor die directly bonded to corresponding materials of the second semiconductor die (e.g., between dielectric materials, between conductive materials) to form interconnects and surrounding dielectric layers. As such, the direct bonding scheme may also be referred to a combination bonding scheme, a hybrid bonding scheme, or the like. In some embodiments, the conductive materials include copper (or other suitable conductive materials or metals, such as tungsten, aluminum, or gold) as a primary constituent, and the dielectric materials include silicon oxides (e.g., SiO2), silicon nitrides (e.g., Si3N4), silicon carbon nitrides (e.g., SiCN), silicon carbonates (e.g., SiCO), or the like. During the direct bonding process, the dielectric materials of the first and second semiconductor dies (or the first and second wafers including the first and second semiconductor dies) are brought together such that the dielectric materials adhere to each other and hermetically seal the conductive components aligned to each other. Subsequently, the semiconductor dies are annealed at an elevated temperature (e.g., post bond annealing process) such that the conductive materials of the conductive pads can expand—e.g., swell vertically toward the bonding interface—at least partially due to the differences in coefficients of thermal expansion (CTE) between the conductive materials and the dielectric materials. This phenomenon may be referred to as CTE-based expansion of the conductive pads. Eventually, the conductive materials are conjoined to form permanent bonding between them—e.g., metallurgical bonding. Additionally, the dielectric materials may enhance their bonding strength during the post bond annealing process. In some embodiments, the post bond annealing process can be carried out at approximately 250° C. for 2 hours or so. In some embodiments, the conductive pads have recessed surfaces with respect to the surface of the dielectric materials. In this manner, when the dielectric materials of the semiconductor dies adhere to each other (e.g., prior to the post bond annealing process), bonding of the dielectric materials can be accomplished without any interference from protruded conductive pads. Further, the recess amount (e.g., a depth of recess, a recess depth, a dishing amount) for the conductive pads may be devised and controlled to be within a certain range. The recess amount may determine whether the conductive materials (e.g., copper) can be suitably conjoined to each other during the post bond annealing process without compromising the bonding strength or the interconnect characteristics. For example, if the recess depths of the conductive pads are insufficient (e.g., too shallow), the conductive materials, during the annealing process, may expand to pry open (e.g., pull apart, delaminate) the bonding interface between the dielectric materials, at least in the region proximate to the conductive pads—e.g., resulting in oxide openings. On the other hand, if the recess depths are excessive (e.g., too deep), the conductive materials, during the annealing process, may not be sufficiently conjoined to each other to form robust interconnects—e.g., resulting in resistive copper joints or copper joints openings. Accordingly, controlling the recess depths may affect yield or reliability of the direct bonding process, and tends to impose strict requirements to various process conditions and/or design factors. For example, conductive pads may be designed (e.g., laid out) to have widths (or lengths) of certain ranges to reduce variations in the recess depths. In some embodiments, the conductive pads may be partitioned or be surrounded with dummy pads to satisfy certain areal density requirements. In some cases, elaborate targeting of the recess depths may be carried out to determine suitable process conditions—e.g., over-polish targeting during chemical-mechanical polish (CMP) process steps used to generate the conductive pads. Even so, statistical random process variations (e.g., life of CMP pads, variations in CMP slurries) may present challenges to the recess depth control. In some embodiments, variations in the recess depths need to be less than ±5 nanometers (nm) across the entire wafer (e.g., across 300 mm diameter of the wafer). The variations in the recess depths may be referred to as a coplanarity of the conductive pads and maintaining the coplanarity of the conductive pads within a tolerable limit (e.g., within ±5 nm) may increase cost for the semiconductor die assemblies. The present technology provides for conductive buffer layers to facilitate relaxing the recess depth requirements—i.e., widening the tolerable limits for the conductive pads coplanarity for hybrid bonding schemes. Such conductive buffer layers can be disposed between the conductive pads before two or more semiconductor dies are attached to each other during the hybrid bonding process. In some embodiments, the conductive buffer layer is porous and includes conductive particles—e.g., copper particles, silver particles, gold particle, nickel particles, or other suitable conductive nanoparticles. In some embodiments, the conductive particles have diameters of approximately 15 nm to 50 nm. In some embodiments, the conductive buffer layer is flexible (e.g., malleable, squeezable, elastic, compressible, or otherwise adaptable) under pressure applied to the conductive buffer layer. In response to the pressure applied to the conductive buffer layer (e.g., when the conductive pads expand into the conductive buffer layer responsive to thermal energy applied to the conductive pads), the conductive buffer layer may deform (e.g., as a result of conductive particles transporting to regions with relatively less pressure). Additionally, or alternatively, the conductive particles may be brought closer to one another or be compressed together (e.g., migrating within the conductive buffer layer) such that the conductive buffer layer occupies less volume. As such, the conductive buffer layer may become less porous as a result of being subject to the pressure. In some embodiments, in response to receiving thermal energy (e.g., during the post bond annealing process at 250° C. for 2 hours) and/or being subject to the pressure, the conductive particles may coalesce (e.g., aggregate, merge, fuse, amalgamate) to form electrically conductive structures (e.g., similar to sintered metal). In a particular embodiment, the post bond annealing process provides sintering for the conductive particles. The electrically conductive structures may be porous in their nature. In some embodiments, the electrically conductive structures have porosity of approximately 30%, which is expected to have no significant effect on the electrical conductivity. Moreover, the porosity of the electrically conductive structures may vary based on the thermal energy (e.g., post bond annealing temperature or time) and/or the magnitude of pressure (e.g., due to variations in the recess depths) applied to the conductive particles. In some embodiments, the electrically conductive structures includes the porosity of 30±10%. In other embodiments, the electrically conductive structures includes the porosity of less than 20%. In view of the conductive buffer layer present between the upper and lower conductive pads to be directly bonded, the recess depths can be targeted to be relatively aggressive—e.g., generating generally greater recess amounts when compared to the recess depths absent the conductive buffer layer. In this manner, when the conductive pads expand, e.g., during the post bond annealing process, the conductive buffer layer can provide a squeezable cushion (e.g., a buffer region, compressible room) against the rigid conductive pads bumping into each other—e.g., when one or more conductive pads have recess depths inadequately shallow tending to result in oxide openings without the conductive buffer layer. Alternatively, the conductive buffer layer can provide an electrically conductive medium between the conductive pads even if the conductive pads do not physically connect to each other after completing the post bond annealing process—e.g., when one or more conductive pads have recess depths inadequately deep tending to result in resistive copper joints or copper joints openings without the conductive buffer layer. As used herein, the terms “front,” “back,” “vertical,” “lateral,” “down,” “up,” “top,” “bottom,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor device assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. FIG.1illustrates various stages of process steps for direct bonding schemes. Diagram100A illustrates a portion of a semiconductor die101with a substrate110having integrated circuitry (not shown) and a through-substrate via (TSV)115coupled with the integrated circuitry. In some embodiments, the TSV115includes a first conductive material117(e.g., tungsten) and a conductive barrier layer118(e.g., TiN). The semiconductor die101also includes a conductive pad125(which may also be referred to as a bond pad) formed in a dielectric layer120(e.g., silicon oxides, silicon nitrides, silicon carbon nitrides, silicon carbonates, or a combination thereof). The conductive pad125is electrically connected to the TSV115(and to the integrated circuitry through the TSV115). In some embodiments, the conductive pad125includes a second conductive material127(e.g., copper) and another conductive barrier layer128(e.g., TaN). The conductive pad125depicted in diagram100A includes a surface recessed by a depth D with respect to the surface of the dielectric layer120(i.e., the surface opposite to the substrate110). In some embodiments, CMP process steps are used to form the conductive pad125, and the recess may be a result of the CMP process. For example, the recess may be formed during over-polishing steps that remove excessive conductive material127on the surface of the dielectric layer120. Moreover, the amount of recess (e.g., the recess depth D) may be targeted to ensure the surface of the conductive pad125not to protrude above the surface of the dielectric layer120—e.g., to avoid such protruded conductive pads125interfering with the bonding process described with reference to diagram1008. The amount of recess may be targeted to be within a certain range such that the conductive materials127can form an interconnect140without compromising overall bonding integrity as described with reference to diagram100C. Diagram100B illustrates two semiconductor dies101aand101b(or two wafers including the semiconductor dies101aand101b) that are attached together such that dielectric materials of the top semiconductor die101band bottom semiconductor die101aadhere to each other to form dielectric-to-dielectric bonding130at the bonding interface105. In some embodiments, the dielectric surfaces are activated (e.g., using a plasma treatment process) to facilitate the bonding of the dielectric surfaces. Also, conductive pads (e.g., the top conductive pad125band the bottom conductive pad125a) of the top and bottom semiconductor dies101aand101bare aligned to face each other but are not connected to each other due to the recessed surfaces of the conductive pads125a/b. Diagram100C illustrates that the bonded dies/wafers are annealed in an elevated temperature (e.g., around 400° C.) such that the conductive materials of the top and bottom conductive pads125a/bmay expand toward each other in response to receiving thermal energy during the post bond annealing process (e.g., due to the mismatch in CTEs between the conductive materials and the dielectric materials) within the open space defined by the recess surfaces and the dielectric material surrounding the conductive pads125a/b. When the surfaces of the top and bottom conductive materials are in contact as a result of the CTE-based expansion, the conductive materials are conjoined (e.g., via atomic migration (intermixing, diffusion) from one conductive material to another conductive material) to form metal-to-metal bonding135—e.g., metallurgical bonding, permanent bonding. Once the metallurgical bonding is formed between the conductive pads125a/b(thus, forming the interconnect140), the conductive materials do not separate (or sever) when the bonded dies/wafers are brought to the ambient temperature or operating temperatures of the semiconductor die assemblies. In this manner, the bonding interface105includes the dielectric-to-dielectric bonding130and the metal-to-metal bonding135. FIGS.2A-Billustrate schematic diagrams200A through200D depicting stages of a process forming semiconductor die assemblies in accordance with embodiments of the present technology. Diagram200A illustrates a portion of a semiconductor die201, which may be an example of or include aspects of the semiconductor die101described with reference toFIG.1. For example, the semiconductor die201includes the substrate110having integrated circuitry (not shown) and the dielectric layer120. The semiconductor die201also includes one or more conductive pads225formed in the dielectric layer120. The conductive pads225may be examples of or include aspects of the conductive pads125described with reference toFIG.1. The TSVs115coupling the conductive pads225to the integrated circuitry are omitted inFIGS.2A-B. The conductive pad225has a surface230recessed with respect to a surface235of the dielectric layer120(the amount of recess denoted as D)—e.g., as a result of the CMP process described with reference toFIG.1. As shown in diagram200A, the surface of the conductive pad225is uncovered (i.e., exposed) at this stage of the process. Diagram200B illustrates a conductive buffer layer210formed on the conductive pads225. Also illustrated in diagram200B are an optional sacrificial layer215between the conductive pads225and the conductive buffer layer210and an optional mask237on the surface235of the dielectric layer120. In some embodiments, the conductive buffer layer210adheres to the sacrificial layer215. As such, the sacrificial layer215may be regarded as a tacky layer (or an adhesion layer) for the conductive buffer layer210. In some embodiments, the sacrificial layer215includes flux that protects the surface230of the conductive pads225from oxidation. In some embodiments, the sacrificial layer215is configured to decompose at an elevated temperature—e.g., at a temperature of about 100° C. or greater. In some embodiments, the sacrificial layer215forms only on the conductive pads225using masked deposition process steps—e.g., using a mask layer (e.g., a photoresist layer, a hard-mask layer) on the surface235of the dielectric layer120, which includes openings corresponding to the conductive pads225. In some embodiments, the conductive buffer layer210may be formed on the conductive pads225based on depositing conductive particles (e.g., copper particles) over the conductive pads225while blocking the conductive particles from depositing on the surface235of the dielectric layer120unoccupied by the conductive pads225. In some embodiments, screen-printing techniques is used to deposit the conductive particles over the conductive pads225only. In other embodiments, masked deposition techniques is used to deposit the conductive particles over the conductive pads225only. In some embodiments, the conductive particles deposited over the conductive pads225may be sintered at an elevated temperature (e.g., 100° C. or greater). In some embodiments, the conductive buffer layer210may be formed on the conductive pads225based on selectively sintering conductive particles that have been disposed over the conductive pads225. For example, a layer of liquid including conductive particles is coated on the semiconductor die201(e.g., on the surface230of the conductive pads225and on the surface235of the dielectric layer120). Subsequently, precision electromagnetic radiation (e.g., laser) may be used to selectively sinter the conductive particles on the conductive pads225only. Thereafter, the un-sintered conductive particles are removed (e.g., from the surface235of the dielectric layer120). In some embodiments, the conductive buffer layer210may be formed on the conductive pads225based on selectively spraying a solution including conductive particles (e.g., copper nanoparticle ink) over the conductive pads225. For example, the copper nanoparticle ink can be directly sprayed on the surface230of the conductive pads225using a precision nozzle. Subsequently, the copper nanoparticle ink deposited over the conductive pads225may be sintered at an elevated temperature (e.g., 100° C. or greater). In some embodiments, while the conductive buffer layer210is formed on the conductive pads225, the optional mask237(e.g., a photoresist, a hard-mask of organic and/or inorganic materials) is deployed on the surface235of the dielectric layer120. After the conductive buffer layer210has been formed only on the conductive pads225, the mask237is removed. In this manner, the surface235of the dielectric layer120can be protected during the various process steps associated with forming the conductive buffer layer210on the conductive pads225. Further, during the sintering process steps, the conductive particles may be protected from oxidation. For example, oxygen pumping (to minimize oxygen partial pressure in the ambient) may be used during the sintering process. In some instances, the sintering may be carried out in a H2ambient. In some cases, oxides formed on the surface of conductive particles can be reduced (or removed) using formic acid cleaning. Diagram200C illustrates two semiconductor dies201(also identified individually as semiconductor dies201aand201b) that are attached together to form the bonding interface205as described with reference toFIG.1(e.g., diagram100B). In a particular aspect of an embodiment shown in diagram200C, the lower (bottom) semiconductor die201aincludes the conductive buffer layer210and the optional sacrificial layer215while the upper (top) semiconductor die201bdoes not. In a further particular aspect of this embodiment, the surface235aof dielectric layer120aof the semiconductor die201ais in contact with the surface235bof dielectric layer120bof the semiconductor die201bforming the dielectric-to-dielectric bonding at the bonding interface205. As shown in diagram200C, two semiconductor dies201aand201bare arranged such that the conductive pads225(also identified individually as conductive pads225a/b) of the semiconductor dies201aand201bare aligned to each other—e.g., the conductive pad225aaligned to the conductive pad225b. Subsequently, the semiconductor dies201aand201b(or the wafers including the semiconductor dies201aand201b) are brought to an elevated temperature (e.g., post bond annealing process steps) to facilitate the CTE-based expansion of the conductive pads225. Diagram200D illustrates that interconnects240are formed—e.g., as a result of the post bond annealing process. In other words, the conductive pads225aand225bexpand upon receiving thermal energy at the elevated temperature (e.g., during the post bond annealing process) such that the surfaces230of the conductive pads225aand225badvance toward the bonding interface205. Moreover, the sacrificial layer215may decompose subject to the thermal energy (e.g., during the post bond annealing process). Accordingly, the sacrificial layer215is omitted in the diagram200D. In some embodiments, the conductive buffer layer210allows a wider range of variations in the recess depths—e.g., widening a tolerable limit for the coplanarity of the conductive pads225. For example, the coplanarity of the conductive pads225may be required to be within ±5 nm absent the conductive buffer layer210. With the conductive buffer layer210included in at least one of the semiconductor dies201a/b, the tolerable limit for the coplanarity of the conductive pads225may be widened (e.g., increased, relaxed) to a greater value, such as ±7 nm, ±10 nm, ±15 nm, or even greater. As a result of using the conductive buffer layer210, the interconnects240include a conductive buffer material (i.e., conductive buffer material included in the conductive buffer layer210) in addition to the conductive pads225—e.g., between the conductive pads225a/b. In some embodiments, the conductive buffer layer is less dense than the upper and lower conductive pads225(e.g., copper pads formed by electroplating process steps). Although the diagram200D illustrates the conductive buffer layer210generally in a plane corresponding to the bonding interface205, locations of the conductive buffer layer210may vary with respect to the bonding interface205in view of varying recess depths of the conductive pads225as described in more detail with reference toFIG.4. Further, the conductive buffer layer210may be discontinuous at certain locations—e.g., the interconnects240may include a portion where the conductive pads225from the lower and upper semiconductor dies201a/bforming direct metal-to-metal bonding. Although the foregoing example schematic diagrams illustrate only one of semiconductor dies201aor201bhaving the conductive buffer layer210, the present technology is not limited thereto. For example, both of the semiconductor dies201aand201bcan include the conductive buffer layer210. FIGS.3A-Cillustrate schematic diagrams300A through300E depicting stages of a process forming semiconductor die assemblies in accordance with embodiments of the present technology. Diagram300A illustrates the semiconductor die201aafter the conductive buffer layer210ahas been formed on the conductive pads225as described with reference to the diagram200B. In some embodiments, the semiconductor die201ais the same type of semiconductor die as the semiconductor dies (e.g., memory dies) that the semiconductor die201acarries (e.g., semiconductor die201b, semiconductor dies301a/b). In other embodiments, the semiconductor die201ais an interface die. The interface die may be different types of semiconductor dies (e.g., logic dies, controller dies) than the semiconductor dies that the semiconductor die201acarries. In some embodiments, a logic die is configured to exchange electrical signals with the semiconductor dies it carries and with higher level circuitry (e.g., a host device) coupled with the logic die. In some embodiments, the interface die is an interposer die having various conductive structures (e.g., redistribution layers, vias, interconnects) configured to route electrical signals between the semiconductor dies it carries and higher level circuitry—e.g., a central processing unit (CPU) coupled with the interposer die. Diagram300A also illustrates a semiconductor die301a, which may be an example of or include aspects of the semiconductor die201b. For example, the semiconductor die301aincludes the substrate110including integrated circuitry (not shown). Further, the semiconductor die301aincludes dielectric layers120c/dformed on both sides of the substrate110. The semiconductor die301amay be referred to as a middle die of a stack of semiconductor dies. The semiconductor die301aincludes conductive pads225(also identified individually as conductive pads225cand225d) in both of the dielectric layers120c/dsuch that the semiconductor die301acan be attached to a semiconductor die underneath (e.g., the semiconductor die201a) and a semiconductor die above (e.g., semiconductor die301bas shown in diagrams300C/D). Diagram300B illustrates the semiconductor die301ahas been directly attached to the semiconductor die201a—e.g., the dielectric layer120aof semiconductor die201aand the dielectric layer120cof the semiconductor die301aform dielectric-to-dielectric bonding at the bonding interface205a. Subsequently, the conductive buffer layer210bis formed on the conductive pads225dof the semiconductor die301a. Also illustrated in diagram300B is the optional sacrificial layer215b. Diagram300C illustrates that another semiconductor die301b, which may be an example of or include aspects of the semiconductor die201b. For example, the semiconductor die301bincludes the substrate110bincluding integrated circuitry (not shown) and a dielectric layer120e. The semiconductor die301bmay be referred to as a top die of a stack of semiconductor dies. The semiconductor die301bincludes conductive pads225(also identified individually as conductive pads225e) in its dielectric layer120. The substrate110bmay be thicker than the substrates of the middle semiconductor dies. Diagram300D illustrates the semiconductor die301bhas been directly attached to the semiconductor die301a—e.g., the dielectric layer120eof semiconductor die301band the dielectric layer120dof the semiconductor die301aform another dielectric-to-dielectric bonding at the bonding interface205b. Subsequently, the stack of semiconductor dies201a,301a, and301bcan be brought to an elevated temperature (e.g., post bond annealing process steps) to have the conductive pads225of all semiconductor dies (e.g., semiconductor dies201a,301a, and301b) expand (e.g., during the post bond annealing process) to form interconnects. Moreover, the sacrificial layer215may decompose at the elevated temperature. Diagram300E illustrates a semiconductor die assembly370including the semiconductor dies201a,301a, and301b. As a result of the post bond annealing process, the conductive pads225from the upper and lower semiconductor dies conjoin to form interconnects240(also identified individually as interconnects240a/b) between the semiconductor dies. Each of the interconnects240includes a conductive buffer material (e.g., the conductive buffer material of the conductive buffer layer210) in addition to the conductive pads (e.g., between the conductive pads) from the upper and lower semiconductor dies. The optional sacrificial layers215a/bis no longer included in the diagram300E as they have decomposed during the post bond annealing process as described above. Although the semiconductor die assembly370as shown in the diagram300E includes one middle semiconductor die301a, the present technology is not limited thereto. For example, in other embodiments, the semiconductor die assembly370includes two or more middle semiconductor dies301a—e.g., four (4), eight (8), twelve (12), or even greater quantity of middle semiconductor dies. FIG.4illustrates cross-sectional schematic diagrams400A through400E of interconnects440a-efor semiconductor die assemblies in accordance with embodiments of the present technology. The interconnects440a-emay be examples of or include aspects of interconnects140or240described with reference toFIGS.1through3. For example, each of the interconnects440a-eincludes the conductive buffer layer210(also identified individually as conductive buffer layer210a-e) (or the conductive buffer material of the conductive buffer layer210) in addition to conductive pads225(also identified individually as upper conductive pads225-1and lower conductive pads225-2) from the top (upper) semiconductor die (e.g., the semiconductor die201b, the semiconductor die301b) and the bottom (lower) semiconductor die (e.g., the semiconductor die201a) with respect to the bonding interface205, respectively. Diagram400A depicts the interconnect440aincluding the conductive buffer layer210alocated generally at the bonding interface205. Recess depths of the conductive pads225-1/2may have been comparable to each other such that the CTE-based expansion of the conductive pads225-1/2brings the conductive buffer layer210aapproximately at the bonding interface205. As depicted in the diagram400A, the surface of conductive pad225-1is separate from the surface of conductive pad225-2but the conductive buffer layer210aelectrically couples the conductive pad225-1with the conductive pad225-2to avoid the interconnect440abeing highly resistive or electrically open. Diagram400B depicts the interconnect440bincluding the conductive buffer layer210blocated slightly off of the bonding interface205. At least partially due to the process variations in generating the conductive pads225-1/2, the recess depths of the conductive pads225-1/2may have been dissimilar (e.g., the conductive pad225-2has a shallower recess depth than that of the conductive pad225-1). As a result of the variations in recess depth of the conductive pads225-1/2, the CTE-based expansion of the conductive pads225-1/2may bring the conductive buffer layer210boff of the bonding interface205. Diagram400C depicts the interconnect440cincluding the conductive buffer layer210cthat may be discontinuous at certain regions. In other words, at least a portion of the surface of the conductive pad225-1is conjoined to at least another portion of the surface of the conductive pad225-2—e.g., at least partial metal-to-metal bonding occurred between the conductive pads225-1and225-2. Although the conductive buffer layer210cis shown generally at the bonding interface205, the conductive buffer layer210cmay be located off of the bonding interface205in view of the variations in recess depth of the conductive pads225-1/2. Diagram400D depicts the interconnect440dincluding the conductive buffer layer210dlocated below the bonding interface205. Further, the interconnect440dincludes the conductive pad225-1extending past the bonding interface205. The conductive pad225-1may represent a conductive pad protruded above the surface of the dielectric layer, in which the conductive pad is formed—e.g., after completing the CMP process generating the conductive pad. Such a protruded conductive pad may be regarded as an extreme incoming condition for the hybrid bonding process, which tends to hinder forming a robust hybrid bonding interface without the present technology. Diagram400D, however, demonstrates that the present technology facilitates overcoming challenges associated with such an extreme condition. For example, the corresponding conductive pad225-2has a suitable recess depth to accommodate the protruded conductive pad225-1—e.g., in view of the widened tolerable limits for the conductive pad coplanarity. Further, the conductive buffer layer210dcan provide a squeezable cushion during the CTE-based expansion of the conductive pads225-1/2. Accordingly, the interconnect440dis expected to have similar characteristics as other interconnects (e.g., interconnects440a-c) in spite of the protruded conductive pad225-1. Diagram400E depicts the interconnect440egenerally similar to the interconnect440d. Further, similar to the conductive buffer layer210c, the conductive buffer layer210eof the interconnect440emay be discontinuous at certain regions. In other words, at least a portion of the surface of the conductive pad225-1is conjoined to at least another portion of the surface of the conductive pad225-2—e.g., at least partial metal-to-metal bonding occurred between the conductive pads225-1and225-2. FIG.5is a block diagram schematically illustrating a system500including a semiconductor die assembly in accordance with embodiments of the present technology. The system500can include a semiconductor device assembly570, a power source572, a driver574, a processor576, and/or other subsystems or components578. The semiconductor device assembly570can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is the system500shown schematically inFIG.5. The semiconductor die assembly370described with reference toFIG.5may be included in the semiconductor device assembly570of the system500. The semiconductor device assembly570can have features generally similar to the semiconductor die assembly370described above with reference toFIGS.3A-C. For example, the semiconductor device assembly570includes two or more semiconductor dies (e.g., the semiconductor dies201a,301a, and301b) that are directly bonded to each other. Further, the semiconductor device assembly570includes interconnects formed between the semiconductor dies. Each of the interconnects may include a conductive buffer material in addition to the first and second conductive pads (e.g., between the first and second conductive pads) from the top and bottom semiconductor dies, respectively. In some embodiments, the semiconductor device assembly570includes a first semiconductor die including a first semiconductor substrate, a first dielectric layer over the first semiconductor substrate, and a first copper pad in the first dielectric layer, the first copper pad having a first surface opposite to the first semiconductor substrate. Further, the semiconductor device assembly570includes a second semiconductor substrate, a second dielectric layer over the second semiconductor substrate, and a second copper pad in the second dielectric layer, the second copper pad having a second surface opposite to the second semiconductor substrate. Moreover, the first dielectric layer is in direct contact with the second dielectric layer at a bonding interface between the first and second semiconductor dies, and the first and second copper pads form an interconnect between the first and second semiconductor dies, the interconnect having a conductive buffer material between the first and second copper pads. In some embodiments, the conductive buffer layer includes aggregates of conductive particles. In some embodiments, the conductive buffer layer is less dense than the first and second copper pads. In some embodiments, the conductive buffer material is porous and includes copper particles. In some embodiments, at least a first portion of the first surface is conjoined to at least a second portion of the second surface. In some embodiments, the first surface is separate from the second surface, and where the first copper pad is electrically connected to the second copper pad through the conductive buffer material. In some embodiments, either the first surface or the second surface extends past the bonding interface. The resulting system500can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems500can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system500may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system500can also include remote devices and any of a wide variety of computer readable media. FIG.6is a flowchart600of a method of forming semiconductor die assemblies in accordance with embodiments of the present technology. The flowchart600may include aspects of methods as described with reference toFIGS.1through4. The method comprises providing a first semiconductor die including a first dielectric layer, where the first dielectric layer includes a first bond pad having a first top surface recessed with respect to a first surface of the first dielectric layer, and where a conductive buffer layer is disposed on the bond pad, the conductive buffer layer being malleable to deform in response to pressure applied to the conductive buffer layer (box610). The method further comprises providing a second semiconductor die including a second dielectric layer having a second surface, where the second dielectric layer includes a second bond pad having a second top surface (box615). The method further comprises attaching the first and second semiconductor dies such that the first surface is in contact with the second surface to form a bonding interface and the first bond pad is aligned to and facing the second bond pad (box620). The method further comprises heating the first and second semiconductor dies attached to each other (box625). In some embodiments, a sacrificial layer is disposed between the first top surface of the first bond pad and the conductive buffer layer, and the conductive buffer layer adheres to the sacrificial layer. In some embodiments, heating the first and second semiconductor dies attached to each other includes decomposing the sacrificial layer at a temperature greater than 100° C. In some embodiments, the second top surface of the second bond pad is recessed with respect to the second surface of the second dielectric layer, and both the first and second top surfaces of the first and second bond pads expand toward the bonding interface in response to heating the first and second semiconductor dies. In some embodiments, at least a first portion of the first top surface is conjoined to at least a second portion of the second top surface as a result of the first and second bond pads expanding toward the bonding interface. In some embodiments, the first top surface is separate from the second top surface after heating the first and second semiconductor dies, and the first bond pad is electrically connected to the second bond pad through the conductive buffer layer. In some embodiments, the second top surface of the second bond pad is protruded with respect to the second surface of the second dielectric layer, and both the first and second top surfaces of the first and second bond pads expand toward each other in response to heating the first and second semiconductor dies. In some embodiments, at least a first portion of the first top surface is conjoined to at least a second portion of the second top surface as a result of the first and second bond pads expanding toward each other. In some embodiments, the first top surface is separate from the second top surface, and the first bond pad is electrically connected to the second bond pad through the conductive buffer layer. It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined. From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, while in the illustrated embodiments certain features or components have been shown as having certain arrangements or configurations, other arrangements and configurations are possible. Moreover, certain aspects of the present technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. The devices discussed herein, including a semiconductor device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means. As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.” The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology. | 44,193 |
11862592 | DETAILED DESCRIPTION The present disclosure will now be described with reference to the drawings wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. It will be appreciated that this detailed description and the corresponding figures do not limit the scope of the present disclosure in any way, and that the detailed description and figures merely provide a few examples to illustrate some ways in which the inventive concepts can manifest themselves. The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some integrated chips (ICs) comprise a plurality of semiconductor device (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) disposed on/within a semiconductor substrate. A metallization structure is disposed over the semiconductor substrate. The metallization structure comprise an interconnect structure (e.g., a copper interconnect) that electrically couples the plurality of semiconductor devices together. Typically, a passivation layer is disposed over the metallization structure. Bond pads are disposed over the metallization layer and extend through the passivation layer to provide a conductive interface between the interconnect structure and input/output (I/O) structures (e.g., wire bonds, solder bumps, etc.). One challenge with the above ICs is bond pad necking (and/or redistribution layer (RDL) necking). Bond pad necking (and/or RDL necking) is a reduction in a thickness of the bond pad (and/or RDL) along sidewalls of the passivation layer. For example, a first portion of the bond pad is disposed along sidewalls of the passivation layer and extends through the passivation layer to a second portion of the bond pad that is disposed on a portion of the interconnect structure disposed between the sidewalls of the passivation layer. The first portion of the bond pad may have bond pad necking due to the first portion of the bond pad having a large thickness variation (e.g., the thickness of the first portion of the bond pad being greater near a top of the sidewalls of the passivation layer than near a bottom of the sidewalls of the passivation layer). Because of bond pad necking, subsequent processing of the bond pads (e.g., a cleaning process to strip away a masking layer) may attack the interconnect structure, thereby resulting in damage to the interconnect structure. Accordingly, bond pad necking may negatively affect the performance of the ICs (e.g., increased power consumption, decreased lifecycle, etc.). In various embodiments, the present application is directed toward an integrated chip (IC). The IC includes a metallization structure disposed over a semiconductor substrate. The metallization structure comprises an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed on the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer having rounded sidewalls is disposed along the opposite inner sidewalls of the passivation layer. A conductive structure (e.g., a bond pad or redistribution layer (RDL)) is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure. Because the sidewall spacer has rounded sidewalls and is disposed along the sidewalls of the passivation layer, thickness variations in a portion of the conductive structure that extends along the rounded sidewalls may be reduced. Thus, the sidewall spacer may reduce bond pad necking (and/or RDL necking). Accordingly, the sidewall spacer may prevent damage to the interconnect structure caused by bond pad necking (and/or RDL necking), thereby improving the performance of the IC (e.g., decreased power consumption, increased lifecycle, etc.). FIGS.1A-1Billustrate various views of some embodiments of an integrated circuit (IC)100having a sidewall spacer122that reduces bond pad necking.FIG.1Aillustrates a cross-sectional view of some embodiments of the IC100ofFIG.1B.FIG.1Billustrates a top view of some embodiments of the IC100ofFIG.1Awith the material of the bond pad124(see, infra) removed, such that a perimeter124pof the bond pad124is illustrated by a dotted line. As shown inFIGS.1A-1B, the IC100comprises a semiconductor substrate102. In some embodiments, the semiconductor substrate102comprises any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). A semiconductor device104is disposed on/within the semiconductor substrate102. In some embodiments, the semiconductor device104may be a transistor (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)). In such embodiments, the semiconductor device104comprises a pair of source/drain regions106disposed in the semiconductor substrate102. In further such embodiments, a gate dielectric108is disposed on the semiconductor substrate102between the source/drain regions106. In further such embodiments, a gate electrode110is disposed on the gate dielectric108. In yet further embodiments, the semiconductor device104may be a high-voltage MOSFET. A metallization structure112is disposed over the semiconductor substrate102and the semiconductor device104. In some embodiments, the metallization structure112comprises an interconnect structure118disposed in an interlayer dielectric (ILD) structure116having one or more ILD layers. The interconnect structure118comprises a plurality of conductive elements (e.g., metal lines, metal vias, metal contacts, etc.) configured to electrically couple the semiconductor device104to other semiconductor devices (not shown) of the IC100. In further embodiments, an uppermost conductive element119(e.g., an uppermost metal line) of the interconnect structure118has an upper surface that is substantially co-planar with an upper surface of the ILD structure116. In yet further embodiments, the upper surface of the uppermost conductive element119may correspond to an upper surface of the interconnect structure118. In some embodiments, the interconnect structure118may comprise, for example, copper, tungsten, aluminum, some other conductive material, or a combination of the foregoing. In further embodiments, the ILD structure116may comprise one or more of, for example, a low-k dielectric layer (e.g., a dielectric with a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, an oxide (e.g., silicon dioxide (SiO2)), some other dielectric material, or a combination of the foregoing. A passivation layer120is disposed over the metallization structure112. In some embodiments, the passivation layer120is disposed on the ILD structure116and the uppermost conductive element119. In further embodiments, the passivation layer120comprises first inner sidewalls120sthat extend from the upper surface of the passivation layer120to the metallization structure112. In yet further embodiments, at least a portion of the upper surface of the uppermost conductive element119is disposed between the first inner sidewalls120s. In some embodiments, the first inner sidewalls120smay be substantially vertical. In further embodiments, the passivation layer120may have a substantially planar upper surface. In yet further embodiments, the passivation layer120may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxy-nitride (SiOXNY)), some other dielectric material, or a combination of the foregoing. It will be appreciated that, in some embodiments, the passivation layer120may comprise one or more dielectric layers. A sidewall spacer122is disposed over the metallization structure112and along the first inner sidewalls120s. In some embodiments, the sidewall spacer122is disposed on the upper surface of the uppermost conductive element119. In other embodiments, the sidewall spacer122may be disposed on the upper surface of the ILD structure116. In further embodiments, the sidewall spacer122has rounded sidewalls122s. In yet further embodiments, opposite rounded sidewalls122sof the sidewall spacer122face one another. In further embodiments, the sidewall spacer122may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), some other dielectric material, or a combination of the forgoing. In yet further embodiments, the sidewall spacer122may comprise a different material than the passivation layer120. In other embodiments, the sidewall spacer122may comprise a same material as the passivation layer120. A bond pad124is disposed over the metallization structure112, the sidewall spacer122, and the passivation layer120. In some embodiments, the bond pad124is disposed on the uppermost conductive element119, the rounded sidewalls122sof the sidewall spacer122, and the upper surface of the passivation layer120. In further embodiments, the bond pad124is electrically coupled to the interconnect structure118, and thus electrically coupled to the semiconductor device104. In yet further embodiments, the bond pad124conformally lines the passivation layer120, the sidewall spacer122, and the interconnect structure118. In some embodiments, the bond pad124may comprise, for example, aluminum, copper, aluminum-copper, some other conductive material, or a combination of the forgoing. In further embodiments, the bond pad124comprises a different conductive material than the interconnect structure118. For example, the bond pad124may comprise aluminum, and the interconnect structure118may comprise copper. In yet further embodiments, the bond pad124may comprise a conductive material that the interconnect structure118does not comprise. Because the sidewall spacer122is disposed along the first inner sidewalls120sand because the sidewall spacer122has rounded sidewalls122s, thickness variations in a portion of the bond pad124that extends along the rounded sidewalls122sof the sidewall spacer122may be reduced. Thus, the sidewall spacer122may reduce bond pack necking. Accordingly, the sidewall spacer122may prevent damage to the interconnect structure118caused by bond pad necking, thereby improving the performance of the IC100(e.g., decreased power consumption, increased lifecycle, etc.). FIGS.2A-2Billustrate various views of some embodiments of an integrated circuit (IC)100having a sidewall spacer122that reduces redistribution layer (RDL) necking.FIG.2Aillustrates a cross-sectional view of some embodiments of the IC100ofFIG.2B.FIG.2Billustrates a top view of some embodiments of the IC100ofFIG.2Awith the material of the RDL202(see, infra) and the material of the capping layer204(see, infra) removed, such that a perimeter202pof the RDL202is illustrated by a first dotted line and a perimeter204pof the capping layer204is illustrated by a second dotted line. As shown inFIGS.2A-2B, a redistribution layer (RDL)202is disposed over the metallization structure112, the sidewall spacer122, and the passivation layer120. In some embodiments, the RDL202is disposed on the uppermost conductive element119, the rounded sidewalls122sof the sidewall spacer122, and the upper surface of the passivation layer120. In yet further embodiments, the RDL202conformally lines the passivation layer120, the sidewall spacer122, and the interconnect structure118. In some embodiments, the RDL202is electrically coupled to the interconnect structure118, and thus electrically coupled to the semiconductor device104. The RDL202is configured to provide an electrical connection between the uppermost conductive element119and an input/output (I/O) structure206that is disposed at a location spaced from the uppermost conductive element119. For example, the RDL202may extend from the uppermost conductive element119across the upper surface of the passivation layer120in a lateral direction to a location that is spaced from the uppermost conductive element119. Accordingly, the I/O structure206may be disposed at the location and electrically coupled to the semiconductor device104via the RDL202. In some embodiments, the I/O structure206is disposed on the RDL202. In other embodiments, the I/O structure206is disposed on an under-bump metallization structure (not shown) that is disposed on the RDL202. In further embodiments, the I/O structure206is configured to electrically couple the RDL202to external circuitry (e.g., a printed circuit board, an external microprocessor, etc.). In further embodiments, the I/O structure206may be, for example, a bump/ball structure, a wire bonding structure, or the like. In yet further embodiments, the I/O structure206may comprise, for example, gold (Au), solder, some other conductive material, or a combination of the foregoing. In some embodiments, the RDL202may comprise, for example, aluminum, copper, aluminum-copper, some other conductive material, or a combination of the forgoing. In further embodiments, the RDL202comprises a different conductive material than the interconnect structure118. For example, the RDL202may comprise aluminum, and the interconnect structure118may comprise copper. In further embodiments, the RDL202may comprise a conductive material that the interconnect structure118does not comprise. In yet further embodiments, the RDL202and/or the bond pad124(see, e.g.,FIGS.1A-1B) may be referred to as a conductive structure. Because the sidewall spacer122is disposed along the first inner sidewalls120sand because the sidewall spacer122has rounded sidewalls122s, thickness variations in a portion of the RDL202that extends along the rounded sidewalls122sof the sidewall spacer122may be reduced. Thus, the sidewall spacer122may reduce RDL necking. Accordingly, the sidewall spacer122may prevent damage to the interconnect structure118caused by RDL necking, thereby improving the performance of the IC100(e.g., decreased power consumption, increased lifecycle, etc.). In some embodiments, a capping layer204is disposed over the passivation layer120and the RDL202. In such embodiments, the I/O structure206extends through the capping layer204at the location to contact the RDL202, such that the I/O structure206is electrically coupled to the RDL202. In further embodiments, the capping layer204may have a substantially planar upper surface. In yet further embodiments, the capping layer204may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), some other dielectric material, or a combination of the foregoing. FIGS.3A-3Billustrate various cross-sectional views of some embodiments of the IC100ofFIGS.1A-1B.FIG.3Aillustrates a cross-sectional view of some more detailed embodiments of the IC100ofFIGS.1A-1B.FIG.3Billustrates a magnified cross-sectional view of some embodiments of a region302ofFIG.3A. It will be appreciated that, in some embodiments, the IC100ofFIGS.2A-2Bmay comprise substantially similar features as illustrated inFIGS.3A-3B. For example, in some embodiments, “bond pad124” may be substituted with “RDL202” in the following paragraphs describingFIGS.3A-3B. As shown inFIGS.3A-3B, an etch stop layer304is disposed between the passivation layer120and the metallization structure112. In some embodiments, the etch stop layer304is disposed on the ILD structure116and the uppermost conductive element119. In further embodiments, the passivation layer120and the sidewall spacer122are disposed on the etch stop layer304. In such embodiments, the first inner sidewalls120smay extend from an upper surface of the etch stop layer304to the upper surface of the passivation layer120. In further such embodiments, the rounded sidewalls122sof the sidewall spacer122may extend from the etch stop layer304to the passivation layer120. In some embodiments, the etch stop layer304comprises second inner sidewalls304sthat extend from the uppermost conductive element119to the sidewall spacer122. In further embodiments, at least a portion of the upper surface of the uppermost conductive element119is disposed between the second inner sidewalls304s. In further embodiments, opposite first inner sidewalls120sare spaced further apart than opposite second inner sidewalls304s. In further embodiments, the second inner sidewalls304sare rounded. In other embodiments, the second inner sidewalls304smay be substantially vertical. In further embodiments, one or more of the second inner sidewalls304smay extend from the ILD structure116to the sidewall spacer122. In such embodiments, at least a portion of the upper surface of the ILD structure116is disposed between the second inner sidewalls304s. In some embodiments, the etch stop layer304comprises, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), some other dielectric material, or a combination of the forgoing. In further embodiments, the etch stop layer304comprises a different material than the sidewall spacer122. In further embodiments, the etch stop layer304comprises a different material than both the passivation layer120and the sidewall spacer122. In yet further embodiments, a height of the etch stop layer304(e.g., between an uppermost surface and a lowermost surface of the etch stop layer304) may be between about 100 nanometers (nm) and about 200 nm. In some embodiments, the uppermost conductive element119comprises third inner sidewalls119sthat extend from an upper surface119uof the uppermost conductive element119to the etch stop layer304. In such embodiments, the upper surface119uof the uppermost conductive element119is disposed between an uppermost surface of the uppermost conductive element119and a lower surface of the uppermost conductive element119. In further embodiments, the opposite second inner sidewalls304sare spaced further apart than opposite third inner sidewalls119s. In yet further embodiments, the third inner sidewalls119sare rounded. In other embodiments, the third inner sidewalls119smay be substantially vertical. In some embodiments, the third inner sidewalls119s, the second inner sidewalls304s, and the rounded sidewalls122sof the sidewall spacer122define common inner sidewalls, respectively, that extend from the uppermost conductive element119to the upper surface of the passivation layer120. In further embodiments, the common sidewalls may have a radius of curvature that is greater than a radius of curvature of the first inner sidewalls120s. In yet further embodiments, the bond pad124continuously extends from the upper surface of passivation layer120to the upper surface119uof the uppermost conductive element119by extending along the common sidewalls. In such embodiments, a portion of the bond pad124disposed over the passivation layer120may have a substantially planar upper surface, a portion of the bond pad124disposed along the common sidewalls may have rounded sidewalls, and a portion of the bond pad124disposed over the upper surface119uof the uppermost conductive element119may have a substantially planar upper surface. In some embodiments, the sidewall spacer122may have a first thickness T1that is at least about 40 percent of a height H of the passivation layer120. In further embodiments, a height of the sidewall spacer122may be substantially the same as the height H of the passivation layer120. In further embodiments, a ratio between the height H of the passivation layer120and the first thickness T1may be, for example, 7 to 3, 6 to 4, or 1 to 1. In further embodiments, the height H of the passivation layer120may be between about 200 nm and about 600 nm. In further embodiments, the first thickness T1may be between about 80 nm and about 600 nm. In yet further embodiments, the rounded sidewalls122sof the sidewall spacer122may have a radius of curvature that is greater than a radius of curvature of the first inner sidewalls120s. In some embodiments, a distance D between the opposite first inner sidewalls120smay be less than or equal to about 3 micrometers (um). In further embodiments, the bond pad124may have a second thickness T2and a third thickness T3. In some embodiments, the second thickness T2may be between about 100 nm and about 10,000 nm. In further embodiments, the second thickness T2may be less than or equal to about 300 nm. In further embodiments, the third thickness T3may be between about 100 nm and about 10,000 nm. In further embodiments, the third thickness T3may be less than or equal to about 300 nm. In further embodiments, a difference between the second thickness T2and the third thickness T3may be plus/minus 20 percent. In further embodiments, the second thickness T2may be greater than the third thickness T3. In some embodiments, the I/O structure206is disposed on the bond pad124. In such embodiments, the I/O structure206may be disposed directly above the bond pad124. In further such embodiments, the I/O structure206may be disposed directly above the uppermost conductive element119. In further embodiments, the I/O structure206is configured to electrically couple the bond pad124to the external circuitry (e.g., a printed circuit board, an external microprocessor, etc.). FIGS.4-12illustrate a series of cross-sectional views of some embodiments for forming the IC100ofFIGS.3A-3B. As shown inFIG.4, an etch stop layer304is formed over a metallization structure112. In some embodiments, the metallization structure112comprises an interconnect structure118disposed in an interlayer dielectric (ILD) structure116. In further embodiments, an uppermost conductive element119(e.g., an uppermost metal line) of the interconnect structure118has an upper surface that is substantially co-planar with an upper surface of the ILD structure116. In some embodiments, a process for forming the etch stop layer304comprises depositing the etch stop layer304on the ILD structure116and the uppermost conductive element119. In further embodiments, the etch stop layer304may be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, some other deposition process, or a combination of the foregoing. Also shown inFIG.4, a first dielectric layer402is formed over the etch stop layer304. In some embodiments, the first dielectric layer402may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), some other dielectric material, or a combination of the foregoing. In further embodiments, the first dielectric layer402comprises a different dielectric material than the etch stop layer304. In some embodiments, a process for forming the first dielectric layer402comprises depositing the first dielectric layer402on the etch stop layer304. In further embodiments, the first dielectric layer402may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. As shown inFIG.5, a passivation layer120is formed over the etch stop layer304. In some embodiments, a process for forming the passivation layer120comprises forming a first opening502in the first dielectric layer402(see, e.g.,FIG.4). In further embodiments, the first opening502is defined by first inner sidewalls120sof the passivation layer120and an upper surface of the etch stop layer304. In yet further embodiments, opposite sides of the first opening502are spaced apart by less than or equal to about 3 um. In some embodiments, a process for forming the passivation layer120comprises depositing a masking layer (not shown) (e.g., a positive/negative photoresist) on the first dielectric layer402. Thereafter, with the masking layer in place, a first etch504(e.g., a wet/dry etch) is performed into the first dielectric layer402. In some embodiments, the first etch504is a dry etch (e.g., reactive-ion etching (RIE)). The first etch504forms the first opening502in the first dielectric layer402by removing unmasked portions of the first dielectric layer402, thereby forming the passivation layer120. Subsequently, in some embodiments, the masking layer is stripped away. As shown inFIG.6, a second dielectric layer602is formed over the passivation layer120and the etch stop layer304. In some embodiments, the second dielectric layer602is formed as a conformal layer lining the first opening502and an upper surface of the passivation layer120. In further embodiments, the second dielectric layer602may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), some other dielectric material, or a combination of the foregoing. In further embodiments, the second dielectric layer602may comprise a different dielectric material than the etch stop layer304and/or the passivation layer120. In other embodiments, the second dielectric layer602may comprise a same dielectric material as the passivation layer120. In some embodiments, a process for forming the second dielectric layer602comprises depositing the second dielectric layer602on the upper surface of the passivation layer120, the first inner sidewalls120s, and the upper surface of the etch stop layer304. In further embodiments, the second dielectric layer602may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. As shown inFIG.7, a sidewall spacer122is formed on the etch stop layer304and along the first inner sidewalls120s. In some embodiments, the sidewall spacer122is formed with rounded sidewalls122s. In further embodiments, a process for forming the sidewall spacer122comprises performing a second etch702(e.g., a wet/dry etch) into the second dielectric layer602(see, e.g.,FIG.6). In some embodiments, the second etch702is a dry etch (e.g., RIE). In further embodiments, the second etch702removes horizontal segments of the second dielectric layer602without removing vertical segments of second dielectric layer602, thereby forming the sidewall spacer122. As shown inFIG.8, a second opening804is formed over the uppermost conductive element119. In some embodiments, the second opening804is defined by the rounded sidewalls122sof the sidewall spacer122, second inner sidewalls304sof the etch stop layer304, third inner sidewalls119sof the uppermost conductive element119, and an upper surface119uof the uppermost conductive element119. In some embodiments, a process for forming the second opening804comprises depositing a second masking layer (not shown) (e.g., a positive/negative photoresist) on the passivation layer120and the sidewall spacer122. Thereafter, with the masking layer in place, a third etch802(e.g., a wet/dry etch) is performed into the etch stop layer304. In some embodiments, the third etch802is a dry etch (e.g., RIE). The third etch802removes unmasked portions of the etch stop layer304, thereby forming the second opening804. Subsequently, in some embodiments, the masking layer is stripped away. In other embodiments, the third etch802may be performed without forming the masking layer. In such other embodiments, the third etch802may selectively remove exposed portions of the etch stop layer304at a higher rate than exposed portions of the sidewall spacer122and/or passivation layer120. As shown inFIG.9, a conductive layer902is formed over the uppermost conductive element119, the etch stop layer304, the sidewall spacer122, and the passivation layer120. In some embodiments, the conductive layer902is formed as a conformal layer lining the second opening804and the upper surface of the passivation layer120. In further embodiments, the conductive layer902may be formed with a thickness (e.g., a distance between an upper surface and a bottom surface of the conductive layer902) that is less than or equal to about 300 nm. In further embodiments, the conductive layer902may comprise, for example, aluminum, copper, aluminum-copper, some other conductive material, or a combination of the forgoing. In further embodiments, the conductive layer902comprises a different conductive material than the interconnect structure118. In yet further embodiments, the conductive layer902may comprise a conductive material that the interconnect structure118does not comprise. In some embodiments, a process for forming the conductive layer902comprises depositing the conductive layer902on the upper surface119uof the uppermost conductive element119, the third inner sidewalls119s, the second inner sidewalls304s, the rounded sidewalls122sof the sidewall spacer122, and the upper surface of the passivation layer120. In further embodiments, the conductive layer902may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. As shown inFIG.10, a bond pad124is formed over the uppermost conductive element119, the etch stop layer304, the sidewall spacer122, and the passivation layer120. In some embodiments, a process for forming the bond pad124comprises forming a masking layer1002on the conductive layer902(see, e.g.,FIG.9). In some embodiments, a process for forming the masking layer1002comprises depositing (e.g., via a spin-on process) a photoresist layer (not shown) on the conductive layer902. Thereafter, the photoresist layer is selectively exposed to radiation. Subsequently, the photoresist layer is exposed to a developing agent to remove portions of the photoresist layer that were exposed (or not exposed) to the radiation, thereby forming the masking layer1002. In some embodiments, with the masking layer1002in place, a fourth etch1004(e.g., wet/dry etch) is performed into the conductive layer902. In some embodiments, the fourth etch1004is a dry etch (e.g., reactive-ion etching (RIE)). The fourth etch1004removes unmasked portions of the conductive layer902, thereby forming the bond pad124. As shown inFIG.11, the masking layer1002(see, e.g.,FIG.10) is removed from the bond pad124. In some embodiments, a process for removing the masking layer1002comprises exposing the masking layer1002to a stripping agent1102. In further embodiments, the stripping agent1102is a solvent-based stripping agent. In further embodiments, the masking layer1002is exposed to the stripping agent1102by submersing the semiconductor substrate102(and thus the masking layer1002) in the stripping agent1102. In yet further embodiments, after the masking layer1002is removed from the bond pad124, formation of the bond pad is complete. In some embodiments, the stripping agent1102comprises an organic compound (e.g., catechol (C6H6O2)). In further embodiments, the stripping agent1102may comprise an amine. In further embodiments, the stripping agent1102removes the conductive material of the interconnect structure118at a faster rate than the conductive material of the bond pad124. For example, the stripping agent1102may remove the conductive material of the interconnect structure at a rate greater than or equal to ten times a rate the striping agent removes the conductive material of the bond pad124. Because the sidewall spacer122is disposed along the first inner sidewalls120sand because the sidewall spacer122has rounded sidewalls122s, thickness variations in a portion of the bond pad124that extends along the rounded sidewalls122sof the sidewall spacer122may be reduced. Thus, the sidewall spacer122may reduce bond pack necking. Accordingly, the bond pad124may prevent the interconnect structure118from being exposed to the stripping agent1102, thereby preventing the stripping agent1102from damaging the interconnect structure118(e.g., undesirably removing portions of the interconnect structure118). As shown inFIG.12, an input/output (I/O) structure206is formed over the bond pad124. In some embodiments, forming the I/O structure206over the bond pad124electrically couples the I/O structure206to the interconnect structure118via the bond pad124. In some embodiments, a process for forming the I/O structure206comprises depositing a conductive structure (not shown) on the bond pad124. In further embodiments, the conductive structure may comprise, for example, gold (Au), solder, some other conductive material, or a combination of the foregoing. In further embodiments, the conductive structure may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a reflow process (e.g., reflow soldering) may be performed on the conductive structure, thereby forming the I/O structure206. It will be appreciated that, in some embodiments, other process(es) (e.g., wire bonding) may be utilized to form the I/O structure206. In yet further embodiments, after the I/O structure206is formed, formation of the IC100is complete. As illustrated inFIG.13, a flowchart1300of some embodiments of a method for forming an integrated circuit (IC) having a sidewall spacer that reduces bond pad necking is provided. It will be appreciated that, in some embodiments, the method provided in flowchart1300may be a substantially similar to a method for forming an integrated circuit (IC) having a sidewall spacer that reduces redistribution layer (RDL) necking. While the flowchart1300ofFIG.13is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At1302, a first opening is formed over a metallization structure, where the metallization structure comprises an interconnect structure disposed in an interlayer dielectric (ILD) structure. The first opening is defined by inner sidewalls of a passivation layer and an upper surface of an etch stop layer.FIGS.4-5illustrate a series of cross-sectional views of some embodiments corresponding to act1302. At1304, a sidewall spacer is formed on the etch stop layer and along the inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls.FIGS.6-7illustrate a series of cross-sectional views of some embodiments corresponding to act1304. At1306, a second opening is formed over the metallization structure, where the second opening is defined by the rounded sidewalls of the sidewall spacer, inner sidewalls of the etch stop layer, and an upper surface of the interconnect structure.FIG.8illustrates a cross-sectional view of some embodiments corresponding to act1306. At1308, a bond pad is formed over the metallization structure and electrically coupled to the interconnect structure, where the bond pad is formed on the upper surface of the interconnect structure, the inner sidewalls of the etch stop layer, the rounded sidewalls of the sidewall spacer, and an upper surface of the passivation layer.FIGS.9-11illustrate a series of cross-sectional views of some embodiments corresponding to act1308. At1310, an input/output (I/O) structure is formed over the bond pad, where the I/O structure is electrically coupled to the interconnect structure via the bond pad.FIG.12illustrates a cross-sectional view of some embodiments corresponding to act1310. In some embodiments, the present application provides an integrated chip (IC). The IC comprises a semiconductor substrate. A metallization structure is disposed over the semiconductor substrate, where the metallization structure comprises an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure, where the conductive structure is a bond pad and/or a redistribution layer (RDL). In other embodiments, the present application provides an integrated chip (IC). The IC comprises a semiconductor substrate. A metallization structure is disposed over the semiconductor substrate, where the metallization structure comprises an interconnect structure disposed in an interlayer dielectric (ILD) structure. An etch stop layer is disposed on the metallization structure, where the interconnect structure comprises an uppermost conductive element that is at least partially disposed between opposite inner sidewalls of the etch stop layer. A passivation layer is disposed on the etch stop layer, where the passivation layer comprises opposite inner sidewalls that extend from an upper surface of the etch stop layer to an upper surface of the passivation layer. A sidewall spacer is disposed on the etch stop layer and along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls that face one another. A conductive structure is disposed on the uppermost conductive element, the opposite inner sidewalls of the etch stop layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the passivation layer. In yet other embodiments, the present application provides a method for forming an integrated chip (IC). The method comprises forming a metallization structure over a semiconductor substrate and a semiconductor device on the semiconductor substrate, where the metallization structure comprises an interconnect structure disposed in an interlayer dielectric (ILD) structure. An etch stop layer is formed over the metallization structure. A dielectric layer is formed on the etch stop layer. A part of the dielectric layer is removed to form a passivation layer, where opposite inner sidewalls of the passivation layer define a first opening. A sidewall spacer is formed on the etch stop layer and along the opposite inner sidewalls of the passivation layer, where the sidewall spacer is formed with rounded sidewalls. A part of the etch stop layer is removed to form a second opening that exposes the interconnect structure. A bond pad or redistribution layer is formed contacting the rounded sidewalls, an upper surface of the passivation layer, and the interconnect structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 40,975 |
11862593 | DETAILED DESCRIPTION In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “on,” “over” and the like, may be used herein for ease of description to describe one element or feature in relation to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the described structures in use or operation in addition to the orientation depicted in the figures. The structures may be otherwise oriented, such as through a 90-degree rotation or at other orientations, and the spatially relative descriptors used herein may likewise be interpreted accordingly depending on the particular orientation. FIG.1is a cross-sectional view of an interconnect structure100including an under bump metallization (UBM) stack102with an indium (In) superconducting solder bump104formed on the UBM stack for utilization in cryogenic electronic circuits according to one embodiment of the present disclosure. The UBM stack102includes an adhesion and barrier layer106and a thick conductive stud or pillar108formed on the adhesion and barrier layer, with the superconducting solder bump104formed on the thick conductive pillar. The thick conductive pillar108has a vertical thickness T as shown inFIG.1that is sufficient to prevent the material of the thick conductive pillar from being fully consumed or converted into intermetallic regions (not shown inFIG.1) through interdiffusion of the materials of the thick conductive pillar and the superconducting solder bump104that may occur at room temperature, as will be described in more detail below. Once the interconnect structure100is at deep cryogenic temperatures, such as when a cryogenic electronic chip (not shown) including the interconnect structure is operating in a cryogenic electronic system, the rate of the interdiffusion between the thick conductive pillar108and the superconducting solder bump104slows significantly and the formation of intermetallic regions due to such interdiffusion is no longer of concern. In the embodiment ofFIG.1, the UBM stack102extends through a passivation layer110of a die or chip (not shown) on which the interconnect structure100is formed. More specifically, the adhesion and barrier layer106extends through an aperture in the passivation layer110to contact a bond pad112of the die or chip on which the interconnect structure100is formed. The bond pad112is electrically coupled to components (not shown) in the associated die or chip and is typically formed from a suitable metal, such as aluminum (Al), copper (Cu) or gold (Au). In the example embodiment ofFIG.1, an interlayer dielectric layer114surrounds the bond pad112, with the passivation layer110formed on the interlayer dielectric layer and on portions of the bond pad. In the UBM stack102, the adhesion and barrier layer106functions to adhere the UBM stack to the bond pad112and to provide a diffusion barrier between the materials of the bond pad and the thick conductive pillar108and superconducting solder bump104. The thick conductive pillar108of the UBM stack102functions as a solder wetting layer to thereby bond the UBM stack through the superconducting solder bump104to a circuit board or other structure (not shown) on which the superconducting solder bump is placed during a soldering or wetting process, as will be understood by those skilled in the art. During the solder wetting or reflow process, the material of the superconducting solder bump104becomes molten to form a connection with the thick conductive pillar108of the UBM stack102and to form a connection to the circuit board or other structure on which the superconducting solder bump is placed. In this way the superconducting solder bump104forms a solder joint between the UBM stack102and the circuit board or other structure on which the superconducting solder bump is placed. The superconducting solder bump104may reflowed and bonded at 175° C. after a hydrochloric acid (HCl) dip and flux application, or a reducing plasma treatment to remove residual indium oxides on the solder bump. The term “bump” as used in this description to refer to the superconducting solder bump104refers to a piece or volume of material that is to be used as solder to interconnect components of a cryogenic electronic circuit, with the material being a superconducting material, such as indium (In), at cryogenic temperatures. In one embodiment of the interconnect structure100, the interconnect structure is a flip chip interconnection structure in which the superconducting solder bump104is indium (In), the thick conductive pillar108is copper (Cu), and the adhesion and barrier layer106is a layered structure including a layer of titanium tungsten or tungsten titanium (TiW) and a thin seed layer of copper (Cu). For example, in one embodiment the layered adhesion and barrier layer106includes a TiW layer having a thickness of 100-150 nm and a thin Cu seed layer having a thickness of 100-200 nm. In embodiments of the interconnect structure100, the vertical thickness T of the thick Cu pillar108is at least 5 μm. The adhesion and barrier layer106may alternatively be formed from only a layer of titanium (Ti) in some embodiments. Also note that inFIG.1, andFIGS.2-4described below, that the thicknesses of the various layers are not to scale to simplify the figures. InFIGS.1-3, for example, the thickness T of the conductive pillar108(e.g., 5 μm) is much larger than illustrated relative to the thickness of the passivation layer110(e.g., few hundred nm). As mentioned above, copper Cu has higher rate of diffusion and formation of intermetallic regions with indium (In) at room temperature compared to other metals, such as nickel Ni. Nickel, however, is a magnetic material and accordingly may not be utilized in UBM stacks for cryogenic systems containing sensitive superconducting logic devices or any cryogenic components that are sensitive magnetic fields, such as quantum computing components. The higher rate of interdiffusion between the Cu pillar108and the In solder bump104at room temperature, and the resulting formation of intermetallic regions within the pillar, can result in the loss of adhesion between the TiW and Cu adhesion and barrier layer106and the Cu pillar if these intermetallic regions extend the entire vertical thickness T of the pillar. Intermetallic regions forming at the bottom of the thick conductive pillar108adjoining the adhesion and barrier layer106can cause the loss of adhesion between the pillar and the adhesion and barrier layer, resulting in failure of the interconnect structure100. The interconnect structure100prevents such failures by ensuring the thickness T of the Cu pillar108is sufficient to ensure the intermetallic regions that form in the Cu pillar at room temperature do not extend through the entire vertical thickness T of the pillar. At room temperature, the intermetallic regions naturally form first in the top of the conductive pillar108adjoining the solder bump104due to the interdiffusion of the copper (Cu) of the pillar and the indium (In) of the solder bump. As long as these intermetallic regions extend only partially through the thickness T of the pillar108and do not reach bottom of the conductive pillar108adjoining the adhesion and barrier layer106, the adhesion of the pillar to the adhesion and barrier layers is maintained to thereby maintain the structural integrity of the interconnect structure100. In the interconnect structure100, the thickness T of the Cu pillar108has a value that is great enough to prevent these intermetallic regions from extending all the way from the In solder bump104to the adhesion and barrier layer106, namely entirely through the thickness T of the Cu pillar. In this way, the interconnect structure100allows the utilization of copper (Cu) in the UBM stack102while also allowing the utilization of indium (In) to form the superconducting solder bump102. Indium, as mentioned above, is unlike conventional room temperature solder materials like tin (Sn), being advantageously a ductile material at deep cryogenic temperatures while also being a superconductor below 3.4 K, being capable of being compression bonded at room temperature, and having a lower melting point than tin-based solders. The conductive pillar108has the thickness T that is sufficient to prevent intermetallic regions or intermetallic compounds (IMCs) in the conductive pillar that form due to interdiffusion between the conductive pillar and the indium solder bump104, which occurs during heat treatments and storage at room temperature, from extending through the thickness of the conductive pillar. The rate of growth of the intermetallic regions in the conductive pillar108is a function of temperature and a function of time. The rate of growth increases at greater temperatures and the extent to which the intermetallic regions extend within the conductive pillar108increase as a function of time. The thickness T of the conductive pillar is large enough to prevent complete growth of these intermetallic regions in the conductive pillar108, or alternatively to prevent the complete consumption of the material of the conductive pillar through the entire conductive pillar for a specified application. The specific application of the interconnect structure100determines the required thickness T of the conductive pillar108. For example, the interconnect structure100may need to withstand, or maintain mechanical and electrical integrity after being subjected to, multiple heat treatments up to 200° C. (indium reflows at 200° C.) and storage at room temperature for multiple months. The thickness T must be large enough that these multiple heat treatments and storage at room temperature must not result in complete growth of intermetallic regions within the conductive pillar108. Thickness T of the conductive pillar108could be reduced, for example, if the growth of IMCs at room temperature for a relatively short period time needed to be prevented. Embodiments of the interconnect structure100enable a relatively thick Cu conductive pillar108, for example having a thickness of 5 μm, to be stored for long periods at room temperature, and be subjected to heat treatments by being brought up to solder melting temperatures (i.e., up to 200° C. for indium) multiple times, without any failure of the interconnect structure so that the structure reliably remains functional for cryogenic applications. In embodiments, where the heat treatments include multiple temperature excursions up to a maximum of 200° C., the UBM stack102of the interconnect structure100can withstand or maintain mechanical and electrical integrity when subjected to cryogenic shocks from room temperature to 4 K after the heat treatments and storage at room temperature. FIG.2is a cross-sectional view of an electronic chip200including an interconnect structure202including a UBM stack204and a superconducting solder bump206according to an embodiment. The flip chip interconnection structure202would include a plurality of UBM stacks204and associated superconducting solder bumps206but only one UBM stack and solder bump is illustrated inFIG.2to simplify the figure and the associated description. The UBM stack204has the same structure as the UBM stack102ofFIG.1in embodiments of the interconnect structure202and will accordingly not again be described in detail. The UBM stack102includes an adhesion and barrier layer208and a thick conductive pillar210formed on the adhesion and barrier layer, with the superconducting solder bump206formed on the thick conductive pillar. The adhesion and barrier layer208extends through an aperture in a passivation layer212to contact a bond pad214of a semiconductor die216on which the interconnect structure202is formed. The bond pad112is electrically coupled to components (not shown) in the semiconductor die216. An interlayer dielectric layer218is formed on the semiconductor die216surrounding the bond pad214and the passivation layer212is formed on the interlayer dielectric layer and on portions of the bond pad. In one embodiment, the interconnect structure202is a flip chip interconnect structure, the superconducting solder bump206is indium (In), the thick conductive pillar210is copper (Cu), and the adhesion and barrier layer208is a layered structure including a layer of tungsten titanium or titanium tungsten (TiW) and a thin seed layer of copper (Cu). In this embodiment, the thick Cu pillar210has a thickness T that is sufficient to prevent the Cu forming the pillar from being fully consumed or converted into intermetallic regions in a vertical direction as indicated by the thickness T. As discussed above in relation toFIG.1, these intermetallic regions may form through interdiffusion of the copper (Cu) of the pillar210and the indium (In) of the solder bump206at room temperature. FIGS.3A-3Gillustrate a process of fabricating an interconnect structure for cryogenic electronic chips including a UBM stack with a superconducting solder bump according to an embodiment of the present disclosure.FIG.3Ashows a portion of wafer300to which the process is applied to form the UBM stack with a superconducting solder bump. The wafer includes bond pads302of a plurality of dies (not shown) in the wafer, each of the bonding pads being exposed through a corresponding aperture or opening304in a passivation layer306on a surface of wafer. Only one bond pad302and the corresponding opening304are illustrated inFIGS.3A-3Bto simplify the figures and the corresponding description of the process of forming UBM stacks and superconducting solder bumps according to this embodiment of the present disclosure. The passivation layer306is formed on the bond pad302and on an interlayer dielectric layer308that is formed on the surface of the die including the bond pad shown inFIG.3A. Although not expressly shown inFIG.3A, the bond pad302is electrically connected through electrical connections (not shown) in the interlayer dielectric308to electrical components contained in the corresponding die in the wafer, as will be appreciated by those skilled in the art. FIG.3Billustrates a first step of the process in which a seed layer310is conformally formed on the upper surface of the wafer300. This seed layer310corresponds to the adhesion and barrier layer of the UBM stack and superconducting solder bump being formed. The seed layer310may be formed through deposition of a suitable material or materials, such as through sputtering or evaporation, on the upper surface of the passivation layer306and on angled edges of the passivation layer and the bond pad302exposed in the opening304of the passivation layer. In one embodiment, the seed layer310is a layered structure including a plurality of layers that collectively provide the adhesion and barrier functions of the UBM stack. This layered structure of the seed layer310may include a layer of titanium tungsten or tungsten titanium (TiW) and a thin seed layer of copper (Cu) in embodiments. In one embodiment, the layered seed layer310includes a TiW layer having a thickness of 100-150 nm and a thin Cu seed layer having a thickness of 100-200 nm. The seed layer310also functions as a plating base layer for subsequent formation of the thick conductive pillar of the UBM stack and superconducting solder bumps on these thick conductive pillars, as will be described in more detail below. After the formation of the seed layer310, a sacrificial layer312is formed on the upper surface of the structure ofFIG.3Band is patterned to form an opening3in the sacrificial layer14over the bond pad302. The sacrificial layer312is a photoresist layer in one embodiment and may be formed through any suitable technique, such as through spin coating a suitable photoresist material on the structure and is similarly patterned through any suitable technique, such as etching. After the formation and patterning of the sacrificial layer312, a thick conductive pillar316is formed on the exposed portion of the seed layer310in the opening314as shown inFIG.3D. The thick conductive pillar316may be formed through any suitable technique, and in one embodiment is formed through electrodeposition or electroplating of a suitable material on the exposed portion of the seed layer in the opening314. In this way, the seed layer310functions in this electroplating process as a seed layer and is maintained at a first voltage to attract oxidized atoms of the plating material and thereby coat the exposed portion of the seed layer in the opening314to form the thick conductive pillar316. The thick conductive pillar316is corresponds to the solder wetting layer of the UBM stack being formed and is copper (Cu) in embodiments of the process. The thick conductive pillar316has a thickness T which, as described above with reference toFIGS.1and2, is sufficient to prevent the Cu material of the thick conductive pillar from being fully consumed or converted into intermetallic regions along the vertical thickness of the pillar due to interdiffusion of the Cu pillar and an indium solder bump subsequently formed on the pillar. As discussed above, these intermetallic regions can result in the loss of adhesion between Cu pillar316and the seed layer310and thereby the failure of the interconnect structure100. Once the thick conductive pillar316has been formed as shown inFIG.3D, a superconducting solder bump318is formed on the thick conductive pillar316as seen inFIG.3E. The thick conductive pillar316may be formed through any suitable technique, and in one embodiment is advantageously formed through electrodeposition or electroplating of a suitable superconducting material, such as indium (In), on the exposed portion of the thick conductive pillar316. The seed layer310and thick conductive pillar316are maintained at a first voltage to attract oxidized atoms of the plating material, such as indium, to thereby coat the exposed portion of the seed layer in the opening314to form the thick conductive pillar316. Formation of the indium solder bump318through electroplating has several advantages including being much faster and wasting less indium material compared to other methods of formation such as through a PVD process. Upon formation of the superconducting solder bump318as shown inFIG.3E, the process thereafter removes the sacrificial layer312as shown inFIG.3F. The removal of the sacrificial layer312may be done through any suitable technique, such as etching, which removes the sacrificial layer without removing the thick conductive pillar316and solder bump318. When the sacrificial layer312has been removed as seen inFIG.3F, unwanted portions320of the seed layer310still remain on the upper surface of the passivation layer306. These unwanted portions320of the seed layer310are to the left and right of the solder bump318and pillar316inFIG.3Fand are then removed. As seen inFIG.3G, the unwanted portions320of the seed layer310have been removed, such as through etching, to form the desired UBM stack and superconducting solder bump318on the UBM stack. The etching of the remaining unwanted portions320of the seed layer310is selective relative to the superconducting solder bump318, meaning the etching does not remove the material of the superconducting solder bump. Thus, the material or materials of seed layer310may be selected, at least in part, to enable this selective etching or removal of unwanted portions of the seed layer while not removing the material of the solder bump318. The UBM stack includes the remaining portion of the seed layer310under the thick conductive pillar314, with this remaining portion of the seed layer forming the adhesion and diffusion barrier layers of the UBM stack. The thick conductive pillar316on the remaining portion of the seed layer310forms the solder wetting layer of the UBM stack having the superconducting solder bump318formed on this pillar. The process ofFIGS.3A-3Gis compatible with readily available commercial solder bump processing equipment and materials. Moreover, the process requires only one lithography step and is easy to scale to volume batch processes. The resulting superconducting solder bumps have been shown to be reliable for cryogenic applications requiring subsequent storage and heat treatment. An additional advantage of this process is that the Cu electroplating can be increased to achieve a Cu pillar structure having an even greater thickness T than shown in the embodiments ofFIGS.1-3. A Cu pillar with a greater thickness T allows for higher standoff for a cryogenic electronic chip including an interconnect structure with UBM stacks of the present application. A higher standoff for the UBM stacks can help relieve coefficient of thermal expansion (CTE) mismatch stress or make flux cleaning and underfilling processes easier. The process ofFIGS.3A-3Grequires the seed layer310be formed from a material that can be removed without removing the superconducting solder bump318and the thick conductive pillar316. Where the seed layer310includes a TiW layer and a thin Cu seed layer and the superconducting solder bump318is indium (In), the seed layer may be etched in the presence of the indium (In) solder bump using hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) based etchants in embodiments of the present disclosure. FIG.4is a simplified functional block diagram of a cryogenic electronic system400including superconducting electronic circuitry402containing one or more cryogenic electronic chips404having interconnect structures406according to an embodiment of the present disclosure. The superconducting electronic circuitry402includes circuitry for performing the required functions of the cryogenic electronic system400. In one embodiment, the superconducting electronic circuitry402corresponds to quantum computing circuitry. The interconnect structures406correspond to one or more of the interconnect structures described above in relation to the embodiments ofFIGS.1-3. The cryogenic electronic system400includes cryogenic cooling components408to cool and maintain the superconducting electronic circuitry402at deep cryogenic temperatures during operation. Interface circuitry410is also coupled to the superconducting electronic circuitry402and functions to provide an interface to receive input data IN from external electronic circuitry (not shown) operating at room temperature and to provide this input data to the superconducting electronic circuitry. The interface circuitry410also receives data from the superconducting electronic circuitry402and provides this data as output data OUT from the cryogenic electronic system400to the external electronic circuitry. FURTHER EXAMPLE EMBODIMENTS In various embodiments, the present disclosure includes systems, methods, and apparatuses for resilient data storage. The following techniques may be embodied alone or in different combinations and may further be embodied with other techniques described herein. In one embodiment, a cryogenic under bump metallization (UBM) stack, comprises: an adhesion and barrier layer; a conductive pillar on the adhesion and barrier layer, the conductive pillar configured to function as a solder wetting layer of the UBM stack and having a thickness; and an indium superconducting solder bump on the conductive pillar, the thickness of the conductive pillar being sufficient to prevent intermetallic regions in the conductive pillar that form due to interdiffusion between the conductive pillar and the indium superconducting solder bump during heat treatments and storage at room temperature from extending through the thickness of the conductive pillar. In one embodiment of the cryogenic UBM stack, the adhesion and barrier layer comprises a layered structure including a plurality of layers. In one embodiment of the cryogenic UBM stack, the layered structure has a layer of tungsten titanium (TiW) and a thin seed layer of copper (Cu). In one embodiment of the cryogenic UBM stack, the layer of TiW has a thickness of 100-150 nm and the thin seed layer of Cu has a thickness of 100-200 nm. In one embodiment of the cryogenic UBM stack, the conductive pillar is copper (Cu). In one embodiment of the cryogenic UBM stack, the thickness of the Cu pillar is at least 5 μm. In one embodiment of the cryogenic UBM stack, the adhesion and barrier layer is a titanium (Ti) layer. In one embodiment of the cryogenic UBM stack, the adhesion and barrier layer may be selectively removed relative to the superconducting solder bump. In another embodiment, a cryogenic electronic chip, comprises: a semiconductor die including a bond pad; and an under bump metallization (UBM) stack on semiconductor die, the UBM stack including: an adhesion and barrier layer on the bond pad; a conductive pillar on the adhesion and barrier layer, the conductive pillar being a solder wetting layer of the UBM stack and having a thickness; and an indium superconducting solder bump on the conductive pillar, the thickness of the conductive pillar having a value great enough to prevent intermetallic regions in the conductive pillar that form due to interdiffusion between the conductive pillar and the indium superconducting solder ball during heat treatments and storage at room temperature from extending through the thickness of the conductive pillar to the adhesion and barrier layer. In another embodiment of the cryogenic electronic chip, the adhesion and barrier layer is a layer of tungsten titanium (TiW) and a thin seed layer of copper (Cu) and the conductive pillar is copper (Cu). In another embodiment of the cryogenic electronic chip, wherein the heat treatments include multiple temperature variations up to a maximum of 200° C. and wherein the UBM stack can maintain mechanical and electrical integrity after being subjected to cryogenic shocks from room temperature to 4 K subsequent to the heat treatments and storage at room temperature. In another embodiment, a method of forming a cryogenic under bump metallization (UBM) stack, comprises: forming a seed layer on a passivation layer of a wafer and on a bond pad of a semiconductor die in the wafer that is exposed through an opening in the passivation layer; forming a sacrificial layer on the seed layer; patterning the sacrificial layer to expose a portion of the seed layer on the bond pad; forming a thick conductive pillar on the exposed portion of the seed layer, the thick conductive pillar having a thickness great enough to prevent intermetallic regions in the thick conductive pillar from extending through the entire thickness of the conductive pillar; forming an indium superconducting solder bump on the thick conductive pillar; removing the patterned sacrificial layer to expose portions of the seed layer; and removing the exposed portions of the seed layer to form the UBM stack under the indium superconducting solder bump. The UBM stack includes an adhesion and barrier layer formed by the remaining portion of the seed layer under the thick conductive pillar and a solder wetting layer formed by the thick conductive pillar. In one embodiment of the method, forming the seed layer comprises depositing one or more materials on the passivation layer and on the bond pad exposed through the opening in the passivation layer. In one embodiment of the method, depositing the one or more materials comprises sputtering or evaporation of the one or more materials. In one embodiment of the method, the one or more materials include tungsten titanium (TiW) and copper (Cu). In one embodiment of the method, forming the sacrificial layer on the seed layer comprises depositing a photoresist layer on the seed layer. In one embodiment of the method, forming the thick conductive pillar on the exposed portion of the seed layer comprises depositing a conductive material on the exposed portion of the seed layer through electroplating the conductive material on the exposed portion of the seed layer. In one embodiment of the method, forming the indium superconducting solder bump on the thick conductive pillar comprises depositing indium on the thick conductive pillar through electroplating. In one embodiment of the method, the conductive material is copper (Cu). In one embodiment of the method, removing the exposed portions of the seed layer to form the UBM stack comprises selectively etching the exposed portions of the seed layer to remove the exposed portions without removing the indium superconducting solder bump. The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described blocks or states may be performed in an order other than that specifically disclosed, or multiple blocks or states may be combined in a single block or state. The example blocks or states may be performed in serial, in parallel, or in some other manner Blocks or states may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments. Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or steps. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more embodiments or are to be performed in any particular embodiment. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list. The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims. | 31,722 |
11862594 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, terms, such as “first”, “second” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIG.1toFIG.8are schematic cross sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the disclosure. In embodiments, the manufacturing method is part of a wafer level packaging process. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a package structure. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. In some embodiments, as shown inFIG.1toFIG.8, one (semiconductor) chip or die is shown to represent plural (semiconductor) chips or dies of the wafer, and one (semiconductor) package structure is shown to represent plural (semiconductor) package structures obtained following the (semiconductor) manufacturing method, however the disclosure is not limited thereto. In alternative embodiments, more than one (semiconductor) chips or dies are shown to represent plural (semiconductor) chips or dies of the wafer, and one or more than one (semiconductor) package structure are shown to represent plural (semiconductor) package structures obtained following the (semiconductor) manufacturing method. Referring toFIG.1, in some embodiments, a carrier C with a debond layer DB and a solder resist layer110acoated thereon is provided. In some embodiments, the carrier C may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstituted wafer for the manufacturing method of the semiconductor package. In some embodiments, the debond layer DB is disposed on the carrier C, as shown inFIG.1. The material of the debond layer DB may be any material suitable for bonding and debonding the carrier C from the above layer(s) (e.g. the solder resist layer110a) or any wafer(s) disposed thereon. In some embodiments, the debond layer DB may include a dielectric layer made of a dielectric material including any suitable polymer-based dielectric material (such as benzocyclobutene (BCB), polybenzoxazole (PBO)). In an alternative embodiment, the debond layer DB may include a dielectric material layer made of an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating film. In a further alternative embodiment, the debond layer DB may include a dielectric material layer made of an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. In certain embodiments, the debond layer DB may be dispensed as a liquid and cured, or may be a laminate film laminated onto the carrier C, or may be the like. The top surface of the debond layer DB, which is opposite to a bottom surface contacting the carrier C, may be levelled and may have a high degree of coplanarity. In certain embodiments, the debond layer DB is, for example, a LTHC layer with good chemical resistance, and such layer enables room temperature debonding from the carrier C by applying laser irradiation, however the disclosure is not limited thereto. In some embodiments, the solder resist layer110ais disposed on the debond layer DB, and the debond layer DB is located between the carrier C and the solder resist layer110a. In some embodiments, a surface S1(e.g. a top surface) of the solder resist layer110amay provide a high degree of coplanarity and flatness. Due to the high degree of coplanarity and flatness, the formation of the later-formed layer(s) and/or element(s) is beneficial. As shown inFIG.1, along a direction Z (e.g. a stacking direction of the carrier C, the debond layer DB and the solder resist layer110a), a thickness T110aof the solder resist layer110ais approximately from 10 μm to 30 μm. In some embodiments, the solder resist layer110ais a layer made of a solder resist material, where the solder resist material is composed of an epoxy-based resin and a filler. In the solder resist layer110a, a weight percentage ratio of the epoxy-based resin to the filler is approximately from 40:60 to 60:40, in some embodiments. The filler, for example, includes silica (SiO2), barium sulfate (BaSO4), or a combination thereof, where a particle diameter of the filler is approximately from 0.2 μm to 2 μm. In some embodiments, the solder resist layer110ais formed on the debond layer DB by lamination. In some embodiments, the solder resist layer110ahas a coefficient of thermal expansion (CTE) approximately ranging from 18 ppm/K to 35 ppm/K, a Young's modulus (E) approximately ranging from 5 GPa to 10 GPa, and a glass transition temperature (Tg) approximately ranging from 150 degrees Celsius to 180 degrees Celsius. In certain embodiments, the solder resist layer110ais photosensitive (see package structures10aand10brespectively depicted inFIG.6andFIG.10). However, the disclosure is not limited thereto; in alternative embodiments, the solder resist layer110ais non-photosensitive (see package structures10cand10drespectively depicted inFIG.14andFIG.16). Due to the solder resist layer110a(e.g. low CTE value) in addition to its specific thickness range, better warpage control (e.g., warpage being less than or substantially equal to 80 μm at room temperature and being greater than or substantially equal to −80 μm) to the package structure10ais achieved. As illustrated inFIG.1, in the embodiment of which the solder resist layer110ais photosensitive, after the solder resist layer110ais laminated onto the debond layer DB with a surface S2(e.g. a bottom surface), a plurality of openings OP1are formed, by photolithography processes, in the solder resist layer110ato expose portions of the debond layer DB. For example, a surface S0of the debond layer DB is partially exposed by the openings OP1formed in the solder resist layer110a. In the solder resist layer110ashown inFIG.1, an angle θ1between the surface S2of the solder resist layer110aand a sidewall SW1of each opening OP1is approximately 60 degrees to 80 degrees, and an angle θ2(i.e. θ2=180 degrees-θ1) between the surface S1of the solder resist layer110aand the sidewall SW1of each opening OP1is 100 degrees to 120 degrees. The surface S2is opposite to the surface S1along the direction Z, and the surface S2is stacked on the surface S0of the debond layer DB as shown inFIG.1, for example. With the formation of the solder resist layer110ahaving the openings OP1, the manufacturing cost and process complexity are further reduced. Only two openings OP1are shown inFIG.1for illustrative purposes, and the disclosure is not limited thereto. The number of the openings OP1may be more than two based on the demand and the design layout. Additionally, for example, on a X-Y plane (where a direction X is different from a direction Y, and the directions X and Y are different from the direction Z (e.g. the stacking direction)), dimensions (e.g. maximum widths) of the openings OP1may be the same, however the disclosure is not limited thereto. In an alternative embodiment, according to the design layout and/or demand, the dimensions of the openings OP1may be the different from each other or may be different in a manner of different groups. In one embodiment, on the X-Y plane, a cross-sectional shape of the openings OP1individually may be round, elliptical, oval, tetragonal, octagonal or any suitable polygonal shape; the disclosure is not limited thereto. Referring toFIG.2, in some embodiments, at least one conductive pillar120and at least one semiconductor die130are formed on the solder resist layer110a. For illustrative purposes, the at least one conductive pillar120include a plurality of conductive pillars120(e.g. two conductive pillars120), and at least one semiconductor die130include one semiconductor die130, as presented inFIG.2. However, the number of the conductive pillars120and the number of the semiconductor die130are not limited to what is depicted in the disclosure, and may be selected and designated based on the demand and design layout. For example, the number of the conductive pillars120may be more than two and the number of the semiconductor die130may be more than one, where the number of the conductive pillars120may be adjusted by changing the number of the openings OP1. In some embodiments, the conductive pillars120and the semiconductor die130are arranged side-by-side on the solder resist layer110a. In some embodiments, the conductive pillars120are formed on the solder resist layer110a(e.g. the surface S1of the solder resist layer110a). In some embodiments, the conductive pillars120may be through integrated fan-out (InFO) vias. In some embodiments, the conductive pillars120are arranged along but not on a cutting line (not shown) between two package structures (e.g. two of the package structures10a). As shown inFIG.2, the conductive pillars120are formed on the solder resist layer110aand penetrate through the solder resist layer110avia the openings OP1, in some embodiment. Through the openings OP1, the conductive pillars120are in physical contact with the debond layer DB, for example. In some embodiments, the conductive pillars120are formed by photolithography, plating, photoresist stripping processes or any other suitable method. For example, the plating process may include an electroplating plating, an electroless plating, or the like. For example, the conductive pillars120may be formed by forming a mask pattern (not shown) covering the solder resist layer110awith openings exposing the surface S0of the debond layer DB exposed by the openings OP1formed in the solder resist layer110a, forming a metallic material filling the openings formed in the mask pattern and the openings OP1to form the conductive pillars120by electroplating or deposition and then removing the mask pattern. In one embodiment, the mask pattern may be removed by acceptable ashing process and/or photoresist stripping process, such as using an oxygen plasma or the like. In some embodiments, prior to the formation of the mask pattern, a seed layer (not shown) may be formed conformally over the solder resist layer110aand extend into the openings OP1to be located on the debond layer DB, where the metallic material filling the openings formed in the mask pattern and the openings OP1formed in the solder resist layer110ais used as an mask to remove portions of the seed layer not being covered thereto. The disclosure is not limited thereto. In some embodiments, the material of the conductive pillars120may include a metal material such as copper or copper alloys, or the like. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc. However, the disclosure is not limited thereto. In alternative embodiments, the conductive pillars120may be pre-fabricated conductive pillars which may be disposed on the solder resist layer110aby picking- and placing. Continued onFIG.2, in some embodiments, the semiconductor die130is disposed on the solder resist layer110aand over the carrier C. For example, the semiconductor die130is picked-up and placed on the solder resist layer110a, and is attached or adhered on the solder resist layer110athrough a connecting film DA. In some embodiments, the connecting film DA is located between the semiconductor die130and the solder resist layer110a, where the connecting film DA physically contacts the backside surface130bof the semiconductor die130and the solder resist layer110a(e.g. the surface S1of the solder resist layer110a). Due to the connecting film DA, the semiconductor die130and the solder resist layer110aare stably adhered to each other. In some embodiments, the connecting film DA may be, for example, a die attach film, a layer made of adhesives or epoxy resin, or the like. In some embodiments, the semiconductor die130includes a substrate131having an active surface130aand a backside surface130bopposite to the active surface130a(along the direction Z), a plurality of conductive pads132formed on the active surface130a, a passivation layer133disposed on and partially exposing the conductive pads132, a post-passivation layer134disposed on the passivation layer133and partially exposing the conductive pads132, connecting vias135disposed on the conductive pads132, and a protection layer136covering the post-passivation layer134and the connecting vias135. In other words, the conductive pads132distributed on the active surface130aof the substrate131are partially exposed by contact openings of the passivation layer133and contact openings of the post-passivation layer134, so as to physically connect to the connecting vias135. For example, the substrate131is a semiconductor substrate. In some embodiments, the material of the substrate131may include a silicon substrate including active components (e.g., transistors and/or memories such as NMOS and/or PMOS devices, or the like) and/or passive components (e.g., resistors, capacitors, inductors or the like) formed therein. In an alternative embodiment, the substrate131may be a bulk silicon substrate, such as a bulk substrate of monocrystalline silicon, a doped silicon substrate, an undoped silicon substrate, or a SOI substrate, where the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant or a combination thereof. The disclosure is not limited thereto. In some embodiments, the conductive pads132may be aluminum pads or other suitable metal pads. For example, the conductive pads132may be formed by electroplating or deposition, and then patterned using a photolithography and etching process. In some embodiments, the connecting vias135may be copper pillars, copper alloy pillar or other suitable metal pillars. For example, the forming process of the connecting vias135may be substantially the same or similar to the formation of the conductive pillars120. However, the disclosure is not limited thereto. In some embodiments, the passivation layer133, the post-passivation layer134and/or the protection layer136may be a PBO layer, a polyimide (PI) layer or other suitable polymers. In certain embodiments, the passivation layer133, the post-passivation layer134and/or the protection layer136may be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. In one embodiment, the materials of the passivation layer133, the post-passivation layer134and/or the protection layer136may be the same. In an alternative embodiment, the materials of the passivation layer133, the post-passivation layer134and/or the protection layer136may be different from one another, the disclosure is not limited thereto. In some embodiments, the semiconductor die130described herein may be referred to as a chip or an integrated circuit (IC). For example, in an alternative embodiment, the semiconductor die130includes a digital chip, an analog chip, or a mixed signal chip, such as an application-specific integrated circuit (“ASIC”) chip, a sensor chip, a wireless and radio frequency (RF) chip, a memory chip, a logic chip, a voltage regulator chip, or a combination thereof. In an alternative embodiment, the semiconductor die130may be referred to as a chip or an IC of combination-type. For example, the semiconductor die130may be a WiFi chip simultaneously including both of a RF chip and a digital chip. The disclosure is not limited thereto. In alternative embodiments, the semiconductor die130may further include additional semiconductor die(s) of the same type or different types. For example, the additional semiconductor die(s) may include digital chips, analog chips or mixed signal chips, such as ASIC chips, sensor chips, wireless and RF chips, memory chips, logic chips or voltage regulator chips. The disclosure is not limited thereto. As shown inFIG.2, for example, positioning locations of the conductive pillars120are located aside of a positioning location of the semiconductor die130on the X-Y plane. In some embodiments, along the direction Z, a height of the conductive pillars120is greater than a height of the semiconductor die130; however, the disclosure is not limited thereto. In an alternative embodiment, the height of the conductive pillars120may be less than or substantially equal to the height of the semiconductor die130. In one embodiment, the conductive pillars120may be formed prior to the formation of the semiconductor die130; however, the disclosure is not limited thereto. In an alternative embodiment, the conductive pillars120may be formed after the formation of the semiconductor die130. Referring toFIG.3, in some embodiments, an insulating encapsulation140ais formed over the carrier C (e.g., on the solder resist layer110a) to encapsulate the conductive pillars120and the semiconductor die130. In other words, the insulating encapsulation140ais formed on the solder resist layer110a, the conductive pillars120and the semiconductor die130, where the conductive pillars120and the semiconductor die130(disposed with the connecting film DA) are covered by and embedded in the insulating encapsulation140a. As shown inFIG.3, for example, the insulating encapsulation140aat least fills up the gaps between the conductive pillars120and the gaps between the conductive pillars120, the semiconductor die130and the connecting films DA. In some embodiments, sidewalls120sof the conductive pillars120and sidewalls130sof the semiconductor die130are covered by the insulating encapsulation140a. In some embodiments, the surface S1of the solder resist layer110aexposed by the conductive pillars120and the semiconductor die130are covered by the insulating encapsulation140a. For example, as shown inFIG.3, the solder resist layer110a, the conductive pillars120, the semiconductor die130and the connecting film DA are not accessibly revealed by the insulating encapsulation140a. In some embodiments, the insulating encapsulation140ais a molding compound formed by a molding process. In some embodiments, the insulating encapsulation140a, for example, may include polymers (such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), dielectric materials having low permittivity and low loss tangent properties, or other suitable materials. The disclosure is not limited thereto. In an alternative embodiment, the insulating encapsulation140amay include an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulation140amay further include inorganic filler or inorganic compound (e.g. silica, clay, and so on) which can be added therein to optimize the CTE of the insulating encapsulation140a. In the disclosure, the material of the insulating encapsulation140ais different from the material of the solder resist layer110a, where the CTE of the insulating encapsulation140ais less than the CTE of the solder resist layer110a. Referring toFIG.4, in some embodiments, the insulating encapsulation140ais planarized to form an insulating encapsulation140exposing the conductive pillars120and the semiconductor die130. In certain embodiments, as shown inFIG.4, after the planarization, top surfaces120tof the conductive pillars120and a top (or front) surface130tof the semiconductor die130(e.g. top surfaces (not labelled) of the connecting vias135and the protection layer136of the semiconductor die130) are exposed by a top surface140tof the insulating encapsulation140. That is, for example, the top surface130tof the semiconductor die130and the top surfaces120tof the conductive pillars120become substantially leveled with the top surface140tof the insulating encapsulation140. In other words, the top surface130tof the semiconductor die130, the top surfaces120tof the conductive pillars120, and the top surface140tof the insulating encapsulation140are substantially coplanar to each other. In some embodiments, the conductive pillars120each penetrate through the insulating encapsulation140and have the top surfaces120texposed therefrom, while the semiconductor die130are embedded inside the insulating encapsulation140and has the top surface130texposed therefrom. For example, as shown inFIG.4, the conductive pillars120and the semiconductor die130are accessibly revealed by the insulating encapsulation140. The insulating encapsulation140amay be planarized by mechanical grinding or chemical mechanical polishing (CMP), for example. After the planarizing step, a cleaning step may be optionally performed, for example to clean and remove the residue generated from the planarizing step. However, the disclosure is not limited thereto, and the planarizing step may be performed through any other suitable method. In some embodiments, during planarizing the insulating encapsulation140a, the connecting vias135and the protection layer136of the semiconductor die130and the conductive pillars120may also be planarized. In certain embodiments, the planarizing step may, for example, be performed on the over-molded insulating encapsulation140ato level the top surface140tof the insulating encapsulation140, the top surfaces120tof the conductive pillars120and the top surface130tof the semiconductor die130. Referring toFIG.5, in some embodiments, a redistribution circuit structure150is formed on the conductive pillars120, the semiconductor die130, and the insulating encapsulation140. As shown inFIG.5, the redistribution circuit structure150is directly formed on the top surfaces120tof the conductive pillars120, the top surface130tof the semiconductor die130, and the top surface140tof the insulating encapsulation140, for example. In some embodiments, the redistribution circuit structure150is electrically connected to the conductive pillars120, and is electrically connected to the semiconductor die130through the connecting vias135. In some embodiments, through the redistribution circuit structure150, the semiconductor die130is electrically connected to the conductive pillars120. In alternative embodiments of which more than one semiconductor dies130are included, the semiconductor dies130are electrically communicated through the redistribution circuit structure150. As shown inFIG.5, for example, the redistribution circuit structure150is referred to as a front-side redistribution layer of the semiconductor die130. For example, as shown inFIG.5, along the stacking direction (e.g. the direction Z), the semiconductor die130is located between the redistribution circuit structure150and the connecting film DA. In addition, a portion of each of the conductive pillars120is located between the redistribution circuit structure150and the solder resist layer110a, and other portion of each of the conductive pillars120is located between the redistribution circuit structure150and the debond layer DB. The insulating encapsulation140is located between the redistribution circuit structure150and the solder resist layer110a, for example. In some embodiments, the formation of the redistribution circuit structure150includes sequentially forming one or more dielectric layers152and one or more metallization layers154in alternation. For example, as shown inFIG.5, the redistribution circuit structure150includes dielectric layers152a,152b,152c,152dand the metallization layers154a,154b,154c. In some embodiments, the metallization layer154ais sandwiched between the dielectric layers152aand152b, the metallization layer154bis sandwiched between the dielectric layers152band152c, the metallization layer154cis sandwiched between the dielectric layers152cand152d. The disclosure is not limited thereto. It should be noted that the redistribution circuit structure150is not limited to include four dielectric layers and three metallization layers. For example, the number of the metallization layers and the numbers of the dielectric layers may be one or more than one. In some embodiments, the material of the dielectric layers152may be PI, PBO, BCB, a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In some embodiments, the material of the dielectric layers152formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. The disclosure is not limited thereto. In some embodiments, the material of the metallization layers154may be made of conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. In some embodiments, the metallization layers154may be patterned copper layers or other suitable patterned metal layers. In some embodiments, a seed layer (not shown) may be formed between one metallization layer154and a respective one dielectric layer152underlying thereto. In some embodiments, the seed layer may be referred to as a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, a material of the seed layer may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the seed layer may include a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer may be formed using, for example, sputtering, physical vapor deposition (PVD), or the like. In some embodiments, portions of a top surface of a topmost layer (e.g. the metallization layer154c) of the metallization layers154are exposed by a topmost layer (e.g. the dielectric layer152d) of the dielectric layers152to electrically connect overlying conductive features (e.g. later-formed under bump metallurgy (UBM) patterns162and/or contact pads164). For example, as shown inFIG.5, the portions of the top surface of the metallization layer154care exposed by openings OP2formed in the the dielectric layer152d. In some embodiments, portions of a bottom surface of a lowest layer (e.g. the metallization layer154a) of the metallization layers154are exposed by a lowest layer (e.g. the dielectric layer152a) of the dielectric layers152to electrically connect underlying conductive features (e.g. the conductive pillars120and the connecting vias135of the semiconductor die130). As shown inFIG.5, in some embodiments, the conductive pillars120, and the redistribution circuit structure150provide a routing function for the semiconductor die130. Referring toFIG.6, in some embodiments, a plurality of UBM patterns162are formed to be disposed on the exposed top surfaces of the topmost layer (e.g. the metallization layer154c) of the metallization layers154for electrically connecting with conductive elements (e.g. conductive balls or conductive bumps). In some embodiments, prior to, during, or after the formation of the UBM patterns162, a plurality of contact pads164are optionally formed to be disposed on some of the exposed top surfaces of the topmost layer (e.g. the metallization layer154c) of the metallization layers154for electrically connecting with semiconductor elements (e.g. semiconductor active or passive devices). The number of the UBM patterns162and the number of the contact pads164are not limited as depicted in the disclosure, and may be selected and designated based on the demand and design layout, the disclosure is not limited thereto. For example, as shown inFIG.6, the UBM patterns162and the contact pads164are formed on and electrically connected to the redistribution circuit structure150. For example, the UBM patterns162and the contact pads164are disposed on the dielectric layer152dand further in contact with the portions of the metallization layer154cexposed by the openings OP2formed in the dielectric layer152d. In some embodiments, the materials of the UBM patterns162and the contact pads164may include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed by an electroplating process, for example. In one embodiment, the material of the UBM patterns162may be the same as that of the contact pads164. In an alternative embodiment, the material of the UBM patterns162may be different from that of the contact pads164. In one embodiment, there may be only the UBM patterns162; however, the disclosure is not limited thereto. In one embodiment, the UBM patterns162and the contact pads164may be formed in the same processing step. In an alternative embodiment, the UBM patterns162and the contact pads164may be formed in different processing steps. Continued onFIG.6, in some embodiments, a plurality of conductive elements172are formed on the redistribution circuit structure150. For example, the conductive elements172are disposed on the UBM patterns162located on the redistribution circuit structure150. In some embodiments, the conductive elements172may be disposed on the UBM patterns162by ball placement process or reflow process. In some embodiments, the conductive elements172are, for example, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, solder balls/bumps or other connectors. When solder is used, the solder may include either eutectic solder or non-eutectic solder. The solder may include lead or be lead-free, and may include Sn—Ag, Sn—Cu, Sn—Ag—Cu, or the like. In the disclosure, for one embodiment, the conductive elements172may be referred to as conductive connectors for connecting with another package; or for another embodiment, the conductive elements172may be referred to as conductive terminals for inputting/outputting electric and/or power signals. In some embodiments, the conductive elements172are electrically connected (e.g. electrically coupled) to the redistribution circuit structure150through the UBM patterns162. As shown in theFIG.6, some of the conductive elements172are electrically connected to the semiconductor die130through the UBM patterns162and the redistribution circuit structure150, and some of the conductive elements172are electrically connected to the conductive pillars120through the UBM patterns162and the redistribution circuit structure150, for example. The number of the conductive elements172is not limited to the disclosure, and may be designated and selected based on the number of the UBM patterns162. In some embodiments, one or more semiconductor devices174are provided and disposed on the redistribution circuit structure150. For example, the semiconductor devices174are disposed on the contact pads164, and are electrically connected to the redistribution circuit structure150through the contact pads164. In some embodiments, some of the semiconductor devices174are electrically connected to the semiconductor die130through the contact pads164and the redistribution circuit structure150. In some embodiments, some of the semiconductor devices174are electrically connected to the conductive pillars120through the contact pads164and the redistribution circuit structure150. In some embodiments, some of the semiconductor devices174are electrically connected to at least one of the conductive elements172through the contact pads164, the redistribution circuit structure150and the UBM patterns162. In some embodiments, the semiconductor devices174may be disposed on the contact pads164through reflow process or flip chip bonding. In some embodiments, the semiconductor devices174include surface mount devices (e.g. passive devices, such as, capacitors, resistors, inductors, combinations thereof, or the like). The number of the semiconductor devices174can be selected based on the number of the contact pads164. In an alternative embodiment, the semiconductor devices174may include surface mount devices of the same type or different types, the disclosure is not limited thereto. In alternative embodiments, the semiconductor devices174are optional, and may be omitted. In some embodiments, along the direction Z, the conductive elements172and the semiconductor devices174are formed on a side of the redistribution circuit structure150, and the insulating encapsulation140is formed on other side of the redistribution circuit structure150. That is, the redistribution circuit structure150is located between the insulating encapsulation140and the conductive elements172and between the insulating encapsulation140and the semiconductor devices174. In some embodiments, the semiconductor devices174may be formed prior to the formation of the conductive elements172. In an alternative embodiment, the conductive elements172may be formed prior to the formation of the semiconductor devices174. The disclosure is not limited to thereto. Referring toFIG.7, in some embodiments, the whole structure depicted inFIG.6along with the carrier C is flipped (turned upside down), where the conductive elements172are placed to a holding device HD, and the carrier C is then debonded from the solder resist layer110a. In some embodiments, the holding device HD may be an adhesive tape, a carrier film or a suction pad. The solder resist layer110ais easily separated from the carrier C due to the debond layer DB. In some embodiments, the carrier C is detached from the solder resist layer110athrough a debonding process, and the carrier C and the debond layer DB are removed. For example, the surface S2of the solder resist layer110aand bottom surface120bof the conductive pillars120are exposed. In one embodiment, the debonding process is a laser debonding process. During the debonding step, the holding device HD is used to secure the package depicted inFIG.6before debonding the carrier C and the debond layer DB. As shown inFIG.7, for example, the openings OP1are filled up with the conductive pillars120, where the surfaces120bof the conductive pillars120are substantially coplanar with the surface S2of the solder resist layer110a. Referring toFIG.8, in some embodiments, a plurality of conductive elements180aare formed on the bottom surfaces120bof the conductive pillars120. For example, the bottom surfaces120bof the conductive pillars120exposed by the surface S2of the solder resist layer110aare covered by the conductive elements180a. For example, the conductive elements180ainclude conductive bumps or conductive balls. The conductive elements180amay be pre-solder pastes, for example. In an alternative embodiment, the conductive elements180amay be pre-solder blocks. In some embodiments, the material of the conductive elements180amay include a lead-free solder material (such as Sn—Ag base or Sn—Ag—Cu base materials) with or without additional impurity (such as Ni, Bi, Sb, Au, or the like). The disclosure is not limited thereto. In the disclosure, the conductive elements180amay also be referred to as conductive terminals for electrical connection to external elements (e.g. an additional semiconductor package/device, a circuit substrate, etc.). As shown inFIG.8, the conductive elements180aare formed outside of the openings OP1and covered the surfaces120bof the conductive pillars120. That is, the conductive elements180aare rest at the surface S2of the solder resist layer110aand are protruding outwards from the surface S2. In some embodiments, the conductive elements172are released from the holding device HD to form the package structure10a. In some embodiments, a dicing (singulating) process is performed to cut a plurality of the package structures10ainterconnected therebetween into individual and separated package structures10abefore releasing the conductive elements172from the holding device HD. In one embodiment, the dicing process is a wafer dicing process including mechanical blade sawing or laser cutting. Up to here, the manufacture of the package structure10ais completed. The package structure10adepicted inFIG.8may be referred to as an integrated fan-out (semiconductor) package structure having dual-side terminals. In some alternative embodiments, the package structure10amay be further mounted with a circuit substrate, an interposer, an additional package, chips/dies or other electronic devices to form a stacked package structure or a package on package (PoP) structure through the conductive elements172and/or other the conductive elements180abased on the design layout and the demand. FIG.9is a schematic cross sectional view of a package structure in accordance with some embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, etc.) of the same elements would not be repeated herein. Referring toFIG.9, for example, a semiconductor package800is provided and then bonded to the package structure10a, thereby forming a package structure SP1of a stacked structure. The detail of the package structure10ais described inFIG.8, and thus is not repeated herein for simplicity. In some embodiments, the semiconductor package800has a substrate810, semiconductor dies820aand820b, bonding wires830aand830b, conductive pads840, conductive pads850, an insulating encapsulation860, and conductive elements870. For example, the semiconductor die820aand the semiconductor die820bare provided and disposed on the substrate810. In some embodiments, the connecting film DA2is located between the semiconductor die820aand the substrate810, and the connecting film DA3is located between the semiconductor die820aand the semiconductor die820b. In some embodiments, due to the connecting films DA2and DA3respectively provided between the semiconductor die820aand the substrate810and between the semiconductor dies820aand820b, the semiconductor dies820a,820bare stably adhered to the substrate810. In some embodiments, the connecting films DA2, DA3may be, for example, a die attach film, a layer made of adhesives or epoxy resin, or the like. For example, the semiconductor dies820aand820bare mounted on one surface (e.g. a surface810a) of the substrate810. In some embodiments, the semiconductor dies820aand820bmay be logic chips (e.g., central processing units, microcontrollers, etc.), memory chips (e.g., dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, etc.), power management chips (e.g., power management integrated circuit (PMIC) chips), radio frequency (RF) chips, sensor chips, signal processing chips (e.g., digital signal processing (DSP) chips), and/or front-end chips (e.g., analog front-end (AFE) chips, the like, or a combination thereof). The semiconductor dies820aand820bare DRAM chips, as shown inFIG.9, for example. In one embodiment, the semiconductor dies820aand820bmay be the same. However, the disclosure is not limited thereto; in an alternative embodiment, the semiconductor dies820aand820bmay be different from each other. In some embodiments, the bonding wires830aand830bare respectively used to provide electrical connections between the semiconductor dies820a,820band some of the conductive pads840(such as bonding pads) located on the surface810aof the substrate810. Owing to the bonding wires830aand830b, the semiconductor dies820aand820bare electrically connected to the substrate810. In some embodiments, the insulating encapsulation860is formed on the surface810aof the substrate810to encapsulate the semiconductor dies820a,820b, the bonding wires830a,830b, and the conductive pads840to protect these components. In some embodiments, the material of the insulating encapsulation860is the same as the materials of the insulating encapsulation140/140a, and thus is not repeated herein for simplicity. In one embodiment, the material of the insulating encapsulation860is different from the materials of the insulating encapsulation140/140a, the disclosure is not limited thereto. In some embodiments, interconnects (not shown) or through insulator vias (not shown) embedded in the substrate810may be used to provide electrical connection between the conductive pads840and the conductive pads850(such as bonding pads) that are located on another surface (e.g. a surface810bopposite to the surface810aalong the direction Z) of the substrate810. In certain embodiments, some of the conductive pads850are electrically connected to the semiconductor dies820aand820bthrough these insulator vias or interconnects (not shown) in addition to some of the conductive pads840and the bonding wires830a,830b. In some embodiments, conductive elements870are disposed on the conductive pads850and over the surface810bof the substrate810. The formation and material of the conductive elements870may be the same or similar to the formation and material of the conductive elements170or the formation and material of the conductive elements180a, and thus are not repeated herein for simplicity. As shown inFIG.9, for example, the conductive elements180aof the package structure10ais bonded to the conductive elements870of the semiconductor package800, and thus joints300aare formed, in the package structure SP1, to electrically connect the semiconductor die130to the semiconductor dies820a,820b. In some embodiments, the joints300aare located between the solder resist layer110aand the substrate810. In other words, the semiconductor dies820a,820bof the semiconductor package800are electrically connected to the semiconductor die130of the package structure10athrough the bonding wires830aand830b, the conductive pads840,850disposed on the substrate810, the joints300a(including the conductive elements870and180a), the conductive pillars120, and the redistribution circuit structure150. In addition, an underfill (not shown) may be optimally formed to wrap around sidewalls of the joints300a. The underfill may further fill up the gaps between the solder resist layer110aof the package structure10aand the substrate810of the semiconductor package800, for example. The underfill may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like, for example. In one embodiment, the underfill may be formed by underfill dispensing or any other suitable method. Owing to the underfill, the bonding strength between the package structure10aand the semiconductor package800are enhanced, thereby improving the reliability of the package structure SP1depictedFIG.9. FIG.10is a schematic cross sectional view of a package structure in accordance with some embodiments of the disclosure.FIG.11is a schematic cross sectional view of a package structure in accordance with some embodiments of the disclosure. Referring toFIG.8andFIG.10together, the semiconductor package structure10adepicted inFIG.8and a semiconductor package structure10bdepicted inFIG.10are similar, the difference is that an additional element, e.g. a redistribution circuit structures190, is further included in the semiconductor package structure10b. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, etc.) of the same elements would not be repeated herein. With the embodiments of which the redistribution circuit structure190is included, the redistribution circuit structure190is formed prior to the formation of the conductive pillars120and after the formation of the solder resist layer110a. In some embodiments, the redistribution circuit structure190is located on the surface S1of the solder resist layer110aand a bottom surface140bof the insulating encapsulation140. Along the direction Z, the bottom surface140bof the insulating encapsulation140is opposite to the top surface140tof the insulating encapsulation140. In some embodiments, the redistribution circuit structure190is electrically connected to the conductive pillars120, is electrically connected to the redistribution circuit structure150through the conductive pillars120, and is electrically connected to the semiconductor die130through the conductive pillars120, the redistribution circuit structure150, and the connecting vias135. In some embodiments, through the conductive pillars120, the redistribution circuit structure150and the UBM patterns162, the redistribution circuit structure190is further electrically connected to at least one of the conductive elements172. In some embodiments, through the conductive pillars120, the redistribution circuit structure150and the contact pads164, the redistribution circuit structure190is further electrically connected to at least one of the semiconductor devices174. In some embodiments, the redistribution circuit structure190is electrically connected to the conductive elements180a. In such embodiments, the semiconductor die130is electrically connected to at least some of the conductive elements180athrough the redistribution circuit structure150, the conductive pillars120and the redistribution circuit structure190. As shown inFIG.10, for example, the redistribution circuit structure190is referred to as a back-side redistribution layer of the semiconductor die130. In some embodiments, the formation of the redistribution circuit structure190includes sequentially forming one or more dielectric layers192and one or more metallization layers194in alternation. For illustrative purposes, as shown inFIG.10, the redistribution circuit structure190includes one dielectric layer192and one metallization layer194. It is appreciated that the redistribution circuit structure190is not limited to include one dielectric layer192and one metallization layer194. The number of the dielectric layer192and the number of the metallization layer194may be more than one based on the demand and the design layout. In some embodiments, the metallization layer194is located on the solder resist layer110a; the dielectric layer192is located on the metallization layer194; and the conductive pillars120, the semiconductor die130and the insulating encapsulation140are located on the dielectric layer192. For example, as shown inFIG.10, the conductive pillars120individually penetrate the dielectric layer192to electrically connect to the metallization layer194, and the metallization layer194penetrate the solder resist layer110ato electrically connect to the conductive elements180a. That is, the conductive elements180aare, via the redistribution circuit structure190, electrically connected to the conductive pillars120. In some embodiments, the material and formation of the dielectric layer192may be the same as the material and formation of the dielectric layers152, and the material and formation of the metallization layer194may be the same as the material and formation of the metallization layers154, thus is not repeated herein. In an alternative embodiment, the material of the dielectric layer192may be the same as or different from the material of the dielectric layers152. In an alternative embodiment, the material of the metallization layer194may be the same as or different from the material of the metallization layers154. The disclosure is not limited thereto. In some alternative embodiments, a seed layer (not shown) may be formed between the metallization layer194and the solder resist layer110aunderlying thereto. In some embodiments, the seed layer may be referred to as a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, a material of the seed layer may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the seed layer may include a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer may be formed using, for example, sputtering, physical vapor deposition (PVD), or the like. In alternative embodiments, the package structure10ain the package structure SP1may be replaced with the package structure10bofFIG.10, see a package structure SP2depicted inFIG.11. In some embodiments, as shown inFIG.11, for the package structure SP2, the semiconductor package800is bonded to the semiconductor package structure10bdepicted inFIG.10by connecting the conductive elements870and the conductive elements180a(e.g. forming the joints300a). In such embodiments, the semiconductor dies820a,820bof the semiconductor package800are electrically connected to the semiconductor die130of the package structure10bthrough the bonding wires830aand830b, the conductive pads840and850disposed on the substrate810, the joints300a(including the conductive elements870and180a), the redistribution circuit structure190, the conductive pillars120, and the redistribution circuit structure150. FIG.12toFIG.14are schematic cross sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the disclosure.FIG.15is a schematic cross sectional view of a package structure in accordance with some embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, etc.) of the same elements would not be repeated herein. Referring inFIG.12, in some embodiments, a carrier C with a debond layer DB and a solder resist layer110bcoated thereon is provided. For example, the debond layer DB is located between the carrier C and the solder resist layer110b. The material of the carrier C and the formation and material of the debond layer DB have been described inFIG.1, and thus are not repeating herein for simplicity. In the disclosure, the formation and material of the solder resist layer110bis similar to the formation and the material of the solder resist layer110adescribed inFIG.1, however, the solder resist layer110bis non-photosensitive. In some embodiments, a thickness T110bof the solder resist layer110bis approximately from 10 μm to 30 μm. Due to the solder resist layer110b(e.g. the low CTE value) in addition to its specific thickness range, better warpage control (e.g., warpage being less than or substantially equal to 80 μm at room temperature and being greater than or substantially equal to −80 μm) to the package structure10cis achieve. Thereafter, in some embodiments, at least one conductive pillar120and at least one semiconductor die130are formed on the solder resist layer110b(e.g. on a surface S3of the solder resist layer110b). For illustrative purposes, the at least one conductive pillar120include a plurality of conductive pillars120(e.g. two conductive pillars120), and at least one semiconductor die130include one semiconductor die130; however, the disclosure is not limited thereto. The formation and material of the conductive pillars120and the formation and material of the semiconductor die130have been described inFIG.1, and thus are not repeating herein for simplicity. In some embodiments, the conductive pillars120and the semiconductor die130are arranged side-by-side on the solder resist layer110balong the X-Y plane. Due to the solder resist layer110bis non-photosensitive, no opening OP1is formed in the solder resist layer110bprior to the formations of conductive pillars120and the semiconductor die130. Referring toFIG.13, in some embodiments, the previously described manufacturing process as described inFIG.3toFIG.7and a subsequent patterning process are performed on the structure depicted inFIG.12. For example, by performing the previously described manufacturing process as described inFIG.3toFIG.7on the structure depicted inFIG.12, the carrier C and the debond layer DB are removed from the solder resist layer110b, where a surface S4of the solder resist layer110bis exposed. The surface S4is opposite to the surface S3along the direction Z. Thereafter, in some embodiments, the exposed solder resist layer110bis then patterned to form a plurality of openings OP3therein. The patterning process, for example, includes a laser drill process. For example, only two openings OP3are shown inFIG.13for illustrative purposes; however, the number of the openings OP3may be more than two based on the demand and the design layout. Additionally, for example, on the X-Y plane, dimensions (e.g. maximum widths) of the openings OP3may be the same, however the disclosure is not limited thereto. In an alternative embodiment, according to the design layout and/or demand, the dimensions of the openings OP3may be the different from each other or may be different in a manner of different groups. In one embodiment, on the X-Y plane, a cross-sectional shape of the openings OP3individually may be round, elliptical, oval, tetragonal, octagonal or any suitable polygonal shape; the disclosure is not limited thereto. As illustrated inFIG.13, after patterning the solder resist layer110b, the bottom surfaces120bof the conductive pillars120are exposed by the openings OP3. As shown inFIG.13, for example, the openings OP3are not filled with the conductive pillars120, where the surfaces120bof the conductive pillars120are substantially coplanar with the surface S3of the solder resist layer110b. That is, the conductive pillars120are not extended into the openings OP3. In the solder resist layer110bshown inFIG.13, an angle θ3between the surface S3of the solder resist layer110band a sidewall SW2of each opening OP3is approximately 40 degrees to 60 degrees, and an angle θ4(i.e. θ4=180 degrees-θ3) between the surface S4of the solder resist layer110band the sidewall SW2of each opening OP3is 120 degrees to 140 degrees. With the formation of the solder resist layer110bhaving the openings OP3, the manufacturing cost is further reduced. Referring toFIG.14, in some embodiments, a plurality of conductive elements180bare formed on the bottom surfaces120bof the conductive pillars120and in the openings OP3. For example, the bottom surfaces120bof the conductive pillars120exposed by the solder resist layer110aare covered by the conductive elements180b. The formation and material of the conductive elements180bis similar to the formation and material of the conductive elements180adescribed inFIG.8, and thus are not repeated herein. In the disclosure, the conductive elements180bmay also be referred to as conductive terminals for electrical connection to external elements (e.g. an additional semiconductor package/device, a circuit substrate, etc.). As shown inFIG.14, the conductive elements180bare formed inside of the openings OP3and covered the surfaces120bof the conductive pillars120. That is, the conductive elements180bare rest at a first plane where the surface S3of the solder resist layer110alocated at and are protruding from the first plane towards a second plane where the surface S4located at. In some embodiments, after forming the conductive elements180b, the conductive elements172are released from the holding device HD to form the package structure10c. In some embodiments, a dicing (singulating) process is performed to cut a plurality of the package structures10cinterconnected therebetween into individual and separated package structures10cbefore releasing the conductive elements172from the holding device HD. In one embodiment, the dicing process is a wafer dicing process including mechanical blade sawing or laser cutting. Up to here, the manufacture of the package structure10cis completed. The package structure10cdepicted inFIG.14may be referred to as an integrated fan-out (semiconductor) package structure having dual-side terminals. In some alternative embodiments, the package structure10cmay be further mounted with a circuit substrate, an interposer, an additional package, chips/dies or other electronic devices to form a stacked package structure or a package on package (PoP) structure through the conductive elements172and/or other the conductive elements180bbased on the design layout and the demand. For example, the package structure10cofFIG.14is bonded to a semiconductor package800to form a package structure SP3, as shown inFIG.15. Referring toFIG.15, for the package structure SP3, the semiconductor package800is bonded to the semiconductor package structure10cdepicted inFIG.14by connecting the conductive elements870and the conductive elements180b(e.g. forming the joints300b), for example. In some embodiments, a portion of each of the joints300bis located in the openings OP3. In such embodiments, the semiconductor dies820a,820bof the semiconductor package800are electrically connected to the semiconductor die130of the package structure10cthrough the bonding wires830aand830b, the conductive pads840and850disposed on the substrate810, the joints300b(including the conductive elements870and180b), the conductive pillars120, and the redistribution circuit structure150. FIG.16is a schematic cross sectional view of a package structure in accordance with some embodiments of the disclosure.FIG.17is a schematic cross sectional view of a package structure in accordance with some embodiments of the disclosure. Referring toFIG.14andFIG.16together, the semiconductor package structure10cdepicted inFIG.14and a semiconductor package structure10ddepicted inFIG.16are similar, the difference is that an additional element, e.g. a redistribution circuit structures190, is further included in the semiconductor package structure10d. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, etc.) of the same elements would not be repeated herein. With the embodiments of which the redistribution circuit structure190is included, the redistribution circuit structure190is formed prior to the formation of the conductive pillars120and after the formation of the solder resist layer110b. The formation and material of the redistribution circuit structure190has been described inFIG.10, and thus are not repeating herein for simplicity. In some embodiments, the redistribution circuit structure190is located on the surface S3of the solder resist layer110band a bottom surface140bof the insulating encapsulation140. Similar to the redistribution circuit structure190of the package structure10bdescribed inFIG.10that providing routing function, for example, the redistribution circuit structure190is also referred to as a back-side redistribution layer of the semiconductor die130of the package structure10ddepicted inFIG.16. That is, the redistribution circuit structure190also provided routing function to the semiconductor die130with other conductive components inside the package structure10dsimilar to the redistribution circuit structure190of the package structure10b. In some alternative embodiments, the package structure10dmay be further mounted with a circuit substrate, an interposer, an additional package, chips/dies or other electronic devices to form a stacked package structure or a package on package (PoP) structure through the conductive elements172and/or other the conductive elements180bbased on the design layout and the demand. For example, the package structure10dofFIG.16is bonded to a semiconductor package800to form a package structure SP4, as shown inFIG.17. The detail of the semiconductor package800is described inFIG.9, and thus is not repeated herein. In some embodiments, as shown inFIG.17, for the package structure SP4, the semiconductor package800is bonded to the semiconductor package structure10ddepicted inFIG.16by connecting the conductive elements870and the conductive elements180b(e.g. forming the joints300b). In such embodiments, the semiconductor dies820a,820bof the semiconductor package800are electrically connected to the semiconductor die130of the package structure10dthrough the bonding wires830aand830b, the conductive pads840and850disposed on the substrate810, the joints300b(including the conductive elements870and180b), the redistribution circuit structure190, the conductive pillars120, and the redistribution circuit structure150. In accordance with some embodiments, a package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler. In accordance with some embodiments, a package structure includes a semiconductor die, an insulating encapsulation, a first redistribution circuit structure, and a solder resist layer. The semiconductor die has a front surface and a rear surface opposite to the front surface. The insulating encapsulation laterally encapsulates the semiconductor die. The first redistribution circuit structure is located on the front surface of the semiconductor die. The solder resist layer is located over the rear surface of the semiconductor die, wherein a material of the solder resist layer comprises a filler. In accordance with some embodiments, a method of manufacturing package structure includes the following steps, providing a carrier; forming a solder resist layer with a material comprising a filler on the carrier; disposing a semiconductor die and conductive pillars on the solder resist layer; encapsulating the semiconductor die and the conductive pillars in the insulating encapsulation; forming a first redistribution circuit structure on the insulating encapsulation; disposing first conductive element over the conductive pillars, the conductive pillars being between the first redistribution circuit structure and the first conductive elements; and disposing second conductive elements on the first redistribution circuit structure, the first redistribution circuit structure being between the insulating encapsulation and the second conductive elements. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure. | 66,047 |
11862595 | DETAILED DESCRIPTION The present disclosure is further explained in detail according to the accompanying drawings. It should be noted that the drawings are schematic representations of the embodiments, and not drawn to scale. The implementations of the present disclosure are described below through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific implementations, and various details in the specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. Referring toFIG.1toFIG.16, it should be noted that the drawings provided in this embodiment only exemplify the basic idea of the present disclosure. Therefore, only the components related to the present disclosure are shown in the drawings, and are not drawn according to the quantities, shapes, and sizes of the components during actual implementation. During actual implementation, the types, quantities, and proportions of the components may be adjusted as needed, and the layout of the components may be more complicated. As shown inFIG.1, in the existing fan-out wafer-level packaging (WLP) process, after plastic packaging is performed on semiconductor chips, the corresponding wafer100may warp. Therefore, follow-up packaging processes may face severe challenges. As shown inFIG.2, during formation of a dielectric layer of a redistribution layer, due to the warpage of the wafer, when photolithography is performed on the dielectric layer, the dielectric layer is unevenly heated and has inconsistent degrees of exposure and development. The topography of a via102formed in the dielectric layer after resist development may be deformed. For example, the dielectric layer around the vias may warp, causing poor contact between a subsequently formed redistribution layer and the chips, thereby affecting the yield of wafer packaging. In light of the foregoing problem, the present disclosure provides a packaging method for a fan-out WLP structure. The packaging method focuses on back-end processes that are carried out after plastic packaging is performed on the semiconductor chips. When the dielectric layer of the redistribution layer is formed, after the vias are formed in the dielectric layer by photolithography, the dielectric layer having the vias formed therein is baked and cured. Therefore, the topography of the dielectric layer around the vias can be effectively improved, and the warpage of the dielectric layer around the vias can be eliminated. In this way, electrical connectivity between the subsequently formed redistribution layer and the semiconductor chips can be improved, thereby increasing the yield of wafer packaging. As shown inFIG.3toFIG.16, the packaging method is described as follows. InFIG.3andFIG.4, step1) is first performed which provides more than two semiconductor chips200each having pads201. The semiconductor chips200may be semiconductor chips requiring packaging. The semiconductor chips may be chips with independent function such as storage chips and circuit chips, or may be integrated function chips such as APU chips and GPU chips, which are not limited herein. The pads201in each of the semiconductor chips200comprise aluminum element or its alloys. During preparation of making the pads201, in order to enhance the electrical properties of the pads and the adhesive properties of each semiconductor chip200, a bonding layer may be formed under the pads201, and an anti-reflection layer is formed on the surface of the pads201. As shown inFIG.3andFIG.4, then step2) of bonding the semiconductor chips200to a bonding layer202to form a fan-out wafer array203is performed. It should be noted that, based on requirements for packaging efficiency and package dimensions, there is generally a plurality of semiconductor chips200bonded to the fan-out wafer array203. In some cases, far more than a few semiconductor chips200are bonded. The quantity of pads201on one semiconductor chip200is not limited to 2, and the specific quantity may be set depending on the type of the semiconductor chips200. As shown inFIG.4, as an example, the semiconductor chips200are only bonded to the bonding layer202, so as to form the fan-out wafer array203. This kind of method incurs little cost, but with this method, warpage and drifting occur easily after subsequent plastic packaging. The bonding layer202may be made of materials such as an adhesive tape, UV adhesive formed by spin coating, or epoxy resin. In some embodiment, the bonding layer202is made of an UV adhesive layer formed by spin coating, and viscosity of the UV adhesive layer may decrease under ultraviolet irradiation. As shown inFIG.3, as an example, the bonding layer202is bonded to a support substrate214, so as to form the fan-out wafer array203. The support substrate214may be made of materials such as glass, ceramic, metal, and polymer. In some embodiment, the support substrate214comprises one of glass, transparent semiconductor materials, and transparent polymers, so that an exposure operation on the UV adhesive layer from a back side of the support substrate214can be performed, thereby greatly simplifying a subsequent peeling process. When the semiconductor chips200are bonded to the bonding layer202, the surfaces of the semiconductor chips200with the pads201are bonded to the bonding layer. After the bonding layer is subsequently removed and before the redistribution layer is formed, the semiconductor chips are inverted, so that the redistribution layer can be formed on the semiconductor chips. As shown inFIG.3andFIG.4, as an example, the fan-out wafer array203may be divided into more than two semiconductor chip units204, and it's defined that each of the semiconductor chips200has a respective initial position. The division is intended to provide a better method for forming the redistribution layer, and the method is to be described in detail below. It should be noted that, the quantity of semiconductor chips200in each of the semiconductor chip units204may be determined according to a maximum shifted distance of the semiconductor chips200in the semiconductor chip unit204after subsequent plastic packaging of the semiconductor chips. A quantity of semiconductor chip units204may be two or more. In this embodiment, for the convenience of understanding, semiconductor chips200arranged in a same row as shown in the figures constituting one semiconductor chip unit204. Therefore, only one semiconductor chip200of a semiconductor chip unit204is shown in the cross-sectional view. As an example, two semiconductor chip units204arranged in the above mentioned manner are used in the figures for illustration. As shown inFIG.5, step3) of packaging the semiconductor chips200by a plastic packaging layer205is then performed. The semiconductor chips200after plastic packaging may shift lateral locations. At this point, each of the semiconductor chips200has a respective shifted position, and the shifted position has a shift distance relative to the initial position. During plastic packaging, plastic packaging materials are heated to a liquid state at a high-temperature, and are pressed. Since all of the semiconductor chips200are re-bonded one by one to form a wafer array, warpage may occur under the pressure, and the semiconductor chips200may drift. That is, after plastic-packaging the semiconductor chips200, there is a shifted distance from the new position (i.e., shifted position) and the initial position of the semiconductor chip in the wafer array. In addition, since each of the semiconductor chips200is located at a different position in the wafer array, directions and degrees of shifting are different for the semiconductor chips200. Correspondingly, the pads on the semiconductor chips may also shift. As an example, the plastic packaging layer205comprises one of polyimide, silica gel, and epoxy resin. The plastic packaging layer205turns opaque after additives are added. As an example, processes for performing plastic packaging on the semiconductor chips200comprise one of an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing process, a vacuum lamination process, and a spin-coating process. In some embodiment, plastic packaging is performed on each of the semiconductor chips200by an injection molding process. The plastic packaging layer205is made of opaque silica gel. As shown inFIG.6toFIG.15, then step4) of removing the bonding layer202(as shown inFIG.6), and forming the redistribution layer208(as shown inFIG.15) on the semiconductor chips200, so as to achieve interconnection between the semiconductor chips200, is performed. The redistribution layer208comprises one or more redistribution sublayers213stacked in sequence. A method for forming each redistribution sublayer213comprises: forming a dielectric layer206on the semiconductor chips200(as shown inFIG.7); forming vias210in the dielectric layer206by photolithography (as shown inFIG.10andFIG.14); baking the dielectric layer206having the vias210formed therein, and eliminating warpage of the dielectric layer around the vias (as shown inFIG.11andFIG.12); curing the fan-out wafer array; and forming a patterned metal distribution layer212in the vias210and on the dielectric layer206, with the pattern of the patterned metal distribution layer corresponding to the layout of the vias210(as shown inFIG.13andFIG.15). The quantity of the redistribution sublayers213in the redistribution layer208is set according to specific packaging requirements. The quantity of the sublayers213may be one, two, three, or more. For example,FIG.15shows two layers. As shown inFIG.7toFIG.10, as a preferred example, a method for forming vias210in a first redistribution sublayer213(the redistribution sublayer that is in direct contact with the pads201of the corresponding semiconductor chip200) is shown. The method comprises: forming the dielectric layer206on the semiconductor chips200, and dividing the dielectric layer206into more than two to-be-etched dielectric layer units207(as shown inFIG.7), wherein the area of each to-be-etched dielectric layer unit207is defined by the above semiconductor chip units204; directly etching all of the to-be-etched dielectric layer units207by photolithography (as shown inFIG.8toFIG.10) one by one, so as to form, in the dielectric layer206, the vias210from which the pads201of the semiconductor chips200are exposed, wherein for etching of each to-be-etched dielectric layer unit207, the exposure stage position of photolithography is readjusted either by moving the exposure lithography tool stage toward the right, or alternating the mask209from opening at left to opening at right; as an example, a photomask209having a shielding structure is used so that the to-be-etched dielectric layer unit207on the left side is exposed (as shown inFIG.8), so as to form the vias210in the to-be-etched dielectric layer unit207on the left side, and the pads201on the semiconductor chip200in the semiconductor chip unit204on the left side is exposed by the vias210; and adjusting the relative orientations of the photomask209having the shielding structure and the to-be-etched dielectric layer unit207, and then exposing the dielectric layer206by the photomask209having the shielding structure (as shown inFIG.9), so as to form the vias210in the to-be-etched dielectric layer unit207on a right side, where the pads201on the semiconductor chip200in the semiconductor chip unit204on the right side is exposed by the vias210. The fan-out wafer array203is divided into a plurality of units to be exposed and etched. Etching and windowing are performed on each to-be-etched dielectric layer unit207in sequence, so as to form the vias from which the pads of a corresponding semiconductor chip are exposed. The photolithography is readjusted during each etching and windowing. That is to say, a single alignment exposure process is divided into a plurality of alignment exposure processes. The exposure stage position of each alignment exposure is adjusted according to shift distances and shift directions of the semiconductor chips of the to-be-etched unit for which the alignment exposure is performed, so that the alignment accuracy of the subsequently formed redistribution layer can be effectively improved because of the high-accuracy of the alignment exposure, thereby effectively increasing the yield of wafer packaging. When the fan-out wafer array203is formed by the bonding layer202and the support substrate214, the support substrate214is removed along with the bonding layer202. As shown inFIG.10, after the dielectric layer206is patterned by photolithography to form a patterned dielectric layer211, the vias210in the patterned dielectric layer211may warp due to plastic packaging of the fan-out wafer array203. The topography of the vias may also be deformed, which generates warpage (as shown inFIG.11, an enlarged view of a dashed box A inFIG.10). The dielectric layer having the vias formed therein is baked, so as to improve the deteriorated topography of the dielectric layer around the vias (as shown inFIG.12, an enlarged view of the dashed box A inFIG.10). In this way, the warped dielectric layer can be bonded to materials of a lower layer, and the restored topography of the dielectric layer can be shaped by means of curing, thereby effectively improving the electrical connectivity between the subsequently formed redistribution layer and the semiconductor chips, and increasing the yield of wafer packaging. In some embodiment, the dielectric layer206comprises one or more of PI and PBO. In some embodiment, the PI material is preferably selected as the material of the dielectric layer206, and the dielectric layer206is baked for 80-120 sat a temperature between 120° C. and 150° C., and then is cured for 110-130 min at a temperature between 220° C. and 260° C. In this way, the deteriorated topography of the dielectric layer around the vias can be effectively improved and cured. In some embodiment, the dielectric layer206is baked for 100 sat a temperature of 120° C. and cured for 120 min at a temperature of 240° C., so as to approximate an optimal effect of restoring the topography of the dielectric layer206around the vias. As shown inFIG.13andFIG.15, as an example, a metal distribution layer is formed in the vias210and on a surface of the patterned dielectric layer211by a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or a chemical plating process, and is etched to form a patterned metal distribution layer212. The metal distribution layer comprises one or more elements of copper, aluminum, nickel, gold, silver, and titanium. As shown inFIG.16, step5) of forming metal bumps215on the redistribution layer208is finally performed. As an example, each metal bump215comprises one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball. Alternatively, the metal bump215comprises a metal post and a solder ball formed on the metal post. Preferably, the metal post is a copper post or a nickel post. In some embodiment, the metal bump215is a gold-tin solder ball. A method for making the gold-tin solder ball comprises: first forming a gold-tin layer on a surface of the redistribution layer208, then causing the gold-tin layer to reflow to form a ball by a high-temperature reflow process, and forming the gold-tin solder ball by means of cooling; or forming the gold-tin solder ball by a bumping process. In summary, the present disclosure provides a packaging method for a fan-out WLP structure, and in the method, when forming the dielectric layer of the redistribution layer, after the vias are formed in the dielectric layer by photolithography, the dielectric layer having the vias formed therein is baked and cured, so that the topography of the dielectric layer around the vias can be effectively improved, and the warpage of the dielectric layer around the vias can be eliminated, thereby improving electrical connectivity between the subsequently formed redistribution layer and the semiconductor chips, and increasing the yield of wafer packaging. Therefore, the present disclosure effectively overcomes various disadvantages in the prior art, and has a high industrial value. The above embodiments only exemplarily illustrate the principles and effects of the present disclosure, but are not used to limit the invention. A person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person skilled in the art without departing from the spirit and technical idea of the present disclosure shall be covered by the claims of the present disclosure. | 17,139 |
11862596 | DETAILED DESCRIPTION OF EMBODIMENTS FIG.1Aillustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure.FIG.1Billustrates an enlarged view showing section I ofFIG.1A. Referring toFIGS.1A and1B, a semiconductor package11may include a redistribution substrate100and a semiconductor chip200. The redistribution substrate100may include a first redistribution pattern110, a second redistribution pattern120, a third redistribution pattern130, a first insulative pattern DP1, a second insulative pattern DP2, an under-bump pattern140, and dielectric layers101,102,103, and104. The dielectric layers101,102,103, and104may include a first dielectric layer101, a second dielectric layer102, a third dielectric layer103, and a fourth dielectric layer104that are vertically stacked. The redistribution substrate100may be called a wire structure. Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim). The semiconductor chip200may be mounted on the redistribution substrate100. The semiconductor chip200may include a chip pad205. The chip pad205may be exposed on a bottom surface of the semiconductor chip200. It will be appreciated that when an element is described to be connected, coupled or in contact with a chip pad, that element may be connected to the semiconductor chip as well as internal circuitry of the integrated circuit formed with the semiconductor chip. The first redistribution pattern110may be provided in the first dielectric layer101and the second dielectric layer102. For example, the first redistribution pattern110may include a first via part110V in the first dielectric layer101and a first wire part110W in the second dielectric layer102. The first redistribution pattern110may be in contact with the chip pad205. The first redistribution pattern110may electrically connect the chip pad205to the second redistribution pattern120which will be discussed below. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. The first dielectric layer101may include an organic material, such as a photosensitive polymer. In this description, the photosensitive polymer may include or may be formed of, for example, one or more of photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. The first dielectric layer101may be a positive photosensitive polymer, but the present inventive concepts are not limited thereto. The first via part110V may be provided in the first dielectric layer101. The first via part110V may penetrate the first dielectric layer101. For example, the first dielectric layer101may have a top surface coplanar with that of the first via part110V. The first dielectric layer101may cover a sidewall of the first via part110V. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. The first wire part110W may be provided on one surface of the first via part110V and may be connected to the first via part110V. The first wire part110W may be provided on one surface of the first dielectric layer101and may extend parallel to the one surface of the first dielectric layer101. The first wire part110W may have a thickness T1of about 3 μm to about 15 μm. The first via part110V may extend from the first wire part110W into the first dielectric layer101. The first redistribution pattern110may include a first seed pattern111and a first conductive layer113. The first conductive layer113may be provided on one surface of the first dielectric layer101and inside the first dielectric layer101. The first conductive layer113may include or may be formed of a metal, such as copper. The first seed pattern111may be interposed between the chip pad205and the first conductive layer113and between the first dielectric layer101and the first conductive layer113. The first seed pattern111may be in contact with the chip pad205. The first seed pattern111may include or may be formed of a conductive material, such as copper, titanium, or any alloy thereof. The first via part110V and the first wire part110W may each include the first seed pattern111and the first conductive layer113. The first seed pattern111of the first via part110V may be directly connected to the first seed pattern111of the first wire part110W, with no boundary therebetween. For example, a first portion of the first seed pattern111may be provided between the chip pad205and a top surface of the first conductive layer113included in the first via part110V, a second portion of the first seed pattern111may be provided between the first dielectric layer101and a sidewall of the first conductive layer113included in the first via part110V, and a third portion of the first seed pattern111may be provided between the first dielectric layer101and a top surface of the first conductive layer113included in the first wire part110W with no boundary between the first portion, the second portion, and the third portion of the first seed pattern111. The first seed pattern111may not extend onto a sidewall and a bottom surface of the first conductive layer113included in the first wire part110W. The first conductive layer113of the first via part110V may be directly connected to the first conductive layer113of the first wire part110W. A first recess region RR1may be provided in a portion of the first wire part110W that is located below the first via part110V of the first redistribution pattern110. The first recess region RR1may be recessed from the first wire part110W toward the first via part110V. The first recess region RR1may extend toward the first via part110V. The first recess region RR1may be defined by a portion of the bottom surface of the first via part110V and inclined inner walls of the first wire part110W. The first recess region RR1may have a tapered shape. For example, the first recess region RR1may have a width that gradually decreases as the first recess region RR1approaches the first via part110V from the first wire part110W. The first recess region RR1may expose the bottom surface of the first via part110V. The first recess region RR1may have one surface at substantially the same level as that of a bottom surface of the first dielectric layer101. For example, the first recess region RR1may have a top surface at substantially the same level as the bottom surface of the first dielectric layer101. In another example, the first recess region RR1may have a top surface at a different level from that of the bottom surface of the first dielectric layer101. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe relative positional relationships, such as illustrated in the figures, e.g. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. The first insulative pattern DP1may be provided in at least one first recess region RR1. The first insulative pattern DP1may contact the first via part110V, but may not contact the first wire part110W. In one embodiment, the first insulative pattern DP1may cover a portion of the bottom surface of the first via part110v. In another embodiment the first insulative pattern DP1may completely cover the bottom surface of the first via part110V. The first insulative pattern DP1may be spaced apart from the inclined inner walls of the first wire part110W that define the first recess region RR1. The first insulative pattern DP1may be located at substantially the same level as that of the first wire part110W. For example, a first surface DP1aof the first insulative pattern DP1may be substantially coplanar with a top surface of the third portion of the first seed pattern111and a second surface DP1bof the first insulative pattern DP1may be substantially coplanar with a bottom surface of the first wire part110W. insulative The first surface DP1aof the first insulative pattern DP1may be in contact with the first via part110V. The insulative second surface DP1bof the first insulative pattern DP1may be opposite to the first surface DP1a. The first insulative pattern DP1may have a first width W1at the first surface DP1aand a second width W2at the second surface DP1b. For example, the first width W1may be greater than the second width W2. In another example, not illustrated, the first width W1may be substantially the same as the second width W2. Therefore, the first insulative pattern DP1may be connected to the second dielectric layer102which will be discussed below, and thus it may be possible to prevent non-exposure of a bottom surface of the first redistribution pattern110. The first width W1may be a maximum width of the first insulative pattern DP1. The first width W1may range, for example, from about 10 μm to about 200 μm. The first insulative pattern DP1may include or may be formed of the same material as that of the first, second, third, and fourth dielectric layers101,102,103, and104. The first insulative pattern DP1may be patterned from the same insulative layer as the second dielectric layer102. The first insulative pattern DP1may be surrounded by the first redistribution pattern110and the second redistribution pattern120. The second insulative pattern DP2may be surrounded by the second redistribution pattern120and the third redistribution pattern130. The first insulative pattern DP1may be spaced apart with the second dielectric layer102. The second insulative pattern DP2may be spaced apart with the third dielectric layer103. The second dielectric layer102may be provided on one surface of the first dielectric layer101. For example, the second dielectric layer102may cover the bottom surface of the first dielectric layer101, and may also cover a bottom surface and a sidewall of the first wire part110W. The second dielectric layer102may be in contact with at least a portion of the bottom surface of the first conductive layer113. The second dielectric layer102may include or may be formed of, for example, a photosensitive polymer. The first and second dielectric layers101and102may have an indistinct boundary therebetween, but the present inventive concepts are not limited thereto. The second redistribution pattern120may be provided on and electrically connected to the first redistribution pattern110. The second redistribution pattern120may include a second wire part120W and a second via part120V. The second via part120V may be provided in the second dielectric layer102. The second wire part120W may be provided on the second via part120V and one surface of the second dielectric layer102. The second via part120V may be interposed between the first redistribution pattern110and the second wire part120W. The second wire part120W may be electrically connected to the second via part120V. The second wire part120W may have a thickness T2of about 3 μm to about 15 μm. The second via part120V may include a first body portion BP1that extends parallel to the second wire part120W, and may also include first protrusion portions PP1that extend from the first body portion BP1into the first recess region RR1. For example, the first body portion BP1may be in contact with at least a portion of the bottom surface of the first wire part110W. As such, the presence of the first insulative pattern DP1may reduce a depth of a second recess region RR2which will be discussed below, and may also reduce a resistance between the first and second redistribution patterns110and120. The second surface DP1bof the first insulative pattern DP1may be in contact with the first body portion BP1. The first protrusion portions PP1may be interposed between the first insulative pattern DP1and the first wire part110W of the first redistribution pattern110. The first protrusion portions PP1may be in contact with a sidewall of the first insulative pattern DP1. For example, the first insulative pattern DP1may be interposed between the first redistribution pattern110and the second redistribution pattern120. The first protrusion portions PP1may be in contact with the inclined inner walls of the first wire part110W. An interval between the first protrusion portions PP1may be substantially the same as the first width W1. The first protrusion portions PP1may be integrally formed with each other. The second redistribution pattern120may include a second seed pattern121and a second conductive layer123. For example, each of the second via part120V and the second wire part120W of the second redistribution pattern120may include the second seed pattern121and the second conductive layer123. The second seed pattern121of the second via part120V may be directly connected to the second seed pattern121of the second wire part120W, with no boundary therebetween. For example, a first portion of the second seed pattern121may be provided between the first redistribution pattern110and a top surface of the second conductive layer123included in the second via part120V, a second portion of the second seed pattern121may be provided between the second dielectric layer102and a sidewall of the second conductive layer123included in the second via part120V, and a third portion of the second seed pattern121may be provided between the second dielectric layer102and a top surface of the second conductive layer123included in the second wire part120W with no boundary between the first portion, the second portion, and the third portion of the second seed pattern121. In another example, a first portion of the second seed pattern121may be interposed between the second dielectric layer102and a top surface of the second wire part120W, a second portion of the second seed pattern121may be interposed between the second dielectric layer102and a sidewall of the first body portion BP1, a third portion of the second seed pattern121may be interposed between the first wire part110W and a top surface of the first body portion BP1, a fourth portion of the second seed pattern121may be interposed between the first protrusion portions PP1and inner walls of the first wire part110W, a fifth portion of the second seed pattern121may be interposed between the first protrusion portions PP1and the first insulative pattern DP1, and sixth portion of the second seed pattern121may be interposed between the first body portion BP1and the first insulative pattern DP1with no boundary between the first portion, the second portion, the third portion, the fourth portion, the fifth portion, and the sixth portion of the second seed pattern121. The second seed pattern121may not extend onto a sidewall and a bottom surface of the second conductive layer123included in the second wire part110W. The second conductive layer123of the second via part120V may be directly connected to the second conductive layer123of the second wire part120W. A second recess region RR2may be provided in a portion of the second wire part120W that is located below the second via part120V of the second redistribution pattern120. The second recess region RR2may be recessed from the second wire part120W toward the second via part120V. The second recess region RR2may extend toward the second via part120V. The second recess region RR2may be defined by a portion of the bottom surface of the second via part120V and inclined inner walls of the second wire part120W. The second recess region RR2corresponding to the second insulative pattern DP2may have a maximum width greater than that of the first recess region RR1. The second recess region RR2may have a tapered shape. For example, the second recess region RR2may have a width that gradually decreases as the second recess region RR2approaches the second via part120V from the second wire part120W. The second recess region RR2may expose the bottom surface of the second via part120V. The second recess region RR2may have one surface at substantially the same level as that of a bottom surface of the second dielectric layer102. For example, the second recess region RR2may have a top surface at substantially the same level as that of the bottom surface of the second dielectric layer102. In another example, the second recess region RR2may have a top surface at a different level from that of the bottom surface of the second dielectric layer102. The second insulative pattern DP2may be provided in at least one second recess region RR2. The second insulative pattern DP2may contact the second via part120V, but may not contact the second wire part120W. In one embodiment, the second insulative pattern DP2may cover a portion of the bottom surface of the second via part120V. In another embodiment, the second insulative pattern DP2may completely cover the bottom surface of the second via part120V. The second insulative pattern DP2may be spaced apart from the inclined inner walls of the second wire part120W that define the second recess region RR2. The second insulative pattern DP2may be located at substantially the same level as that of the second wire part120W. For example, a third surface DP2aof the second insulative pattern DP2may be substantially coplanar with a top surface of the second seed pattern121between the second dielectric layer102and the second wire part120W and a fourth surface DP2bof the second insulative pattern DP2may be substantially coplanar with a bottom surface of the second wire part120W. The insulative third surface DP2aof the second insulative pattern DP2may be in contact with the second via part120V. The insulative fourth surface DP2bof the second insulative pattern DP2may be opposite to the third surface DP2a. The second insulative pattern DP2may have a third width W3at the third surface DP2aand a fourth width W4at the fourth surface DP2b. For example, the third width W3may be greater than the fourth width W4. In another example, not illustrated, the third width W3may be substantially the same as the fourth width W4. Therefore, the second insulative pattern DP2may be connected to the third dielectric layer103which will be discussed below, and thus it may be possible to prevent non-exposure of a bottom surface of the second redistribution pattern120. The third width W3may be a maximum width of the second insulative pattern DP2. The third width W3may range, for example, from about 20 μm to about 400 μm. The first width W1may be less than the third width W3. The second insulative pattern DP2may include or may be formed of the same material as that of the first, second, third, and fourth dielectric layers101,102,103, and104. For example, the first and second insulative patterns DP1and DP2may have substantially the same thickness as each other. In another example, not illustrated, the first and second insulative patterns DP1and DP2may have different thicknesses from each other. The thickness of the first insulative pattern DP1may be defined as a vertical distance from the first surface DP1ato the second surface DP1b. The thickness of the second insulative pattern DP2may be defined as a vertical distance from the third surface DP2ato the fourth surface DP2b. The third dielectric layer103may be provided on one surface of the second dielectric layer102. For example, the third dielectric layer103may cover the bottom surface of the second dielectric layer102, and may also cover a bottom surface and a sidewall of the second wire part120W. The third dielectric layer103may include or may be formed of, for example, a photosensitive polymer. The second and third dielectric layers102and103may have an indistinct boundary therebetween, but the present inventive concepts are not limited thereto. The third redistribution pattern130may be provided on one surface of the second redistribution pattern120, and may be electrically connected to the second redistribution pattern120. The third redistribution pattern130may include a third wire part130W and a third via part130V. The third via part130V may be provided in the third dielectric layer103. The third wire part130W may be provided on the third via part130V and one surface of the third dielectric layer103. The third via part130V may be interposed between the second redistribution pattern120and the third wire part130W. The third wire part130W may be electrically connected to the third via part130V. The third wire part130W may have a thickness T3of about 3 μm to about 15 μm. The third via part130V may include a second body portion BP2that extends parallel to the third wire part130W, and may also include second protrusion portions PP2that extend from the second body portion BP2into the second recess region RR2. The second protrusion portions PP2may be interposed between the second insulative pattern DP2and the second wire part120W of the second redistribution pattern120. The second protrusion portions PP2may be in contact with a sidewall of the second insulative pattern DP2. For example, the second insulative pattern DP2may be interposed between the second redistribution pattern120and the third redistribution pattern130. The second protrusion portions PP2may be in contact with the inclined inner walls of the second wire part120W. An interval between the second protrusion portions PP2may be substantially the same as the third width W3. For example, the interval between the first protrusion portions PP1may be less than the interval between the second protrusion portions PP2. The second protrusion portions PP2may be integrally formed with each other. The third redistribution pattern130may include a third seed pattern131and a third conductive layer133. For example, each of the third via part130V and the third wire part130W of the third redistribution pattern130may include the third seed pattern131and the third conductive layer133. The third seed pattern131of the third via part130V may be directly connected to the third seed pattern131of the third wire part130W, with no boundary therebetween. For example, a first portion of the third seed pattern131may be interposed between the second redistribution pattern120and a top surface of the third conductive layer133included in the third via part130V, a second portion of the third seed pattern131may be interposed between the third dielectric layer103and a sidewall of the third conductive layer133included in the third via part130V, and a third portion of the third seed pattern131may be interposed between the third dielectric layer103and a top surface of the third conductive layer133included in the third wire part130W with no boundary between the first portion, the second portion, and the third portion of the third seed pattern131. In another example, a first portion of the third seed pattern131may be interposed between the third dielectric layer103and a top surface of the third wire part130W, a second portion of the third seed pattern131may be interposed between the third dielectric layer103and a sidewall of the second body portion BP2, a third portion of the third seed pattern131may be interposed between the second protrusion portions PP2and inner walls of the second wire part120W, a fourth portion of the third seed pattern131may be interposed between the second protrusion portions PP2and the second insulative pattern DP2, and a fifth portion of the third seed pattern131may be interposed between the second body portion BP2and the second insulative pattern DP2with no boundary between the first portion, the second portion, the third portion, the fourth portion, and the fifth portion of the third seed pattern131. The third seed pattern131may not extend onto a sidewall and a bottom surface of the third conductive layer133included in the third wire part130W. The third conductive layer133of the third via part130V may be directly connected to the third conductive layer133of the third wire part130W. A third recess region RR3may be provided in a portion of the third via part130V that is located below the third wire part130W of the third redistribution pattern130. The third recess region RR3may be recessed from the third wire part130W toward the third via part130V. The third recess region RR3may extend toward the third via part130V. The third recess region RR3may be defined by a bottom surface of the third via part130V and inclined inner walls of the third wire part130W. The third recess region RR3may have a tapered shape. For example, the third recess region RR3may have a width that gradually decreases as the third recess region RR3approaches the third via part130V from the third wire part130W. The third recess region RR3may expose the bottom surface of the third via part130V. The third recess region RR3may have one surface at substantially the same level as that of a bottom surface of the third dielectric layer103. For example, the third recess region RR3may have a top surface at substantially the same level as that of the bottom surface of the third dielectric layer103. In another example, the third recess region RR3may have a top surface at a different level from that of the bottom surface of the third dielectric layer103. The third recess region RR3may have a depth D1of about 3 μm to about 20 μm. The depth D1of the third recess region RR3may be defined as a vertical distance from a bottom surface of the third wire part130W to the bottom surface of the third via part130V. The second recess region RR2may have a depth that is defined as a vertical distance from the bottom surface of the second wire part120W to the bottom surface of the second via part120V. The first recess region RR1may have a depth that is defined as a vertical distance from the bottom surface of the first wire part110W to the bottom surface of the first via part110V. For example, the depths of the first, second, and third recess regions RR1, RR2, and RR3may be substantially the same as each other. A fifth width W5may be given as a minimum width of the third recess region RR3. For example, the fifth width W5may be less than the third width W3. Referring back toFIG.1B, the second via part120V may have a maximum width greater than that of the first via part110V and substantially the same as that of the third via part130V. In another example, not illustrated, the second via part120V may have a maximum width different from that of the third via part130V. A vertical alignment may be achieved between the first via part110V, the second via part120V, the third via part130V, the first insulative pattern DP1, and the second insulative pattern DP2. For example, the redistribution substrate100may have a stack via structure. As the redistribution substrate100has the vertically aligned via structure, it may be possible to reduce a circuit design time and to prevent electrical degradation such as signal loss. In addition, it may be possible to increase integration of the semiconductor package11. The fourth dielectric layer104may be provided on one surface of the third dielectric layer103. For example, the fourth dielectric layer104may cover at least portions of the sidewall and the bottom surface of the third wire part130W. The fourth dielectric layer104may include or may be formed of, for example, a photosensitive polymer. The third and fourth dielectric layers103and104may have an indistinct boundary therebetween, but the present inventive concepts are not limited thereto. The under-bump pattern140may be provided in the third recess region RR3and/or the fourth dielectric layer104. The under-bump pattern140may be coupled to the third redistribution pattern130. The under-bump pattern140may have a bottom surface that is partially or completed uncovered by the fourth dielectric layer104. The under-bump pattern140may serve as a pad for a conductive terminal400which will be discussed below. The under-bump pattern140may include or may be formed of a metallic material, such as copper. For example, the bottom surface of the under-bump pattern140may be coplanar with a bottom surface of the fourth dielectric layer104. The bottom surface of the under-bump pattern140may have a flat surface. A minimum width of the under-bump pattern140may be substantially the same as the fifth width W5. A conductive terminal400may be provided on a bottom surface of the redistribution substrate100. For example, the conductive terminal400may be disposed on the bottom surface of the under-bump pattern140, thereby being electrically connected to the under-bump pattern140. The conductive terminal400may be in contact with the under-bump pattern140. Therefore, the conductive terminal400may be electrically connected to the semiconductor chip200through the first, second, and third redistribution patterns110,120, and130. The conductive terminal400may include a solder, a bump, a pillar, or a combination thereof. The conductive terminal400may include or may be formed of a solder material. The semiconductor package11may further include a molding layer300. The molding layer300may be disposed on the redistribution substrate100, thereby covering the semiconductor chip200. The molding layer300may cover an uppermost one of the first, second, third, and fourth dielectric layer101,102,103, and104. For example, the first dielectric layer101may be the uppermost one of the first, second, third, and fourth dielectric layers101,102,103, and104. The molding layer300may include or may be formed of a dielectric polymer, such as an epoxy molding compound. FIG.1Cillustrates an enlarged view of section I depicted inFIG.1A, showing a semiconductor package according to a comparative example. A duplicate description will be omitted below. Referring toFIG.1C, as discussed with reference toFIGS.1A and1B, the redistribution substrate100may have a stack via structure. However, differently from that shown inFIG.1B,FIG.1Cdepicts an embodiment in which none of the insulative patterns DP1and DP2are provided in the recess regions RR1and RR2. In this case, the second and third recess regions RR2and RR3may each have a depth greater than that shown inFIGS.1A and1B. The third recess region RR3may have an increased depth D1′, and thus the under-bump pattern140may have a curved shape at the bottom surface thereof. Therefore, the conductive terminal400attached to the bottom surface of the under-bump pattern140may not be formed to have a spherical shape. The shape defect of the conductive terminal400may induce contact failure between the conductive terminal400and an external circuit. In this case, a semiconductor package may reduce in reliability. Referring back toFIGS.1A and1B, as the insulative patterns DP1and DP2are provided in the recess regions RR1and RR2, there may be a reduction in the depth D1of the third recess region RR3. Therefore, the conductive terminal400may be prevented from failure as discussed inFIG.1C, which may result in prevention of contact failure between the conductive terminal400and an external circuit. As a result, the semiconductor package11in accordance with the example ofFIG.1Bmay increase in reliability. FIGS.2A to2F,2H, and2Iillustrate cross-sectional views showing a method of fabricating a semiconductor package according to some example embodiments of the present disclosure.FIG.2Gillustrates an enlarged view showing section II ofFIG.2F. A duplicate description will be omitted below. Referring toFIG.2A, a semiconductor chip200and a molding layer300may be disposed on a carrier substrate900. One surface of the semiconductor chip200may face the carrier substrate900. A chip pad205may be provided on the one surface of the semiconductor chip200. The molding layer300may be formed on the carrier substrate900, thereby covering at least a portion of the semiconductor chip200. For example, the molding layer300may cover top and lateral surfaces of the semiconductor chip200. Differently from that shown, the molding layer300may cover the lateral surface of the semiconductor chip200, but may not cover or cover only a portion of the top surface of the semiconductor chip200. The carrier substrate900may be removed to expose a surface of each of the semiconductor chip200and the molding layer300. Afterwards, the semiconductor chip200and the molding layer300may be turned upside down. Referring toFIG.2B, a first dielectric layer101may be formed on the semiconductor chip200and the molding layer300. The first dielectric layer101may cover the exposed surface of each of the semiconductor chip200and the molding layer300. The formation of the first dielectric layer101may be performed by a coating process, such as spin coating or slit coating. The first dielectric layer101may include or may be formed of, for example, a photosensitive polymer. The photosensitive polymer may include or may be formed of, for example, one or more of photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. The first dielectric layer101may be patterned to form a first hole109in the first dielectric layer101. The patterning of the first dielectric layer101may be performed by exposure and development processes. The first hole109may expose a top surface of the chip pad205. The first hole109may have a tapered shape. For example, the first hole109may have a diameter or width that is greater at its upper portion than at its lower portion. In this case, the lower portion of the first hole109may be adjacent to the chip pad205. The first hole109may define an inner wall of the first dielectric layer101. As the first hole109has a tapered shape, an obtuse angle may be provided between the inner wall of the first dielectric layer101and the top surface of the chip pad205. The chip pad205and the first hole109may each be formed in plural. A first seed layer111P, a first resist pattern171, and first conductive layers113may be formed on a top surface of the first dielectric layer101. According to some example embodiments, the first seed layer111P may be formed on the first dielectric layer101and in the first holes109. The first seed layer111P may conformally cover the top surface of the first dielectric layer101, the inner wall of the first dielectric layer101, and the exposed top surface of the chip pad205. The first resist pattern171may be formed on the first seed layer111P. The formation of the first resist pattern171may include coating a photoresist material onto the first seed layer111P. The first resist pattern171may be patterned to form first openings. The patterning of the first resist pattern171may be performed by exposure and development processes. The first openings may vertically overlap corresponding first holes109. The first openings may have their widths greater than those of the corresponding first holes109. Alternatively, the first openings may have their lengths greater than those of the corresponding first holes109. Each of the first openings may have a sidewall substantially perpendicular to a bottom surface thereof. Each of the first openings may expose a portion of the first seed layer111P. The first conductive layers113may be formed in corresponding first holes109, thereby covering the first seed layer111P. The first conductive layers113may correspondingly fill lower portions of the first openings. For example, the first conductive layers113may fill the corresponding first holes109and may not extend onto a top surface of the first resist pattern171. The first conductive layers113may be formed by performing an electroplating process in which the first seed layer111P is used as an electrode. A planarization process may not be separately performed during the formation of the first conductive layers113. A first recess region RR1may be defined on each of the first conductive layers113. The first recess region RR1may extend toward the first hole109. The first recess region RR1may vertically overlap the chip pad205. The first recess region RR1may define an inner wall of the first conductive layer113. The first recess region RR1may have a width that is greater at its upper portion than at its lower portion. For example, the first recess region RR1may have a tapered shape. Referring toFIG.2C, the first resist pattern171may be removed to expose top surfaces of first segments of the first seed layer111P. A strip process may be performed to remove the first resist pattern171. Referring toFIG.2D, the exposed first segments of the first seed layer111P may be removed to form first seed patterns111. An etching process may be performed to remove the first segments from the first seed layer111P. A wet etching process may be adopted as the etching process. In the etching process, the first conductive layers113may have an etch selectivity with respect to the first seed layer111P. The first seed layer111P may have second segments that are disposed on bottom surfaces of the first conductive layers113and are not exposed to the etching process. After the etching process is terminated, the remaining second segments of the first seed layer111P may be formed into the first seed patterns111. Therefore, first redistribution patterns110may be formed. The first redistribution patterns110may be laterally spaced apart from each other. Each of the first redistribution patterns110may include a first seed pattern111and a first conductive layer113. The first conductive layers113may be disposed on corresponding first seed patterns111. Each of the first redistribution patterns110may include a first via part110V and a first wire part110W. The first via part110V may be provided in one of the first holes109. The first recess region RR1may be an area formed above the first via part110V and in a portion of the first wire part110W. The first recess region RR1may be recessed from the first wire part110W toward the first via part110V. Referring toFIG.2E, on the first dielectric layer101, a second dielectric layer102may be formed to cover the first dielectric layer101and the first redistribution patterns110. For example, the second dielectric layer102may cover top surfaces and sidewalls of the first redistribution patterns110. The second dielectric layer102may be patterned to form second holes108and first insulative patterns DP1. The first insulative pattern DP1may be provided in at least one first recess region RR1. For example, the first insulative pattern DP1may have at its top surface a width substantially the same as or less than a width at its bottom surface. A maximum width of the second hole108that corresponds to the first insulative pattern DP1may be greater than a maximum width of the second hole108that does not correspond to the first insulative pattern DP1. Therefore, the first insulative pattern DP1and the second dielectric layer102may be connected to prevent non-exposure of the top surface of the first redistribution pattern110. The second holes108may have tapered shapes. For example, each of the second holes108may expose a top surface of the first wire part110W. In another example, each of the second holes108may expose a top surface of the first wire part110W, and may also expose the first recess region RR1. Referring toFIG.2F, second redistribution patterns120may be formed in corresponding second holes108. The second redistribution patterns120may extend onto a top surface of the second dielectric layer102. The second redistribution patterns120may be laterally spaced apart from each other. The second redistribution patterns120may be formed by the same method as that used for forming the first redistribution patterns110. For example, the formation of the second redistribution patterns120may include forming a second seed layer, forming on the second seed layer a second resist pattern having second openings, forming second conductive layers123in the second holes108and the second openings, removing the second resist pattern to expose a portion of the second seed layer, and etching the exposed portion of the second seed layer to form second seed patterns121. Each of the second redistribution patterns120may include the second seed pattern121and the second conductive layer123. The second conductive layers123may be disposed on corresponding second seed patterns121. Each of the second redistribution patterns120may include a second via part120V and a second wire part120W. A second recess region RR2may be defined on each of the second redistribution patterns120. The second recess region RR2may extend toward the second hole108. The second recess region RR2may define an inner wall of the second wire part120W. The second recess region RR2may have a width that is greater at its upper portion than at its lower portion. The second recess region RR2may have a tapered shape. The second recess region RR2corresponding to the first insulative pattern DP1may have a maximum width greater than that of the first recess region RR1. The first insulative pattern DP1and the second redistribution pattern120will be further discussed in detail with reference toFIG.2G. The first insulative pattern DP1may have a first surface DP1ain contact with the first redistribution pattern110and a second surface DP1bopposite to the first surface DP1a. The first insulative pattern DP1may have a first width W1at the first surface DP1a. The first insulative pattern DP1may have a second width W2at the second surface DP1b. For example, the first width W1may be greater than the second width W2. In another example, not illustrated, the first width W1may be substantially the same as the second width W2. The first width W1may be a maximum width of the first insulative pattern DP1. The second via part120V may include a first body portion BP1that extends parallel to the second wire part120W, and may also include first protrusion portions PP1that extend from the first body portion BP1into the first recess region RR1. The first body portion BP1may be in contact with at least a portion of the top surface of the first wire part110W. The second surface DP1bof the first insulative pattern DP1may be in contact with the first body portion BP1. The first protrusion portions PP1may be interposed between the first insulative pattern DP1and the first wire part110W of the first redistribution pattern110. The first protrusion portions PP1may be in contact with a sidewall of the first insulative pattern DP1. For example, the first insulative pattern DP1may be interposed between the first redistribution pattern110and the second redistribution pattern120. The first protrusion portions PP1may be in contact with inclined inner walls of the first wire part110W. An interval between the first protrusion portions PP1may be substantially the same as the first width W1. A minimum width of the second recess region RR2may be substantially the same as a third width W3of a second insulative pattern DP2which will be discussed below. The first width W1may be less than the third width W3. The first protrusion portions PP1may be integrally formed with each other. Referring toFIG.2H, on the second dielectric layer102, a third dielectric layer103may be formed to cover the second dielectric layer102and the second redistribution patterns120. For example, the third dielectric layer103may cover top surfaces and sidewalls of the second redistribution patterns120. The third dielectric layer103may be patterned to form third holes107and second insulative patterns DP2. The second insulative pattern DP2may be provided in at least one second recess region RR2. For example, the second insulative pattern DP2may have at its top surface a width substantially the same as or less than a width at its bottom surface. A maximum width of the third hole107that corresponds to the second insulative pattern DP2may be greater than a maximum width of the third hole107that does not correspond to the second insulative pattern DP2. Therefore, the second insulative pattern DP2and the third dielectric layer103may be connected to prevent non-exposure of the top surface of the second redistribution pattern120. The third holes107may have tapered shapes. For example, each of the third holes107may expose a top surface of the second wire part120W. For another example, each of the third holes107may expose a top surface of the second wire part120W, and may also expose the second recess region RR2. Referring toFIG.2I, third redistribution patterns130may be formed in corresponding third holes107. The third redistribution patterns130may extend onto a top surface of the third dielectric layer103. The third redistribution patterns130may be laterally spaced apart from each other. The third redistribution patterns130may be formed by the same method as that used for forming the first redistribution patterns110. For example, the formation of the third redistribution patterns130may include forming a third seed layer, forming on the third seed layer a third resist pattern having third openings, forming third conductive layers133in the third holes107and the third openings, removing the third resist pattern to expose the third seed layer, and etching the exposed portion of the third seed layer to form third seed patterns131. Each of the third redistribution patterns130may include the third seed pattern131and the third conductive layer133. Each of the third redistribution patterns130may include a third via part130V and a third wire part130W. A third recess region RR3may be defined on each of the third redistribution patterns130. The third recess region RR3may extend toward the third hole107. The third recess region RR3may define an inner wall of the third wire part130W. The third recess region RR3may have a width that is greater at its upper portion than at its lower portion. The third recess region RR3may have a tapered shape. A maximum width of the third recess region RR3that corresponds to the second insulative pattern DP2may be less than a maximum width of the second recess region RR2that corresponds to the second insulative pattern DP2. Thereafter, on the third dielectric layer103, a fourth dielectric layer104may be formed to cover the third redistribution patterns130and the top surface of the third dielectric layer103. The fourth dielectric layer104may be formed by substantially the same method as that used for forming the first dielectric layer101. Under-bump patterns140may be formed on top surfaces of the third redistribution patterns130. The under-bump patterns140may fill the third recess regions RR3that correspond to the insulative patterns DP1and DP2. The fourth dielectric layer104may cover none of or only portions of top surfaces of the under-bump patterns140. For example, subsequent to forming the fourth dielectric layer104, all of or portions of top surfaces of the under-bump patterns140may be exposed. Conductive terminals400may be correspondingly formed on the exposed top surfaces of the under-bump patterns140. The formation of the conductive terminals400may include performing a solder-ball attaching process. A semiconductor package11may thus be fabricated. Referring back toFIGS.1A and1B, the semiconductor package11may be turned upside down. For example, the first surface DP1aof the first insulative pattern DP1may become a top surface, and the second surface DP1bof the first insulative pattern DP1may become a bottom surface. The third via part130V may include a second body portion BP2that extends parallel to the third wire part130W, and may also include second protrusion portions PP2that extend from the second body portion BP2into the second recess region RR2. The second protrusion portions PP2may be interposed between the second insulative pattern DP2and the second wire part120W of the second redistribution pattern120. The second protrusion portions PP2may be in contact with a sidewall of the second insulative pattern DP2. For example, the second insulative pattern DP2may be interposed between the second redistribution pattern120and the third redistribution pattern130. The second protrusion portions PP2may be in contact with inclined inner walls of the second wire part120W. An interval between the second protrusion portions PP2may be substantially the same as a third width W3which will be discussed below. For example, the interval between the first protrusion portions PP1may be less than the interval between the second protrusion portions PP2. The second protrusion portions PP2may be integrally formed with each other. The second insulative pattern DP2may have a third surface DP2ain contact with the second via part120V. The second insulative pattern DP2may have a fourth surface DP2bopposite to the third surface DP2a. The second insulative pattern DP2may have a third width W3at the third surface DP2aand a fourth width W4at the fourth surface DP2b. For example, the third width W3may be greater than the fourth width W4. In another example, not illustrated, the third width W3may be substantially the same as the fourth width W4. The third width W3may range, for example, from about 20 μm to about 400 μm. The first width W1may be less than the third width W3. A fifth width W5may be given as a minimum width of the third recess region RR3. The fifth width W5may be given as a minimum width of the under-bump pattern140. For example, the fifth width W5may be less than the third width W3. FIG.3illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure. A duplicate description will be omitted below. Referring toFIG.3, a semiconductor package11amay include the redistribution substrate100and the semiconductor chip200. Unlike the semiconductor package11ofFIG.3F, the molding layer300may be omitted. The semiconductor chip200may have a width Wa substantially the same as a width Wb of the redistribution substrate100. For example, according to some example embodiments of the present disclosure, the semiconductor package11amay be a fan-in semiconductor package. The formation of the redistribution substrate100may be substantially the same as that discussed above with reference toFIGS.2A to2I. FIGS.4A to4Dillustrate cross-sectional views showing a method of fabricating a semiconductor package according to some example embodiments of the present disclosure. Referring toFIG.4A, a first dielectric layer101may be formed on a carrier substrate900. The first dielectric layer101may cover one surface of the carrier substrate900. The formation of the first dielectric layer101may be performed by a coating process, such as spin coating or slit coating. The first dielectric layer101may include or may be formed of, for example, a photosensitive polymer. The photosensitive polymer may include or may be formed of, for example, one or more of photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. The first dielectric layer101may be patterned to form a first hole109in the first dielectric layer101. The patterning of the first dielectric layer101may be performed by exposure and development processes. The first hole109may have a tapered shape. For example, the first hole109may have a diameter or width that is greater at its upper portion than at its lower portion. The first hole109may define an inner wall of the first dielectric layer101. As the first hole109has a tapered shape, an obtuse angle may be provided between the inner wall of the first dielectric layer101and the one surface of the carrier substrate900. The first hole109may be formed in plural. A first seed layer111P, a first resist pattern171, and first conductive layers113may be formed on a top surface of the first dielectric layer101. According to some example embodiments, the first seed layer111P may be formed on the first dielectric layer101and in the first holes109. The first seed layer111P may conformally cover the top surface of the first dielectric layer101, the inner wall of the first dielectric layer101, and an exposed top surface of the carrier substrate900. The first resist pattern171may be formed on the first seed layer111P. The formation of the first resist pattern171may include coating a photoresist material onto the first seed layer111P. The first resist pattern171may be patterned to form first openings. The patterning of the first resist pattern171may be performed by exposure and development processes. The first openings may vertically overlap corresponding first holes109. The first openings may have their widths greater than those of the corresponding first holes109. Alternatively, the first openings may have their lengths greater than those of the corresponding first holes109. Each of the first openings may have a sidewall substantially perpendicular to a bottom surface thereof. Each of the first openings may expose a portion of the first seed layer111P. The first conductive layers113may be formed in corresponding first holes109, covering the first seed layer111P. The first conductive layers113may correspondingly fill lower portions of the first openings. For example, the first conductive layers113may fill the corresponding first holes109, and may not extend onto a top surface of the first resist pattern171. The first conductive layers113may be formed by performing an electroplating process in which the first seed layer111P is used as an electrode. A planarization process may not be separately performed during the formation of the first conductive layers113. A first recess region RR1may be defined on each of the first conductive layers113. The first recess region RR1may extend toward the first hole109. The first recess region RR1may vertically overlap the first hole109. The first recess region RR1may define an inner wall of the first conductive layer113. The first recess region RR1may have a width that is greater at its upper portion than at its lower portion. The first recess region RR1may have a tapered shape. Referring toFIG.4B, the carrier substrate900may be provided thereon with a first redistribution pattern110, a second redistribution pattern120, a third redistribution pattern130, a first insulative pattern DP1, a second insulative pattern DP2, a second dielectric layer102, a third dielectric layer103, and a fourth dielectric layer104. The first redistribution pattern110, the second redistribution pattern120, the third redistribution pattern130, the first insulative pattern DP1, the second insulative pattern DP2, the second dielectric layer102, the third dielectric layer103, and the fourth dielectric layer104may be formed by using methods substantially the same as those discussed with reference toFIGS.2A to2I. Bonding pads150may be formed in the fourth dielectric layer104. The bonding pads150may be formed on top surfaces of the third redistribution patterns130. The bonding pads150may fill the third recess regions RR3that correspond to the insulative patterns DP1and DP2. The fourth dielectric layer104may cover none of or only portions of the top surfaces of bonding pads150. For example, all of or portions of the top surfaces of bonding pads150may be exposed. At least one bonding pad150may be vertically aligned with the first and second insulative patterns DP1and DP2. Referring toFIG.4C, a semiconductor chip200may be prepared which has a plurality of chip pads205. The semiconductor chip200may be disposed on the fourth dielectric layer104so as to align the chip pads205with the bonding pads150. A plurality of bonding terminals250may be formed between the semiconductor chip200and the redistribution substrate100. The bonding terminals250may be correspondingly coupled to the chip pads205and the bonding pads150. A molding layer300may be formed on the fourth dielectric layer104, thereby encapsulating the semiconductor chip200. The molding layer300may further extend into a gap between the fourth dielectric layer104and the semiconductor chip200, thereby encapsulating the bonding terminals250. The carrier substrate900may be removed from the first dielectric layer101. Therefore, the first dielectric layer101may be exposed at its bottom surface, and the first redistribution patterns110may be exposed at their bottom surfaces. Referring toFIG.4D, under-bump patterns140may be formed on the bottom surface of the first redistribution pattern110. The under-bump patterns140may be coupled to the exposed first via part110V of the first redistribution pattern110. Conductive terminals400may be correspondingly formed on bottom surfaces of the under-bump patterns140. The formation of the conductive terminals400may include performing a solder-ball attaching process. A semiconductor package11bmay thus be fabricated. The following will discuss a single semiconductor package for brevity of description, but methods of fabricating semiconductor packages are not limited to chip-level fabrication. For example, semiconductor packages may be fabricated at a chip, panel, or wafer level. FIG.5illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure. A duplicate description will be omitted below. Referring toFIG.5, a semiconductor package12may include a lower semiconductor package20and an upper semiconductor package22. The lower semiconductor package20may include a redistribution substrate100, a conductive terminal400, a first semiconductor chip210A, a second semiconductor chip220A, a molding layer300, and a conductive structure520. The redistribution substrate100, the conductive terminal400, and the molding layer300may be substantially the same as those discussed with reference toFIGS.1A and1B. The second semiconductor chip220A may be laterally spaced apart from the first semiconductor chip210A. The second semiconductor chip220A may be of a different type from the first semiconductor chip210A. For example, the first semiconductor chip210A may include one of a logic chip, a memory chip, and a power management chip, and the second semiconductor chip220A may include another of a logic chip, a memory chip, and a power management chip. The logic chip may include an applicant specific integrated circuit (ASIC) chip or an application processor (AP) chip. The ASIC chip may include an application specific integrated circuit (ASIC). The power management chip may include a power management integrated circuit (PMIC). For example, the first semiconductor chip210A may be an ASIC chip, and the second semiconductor chip220A may be a power management chip. Each of the first and second semiconductor chips210A and220A may be similar to the semiconductor chip200discussed with reference toFIGS.1A and1B. Differently from that shown, the second semiconductor chip220A may be omitted. In another example, a third semiconductor chip may further be mounted on a top surface of the redistribution substrate100. Chip pads215A of the first semiconductor chip210A and chip pads225A of the second semiconductor chip220A may be electrically connected through first redistribution patterns110to the redistribution substrate100. Therefore, the second semiconductor chip220A may be electrically connected through the redistribution substrate100to the first semiconductor chip210A. The conductive structure520may be disposed on the top surface of the redistribution substrate100. The conductive structure520may be electrically connected through a bonding pad150to the first redistribution pattern110. The conductive structure520may be laterally spaced apart from the first and second semiconductor chips210A and220A. When viewed in plan view, the conductive structure520may be provided on an edge of the redistribution substrate100. A metal pillar may be provided on the redistribution substrate100, forming the conductive structure520. For example, the conductive structure520may be the metal pillar. The conductive structure520may be electrically connected to the redistribution substrate100. For example, the conductive structure520may be electrically connected through the redistribution substrate100to the first semiconductor chip210A, the second semiconductor chip220A, or the conductive terminal400. The conductive structure520may include or may be formed of a metal, such as copper. The molding layer300may be provided on the top surface of the redistribution substrate100and may cover the first and second semiconductor chips210A and220A. The molding layer300may surround sidewalls of the conductive structure520. The molding layer300may be provided between the first and second semiconductor chips210A and220A, between the first semiconductor chip210A and the conductive structure520, and between the second semiconductor chip220A and the conductive structure520. The molding layer300may cover none of or only portions of a top surface520aof the conductive structure520. For example, subsequent to providing the molding layer300, all of or portions of top surface520aof the conductive structure520may be exposed. The lower semiconductor package20may further include an upper redistribution layer600. The upper redistribution layer600may be provided on a top surface of the molding layer300. The upper redistribution layer600may include upper dielectric patterns610, upper redistribution patterns620, and upper bonding pads640. The upper dielectric patterns610may be stacked on the molding layer300. The upper dielectric patterns610may include or may be formed of a photosensitive polymer. Each of the upper redistribution patterns620may include a via part in the upper dielectric pattern610and a wire part between the upper dielectric patterns610. The upper redistribution patterns620may include or may be formed of a metal, such as copper. At least one of the upper redistribution patterns620may be in contact with the top surface520aof the conductive structure520. Therefore, the upper redistribution patterns620may be coupled to the conductive structure520. The upper bonding pad640may be disposed on an uppermost one of the upper dielectric patterns610, and may be coupled to the upper redistribution patterns620. The upper bonding pad640may be electrically connected through the upper redistribution patterns620and the conductive structure520to the conductive terminal400, the first semiconductor chip210A, or the second semiconductor chip220A. The presence of the upper redistribution patterns620may allow the upper bonding pad640to not vertically align with the conductive structure520. The upper semiconductor package22may be disposed on the lower semiconductor package20. For example, the upper semiconductor package22may be placed on the upper redistribution layer600. The upper semiconductor package22may include an upper substrate710, an upper semiconductor chip720, and an upper molding layer730. The upper substrate710may be a printed circuit board. Alternatively, the upper substrate710may be a redistribution layer. For example, the upper substrate710may be manufactured by an example for fabricating the redistribution substrate100discussed with reference to FIGS.2A to2I. A first connection pad701and a second connection pad702may be respectively disposed on a bottom surface and a top surface of the upper substrate710. The upper substrate710may be provided therein with a wiring line703coupled to the first and second connection pads701and702. The wiring line703is schematically illustrated and may be variously changed in shape and arrangement. The first connection pad701, the second connection pad702, and the wiring line703may include or may be formed of a conductive material, such as metal. The upper semiconductor chip720may be disposed on the upper substrate710. The upper semiconductor chip720may include integrated circuits (not shown), which integrated circuits may include a memory circuit, a logic circuit, or a combination thereof. The upper semiconductor chip720may be of a different type from the first and second semiconductor chips210A and220A. For example, the upper semiconductor chip720may be a memory chip. A bump terminal715may be interposed between the upper substrate710and the upper semiconductor chip720, and may be coupled to the second connection pad702and a chip pad725of the upper semiconductor chip720. The upper semiconductor chip720may be electrically connected to the first connection pad701through the bump terminal715and the wiring line703. Differently from that shown, the bump terminal715may be omitted, and the chip pad725may be directly coupled to the second connection pad702. The upper substrate710may be provided thereon with the upper molding layer730that covers the upper semiconductor chip720. The upper molding layer730may include or may be formed of a dielectric polymer, such as an epoxy-based polymer. The upper semiconductor package22may further include a thermal radiation structure780. The thermal radiation structure780may include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The thermal radiation structure780may include or may be formed of, for example, metal. The thermal radiation structure780may be disposed on a top surface of the upper molding layer730. The thermal radiation structure780may further extend onto a sidewall of the upper molding layer730or a sidewall of the molding layer300. The semiconductor package12may further include a connection terminal650. The connection terminal650may be interposed between and coupled to the upper bonding pad640and the first connection pad701. In such a configuration, the upper semiconductor package22may be electrically connected through the connection terminal650to the first semiconductor chip210A, the second semiconductor chip220A, and the conductive terminal400. The electrical connection of the upper semiconductor package22may mean an electrical connection with integrated circuits in the upper semiconductor chip720. In another example, the upper substrate710may be omitted, and the connection terminal650may be directly coupled to the chip pad725of the upper semiconductor chip720. In this case, the upper molding layer730may be in contact with a top surface of the upper redistribution layer600. Alternatively, the upper substrate710and the connection terminal650may be omitted, and the chip pad725of the upper semiconductor chip720may be directly coupled to the upper bonding pad640. FIG.6Aillustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure.FIG.6Billustrates an enlarged view showing section III ofFIG.6A. A duplicate description will be omitted below. Referring toFIGS.6A and6B, a semiconductor package13may include a lower semiconductor package21and an upper semiconductor package22. The lower semiconductor package21may include a redistribution substrate100, a conductive terminal400, a first semiconductor chip210A, a second semiconductor chip220A, a molding layer300, and a connection substrate500. The redistribution substrate100, the conductive terminal400, and the molding layer300may be substantially the same as those discussed with reference toFIGS.1A and1B. The first semiconductor chip210A and the second semiconductor chip220A may be substantially the same as the first semiconductor chip210A and the second semiconductor chip220A discussed inFIG.5. The connection substrate500may be disposed on the redistribution substrate100. The connection substrate500may have a substrate hole590that penetrates therethrough. For example, the substrate hole590may be formed to penetrate top and bottom surfaces of a printed circuit board, and thus the connection substrate500may be fabricated. When viewed in plan, the substrate hole590may be formed on a central portion of the redistribution substrate100. The first and second semiconductor chips210A and220A may be disposed in the substrate hole590of the connection substrate500. The first and second semiconductor chips210A and220A may be spaced apart from an inner wall of the connection substrate500. The connection substrate500may include a base layer510and a conductive structure520′. The base layer510may include a plurality of stacked base layers. The stacked base layers510may include a dielectric material. For example, the stacked base layers510may include or may be formed of a carbon-based material, a ceramic, or a polymer. The substrate hole590may penetrate the stacked base layers510. The conductive structure520′ may be provided in the stacked base layers510. The conductive structure520′ may include a first pad521, a conductive line523, vias524, and a second pad522. The first pad521may be exposed on a bottom surface500bof the connection substrate500. The conductive line523may be interposed between the stacked base layers510. The vias524may penetrate the stacked base layers510and may be coupled to the conductive line523. The second pad522may be exposed on a top surface500aof the connection substrate500and may be coupled to one of the vias524. The second pad522may be electrically connected to the first pad521through the vias524and the conductive line523. The second pad522may not be vertically aligned with the first pad521. The number of second pads522may be different from the number of first pads521. The conductive structure520′ may include metal. The conductive structure520′ may include, for example, at least one selected from copper, aluminum, tungsten, titanium, tantalum, iron, and any alloy thereof. The molding layer300may be provided on the first semiconductor chip210A, the second semiconductor chip220A, and the connection substrate500. The molding layer300may be interposed between the first semiconductor chip210A and the second semiconductor chip220A, between the first semiconductor chip210A and the connection substrate500, and between the second semiconductor chip220A and the connection substrate500. According to some example embodiments, an adhesive dielectric film may be attached to a top surface of the connection substrate500, top surfaces of the first and second semiconductor chips210A and220A, and sidewalls of the first and second semiconductor chips210A and220A, thereby forming the molding layer300. For example, an ajinomoto build-up film (ABF) may be used as the adhesive dielectric film. For another example, the molding layer300may include a dielectric polymer, such as an epoxy-based polymer. The lower semiconductor package21may further include an upper redistribution layer600. The upper redistribution layer600may be disposed on the molding layer300and the connection substrate500. The upper redistribution layer600may include upper dielectric patterns610, upper redistribution patterns620, and upper bonding pads640. The upper dielectric patterns610, the upper redistribution patterns620, and the upper bonding pads640may be substantially the same as those discussed above in the example ofFIG.5. In contrast, at least one of the upper redistribution patterns620may extend into the molding layer300, and may thus be coupled to the second pad522. The upper semiconductor package22may be disposed on the lower semiconductor package21. For example, the upper semiconductor package22may be placed on the upper redistribution layer600. The upper semiconductor package22may include an upper substrate710, an upper semiconductor chip720, and an upper molding layer730. The upper semiconductor package22and the connection terminal650may be substantially the same as those discussed inFIG.4. For example, the connection terminal650may be interposed between the lower semiconductor package21and the upper semiconductor package22. The upper semiconductor package22may further include a thermal radiation structure780. According to the present disclosure, insulative patterns may be interposed between redistribution patterns. Therefore, there may be a reduction in depth of a region where the redistribution patterns are recessed. Accordingly, it may be possible to prevent failure of a conductive terminal that electrically connects a redistribution substrate to an external circuit. In conclusion, the redistribution substrate and a semiconductor package including the same may exhibit increased reliability. Although the present inventive concepts have been described in connection with example embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and essential feature of the present inventive concepts. The above disclosed embodiments should thus be considered illustrative and not restrictive. | 73,500 |
11862597 | Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described herein in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, this application is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure of the present application as defined by the appended claims. DETAILED DESCRIPTION OF EMBODIMENTS The present disclosure is directed to a substrate for a system-on-chip (SoC) package that has an asymmetrical build-up from a core (or core layers) of the substrate and methods for making such a substrate. Many current SoC package substrates have symmetric build-up (or stackup) of layers in both directions from the core layers of the substrates. For instance, the substrates have the same number of layers on the frontside (e.g., layers above the core) and the backside (e.g., layers below the core) of the substrate. The symmetric build-up of layers is due to the requirements for the build-up process during substrate manufacturing. For instance, many current SoC package substrate manufacturing equipment requires layers to be built-up in both directions (symmetrically) from the core or core layers because of the design of the equipment. In a symmetric stackup SoC package substrate, however, most of the routings for device connections are made in the frontside layers of the substrate with only a few simple routings being made in the backside layers. Thus, much of the backside layers contribute additional material cost without providing any technological benefit in the SoC package substrate (e.g., many layers have no technical impact on operation of the SoC). The present disclosure contemplates removing many of the backside layers of the SoC package substrate in an asymmetric stackup structure for the substrate. Embodiments contemplated herein may help increase output of SoC package substrates using existing manufacturing equipment, thus not requiring significant additional new capital investment. Additionally, the embodiments contemplated herein may reduce the cost of manufacturing SoC package substrates by reducing the number of layers in the substrates, thereby reducing material usage per package. One embodiment disclosed herein has three broad elements: 1) a substrate core having a plurality of core layers built-up where the substrate core has a first recess in a top core layer and a second recess in a bottom core layer, 2) a first integrated passive device positioned in the first recess and a second integrated passive device positioned in the second recess, and 3) a plurality of build-up layers positioned on the top core layer of the substrate core with at least one via path through the build-up layers and the substrate core. In some embodiments, the at least one via path connects a conductive contact positioned on a lower surface of the substrate core to an upper surface of the build-up layers. For example, the via path may include a first via through the substrate core connected to a second via through the build-up layers. In certain embodiments, the via path includes a conductive contact on an upper surface of the substrate core that connects the first via to the second via. In various embodiments, an upper surface of the first integrated passive device in is at substantially a same height as (e.g., flush with) an upper surface of the first conductive contact. Similarly, wherein a lower surface of the second integrated passive device may be at substantially a same height as a lower surface of the second conductive contact. In certain embodiments, the package substrate does not include build-up layers below the substrate core (e.g., the backside layers) that are symmetrical with the build-up layers above the substrate core (e.g., the frontside layers). Accordingly, the package substrate may be termed to be “asymmetric”. While the package substrate may be asymmetric with respect to the build-up layers, any number of layers may be added below the substrate core as needed for a particular implementation of the package substrate, as described herein. For instance, the number of backside layers may be varied based on routing or power integrity needs of a package that includes the package substrate. In short, the present inventors have recognized that an asymmetric package substrate can be generated to reduce the use of materials in the package. Additionally, the present inventors have recognized that an asymmetric package substrate can be made without significant changes to existing manufacturing equipment, thus reducing the need for new capital investment. The present inventors have also recognized that manufacturing methods for the asymmetric package substrates may be implemented that increase the production output of package substrates versus the production of symmetric package substrates. For instance, manufacturing methods may be implemented that produce two asymmetric package substrates in a process flow versus one symmetric package substrate. FIG.1depicts a side-view cross-sectional representation of an embodiment of a package substrate. In the illustrated embodiment, package substrate100includes substrate core102and build-up layers104. Substrate core102may include insulating material106. Insulating material106may include, for example, resin material, fiber material, glass material, other electrically insulating materials, or combinations thereof. In various embodiments, insulating material106includes multiple layers of insulating material that are integrated to form substrate core102. For instance, multiple layers of insulating material laminated or otherwise built-up or stacked in the vertical dimension ofFIG.1to form insulating material106. The number of layers in insulating material106may vary based on, for example, desired mechanical or electrical properties of substrate core102. In the illustrated embodiment, insulating material106includes four insulating material layers (e.g., substrate core102is a 4-layer core). In certain embodiments, substrate core102includes one or more conductive material layers108. Conductive material layers108may include, for example, copper layers. The number and position of conductive material layers108in substrate core102may be varied based on design considerations for the mechanical or electrical properties of substrate core102. In the illustrated embodiment, substrate core102includes two conductive material layers—an upper conductive material layer near the upper surface of the substrate core and a lower conductive material layer near the lower surface of the substrate core. Intermediate conductive material layers may be positioned in substrate core102to provide additional routing in the substrate core. In various embodiments, one or more vias110are formed through insulating material106and conductive material108in substrate core102. Vias110may include conductive material (such as copper) to provide conductive pathways through substrate core102. In some embodiments, vias110are substantially vertical vias through substrate core102. Other embodiments may, however, be contemplated where vias110include one or more non-vertical connections (e.g., zig-zagged vias). In the illustrated embodiment, vias110include via walls110A and via fill110B. Via walls110A may include, for example, conductive material (such as copper) while via fill110B includes insulating material (such as resin or fiber material). Thus, via walls110A provide a conductive path through substrate core102. In certain embodiments, one or more conductive contacts112are positioned on the upper surface of substrate core102and the lower surface of substrate core102. Conductive contacts112may be copper contacts or another suitable electrically conductive material. Conductive contacts112may be implemented to provide electrical connections to vias110on the upper and lower surfaces of substrate core102. In various embodiments, substrate core102includes insulating layers114on the upper and lower surfaces of the substrate core. Insulating layers114may include, for example, ABF or other insulating materials. Insulating layers114may encapsulate or surround conductive contacts112, as shown inFIG.1. In some embodiments, conductive contacts116are positioned on the upper and lower surfaces of insulating layers114. Conductive contacts116may connect through insulating layers114to conductive contacts112to provide electrical connections on the upper and lower surfaces of the insulating layers. In the illustrated embodiment, substrate core102includes recesses118in the upper and lower surfaces of insulating material106. In some embodiments, recesses118extend down to conductive material108in substrate core102, as shown inFIG.1. In other embodiments, recesses118may extend to other depths in substrate core102(such as other layers of conductive material in the substrate core). In certain embodiments, integrated passive devices (IPDs)120are positioned in recesses118. IPDs120may include, for example, pluralities of passive devices (such as capacitors or inductors) that are formed or integrated on a substrate (such as a semiconductor substrate). In the illustrated embodiment, IPDs120are positioned on and mechanically coupled to portions of conductive material108exposed in recesses118. In some contemplated embodiments, IPDs120may be electrically coupled to conductive material108(such as for routing connections to the IPDs). Discussion of the relative heights of IPDs120and conductive contacts112is found below in the description for the embodiment of substrate core102depictedFIG.9. In some embodiments, conductive contacts116are formed to conductive contacts122of IPDs120. Conductive contacts122are contacts formed on the upper/lower surfaces of IPDs120. Conductive contacts122may be, for example, copper contacts made to connections for passive devices on IPDs120. Conductive contacts116may be formed through insulating layers114and connect to conductive contacts122to provide electrical connection areas for the passive devices on IPDs120above/below the insulating layers114. Turning now to build-up layers104, in the illustrated embodiment, the build-up layers include insulating material124and conductive material126. Insulating material124may include, for example, resin material, fiber material, glass material, other electrically insulating materials, or combinations thereof. Conductive material126may include, for example, copper or another electrically conductive material. In various embodiments, build-up layers104include multiple layers of insulating material124and multiple layers of conductive material126that are built-up (stacked) to form the build-up layers. The number of layers of insulating material124and conductive material126may vary based on, for example, desired mechanical or electrical properties of build-up layers104and package substrate100. In various embodiments, build-up layers104enclose (e.g., encapsulate) IPD120in recess118. In some embodiments, build-up layers104enclose insulating layer114, which encloses IPD120. In various embodiments, layers of conductive material126are connected by vias128. Vias128may be, for example, copper vias. Vias128may be formed through layers of insulating material124to provide electrical connections between the various layers of conductive material126. Together, conductive material126and vias128provide electrical routing in build-up layers104. Conductive material126and vias128may provide electrical routing through build-up layers104with insulating material providing electrical insulation between the different routings of conductive material126and vias128. In certain embodiments, build-up layers104include conductive material126and vias128routed to IPDs120, as illustrated inFIG.1. In the illustrated embodiment, frontside layer130is positioned over build-up layers104. Frontside layer130may be, for example, a surface finish layer or other finishing layer. In certain embodiments, frontside layer130includes insulating layer132and conductive contacts134through the insulating layer. Insulating layer132may be, for example, a dielectric material such as ABF or solder resist. Conductive contacts134may be metal bumps or pads such as C4 bump pads or solder bumps. In some contemplated embodiments, conductive contacts134are plated contacts (e.g., contacts formed by ENIG (Electroless Nickel Immersion Gold) plating or ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) plating). In various embodiments, as illustrated inFIG.1, conductive contacts134connect to conductive material126and vias128while extending above the upper surface of insulating layer132to provide electrical connections to the conductive material126and vias128. Turning back to substrate core102, in certain embodiments, backside layer136is positioned on the lower surface of the substrate core. Backside layer136may include, for example, fiber, resist, or resin insulating materials such as ABF or solder resist. In various embodiments, backside layer136is a layer used as an adhesive layer between substrate core102and a carrier substrate that remains after the carrier substrate is removed, as described below. In the illustrated embodiment, backside layer136includes openings138to expose conductive contacts116through the backside layer. Accordingly, openings138allow electrical connections to be made to conductive contacts116. Openings138may be formed through various methods, as described herein. The thickness of backside layer136may also vary based on the manufacturing method implemented or the design of package substrate100, as described herein. In the illustrated embodiment ofFIG.1, package substrate100is an asymmetric package substrate with multiple build-up layers104positioned above substrate core102and backside layer136positioned below the substrate core. While the illustrated embodiment of package substrate100depicts backside layer136as a single layer, it should be understood that package substrate100may include any number of backside layers depending on the routing or power requirements of the package substrate. The ability to vary the number of backside layers, however, is advantageous over symmetric package substrate designs that are required to have the same number of build-up layers on the frontside and the backside of substrate core102(due to requirements for the build-up process during substrate manufacturing). For instance, in the illustrated embodiment, the backside of substrate core102may have any number of backside layers136without affecting the structure or number of build-up layers104on the frontside of the substrate core. Accordingly, the structure of package substrate100may be flexible to accommodate different design, assembly, or yield considerations. As described herein, substrate core102in package substrate100, shown inFIG.1, is a core with multiple layers (e.g., a 4-layer core). The presence of a multiple layer, thicker substrate core102in package substrate100may reduce warpage in the package substrate. Additionally, substrate core102may have a lower coefficient of thermal expansion than cores that have cavities or other openings through the core. The implementation of recesses118in substrate core102for coupling IPDs120to the substrate core may also allow the thickness of the substrate core to be determined regardless of the thickness of the IPDs, and vice versa. For instance, substrate core102may have any thickness compared to IPDs120as long as recesses118can be deep enough to allow the IPDs to be flush with the contacts on the surfaces of the substrate core (e.g., conductive contacts112). The ability to have two IPDs120coupled to substrate core102may also increase the density of IPDs in package substrate100. For instance, package substrate100, shown inFIG.1, may have double the IPD density for the same core area as other typical package substrates. Example manufacturing processes for providing the asymmetric structure of package substrate100will now be discussed in more detail. Example Fabrication Methods for Package Substrate100 FIGS.2-8depict various steps in embodiments of a fabrication method for package substrate100.FIG.2depicts a side-view cross-sectional representation of an embodiment of substrate cores being coupled to a carrier substrate. InFIG.2, substrate cores102A,102B with IPDs120positioned in recesses118are coupled to carrier substrate200. Carrier substrate200may be any substrate capable of mechanically supporting substrate cores102A,102B through various processing steps. In various embodiments, carrier substrate200is coupled to substrate cores102A,102B using backside layers136A,136B. Backside layers136A,136B may be, for example, fiber or resin layers such as ABF layers that can function as adhesive layers between substrate cores102A,102B and carrier substrate200. In some embodiments, carrier substrate200and backside layers136A,136B are laminated to substrate cores102A,102B. In certain embodiments, substrate core102A and substrate core102B are coupled to carrier substrate200with the substrate cores mirroring each other, as shown inFIG.2. For instance, substrate core102A is coupled in an upright (normal) orientation to the upper surface of carrier substrate200with backside layer136A while substrate core102B is coupled in an upside-down orientation to the lower surface of the carrier substrate with backside layer136B. FIG.3depicts a side-view cross-sectional representation of an embodiment of build-up layers formed on substrate cores coupled to the carrier substrate. InFIG.3, build-up layer104A is formed on substrate core102A and build-up layer104B is formed on substrate core102B. In certain embodiments, build-up layers104A,104B are formed simultaneously on substrate cores102A,102B. For instance, as described above, typical build-up processes form build-up layers on both the frontside and backside of devices simultaneously. Thus, having the two substrate cores102A,102B coupled to carrier substrate200and mirroring each other allows the build-up process to form build-up layers104A,104B simultaneously on the two substrate cores. For instance, build-up layer104A is formed on the “frontside” of carrier substrate200and build-up layer104B is formed simultaneously on the “backside” of carrier substrate200. FIG.4depicts a side-view cross-sectional representation of an embodiment of carrier substrate200detached (e.g., removed) from substrate core102A and substrate core102B. After removing carrier substrate200, backside layer136A remains coupled to substrate core102A and backside layer136B remains coupled to the substrate core102B. With carrier substrate200removed, two package substrates (e.g., first package substrate100A and second package substrate100B) are formed by the corresponding substrate cores and build-up layers, as shown inFIG.4. Accordingly, a single build-up process step is able to form two package substrates—substrate core102A with build-up layer104A forming first package substrate100A and substrate core102B with build-up layer104B forming second package substrate100B. Forming two package substrates (e.g., first package substrate100A and second package substrate100B) using a similar build-up process to that used for forming a single package substrate with build-up layers on both the frontside and backside of the core may increase the throughput in producing the package substrates (e.g., two package substrates are formed instead of one package substrate). FIGS.5-8depict examples of further processing steps on a package substrate after carrier substrate200is removed to form first package substrate100A and second package substrate100B. For simplicity in the drawings, these further processing steps are described with reference to package substrate100. Accordingly, the additional processing described in reference to package substrate100may be implemented for either first package substrate100A or second package substrate100B, shown inFIG.4. FIG.5depicts a side-view cross-sectional representation of an embodiment of openings formed to conductive contacts in a package substrate. In certain embodiments, openings138are formed to conductive contacts116through backside layer136. In illustrated embodiment, openings138are formed by patterning and selective removal of material from backside layer136to form the openings (e.g., patterning using a resist and an etch process for selective removal). FIG.6depicts a side-view cross-sectional representation of an alternative embodiment of openings formed to conductive contacts in a package substrate. In the illustrated embodiment, openings138are formed by thinning backside layer136down to a height of conductive contacts116. Thinning backside layer136may include, for example, planarization of the backside layer or other known techniques. In various embodiments, surface finishes may be formed after openings138to conductive contacts116are formed. Surface finishes may include, but not be limited to, adding additional conductive contacts or adding insulating layers on package substrate100.FIG.7depicts a side-view cross-sectional representation of an embodiment of surface finishes on a package substrate. In certain embodiments, the surface finishes inFIG.7are implemented on the embodiment of package substrate100shown inFIG.5. Additional embodiments, however, may be contemplated where the surface finishes inFIG.7are implemented on other embodiments of a package substrate (such as package substrate100shown inFIG.6). The embodiment of package substrate100depicted inFIG.7may be similar in structure to the embodiment of package substrate100depicted inFIG.1. In the illustrated embodiment ofFIG.7, frontside layer130, which includes insulating layer132and conductive contacts134through the insulating layer, is formed on the upper surface (in the illustration) of build-up layers104. In certain embodiments, insulating layer132is a solder resist layer and conductive contacts134include a combination of conductive materials. For instance, conductive contacts134may include a combination of plated contacts (e.g., contacts formed by ENIG or ENEPIG) formed on build-up layers104and ball contacts (e.g., solder ball contacts) formed on top of the plated contacts. FIG.8depicts a side-view cross-sectional representation of an alternative embodiment of surface finishes on a package substrate. In certain embodiments, the surface finishes inFIG.8are implemented on the embodiment of package substrate100shown inFIG.6. Additional embodiments, however, may be contemplated where the surface finishes inFIG.8are implemented on other embodiments of a package substrate (such as package substrate100shown inFIG.5). As shown inFIG.8, insulating layer132and conductive contacts134are formed on the frontside of build-up layers104, thus forming frontside layer130. In the illustrated embodiment, conductive contacts134in frontside layer130are plated contacts in insulating layer132and the insulating layer is thinned (e.g., planarized) to expose the conductive contacts. Additionally, the backside of package substrate100(e.g., the lower surface of substrate core102) includes conductive contacts116exposed through backside layer136by openings138. As backside layer136, shown inFIG.8, is relatively thin and at the same height as conductive contacts116, in some embodiments, an additional backside layer (e.g., backside layer800) is formed over backside layer136with openings138extending through the additional backside layer. As described herein, the process step examples depicted inFIGS.2-8provide various embodiments for producing two package substrates using a single carrier substrate. Producing two package substrates from a single carrier substrate increases the output quantity of package substrates from the single carrier substrate. It should be understood that additional package substrates may be formed from a single carrier substrate during some processing techniques. For instance, a single carrier substrate may be capable of supporting multiple substrate cores on a single side of the carrier substrate (such as in side-by-side positioning). Accordingly, the process step examples depicted inFIGS.2-8may double the output quantity of package substrates from any carrier substrate, thereby increasing the throughput for producing package substrates. Example Fabrication Method for Substrate Core102with IPD120 FIG.9depicts a side-view cross-sectional representation of various steps in an embodiment of a fabrication method for substrate core102. In step (a), insulating material106is provided with layers of conductive material108along with vias110formed between conductive contacts112. In the illustrated embodiment, insulating material106is a four-layer insulating material. The thickness of insulating material106may, however, vary depending on desired properties of substrate core102. In step (b), recesses118are formed in the upper and lower surfaces of insulating material106. In certain embodiments, recesses118are formed to a depth of the upper and lower layers of conductive material108. Recesses118may be formed by, for example, laser cavity etching of insulating material106. In various embodiments, the depth of recesses118and conductive material108may be predetermined by a height (thickness) of IPDs120that are to be positioned in the recesses. In certain embodiments, recesses118and conductive material108have a depth such that when IPDs120are positioned in the recesses, upper/lower surfaces121of the IPDs have heights that are similar as heights of conductive contacts112. For instance, the distances of upper/lower surfaces121of IPDs120from the upper/lower surfaces of insulating material106is substantially the same as the distances of the upper/lower surfaces of conductive contacts112from the upper/lower surfaces of insulating material106. Accordingly, upper/lower surfaces121of IPDs120may be considered to be substantially flush with the upper/lower surfaces of conductive contacts112. While upper/lower surfaces121are at similar heights to the upper/lower surfaces of conductive contacts112, there may be some small variations in the heights, as shown inFIGS.1and9. Such surfaces may still be considered to be flush in terms of the design of package substrate100. These small differences in height may be caused, for example, by manufacturing variations. After IPDs120are positioned in recesses118, insulating layers114and conductive contacts116through the insulating layers may be formed, as shown in step (c). Forming insulating layers114may include, for example, lamination or other insulating material deposition techniques. Either laser etching or resist patterning and etching may be used to form openings through insulating layers114to conductive contacts112and/or conductive contacts122. The openings may then be filled with conductive material (e.g., metal) to form conductive contacts116. Substrate core102, shown in step (c) ofFIG.9, may be the result of formation of insulating layers114and conductive contacts116. Substrate core102may then be further processed as described herein (e.g., coupling to carrier substrate200and formation of build-up layers104, as shown inFIGS.2-8). Exemplary Embodiments With Coreless Substrate In Package Substrate In various embodiments, package substrate100may include a coreless substrate rather than a substrate core (e.g., substrate core102is replaced with a coreless substrate).FIG.10depicts a side-view cross-sectional representation of various steps in an embodiment of a fabrication method for coreless substrate1000. In step (a), the formation of coreless substrate1000begins with insulating material1006. Insulating material1006may include insulating materials such as, but not limited to, resin material, fiber material, glass material, other electrically insulating materials, or combinations thereof. Conductive material1008is then positioned (e.g., formed) in insulating material1006. Conductive materials1008may include, but not be limited to, copper material or copper alloy material. In various embodiments, conductive materials1008on the upper/lower surfaces of insulating material1006may form conductive contacts112. With insulating material1006and core material1008in place, in step (b), recess118is formed in the upper surface of insulating material1006. Recess118may be formed by, for example, laser cavity etching of insulating material1006. After recess118is formed, IPD120may be positioned in the recess. It should be noted that due to the relatively small thickness of coreless substrate1000(e.g., insulating material1006), that typically only one recess118and one IPD120may be placed in the coreless substrate. Embodiments of thicker coreless substrates with two recesses and two IPDs may, however, be contemplated. After IPD120is positioned in recess118, in step (c), coreless substrate build-up layers1004may be formed on the upper and lower surfaces of insulating material1006. Build-up layers1004may be formed similarly to build-up layers104, as described herein. For instance, build-up layers1004may include insulating material124with conductive material126and vias128positioned in the insulating material. Additionally, conductive contacts122may be coupled to IPD120. Conductive contacts122and/or conductive contacts112may be connected to conductive contacts116on build-up layers1004(e.g., using conductive material126and vias128). In various embodiments, build-up layers1004include multiple layers of insulating material124and multiple layers of conductive material126that are built-up (stacked) to form the build-up layers. In one contemplated embodiment, build-up layers1004include two layers of insulating material and conductive material126. Other numbers of layers, however, may be contemplated for coreless substrate1000. In various embodiments, build-up layers1004enclose (e.g., encapsulate) IPD120in recess118. Coreless substrate1000, shown inFIG.10, may then be further processed to form a package substrate. For instance, coreless substrate1000may be processed similarly to the process for forming a package substrate from substrate core102, as shown inFIGS.2-8. In various embodiments, two coreless substrates1000are processed using a carrier substrate (e.g., carrier substrate200) with the formation of build-up layers104on both coreless substrates simultaneously, as shown inFIGS.2and3. FIG.11depicts a side-view cross-sectional representation of an embodiment of package substrate100′ with coreless substrate1000. In the illustrated embodiment, build-up layers104are formed on the upper surface of coreless substrate1000. For instance, build-up layers104are formed on the upper surface of coreless build-up layers1004. Build-up layers104in package substrate100′ may be formed similarly to the build-up layers in package substrate100, shown inFIG.1. For instance, build-up layers104may include insulating material124and conductive material126. Insulating material124in build-up layers104may be the same insulating material as used in coreless build-up layers1004. In various embodiments, build-up layers104include multiple layers of insulating material124and multiple layers of conductive material126that are built-up (stacked) to form the build-up layers. As described above, the number of layers of insulating material124and conductive material126may vary based on, for example, desired mechanical or electrical properties of build-up layers104and package substrate100′. In various embodiments, as described herein, layers of conductive material126may be connected by vias128(e.g., copper vias). In the illustrated embodiment, frontside layer130is positioned over build-up layers104. Frontside layer130may be, for example, a surface finish layer or other finishing layer. In certain embodiments, frontside layer130includes insulating layer132and conductive contacts134through the insulating layer. In various embodiments, backside layer136is positioned on the lower surface of the coreless substrate1000(e.g., on the lower surface of coreless build-up layers1004). Backside layer136may be a layer used as an adhesive layer between coreless substrate1000and a carrier substrate that remains after the carrier substrate is removed, as described herein. In the illustrated embodiment, backside layer136includes openings138to expose conductive contacts116through the backside layer. In the illustrated embodiment ofFIG.11, package substrate100′ is an asymmetric package substrate with multiple build-up layers104positioned above coreless substrate1000and backside layer136positioned below the coreless substrate with intervening coreless build-up layers1004. Package substrate100′ may include any number of backside layers136and intervening coreless build-up layers1004depending on the routing or power requirements of the package substrate. The ability to vary the number of backside layers and intervening coreless build-up layers1004, however, is advantageous over symmetric package substrate designs that are required to have the same number of build-up layers on the frontside and the backside of a substrate (due to requirements for the build-up process during substrate manufacturing). For instance, in the illustrated embodiment, the backside of coreless substrate1000may have any number of backside layers136and intervening coreless build-up layers1004without affecting the structure or number of build-up layers104on the frontside of the substrate core. Accordingly, the structure of package substrate100′ may be flexible to accommodate different design, assembly, or yield considerations. Example Fabrication Method FIG.12is a flow diagram illustrating a method1200of fabrication for package substrate100, according to some embodiments. At1202, in the illustrated embodiment, a first recess is formed in an upper surface of a substrate core having multiple insulating layers built-up in a vertical dimension with at least one conductive material layer positioned in the insulating layers. At1204, in the illustrated embodiment, a second recess is formed in a lower surface of the substrate core in the vertical dimension. At1206, in the illustrated embodiment, a first integrated passive device is positioned in the first recess. In some embodiments, the first integrated passive device is coupled to the at least one conductive material layer exposed in the first recess. At1208, in the illustrated embodiment, a second integrated passive device is positioned in the second recess. At1210, in the illustrated embodiment, a plurality of build-up layers is formed on the upper surface of the substrate core. In some embodiments, at least one insulating layer is formed on the lower surface of the substrate core. The at least one insulating layer may be patterned to expose the second conductive contact through the single insulating layer. At1212, in the illustrated embodiment, at least one via path is formed through the build-up layers and the substrate core where the at least one via path connects a second conductive contact positioned on the lower surface of the substrate core to an upper surface of the build-up layers. In some embodiments, forming the at least one via path includes forming a via through the build-up layers that connects to a via through the substrate core. Example Computer System Turning next toFIG.13, a block diagram of one embodiment of a system1300is shown that may incorporate and/or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system1300includes at least one instance of a system on chip (SoC)1306which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, a communication fabric, and interfaces to memories and input/output devices. In some embodiments, one or more processors in SoC1306includes multiple execution lanes and an instruction issue queue similar to processor NNN (of FIG. N) and processor NNN (of FIG. N). In various embodiments, SoC1306is coupled to external memory1302, peripherals1304, and power supply1308. A power supply1308is also provided which supplies the supply voltages to SoC1306as well as one or more supply voltages to the memory1302and/or the peripherals1304. In various embodiments, power supply1308represents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, more than one instance of SoC1306is included (and more than one external memory1302is included as well). The memory1302is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such as mDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with a SoC or an integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration. The peripherals1304include any desired circuitry, depending on the type of system1300. For example, in one embodiment, peripherals1304includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripherals1304also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals1304include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. As illustrated, system1300is shown to have application in a wide range of areas. For example, system1300may be utilized as part of the chips, circuitry, components, etc., of a desktop computer1310, laptop computer1320, tablet computer1330, cellular or mobile phone1340, or television1350(or set-top box coupled to a television). Also illustrated is a smartwatch and health monitoring device1360. In some embodiments, smartwatch may include a variety of general-purpose computing related functions. For example, smartwatch may provide access to email, cellphone service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health related functionality. For example, a health monitoring device may monitor a user's vital signs, track proximity of a user to other users for the purpose of epidemiological social distancing, contact tracing, provide communication to an emergency service in the event of a health crisis, and so on. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring related functions. Other wearable devices are contemplated as well, such as devices worn around the neck, devices that are implantable in the human body, glasses designed to provide an augmented and/or virtual reality experience, and so on. System1300may further be used as part of a cloud-based service(s)1370. For example, the previously mentioned devices, and/or other devices, may access computing resources in the cloud (i.e., remotely located hardware and/or software resources). Still further, system1300may be utilized in one or more devices of a home other than those previously mentioned. For example, appliances within the home may monitor and detect conditions that warrant attention. For example, various devices within the home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a repair facility) should a particular event be detected. Alternatively, a thermostat may monitor the temperature in the home and may automate adjustments to a heating/cooling system based on a history of responses to various conditions by the homeowner. Also illustrated inFIG.13is the application of system1300to various modes of transportation. For example, system1300may be used in the control and/or entertainment systems of aircraft, trains, buses, cars for hire, private automobiles, waterborne vessels from private boats to cruise liners, scooters (for rent or owned), and so on. In various cases, system1300may be used to provide automated guidance (e.g., self-driving vehicles), general systems control, and otherwise. These any many other embodiments are possible and are contemplated. It is noted that the devices and applications illustrated inFIG.13are illustrative only and are not intended to be limiting. Other devices are possible and are contemplated. The present disclosure includes references to “an “embodiment” or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments will necessarily manifest any or all of the potential advantages. Whether an advantage is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why an implementation that falls within the scope of the claims might not exhibit some or all of any disclosed advantages. For example, a particular implementation might include other circuitry outside the scope of the disclosure that, in conjunction with one of the disclosed embodiments, negates or diminishes one or more the disclosed advantages. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation techniques or tools) could also negate or diminish disclosed advantages. Even assuming a skilled implementation, realization of advantages may still depend upon other factors such as the environmental circumstances in which the implementation is deployed. For example, inputs supplied to a particular implementation may prevent one or more problems addressed in this disclosure from arising on a particular occasion, with the result that the benefit of its solution may not be realized. Given the existence of possible factors external to this disclosure, it is expressly intended that any potential advantages described herein are not to be construed as claim limitations that must be met to demonstrate infringement. Rather, identification of such potential advantages is intended to illustrate the type(s) of improvement available to designers having the benefit of this disclosure. That such advantages are described permissively (e.g., stating that a particular advantage “may arise”) is not intended to convey doubt about whether such advantages can in fact be realized, but rather to recognize the technical reality that realization of such advantages often depends on additional factors. Unless stated otherwise, embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims that are drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative rather than restrictive, absent any statements in the disclosure to the contrary. The application is thus intended to permit claims covering disclosed embodiments, as well as such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure. For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims that depend from other independent claims. Similarly, features from respective independent claims may be combined where appropriate. Accordingly, while the appended dependent claims may be drafted such that each depends on a single other claim, additional dependencies are also contemplated. Any combinations of features in the dependent that are consistent with this disclosure are contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically enumerated in the appended claims. Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims of another format or statutory type (e.g., method). Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Public notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how to interpret claims that are drafted based on this disclosure. References to a singular form of an item (i.e., a noun or noun phrase preceded by “a,” “an,” or “the”) are, unless context clearly dictates otherwise, intended to mean “one or more.” Reference to “an item” in a claim thus does not, without accompanying context, preclude additional instances of the item. A “plurality” of items refers to a set of two or more of the items. The word “may” is used herein in a permissive sense (i.e., having the potential to, being able to) and not in a mandatory sense (i.e., must). The terms “comprising” and “including,” and forms thereof, are open-ended and mean “including, but not limited to.” When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense. A recitation of “w, x, y, or z, or any combination thereof” or “at least one of . . . w, x, y, and z” is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrasings cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “at least one of . . . w, x, y, and z” thus refers to at least one element of the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase is not to be interpreted to require that there is at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z. Various “labels” may precede nouns or noun phrases in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, the labels “first,” “second,” and “third” when applied to a feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. The phrase “based on” or is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.” The phrases “in response to” and “responsive to” describe one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect, either jointly with the specified factors or independent from the specified factors. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A, or that triggers a particular result for A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase also does not foreclose that performing A may be jointly in response to B and C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B. As used herein, the phrase “responsive to” is synonymous with the phrase “responsive at least in part to.” Similarly, the phrase “in response to” is synonymous with the phrase “at least in part in response to.” Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. Thus, an entity described or recited as being “configured to” perform some task refers to something physical, such as a device, circuit, a system having a processor unit and a memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible. In some cases, various units/circuits/components may be described herein as performing a set of task or operations. It is understood that those entities are “configured to” perform those tasks operations, even if not specifically noted. The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform a particular function. This unprogrammed FPGA may be “configurable to” perform that function, however. After appropriate programming, the FPGA may then be said to be “configured to” perform the particular function. For purposes of United States patent applications based on this disclosure, reciting in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution of a United States patent application based on this disclosure, it will recite claim elements using the “means for” [performing a function] construct. Different “circuits” may be described in this disclosure. These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random-access memory), programmable logic arrays, and so on. Circuitry may be custom designed, or taken from standard libraries. In various implementations, circuitry can, as appropriate, include digital components, analog components, or a combination of both. Certain types of circuits may be commonly referred to as “units” (e.g., a decode unit, an arithmetic logic unit (ALU), functional unit, memory management unit (MMU), etc.). Such units also refer to circuits or circuitry. The disclosed circuits/units/components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many instances, the internal arrangement of hardware elements within a particular circuit may be specified by describing the function of that circuit. For example, a particular “decode unit” may be described as performing the function of “processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units,” which means that the decode unit is “configured to” perform this function. This specification of function is sufficient, to those skilled in the computer arts, to connote a set of possible structures for the circuit. In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements defined by the functions or operations that they are configured to implement, The arrangement and such circuits/units/components with respect to each other and the manner in which they interact form a microarchitectural definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition is recognized by those of skill in the art as structure from which many physical implementations may be derived, all of which fall into the broader structure described by the microarchitectural definition. That is, a skilled artisan presented with the microarchitectural definition supplied in accordance with this disclosure may, without undue experimentation and with the application of ordinary skill, implement the structure by coding the description of the circuits/units/components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a fashion that may appear to be functional. But to those of skill in the art in this field, this HDL description is the manner that is used transform the structure of a circuit, unit, or component to the next level of implementational detail. Such an HDL description may take the form of behavioral code (which is typically not synthesizable), register transfer language (RTL) code (which, in contrast to behavioral code, is typically synthesizable), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may subsequently be synthesized against a library of cells designed for a given integrated circuit fabrication technology, and may be modified for timing, power, and other reasons to result in a final design database that is transmitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof may also be custom-designed in a schematic editor and captured into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnect between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized to a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of these circuits commonly results in the scenario in which the circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuit is configured to do, as this process is performed at a different stage of the circuit implementation process. The fact that many different low-level combinations of circuit elements may be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations may vary according to changes in the fabrication technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methodologies to produce these different implementations may be arbitrary. Moreover, it is common for a single implementation of a particular functional specification of a circuit to include, for a given embodiment, a large number of devices (e.g., millions of transistors). Accordingly, the sheer volume of this information makes it impractical to provide a full recitation of the low-level structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes structure of circuits using the functional shorthand commonly employed in the industry. | 58,055 |
11862598 | DETAILED DESCRIPTION Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments. A semiconductor device of the present disclosure and a method of manufacturing the semiconductor device will be now described with reference to the drawings. In the following, the same or similar elements will be denoted by the same reference numerals, and explanation thereof will not be repeated. In the present disclosure, phases “a certain thing A is formed in another certain thing B” and “a certain thing A is formed on another certain thing B” include, unless otherwise specified, “a certain thing A is directly formed in another certain thing B” and “a certain thing A is formed on another certain thing B with other thing interposed between the certain thing A and the another thing B.” Similarly, phases “a certain thing A is placed in another certain thing B” and “a certain thing A is placed on another certain thing B” include, unless otherwise specified, “a certain thing A is directly placed in another certain thing B” and “a certain thing A is placed in another certain thing B with other thing interposed between the certain thing A and the another thing B.” Similarly, a phase “a certain thing A is located on another certain thing B” includes, unless otherwise specified, “a certain thing A is located on another certain thing B in contact of the certain thing A with the another certain thing B” and “a certain thing A is located on another certain thing B with other thing interposed between the certain thing A and the another thing B.” In addition, a phase “a certain thing A overlaps with another certain thing B when viewed in a certain direction” includes, unless otherwise specified, “a certain thing A overlaps entirely with another certain thing B” and “a certain thing A overlaps partially with another certain thing B.” First Embodiment FIGS.1to19show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1of the first embodiment includes a plurality of semiconductor elements10, a support substrate20, two input terminals31and32, an output terminal33, a pair of gate terminals34A and34B, a pair of detection terminals35A and35B, a pair of side terminals37A and37B, a plurality of base portions41, a plurality of connecting members51, a plurality of connecting members52, a plurality of intermediate metal layers7, a sealing member60, a first positioning portion81, and a second positioning portion82. FIG.1is a perspective view showing the semiconductor device A1.FIG.2is a plan view showing the semiconductor device A1.FIG.3is the plan view shown inFIG.2from which the sealing member is omitted.FIG.4is view showing an excerpt of a portion ofFIG.3.FIG.5is a front view showing the semiconductor device A1.FIG.6is a bottom view showing the semiconductor device A1.FIG.7is a left side view showing the semiconductor device A1.FIG.8is a right side view showing the semiconductor device A1.FIG.9is a cross-sectional view taken along line IX-IX inFIG.3.FIG.10is a cross-sectional view taken along line X-X inFIG.3.FIG.11is an enlarged main part cross-sectional view which is obtained by enlarging a portion ofFIG.10.FIG.12is an enlarged main part cross-sectional view similar toFIG.11, which shows a semiconductor element10B.FIG.13is a cross-sectional view taken along line XIII-XIII inFIG.3.FIG.14is an enlarged main part cross-sectional view which is obtained by enlarging a portion ofFIG.13.FIG.15is a cross-sectional view taken along line XV-XV inFIG.3.FIG.16is an enlarged main part cross-sectional view which is obtained by enlarging a portion ofFIG.15.FIG.17is a main part perspective view showing the semiconductor device A1.FIG.18is an exploded main part perspective view showing the semiconductor device A1.FIG.19is an enlarged main part cross-sectional view showing an example of a method of manufacturing the semiconductor device A1. For the sake of convenience of explanation, inFIGS.1to19, three directions orthogonal to one another are defined as an x direction, a y direction, and a z direction, respectively. The x direction is the horizontal direction in the plan view (seeFIG.2) of the semiconductor device A1. The y direction is the vertical direction in the plan view (seeFIG.2) of the semiconductor device A1. If necessary, one in the x direction is defined as an x1 direction, and the other in the x direction is defined as an x2 direction. Similarly, one in the y direction is defined as a y1 direction, the other in the y direction is defined as a y2 direction, one in the z direction is defined as a z1 direction, and the other in the z direction is defined as a z2 direction. In some cases, the z1 direction is referred to as a lower side and the z2 direction is referred to as an upper side. Further, the dimension in the z direction may be referred to as a “thickness.” The z direction corresponds to a “thickness direction” of the present disclosure. [Semiconductor Element10] Each of the plurality of semiconductor elements10is made of a semiconductor material mainly composed of SiC (silicon carbide). The semiconductor material is not limited to SiC, but may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. Each of the plurality of semiconductor elements10is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Each semiconductor element10is not limited to MOSFET, but may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET), a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor), an IC chip such as an LSI, a diode, a capacitor, and so on. The plurality of semiconductor elements10are all the same elements, for example, n-channel MOSFETs. Each semiconductor element10has, for example, a rectangular shape when viewed in the z direction (hereinafter also referred to as “in a plan view”), but is not limited thereto. The thickness of each semiconductor element10is, for example, about 50 to 370 μm, specifically about 350 μm, but is not limited thereto. The plurality of semiconductor elements10include a plurality of semiconductor elements10A and a plurality of semiconductor elements10B. As shown inFIG.3, the semiconductor device A1includes four semiconductor elements10A and four semiconductor elements10B. The number of semiconductor elements10is not limited to this configuration and may be appropriately changed according to the performance required for the semiconductor device A1. When the semiconductor device A1is, for example, a half-bridge type switching circuit, the plurality of semiconductor elements10A form an upper arm circuit in the switching circuit, and the plurality of semiconductor elements10B form a lower arm circuit in the switching circuit. As shown inFIGS.3and10, each of the plurality of semiconductor elements10A is mounted on the support substrate20(a conductive member24A to be described later). The plurality of semiconductor elements10A are lined up in the y direction and are separated from each other. As shown inFIGS.3and10, each semiconductor element10A is conductively bonded to the support substrate20(the conductive member24A) via the intermediate metal layer7A. The semiconductor element10A and the intermediate metal layer7A are in contact with each other by solid phase diffusion bonding. In the present disclosure, “A and B are bonded by solid phase diffusion bonding” means that A and B are fixed to each other in a state of being in direct contact with each other at a bonding interface as a result of solid phase diffusion bonding, and can be said that a solid phase diffusion bonding layer is composed of A and B. If the solid phase diffusion bonding is performed under the ideal conditions, the bonding interface may not be clearly present due to diffusion of metal elements. On the other hand, if an inclusion such as an oxide film is present on the surface layers of A and B, or if there are voids between A and B, these inclusion and voids may be present at the bonding interface. As shown inFIGS.3and9, each of the plurality of semiconductor elements10B is mounted on the support substrate20(a conductive member24B to be described later). The plurality of semiconductor elements10B are lined up in they direction and are separated from each other. As shown inFIGS.3and9, each semiconductor element10B is conductively bonded to the support substrate20(the conductive member24B) via the intermediate metal layer7B. The semiconductor element10A and the intermediate metal layer7B are bonded by solid phase diffusion bonding. In the example shown inFIG.3, the plurality of semiconductor elements10A and the plurality of semiconductor elements10B are arranged side by side alternately when viewed along the x direction, but the plurality of semiconductor elements10A and the plurality of semiconductor elements10B may be arranged so as to overlap when viewed along the x direction. As shown inFIGS.9to16, each of the plurality of semiconductor elements10(the plurality of semiconductor elements10A and the plurality of semiconductor elements10B) has an element main surface101, an element back surface102, and an element facing surface103. A semiconductor element10A is shown inFIG.11, and a semiconductor element10B is shown inFIG.12. In the illustrated example, the configurations of the respective parts of the semiconductor element10A and the semiconductor element10B are common. In each semiconductor element10, the element main surface101and the element back surface102are separated from each other in the z direction. The element main surface101faces the z2 direction, and the element back surface102faces the z1 direction. Each element facing surface103is a surface facing a direction intersecting the z direction. In the present embodiment, four element facing surfaces103facing the x direction (the x1 direction and the x2 direction) and the y direction (the y1 direction and the y2 direction) are provided. The element back surface102of the semiconductor element10A faces the conductive member24A. The element back surface102of each semiconductor element10B faces the conductive member24B. As shown inFIGS.11and12, each of the plurality of semiconductor elements10has a main surface electrode11, a back surface electrode12, and an insulating film13. The main surface electrode11is provided on the element main surface101. The main surface electrode11includes a first electrode111and a second electrode112, as shown in FIGS.11and12. The first electrode111is, for example, a source electrode through which a source current flows. The second electrode112is, for example, a gate electrode to which a gate voltage for driving each semiconductor element10is applied. The first electrode111is larger than the second electrode112. In the illustrated example, a case where the first electrode111is composed of one region is shown, but it may be divided into a plurality of regions. The back surface electrode12is provided on the element back surface102, as shown inFIGS.11and12. The back surface electrode12is formed over the entire element back surface102. The back surface electrode12is, for example, a drain electrode through which a drain current flows. At least the surface layer of the back surface electrode12is made of first metal. The first metal is metal bonded by solid phase diffusion bonding, for example, Ag, Cu, Ni, Fe, or Al. The entire back surface electrode12may be made of the first metal, or may have, for example, a structure in which a surface layer made of the first metal is laminated on a metal layer made of a different type of metal. The insulating film13is provided on the element main surface101, as shown inFIGS.11and12. The insulating film13has an electrical insulating property. The insulating film13surrounds the main surface electrode11in a plan view. The insulating film13insulates the first electrode111and the second electrode112from each other. The insulating film13is formed by stacking, for example, a SiO2(silicon dioxide) layer, a SiN4(silicon nitride) layer, and a polybenzoxazole layer in this order from the element main surface101. The configuration of the insulating film13is not limited to that described above, and for example, a polyimide layer may be used instead of the polybenzoxazole layer. [Support Substrate20] The support substrate20supports the plurality of semiconductor elements10. The support substrate20includes an insulating substrate21, a pair of main surface metal layers22A and22B, a pair of back surface metal layers23A and23B, a pair of conductive members24A and24B, a pair of insulating layers25A and25B, a pair of gate layers26A and26B, and a pair of detection layers27A and27B. The insulating substrate21, the pair of main surface metal layers22A and22B, and the pair of back surface metal layers23A and23B are composed as a so-called DBC (Direct Bonded Copper) substrate. In the present embodiment, the case of a DBC substrate is shown, but the present disclosure is not limited thereto, and for example, a DBA (Direct Bonded Aluminum) substrate may be used. The insulating substrate21insulates the main surface metal layers22A and22B and the back surface metal layers23A and23B from each other. The constituent material of the insulating substrate21is, for example, ceramics having excellent thermal conductivity. As such ceramics, for example, AlN (aluminum nitride), SiN (silicon nitride), Al2O3(aluminum oxide), and the like are used. Further, as the material of the insulating substrate21, an insulating resin material may be used instead of ceramics. Examples of such an insulating resin material may include an epoxy-based resin material and a PDMS (polydimethylsiloxane)-based resin material. The thickness of the insulating substrate21is, for example, about 0.32 mm. As shown inFIG.3, the insulating substrate21has a rectangular shape in a plan view. The insulating substrate21has a flat plate shape. As shown inFIGS.9,10,13, and15, the insulating substrate21has a main surface211and a back surface212. The main surface211and the back surface212are separated from each other in the z direction. The main surface211faces the z2 direction, and the back surface212faces the z1 direction. The pair of main surface metal layers22A and22B is arranged on the main surface211. The pair of back surface metal layers23A and23B is arranged on the back surface212. The pair of main surface metal layers22A and22B is arranged on the main surface211of the insulating substrate21, as shown inFIGS.9,10,13, and15. The pair of main surface metal layers22A and22B is separated from each other and is lined up in the x direction. The constituent material of each of the main surface metal layers22A and22B is, for example, Cu (copper), a Cu alloy, or Al (aluminum). The thickness of each of the main surface metal layers22A and22B is, for example, about 0.2 mm. Each of the main surface metal layers22A and22B has substantially a rectangular shape in a plan view. Each of the main surface metal layers22A and22B has, for example, a dimension of about 20 mm in the x direction and a dimension of about 30 mm in the y direction. As shown inFIGS.4and6, each of the main surface metal layers22A and22B has a pair of end edges221and222and a pair of end edges223and224. Each of the pair of end edges221and222extends in the y direction in a plan view. The pair of end edges221and222is separated from each other in the x direction. The end edge222is located in the x2 direction with respect to the end edge221. In the examples shown inFIGS.4and6, the pair of end edges221and222is substantially parallel to each other. Each of the pair of end edges223and224extends in the x direction in a plan view. The pair of end edges223and224is separated from each other in the y direction. The end edge224is located in the y2 direction with respect to the end edge223. In the examples shown inFIGS.4and6, since each of the main surface metal layers22A and22B has a rectangular shape in a plan view, the pair of end edges221and222and the pair of end edges223and224are substantially parallel to each other. The pair of back surface metal layers23A and23B is arranged on the back surface212of the insulating substrate21, as shown inFIGS.9,10,13, and15. The pair of back surface metal layers23A and23B is separated from each other and are lined up in the x direction. The lower surface (a surface facing the z1 direction) of each of the back surface metal layers23A and23B is exposed from the sealing member60. For example, a heat sink (not shown) may be connected to the lower surface of each of the back surface metal layers23A and23B. The constituent material of each of the back surface metal layers23A and23B is the same as that of each of the main surface metal layers22A and22B. That is, the constituent material of each of the back metal layers23A and23B is, for example, Cu, a Cu alloy, or Al. The thickness of each of the back surface metal layers23A and23B is, for example, about 0.2 mm. Each of the back surface metal layers23A and23B has substantially a rectangular shape in a plan view. Each of the back surface metal layers23A and23B has, for example, a dimension of about 20 mm in the x direction and a dimension of about 23 mm in the y direction. The dimension of each of the back surface metal layers23A and23B in the y direction is not limited to the above-mentioned value (23 mm), but may be about 75 to 90% of the dimension of each of the main surface metal layers22A and22B in the y direction. The back surface metal layer23A corresponds to a “first back surface metal layer” described in the claims, and the back surface metal layer23B corresponds to a “second back surface metal layer” described in the claims. As shown inFIGS.4and6, each of the back surface metal layers23A and23B has a pair of end edges231and232and a pair of end edges233and234. Each of the pair of end edges231and232extends in the y direction in a plan view. The pair of end edges231and232is separated from each other in the x direction. The end edge232is located in the x2 direction with respect to the end edge231. Each of the pair of end edges233and234extends in the x direction in a plan view. The pair of end edges233and234is separated from each other in the y direction. The end edge234is located in the y2 direction with respect to the end edge233. In the examples shown inFIGS.4and6, since each of the back surface metal layers23A and23B has a rectangular shape in a plan view, the pair of end edges231and232and the pair of end edges233and234are substantially parallel to each other. As shown inFIG.4, the end edge233of the back surface metal layer23A overlaps the semiconductor element10A located closest to the y1 direction among the plurality of semiconductor elements10A in a plan view. The end edge234of the back surface metal layer23B overlaps the semiconductor element10B located closest to the y2 direction among the plurality of semiconductor elements10B in a plan view. In the support substrate20, as shown inFIGS.4and6, the main surface metal layer22A and the back surface metal layer23A overlap in a plan view, and the main surface metal layer22B and the back surface metal layer23B overlap in a plan view. In particular, in the example shown inFIG.4, in a plan view, the center of each of the main surface metal layers22A and22B in the y direction and the center of each of the back surface metal layers23A and23B in the y direction overlap each other. The end edge231of each of the back surface metal layers23A and23B overlaps the end edge221of each of the main surface metal layers22A and22B in a plan view, and the end edge232of each of the back surface metal layers23A and23B overlaps the end edge222of each of the main surface metal layers22A and22B in a plan view. Further, the end edge233of each of the back surface metal layers23A and23B overlaps each of the main surface metal layers22A and22B in a plan view and is located in the y2 direction with respect to the end edge223of each of the main surface metal layers22A and22B. The edge234of each of the back surface metal layers23A and23B overlaps each of the main surface metal layers22A and22B in a plan view and is located in the y1 direction with respect to the end edge224of each of the main surface metal layers22A and22B. Each of the end edges221,222,231, and232corresponds to a “first end edge” described in the claims, and each of the end edges223,224,233, and234corresponds to a “second end edge” described in the claims. As shown inFIGS.3,9,10, and17, the pair of conductive members24A and24B is separated from each other and is lined up in the x direction. The conductive member24A is arranged on the main surface metal layer22A, and the conductive member24B is arranged on the main surface metal layer22B. The plurality of semiconductor elements10A are arranged on the conductive member24A, and the plurality of semiconductor elements10B are arranged on the conductive member24B. The conductive member24A includes a conductive layer241A, two metal layers242A and243A, and a support surface layer245A. The conductive member24B includes a conductive layer241B, two metal layers242B and243B, and a support surface layer245B. The conductive members24A and24B may be composed of a single metal layer and the support surface layers245A and245B. Each of the conductive layers241A and241B is composed of, for example, graphite. As described above, graphite has a hexagonal crystal structure and is layered, and its thermal conductivity is anisotropic between a direction parallel to the layer and a direction orthogonal to the layer. The thermal conductivity in the direction parallel to the layer is about 1,500 W/mK, and the thermal conductivity in the direction orthogonal to the layer is about 5 W/mK. Each of the conductive layers241A and241B is arranged in the direction parallel to the layer along the z direction. Further, as described above, graphite has anisotropy in the coefficient of linear expansion. The coefficient of linear expansion in the direction parallel to the layer is about 0 ppm/K, and the coefficient of linear expansion in the direction orthogonal to the layer is about 25 ppm/K. Each of the conductive layers241A and241B is arranged in the direction orthogonal to the layer along they direction. Therefore, each of the conductive layers241A and241B is arranged so that the coefficient of linear expansion in they direction is about 25 ppm/K and the coefficient of linear expansion in the x direction is about 0 ppm/K. That is, each of the conductive layers241A and241B is arranged in a direction in which the coefficient of linear expansion is relatively large along the y direction. As shown inFIGS.9to16, the metal layers242A and242B are arranged on the upper surfaces (the surfaces facing the z2 direction) of the conductive layers241A and241B, respectively. The constituent material of each of the metal layers242A and242B is, for example, Cu or a Cu alloy. The metal layers242A and242B are provided to improve the bonding between the conductive members24A and24B and the semiconductor elements10A and10B, respectively. The thickness of each of the metal layers242A and242B is, for example, about 0.1 to 2.0 mm. A substrate recess215A is formed in the metal layer242A of the present embodiment. The substrate recess215A is recessed inward in the x direction from the end portion of the metal layer242A in the x direction. In the illustrated example, two substrate recesses215A are provided at both ends of the metal layer242A in the x direction, respectively. The inner surface of the substrate recess215A is a substrate facing surface213A. In the illustrated example, the substrate facing surface213A faces outward in the x direction. The substrate recess215A and the substrate facing surface213A may be provided on the constituent elements of the support substrate20, and are not limited to the configuration formed on the metal layer242A. Further, a substrate recess215B is formed in the metal layer242B of the present embodiment. The substrate recess215B is recessed inward in the x direction from the end portion of the metal layer242B in the x direction. In the illustrated example, two substrate recesses215B are provided at both ends of the metal layer242B in the x direction, respectively. The inner surface of the substrate recess215B is a substrate facing surface213B. In the illustrated example, the substrate facing surface213B faces outward in the x direction. The substrate recess215B and the substrate facing surface213B may be provided on the constituent elements of the support substrate20, and are not limited to the configuration formed on the metal layer242B. The support surface layer245A is laminated on the metal layer242A. The support surface layer245A is a layer made of a second metal. The second metal is a metal bonded by solid phase diffusion bonding and is, for example, Ag, Cu, Ni, Fe, or Al. The thickness of the support surface layer245A is not limited in any way and is, for example, 0.5 μm to 5.0 μm. In the illustrated example, it is, for example, about 2.0 μm. The support surface layer245B is laminated on the metal layer242B. The support surface layer245B is a layer made of a second metal. The thickness of the support surface layer245B is not limited in any way and is, for example, 0.5 μm to 5.0 μm. In the illustrated example, it is, for example, about 2.0 μm. As shown inFIGS.9to15, the metal layers243A and243B are arranged on the lower surfaces (the surfaces facing the z1 direction) of the conductive layers241A and241B, respectively. The constituent material of each of the metal layers243A and243B is, for example, Cu or a Cu alloy. The metal layers243A and243B are provided to improve the bonding between the conductive members24A and24B and the main surface metal layers22A and22B, respectively. The thickness of each of the metal layers243A and243B is, for example, about 0.1 to 2.0 mm. Each of the metal layers242A,242B,243A, and243B corresponds to a “surface metal layer” described in the claims. As shown inFIGS.9to13, a conductive bonding layer29A is interposed between the conductive member24A (the metal layer243A) and the main surface metal layer22A. The conductive member24A is bonded to the main surface metal layer22A by the conductive bonding layer29A. As shown inFIGS.9,10, and15, a conductive bonding layer29B is interposed between the conductive member24B (the metal layer243B) and the main surface metal layer22B. The conductive member24B is bonded to the main surface metal layer22B by the conductive bonding layer29B. Each of the conductive bonding layers29A and29B is, any of, for example, solder, metal paste, sintered metal, and the like. The pair of insulating layers25A and25B has an electrical insulating property, and the constituent material thereof is, for example, a glass epoxy resin. As shown inFIG.3, each of the pair of insulating layers25A and25B has a strip shape extending in the y direction. The insulating layer25A is bonded to the conductive member24A, as shown inFIGS.3and10. The insulating layer25A is located in the x2 direction with respect to the plurality of semiconductor elements10A. The insulating layer25B is bonded to the conductive member24B, as shown inFIGS.3and9. The insulating layer25B is located in the x1 direction with respect to the plurality of semiconductor elements10B. The pair of gate layers26A and26B has conductivity, and the constituent material thereof is, for example, Cu or a Cu alloy. As shown inFIG.3, each of the pair of gate layers26A and26B has a strip shape extending in the y direction. The gate layer26A is arranged on the insulating layer25A, as shown inFIGS.3and10. The gate layer26A is electrically connected to the second electrode112(the gate electrode) of each semiconductor element10A via the connecting member51(a gate wire511to be described later). The gate layer26B is arranged on the insulating layer25B, as shown inFIGS.3and9. The gate layer26B is electrically connected to the second electrode112(the gate electrode) of each semiconductor element10B via the connecting member51(the gate wire511to be described later). The pair of detection layers27A and27B has conductivity, and the constituent material thereof is, for example, Cu or a Cu alloy. As shown inFIG.3, each of the pair of detection layers27A and27B has a strip shape extending in they direction. As shown inFIGS.3and10, the detection layer27A is arranged on the insulating layer25A together with the gate layer26A. The detection layer27A is located on the insulating layer25A next to the gate layer26A and is separated from the gate layer26A in a plan view. In the examples shown inFIGS.3and10, the detection layer27A is located in the x2 direction with respect to the gate layer26A and is arranged farther than the gate layer26A with respect to the plurality of semiconductor elements10A. The arrangements of the gate layer26A and the detection layer27A in the x direction may be reversed. The detection layer27A is electrically connected to the first electrode111(the source electrode) of each semiconductor element10A via the connecting member51(a detection wire512to be described later). As shown inFIGS.3and9, the detection layer27B is arranged on the insulating layer25B together with the gate layer26B. The detection layer27B is located on the insulating layer25B next to the gate layer26B and is separated from the gate layer26B in a plan view. In the examples shown inFIGS.3and9, the detection layer27B is located in the x1 direction with respect to the gate layer26B and is arranged farther than the gate layer26B with respect to the plurality of semiconductor elements10B. The arrangements of the gate layer26B and the detection layer27B in the x direction may be reversed. The detection layer27B is electrically connected to the first electrode111(the source electrode) of each semiconductor element10B via the connecting member51(the detection wire512to be described later). [Intermediate Metal Layer7] As shown inFIGS.3and9to19, the intermediate metal layer7is interposed between the semiconductor element10and the support substrate20in the z direction. The semiconductor element10and the intermediate metal layer7are bonded by solid phase diffusion bonding. Further, the intermediate metal layer7and the support substrate20are bonded by solid phase diffusion bonding. In the present embodiment, the plurality of intermediate metal layers7include the intermediate metal layer7A and the intermediate metal layer7B. The intermediate metal layer7A is interposed between the plurality of semiconductor elements10A and the conductive member24A of the support substrate20. The intermediate metal layer7A of the present embodiment includes a first layer71A, a second layer72A, and a third layer73A. The first layer71A is a layer made of a first metal and is a layer bonded to the back surface electrode12of each semiconductor element10A by solid phase diffusion bonding. The thickness of the first layer71A is not limited in any way and is, for example, 0.5 μm to 5.0 μm. In the illustrated example, it is, for example, about 2.0 μm. The second layer72A is a layer made of a second metal and is a layer bonded to the support surface layer245A of the conductive member24A of the support substrate20by solid phase diffusion bonding. The thickness of the second layer72A is not limited in any way and is, for example, 0.5 μm to 5.0 μm. In the illustrated example, it is, for example, about 2.0 μm. The third layer73A is a layer interposed between the first layer71A and the second layer72A. The third layer73A is made of a third metal. As the third metal, it is preferable to select metal softer than the first metal and the second metal. The third metal is, for example, Al, an Al alloy, or a Mg alloy. In addition, an underlayer or barrier layer (not shown) made of, for example, Ni, Ti, or the like may be provided between the third layer73A and at least one of the first layer71A and the second layer72A. The thickness of the third layer73A is not limited in any way and is, for example, 50 μm to 300 μm, specifically about 200 μm. As shown inFIGS.3,11,13, and14, in the present embodiment, the intermediate metal layer7A includes a plurality of first recesses701A and second recesses702A. The plurality of first recesses701A are formed on the side of the intermediate metal layer7A where the first layer71A is provided in the z direction. The first recesses701A are recessed toward the second layer72A in the z direction. In the illustrated example, the first recesses701A are arranged side by side in the y direction when viewed along the z direction. The number of first recesses701A corresponds to the number of semiconductor elements10A and is four in the illustrated example. Each first recess701A has a rectangular shape when viewed along the z direction. The semiconductor element10A is bonded to the bottom of the first recess701A by solid phase diffusion bonding. When viewed along the z direction, the semiconductor element10A is included in the first recess701A. A method of forming the first recess701A is not limited in any way, and examples thereof may include laser processing and press processing using a mold. If the first recess701A is formed by press processing after the first layer71A is formed, cracks or the like may occur in the first layer71A at the outer edge of the first recess701A. The depth of the first recess701A is not limited in any way and is, for example, 25 μm to 150 μm. When the thickness of the third layer73A is 200 μm, the depth of the first recess701A is about 100 μm. Further, a portion of the semiconductor element10A protrudes from the first recess701A in the z2 direction. When the thickness of the semiconductor element10A in the z direction is 350 μm, the protruding height is, for example, about 250 μm, which is larger than ½ of the height of the semiconductor element10A. The inner surface of the first recess701A constitutes a first facing surface711A. In the present embodiment, since the first recess701A has a rectangular shape, four first facing surfaces711A are provided. Each first facing surface711A faces the element facing surface103of the semiconductor element10A. Portions where the first facing surface711A and the element facing surface103face each other are engaged with each other to form the first positioning portion81. The first positioning portion81is provided to suppress the relative movement of the semiconductor element10A and the intermediate metal layer7A. In the present embodiment, the relative movement in the x direction and the y direction is suppressed by the first positioning portion81. The second recess702A is formed on the side of the intermediate metal layer7A where the second layer72A is provided in the z direction. The second recess702A is recessed toward the first layer71A in the x direction. In the illustrated example, the second recess702A is formed by forming both ends of the intermediate metal layer7A in they direction so as to protrude to the opposite side of the semiconductor element10A in the z direction. The inner surface of the second recess702A constitutes a second facing surface712A. As shown inFIG.14, the second facing surface712A is a surface facing inward in the y direction and faces the substrate facing surface213A. Portions where the second facing surface712A and the substrate facing surface213A face each other are engaged with each other to form the second positioning portion82. The second positioning portion82is provided to suppress the relative movement of the intermediate metal layer7A and the conductive member24A of the support substrate20. In the present embodiment, the relative movement in the x direction is suppressed by the second positioning portion82. In the present embodiment, two second facing surfaces712A are provided on both sides of the intermediate metal layer7A in the x direction. As a result, two second positioning portions82are provided for the intermediate metal layer7A. The intermediate metal layer7B is interposed between the plurality of semiconductor elements10B and the conductive member24B of the support substrate20. The intermediate metal layer7B of the present embodiment includes a first layer71B, a second layer72B, and a third layer73B. The first layer71B is a layer made of a first metal and is a layer bonded to the back surface electrode12of each semiconductor element10B by solid phase diffusion bonding. The thickness of the first layer71B is not limited in any way and is, for example, 0.5 μm to 5.0 μm. In the illustrated example, it is, for example, about 2.0 μm. The second layer72B is a layer made of a second metal and is a layer bonded to the support surface layer245B of the conductive member24B of the support substrate20by solid phase diffusion bonding. The thickness of the second layer72B is not limited in any way and is, for example, 0.5 μm to 5.0 μm. In the shown example, it is, for example, about 2.0 μm. The third layer73B is a layer interposed between the first layer71B and the second layer72B. The third layer73B is made of a third metal. In addition, an underlayer or barrier layer (not shown) made of, for example, Ni, Ti, or the like may be provided between the third layer73B and at least one of the first layer71B and the second layer72B. The thickness of the third layer73B is not limited in any way and is, for example, 50 μm to 300 μm, specifically about 200 μm. As shown inFIGS.3,11,15, and16, in the present embodiment, the intermediate metal layer7B has a plurality of first recesses701B and second recesses702B. The plurality of first recesses701B are formed on the side of the intermediate metal layer7B where the first layer71B is provided in the z direction. The first recesses701B are recessed toward the second layer72B in the z direction. In the illustrated example, the first recesses701B are arranged side by side in they direction when viewed along the z direction. The number of first recesses701B corresponds to the number of semiconductor elements10B and is four in the illustrated example. Each first recess701B has a rectangular shape when viewed along the z direction. The semiconductor element10B is bonded to the bottom of the first recess701B by solid phase diffusion bonding. When viewed along the z direction, the semiconductor element10B is included in the first recess701B. A method of forming the first recess701B is not limited in any way, and examples thereof may include laser processing and press processing using a mold. If the first recess701B is formed by press processing after the first layer71B is formed, cracks or the like may occur in the first layer71B at the outer edge of the first recess701B. The depth of the first recess701B is not limited in any way and is, for example, 25 μm to 150 μm. When the thickness of the third layer73B is 200 μm, the depth of the first recess701B is about 100 μm. Further, a portion of the semiconductor element10B protrudes from the first recess701B in the z2 direction. When the thickness of the semiconductor element10B in the z direction is 350 μm, the protruding height is, for example, about 250 μm, which is larger than ½ of the height of the semiconductor element10B. The inner surface of the first recess701B constitutes a first facing surface711B. In the present embodiment, since the first recess701B has a rectangular shape, four first facing surfaces711B are provided. Each first facing surface711B faces the element facing surface103of the semiconductor element10B. Portions where the first facing surface711B and the element facing surface103face each other are engaged with each other to form the first positioning portion81. The first positioning portion81is provided to suppress the relative movement of the semiconductor element10B and the intermediate metal layer7B. In the present embodiment, the relative movement in the x direction and the y direction is suppressed by the first positioning portion81. The second recess702B is formed on the side of the intermediate metal layer7B where the second layer72B is provided in the z direction. The second recess702B is recessed toward the first layer71B in the x direction. In the illustrated example, the second recess702B is formed by forming both ends of the intermediate metal layer7B in they direction so as to protrude to the opposite side of the semiconductor element10B in the z direction. The inner surface of the second recess702B constitutes a second facing surface712B. As shown inFIG.14, the second facing surface712B is a surface facing inward in the y direction and faces the substrate facing surface213B. Portions where the second facing surface712B and the substrate facing surface213B face each other are engaged with each other to form the second positioning portion82. The second positioning portion82is provided to suppress the relative movement of the intermediate metal layer7B and the conductive member24B of the support substrate20. In the present embodiment, the relative movement in the x direction is suppressed by the second positioning portion82. In the present embodiment, two second facing surfaces712B are provided on both sides of the intermediate metal layer7B in the x direction. As a result, two second positioning portions82are provided for the intermediate metal layer7B. [Input Terminals31and32] The two input terminals31and32are metal plates, respectively. The constituent material of each metal plate is Cu or a Cu alloy. Both of the two input terminals31and32have a dimension of, for example, about 0.8 mm in the z direction, but are not limited thereto. Both of the two input terminals31and32are located closer to the x2 direction in the semiconductor device A1, as shown inFIGS.1,3,9, and10. For example, a power supply voltage is applied between the two input terminals31and32. The power supply voltage may be directly applied to the input terminals31and32from a power supply (not shown), or may be applied to the input terminals31and32via a bus bar (not shown) connected so as to sandwich the input terminals31and32. Further, a snubber circuit or the like may be connected in parallel. The input terminal31is a positive electrode (P terminal), and the input terminal32is a negative electrode (N terminal). The input terminal32is arranged apart from both the input terminal31and the support substrate20(the conductive member24A) in the z direction. The input terminal31includes a pad portion311and a terminal portion312, as shown inFIGS.3and9. The pad portion311is a portion of the input terminal31covered with the sealing member60. In the example shown inFIG.3, the end portion of the pad portion311on the x1 direction side has a comb-tooth shape in a plan view, but may have a rectangular shape in a plan view instead of the comb-tooth shape. The comb-shaped portion of the pad portion311is conductively bonded to the conductive member24A (the metal layer242A). The bonding between the pad portion311and the conductive member24A may be one of laser bonding, ultrasonic bonding, and bonding using a conductive bonding material. The terminal portion312is a portion of the input terminal31exposed from the sealing member60. As shown inFIGS.3,5,6,8, and9, the terminal portion312extends from the sealing member60in the x2 direction in a plan view. The input terminal32includes a pad portion321and a terminal portion322, as shown inFIGS.3and9. The pad portion321is a portion of the input terminal32covered with the sealing member60. As shown inFIG.3, the pad portion321includes a connecting portion321aand a plurality of extending portions321b. The connecting portion321ahas a strip shape extending in they direction. The connecting portion321ais connected to the terminal portion322. The plurality of extending portions321bhave a strip shape extending from the connecting portion321ain the x1 direction. The plurality of extending portions321bare separated from each other and are lined up in the y direction in a plan view. The tip portion of each extending portion321boverlaps each base portion41in a plan view and is bonded to each base portion41. The bonding may be laser welding using laser light, ultrasonic bonding, or bonding using a bonding material. The tip portion is an end edge portion on the x1 direction side of the extending portion321bthat is opposite to the side connected to the connecting portion321ain the x direction. The terminal portion322is a portion of the input terminal32exposed from the sealing member60. As shown inFIGS.2,3, and6, the terminal portion322extends from the sealing member60in the x2 direction in a plan view. The terminal portion322has a rectangular shape in a plan view. As shown inFIGS.2,3, and6, the terminal portion322overlaps the terminal portion312of the input terminal31in a plan view. The terminal portion322is separated from the terminal portion312in the z2 direction. The shape of the terminal portion322is the same as the shape of, for example, the terminal portion312. The output terminal33is a metal plate. The constituent material of the metal plate is, for example, Cu or a Cu alloy. As shown inFIGS.1,2,3,5,6, and9, the output terminal33is located closer to the x1 direction in the semiconductor device A1. AC power (voltage) power-converted by the plurality of semiconductor elements10is output from the output terminal33. As shown inFIGS.3and9, the output terminal33includes a pad portion331and a terminal portion332. The pad portion331is a portion of the output terminal33covered with the sealing member60. In the example shown inFIG.3, a portion of the pad portion331on the x2 direction side has a comb-tooth shape in a plan view, but may have a rectangular shape in a plan view instead of the comb-tooth shape. The comb-shaped portion of the pad portion331is conductively bonded to the conductive member24B (the metal layer242B). The bonding between the pad portion331and the conductive member24B may be laser bonding, ultrasonic bonding, or bonding using a conductive bonding material. The terminal portion332is a portion of the output terminal33exposed from the sealing member60. As shown inFIGS.2,3,5,6,9, and10, the terminal portion332extends from the sealing member60in the x1 direction. As shown inFIG.3, the pair of gate terminals34A and34B is located next to the respective conductive members24A and24B in the y direction. A gate voltage for driving the plurality of semiconductor elements10A is applied to the gate terminal34A. A gate voltage for driving the plurality of semiconductor elements10B is applied to the gate terminal34B. As shown inFIG.3, the pair of detection terminals35A and35B is located next to the pair of gate terminals34A and34B in the x direction. A voltage (voltage corresponding to a source current) applied to each main surface electrode11(the first electrode111) of the plurality of semiconductor elements10A is detected from the detection terminal35A. A voltage (voltage corresponding to a source current) applied to each main surface electrode11(the first electrode111) of the plurality of semiconductor elements10B is detected from the detection terminal35B. As shown inFIG.3, a plurality of dummy terminals36are located on the opposite side of the pair of detection terminals35A and35B from the pair of gate terminals34A and34B in the x direction. In the semiconductor device A1, the number of dummy terminals36is six. Of these, three dummy terminals36are located on one side (the x2 direction) in the x direction. The remaining three dummy terminals36are located on the other side (the x1 direction) in the x direction. The number and arrangement of dummy terminals36are not limited to the above configuration. The plurality of dummy terminals36may not be provided. As shown inFIGS.1to5and6, the pair of gate terminals34A and34B, the pair of detection terminals35A and35B, and the plurality of dummy terminals36are arranged along the x direction in a plan view. In the semiconductor device A1, the pair of gate terminals34A and34B, the pair of detection terminals35A and35B, and the plurality of dummy terminals36are all formed from the same lead frame. An insulating plate39has an electrical insulating property, and the constituent material thereof is, for example, insulating paper. A portion of the insulating plate39is a flat plate and is sandwiched between the terminal portion312of the input terminal31and the terminal portion322of the input terminal32in the z direction, as shown inFIGS.3,5,8,9, and10. In a plan view, the input terminal31entirely overlaps the insulating plate39. Further, in a plan view, in the input terminal32, a portion of the pad portion321, and the entire terminal portion322overlap the insulating plate39. The two input terminals31and32are insulated from each other by the insulating plate39. A portion of the insulating plate39(the portion on the x1 direction side) is covered with the sealing member60. As shown inFIG.9, the insulating plate39includes an interposing portion391and an extending portion392. The interposing portion391is interposed between the terminal portion312of the input terminal31and the terminal portion322of the input terminal32in the z direction. The entire interposing portion391is sandwiched between the terminal portion312and the terminal portion322. The extending portion392extends from the interposing portion391further than the terminal portion312and the terminal portion322in the x2 direction. [Base Portion41] Each of the plurality of base portions41has electrical insulating property, and the constituent material thereof is, for example, ceramics. As shown inFIG.9, each base portion41is bonded to the surface of the conductive member24A. Each base portion41has, for example, a rectangular shape in a plan view. The plurality of base portions41are lined up in the y direction and are separated from each other. The dimension of each base portion41in the z direction is substantially the same as the sum of the dimension of the input terminal31in the z direction and the dimension of the insulating plate39in the z direction. Each extending portion321bof the pad portion321of the input terminal32is bonded to each base portion41. Each base portion41supports the input terminal32so that the input terminal32is substantially parallel to the support substrate20. [Connecting Member51] The plurality of connecting members51are so-called bonding wires. Each of the plurality of connecting members51has conductivity, and the constituent material thereof is, any of, for example, Al, Cu, Au, a clad material, and an alloy having one or more of these. As shown inFIG.3, the plurality of connecting members51include a plurality of gate wires511, a plurality of detection wires512, a pair of first connecting wires513, and a pair of second connecting wires514. As shown inFIG.3, each of the plurality of gate wires511is bonded to the second electrode112(the gate electrode) of each semiconductor element10and to any of the pair of gate layers26A and26B. The plurality of gate wires511include one that electrically connects the second electrode112of each semiconductor element10A and the gate layer26A, and one that electrically connects the second electrode112of each semiconductor element10B and the gate layer26B. As shown inFIGS.3,9, and10, each of the plurality of detection wires512is bonded to the first electrode111(the source electrode) of each semiconductor element10and to any of the pair of detection layers27A and27B. The plurality of detection wires512include one that electrically connects the first electrode111of each semiconductor element10A and the detection layer27A, and one that electrically connects the first electrode111of each semiconductor element10B and the detection layer27B. As shown inFIG.3, one of the pair of first connecting wires513electrically connects the gate layer26A and the gate terminal34A, and the other thereof electrically connects the gate layer26B and the gate terminal34B. The one first connecting wire513is bonded to the gate layer26A and the pad portion341of the gate terminal34A. The other first connecting wire513is connected to the gate layer26B and the pad portion341of the gate terminal34B. As shown inFIG.3, one of the pair of second connecting wires514electrically connects the detection layer27A and the detection terminal35A, and the other thereof electrically connects the detection layer27B and the insulating layer25B. The one second connecting wire514is bonded to the detection layer27A and the pad portion351of the detection terminal35A. The other second connecting wire514is bonded to the detection layer27B and the pad portion351of the detection terminal35B. [Connecting Member52] Each of the plurality of connecting members52has conductivity, and the constituent material thereof is, any of, for example, Al, Cu, Au, a clad material, and an alloy having one or more of these. In the present embodiment, the plurality of connecting members52include a plurality of first main wires521and a plurality of second main wires522. The connecting members52are not limited to the wires, but may be, for example, plate-shaped connecting members formed of metal plates. As shown inFIGS.3and10, each of the plurality of first main wires521electrically connects each semiconductor element10A and the conductive member24B. Each first main wire521is bonded to the first electrode111(the source electrode) of each semiconductor element10A and the metal layer242B of the conductive member24B. In the illustrated example, two first main wires521are bonded to the first electrode111of one semiconductor element10A, but this is an example, and the number of first main wires521is not limited in any way. As shown inFIGS.3and9, each of the plurality of second main wires522connects each semiconductor element10B and the input terminal32. Each second main wire522is bonded to the first electrode111(the source electrode) of each semiconductor element10B and each extending portion321bof the pad portion321of the input terminal32. In the shown example, two second main wires522are bonded to the first electrode111of one semiconductor element10B, but this is an example, and the number of second main wires522is not limited in any way. [Sealing Member60] As shown inFIGS.1and2to15, the sealing member60covers the plurality of semiconductor elements10, a portion of the support substrate20, a portion of the two input terminals31and32, a portion of the output terminal33, a portion of the pair of gate terminals34A and34B, a portion of the pair of detection terminals35A and35B, a portion of the plurality of dummy terminals36, the plurality of base portions41, the plurality of connecting members51, the plurality of connecting members52, and the intermediate metal layers7A and7B. The constituent material of the sealing member60is an insulating resin material, for example, an epoxy resin. The sealing member60can be formed, for example, by transfer molding. The dimension of the sealing member60in the z direction is, for example, about 10 mm. As shown inFIGS.1,2,10,13, and15, the sealing member60includes a resin main surface61, a resin back surface62, and a plurality of resin side surfaces631to634. The resin main surface61and the resin back surface62are separated from each other in the z direction, as shown inFIGS.5,7to10,13, and15. The resin main surface61faces the z1 direction, and the resin back surface62faces the z2 direction. As shown inFIG.6, the resin back surface62has a frame shape surrounding the pair of back surface metal layers23A and23B in a plan view. The plurality of resin side surfaces631to634are each connected to both the resin main surface61and the resin back surface62, and are sandwiched between them in the z direction. As shown inFIGS.2,3,5,6,9, and10, the two resin side surfaces631and632are separated from each other in the x direction. The resin side surface631faces the x1 direction, and the resin side surface632faces the x2 direction. As shown inFIGS.2,3,6to8,13, and15, the two resin side surfaces633and634are separated from each other in they direction. The resin side surface633faces the y1 direction, and the resin side surface634faces the y2 direction. In a method of manufacturing the semiconductor device A1, as shown inFIGS.18and19, the intermediate metal layer7A is placed on the conductive member24A of the support substrate20. At this time, the substrate facing surface213A and the second facing surface712A face each other to form the second positioning portion82. Similarly, the intermediate metal layer7B is placed on the conductive member24B of the support substrate20. At this time, the substrate facing surface213B and the second facing surface712B face each other to form the second positioning portion82. Further, the plurality of semiconductor elements10A are placed on the plurality of first recesses701A of the intermediate metal layer7A. At this time, the element facing surface103and the first facing surface711A face each other to form the first positioning portion81. Further, the plurality of semiconductor elements10B are placed on the plurality of first recesses701B of the intermediate metal layer7B. At this time, the element facing surface103and the first facing surface711B face each other to form the first positioning portion81. Then, pressure treatment and heat treatment are performed in which the semiconductor element10A, the intermediate metal layer7A, and the conductive member24A (the support substrate20) are pressed against each other, and the semiconductor element10B, the intermediate metal layer7B, and the conductive member24B (the support substrate20) are pressed against each other. As a result, the first layers71A and71B and the back surface electrodes12of the semiconductor elements10A and10B are bonded by solid phase diffusion bonding. Further, the second layers72A and72B and the support surface layers245A and245B are bonded by solid phase diffusion bonding. The operations and effects of the semiconductor device A1according to the first embodiment are as follows. As shown inFIGS.11,12,14, and16, the semiconductor device A1includes the first positioning portion81. The first positioning portion81suppresses the relative movement of the semiconductor elements10A and10B and the intermediate metal layers7A and7B. Therefore, for example, at the time of manufacturing the semiconductor device A1, after mounting the semiconductor elements10A and10B on the intermediate metal layers7A and7B, it is possible to prevent the semiconductor elements10A and10B from being improperly displaced with respect to the intermediate metal layers7A and7B until the semiconductor elements10A and10B (the back surface electrodes12) and the intermediate metal layers7A and7B (the first layers71A and71B) are bonded to each other by solid phase diffusion bonding. Therefore, according to the semiconductor device A1, the displacement of the semiconductor elements can be suppressed. The first positioning portion81is configured by engaging the element facing surfaces103of the semiconductor elements10A and10B and the first facing surfaces711A and711B of the intermediate metal layers7A and7B with each other. Therefore, it is not necessary to provide, for example, an adhesive for temporarily fixing between the back surface electrodes12and the first layers71A and71B. As a result, impurities that may exist between the back surface electrodes12and the first layers71A and71B can be reduced, thereby more reliably performing solid phase diffusion bonding. The first facing surfaces711A and711B are composed of the inner surfaces of the first recesses701A and701B. Further, the semiconductor elements10A and10B are contained in the first recesses701A and701B when viewed along the z direction, and a portion of each of the semiconductor elements10A and10B is accommodated in each of the first recesses701A and701B. As a result, it is possible to prevent the semiconductor elements10A and10B from moving in both the x direction and the y direction with respect to the intermediate metal layers7A and7B. Portions of the semiconductor elements10A and10B protrude from the first recesses701A and701B in the z2 direction, respectively. The intermediate metal layers7A and7B are electrically connected to the back electrodes12of the semiconductor elements10A and10B, respectively, while being insulated from the first electrode111and the second electrode112, respectively. By protruding the semiconductor elements10A and10B, it is possible to prevent the intermediate metal layers7A and7B from being improperly connected electrically to the first electrode111and the second electrode112, respectively. Further, in order to avoid such electrical connection, it is preferable to protrude ½ or more of the thickness of the semiconductor elements10A and10B in the z direction. As shown inFIGS.13to18, the semiconductor device A1includes the second positioning portion82. The second positioning portion82suppresses the relative movement between the support substrate20and the intermediate metal layers7A and7B. Therefore, for example, at the time of manufacturing the semiconductor device A1, after mounting the intermediate metal layers7A and7B on the support substrate20(the conductive members24A and24B), it is possible to prevent the intermediate metal layers7A and7B from being improperly displaced with respect to the support substrate20until the support substrate20(the support surface layers245A and245B) and the intermediate metal layers7A and7B (the second layers72A and72B) are bonded to each other by solid phase diffusion bonding. Therefore, the displacement of the semiconductor elements can be further suppressed. The second positioning portion82is configured by engaging the substrate facing surfaces213A of the support substrate20(the conductive members24A and24B) and the second facing surfaces712A and712B of the intermediate metal layers7A and7B with each other. Therefore, it is not necessary to provide, for example, an adhesive for temporarily fixing between the second layers72A and72B and the support surface layers245A and245B. As a result, impurities that may exist between the second layers72A and72B and the support surface layers245A and245B can be reduced, thereby more reliably performing solid phase diffusion bonding. The second recesses702A and702B are formed in the intermediate metal layers7A and7B, respectively. The second recesses702A and702B are arranged so as to cross the conductive members24A and24B in the x direction, respectively. Therefore, four semiconductor elements10A and10B are arranged on each of the intermediate metal layers7A and7B. This has an advantage that the manufacturing efficiency can be improved over a configuration in which a plurality of intermediate metal layers7A and7B are individually facilitated for each of the four semiconductor elements10A and10B. The first layers71A and71B of the intermediate metal layers7A and7B and the back electrodes12of the semiconductor elements10A and10B are formed of the same first metal. This is preferable for solid phase diffusion bonding between the first layers71A and71B of the intermediate metal layers7A and7B and the back electrodes12of the semiconductor elements10A and10B. Further, selecting Ag as the first metal is advantageous for more reliable solid phase diffusion bonding. The second layers72A and72B of the intermediate metal layers7A and7B and the support surface layers245A and245B of the support substrate20are formed of the same second metal. This is preferable for solid phase diffusion bonding between the second layers72A and72B of the intermediate metal layers7A and7B and the support surface layers245A and245B of the support substrate20. Further, selecting Ag as the second metal is advantageous for more reliable solid phase diffusion bonding. The intermediate metal layers7A and7B include the third layers73A and73B interposed between the first layers71A and71B and the second layers72A and72B, respectively. The third layers73A and73B are made of the third metal softer than the first metal of the first layers71A and71B and the second metal of the second layers72A and72B. As a result, when the semiconductor elements10A and10B, the intermediate metal layers7A and7B, and the conductive members24A and24B (the support substrate20) are collectively pressure-treated and heat-treated so that they are bonded to each other by solid-phase diffusion bonding, the third layers73A and73B function as buffer layers. As a result, for example, it is possible to suppress a situation in which the semiconductor elements10A and10B are unintentionally tilted to prevent properly performing the solid phase diffusion bonding. When the first metal and the second metal are Ag, it is preferable to select Al as the third metal in order to enhance such an effect. Further, it is desirable that the thickness of the third layers73A and73B is thicker than that of the first layers71A and71B and the second layers72A and72B in order to improve the buffer function. FIGS.20to26show other embodiments and modifications thereof of the present disclosure. In these figures, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment. Second Embodiment FIGS.20and21show a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A2of the second embodiment, the configurations of the intermediate metal layer7and the support substrate20are different from those of the above-described embodiment. AlthoughFIGS.20and21show the semiconductor element10A, the intermediate metal layer7A, and the conductive member24A, the semiconductor element10B, the intermediate metal layer7B, and the conductive member24B of the second embodiment have the same configurations as the semiconductor element10A, the intermediate metal layer7A, and the conductive member24A, respectively, unless otherwise stated. The intermediate metal layer7A of the second embodiment includes the first recess701A and does not include the second recess702A of the above-described embodiment. The intermediate metal layer7A has a rectangular shape when viewed along the z direction and includes four second facing surfaces712A. The second facing surface712A is a surface facing outward in the x direction or the y direction. Further, one intermediate metal layer7A is provided for one semiconductor element10A. That is, in the second embodiment, the number of semiconductor elements10A is equal to the number of intermediate metal layers7A. The substrate recess215A is formed in the conductive member24A. The substrate recess215A is recessed in the z direction from the metal layer242A toward the insulating substrate21. In the illustrated example, the substrate recess215A has a rectangular shape when viewed along the z direction. The inner surface of the substrate recess215A constitutes the substrate facing surface213A. The inner surface thereof includes four substrate facing surfaces213A. When viewed along the z direction, the intermediate metal layer7A is contained in the substrate recess215A. Portions where the substrate facing surface213A and the second facing surface712A face each other constitute the second positioning portion82of the second embodiment. Also in the second embodiment, the displacement of the semiconductor elements10A and10B can be suppressed. Further, according to the second positioning portion82of the second embodiment, it is possible to suppress the relative movement of the intermediate metal layers7A and7B with respect to the support substrate20(the conductive members24A and24B) in the x direction and the y direction. This is preferable for suppressing the displacement of the semiconductor elements10A and10B. <First Modification of Second Embodiment> FIGS.22and23show a first modification of the semiconductor device A2. A semiconductor device A21of the first modification is different from that of the above-described embodiment in the configuration of the support substrate20(the conductive member24A). AlthoughFIGS.22and23show the semiconductor element10A, the intermediate metal layer7A, and the conductive member24A, they have the same configurations as the semiconductor element10B, the intermediate metal layer7B, and the conductive member24B of the first modification, respectively, unless otherwise stated. The conductive member24A of the first modification includes a substrate protruding portion216A. The substrate protruding portion216A is a portion that protrudes from the conductive member24A on the side opposite to the insulating substrate21in the z direction. The substrate protruding portion216A has a rectangular annular shape when viewed along the z direction. By forming the substrate protruding portion216A, the substrate recess215A is provided in the conductive member24A. Similar to the semiconductor device A2, the inner surface of the substrate recess215A constitutes the substrate facing surface213A. Also in the first modification, the displacement of the semiconductor elements10A and10B can be suppressed. Further, as can be understood from the first modification, the detailed geometrical shapes of the semiconductor elements10A and10B, the intermediate metal layers7A and7B, and the conductive members24A and24B constituting the first positioning portion81and the second positioning portion82are not limited in any way. Third Embodiment FIGS.24to26show a semiconductor device according to a third embodiment of the present disclosure. The semiconductor device A3of the third embodiment is different from that of the above-described embodiment in the specific configuration of the second positioning portion82. AlthoughFIGS.24to26show the semiconductor element10A, the intermediate metal layer7A, and the conductive member24A, they have the same configurations as the semiconductor element10B, the intermediate metal layer7B, and the conductive member24B of the third embodiment, respectively, unless otherwise stated. The second positioning portion82of the third embodiment is composed of a welded portion91. The welded portion91is a portion where a portion of the intermediate metal layer7A and a portion of the conductive member24A (the support surface layer245A in the shown example) are welded. The welded portion91is provided at a position that avoids the semiconductor elements10A and10B when viewed along the z direction. A welding method for forming the welded portion91is not limited in any way, and may employ, for example, laser welding. A laser beam used for laser welding is not limited in any way. For example, a YAG laser, a second harmonic of the YAG laser, a YLF laser, a YVO4laser, a KrF laser, a CO2laser, a CO laser, or the like is appropriately used for laser welding. Also in the third embodiment, the displacement of the semiconductor elements10A and10B can be suppressed. Further, by forming the second positioning portion82with the welded portion91, it is possible to temporarily fix the intermediate metal layers7A and7B to the conductive members24A and24B, respectively, prior to solid phase diffusion bonding. As a result, the displacement of the semiconductor elements10A and10B can be further suppressed. Further, since the welded portion91is provided at the position that avoids the semiconductor elements10A and10B when viewed along the z direction, it is possible to prevent the welded portion91from obstructing the solid phase diffusion bonding. The semiconductor devices according to the present disclosure are not limited to the above-described embodiments. The specific configurations of parts of the semiconductor devices according to the present disclosure can be freely changed in design in various ways. For example, the semiconductor devices according to the present disclosure include embodiments related to the following Supplementary Notes. (Supplementary Note 1) According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer. (Supplementary Note 2) In the semiconductor device of Supplementary Note 1, in the first positioning portion, the portion of the semiconductor element and the first portion of the intermediate metal layer are engaged with each other. (Supplementary Note 3) In the semiconductor device of Supplementary Note 2, the semiconductor element includes an element facing surface that constitutes the first positioning portion, the intermediate metal layer includes a first facing surface that constitutes the first positioning portion, and the element facing surface and the first facing surface face each other in a direction intersecting the thickness direction. (Supplementary Note 4) In the semiconductor device of Supplementary Note 3, the intermediate metal layer includes a first recess that is recessed in the thickness direction from a side where the semiconductor element is located, and the first facing surface is an inner surface of the first recess. (Supplementary Note 5) In the semiconductor device of any one of Supplementary Notes 1 to 4, the intermediate metal layer and the support substrate are bonded to each other by solid phase diffusion bonding, and the semiconductor device further includes: a second positioning portion including a second portion of the intermediate metal layer and a portion of the support substrate and configured to suppress relative movement between the intermediate metal layer and the support substrate. (Supplementary Note 6) In the semiconductor device of Supplementary Note 5, in the second positioning portion, the second portion of the intermediate metal layer and the portion of the support substrate are engaged with each other. (Supplementary Note 7) In the semiconductor device of Supplementary Note 6, the intermediate metal layer includes a second facing surface that constitutes the second positioning portion, the support substrate includes a substrate facing surface that constitutes the second positioning portion, and the second facing surface and the substrate facing surface face each other in a direction intersecting the thickness direction. (Supplementary Note 8) In the semiconductor device of Supplementary Note 7, the intermediate metal layer includes a second recess that is recessed in the thickness direction from a side where the support substrate is located, and the second facing surface is an inner surface of the second recess. (Supplementary Note 9) In the semiconductor device of Supplementary Note 7, the support substrate includes a substrate recess that is recessed in the thickness direction from a side where the intermediate metal layer is located, and the substrate facing surface is an inner surface of the substrate recess. (Supplementary Note 10) In the semiconductor device of Supplementary Note 5, in the second positioning portion, the second portion of the intermediate metal layer and the portion of the support substrate are bonded to each other by welding. (Supplementary Note 11) In the semiconductor device of any one of Supplementary Notes 5 to 10, the semiconductor element includes a back surface metal layer bonded to the intermediate metal layer by solid phase diffusion bonding, and the back surface metal layer is made of a first metal. (Supplementary Note 12) In the semiconductor device of Supplementary Note 11, the intermediate metal layer includes a first layer bonded to the back surface metal layer of the semiconductor element by solid phase diffusion bonding, and the first layer is made of the first metal. (Supplementary Note 13) In the semiconductor device of Supplementary Note 12, the support substrate includes a support surface layer bonded to the intermediate metal layer by solid phase diffusion bonding, and the support surface layer is made of a second metal. (Supplementary Note 14) In the semiconductor device of Supplementary Note 13, the intermediate metal layer includes a second layer bonded to the support surface layer of the support substrate by solid phase diffusion bonding, and the second layer is made of the second metal. (Supplementary Note 15) In the semiconductor device of Supplementary Note 14, the intermediate metal layer includes a third layer interposed between the first layer and the second layer, and the third layer is made of a third metal softer than the first metal and the second metal. (Supplementary Note 16) In the semiconductor device of Supplementary Note 15, a thickness of the third layer is thicker than thicknesses of the first layer and the second layer. (Supplementary Note 17) In the semiconductor device of Supplementary Note 16, the first metal and the second metal contain Ag. (Supplementary Note 18) In the semiconductor device of Supplementary Note 17, the third layer contains Al. According to the present disclosure in some embodiments, it is possible to provide a semiconductor device capable of suppressing the displacement of semiconductor elements. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures. | 78,860 |
11862599 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A package component stack having alignment marks bonded to dummy alignment marks and the method of forming the same are provided. In accordance with some embodiments of the present disclosure, a first alignment mark is formed in a first package component, and is bonded to a first dummy alignment mark in a second package component. The first dummy alignment mark is not used for alignment purpose. Also, a second alignment mark may be formed in the second package component, and is bonded to a second dummy alignment mark in the first package component. By bonding alignment marks to dummy alignment marks instead of bonding to dielectric layers, the bonding strength is improved. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. FIGS.1-13and14Aillustrate the cross-sectional views of intermediate stages in the formation of a stack of package components including alignment marks and dummy alignment marks in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown inFIG.29. Referring toFIG.1, package component20is provided, which includes dies20′ therein. Package component20may further include substrate22. In accordance with some embodiments, substrate22is a semiconductor substrate, which may be formed of or comprises a crystalline silicon substrate. Substrate22may also be formed of or comprise other semiconductor materials such as silicon germanium, carbon-doped silicon, or the like. In accordance with some embodiments, package component20is a device wafer, which includes active devices and/or passive devices therein. In accordance with alternative embodiments, package component20is an interposer wafer, which is free from active devices and passive devices therein. In accordance with alternative embodiments, package component20is a reconstructed wafer, which includes discrete dies encapsulated in an encapsulant (such as a molding compound), and redistribution lines formed to connect to the discrete dies. Package component20is referred to as wafer20hereinafter, which includes a plurality of dies20′ therein. In accordance with some embodiments, device dies20′ include active circuits (not shown), which include active devices such as transistors (not shown) formed at the top surface of semiconductor substrate22. In accordance with alternative embodiments in which wafer20is an interposer wafer, there is no active circuit at the top surface of wafer20. Through-vias (sometimes referred to as Through-Silicon Vias (TSVs))26may be formed to extend into substrate22. TSVs26are also sometimes referred as through-silicon vias when formed in a silicon substrate. Each of TSVs26may be encircled by an isolation liner (not shown), which is formed of a dielectric material such as silicon oxide, silicon nitride, or the like. The isolation liners isolate the respective TSVs26from semiconductor substrate22. TSVs26and the isolation liners extend from a top surface of semiconductor substrate22to an intermediate level between the top surface and the bottom surface of semiconductor substrate22. Over substrate22may include an Inter-Layer Dielectric (ILD, not shown separately), which fills the space between the gate stacks of transistors in integrated circuit devices22. In accordance with some embodiments, the ILD may be formed of Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-Doped Phospho Silicate Glass (BPSG), Fluorine-Doped Silicate Glass (FSG), silicon oxide, or the like. Contact plugs (not shown) are formed in the ILD, and are used to electrically connect integrated circuit devices22to overlying conductive features. In accordance with some embodiments of the present disclosure, the contact plugs are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys therefore, and/or multi-layers thereof. The formation of the contact plugs may include forming contact openings in the ILD, filling a conductive material(s) into the contact openings, and performing a planarization process (such as Chemical Mechanical Polish (CMP) process or a mechanical grinding process) to level the top surfaces of the contact plugs with the top surface of the ILD. Interconnect structure27is formed over semiconductor substrate22. Interconnect structure27may include the ILD, contact plugs, a plurality of dielectrics layers28, and metal lines/pads30and vias32formed in dielectric layers28. Metal lines/pads30and vias32are electrically connected to TSVs26and the integrated circuits. Dielectric layers28may comprise one or more Inter-Metal-Dielectric (IMD) layers. The IMD layers may be formed of low-k dielectric materials having low k values, which may be, for example, lower than about 3.0, or in the range between about 2.5 and about 3.0. The low-k dielectric material may be a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with alternative embodiments, dielectric layers28are formed of or comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and/or multi-layers thereof. Metal lines/pads30are formed in dielectric layers28. Vias32are formed in dielectric layers28to interconnect metal lines/pads30. The metal lines/pads30in the topmost IMD28are also referred to as top metal lines/pads30T. In accordance with some embodiments, the top metal lines/pads30T are the metal lines/pads formed in the topmost inorganic low-k dielectric layers in interconnect structure27, and the dielectric layer/layers33overlying the top metal lines/pads are non-low-k dielectric layers, polymer layers, or the like. For example, the non-low-k dielectric layers33may include dielectric layers33having k values greater than 3.9, and may be formed of or comprise undoped silicate glass (USG), silicon oxide, silicon nitride, or the like, composite layers thereof, and/or combinations thereof. The dielectric layer/layers33may also include polymer layers, which may be formed of or comprise polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. Metal pads34may be formed in dielectric layers33. Immediately above top metal lines/pads30T, there may be the first (non-low-k) passivation layer, and metal pads34may extend into the first passivation layer, with the first passivation layer in contact with the topmost dielectric layer28and top metal lines/pads30T. A second passivation layer may extend on the edges and the top surfaces of metal pads34. The passivation layers may be formed of silicon oxide, silicon nitride, USG, or the like. Metal pads34may be formed of or comprise aluminum, aluminum copper, copper, nickel, or the like. There may be, or may not be, Post Passivation Interconnect (PPI) formed over and connecting to metal pads34. Dielectric layer36is deposited over metal pads34as a surface dielectric layer of wafer20. Dielectric layer36may be formed of or comprise PBO, polyimide, silicon oxide, silicon nitride, or the like. Referring toFIG.2, wafer20is placed on release film12, which is further coated on carrier10. The respective process is illustrated as process202in the process flow200as shown inFIG.29. The front side of wafer20, which is the side of the substrate22having the active devices and interconnect structure27, faces carrier10in accordance with some embodiments. In accordance with alternative embodiments, the backside of wafer20may face carrier10instead. Carrier10is formed of a transparent material, and may be a glass carrier, a ceramic carrier, or the like. Release film12may be formed of a Light-To-Heat-Conversion (LTHC) coating material. In accordance with some embodiments of the present disclosure, the LTHC coating material is capable of being decomposed under the heat of light/radiation (such as a laser beam), and hence can release carrier10from the structure formed thereon. A buffer layer (not shown) may be formed on release film12, with wafer20being placed over the buffer layer. In accordance with some embodiments, the buffer layer may be formed of or comprises a polymer such as polyimide, PBO, BCB, or the like. In accordance with alternative embodiments, the buffer layer is not formed. Referring toFIG.3, a backside grinding process is performed to remove a portion of substrate22, until through-vias26are revealed. The respective process is illustrated as process204in the process flow200as shown inFIG.29. Next, as also shown inFIG.3, substrate22may be recessed slightly (for example, through etching), so that the top portions of through-vias26protrude out of the back surface of substrate22. The respective process is illustrated as process206in the process flow200as shown inFIG.29. Next, a dielectric layer40is deposited, followed by a planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process to re-expose through-vias26, forming the structure shown inFIG.4. The respective process is illustrated as process208in the process flow200as shown inFIG.29. In the resulting structure, through-vias26penetrate through both of substrate22and dielectric layer40. In accordance with some embodiments, dielectric layer40is formed of or comprises silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, or the like. Referring toFIG.4, dielectric layer42is deposited. The respective process is illustrated as process210in the process flow200as shown inFIG.29. In accordance with some embodiments, as shown inFIG.5, dielectric layer42is in contact with dielectric layer40and through-vias26, and there is no additional dielectric layer and redistribution lines (RDLs) in between. In accordance with alternative embodiments of the present disclosure, there may be one or a plurality of dielectric layers between dielectric layers40and42. There may also be one or a plurality of layers of RDLs in the dielectric layers, which RDLs are electrically connected to through-vias26. Dielectric layer42may comprise or may be formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like. In the illustrated example, the subsequently formed bond pads and alignment marks are formed through a single damascene process. In accordance with alternative embodiments, dual damascene processes are adopted, and vias are also formed underlying and connecting the subsequently formed bond pads to through-vias26. Further referring toFIG.4, openings44are formed in dielectric layer42. To form openings44, a photo resist (not shown) and possibly a hard mask (not shown) may be formed over dielectric layer42, and are patterned to define the patterns of openings44. In accordance with some embodiments of the present disclosure, an anisotropic etching process is performed to etch dielectric layer42, and to form openings44. In accordance with some embodiments in which no RDLs are formed over through-vias26, through-vias26are exposed to openings44. In accordance with alternative embodiments in which RDLs are formed, the RDLs are exposed to openings44. FIG.5illustrates the formation of bond pads48, alignment mark50-AM, and dummy alignment mark50-DAM. The respective process is illustrated as process212in the process flow200as shown inFIG.29. The formation process may include depositing a diffusion barrier, depositing a conductive material (metallic material) over the diffusion barrier, and performing a planarization process to remove excess diffusion barrier layer and conductive material. In accordance with some embodiments of the present disclosure, the diffusion barrier is formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The diffusion barrier may be formed, for example, using Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or the like. The metallic material may be deposited, for example, through an Electro-Chemical Plating (ECP) process. The metallic material may include copper or copper alloy, tungsten, aluminum, silver, alloys thereof, or another metallic material that can diffuse in a subsequent anneal process, so that metal-to-metal direct bonding may be formed. Bond pads48, alignment mark50-AM, and dummy alignment mark50-DAM are thus formed in surface dielectric layer42. The diffusion barrier layer in each of bond pads48, alignment mark50-AM, and dummy alignment mark50-DAM may have the shape of a basin, and the metallic material is located in the basin. For example, as shown inFIGS.27and28, each of alignment mark50-AM, and dummy alignment mark50-DAM includes diffusion barrier49A and metallic material49B. In a top view, the diffusion barriers may encircle the metallic materials in the corresponding bond pads48, alignment mark50-AM, and dummy alignment mark50-DAM. It is appreciated that the electrical connection of some of bond pads48to the corresponding through-vias26are not shown, while these electrical connections are also formed. In accordance with some embodiments, alignment mark50-AM and dummy alignment mark50-DAM are electrically floating, and all materials (such as dielectric layers40and42) underlying and contacting alignment mark50-AM and dummy alignment mark50-DAM may be dielectric materials. Furthermore, all materials surrounding and contacting each of alignment mark50-AM and dummy alignment mark50-DAM may be dielectric materials. In accordance with alternative embodiments, some or all of alignment mark50-AM and dummy alignment mark50-DAM may be connected to through-vias for connecting to electrical ground, power supply voltage VDD, or signal lines. The wafer20may be used to perform the subsequently discussed bonding process at wafer level, wherein a wafer-to-wafer bonding is performed as an example. In accordance with alternative embodiments, a singulation process is performed to saw wafer20apart, so that dies20′ are separated into discrete dies. The discrete dies20′ are then used to form die stacks at die level. In the subsequent discussion, the wafer-to-wafer bonding is used as an example, and the die-to-die bonding are also in the scope of the present disclosure. The corresponding wafer20or die20′ are also referred to as package components to indicate that wafers/dies are example, while the present disclosure also apply to the bonding of other types of package components such as packages. Referring toFIG.6, package component120is provided. Package component120may also be a wafer, which may include dies120′ therein. Package component120may be a device wafer, an interposer wafer, a reconstructed wafer, or the like. In subsequent discussion, a device wafer is used as an example, while the discussion may also be applied to other types of package components. As aforementioned, the bonding may also be at die level, and hence package component120′ may also be a discrete die. In accordance with some embodiments, wafer120includes similar features as what have been discussed for wafer20. The like features in wafer120may be identified by adding “100” to the feature numbers of the corresponding features in wafer20. For example, wafer120may include substrate122, through-vias126, metal lines/pads130, top metal lines/pads130T, vias132, dielectric layers128and133, metal pads134, surface dielectric layer142, bond pads148, alignment mark150-AM, and dummy alignment mark150-DAM. Unless specified otherwise, the formation processes and the materials of the features in wafer120may be similar to that of their corresponding features in wafer20, and the details are not repeated herein. It is appreciated, however, the circuits and structures in wafer120may be the same as (except the alignment marks and dummy alignment marks) or different from what are in wafer20. FIG.15illustrates an example top view of alignment mark150-AM and dummy alignment mark150-DAM in wafer120(as shown inFIG.6) in accordance with some embodiments. It is appreciated that the patterns of the illustrated alignment marks and dummy alignment marks throughout the description are examples, and the alignment marks and dummy alignment marks may have any applicable arrangements and shapes. Alignment mark150-AM may include one or a plurality of features (which are also referred to as patterns), which are formed in the same formation process as forming bond pads148(FIG.6). The formation processes and the materials may be similar to that of bond pads48, as above-discussed. The plurality of features in alignment mark150-AM collectively form a pattern that may be recognized by an aligner, which may be a part of a bonding apparatus for bonding wafer120to wafer20. Dummy alignment mark150-DAM also includes a plurality of features, which are formed in the same formation process as for forming bond pads148(FIG.6) and alignment mark150-AM. Throughout the description, when the term “alignment mark” or “dummy alignment mark” is used, it may refer to the features collectively, or the individual features inside the collective pattern, depending on the context. It is appreciated that although alignment mark150-AM and dummy alignment mark150-DAM are located in the same chip area, the aligner searches for, and recognizes the pattern of, alignment mark150-AM, while the pattern of dummy alignment mark150-DAM is not searched for by the aligner. Rather, the features in dummy alignment mark150-DAM are treated by the aligner as environmental features or a background pattern. Accordingly, dummy alignment mark150-DAM is a “dummy” alignment mark since it does not have the function of being used for aligning purpose, even if it may intermix with alignment mark150-AM. FIG.16illustrates an example top view of alignment mark50-AM and dummy alignment mark50-DAM in wafer20(FIG.6) in accordance with some embodiments. Alignment mark50-AM may also include one or a plurality of features, which are formed in the same formation process as for forming bond pads48(FIGS.4and5). The plurality of features in alignment mark50-AM collectively form a pattern that may be recognized by the aligner, which may be a part of the bonding apparatus. Dummy alignment mark50-DAM may also include a plurality of features, which are formed in the same formation process as bond pads48and alignment mark50-AM. It is appreciated that although alignment mark50-AM and dummy alignment mark50-DAM are located in the same chip area, the aligner searches for, and recognizes the pattern of, alignment mark50-AM, while the pattern of dummy alignment mark50-DAM is not searched for by the aligner. Rather, the features of dummy alignment mark50-DAM are treated by the aligner as environmental pattern or a background pattern. Accordingly, dummy alignment mark50-DAM is a “dummy” alignment mark since it does not have the function of being used for aligning purpose. Referring back toFIG.6, the aligner of the bonding instrument searches and recognizes the pattern of alignment mark50-AM of wafer20. The aligner of the bonding instrument also searches and recognizes the pattern of alignment mark150-AM of wafer120. With the relative positions of wafers20and120known, an alignment process may be performed to align wafer120to wafer20. The respective process is illustrated as process214in the process flow200as shown inFIG.29. Referring toFIG.7, with wafer120being aligned to wafer20, a bonding process is performed to bond wafer120to wafer20. The respective process is illustrated as process216in the process flow200as shown inFIG.29. The bonding process may be performed through hybrid bonding. Accordingly, the surface dielectric layer142in wafer120is bonded to the surface dielectric layer42in wafer20through fusion bonding, for example, with Si—O—Si bonds formed between surface dielectric layer142and surface dielectric layer42. Alignment mark150-AM are bonded to the respective dummy alignment mark50-AM through metal-to-metal bonding (with metal inter-diffusion), and dummy alignment mark150-DAM are bonded to alignment mark50-AM through metal-to-metal bonding (with metal inter-diffusion). FIG.17illustrates a top view of the bonded alignment mark50-AM, dummy alignment mark50-DAM, alignment mark150-AM, and dummy alignment mark150-DAM in accordance with some embodiments. The features/patterns in alignment mark150-AM overlap and bond to the corresponding features/patterns in dummy alignment mark50-DAM in a one-to-one correspondence. The features/patterns in dummy alignment mark150-DAM overlap and bond to the features/patterns in alignment mark50-AM in a one-to-one correspondence. In accordance with some embodiments, there may not be any alignment mark50-AM overlapping and bonding to alignment mark150-AM, and there may not be any alignment mark150-AM underlying and bonding to alignment mark50-AM. In accordance with alternative embodiments, some, but not all, of the features/patterns in alignment mark150-AM overlap some, but not all, the features/patterns in alignment mark50-AM, while there are still some other features/patterns in alignment mark150-AM overlapping some of the features/patterns in alignment mark50-AM, and there are still some features/patterns in alignment mark50-AM underlying some of the features/patterns in dummy alignment mark150-DAM. In accordance with some embodiments, alignment mark150-AM, dummy alignment mark150-DAM, alignment mark50-AM, and dummy alignment mark50-DAM are electrically floating (when the respective final package is used and powered up). In accordance with alternative embodiments, some or all of alignment mark150-AM, dummy alignment mark50-AM, alignment mark150-AM, and dummy alignment mark50-AM may be connected to electrical ground, power supply voltage VDD, and/or signal lines in any combinations, while the rest (if any) are electrically floating. Referring toFIG.8, a backside grinding process is performed on the backside of substrate122, so that through-vias126are exposed. The respective process is illustrated as process218in the process flow200as shown inFIG.29. Next, substrate122is recessed slightly (for example, through etching), so that the top portions of through-vias126protrude out of the back surface of substrate122. Next, a dielectric layer140′ is deposited, followed by a planarization process such as a CMP process or a mechanical grinding process to re-expose through-vias26. Referring toFIG.9, dielectric layer(s)142′ is deposited. Additional dielectric layers and RDLs (not shown) may be, or may not be, formed between dielectric layer142′ and substrate122. A patterning process is then performed to form openings144in dielectric layer(s)142′. In subsequent processes, as shown inFIG.10, dummy alignment mark150-DAM′ and alignment mark150-AM′ are formed. The respective process is illustrated as process220in the process flow200as shown inFIG.29. The structures, materials, and formation processes may be essentially the same as dummy alignment mark50-DAM′ and alignment mark150-AM′. FIG.11illustrates the stacking of more wafers (if any) over wafer120in accordance with some embodiments until a top wafer is bonded. The respective process is illustrated as process222in the process flow200as shown inFIG.29. In accordance with alternative embodiments, no more wafer (or die) is bonded over wafer120(or die120′). The bonding processes may be performed using alignment marks, which are bonded to dummy alignment marks, similar to the bonding of underlying wafers/dies. The top wafer is identified as20-n, with the sequence number n being 2 or greater, indicating that there are two wafers (wafers20and120, with n being equal to 2) or up to n wafers stacked together. In the previous illustrated bonding of wafer120to wafer20, a face-to-back bonding is illustrated as an example, while the bonding of any wafer to the underlying wafer may also be a face-to-face bonding or a back-to-back bonding. For example,FIG.11illustrates that wafer20-nhas its back surface facing the underlying wafer stack (die stack), so the corresponding bonding will be either back-to-face bonding or back-to-back bonding, depending on the orientation of the immediate underlying wafer/die. FIG.11also illustrates the formation of Under-Bump-Metallurgies (UBMs)52-n. Each of UMBs52-nmay include a barrier layer (such as a titanium layer) and a metal layer (comprising copper, aluminum, nickel, palladium, or the like) over the titanium layer. The formation process may include etching a surface dielectric layer of the top wafer20-nto form openings, and depositing the barrier layer and the metal layer, for example, using PVD. The deposited titanium layer and the copper layer are patterned to form the UBMs52-nas illustrated. FIG.12illustrates the formation of electrical connectors54-n, each may be formed of or comprise a metal pillar such as a copper pillar, a solder region, or a metal pillar and a solder layer on the copper pillar. The respective process is illustrated as process224in the process flow200as shown inFIG.29. The formation process may include placing solder balls on UBMs52-n, and then performing a reflow process to reflow the solder balls. Alternatively, the formation of UBMs52-nand electrical connectors54-nmay include depositing a metal seed layer, forming a patterned plating mask over the metal seed layer, plating electrical connectors54-nin the openings in the plating mask, removing the plating mask, and etching the metal seed layer. Throughout the description, the stacked wafers are collectively referred to as a wafer stack60. In a subsequent process, wafer stack60is de-bonded from carrier10. The respective process is illustrated as process226in the process flow200as shown inFIG.29. For example, a laser beam may be projected on release film12, so that release film12is decomposed, releasing wafer stack60. In subsequent processes, the wafer stack60may be flipped upside down, and is placed on another carrier (not shown) or tape62, which is fixed on frame64, as shown inFIG.13. Electrical connectors66may then be formed on the front side of wafer20. The respective process is illustrated as process228in the process flow200as shown inFIG.29. Electrical connectors66may include solder regions. In accordance with alternative embodiments, electrical connectors66are formed before placing wafer20(as shown inFIG.2) on carrier10. In accordance with some embodiments in which the wafer-level bonding is performed, a singulation process may be performed to saw wafer stack60along scribe lines67. Die stack60is sawed apart into discrete packages60′. The respective process is illustrated as process230in the process flow200as shown inFIG.29. FIG.14Aillustrates an example in which package60′ is bonded to package component68, which may be another package, an interposer, a package substrate, a printed circuit board, or the like. Underfill70may be dispensed into the gap between package60′ and package component68. Package72is thus formed. Package60′ may also be bonded to an overlying package component (not shown) through electrical connectors66. FIGS.14B,18,19, and20in combination illustrate package72in accordance with an alternative embodiment.FIG.14Billustrates a cross-sectional view of package72. Alignment mark50-AM is formed on the surface of wafer20, and in surface dielectric layer42. The formation process may be essentially the same as described in previous embodiments. Dummy alignment mark150-DAM is formed on the surface of wafer120, and in surface dielectric layer142. The features in dummy alignment mark150-DAM overlap, and are bonded to, the features in dummy alignment mark50-DAM with a one-to-one correspondence. In the alignment of wafer120to wafer20, alignment mark50-DAM is searched for by an aligner, and is used for the aligning and the positioning of wafer20. Dummy alignment mark50-DAM and alignment mark150-AM may be, or may not be, formed in wafer20and120, respectively. The aligning and positioning of wafer120, on the other hand, is not performed by using dummy alignment mark150-DAM. Rather, the alignment is performed by using an embedded alignment mark, which is embedded inside wafer120, rather than being on the surface of wafer120. An example embedded alignment mark is130T-AM. Alignment mark130T-AM is also illustrated inFIG.14Ausing dashed lines to indicate that it may, or may not be formed. In accordance with some embodiments, the embedded alignment mark (130T-AM in the illustrated embodiments) may be in the top metal layer (the same metal layer of top metal lines/pads130T). The embedded alignment mark130T-AM is formed in the same process as for forming the metal lines/pads130in the top metal layer of the wafer120. To allow embedded alignment mark130T-AM to be seen in the alignment process, the upper dielectric layers in wafer120covering the embedded alignment mark130T-AM are transparent. The upper dielectric layers may include surface layer142and the dielectric layers between surface layer142and the embedded alignment mark. In accordance with alternative embodiments, the embedded alignment mark may be in another layer between the top metal layer130and surface layer142. For example, the embedded alignment mark may be in the layer of metal pads34. Alternatively, the embedded alignment mark may in a dielectric layer in which PPIs (if any) are formed, which dielectric layer is between metal pads34and surface layer142. FIG.18illustrates a top view of dummy alignment mark150-DAM and embedded alignment mark130T-AM in wafer120in accordance with some embodiments. In the illustrated example, dummy alignment mark150-DAM includes circular features therein, and the features may be arranged aligning to a letter (such as “Z” in the illustrated example). Embedded alignment mark130T-AM may form a ring. In the top view or the bottom view of wafer120, the ring encircles dummy alignment mark150-DAM. Again, it is appreciated that the patterns and the shapes of the illustrated alignment marks and dummy alignment marks throughout the description are examples, and these marks may have any applicable arrangements and shapes that can be identified by the aligner. For example, in the top view, embedded alignment mark130T-AM may be aside of dummy alignment mark150-DAM, or may have another pattern/shape such as different letters, elongated strips, rectangular shapes, hexagonal shapes, or the like. FIG.19illustrates a top view of alignment mark50-AM in wafer20in accordance with some embodiments. The features in alignment mark50-AM may have a same arrangement as dummy alignment mark150-DAM (for example, aligned to a letter).FIG.20illustrates the top view of the (dummy) alignment marks after the bonding of wafer120to wafer20. The features in dummy alignment mark150-DAM may be bonded to the corresponding features in alignment mark50-AM with a one-to-one correspondence. Alignment mark130T-AM, on the other hand, is not bonded to any dummy alignment mark in wafer20since alignment mark130T-AM is embedded, and is spaced apart from wafer20by surface dielectric layer142. In accordance with some embodiment, as discussed above, embedded alignment mark (such as130T-AM) is formed in wafer120, and there is no alignment mark (such as150-AM) at the surface of in wafer120. Accordingly, the positioning of wafer120and the alignment of wafer120to wafer20are based on embedded alignment mark (such as130T-AM) in wafer120, but not on the alignment mark at the surface of wafer120. In accordance with alternative embodiments, both of alignment mark150-AM and embedded alignment mark130T-AM are formed in wafer120, and both of alignment mark50-AM and dummy alignment mark50-DAM are formed in wafer20. The positioning of wafer120and the alignment of wafer120to wafer20are thus based on both of alignment mark150-AM and embedded alignment mark130T-AM in wafer120. Accordingly, inFIG.14B, dummy alignment mark150-DAM and alignment mark50-DAM are illustrated as being dashed to indicate these features may be, or may not be, formed. FIGS.21,22, and23illustrate the alignment marks and dummy alignment marks in accordance with alternative embodiments. The cross-sectional view of the corresponding (dummy) alignment marks may also be represented byFIG.14B, which illustrates embedded alignment mark130T-AM, dummy alignment mark150-DAM, and alignment mark50-AM. Referring toFIG.21, embedded alignment mark130T-AM includes a plurality of elongated strips, and dummy alignment mark150-DAM includes a plurality of circular feature aligned to a plurality of straight lines.FIG.22illustrates alignment mark50-AM, which includes a plurality of circular patterns aligned to a plurality of straight lines.FIG.23illustrates the top view of the (dummy) alignment marks after the bonding of wafer120to wafer20. The upper alignment mark50-AM is drawn as transparent inFIG.23to show the underlying dummy alignment mark150-DAM, but is not limited to transparent materials. The features in dummy alignment mark150-DAM are bonded to the corresponding features in alignment mark50-AM with a one-to-one correspondence. Alignment mark130T-AM, on the other hand, is not bonded to any dummy alignment mark in wafer20. FIGS.24,25, and26illustrate the alignment marks and dummy alignment marks in accordance with alternative embodiments. The cross-sectional view of the corresponding (dummy) alignment marks may also be represented byFIG.14B, which illustrates embedded alignment mark130T-AM, dummy alignment mark150-DAM, and alignment mark50-AM. Referring toFIG.24, embedded alignment mark130T-AM includes a plurality of elongated strips, and dummy alignment mark150-DAM includes a plurality of circular patterns arranged as an array. The arrangement of the patterns in dummy alignment mark150-DAM as an array may make the pattern density more uniform, so that a larger alignment mark may be formed without worsening pattern loading effect. In accordance with some embodiments, the embedded alignment mark130T-AM may overlap (or overlapped by depending on the viewing orientation) some of the patterns in dummy alignment mark150-DAM. In accordance with alternative embodiments, the embedded alignment mark130T-AM may overlap all of the patterns in dummy alignment mark150-DAM.FIG.25illustrates alignment mark50-AM, which includes a plurality of circular patterns that also form an array. In accordance with some embodiments, as shown inFIGS.24and25, the array of dummy alignment mark150-DAM (and the array of alignment mark50-AM) have non-uniform spacings and include sub-arrays with uniform spacings. In accordance with alternative embodiments, all of alignment mark50-AM and dummy alignment mark50-DAM may have a uniform spacing.FIG.26illustrates the top view of the (dummy) alignment marks after the bonding of wafer120to wafer20. The upper alignment mark50-AM is drawn as transparent inFIG.26to show the underlying dummy alignment mark150-DAM, but is not limited to transparent materials. The features in dummy alignment mark150-DAM are bonded to the corresponding features in alignment mark50-AM with a one-to-one correspondence. Alignment mark130T-AM, on the other hand, is not bonded to any dummy alignment mark in wafer20. Referring again toFIGS.15through26, it is observed that dummy alignment marks and alignment marks may have rectangular contours. The contours of the alignment marks are the rectangles drawn aligning to the edges of alignment marks. For example, as shown inFIG.21, alignment mark130T-AM has contour174-AM, and dummy alignment mark150-DAM has contour174-DAM. As shown inFIG.22, alignment mark50-AM has contour74-AM. As shown inFIG.23, contours174-AM,174-DAM, and74-AM have overlapped area, and occupy the same chip area of package72(FIG.14B). The overlapping of contour areas may be partial overlapping, with a part of a first contour area occupied by the dummy alignment mark partially overlapping a part of a second contour area occupied by the alignment mark. There is, however, at least a part of the first contour area or the second contour area not overlapped by the other with the partial overlapping. Alternatively, the overlapping may be full overlapping, with the first contour area and the second contour area occupy the exact same chip area of package72(FIG.14B). In addition, as shown inFIGS.15through26, in the top view of wafers20and/or120, the patterns of the dummy alignment mark and the patterns of the corresponding alignment mark may be inter-mixed. For example, at least one of the features of dummy alignment marks50-DAM (or150-DAM) may be inserted between the features of the corresponding alignment marks50-AM (or150-AM). Also, at least one of the features of alignment marks50-AM (or150-AM) may be inserted between the features of the corresponding dummy alignment marks50-DAM (or150-DAM). FIG.27illustrates an embodiment in which the alignment marks and/or dummy alignment marks in wafer120have different sizes than the alignment marks and/or dummy alignment marks in wafer20. For example, in the illustrated embodiments, alignment marks150-AM and dummy alignment marks150-DAM in wafer120are smaller (in lateral dimension) than the corresponding dummy alignment marks50-DAM and alignment marks50-AM in wafer20. This is also illustrated in the example embodiment as shown inFIG.17. In accordance with alternative embodiments as shown inFIG.28, the alignment marks and/or dummy alignment marks in wafer120have the sizes same as, or greater than, the alignment marks and/or dummy alignment marks in wafer20. In above-illustrated embodiments, some processes and features are discussed in accordance with some embodiments of the present disclosure to form a three-dimensional (3D) package. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. The embodiments of the present disclosure have some advantageous features. By forming dummy alignment marks together with alignment marks, the dummy alignment marks of one wafer, although not used for alignment, may form metal-to-metal bonding with the alignment marks of another wafer. Accordingly, the non-bonding issue that occurred in the bonding using conventional alignment marks is avoided, and the bonding quality of hybrid bonding is improved. In accordance with some embodiments of the present disclosure, a method comprises placing a first package component, wherein the first package component comprises a first alignment mark; and a first dummy alignment mark; aligning a second package component to the first package component, wherein the second package component comprises a second alignment mark; and a second dummy alignment mark, wherein the aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for positioning the second package component; and bonding the second package component to the first package component to form a package, wherein after the bonding, the first alignment mark is bonded to the second dummy alignment mark. In an embodiment, the first alignment mark comprises a first plurality of discrete features, the second dummy alignment mark comprises a second plurality of discrete features, and wherein the first plurality of discrete features are bonded to the second plurality of discrete features with a one-to-one correspondence. In an embodiment, after the bonding, the second alignment mark is bonded to the first dummy alignment mark. In an embodiment, the first alignment mark comprises a first plurality of discrete features, the first dummy alignment mark comprises a second plurality of discrete features, and wherein the first plurality of discrete features and the second plurality of discrete features are inter-mixed. In an embodiment, a first surface dielectric layer in the first package component is bonded to a second surface dielectric layer in the second package component through fusion bonding, and the first alignment mark is bonded to the second dummy alignment mark through metal-to-metal direct bonding. In an embodiment, the second alignment mark is an embedded alignment mark, and after the bonding, the second alignment mark is physically spaced apart from the first package component. In an embodiment, the bonding the second package component to the first package component comprises bonding a second wafer to the first wafer. In an embodiment, the first alignment mark has a first outer contour, and the first dummy alignment mark has a second outer contour, and wherein the first outer contour at least partially overlaps the second outer contour. In an embodiment, the first alignment mark comprises a first plurality of discrete features, the second dummy alignment mark comprises a second plurality of discrete features, and wherein each of the first plurality of discrete features is smaller than a corresponding one of the second plurality of discrete features. In an embodiment, the first alignment mark comprises a first plurality of discrete features, the second dummy alignment mark comprises a second plurality of discrete features, and wherein each of the first plurality of discrete features has a same size as, and fully overlaps, a corresponding one of the second plurality of discrete features. In accordance with some embodiments of the present disclosure, a method comprises aligning a first wafer to a second wafer using a first alignment mark in the first wafer and a second alignment mark in the second wafer, wherein the second alignment mark is in a same chip area as a dummy alignment mark in the second wafer; and bonding the first wafer to the second wafer through hybrid bonding, wherein after the bonding, the first alignment mark in the first wafer is bonded to the dummy alignment mark in the second wafer. In an embodiment, after the bonding, the second alignment mark in the second wafer is bonded to an additional dummy alignment mark in the first wafer. In an embodiment, the second alignment mark in the second wafer is embedded in the second wafer, and after the bonding, the second alignment mark is separated from the first wafer by a dielectric layer in the second wafer. In an embodiment, the second alignment mark comprises a ring, and in a top view of the second wafer and the first wafer, the ring encircles the second dummy alignment mark and the first alignment mark. In an embodiment, the first alignment mark and the dummy alignment mark comprise circular patterns. In accordance with some embodiments of the present disclosure, a method comprises searching for a first alignment mark in a first package component, wherein the first package component further comprises a first dummy alignment mark occupying a same chip area as the first alignment mark; searching for a second alignment mark in a second package component, wherein the second package component further comprises a second dummy alignment mark occupying a same chip area as the second alignment mark; aligning the second package component to the first package component using the first alignment mark and the second alignment mark; and bonding the second package component with the first package component. In an embodiment, during the searching for the first alignment mark, the first dummy alignment mark is not searched for. In an embodiment, after the bonding, the first alignment mark is bonded to the second dummy alignment mark, and the second alignment mark is bonded to the first dummy alignment mark. In an embodiment, a plurality of first discrete patterns in the first alignment mark are bonded to a plurality of second discrete patterns in the second dummy alignment mark with a one-to-one correspondence. In an embodiment, a plurality of third discrete patterns in the second alignment mark are bonded to a plurality of fourth discrete patterns in the first dummy alignment mark with a one-to-one correspondence. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 47,338 |
11862600 | DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The word “over” used with regards to a deposited material formed “over” a side or surface, may be used herein to mean that the deposited material may be formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over” used with regards to a deposited material formed “over” a side or surface, may be used herein to mean that the deposited material may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material. Various aspects of the disclosure are provided for devices, and various aspects of the disclosure are provided for methods. It will be understood that basic properties of the devices also hold for the methods and vice versa. Therefore, for sake of brevity, duplicate description of such properties may have been omitted. In various embodiments, a deep drawing of a metalized dielectric (e.g. plastic) foil (the dielectric foil may also be referred to as “carrier”) or of a copper foil may be used to form 3D interconnects. The metallization may in various embodiments be pre structured. This may allow to provide a batch front side (FS) interconnect method including hetero-integration of logic- and power chips by providing interconnects having different metal thicknesses. In various embodiments, a method of forming a semiconductor chip package is provided that uses a parallel/semi-parallel process instead of wire bonding. The process may be flexible enough to allow a variety of products and adaptions for process variations. Additionally, the precision may be improved by an optimized process sequence. In various embodiments, the wiring of the package may be achieved by a combination of metal foils and a malleable (formable) dielectric material (the carrier), preferably a polymer material. The metal foil and/or the carrier may be structured to achieve a desired functionality and may afterwards be pressed over the chip. Thereby, the metal foil (and the carrier, if present) may be formed into a 3D-structure, forming the electrical interconnects as well as all required contacts. In other words, a redistribution layer may be formed. An additional molded encapsulation may in various embodiments be provided for mechanical stability and robustness. In various embodiments, general principles of metal forming (deep-drawing) and connection (ultrasonic welding, soldering, conductive glue) may be combined to form electrical contacts and a connection layer for the chip. Each ofFIGS.1to3,6,7,9A, and9Bschematically illustrates, as sequences of two or more schematic cross-sectional views, a method of forming a chip package100in accordance with various embodiments. InFIGS.3and6, a top view outlining all of the vertically stacked structures is additionally provided to enhance an understanding of where the cross section is located. As shown in each ofFIGS.1to3,6,7,9A, and9B, a malleable carrier112with a layer of an electrically conductive material (“layer” for short)110formed thereon may be provided. In various embodiments, the malleable carrier112(together with the layer110) may be positively fitted to a chip102to at least partially enclose the chip102with the malleable carrier112(and the layer110). The chip102may include a semiconductor substrate108, and chip contacts104. Around the chip contacts104, a dielectric material106may be arranged. At least one of the chip contacts104may be arranged on a front side102F of the chip102. In various embodiments, another of the chip contacts104may be arranged on a back side102B of the chip102. By the positive fitting process, it may be achieved that the layer110at least partially physically contacts the chip102, such that the layer110electrically contacts at least one of the chip contacts104of the chip102. The layer may form a redistribution layer. At least one of the chip contacts104may in various embodiments be free from the (redistribution) layer110and may be referred to as a further chip contact104. The further chip contact104and a portion of the layer110(which may form the redistributed contact) may be exposed at the same side. The side of the package100where electrical contacts are exposed (redistributed chip contacts formed by portions of the layer110and, optionally, original chip contacts104) may be referred to as a front side100F of the chip package100. In the exemplary embodiment ofFIGS.1and2, the front side102F chip contacts104are unconnected to the layer110, and are exposed together with the redistributed backside chip contact104at the front side100F of the chip package100. In the exemplary embodiments ofFIGS.1and2, only one redistributed chip contact is formed, namely the redistributed chip backside contact. This embodiment may be fully capable of forming a DirectFET-like package. Since the chip sides may be on drain potential anyhow, an insulation between the layer110and the chip side surfaces may not be necessary. Nevertheless, an adhesion promoter770or an adhesive chip insulation layer552may be provided at the sides of the chip102in various embodiments (see for exampleFIG.5orFIG.7). In various embodiments, the layer110along the sides of the chip102may carry a different potential than the semiconductor substrate108, which may have significant conductivity. A lack of insulation between the layer110and the semiconductor substrate108may in that case result in a short in the related contacts104. An additional chip side insulation layer440,552, which may optionally additionally act as an adhesion layer552, may therefore be provided in various embodiments (see for exampleFIG.4,FIG.5orFIG.7). The insulation layer440,552or the adhesion promoter770may in various embodiments be provided on sides of the chip102before the deep drawing process. In other words, instead of processing a bare semiconductor chip102, a recon die like for fan-out wafer-level packaging (FoWLP) may be used. The chip102may thus be provided with the insulation layers440,552on its side surfaces before being enclosed by the carrier/layer combination112/110. This means that the chip102may be provided with tough, insensitive side walls that may be well suited for being pressed. Furthermore, an insulating backside may be provided (the insulation layer440may enclose the chip102from all sides and from the backside102B). This is shown in the exemplary embodiment ofFIG.4. In various embodiments, the insulation layer552may be realized by the application of a dielectric layer552on the chip side surfaces, e.g. an oxide, a nitride, an imide, or an epoxy. In various embodiments, the insulation layer552, e.g. a polymer layer, may be applied on the carrier/layer-combination112/110. An exemplary embodiment is shown inFIG.6. Please note that in the top view, outlines of all the vertically stacked elements are shown. In other words, the view from the top is not meant to indicate that the layer110is formed above the insulation layer552. That it is formed between the carrier112and the insulation layer552(in regions where the insulation layer552is formed) can be seen in the cross-sectional view in the second panel ofFIG.6. In other words, on the layer110, the insulation layer552may be pre-applied, as a structured layer552, e.g. printed or pre-structured and attached. The insulation layer552may be configured to isolate a part of the layer110towards the chip102, for example most of the layer110. The insulation layer552may be or include the same material (e.g. polymer) as used as the carrier112, or it may for example be an isolating adhesive layer, like e.g. Tesa HAF®. The insulation layer552may in various embodiments not only be applied between the layer110and the chip102, but also between the carrier112and the chip102. In various embodiments, the insulation layer552may provide an additional advantage by filling a gap between the chip side and the carrier112(or the layer110, respectively) and seal it safely. Also an area of the carrier112, which may contact the non-pad area on the chip frontside102F, may be glued on in this way. In various embodiments, in which an increased adhesion may be desired but an insulation may not be necessary, or in which the layer110is to be connected to the insulation layer552(e.g., a polymer layer), an adhesion promotion770(seeFIG.7) may be provided, for example a surface roughening. The adhesion promotion770may be applied to the layer110before the deep drawing. In various embodiments, the backside chip contact104may be unconnected to the layer110, or the chip102may not have a backside chip contact (like in the exemplary embodiment ofFIG.4). Redistributed chip contacts104from the front side102F of the chip102may be exposed at the front side100F of the chip package100, where the back side102B of the chip102may be exposed (as shown in an exemplary fashion inFIGS.3,6,9A,9B,10A, and10B) or may be covered by an insulation (as shown in an exemplary fashion inFIGS.4,5, and7). In various embodiments, to address a multitude of different potentials (which may for example be required to contact the chip frontside102F), the metal layer110may be a structured layer. This is indicated in particular inFIGS.3,6, and8, where the schematic top views are provided, but may also be relevant for other embodiments. In various embodiments, a carrier/layer-combination112/110, e.g. a one layer flex, may be structured to form a multitude of contacts that on the one hand (at one end) fit on the chip contacts104, and on the other hand (at the other end) form pads that form outer contacts of the package100after processing. The carrier112with the structured layer110formed thereon may be pressed onto the frontside102F of the chip102(the deep drawing is visualized by white arrows in the figures), thereby forming all electrical connections to the chip contacts104and (redistributed) pads at the same time. This is in particular visualized inFIGS.3and6. In various embodiments, to achieve a robust standard outline, an additional molding process may be applied as described in context withFIG.2and shown in, e.g.,FIG.3andFIG.6, respectively. To achieve a high robustness of the chips102, a thick passivation may be desirable. This may allow for an additional feature: By forming the chip contacts104with a shape that may allow (or require) locking the chip contacts104and the structured layer110(which may in this case be structured with a matching, i.e. complementary, structure, a self-aligning feature may be achieved. For example, jigsaw puzzle type complementary structures may be provided by the chip contact104(e.g., as a protrusion) and the layer110(e.g., as an opening). This is shown inFIG.8in an exemplary fashion. A higher robustness may be achieved thereby. For forming the structured metal layer110on the carrier112, it may be preferable to not use B-stage material like for example resin-coated copper (RCC), but to use a combination of a malleable polymer, e.g. polyimide, and metal, e.g. copper, for example so-called flex-boards. In particular, the structured layer110may be present on the carrier112only in regions where a respective electrical contact to the chip contacts104is to be formed (a contact portion), where the deep-drawn layer110is to form the redistributed chip contact (a redistributed contact portion), and in a region connecting the contact portion and the redistributed contact portion. The layer110may be structured to form one or more redistributed chip contacts. In each of the exemplary embodiments ofFIGS.3and6, six redistributed chip contact are formed, and the layer110on the carrier112ofFIG.8is also configured to form six redistributed chip contacts. In each of the exemplary embodiments ofFIGS.4,5, and7, at least two redistributed chip contacts are formed. In each of the exemplary embodiments ofFIGS.9A,9B,10A, and10B, further features of which will be discussed below, at least four redistributed chip contacts are formed. The layer110may be structured essentially as known in the art. Depending on a complexity of the structures to be formed and/or the materials of the carrier112and of the layer110, this will usually be done by lithographic processing. Different surfaces may be formed according to the described embodiments, e.g. by galvanic or e-less plating. Additionally layers of connecting materials like adhesive (e.g. glue) and contact enhancement material, e.g. solder, may be applied by e.g. stencil printing, screen-printing, inkjet printing. The further process, i.e. a preparation for the deep drawing process, may for example include applying, e.g. mounting, the chip102to the carrier/layer combination112/110for example by a temporary bonding or by a permanent connection, or by attaching the chip102to a temporary carrier (not shown). In various embodiments, the electrically conductive material of the layer110may include or consist of at least one of a group of electrically conductive materials. The group may include copper, silver, aluminum, and an alloy of one or more of the above materials. A soft copper (galvanic or oxygen-free) may be preferred. The dielectric carrier112may in various embodiments include a polymer, for example an imide, e.g. polyimide, a resin, e.g. a b-stage resin, or a high temperature capable thermoplastic polymer like polyphenylene sulfide (PPS). These materials may in various embodiments be filled to lower the CTE and improve package robustness. Thermally highly conductive fillers may be applied to improve thermal performance. In various embodiments, it may be sufficient that the dielectric carrier112is malleable during the deep drawing process, which may occur at an elevated processing temperature. The dielectric carrier112may in various embodiments harden, at least to some degree, after the deep drawing. In an exemplary embodiment, a copper-metallized plastic foil, e.g. polyimide foil, may be used. The deep drawing may in various embodiments include hot pressing. For the pressing, the chip102may be rested on a rather hard support surface. The cover-side may either be provided as having a dedicated form, which may conform to the topology of the output, or a soft stack-up may be provided to achieve a quasi-hydrostatic pressure and result in an almost conformal formation of carrier/layer combination112/110(the cover layer) over the chip102. The method including the soft stack-up may have the advantage that forces applied to the chip (e.g., shear and tensile forces), which may be dangerous for the chip102, may be minimized. In various embodiments, the carrier112, which may for example include a resin-coated copper or a similar material, may be thicker than the chip102. For example, as shown inFIG.1, a simple connection of the chip backside102B to the frontside102F (or the package frontside100F, respectively) may be formed. The chip102may be placed on the metal side of the carrier-layer-combination112/110, i.e. on the layer110. Subsequently, the carrier112may be deep-drawn, e.g. hot pressed, around the chip102. Thereby, the (metal) layer110may be deformed to form a complete cover of the chip backside102B and the chip side surfaces, and to be flush with the chip front side102F. The portions of the metal layer110that are flush with the chip front side102F may form the redistributed chip contact. In other words, the metal areas that exceed the chip area may result in a solderable contact on the same level as the chip front side102F. If this is already prepared in a way that is applicable for board soldering, the chip package100is ready. In various embodiments, further processes like separation, surface finishing etc. may be applied. In various embodiments, the chip102may be thicker than the carrier112or thicker than the carrier-layer-combination (e.g., a metalized plastic foil). In that case, the deep drawing may result in a topology that reproduces at least partly the contours of the chip102. Exemplary embodiments are shown inFIGS.2to7and9A to10B. A package100with a standard appearance may be achieved by a subsequent molding process that may partially encapsulate the carrier112with a mold compound220. Since the mold compound220may not be in direct contact with the chip102, a relatively cheap quality may be used, thereby a further cost reduction may be achieved. In the above described embodiments, packages100with an outline like a quad flat no leads package (VQFN) or dual small outline packages (DSO), either with exposed pads or without, have been realized, having in common that they have only one row of outline pads on one side and no possibility for package internal routing. In various embodiments, exemplary embodiments of which are described inFIGS.9A to10B, at least one additional conductive layer990in addition to the conductive layer110may be provided. The exemplary embodiments are described with two layers110,990. However, in principle the number of conductive layers may be unlimited, for example three, four, or more layers, which may be separated by the carrier112and further layers of dielectric material, which may be the same as the material of the carrier layer112or a different material. In various embodiments, the additional layer990may be provided on a side of the carrier112that is opposite the layer110. For example, a flex board with structured electrically conductive layers on both sides may be provided. In various embodiments, the layer110may be configured to form all desired contacts to the chip102, i.e. to the chip contacts104, and to the package100outside (e.g. the portions of the layer110that are exposed on the front side100F of the package100after the deep drawing). The additional layer990may be configured as a routing layer, which may lead contacts over the layer110. A second row of exposed contacts around the chip102may be formed in this way. A contact between the additional layer990and either the layer110or a front side100F of the package100may be provided by vias992(seeFIG.9A) and/or by providing the carrier112as a structured carrier112with openings994through which the additional layer990may be exposed (seeFIG.9B). In a case of providing the insulating layer552, matching openings996to the openings994may be provided for exposing the additional layer990to the front side100F of the package100. In various embodiments, with this approach, land grid array or ball grid array packages can be built, realizing more than one row of pads around the package outline. Additionally, the additional layer(s)990may optionally be used for a complex routing of different potentials. In various embodiments, the two layers110,990for connection may also be used to achieve a hetero-integration with fine line space for logic and thick metal lines (e.g. copper lines) for power applications. A corresponding exemplary embodiment is shown inFIG.9B, in which the additional layer990is thicker than the layer110. A second chip (not shown) may in various embodiments be integrated and connected with the chip102. Thereby, a hetero-integration of e.g. logic and power chips102with different technology requirements in the same package technology may be provided. In various embodiments, the layers110,990may be of the same thickness before the deep drawing, and the outer layer(s)990may thereafter be thickened, for example by galvanic processes. In various embodiments, for example if only the layer110is present, the layer110may have a thickness in a range from about 5 μm to about 250 μm. In various embodiments, the layer110may have a thickness in a range from about 5 μm to about 50 μm, and the further layer(s)990may have a thickness in a range from about 50 μm to about 250 μm. In various embodiments, the method of forming the chip package may allow to improve the connection of the chip102(e.g., the chip contacts104) to the conductive layer110. A reliable, robust and conductive interconnect may have to be formed. For this, in various embodiments, two clean, sufficiently noble surfaces may be pressed together, preferably with a high deformation. To achieve this, an artificially tailored roughness and/or an application of activating plasma may in various embodiments be applied. Alternatively or additionally, an additional connecting material may be applied, for example a solder material1010,1012. In various embodiments, the chip102may be soldered to the metal layer110before the deep drawing process (the pressing and optionally heating). The soldering may be achieved by printed solder or by solder balls1010(or by copper/nickel core balls). A corresponding exemplary embodiment is shown inFIG.10. In various embodiments, a solder reservoir may be applied before the deep drawing process (the pressing and optionally heating), and the soldering process may be combined with the pressing process. A corresponding exemplary embodiment is shown inFIG.11. A thin solder layer1012may result in a fully reacted phase, i.e. a diffusion solder. As an alternative to the soldering, for example gluing (highly conductive or anisotropic conductive) or sintering may be used. In various embodiments, an exemplary embodiment of which is visualized in the process shown inFIG.11, the metal layer110may not be mounted to the carrier112during the deep drawing process. Instead, the metal layer110may be conformed to a pre-shaped mold1140during a molding process, in which the malleable (optionally liquid) carrier material112may be pressed towards the metal layer110for pressing the metal layer110towards the pre-shaped mold1140. The carrier material112may be configured to harden after the deep-drawing process, to serve as a stabilizing carrier112for the metal layer110. Further processing may include grinding, on one side or on both sides of the carrier/layer combination112/110. The pre-shaped mold1140may be removed after the grinding of the top side, or before the grinding of the bottom side, respectively. In various embodiments, the resulting carrier/layer combination112/110, which may serve as a contact structure, may include tracks and trough-contacts. FIG.12shows a flow diagram1200of a method of forming a chip package in accordance with various embodiments. The method may include providing a malleable carrier with a layer of an electrically conductive material formed thereon (1210), and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier, wherein the layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip, and wherein the layer forms a redistribution layer (1220). Various examples will be illustrated in the following: Example 1 is a method of forming a chip package. The method may include providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier, wherein the layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip, and wherein the layer forms a redistribution layer. In Example 2, the subject-matter of Example 1 may optionally include that the chip includes a further chip contact, and that the further chip contact and a portion of the layer are exposed at the same side of the chip package. In Example 3, the subject-matter of Example 1 or 2 may optionally include that the layer is a structured layer. In Example 4, the subject-matter of any of Examples 1 to 3 may optionally include that the electrically conductive material includes at least one of a group of electrically conductive materials, the group including copper, silver, aluminum, and an alloy of one or more of the above materials. In Example 5, the subject-matter of any of Examples 1 to 4 may optionally include that the electrically conductive material is coated with a further electrically conductive material including at least one of a group of electrically conductive materials, the group including tin, zinc, nickel, silver, palladium, and gold. In Example 6, the subject-matter of any of Examples 1 to 5 may optionally further include arranging insulating material along side walls of the chip, wherein the insulating material optionally completely covers the side walls of the chip. In Example 7, the subject-matter of Example 6 may optionally include that the insulating material is arranged along the side walls of the chip before the positive fitting of the malleable carrier to the chip. In Example 8, the subject-matter of Example 6 may optionally include that the arranging the insulating material along side walls of the chip includes arranging the insulating material in a predefined area on the carrier over the layer of electrically conductive material before the positive fitting of the malleable carrier to the chip. In Example 9, the subject-matter of any of Examples 1 to 8 may optionally further include arranging an encapsulation material on the malleable carrier after the positive fitting of the malleable carrier to the chip. In Example 10, the subject-matter of any of Examples 1 to 9 may optionally further include that the chip contact of the chip forms a protrusion with a predefined shape, and that the layer includes an opening having a predefined shape matching the protrusion. In Example 6, the subject-matter of any of Examples 1 to 5 may optionally further include an adhesive material on the carrier before the positive fitting of the malleable carrier to the chip. In Example 12, the subject-matter of Example 11 may optionally include that the adhesive material is arranged over and/or under the layer of electrically conductive material. In Example 13, the subject-matter of Example 11 or 12 may optionally include that the arranging the adhesive material includes printing, for example stencil printing, screen-printing, inkjet printing, and/or spraying. In Example 14, the subject-matter of any of Examples 1 to 13 may optionally include that the layer has a thickness in a range from 5 μm to 250 μm. In Example 15, the subject-matter of any of Examples 1 to 14 may optionally further include forming a further layer of an electrically conductive material on the carrier on a side of the carrier that is opposite the layer. In Example 16, the subject-matter of Example 15 may optionally include forming at least one contact extending through the carrier electrically conductively connecting the layer and the further layer. In Example 17, the subject-matter of Example 15 or 16 may optionally include that the layer is thicker than the further layer, or vice versa. In Example 18, the subject-matter of Example 17 may optionally include that the forming of the thicker layer includes forming a base layer, which optionally has the same thickness as the thinner layer, and galvanizing the base layer with further electrically conductive material, thereby increasing the thickness of the base layer to form the thicker layer. In Example 19, the subject-matter of any of Examples 15 to 18 may optionally include that the layer has a thickness of between 5 μm and 50 μm, and the further layer has a thickness of between more than 50 μm and 250 μm, or vice versa. In Example 20, the subject-matter of any of Examples 1 to 19 may optionally further include arranging connection material in at least one predefined area on the layer. In Example 21, the subject-matter of Example 20 may optionally include that the connection material includes at least one of a group of connection materials including solder, electrically conductive glue, and an electrically conductive sinter material. Example 22 is a chip package. The chip package may include a chip including at least one chip contact, and a malleable carrier with a layer of an electrically conductive material formed thereon fitted to the chip and partially enclosing the chip, wherein the layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip, and wherein the layer forms a redistribution layer. In Example 23, the subject-matter of Example 22 may optionally include that the chip includes a further chip contact, and that the further chip contact and a portion of the layer are exposed at the same side of the chip package. In Example 24, the subject-matter of Example 22 or 23 may optionally include that the layer is a structured layer. In Example 25, the subject-matter of any of Examples 22 to 24 may optionally include that the electrically conductive material includes at least one of a group of electrically conductive materials, the group including copper, silver, aluminum, and an alloy of one or more of the above materials. In Example 26, the subject-matter of any of Examples 22 to 25 may optionally include that the electrically conductive material is coated with a further electrically conductive material including at least one of a group of electrically conductive materials, the group including tin, zinc, nickel, silver, palladium, and gold. In Example 27, the subject-matter of any of Examples 22 to 26 may optionally further include insulating material arranged along side walls of the chip, wherein the insulating material optionally completely covers the side walls of the chip. In Example 28, the subject-matter of any of Examples 22 to 27 may optionally further include encapsulation material arranged over the malleable carrier. In Example 29, the subject-matter of any of Examples 22 to 28 may optionally further include that the chip contact of the chip forms a protrusion with a predefined shape, and that the layer includes an opening having a predefined shape matching the protrusion. In Example 30, the subject-matter of any of Examples 22 to 29 may optionally further include an adhesive material arranged between the carrier and the chip. In Example 31, the subject-matter of Example 30 may optionally include that the adhesive material is arranged over and/or under the layer of electrically conductive material. In Example 32, the subject-matter of any of Examples 22 to 31 may optionally further include that the layer has a thickness in a range from 5 μm to 250 μm. In Example 33, the subject-matter of any of Examples 22 to 32 may optionally further include a further layer of an electrically conductive material on the carrier on a side of the carrier that is opposite the layer. In Example 34, the subject-matter of Example 33 may optionally further include at least one contact extending through the carrier electrically conductively connecting the layer and the further layer. In Example 35, the subject-matter of Example 33 or 34 may optionally include that the layer is thicker than the further layer, or vice versa. In Example 36, the subject-matter of any of Examples 33 to 35 may optionally include that the layer has a thickness of between 5 μm and 50 μm, and the further layer has a thickness of between more than 50 μm and 250 μm, or vice versa. In Example 37, the subject-matter of any of Examples 22 to 36 may optionally further include connection material in at least one predefined area between the layer and the chip. In Example 38, the subject-matter of Example 37 may optionally include that the connection material includes at least one of a group of connection materials including solder, electrically conductive glue, and an electrically conductive sinter material. While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced. | 32,500 |
11862601 | DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments will be explained in detail with reference to the accompanying drawings. Some of the parts which are not associated with the description may not be provided in order to describe embodiments of the disclosure and like reference numerals refer to like elements throughout the specification. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.” In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising” “includes” and/or “including”, “have” and/or “having” are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof. When a layer, film, region, substrate, or area, or element is referred to as being “on” another layer, film, region, substrate, or area, or element, it may be directly on the other film, region, substrate, or area, or element, or intervening films, regions, substrates, or areas, or elements may be present therebetween. Conversely, when a layer, film, region, substrate, or area, or element, is referred to as being “directly on” another layer, film, region, substrate, or area, or element, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further when a layer, film, region, substrate, or area, or element, is referred to as being “below” another layer, film, region, substrate, or area, or element, it may be directly below the other layer, film, region, substrate, or area, or element, or intervening layers, films, regions, substrates, or areas, or elements, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, or element, is referred to as being “directly below” another layer, film, region, substrate, or area, or element, intervening layers, films, regions, substrates, or areas, or elements may be absent therebetween. Further, “over” or “on” may include positioning on or below an object and does not necessarily imply a direction based upon gravity. The spatially relative terms “below”, “beneath”, “lower”, “above”, “upper”, or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations Sizes of components in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto. Additionally, the terms “overlap” or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The terms “face” and “facing” mean that a first element may directly or indirectly oppose a second element. In a case in which a third element intervenes between the first and second element, the first and second element may be understood as being indirectly opposed to one another, although still facing each other. When an element is described as ‘not overlapping’ or ‘to not overlap’ another element, this may include that the elements are spaced apart from each other, offset from each other, or set aside from each other or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. In the specification, an expression such as “A and/or B” indicates A, B, or A and B. Also, an expression such as “at least one of A and B” indicates A, B, or A and B. In embodiments below, when a component is referred to as being “on a plane,” it is understood that a component is viewed from the top, and when a component is referred to as being “on a schematic cross section,” it is understood that the component is vertically cut and viewed from the side. It will be understood that when a layer, region, or component is referred to as being “connected” or “coupled” to another layer, region, or component, it may be “directly connected” or “directly coupled” to the other layer, region, or component and/or may be “indirectly connected” or “indirectly coupled” to the other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it may be “directly electrically connected” or “directly electrically coupled” to the other layer, region, or component and may be “indirectly electrically connected” or “indirectly electrically coupled” to the other layer, region, or component with other layers, regions, or components interposed therebetween. Also, when an element is referred to as being “in contact” or “contacted” or the like to another element, the element may be in “electrical contact” or in “physical contact” with another element; or in “indirect contact” or in “direct contact” with another element. “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. In the following examples, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that may not be perpendicular to one another. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments pertain. In addition, it will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. FIG.1is a plan view illustrating a display device according to an embodiment. Referring toFIG.1, the display device10may include a display panel and a connecting member300. The display panel may include a display area DA and a non-display area NDA. For example, the display panel may have a substantially rectangular shape having a long side in a first direction D1and a short side in a second direction D2substantially perpendicular to the first direction D1. A display area DA may be disposed in a central portion of the display panel, and the non-display area NDA may be disposed to surround or be adjacent to the display area DA. However, a shape of the display panel is not limited thereto. An image may be displayed in the display area DA. For example, a pixel that may display the image may be disposed in the display area DA. Signals generated from an external device may be provided to the pixel, and the pixel may emit light having a predetermined color (for example, a red color, a green color, or a blue color). Pads130to which the signals generated from the external device may be applied may be disposed in the non-display area NDA so that the signals may be provided to the pixel. The pads may include a metal material such as silver (Ag). For example, the pads may be disposed on a lower portion of the display panel. Each of the pads may be arranged or disposed to be spaced apart from each other with a constant width along the second direction D2in a plan view. Accordingly, spaces in which the pads130may be spaced apart from each other may also be arranged or disposed in the second direction D2. The connecting member300may be disposed on the pads130, and may be electrically connected to the pads130. The connecting member300may transfer the signals provided from the external device to the pads130. For example, circuit patterns that may transfer the signals to the pads may be formed or disposed on the connecting member300. The connecting member300may include a flexible printed circuit board. FIG.2is a schematic cross-sectional view taken along line I-I′ ofFIG.1. Referring toFIGS.1and2, the display device10may include a display panel100, a connecting member300, and an adhesive member500. The display panel100may include a first substrate110, the pads130, wires150, a second substrate170, and a polarizing plate190. The first substrate110may include a transparent material or an opaque material. The first substrate110may include first to (n)th (where n is an integer of 3 or more) regions arranged or disposed along the second direction D2. For example, the first substrate110may include a quartz substrate or a glass substrate. On the other hand, the first substrate110may include a plastic substrate having flexibility. The plastic substrate may be a polyimide substrate, and the first substrate110may have a structure in which at least one polyimide layer and at least one barrier layer may be alternately stacked. The pads130may be disposed on the first substrate110. The pads130may include first to fourth pads131,132,133and134. For example, the pads130may be disposed on the lower portion of the display panel100. For example, each of the pads130may be arranged or disposed to be spaced apart from each other with a constant width along the second direction D2in a plan view. In other words, the pads130may be disposed in odd-numbered regions among the first to (n)th regions. The spaces in which the pads130may be spaced apart from each other may be disposed in even-numbered regions among the first to (n)th regions. The signals applied to the connecting member300may be provided to the pads130. The wires150may be disposed between the pixel and the pads130. The wires150may include first to fourth wires151,152,153and154. Each of the wires150may be arranged or disposed to be spaced apart from each other with a constant width along the second direction D2in a plan view. The wires150may include a metal material such as copper (Cu). An insulating portion140(seeFIG.4) may be disposed between two adjacent wires. The wires150may be electrically connected to the pads130, respectively, and may be extended in the first direction D1. For example, the first wire151may be electrically connected to the first pad131, and may be extended in the first direction D1. Accordingly, the signals applied to the pads130may be provided to the wires150, and may be provided to the pixel disposed in the display area DA. For example, the signals applied to the first pad131may be provided to the first wire151. The signals may include various signals that may drive the display device10. For example, the signals may include a power voltage, a gate signal, or a data voltage. Accordingly, the wires150may include a power voltage line, a gate line, or a data line. The second substrate170may be disposed on the first substrate110. For example, the second substrate170may be disposed to face the first substrate110. The second substrate170may include a glass, a quartz, or a plastic. For example, when the display device10is a liquid crystal display (“LCD”), a liquid crystal layer may be disposed between the first substrate110and the second substrate170. On the other hand, when the display device10is an organic light emitting display, an organic light emitting diode (“OLED”) may be disposed between the first substrate110and the second substrate170. For example, the second substrate170may be a color filter substrate. For example, the second substrate170may include color filters, and each of the color filters may be a wavelength selective optical filter that selectively transmits only a portion of a wavelength band of a light incident to each color filter by transmitting a light in a specific wavelength band and blocking the light in another specific wavelength band. For example, the color filters may include a red color filter, a green color filter, and a blue color filter. The polarizing plate190may be disposed on the second substrate170. The polarizing plate190may transmit only an external light having a predetermined vibrating direction among external lights incident to the display device10. Accordingly, the polarizing plate190may block the external lights incident on the display device10so that the external lights reflected from the display device10may be reduced. The connecting member300may be disposed on the first substrate110. For example, the pads130may be disposed in the non-display area NDA of the first substrate110, and the connecting member300may be disposed on the pads130. The connecting member300may include an upper surface300aand a rear surface300b. The rear surface300bmay face an upper surface of the first substrate110, and the upper surface300aof the connecting member300may be opposite to the rear surface300bof the connecting member300. The connecting member300may be electrically connected to the pads130. In detail, the connecting member300may provide the signals generated from the external device to the pads130. For example, circuit patterns may be formed on the connecting member300. The adhesive member500may be disposed between the pads130and the connecting member300. The adhesive member500may include a conductive material. For example, the adhesive member500may be an anisotropic conducting film (“ACF”). The ACF may include an adhesive cured by heat and conductive particles. When a pressure is applied to the ACF, the adhesive may be spread so that the conductive particles may be exposed to a surface of the ACF. Accordingly, the ACF may concurrently have a conductivity and an adhesiveness. Therefore, the signals provided to the adhesive member500through the connecting member300may be provided to the pads130. The signals may be generated from the external device, and may be provided to the pixel through the connecting member300, the adhesive member500, the pads130, and the wires150. The spaces spaced apart from each other in the second direction D2may be located or disposed between two adjacent pads among the pads130so that each of the pads130may be insulated from each other. Accordingly, the signals may be provided to the pads130, respectively. For example, a first signal applied to the connecting member300may be provided to the first pad131, and a second signal, which may be applied to the connecting member300, different from the first signal may be provided to the second pad132. Therefore, the first signal may be provided to the first wire151, and the second signal may be provided to the second wire152. Meanwhile, a particle700may be positioned between the display panel100and the connecting member300. The particle700may be a piece that may be separated from the pads130in a process of patterning the pads130, or may penetrate the display device10from an outside of the display device10during a process of manufacturing the display device10. For example, the particle700may include a conductive material. In a case that the particle700includes the conductive material, the particle700may have a conductivity. For example, when the particle700overlaps two adjacent pads among the pads130, a short may occur between the two adjacent pads. Here, the particle700may overlap the two adjacent pads in a plan view. For example, as shown inFIG.1, the particle700may overlap the third and fourth pads133and134. For example, the particle700may be positioned or disposed between the connecting member300and the adhesive member500in schematic cross-section view as shown inFIG.4, or may be positioned or disposed between the adhesive member500and the pads130in schematic cross-section view as shown inFIG.5. In a case that the display device10includes the particle700as described above, a short may occur between pads overlapping the particle700. Accordingly, the signals may not be provided to the pads where the short occurs. For example, in a case that the particle700is positioned or disposed between the third and fourth pads133and134, a defect in which third and fourth signals may be provided to the third pad133may occur, or a defect in which the third and fourth signals may be provided to the fourth pad134may occur. FIG.3is a flowchart illustrating a method of manufacturing a display device according to an embodiment.FIG.4toFIG.11Bare schematic cross-sectional views illustrating a method of manufacturing a display device according to an embodiment.FIG.12is a plan view illustrating the display device according to an embodiment. For example, FIG.4toFIG.11Bare schematic cross-sectional views of an embodiment. Referring toFIGS.3,4,5, and12, to manufacture a display device20, after checking the particle700or710positioned or disposed between the display panel100and the connecting member300, it may be determined whether the particle700overlaps two adjacent pads among the pads130(S110). In an embodiment, the particle710may be positioned or disposed between the connecting member300and the adhesive member500as shown inFIG.4. In an embodiment, the particle700may be positioned or disposed between the adhesive member500and the display panel100as shown inFIG.5. Whether the particle700overlaps the two adjacent pads among the pads130may be determined according to whether a defect occurs. For example, when both the third and fourth signals are provided to the fourth pad134, or when both the third and fourth signals are provided to the third pad133, it may be determined that the particle700overlaps the two adjacent pads among the pads130. However, a method of determining whether the particle700overlaps two adjacent pads among the pads130is not limited thereto. Referring toFIGS.3,6,7,8, and12, a laser910may be irradiated to the upper surface300aof the connecting member300overlapping at least a part of the particle700(S130). In detail, each of the pads130may be arranged or disposed to be spaced apart from each other with the constant width along the second direction D2in a plan view. Accordingly, spaces spaced apart from each other in the second direction D2between the pads130may be defined. The particle700may overlap the third and fourth pads133and134, which may be located or disposed adjacent to each other, among the pads130. In other words, the particle700may be positioned or disposed in the space where the two adjacent pads may be spaced apart from each other. For example, the laser910may be irradiated to the upper surface300aoverlapping the particle700positioned or disposed in the space. Since the laser910has a relatively short wavelength, materials overlapping a region to which the laser910is irradiated may be removed. In an embodiment, the laser910may be a femtosecond laser, by way of example. However, the disclosure is not limited thereto. The laser910may have a wavelength in a range of about 300 nm to about 350 nm. For example, the laser910may have a wavelength of about 343 nm. However, a wavelength of the laser910is not limited to the above-described range, and the wavelength of the laser910may be appropriately selected according to materials of components included in the display device20. Since the laser910is irradiated, the connecting member300, the adhesive member500, and the particle700which may overlap the region to which the laser910may be irradiated may be removed (S150and S170). In detail, as shown inFIG.6, the connecting member300overlapping the region to which the laser910may be irradiated may be removed by irradiating the laser910with a first output. Accordingly, a first hole310may be formed. In other words, the first hole310may be formed in at least one of the even-numbered regions among the first to (n)th regions included in the first substrate110. Subsequently, as shown inFIG.7, the adhesive member500exposed by the first hole310may be removed by irradiating the laser910with a second output. Accordingly, a second hole510may be formed. Therefore, the second hole510may be connected to the first hole310. In an embodiment, the second output may be the same as the first output. For example, the connecting member300may be removed together with the adhesive member500. Subsequently, as shown inFIG.8, the particle700overlapping the first and second holes310and510may be removed by irradiating the laser910with a third output. In an embodiment, the third output may be smaller than the first output and the second output. For example, the first output and the second output may be about 100 W or more, and the third output may be below or less than ab out 100 W. After removing the connecting member300, the adhesive member500, and the particle700which may overlap the region to which the laser may be irradiated, whether the particle700positioned or disposed at the region to which the laser910may be irradiated may be removed may be checked (S190). In a case that the particle700is not removed, the laser910may be re-irradiated. For example, a case that the particle700is not removed may mean a case that the short between two adjacent pads still occurs because a part of the particle700remains. In an embodiment, since the laser910is re-irradiated, the part of the particle700may be removed. Referring toFIGS.3,9and12, after removing the connecting member300, the adhesive member500, and the particle700which may overlap the region to which the laser910may be irradiated, air930may be injected to the first and second holes310and510formed by removing the connecting member300, the adhesive member500, and the particle700(S210). For example, a fragment950of the particle700may remain inside and/or around the first and second holes310and510. The fragment950may be removed by injecting air930to the first and second holes310and510. Referring toFIGS.3,10A,10B, and12, after injecting air930to the first and second holes310and510, a desiccant970amay be coated to the first and second holes310and510(S230). For example, the desiccant970amay prevent the penetration of air and moisture. In an embodiment, the desiccant970amay be coated by a spray method. Accordingly, a desiccant layer970b_1that may completely cover or overlap an upper surface of the first hole310may be formed. In other words, insides of the first and second holes310and510may be empty. On the other hand, the desiccant member970b_2filled in the insides of the first and second holes310and510may be formed. Referring toFIGS.3,11A,11B, and12, after coating the desiccant970ato the first and second holes310and510, an ultraviolet-ray990may be irradiated to the desiccant layer970b_1(S250). In an embodiment, since the ultraviolet-ray990is irradiated to the desiccant layer970b_1, a cured desiccant layer970c_1that may completely cover or overlap the upper surface of the first hole310may be formed. Accordingly, the insides of the first and second holes310and510may be empty. In an embodiment, since the ultraviolet-ray990is irradiated to the desiccant member970b_2, a cured desiccant member970c_2filling the insides of the first and second holes310and510may be formed. Meanwhile, in an embodiment, when the desiccant970aincludes a material that cures over time, a process of irradiating ultraviolet-ray990may be omitted. In an embodiment, after removing the connecting member300, the adhesive member500, and the particle700which may overlap the region to which the laser may be irradiated, a heat may be applied to a periphery of the region. Since the heat is applied, a periphery of a portion where the connecting member300, the adhesive member500, and the particle700are removed may be melted and cured so that the penetration of air and moisture may be prevented. Referring toFIG.12, the display device20may not include the particle700overlapping two adjacent pads. In an embodiment, since the laser910is irradiated to the particle700overlapping the third and fourth pads133and134, the particle700overlapping the third and fourth pads133and134may be removed. Accordingly, the short between the third and fourth pads133and134may be prevented. For example, the third signal provided from the connecting member300to the third pad133may not be provided to the fourth pad134and the fourth wire154. In other words, the fourth signal provided from the connecting member300to the fourth pad134may not be provided to the third pad133and the third wire153. According to a method of manufacturing the display device20according to an embodiment, since the laser910is irradiated to the upper surface300aof the connecting member300, the particle700may be removed. Accordingly, the laser910may not transmit through the first substrate110. Therefore, the wavelength of the laser910may not be limited to a wavelength in a range for transmitting through the first substrate110. The laser910may be irradiated to the upper surface300aof the connecting member300. Therefore, the laser910may be irradiated to the particle700regardless of a structure of the display device20. According to the above-described, an embodiment in which the particle700may be positioned between the adhesive member500and the display panel100are mainly described, but the disclosure is not limited thereto. For example, even when the particle710may be positioned or disposed between the connecting member300and the adhesive member500, the particle710may be removed through the above-described method. FIG.13is a plan view illustrating a display device according to an embodiment,FIG.14is a side view illustrating area A ofFIG.13, andFIG.15is a schematic cross-sectional view taken along line ofFIG.14. Referring toFIGS.13,14, and15, the display device30may include a display panel200, a connecting member400and an adhesive member600. The display panel200may include a first substrate210, pads However, since the wires250and a polarizing plate290may be substantially the same as the wires150and the polarizing plate190of the display device10or20described above, the first substrate210, the pads230, the second substrate270, the connecting member400, and the adhesive member600will be described below. The wires250may include first to fourth wires251,252,253and254. The first substrate210may include a transparent material or an opaque material. For example, the first substrate210may include a quartz substrate, or a glass substrate. On the other hand, the first substrate210may include a plastic substrate having flexibility. The second substrate270may be disposed on the first substrate210. For example, the second substrate270may be disposed to face the first substrate210. The second substrate270may include glass, quartz, plastic, or the like, by way of example. For example, in a case that the display device30is a liquid crystal display (“LCD”), a liquid crystal layer may be disposed between the first substrate210and the second substrate270. On the other hand, when the display device30is an organic light emitting display, an organic light emitting diode (“OLED”) may be disposed between the first substrate210and the second substrate270. For example, the second substrate270may be a color filter substrate. The second substrate170may include color filters, and each of the color filters may be a wavelength selective optical filter that may selectively transmit only a portion of a wavelength band of a light incident to each color filter by transmitting a light in a specific wavelength band and blocking the light in another specific wavelength band. For example, the color filters may include a red color filter, a green color filter, and a blue color filter. The pads230may be disposed on side surfaces210aof the first and second substrates210and270. The pads230may include first to fourth pads231,232,233and234. For example, each of the pads230may be arranged or disposed to be spaced apart from each other with a constant width along the second direction D2in a plan view. In other words, the first substrate210may include first to (n)th regions along the second direction D2, and the pads230may be disposed in odd-numbered regions among the first to (n)th regions. The signal from the connecting member400may be provided to the pads230. The connecting member400may be disposed on the side surfaces210aof the first and second substrates210and270. The connecting member400may include an upper surface400aand a rear surface400b. The rear surface400bmay face the side surfaces210aof the first and second substrates210and270with the pads230interposed or disposed therebetween. The upper surface400aof the connecting member400may be parallel to the side surfaces210aof the first and second substrates210and270. The connecting member400may be electrically connected to the pads230. In detail, the connecting member400may provide the signals generated from the external device to the pads230. For example, circuit patterns may be formed or disposed on the connecting member400. The adhesive member600may be disposed between the pads230and the connecting member400. The adhesive member600may include a conductive material. Accordingly, the adhesive member600may transfer the signal from the connecting member400to the pads230. In an embodiment, the adhesive member600may be an anisotropic conducting film. Meanwhile, the particle700may be positioned or disposed between the display panel200and the connecting member400. The particle700may be a piece that may be separated from the pads230during a process of patterning the pads230, or may penetrate from an outside of the display device30during a process of manufacturing the display device30. For example, the particle700may include a conductive material. As the particle700includes the conductive material, the particle700may have a conductivity. For example, when the particle700overlaps two adjacent pads among the pads230, a short may occur between the two adjacent pads. Here, the particle700may overlap the two adjacent pads in a plan view. For example, as shown inFIG.14, the particle700may overlap the third and fourth pads233and234. In a case that the display device30includes the particle700as described above, the short may occur between pads overlapping the particle700. Accordingly, the signals may not be provided to the pads where the short may occur. For example, since the particle700may be positioned or disposed between the third and fourth pads233and234, a defect in which third and fourth signals are provided to the third pad233may occur, or a defect in which the third and fourth signals are provided to the fourth pad234may occur. FIG.16toFIG.22are schematic cross-sectional views illustrating a method of manufacturing a display device according to an embodiment.FIG.23is a side view illustrating a display device according to an embodiment. For example,FIG.16toFIG.22are schematic cross-sectional views taken along line IV-IV′ ofFIG.14. Referring toFIGS.3,14,16, and23, to manufacture a display device40, after checking the particle700positioned or disposed between the display panel200and the connecting member400, it may be determined whether the particle700overlaps two adjacent pads among the pads230(S110). The display device40may include an insulating portion240disposed between the first210and second substrates270. Referring toFIGS.3,14,17,18,19, and23, a laser910may be irradiated to the upper surface400aof the connecting member400overlapping at least a part of the particle700(S130). Since the laser910has a relatively short wavelength, materials overlapping the region to which the laser910may be irradiated may be removed. Since the laser910is irradiated, the connecting member400, the adhesive member600, and the particle700which may overlap the region to which the laser910may be irradiated may be removed (S150and S170). Accordingly, a first hole410may be formed in the connecting member400, and a second hole610may be formed in the adhesive member600. In other words, the first hole410may be formed in at least one of the even-numbered regions among the first to (n)th regions included in the first substrate210. After removing the connecting member400, the adhesive member600and the particle700which may overlap the region to which the laser may be irradiated, whether the particle700positioned or disposed at the region to which the laser910may be irradiated may be removed may be checked (S190). Referring toFIGS.3,20, and23, after removing the connecting member400, the adhesive member600, and the particle700which may overlap the region to which the laser910may be irradiated, air930may be injected to the first and second holes410and610formed by removing the connecting member400, the adhesive member600, and the particle700(S210). Referring toFIGS.3,21, and23, after injecting the air930to the first and second holes410and610, a desiccant970amay be coated to the first and second holes410and610(S230). In an embodiment, the desiccant970amay be coated by a spray method. Accordingly, a desiccant layer970b_1may be formed.FIGS.21-23may also include a desiccant layer970band cured desiccant layer970c. Referring toFIGS.3,22and23, after coating the desiccant970ato the first and second holes410and610, an ultraviolet-ray990may be irradiated to the desiccant layer970b_1(S250). Since the ultraviolet-ray990is irradiated to the desiccant layer970b_1, a cured desiccant layer970c_1may be cured. Referring toFIG.23, since the display device40may include the pads230and the connecting member400which may be disposed on the side surfaces210aof the first and second substrates210and270, a non-display area NDA of the display device40may be reduced. Since the laser910is irradiated to the particle700between the third and fourth pads233and234, the particle700between the third and fourth pads233and234may be removed. Accordingly, the short between the third and fourth pads233and234may be prevented. For example, the third signal provided from the connecting member400to the third pad233may not be provided to the fourth pad234and the fourth wire254. In other words, the fourth signal provided from the connecting member400to the fourth pad234may not be provided to the third pad233and the third wire253. According to the method of manufacturing the display device40according to an embodiment, since the laser910is irradiated to the upper surface400aof the connecting member400, the particle700may be removed. Accordingly, the laser910may not transmit through the first and second substrates210and270. Therefore, the wavelength of the laser910may not be limited to a wavelength in a range for transmitting through the first and second substrates210and270. The laser910may be irradiated to the upper surface410aof the connecting member400. Therefore, the laser910may be irradiated to the particle700regardless of a structure of the display device40. The disclosure may be applied to a display device and an electronic device using the display device. For example, the disclosure may be applied to a cellular phone, a smart phone, a video phone, a smart pad, a smart watch, a tablet PC, a navigation system, a television, a computer monitor, a laptop, etc. within the spirit and the scope of the disclosure. The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages of the disclosure. Accordingly, all such modifications are intended to be included within the scope of the disclosure as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. | 38,299 |
11862602 | DETAILED DESCRIPTION As used in this disclosure with reference to an element having a planar surface, a statement that an electrically conductive element is “at” a surface of a substrate indicates that, when the substrate is not assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the substrate toward the surface of the substrate from outside the substrate. Thus, a terminal or other conductive element which is at a surface of a substrate may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the substrate. In some embodiments, the conductive element may be attached to the surface or may be disposed in one or more layers of dielectric coating on the said surface. In this disclosure, first and second orthogonal directions X and Y are referred to herein as “horizontal” or “lateral” directions, whereas the directions perpendicular to a plane defined by the X and Y directions, such as a third direction Z, are referred to herein as upward or downward directions and are also referred to herein as the “vertical” directions. The directions referred to herein are in the frame of reference of the structures referred to. Thus, these directions may lie at any orientation to the normal or gravitational frame of reference. A statement that one feature is disposed at a greater height “above a surface” than another feature means that the one feature is at a greater distance in the same orthogonal direction away from the surface than the other feature. Conversely, a statement that one feature is disposed at a lesser height “above a surface” than another feature means that the one feature is at a smaller distance in the same orthogonal direction away from the surface than the other feature. As illustrated inFIG.1, a conventional multi-core processor wafer10may have a plurality of adjacent nodes14a,14b,14c, and14d(collectively nodes14) arranged at the vertices of a square. Each of the nodes14may be electrically connected with adjacent ones of the nodes via an adjacent connection15, and each of the nodes may be electrically connected with an opposite one of the nodes via an opposite connection16. In a conventional node arrangement having an orthogonal or Manhattan routing, each of the adjacent connections15extends in one of the horizontal orthogonal directions X or Y, and each of the opposite connections16only has portions extending in the directions X and Y. In one example in which the adjacent nodes14are horizontally and vertically spaced apart from one another by 8 mm, each of the adjacent connections15will have a length of 8 mm, and each of the opposite connections16will have a length of 16 mm Limitations in lithography technology currently limit routing in CMOS wafers to electrical connections extending in orthogonal X and Y directions, as shown inFIG.1. In contrast, as illustrated inFIG.2, a multi-core processor wafer20according to one embodiment of the invention may have a plurality of adjacent nodes24a,24b,24c, and24d(collectively nodes24) arranged at the vertices of a square. Each of the nodes24may be electrically connected with adjacent ones of the nodes via an adjacent connection25, and each of the nodes may be electrically connected with an opposite one of the nodes via an oblique connection26. In a node arrangement according to the invention, each of the adjacent connections25extends in one of the orthogonal horizontal directions X or Y, and each of the oblique connections26extends in oblique horizontal directions V or W. As shown, the oblique directions V and W are rotated 45 degrees from the orthogonal directions X and Y, although in other embodiments (e.g.,FIG.10), other oblique rotational orientations may be used. In one example in which the adjacent nodes24are horizontally and vertically spaced apart from one another by 8 mm, each of the adjacent connections25will have a length of 8 mm, and each of the oblique connections26will have a length of 11.3 mm, which is 29.3% less than the 16 mm length of the opposite connections14ofFIG.1. As illustrated inFIG.3, a conventional 64-core processor wafer arrangement is shown on a wafer30that has sixteen nodes34, each node arranged at an intersection of four of the cores31. The wafer30may be a semiconductor wafer that is implemented in one of various semiconductor materials such as silicon, silicon-germanium, indium phosphide, and gallium arsenide or one or more other Group III-V semiconductor compounds or Group II-VI semiconductor compounds, etc. The wafer30may have lengths in the orthogonal X and Y directions of 32 mm, for example. The wafer30may have layers of electrical connections configured to function in a hierarchical mesh network topology, including a core layer in which each node34is connected to each of the four cores31that are in contact with the node, and a network layer vertically adjacent to the core layer (in a Z direction orthogonal to the X and Y directions) a that contains connections between the nodes. For example, table 1 below shows the relationship between nodes34and cores31in a conventional hierarchical switch architecture, in which one node is required for every four cores, one hop is required for every log4(nodes), and three switch ports are required for every hop. TABLE 1CPUSwitchSwitchCoresNodesHopsPorts(c)(n)(h)(p)1641364162625664391024256412 FIG.4illustrates a conventional 64-core processor wafer arrangement that is shown on a wafer40that has sixteen nodes44, each node arranged at an intersection of four cores, in the manner shown inFIG.3. The wafer40may have layers of electrical connections, including a network layer42that can be used to connect the nodes44to one another. Similar to the architecture shown inFIG.1, the network layer42may have local adjacent connections45between adjacent ones of the nodes44and local opposite connections46between opposite ones of the nodes. However, the network layer42may also have longer unidirectional connections47that extend between two non-adjacent nodes44in one of the orthogonal horizontal directions X or Y and longer bidirectional connections48that extend between two non-adjacent modes only having portions extending in the directions X and Y. In one example in which the adjacent nodes44are horizontally and vertically spaced apart from one another by 8 mm, each of the local adjacent connections45will have a length of 8 mm, each of the local opposite connections46will have a length of 16 mm, each of the longer unidirectional connections47will have a length of 16 mm, and each of the longer bidirectional connections48will have a length of 32 mm. FIGS.5,5A, and5Billustrate a microelectronic assembly50including a wafer60and an interconnection structure70. The wafer60includes a 64-core processor wafer arrangement according to an embodiment of the invention. The wafer60has sixteen nodes64, each node arranged at an intersection of four cores, in the manner shown inFIG.3. The wafer60may have unitary crystalline structure of semiconductor material, or it may be a reconstituted wafer. The wafer60may have an orthogonal network layer62of electrical connections (shown separately inFIG.5A) that can connect the nodes64to one another along directions of a first orthogonal set of directions X, Y. The interconnection structure70may have an oblique network layer72(shown separately inFIG.5B) that can connect the nodes64to one another along directions of a second set of directions V, W that are each oriented at an oblique angle to the first orthogonal set of directions. Referring toFIGS.5and5A, the orthogonal network layer62may have local adjacent connections65between adjacent ones of the nodes64and longer unidirectional connections67that extend between two non-adjacent nodes in one of the orthogonal horizontal directions X or Y. The orthogonal network layer62may be contained within the wafer60. In one example in which the adjacent nodes are horizontally and vertically spaced apart from one another by 8 mm, each of the local adjacent connections65will have a length of 8 mm, and each of the longer unidirectional connections67will have a length of 16 mm. Referring toFIGS.5and5B, similar to the architecture shown inFIG.2, the oblique network layer72may have local oblique connections76between opposite ones of the nodes. Each of the local oblique connections76extends in oblique horizontal directions V or W that are rotated 45 degrees from the orthogonal directions X and Y, although in other embodiments (e.g.,FIG.10), other oblique rotational orientations may be used. The oblique network layer72may also have longer oblique connections78that extend between two non-adjacent nodes64in the oblique horizontal directions V or W. In an example in which the adjacent nodes64are horizontally and vertically spaced apart from one another by 8 mm, each of the local oblique connections76will have a length of 11.3 mm, and each of the longer oblique connections78will have a length of 22.6 mm Therefore, the local oblique connections76of 11.3 mm are each 29.3% less than the 16 mm length of the local opposite connections46ofFIG.4, and the longer oblique connections78of 22.6 mm are each 29.3% less than the 32 mm length of the longer bidirectional connections48ofFIG.4. The oblique network layer72may extend within the interconnection structure70that is affixed to an active surface of the wafer60. The interconnection structure70may comprise a low-loss directly-bonded interconnect layer or layers that permit the oblique routing of the local oblique connections76and the longer oblique connections78. Suitable low-loss materials for the oblique network layer72may include glass, quartz, sapphire, or ZIF. The use of low-loss materials for the interconnection structure70that includes the oblique network layer72permits longer-distance connections to experience shorter latency than the same connections in semiconductor material. The interconnection structure70may be bonded in a stacked arrangement with the wafer60using various bonding techniques, including using direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique, or a DBI® hybrid bonding technique, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi Corp. (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). According to some examples, thermocompression bonding may be used. This process may enable the interconnection structure70to bond to the wafer60with adjacent electrical connections at an extremely fine pitch. For example, the connection may be at a pitch as low as approximately 1μ-10μ. In such a direct bonding example, a surface of the interconnection structure70may be laminated onto a confronting exposed front surface of the wafer60, and heat and pressure may be used to bond the confronting surfaces to one another. Referring toFIG.6, the orthogonal network layer62may be formed in the wafer60using reticles52as an aligner mask. An arrangement of the reticles52may be placed overlying the wafer60in a pattern extending in the first orthogonal set of directions X, Y. As shown inFIG.6, each reticle52is rectangular in shape, but in other examples, each reticle may have a square shape. Lithography is then performed on the wafer60to form the local adjacent connections65and the longer unidirectional connections67of the orthogonal network layer62, the connections extending in the first orthogonal set of directions X, Y relative to the lithography equipment. Referring now toFIG.7, the oblique network layer72may be formed in the interconnection structure70using the reticles52as an aligner mask. An arrangement of the reticles52may be placed overlying the interconnection structure70in a pattern extending in the first orthogonal set of directions X, Y. As shown inFIG.7, each reticle52is rectangular in shape, but in other examples, each reticle may have a square shape. Before the lithography is performed, the interconnection structure70with the reticles52thereon may be rotated relative to the lithography equipment, by an oblique angle such as 45 degrees. Then, lithography may performed to form connections extending in the second set of directions V, W that are obliquely oriented relative to the X, Y orientation of the reticles. The resulting connection patterns in the interconnection structure70relative to one of the reticles52are shown inFIG.8, in which the local oblique connections76and the longer oblique connections78of the oblique network layer72extend in the second set of horizontal directions V, W, while the example reticle52extends in the first set of horizontal directions X, Y. Accordingly, referring toFIG.9, after the local oblique connections76and the longer oblique connections78are formed in the interconnection structure70, the interconnection structure may be rotated relative to the wafer60, so that the areas that were previously covered by the reticles52are in alignment between the wafer and the interconnection structure. The combined pattern of connections will be as shown inFIG.5, in which the local adjacent connections65and the longer unidirectional connections67of the orthogonal network layer62extend in the first orthogonal set of directions X, Y, and in which the local oblique connections76and the longer oblique connections78of the oblique network layer72extend in the second oblique set of directions V, W. FIG.10illustrates connections in a microelectronic assembly50′ that is a variation of the microelectronic assembly50, but having a non-45 degree oblique interconnection pattern between the local adjacent connections65′ and the local oblique connections76′. For example, rather than having the second oblique set of directions V, W be orthogonal relative to one another, the directions V′ and W′ can each be obliquely oriented at the same angle relative to the horizontal direction X, which need not be 45 degrees. As shown inFIG.10, each of the directions V′ and W′ may be angled at 30 degrees relative to the horizontal direction X, such that the directions V′ and W′ are offset from each other by 120 degrees. The example shown inFIG.10is only one possibility. The directions V′ and W′ may be angled at other oblique angles relative to the horizontal direction X, such as 15°, 20°, 30°, 50°, 60°, 75°, or other angles not listed here. FIG.11illustrates one example of a microelectronic package80including the wafer60and the interconnection structure70mounted to a substrate81. The microelectronic package80may have a core layer90that is configured to function in a hierarchical mesh network topology with the wafer60(that serves as the network layer). An interposer91may be disposed adjacent to the core layer90, and the interconnection structure70may be disposed between the interposer91and the wafer60. The core layer90, the interposer91, and the wafer60may each have electrical connections extending in the first set of orthogonal horizontal directions X and Y, and the interconnection structure70may have electrical interconnections extending in the second set of oblique horizontal directions V and W, similar to the connections described above with regard to the microelectronic assembly50. Expansion wafers92similar to the base wafer60may be stacked above the base wafer60. In the embodiment shown, the core layer90, the base wafer60, and the expansion wafers92may together function as a hierarchical mesh network. The core layer90may be flip-chip mounted to a first surface82of the substrate81via conductive bumps84, which may be spaced from one another at a 150μ pitch, for example. A second surface83of the substrate81may have conductive terminals85exposed thereat that are configured for electrical connection with a component external to the microelectronic package80. Each of the core layer90, the interposer91, the interconnection structure70, the base wafer60, and the expansion wafers92may be directly bonded to one another in a vertical stack overlying the substrate80, using any of the various bonding techniques described above with reference to the microelectronic assembly50. Through-silicon vias, or TSVs (not shown), may be used for inter-wafer electrical interconnection among the aforementioned layers, wafers, and structures.FIG.11Aillustrates an embodiment where the core layer90, the interconnection structure70, the base wafer60, and the expansion wafers92may be directly bonded to one another in a vertical stack overlying the substrate80, without an interposer. The microelectronic assemblies and microelectronic packages described above with reference toFIGS.1-11above can be utilized in construction of diverse electronic systems, such as the system100shown inFIG.12. For example, the system100in accordance with a further embodiment of the invention includes a plurality of modules or components106such as the microelectronic assemblies50and50′ and microelectronic package80described above, in conjunction with other electronic components108,110and111. In the exemplary system100shown, the system can include a circuit panel, motherboard, or riser panel102such as a flexible printed circuit board, and the circuit panel can include numerous conductors104, of which only one is depicted inFIG.12, interconnecting the modules or components106,108,110with one another. Such a circuit panel102can transport signals to and from each of the microelectronic packages and/or microelectronic assemblies included in the system100. However, this is merely exemplary; any suitable structure for making electrical connections between the modules or components106can be used. In a particular embodiment, the system100can also include a processor such as the semiconductor chip108, such that each module or component106can be configured to transfer a number N of data bits in parallel in a clock cycle, and the processor can be configured to transfer a number M of data bits in parallel in a clock cycle, M being greater than or equal to N. In the example depicted inFIG.12, the component108is a semiconductor chip and component110is a display screen, but any other components can be used in the system100. Of course, although only two additional components108and111are depicted inFIG.12for clarity of illustration, the system100can include any number of such components. Modules or components106and components108and111can be mounted in a common housing101, schematically depicted in broken lines, and can be electrically interconnected with one another as necessary to form the desired circuit. The housing101is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen110can be exposed at the surface of the housing. In embodiments where a structure106includes a light-sensitive element such as an imaging chip, a lens111or other optical device also can be provided for routing light to the structure. Again, the simplified system shown inFIG.12is merely exemplary; other systems, including systems commonly regarded as fixed structures, such as desktop computers, routers and the like can be made using the structures discussed above. It will be appreciated that the various dependent claims and the features set forth therein can be combined in different ways than presented in the initial claims. It will also be appreciated that the features described in connection with individual embodiments may be shared with others of the described embodiments. For example, the microelectronic package80shown inFIG.11may be modified to omit the expansion layers92. Also, although the wafers herein are described as semiconductor wafer, in other embodiments, the wafers herein such as the wafer60may be a semiconductor die that is directly bonded to a semiconductor wafer and/or an interconnection structure such as the interconnection structure70. Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. | 20,548 |
11862603 | DETAILED DESCRIPTION Hereinafter, embodiments of the present inventive concepts will be described in detail with reference to the accompanying drawings. FIG.1is a plan view of a semiconductor package10according to an embodiment of the present inventive concepts, andFIG.2is a cross-sectional view taken along line I-I′ of the semiconductor package10ofFIG.1. Referring toFIGS.1and2, a semiconductor package10according to this embodiment may include a package substrate100, first and second lower semiconductor chips210and220arranged on the package substrate100, and an upper semiconductor chip300disposed on the first and second lower semiconductor chips210and220.FIG.1illustrates an arrangement of the first and second lower semiconductor chips210and220, and the upper semiconductor chip300is schematically illustrated by a dotted line. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, the elements should not be limited by these terms; rather, these terms are only used to distinguish one element from another element. Thus, a first element discussed could be termed a second element without departing from the scope of the present inventive concepts. The package substrate100may include a body portion101, an upper substrate pad103disposed on an upper surface of the body portion101, and a lower substrate pad105disposed on a lower surface of the body portion101. In addition, the package substrate100may have a wiring pattern (not illustrated) and/or a connection via (not illustrated) electrically connecting the upper substrate pad103and the lower substrate pad105. For example, the package substrate100may be a printed circuit board. The package substrate100is not limited to a printed circuit board, but may be various types of wiring boards and/or other structures providing electrical connectivity. The package substrate100may be made of at least one material selected from a phenol resin, an epoxy resin, and a polyimide. For example, the package substrate100may include FR4, tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimidetriazine (BT), Thermount, cyanate ester, polyimide, and/or liquid crystal polymer. In addition, the upper substrate pad103, the lower substrate pad105, the wiring pattern, and the connection via may include, for example, copper (Cu), nickel (Ni), aluminum (Al), and/or beryllium copper. An external connection terminal110may be formed on the lower substrate pad105of the package substrate100. The external connection terminal110may include, for example, a solder ball, a conductive bump, a conductive paste, a ball grid array (BGA), a lead grid array (LGA), or a pin grid array (PGA), or a combination thereof. In some embodiments, the external connection terminal110may be omitted. The first and second lower semiconductor chips210and220may include semiconductor substrates211and221, having an active surface and a non-active surface, located opposite to the active surface, respectively. A plurality of active/passive elements (e.g., transistors) and bonding pads213and223connected thereto may be formed on the active surfaces of the semiconductor substrates211and221, respectively. The non-active surfaces of the first and second lower semiconductor chips210and220may be surfaces facing an upper surface of the package substrate100(e.g., the non-active surfaces of the first and second lower semiconductor chips210and220may be surfaces of the semiconductor substrates211and221that are nearest the package substrate100). The first and second lower semiconductor chips210and220may be bonded to the upper surface of the package substrate100using adhesive layers217and227, respectively. The first and second lower semiconductor chips210and220may be electrically connected to the package substrate100by wires215and225, respectively. The wires215and225may connect the bonding pads213and223of the first and second lower semiconductor chips210and220and first pads103A, among the upper substrate pad103, respectively. In a similar manner to the first and second lower semiconductor chips210and220, the upper semiconductor chip300may include a semiconductor substrate311having an active surface and a non-active surface, located opposite to the active surface. A plurality of active/passive elements (e.g., transistors) and bonding pads313connected thereto may be formed on the active surface of the semiconductor substrate311. The non-active surface of the upper semiconductor chip300may be a surface facing the upper surface of the package substrate100. The upper semiconductor chip300may be bonded to upper surfaces of the first and second lower semiconductor chips210and220using a non-conductive adhesive layer317. The non-conductive adhesive layer317may be formed on the lower surface of the upper semiconductor chip300, and may be then bonded to the first and second lower semiconductor chips210and220. In a similar manner to the first and second lower semiconductor chips210and220, the upper semiconductor chip300may be electrically connected to the package substrate100by a wire315. The wire315may connect the bonding pads313of the upper semiconductor chip300and second pads103B, among the upper substrate pad103, respectively. The semiconductor package10employed in this embodiment may further include a molded member500on, and in some embodiments surrounding, the first and second lower semiconductor chips210and220and the upper semiconductor chip300. It will be understood that “an element A surrounds an element B” (or similar language) as used herein means that the element A is at least partially around the element B but does not necessarily mean that the element A completely encloses the element B. The molded member500may be on and/or surround the first and second lower semiconductor chips210and220and the upper semiconductor chip300to protect the first and second lower semiconductor chips210and220and the upper semiconductor chip300from an external environment. The molded member500may be formed by injecting an appropriate amount of molding resin onto the package substrate100in an injection process, and performing a curing process to form an external shape of the semiconductor package10. In some embodiments, the molding resin may be pressurized to form the external shape of the semiconductor package10by a pressurization process such as a press. In this case, process conditions such as delay time between the injection process of the molding resin and the pressurization process of the molding resin, an amount of the molding resin injected, and/or a temperature/pressure of the pressurization process may be set in consideration of physical properties such as viscosity of the molding resin. The molded member500may include an epoxy-based molding resin or a polyimide-based molding resin. For example, the molded member500may include an epoxy molding compound (EMC) or a high-K epoxy molding compound. The upper semiconductor chip300may be bonded to the active surfaces of the first and second lower semiconductor chips210and220by the non-conductive adhesive layer317. The upper semiconductor chip300may be disposed to be on, and in some embodiments cover, the upper surfaces of the first and second lower semiconductor chips210and220. An area of the upper semiconductor chip300to be mounted may be greater than an area of the first and second lower semiconductor chips210and220to be mounted, but is not limited thereto. In an embodiment, upper portions of the first and second lower semiconductor chips210and220may be received in the non-conductive adhesive layer317. In this case, “the upper portions may be received” refers to a state into which not only the upper portions of the first and second lower semiconductor chips210and220, but also portions of side surfaces of the first and second lower semiconductor chips210and220, adjacent to the upper portions, are surrounded by the non-conductive adhesive layer317. This feature may also be expressed by a thickness of each portion of the non-conductive adhesive layer317. In the non-conductive adhesive layer317, a thickness (T2) (e.g., in a direction perpendicular to an upper surface of the package substrate100) of a portion of the non-conductive adhesive layer317between the first and second lower semiconductor chips210and220may be greater than a thickness (T1aand/or T1b) (e.g., in a direction perpendicular to the upper surface of the package substrate100) of a portion of the non-conductive adhesive layer317respectively bonded to the first and second lower semiconductor chips210and220. The first and second lower semiconductor chips210and220employed in this embodiment may be different types of semiconductor chips having different heights (Ha and Hb). As illustrated inFIG.2, a level of an upper surface of the first lower semiconductor chip210may be higher (e.g., farther from the upper surface of the package substrate100) than a level of an upper surface of the second lower semiconductor chip220, and a received depth of the first lower semiconductor chip210may be greater than a received depth of the second lower semiconductor chip220. For example, in some embodiments, the first lower semiconductor chip210may extend farther into the non-conductive adhesive layer317than the second lower semiconductor chip220. When this feature is expressed by the thickness of each portion of the non-conductive adhesive layer317, the thickness (T1a) of the portion of the non-conductive adhesive layer317bonded to the first lower semiconductor chips210may be less than the thickness (T1b) of the portion of the non-conductive adhesive layer317bonded to the second lower semiconductor chips220. Therefore, the upper semiconductor chip300may be aligned relatively horizontally, despite a relatively large difference in levels between the upper surfaces of the first and second lower semiconductor chips210and220. The semiconductor package10according to some embodiments of the present inventive concepts may solve a problem of mechanical deterioration caused by the non-conductive adhesive layer317. This effect will be described in detail with reference toFIG.3. As described above, the first and second lower semiconductor chips210and220may be mounted on the package substrate100at different heights and/or so as to have different heights (Ha and Hb). As such, when a deviation in heights of the first and second lower semiconductor chips210and220is high, a conventional non-conductive adhesive layer may not sufficiently receive the first and second lower semiconductor chips210and220(especially, the second lower semiconductor chip220having a relatively low height Hb) due to its relatively high viscosity. FIG.3is an enlarged view of portion “A” of the semiconductor package ofFIG.2. InFIG.3, a lower surface of a conventional non-conductive film317L is illustrated with a dashed line. Referring toFIG.3, a conventional non-conductive film317L (a lower surface thereof is indicated by a dotted line) may be only bonded to the upper surface of the second lower semiconductor chip220having a relatively low height, and may not extend to a side portion thereof, adjacent to the upper surfaces. Therefore, it may be difficult to provide a firm bond between the upper semiconductor chip300and the second lower semiconductor chip220. In particular, the conventional non-conductive film317L may have a concave portion CV recessed on a corner of the second lower semiconductor chip220. Since it may be hardly filled up to the concave portion CV when the molded member500is applied, even after the molded member500is applied, voids may be generated between the upper semiconductor chip300and the second lower semiconductor chip220. Therefore, mechanical reliability of the semiconductor package10may be significantly deteriorated. In the semiconductor package10according to some embodiments of the present inventive concepts, as described above, the upper portions of the first and second lower semiconductor chips210and220may be disposed in the non-conductive adhesive layer317located on the lower surface of the upper semiconductor chip300, to ensure a firm joint between the first and second lower semiconductor chips210and220(particularly, the second lower semiconductor chip220having a relatively low height (Hb)) and the upper semiconductor chip300, and, in addition, to effectively prevent and/or reduce degradation in reliability of a package due to voids after applying the molded member500. The degradation in reliability may occur as a difference in levels between the upper surfaces of the first and second lower semiconductor chips210and220increases. Therefore, some embodiments of the present inventive concepts may be advantageously applied, when the difference in levels between the upper surfaces of the first and second lower semiconductor chips210and220is relatively high. For example, embodiments described herein may be advantageously applied when the difference in level between the upper surfaces of the first and second lower semiconductor chips210and220is at least 10 μm. The non-conductive adhesive layer317employed in this embodiment may be formed by using an adhesive film having a viscosity lower than that of a conventional non-conductive adhesive layer (e.g., 1,800 to 5,000 Pa·s at 120° C.), to receive the upper portions of the first and second lower semiconductor chips210and220. For example, an adhesive film for the non-conductive adhesive layer317may have a viscosity of about 1,500 Pa·s or less. In this case, the viscosity refers to a viscosity when the viscosity is changed to have a minimum value thereof, and may be a value measured under a temperature condition of about 120° C. The measurement temperature may have an error range of about ±5° C. relative to 120° C. The non-conductive adhesive layer317may be provided as an adhesive layer for bonding the first and second lower semiconductor chips210and220and the upper semiconductor chip300, and may be, for example, a non-conductive film (NCF). In some embodiments, the non-conductive adhesive layer317may include an adhesive resin. For example, the adhesive resin may include a bisphenol type epoxy resin, a novolac type epoxy resin, a phenol resin, a urea resin, a melamine resin, an unsaturated polyester resin, a resorcinol resin, and combinations thereof. A portion of the non-conductive adhesive layer317bonded to the first and second lower semiconductor chips210and220, respectively, may provide a space for the wires215and225. In some embodiments, the received depth of the first lower semiconductor chips210may range from 10% to 50% of the thickness (T2) of the non-conductive adhesive layer317(e.g., between the first and second lower semiconductor chips210and220). In some embodiments, the first and second lower semiconductor chips210and220may be volatile memory chips and/or non-volatile memory chips. For example, the volatile memory chip may include a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (ZRAM), or a twin transistor RAM (TTRAM). In addition, the non-volatile memory chip may include, for example, a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM (STT-MRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM, a nano-floating gate memory, a holographic memory, a molecular electronics memory, or an insulator resistance change memory. In some embodiments, the upper semiconductor chip300may be a processor chip. For example, the upper semiconductor chip300may include a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a system on chip, but is not limited thereto. For example, the upper semiconductor chip300may be or include a microprocessor that includes a single core or multiple cores. In the above-described embodiment, the semiconductor package10is illustrated to include first and second lower semiconductor chips210and220, and the upper semiconductor chip300bonded to the upper surfaces of the first and second lower semiconductor chips210and220. In some embodiments, in the semiconductor package10, at least one semiconductor chip may be replaced with a dummy chip, such as a stiff member or a heat spreader (see, e.g.,FIGS.4,8, and12), and the dummy chip may be additionally disposed (see, e.g.,FIG.10). In some embodiments, the at least one semiconductor chip may be a chip stack in which a plurality of semiconductor chips may be stacked (see, e.g.,FIG.7). In this specification, the term “chip structure” may be used to refer to a chip-shaped structure such as the semiconductor chip, the dummy chip, and the chip stack. For example, it may be referred to as a lower chip structure or an upper chip structure, depending on a position of the chip structure. FIG.4is a plan view of a semiconductor package10A according to an embodiment of the present inventive concepts, andFIGS.5A and5Bare cross-sectional views taken along lines I1-I1′ and I2-I2′ of the semiconductor package10A ofFIG.4, respectively. Referring toFIGS.4,5A, and5B, it may be understood that a semiconductor package10A according to this embodiment has a similar structure as the embodiment illustrated inFIGS.1to3, except for a further inclusion of a dummy chip230D as a lower chip structure. Therefore, the description of the embodiment illustrated inFIGS.1to3may be combined with a description of this embodiment, unless otherwise stated. The semiconductor package10A according to this embodiment may include a package substrate100, first and second lower semiconductor chips210and220disposed on the package substrate100, a dummy chip230D disposed on the package substrate100, and an upper semiconductor chip300disposed on the first and second lower semiconductor chips210and220and the dummy chip230D. The dummy chip230D may be provided as a lower chip structure together with the first and second lower semiconductor chips210and220, to stably support the upper semiconductor chip300. Referring toFIGS.5A and5B, the upper semiconductor chip300may be bonded to active surfaces of the first and second lower semiconductor chips210and220and an upper surface of the dummy chip230D by a non-conductive adhesive layer317. The upper semiconductor chip300may be disposed to be on and, in some embodiments, cover upper surfaces of the first and second lower semiconductor chips210and220. An area of the upper semiconductor chip300to be mounted may be greater than an area of the first and second lower semiconductor chips210and220to be mounted and the dummy chip230D to be mounted. The first and second lower semiconductor chips210and220and the dummy chip230D mounted on the package substrate100may have different heights (Ha, Hb, and Hc). An upper portion of the dummy chip230D, together with upper portions of the first and second lower semiconductor chips210and220, may be received in the non-conductive adhesive layer317. In view of a thickness of each portion of the non-conductive adhesive layer317, a thickness (T2) of a portion of the non-conductive adhesive layer317between the first and second lower semiconductor chips210and220may be greater than a thickness (T1a, T1b, or T1c) of a portion of the non-conductive adhesive layer317respectively bonded to the first and second lower semiconductor chips210and220and the dummy chip230D. A received depth of the first and second lower semiconductor chip210or220may be different from a received depth of the dummy chip230D. Specifically, the received depths may be proportional to mounting heights (Ha, Hb, and Hc), and the thicknesses (e.g., T1a<T1b<T1c) of the non-conductive adhesive layer317may be inversely proportional to the mounting heights (e.g., Ha>Hb>Hc). In some embodiments, the upper semiconductor chip300may be aligned relatively horizontally, in spite of the difference in levels between the upper surfaces of the first and second lower semiconductor chips210and220and the upper surface of the dummy chip230D. In addition, in the semiconductor package10A according to this embodiment, all of the upper portions of the first and second lower semiconductor chips210and220and the upper portion of the dummy chip230D may be received in the non-conductive adhesive layer317disposed on a lower surface of the upper semiconductor chip300. Therefore, a firm joint between all of the lower chip structures and the upper semiconductor chip300may be provided, and after a molded member500is applied, generation of voids may be reduced and/or suppressed. FIG.6is a plan view of a semiconductor package10B according to an embodiment of the present inventive concepts, andFIG.7is a cross-sectional view taken along line II-II′ of the semiconductor package10B ofFIG.6. Referring toFIGS.6and7, it may be understood that a semiconductor package10B according to this embodiment has a similar structure as the embodiment illustrated inFIGS.1and2, except that first and second chip stacks are employed as a lower chip structure. Therefore, the description of the embodiment illustrated inFIGS.1to3may be combined with a description of this embodiment, unless otherwise stated. The semiconductor package10B according to this embodiment may include a package substrate100, first and second chip stacks210S and220S disposed on the package substrate100, and an upper semiconductor chip300disposed on the first and second chip stacks210S and220S. The first and second chip stacks210S and220S may include first to fourth semiconductor chips210A to210D and220A to220D, sequentially stacked, and adhesive films217disposed therebetween, respectively. The first to fourth semiconductor chips210A to210D and220A to220D may be memory chips. The first to fourth semiconductor chips210A to210D and220A to220D may have substantially the same planar shape and planar area. A thickness of each of the fourth semiconductor chips210D and220D may be greater than a thickness of each of the first to third semiconductor chips210A to210C and220A to220C. Each of the first to fourth semiconductor chips210A to210D and220A to220D may include a semiconductor substrate211having an active surface facing the package substrate100and a non-active surface opposite to the active surface. The active surface of the semiconductor substrate211may include active/passive elements (e.g., transistors) and wiring layers connected thereto. The active/passive elements and the wiring layers may constitute a memory circuit. Each of the first to third semiconductor chips210A to210C and220A to220C may include through-vias TV passing through the semiconductor substrate211and electrically connected to active/passive elements (e.g., the memory circuit). The fourth semiconductor chips210D and220D may not include through-vias, but they are not limited thereto. Each of the first to fourth semiconductor chips210A to210D and220A to220D may include a bonding pad BP on an active surface of the semiconductor substrate211. The first semiconductor chips210A and220A may be mounted on the package substrate100in a face-down state such that the active surfaces thereof face the package substrate100. The bonding pad BP of the first semiconductor chips210A and220A, and first pads103A, among an upper substrate pad103, may be connected to each other by an adhesive film217. Similarly, the bonding pads BP of the second to fourth semiconductor chips210B to210D and220B to220D may be passed through and connected to the through-vias TV of the first to third semiconductor chips210A to210C and220A to220C by the adhesive film217. The first and second chip stacks210S and220S may have different mounting heights (Ha and Hb) due to, for example, process errors (e.g., a difference in thickness of an adhesive layer217and/or a difference in bonding processes), even though same or similar semiconductor chips210A to210D and220A to220D are stacked in the same number. As such, even when the first and second chip stacks210S and220S may be stacked with the same kind of four semiconductor chips210A to210D and220A to220D, the first and second chip stacks210S and220S may have different mounting heights (Ha and Hb) due to the process error. As discussed herein, a difference in mounting height (e.g., Hb-Ha) may cause generation of voids in comparative devices. For example, the difference in mounting height (e.g., Hb-Ha) may be 10 μm or more. Referring toFIG.7, the upper semiconductor chip300may be bonded to upper surfaces of the first and second chip stacks210S and220S having different heights (Ha and Hb) by a non-conductive adhesive layer317. The upper semiconductor chip300may be disposed to be on and, in some embodiments, cover the upper surfaces of the first and second chip stacks210S and220S. Upper portions of the first and second chip stacks210S and220S may be received in the non-conductive adhesive layer317, similarly to the previously-described embodiments. In view of a thickness of each portion of the non-conductive adhesive layer317, a thickness (T2) of a portion of the non-conductive adhesive layer317between the first and second chip stacks210S and220S may be greater than a thicknesses (T1aand/or T1b) of a portion of the non-conductive adhesive layer317bonded to each of the first and second chip stacks210S and220S (e.g., portions of the non-conductive adhesive layer317on an upper surface of the first and second chip stacks210S and220S). In some embodiments, a received depth of each of the first and second chip stacks210S and220S may be proportional to a mounting height (Ha and/or Hb) of each of the first and second chip stacks210S and220S, and the thickness (e.g., T1a<T1b) of the portion of the non-conductive adhesive layer317may be inversely proportional to the mounting height (e.g., Ha>Hb). In some embodiments, the upper semiconductor chip300may be aligned relatively horizontally, despite the difference in level of the upper surfaces of the first and second chip stacks210S and220S. In addition, in the semiconductor package10B according to some embodiments, both upper portions of the first and second chip stacks210S and220S may be received in the non-conductive adhesive layer317disposed on a lower surface of the upper semiconductor chip300. As a firm joint between the first and second chip stacks210S and220S and the upper semiconductor chip300is provided, the occurrence of voids may be reduced and/or suppressed after the molded member500is applied. FIG.8is a plan view of a semiconductor package10C according to an embodiment of the present inventive concepts, andFIGS.9A and9Bare cross-sectional views taken along lines II1-II1′ and II2-II2′ of the semiconductor package10C ofFIG.8, respectively. Referring toFIGS.8,9A, and9B, it may be understood that a semiconductor package10C according to this embodiment has a similar structure as the embodiment illustrated inFIGS.1and2, except for a more complicated arrangement (three semiconductor chips210,220, and230and two dummy chips240D1and240D2) as a lower chip structure. Therefore, the description of the embodiment illustrated inFIGS.1to3may be combined with a description of this embodiment, unless otherwise stated. The semiconductor package10C according to some embodiments of the present inventive concepts may include a package substrate100, first to third lower semiconductor chips210,220, and230arranged on the package substrate100, first and second dummy chips240D1and240D2arranged on the package substrate100, and an upper semiconductor chip300disposed on the first to third lower semiconductor chips210,220, and230, and the first and second dummy chips240D1and240D2. The first and second dummy chips240D1and240D2may be arranged in a symmetrical structure, together with the first to third lower semiconductor chips210,220, and230(though the present inventive concepts are not limited thereto), to stably support the upper semiconductor chip300. Referring toFIGS.9A and9B, the upper semiconductor chip300may be bonded to active surfaces of the first to third lower semiconductor chips210,220, and230, and upper surfaces of the first and second dummy chips240D1,240D2by a non-conductive adhesive layer317. The upper semiconductor chip300may be disposed to be on and, in some embodiments, cover upper surfaces of the first to third lower semiconductor chips210,220, and230. An area of the upper semiconductor chip300is illustrated to be greater than an area of the first to third lower semiconductor chips210,220, and230and the first and second dummy chips240D1and240D2. In some embodiments, the upper semiconductor chip300may be provided to be on and/or cover only a portion of the first to third lower semiconductor chips210,220, and230, and/or a portion of an area of the first and second dummy chips240D1and240D2to be mounted. The third lower semiconductor chip230may include semiconductor substrate231, having an active surface and a non-active surface, located opposite to the active surface. A plurality of active/passive elements (e.g., transistors) and bonding pads233connected thereto may be formed on the active surface of the semiconductor substrate231. The non-active surface of the third lower semiconductor chip230may be a surface facing an upper surface of the package substrate100(e.g., the non-active surface of the third lower semiconductor chip230may be a surface of the semiconductor substrate231that is nearest the package substrate100). The third lower semiconductor chip230may be bonded to the upper surface of the package substrate100using adhesive layer237. The third lower semiconductor chip230may be electrically connected to the package substrate100by wire235. The wire235may connect the bonding pads233of the third lower semiconductor chip230and first pads103A, among the upper substrate pad103, respectively. Although the first and second lower semiconductor chips210and220mounted on the package substrate100have similar heights (Ha and Hb), the heights (Ha and Hb) of the first and second lower semiconductor chips210and220may be different from a height (Hc) of the third lower semiconductor chip230and/or a height (Hd) of the first and second dummy chips240D1and240D2, and the height (Hc) of the third lower semiconductor chip230may be also different from the height (Hd) of the first and second dummy chips240D1and240D2. Upper portions of the first to third lower semiconductor chips210,220, and230and upper portions of the first and second dummy chips240D1and240D2may be received in the non-conductive adhesive layer317. In view of a thickness of each portion of the non-conductive adhesive layer317, a thickness (T2) of a portion of the non-conductive adhesive layer317between the first and/or second lower semiconductor chips210and220and the third lower semiconductor chip230may be greater than thickness (T1a, T1b, or T1c) of a portion of the non-conductive adhesive layer317respectively bonded to the semiconductor chips210,220, and230, and a thickness (T1d) of a portion of the non-conductive adhesive layer317respectively bonded to the first and second dummy chips240D1and240D2(e.g., bonded to an upper surface of the first and second dummy chips240D1and240D2). Received depths of the first to third lower semiconductor chips210,220, and230and the first and second dummy chips240D1and240D2may be proportional to the mounting heights (e.g., Ha=Hb>Hd>Hc), and the thickness (e.g., Tc>Td>Ta=Tb) of each portion of non-conductive adhesive layer317may be inversely proportional to the mounting heights (e.g., Ha=Hb>Hd>Hc). In the semiconductor package10C according to this embodiment, the upper portions of the first to third lower semiconductor chips210,220, and230, and the upper portions of the first and second dummy chips240D1and240D2may be received in the non-conductive adhesive layer317, located on the lower surface of the upper semiconductor chip300, to provide a firm joint between all of the lower chip structures and the upper semiconductor chip300, and to reduce and/or suppress occurrence of voids after the molded member500is applied. FIG.10is a plan view of a semiconductor package10D according to an embodiment of the present inventive concepts, andFIG.11is a cross-sectional view taken along line III-III′ of the semiconductor package10D ofFIG.10. Referring toFIGS.10and11, it may be understood that a semiconductor package10D according to this embodiment has a similar structure as the embodiment illustrated inFIGS.1and2, except that a single lower chip structure is a stack structure of a semiconductor chip (a second semiconductor chip220) and a dummy chip230D. Therefore, the description of the embodiment illustrated inFIGS.1to3may be combined with a description of this embodiment, unless otherwise stated. The semiconductor package10D according to this embodiment may include a package substrate100, first and second lower semiconductor chips210and220disposed on the package substrate100, a dummy chip230D disposed on the second lower semiconductor chip220, and an upper semiconductor chip300disposed on the first lower semiconductor chips210and the dummy chip230D. In this embodiment, since a difference in mounting height between the first and second lower semiconductor chips210and220is remarkably high, the difference may be reduced by disposing the dummy chip230D on the second lower semiconductor chip220. The dummy chip230D may be disposed on an active surface of the second lower semiconductor chip220using an adhesive layer237. As a result, a height (Hb) of a stack structure of the second lower semiconductor chip220and the dummy chip230D may be close to a height (Ha) of the first lower semiconductor chip210, but there may still be a deviation in height. Referring toFIG.11, the upper semiconductor chip300may be bonded to an active surface of the first lower semiconductor chips210and an upper surface of the dummy chip230D by a non-conductive adhesive layer317. The upper semiconductor chip300may be disposed to be on and, in some embodiments, cover the active surface of the first lower semiconductor chip210and the upper surface of the dummy chip230D. Upper portions of the first lower semiconductor chip210and the dummy chip230D may be received in the non-conductive adhesive layer317. In view of a thickness of each portion of the non-conductive adhesive layer317, a thickness (T2) of a portion of the non-conductive adhesive layer317between the first lower semiconductor chip210and the dummy chip230D may be greater than a thickness (T1aor T1b) of a portion of the non-conductive adhesive layer317respectively bonded to the first lower semiconductor chip210and the dummy chip230D (e.g., portions of the non-conductive adhesive layer317bonded to upper surfaces of the first lower semiconductor chip210and the dummy chip230D). Received depths of the first lower semiconductor chips210and the dummy chip230D may be proportional to the mounting heights (Ha and Hb), and the thicknesses (e.g., T1a<T1b) of the non-conductive adhesive layer317for each portion may be inversely proportional to the mounting heights (e.g., Ha>Hb). In the semiconductor package10D according to this embodiment, all of the upper portions of the first lower semiconductor chips210and the dummy chip230D may be received in the non-conductive adhesive layer317disposed on a lower surface of the upper semiconductor chip300. Therefore, a firm joint between the first lower semiconductor chips210, the dummy chip230D, and the upper semiconductor chip300may be provided, and after a molded member500is applied, generation of voids may be reduced and/or suppressed. FIG.12is a cross-sectional view of a semiconductor package according10E to an embodiment of the present inventive concepts. Referring toFIG.12, it may be understood that a semiconductor package10E according to this embodiment has a similar structure as the embodiment illustrated inFIGS.1and2, except that a dummy chip400as an upper chip structure is further included. Therefore, the description of the embodiment illustrated inFIGS.1to3may be combined with a description of this embodiment, unless otherwise stated. The cross-section ofFIG.12is taken along a similar perspective/location as the line I-I′ of the semiconductor package10ofFIG.1, though the structures of the semiconductor package10E ofFIG.12may differ from those of semiconductor package10ofFIG.1. Lower chip structures of the semiconductor package10E include first and second lower semiconductor chips210and220disposed side by side on the package substrate100, similar to the embodiment illustrated inFIG.2. The dummy chip400, such as a reinforcing member or a heat dissipation member, may be employed as the upper chip structure. The dummy chip400may be disposed on active surfaces (and/or upper surfaces) of the first and second lower semiconductor chips210and220. In some embodiments, the dummy chip400may be a heat dissipation member. An upper surface400T of the dummy chip400may be exposed from an upper surface500T of a molded member500. The upper surface400T of the dummy chip400may be coplanar with the upper surface SOOT of the molded member500. The first and second lower semiconductor chips210and220mounted on the package substrate100may have different heights (Ha and Hb). Upper portions of the first and second lower semiconductor chips210and220may be received in a non-conductive adhesive layer317. In view of a thickness of each portion of the non-conductive adhesive layer317, a thickness (T2) of a portion of the non-conductive adhesive layer317between the first and second lower semiconductor chips210and220may be greater than a thickness (T1aand/or T1b) of the non-conductive adhesive layer317respectively bonded to the first and second lower semiconductor chips210and220. Received depths of the first and second lower semiconductor chips210and220may be proportional to the mounting heights (Ha and/or Hb), and the thickness (e.g., T1a<T1b) of each portion of the non-conductive adhesive layer317may be inversely proportional to the mounting heights (e.g., Ha>Hb). In some embodiments, the dummy chip400may be aligned relatively horizontally, despite a difference in levels of the upper surfaces of the first and second lower semiconductor chips210and220. In addition, in the semiconductor package10E according to some embodiments, both the upper portions of the first and second lower semiconductor chips210and220may be received in the non-conductive adhesive layer317disposed on a lower surface of the dummy chip400. Therefore, a firm joint between the second lower semiconductor chips210and220and the dummy chip400may be provided, and after a molded member500is applied, generation of voids may be reduced and/or suppressed. FIG.13is a cross-sectional view of a semiconductor package10F according to an embodiment of the present inventive concepts. Referring toFIG.13, it may be understood that a semiconductor package10F according to this embodiment has a similar structure as the embodiment illustrated inFIGS.1and2, except for a non-conductive adhesive layer317including first and second adhesive material layers317aand317bsequentially arranged on a lower surface of an upper semiconductor chip300. Therefore, the description of the embodiment illustrated inFIGS.1to3may be combined with a description of this embodiment, unless otherwise stated. The cross-section ofFIG.13is taken along a similar perspective/location as the line I-I′ of the semiconductor package10ofFIG.1, though the structures of the semiconductor package10F ofFIG.13may differ from those of semiconductor package10ofFIG.1. Similar to the embodiment illustrated inFIG.2, the semiconductor package10F according to this embodiment may include a package substrate100, first and second lower semiconductor chips210and220arranged on the package substrate100, and an upper semiconductor chip300disposed on the first and second lower semiconductor chips210and220. The upper semiconductor chip300may be bonded to active surfaces of the first and second lower semiconductor chips210and220by a non-conductive adhesive layer317. The first and second lower semiconductor chips210and220mounted on the package substrate100may have different heights (Ha and Hb). Upper portions of the first and second lower semiconductor chips210and220may be received in the non-conductive adhesive layer317. In view of a thickness of each portion of the non-conductive adhesive layer317, a thickness (T2) of a portion of the non-conductive adhesive layer317between the first and second lower semiconductor chips210and220may be greater than a thickness (T1aand/or T1b) of a portion of the non-conductive adhesive layer317respectively bonded to the first and second lower semiconductor chips210and220. Received depths of the first and second lower semiconductor chips210and220may be proportional to mounting heights (Ha and Hb), and the thickness (e.g., T1a<T1b) of each portion of the non-conductive adhesive layer317may be inversely proportional to the mounting heights (e.g., Ha>Hb). The non-conductive adhesive layer317employed in this embodiment may include first and second adhesive material layers317aand317bsequentially arranged on a lower surface of the upper semiconductor chip300. The first adhesive material layer317aand the second adhesive material layer317bmay be formed of different materials. Before curing, the first adhesive material layer317amay be configured to have a viscosity smaller than that of the second adhesive material layer317b. Since the second adhesive material layer317bhas a relatively high viscosity, a space between the first and second lower semiconductor chips210and220and the upper semiconductor chip300may be secured using a thickness (T2b) of the second adhesive material layer317b. Wires215and225may be located in the space. In some embodiments, the thickness T1aof a portion of the non-conductive adhesive layer317between the first lower semiconductor chip210and the upper semiconductor chip300may include portions of the first adhesive material layer317aand/or the second adhesive material layer317b. In some embodiments, the thickness T1bof a portion of the non-conductive adhesive layer317between the second lower semiconductor chip220and the upper semiconductor chip300may include portions of the first adhesive material layer317aand/or the second adhesive material layer317b. The first adhesive material layer317amay have the thickness (T2b) sufficient to receive upper portions of the first and second lower semiconductor chips210and220. Upper surfaces of the first and second lower semiconductor chips210and220may be located on different levels in the first adhesive material layer317aand/or the second adhesive material layer317b. In some embodiments, an upper surface210T of the first lower semiconductor chip210may be higher than an upper surface220T of the second lower semiconductor chip220, and the upper surface210T of the first lower semiconductor chip210may be located on substantially the same level as an interface of the first and second adhesive material layers317aand317b, and/or nearer to the interface than the upper surface220T of the second lower semiconductor chip220. As described above, the first and second lower semiconductor chips210and220may be received at different depths by using the first adhesive material layer317aand the second adhesive material layer317bhaving different viscosities. A space between the first and second lower semiconductor chips210and220and the upper semiconductor chip300may be stably provided. FIGS.14A and14Bare cross-sectional views of a semiconductor package10G according to an embodiment of the present inventive concepts. Referring toFIGS.14A and14B, it may be understood that a semiconductor package10G according to this embodiment has a similar structure as the embodiment illustrated inFIGS.9A and9B, except for a non-conductive adhesive layer317including first and second adhesive material layers317aand317bsequentially arranged on a lower surface of an upper semiconductor chip300. Therefore, the description of the embodiment illustrated inFIGS.8and9A and9Bmay be combined with a description of this embodiment, unless otherwise stated. The cross-sections ofFIGS.14A and14Bare respectively taken along a similar perspective/location as the lines II1-II1′ and II2-II2′ of the semiconductor package10C ofFIG.8, though the structures of the semiconductor package10G ofFIGS.14A and14Bmay differ from those of semiconductor package10C ofFIG.8. Similar to the embodiment illustrated inFIGS.8,9A, and9B, The semiconductor package10G according to this embodiment may include a package substrate100, first to third lower semiconductor chips210,220, and230arranged on the package substrate100, first and second dummy chips240D1and240D2arranged on the package substrate100, and an upper semiconductor chip300arranged on the first to third lower semiconductor chips210,220, and230and the dummy chips240D1and240D2. The upper semiconductor chip300may be bonded to active surfaces of the first to third lower semiconductor chips210,220, and230and upper surfaces of the first and second dummy chips240D1,240D2by a non-conductive adhesive layer317. The non-conductive adhesive layer317employed in this embodiment may include first and second adhesive material layers317aand317bsequentially arranged on a lower surface of the upper semiconductor chip300. The first adhesive material layer317amay be configured to have a viscosity lower than that of the second adhesive material layer317b. A space between the first to third lower semiconductor chips210,220, and230and the first and second dummy chips240D1and240D2and the upper semiconductor chip300using the second adhesive material layer317bhaving a relatively high viscosity may be secured, and wires215,225, and235may be located in the secured space. Upper surfaces210T and220T of the first and second lower semiconductor chips210and220and an upper surface230T of the third lower semiconductor chip230may be located on different levels in the first adhesive material layer317a. In an embodiment, the upper surface210T of the first lower semiconductor chip210may be located higher than the upper surface220T of the second lower semiconductor chip220. In some embodiments, upper surfaces240T of the first and second dummy chips240D1and240D2, and may be located on substantially the same level as an interface between the first and second adhesive material layers317aand317b, though the present inventive concepts are not limited thereto. As such, in a process of receiving the lower chip structures210,220,230,240D1, and240D2at different depths, the first adhesive material layer317aand the second adhesive material layer317bhaving different viscosities may be used to stably ensure a space between the lower chip structures210,220,230,240D1, and240D2and the upper semiconductor chip300. In some embodiments, the thickness T1aof a portion of the non-conductive adhesive layer317between the first lower semiconductor chip210and the upper semiconductor chip300may include portions of the first adhesive material layer317aand/or the second adhesive material layer317b. In some embodiments, the thickness T1bof a portion of the non-conductive adhesive layer317between the second lower semiconductor chip220and the upper semiconductor chip300may include portions of the first adhesive material layer317aand/or the second adhesive material layer317b. In some embodiments, the thickness T1cof a portion of the non-conductive adhesive layer317between the third lower semiconductor chip230and the upper semiconductor chip300may include portions of the first adhesive material layer317aand/or the second adhesive material layer317b. In some embodiments, the thickness T1dof a portion of the non-conductive adhesive layer317between the first and second dummy chips240D1and240D2and the upper semiconductor chip300may include portions of the first adhesive material layer317aand/or the second adhesive material layer317b. Even when a plurality of lower chip structures are arranged at different heights on the package substrate, a relatively low viscosity non-conductive adhesive layer may be used to stack an upper chip structure, to solve poor adhesion of a portion of the lower chip structures (especially lower chip structures having relatively low heights) due to a difference in height of the lower chip structures, or degradation of reliability due to occurrence of voids (after applying a molded member). Various and advantages and effects of the present inventive concepts are not limited to the above description. While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concepts as set forth by the appended claims. | 49,032 |
11862604 | DETAILED DESCRIPTION The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings as described below. It is noted that, for purposes of illustrative clarity, certain elements in various drawings may not be drawn to scale. The configuration of various levels of a stacked integrated circuit including methods for producing such are described herein. In accordance with many embodiments chiplets are bonded to a chip with DBI technology having fine pitch interconnects and TSVs wherein a bump plane is created and releveled creating a single level bump plane for additional boding of layers. Integrated circuit design generally deals with the creation of electrical components and the design and placement of such components onto a platform such as a silicon wafer. The design and layout of the electrical components is performed in such a way as to create functional blocks designed to perform certain processes of the integrated circuit. For example, some blocks may be a complex layout comprising a core of a processor; others may serve as controllers such as memory or graphics controllers, while others may be advanced SerDes Blocks. In other examples, the blocks can be as simple as amplifiers or gain blocks that may serve as attenuators or amplifiers. In some instances, the blocks may also comprise various types of passive elements such as resistors, capacitors and/or inductors that form the basis of an analog circuit. The analog circuit may be one type of circuit used in the design process wherein the layout of the various elements may be in series or parallel according to the overall function and physical constraints of the system. Moreover, such elements may use a heterogeneous processes which combines different foundry nodes and/or technologies such as Silicon Germanium (SiGe), Gallium Arsenide (GaAs), etc. The blocks may be considered the building blocks of an integrated circuit and each one is a carefully mapped out plan of transistors, resistors, capacitors and metallic interconnects forming the functional blocks of the IC design.FIG.1illustrates an example of an IC with various “blocks” depicted. For example,FIG.1illustrates an IC with various processing units (PU)110as well as L2Cache blocks120, and some SerDes blocks130. These are a few examples of how blocks fit into the overall system design. The demand for smaller, higher performing, and higher capacity components affects the design of the overall IC. IC design is mapped out in functional blocks. The functional blocks often include but are not limited to cores, memory controllers, processor controllers, parallel interface chips, and in some cases SerDes blocks. SerDes block is a configured portion of an IC in which a large number of parallel paths on the input end and converts them to a smaller number of high speed communication paths on the output end. SerDes blocks can take up large portions of a silicon substrate and require the placement on an advanced portion of the IC node. This is also true for other complex blocks in the IC. Furthermore, as the size of the IC decreases the IP design of the SerDes block and other advanced blocks can be affected such that the blocks become highly sensitive to rotational placement. In other words, as the size of the IC decreases and room becomes limited an advanced block cannot just be rotated to fit the space because the IP design on one side will not be equivalent to that on the other side. The rotational sensitivity increases the number of designs required per IC, which can increase costs if designers have to maintain multiple designs for various rotational positions. The bonding of layers of an IC has become an important aspect of the industry as the complexity of design increases and manufactures are looking for ways to improve efficiency of the product. An approach to bond layers of an IC is taught in U.S. Pat. No. 6,962,835 to Tong et al., which is incorporated herein by reference in its entirety. As taught by Tong a method of bonding layers known as Direct Bond Interconnect (DBI®) allows for layers to be bonded with an extremely fine pitch. Pitch refers to the ratio of thickness and distance between interconnects. Wafer direct bonding allows wafers to be bonded at room temperature without using any adhesive. In more detail, as the wafer surfaces including the metal bonding pads contact at room temperature, the contacting non-metal parts of opposing wafer surfaces began to form a bond at the contact point or points, and the attractive bonding force between the wafers increases as the contact chemical bonding area increases. Without the presence of the metal pads, the wafers would bond across the entire wafer surface. According to the present invention, the presence of the metal pads, while interrupting the bonding seam between the opposing wafers, does not prohibit chemical wafer to wafer bonding. Due to the malleability and ductility of the metal bonding pads, the pressure generated by the chemical wafer-to-wafer bonding in the non-metal regions may results in a force by which nonplanar and/or rough regions on the metal pads may be deformed resulting in improved planarity and/or roughness of the metal pads and intimate contact between the metal pads. The pressure generated by the chemical bonding is sufficient to obviate the need for external pressure to be applied in order for these metal pads to be intimately contacted to each other. A strong metallic bond can be formed between the intimately contacted metal pads, even at room temperature, due to inter-diffusion or self-diffusion of metal atoms at the mating interface. This diffusion is thermodynamically driven to reduce the surface free energy and is enhanced for metals that typically have high inter-diffusion and/or self-diffusion coefficients. These high diffusion coefficients are a result of a cohesive energy that is typically mostly determined by the mobile free electron gas that is not disturbed by the motion of metal ions during the diffusion The wafer-to-wafer chemical bonding in the non-metal regions thus effects electrical connection between metal pads on the two different wafers. The geometrical and mechanical constraints governing this effect are described below. DBI technology is enhancing the ability to improve the design of integrated circuits through the use of chiplets. As technology developed with regards to integrated circuit design, blocks may have been contained in individualized chiplets or die that were fit into a larger system called multi-chip modules or System in Package (SIP). As the technology improved the individual chiplets were replaced with system on chip (SOC) design as analog and digital content (mixed signal) could be integrated into a single chip. With further improvements, including DBI technology, interconnects now have the capability of equaling the density of the SOC connections. The use of chiplets allows for advanced blocks such as SerDes to be removed from the main body of the IC chip and still serve as a functional block of the overall IC. This is an improvement over past chip designs because it increases the available space on the chip for other functional blocks while still maintaining the advanced blocks necessary for the ever-increasing demand. However, the DBI technology with the use of chiplets generates an issue with respect to the bump planes that are used in chip to chip bonding. Bump planes extend the interconnects to the next level assembly, such as another chip, interposer, substrate, etc., as illustrated inFIG.11; thus, providing that the overall chip function is maintained between stacked layers. Bump planes are typically metallic buildups from the chip surface to a level height and will become a preferable method for creating a new bonding surface with the increased use of chiplets in IC design. Turning now toFIG.2a, in many embodiments a chip or substrate220is bonded with a plurality of chiplets210using DBI technology. It can be seen from the side view inFIG.2bthe use of chiplets according to many embodiments creates an uneven or multi-level surface from which to bond the next layer or chip of the IC. In accordance with many embodiments, the bonding surface should be as level as possible given the constraints of the technology to properly form a bond with the next layer. The bonded chiplets may be configured with through silicon vias (TSVs)215that create interconnects between the outer surface of the chiplet and the underlying chip. The TSVs215will be the interconnect points from which bumps or posts are built upon as will be further described herein. It should be noted that when making reverence to plating the bumps/posts on the chiplet level it is done so in coordination with the TSVs215of the chiplets. In accordance with many embodiments,FIGS.3-5and7illustrate process flows of methods of releveling the bump plane such that it is at one level rather than multiple levels after the bonding of chiplets to the chip. It is preferable according to many embodiments to bond the chiplets using the DBI technology referenced herein. In accordance with many embodiments, the process of releveling the bump plane begins with the creating of a multi-level surface through the bonding of chiplets to a chip. This is done as illustrated by the process flows inFIGS.3-5and7as the beginning two steps of the processes according to many embodiments. The chips and the chiplets may be processed to prepare the chips and chiplets to be bonded via DBI technology. DBI bonding technique requires the flattening of the bonding surface to the extent that it is as flat as possible. In many cases the flattening actually creates a concave like surface that aids in the bonding. The bond is then formed between an oxide and metallic, usually copper, layer at room temperature or low temperature settings. The bond generally comprises a combination of covalent bonds and Van der Waals bonds. In many embodiments the bond is then low temperature annealed thereby creating a strong fine pitch interconnect between the two layers. The preparation and DBI bonding of the chips to chiplets is represented in steps310and315respectively inFIGS.3-5and7according to many embodiments. Now turning the focus to the flow diagram inFIG.3, as the chiplets and chips are bonded, preferably thought DBI technology, an uneven surface is created as illustrated inFIG.2b. The uneven surface now requires an even surface for subsequent bonding of chips in the process of 3-D stacking. The chip/chiplet combination surface may be passivated320with an inert solution that might render any metallic surfaces inert during the next few steps of the process. In many embodiments, the passivation320may be done with a nitride. While nitride is presented in step320any number of passivation substances may be used for this purpose. Once passivation is complete, many embodiments may preferably apply a photo resist (PR) layer325wherein the PR layer is patterned, exposed such that openings are created exposing the lower chip surface. The application of a PR layer810is pictorially illustrated inFIG.8by element810. In accordance with many embodiments the passivation is then etched330followed by the removal of the PR layer335. Prior to building the bump plane or bumps that will ultimately form a bump plane, many embodiments may involve the application of a seed layer350. A seed layer generally refers to an electroless plating of a thin layer of metal by which the subsequent bumps may be built upon. The seed layer enables the plating of the interconnects. There may also be a barrier metal adjacent to the seed which would aid in preventing electromigration or undesirable intermetallic formations. In accordance with many embodiments the seed layer may be placed by sputtering, atomic layer deposition (ALD), physical vapor deposition (PVD) or by Chemical Vapor Deposition (CVD). Once the seed layer is placed340, a second PR layer may be patterned and exposed creating openings to the chip and chiplet levels according to various embodiments. With the chip and chiplet surfaces exposed according to the desired pattern, the bumps or posts may then be plated350according to many embodiments. Referencing nowFIG.8, according to many embodiments the posts or bumps820are plated up through the second PR layer810wherein and a desired finalized bump plane may be present based on the height of the lowest level of bumps. In accordance with many embodiments the bumps are plated such that those connected to the lower chip level extend at least beyond the height of the chiplets. This can be seen inFIG.8where the portion of bumps810connected to the chip220extend beyond the height of the chiplets210. According to many embodiments the finalized bump plane is releveled using a planarization or physical removal of the plated bumps and remaining PR level thus creating a level bump plane represented by element830inFIG.8and shown on the flow chart ofFIG.3in step355. Once the bump plane has been planarized and leveled355, a solder cap822(FIG.8) may then be plated on the bumps for the future bonding of two subsequent chips, according to various embodiments. The final steps in releveling the bump plane according to many embodiment involves the removal of365the remaining PR layer as well as stripping370the seed layer. Thus, the releveled bump plane of a chip to chiplet IC is illustrated inFIG.8b. In accordance with various other embodiments, the releveling of the bump plane may be done via other process steps illustrated inFIG.4. Similar to the process illustrated inFIG.3, many embodiments, as illustrated inFIG.4, utilize the DBI technology by preparing and bonding the chiplets to chips prior to building and leveling of a bump plane. In accordance with many embodiments, the process flow illustrated inFIG.4may pattern and expose a PR layer510without the application of a passivation layer illustrated by step320ofFIG.3. In accordance with various embodiments, the PR layer is patterned and exposed such that only the edges of the chiplets are left covered with a PR material. This can be further illustrated byFIG.6wherein the edges of the chiplets remain covered by the PR layer610. This is a preferable process because the subsequent application of a seed layer415will not create metallic contacts to the edges of the chiplets, which will aid in the building up or plating of the bumps. Once a seed layer is placed415in accordance with embodiments illustrated inFIG.4, a second PR layer is patterned and exposed to open the desired interconnect locations on the chip and chiplets. From there, similar to the embodiments previously illustrated inFIG.3the bumps or posts are then plated and built up to the desired level. In accordance with many embodiments, the plating of the bumps occurs at a certain rate and when it is completed the remaining surface is still uneven requiring the subsequent removal of material to have a level surface. Preferably, the removal or releveling of the surface is done through planarization or cutting off of material. In many embodiments the planarization355,430,530, and745may be done by any number of methods that may include the use of grinding, chemical-mechanical polish (CMP) or laser ablation. Similar to the process illustrated inFIG.3, and according to various embodiments, step435involves the application of a solder cap for subsequent chip to chip bonding. In accordance with many embodiments and illustrated inFIG.4, steps440through450involve the removal of the previously applied PR layers and seed layer. In many embodiments, the removal of the PR and seed layers is done through chemical etching by which the relatively thin layers are removed with little effect on the plated bumps or other more permanent layers. Turning now toFIG.5, according to some embodiments, the process illustrated therein is similar to that ofFIG.4with the absence of the additional PR removal steps.FIG.5illustrates one of various embodiments in which a single PR removal process is used540. In some embodiments the PR removal process may include the removal of all the PR layers applied; while in other embodiments some may remain. FIG.7illustrates another process flow in accordance with various embodiments. The flow illustrated is similar to that presented inFIGS.4and5, however the releveling of the bump plane may follow another process after the posts or bumps have been plated. For example, before planarizing the posts the PR layers and seed layer may be removed730and735. Additionally, prior to planarizing745to reveal the posts a type of molding740may be formed or applied to the chiplet side of the IC thereby covering the exposed surfaces of the larger chip and chiplets as wells as the plated posts of the chip and chiplets. In some embodiments this may be similar to the PR layer810illustrated inFIG.8. In accordance with many embodiments, the molding may be a compression type molding while in other embodiments, the molding may be a vacuum format. In accordance with many embodiments, the molding may be an epoxy or silicon based material. Once the molding has been applied or formed covering the surfaces, the layer may be planarized or back-ground. Back-grinding refers to a post process by which a layer or layers may be removed by any suitable method that will result in exposing the plated posts. The exposure of the plated posts by planarizing thus establishes a re-leveled bump plane from which the posts, and thus the IC with chiplets, may be prepared for subsequent bonding. Once the planarization has been completed, the exposed posts/bumps may be prepared for bonding using any suitable method. In accordance with many embodiments the preparing of the posts may be done by the application of a redistribution layer (RDL). An RDL is an additional layer that allows for the interconnects to be redistributed to other locations. Additionally, other embodiments may include the use of a Re-passivation (RePSV). After RDL or RePSV the solder cap may be applied thereby creating the bumps required to will allow the re-leveled chip with chiplets to be bonded to the subsequent layers. Turning now toFIG.9, according to many embodiments the bump plane may be configured and releveled using any number of processes presented herein where a permanent layer of material910, such as a mold layer, may be applied to the chip after a base layer of posts have been plated from the chip level. In accordance with many embodiments, the permanent layer may be a permanent resist layer or a dielectric layer. In accordance with various embodiments, the permanent layer may then be ground down or partially removed to expose the die. In other embodiments the grinding of the surface may only be done to remove as much material as necessary to create a surface just above the level of the chiplet. One exemplary method would be to leave a small surface above the chiplet to eliminate the need for additional dielectric material. The back grinding or partial removal of the permanent layer910may be considered equivalent to the planarization of other methods presented herein because the intent is to create one level surface from which to build the permanent interconnection bumps. In other words, it is to create the releveled bump plane. In accordance with many embodiments a PR layer may then be patterned on top of the background permanent layer and exposed so as to create openings to the pre-plated posts and the chiplets such that a final plating may occur to create the final bump level for future bonding. According to many embodiments,FIG.10illustrates another method of plating of the posts that may be used in conjunction with any number of processes described herein or which may be deemed suitable. For example,FIG.10illustrates a process by which the entire surface of chip and chiplets is patterned and exposed to create holes to the chiplets and chip accordingly. However, in accordance with many embodiments the exposed holes to the chips are larger than those for the chiplets. The process of plating over the entire surface where some holes are larger than others will result in the larger holes producing larger bumps1010at the same rate as the smaller bumps corresponding to the chiplets. Thus, the timed plating process will result in a single level plane of bumps or posts by which future bonding may occur. In accordance with many embodiments described herein, the releveled bump plane on the chip is then ready for bonding to the next level assembly, such as the another chip, interposer, substrate, etc. In accordance with many embodiments bonding may follow the process steps discussed previously or in other embodiments the chiplets may be predisposed with posts on a back side surface and the chips may also have posts pre-plated to the chip to chiplet bonding surface. This is illustrated inFIG.11where the pre-posted chiplets1120may be configured to have posts at a first height and prepared to be bonded to the chip220. The chip220, in accordance with various embodiments described herein, may have the bump plane and corresponding posts1130configured to the same level as the pre-posted chiplets1120. In such embodiments the posts on the chiplets and those on the chip may be the same or similar height such that minimal processing is necessary to create a bond. The configuration is then ready to be bonded to the next level assembly1110. Doctrine of Equivalents This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims. | 22,237 |
11862605 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments will be described with respect to embodiments in a specific context, namely an integrated circuit package, such as a 3DIC package, and a method of forming the same. Other embodiments may also be applied, however, to other electrically connected components, including, but not limited to, package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, in assembling packaging, in processing substrates, interposers, or the like, or mounting input components, boards, dies or other components, or for connection packaging or mounting combinations of any type of integrated circuit or electrical component. Various embodiments described herein allow for forming integrated circuit packages by direct bonding integrated circuit dies to one another. Various embodiments described herein further allow for embedding heat dissipation structures within integrated circuit packages and reducing a time for formation of the heat dissipation structures and the integrated circuit packages. Accordingly, a wafer per hour (WPH) yield may be increased and production cost may be reduced during the production of integrated circuit packages. FIGS.1A and1Billustrate top and cross-sectional views of an integrated circuit (IC) package100in accordance with some embodiments.FIG.1Aillustrates a top view, whileFIG.1Billustrated a cross-sectional view along a line BB′ inFIG.1A. In some embodiments, the IC package100comprises a first IC die structure101bonded to a second IC die structure103. In some embodiments, the first IC die structure101is electrically connected to the second IC die structure103. The first IC die structure101comprises an IC die105encapsulated in encapsulants107and109. In some embodiments, the IC die105may comprise a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, an SoC die, or the like. In some embodiments, the IC die105may be formed using a method described below with reference toFIGS.17A-17C, and the detailed description of the IC die105is provided at that time. The encapsulants107and109may comprise suitable insulating materials. In some embodiments, the encapsulants107and109may comprise a same material. In other embodiments, the encapsulants107and109may comprise different materials. In some embodiments, the first IC die structure101further comprises a plurality of connectors111on a front side of the IC die105, which electrically connect the IC package100to external components bonded to the connectors111. In some embodiments, the first IC die structure101may be formed using a method described below with reference toFIGS.20A and20B, and the detailed description of the first IC die structure101is provided at that time. The second IC die structure103comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174bonded to one another in a pairwise manner, such that a backside of one IC die in a pair is bonded to a front side of another die in the pair. Furthermore, a front side of the IC die1171of the die stack113is bonded to the base structure115and a backside of the IC die1174is bonded to a backside of the IC die105. In some embodiments, the IC dies1171-1174may comprise a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, an SoC die, or the like. In some embodiments, the IC dies1171-1174may be formed using a method described below with reference toFIGS.17A-17C,18A and18B, and the detailed description of the IC dies1171-1174is provided at that time. The base structure115may comprise a semiconductor material, an insulating material, a combination thereof, or the like. In some embodiments, the base structure115may comprise a same material as the substrate of the IC dies105and1171-1174. In such embodiments, the base structure115and the IC dies105and1171-1174may have substantially similar coefficients of thermal expansion (CTEs), which may prevent the damage of the IC package100due to the CTE mismatch. In some embodiments, the base structure115may not comprise active and/or passive devices on or in the base structure115. In some embodiments, the IC dies1171-1174are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the encapsulants1231-1234may comprise a suitable insulating material. In some embodiments, the encapsulants1231-1234may comprise a same material. In other embodiments, the encapsulants1231-1234may comprise different materials. In some embodiments, the die structure103further comprises stacked dummy structures119, such that the die stack113is interposed between the adjacent stacked dummy structures119. In some embodiments, each stacked dummy structure119comprises a stack of dummy structures1211-1214, such that the encapsulants1231-1234are interposed between the dummy structures1211-1214and the IC dies1171-1174, respectively. The dummy structures1211-1214may comprise a semiconductor material, an insulating material, a combination thereof, or the like. In some embodiments, the dummy structures1211-1214may comprise a same material as the substrates of the IC dies105and1171-1174. In such embodiments, the dummy structures1211-1214and the IC dies105and1171-1174may have substantially similar CTEs, which may prevent the damage of the IC package100due to the CTE mismatch. In some embodiments, the dummy structures1211-1214may not comprise active and/or passive devices and may not provide addition electrical functionality to the IC package100. In some embodiments, the stacked dummy structures119may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure101. Accordingly, the stacked dummy structures119may also be referred to as heat dissipation structures119. Referring further toFIGS.1A and1B, the stacked dummy structures119and the base structure115may have a rectangular shape in a top view. In some embodiments, three sidewalls of each stacked dummy structure119are substantially coplanar with respective three sidewalls of the base structure115, such that a first width of the stacked dummy structures119is substantially equal to the a first width W1of the base structure115and a second width W2of the base structure115is greater than a second width W3of the stacked dummy structures119. In some embodiments, the width W1may be between about 5 mm and about 10 mm. In some embodiments, the width W2may be between about 7 mm and about 15 mm. In some embodiments, the width W3may be between about 1 mm and about 4 mm. In some embodiments, a ratio W1/W2may be between about 0.7 and about 0.6. In some embodiments, a ratio W1/W3may be between about 5 and about 2.5. In some embodiments, a ratio W2/W3may be between about 7 and about 3.75. In the embodiment illustrated inFIGS.1A and1B, the first IC die structure101comprises a single IC die (such as the IC die105), and the second IC die structure103comprises a single die stack (such as the die stack113) comprising four IC dies (such as the IC dies1171-1174) and two dummy structures (such as the stacked dummy structures119) each comprising a stack of four dummy structures (such as the dummy structures1211-1214). In other embodiments, the first IC die structure101may comprise more than one IC die, and the second IC die structure103may comprise more than one die stack comprising more or less than four IC dies and more or less than two dummy structures comprising stacks of more or less than four dummy structures, depending on design requirements for the IC package100. In some embodiments, the IC package100may be formed using a method described below with reference toFIGS.21A-21H, and the detailed description of the IC package100is provided at that time. FIGS.2A and2Billustrate top and cross-sectional views of an IC package200in accordance with some embodiments.FIG.2Aillustrates a top view, whileFIG.2Billustrated a cross-sectional view along a line BB′ inFIG.2A. To highlight differences between the IC package200and the IC package100(seeFIGS.1A and1B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package200comprises a first IC die structure101bonded to a second IC die structure201. In some embodiments, the first IC die structure101is electrically connected to the second IC die structure201. The second IC die structure201comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the second die structure201further comprises stacked dummy structures203, such that the die stack113is interposed between the adjacent stacked dummy structures203. In some embodiments, each stacked dummy structures203comprises a stack of dummy structures2051-2054, such that the encapsulants1231-1234are interposed between the dummy structures2051-2054and the IC dies1171-1174, respectively. In some embodiments, the dummy structures2051-2054may be formed using similar materials and methods as the dummy structures1211-1214described above with reference toFIGS.1A and1B, and the description is not repeated herein. In some embodiments, the stacked dummy structures203may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure101. Accordingly, the stacked dummy structures203may also be referred to as heat dissipation structures203. Referring further toFIGS.2A and2B, the stacked dummy structures203and the base structure115may have a rectangular shape in a top view. In some embodiments, two sidewalls of each stacked dummy structure203are substantially coplanar with respective two sidewalls of the base structure115. In some embodiments, a first width W4of the stacked dummy structures203is less than a first width W1of the base structure115and a second width W5of the stacked dummy structures203is less than a second width W2of the base structure115. In some embodiments, the width W4may be between about 4.0 mm and about 9.5 mm. In some embodiments, the width W5may be between about 1 mm and about 4 mm. In some embodiments, a ratio W1/W4may be between about 1.25 and about 1.5. In some embodiments, a ratio W1/W5may be between about 5 and about 2.5. In some embodiments, a ratio W2/W4may be between about 1.75 and about 1.5. In some embodiments, a ratio W2/W5may be between about 7 and about 3.75. In some embodiments, a ratio W4/W5may be between about 5 and about 2.5. In some embodiments, the IC package200may be formed using a method described below with reference toFIGS.21A-21H, and the detailed description of the IC package200is provided at that time. FIGS.3A and3Billustrate top and cross-sectional views of an IC package300in accordance with some embodiments.FIG.3Aillustrates a top view, whileFIG.3Billustrated a cross-sectional view along a line BB′ inFIG.3A. To highlight differences between the IC package300and the IC package100(seeFIGS.1A and1B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package300comprises a first IC die structure101bonded to a second IC die structure301. In some embodiments, the first IC die structure101is electrically connected to the second IC die structure301. The second IC die structure301comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the die structure103further comprises stacked dummy structures303, such that the die stack113is interposed between the adjacent stacked dummy structures303. In some embodiments, each stacked dummy structure303comprises a stack of dummy structures3051-3054, such that the encapsulants1231-1234are interposed between the dummy structures3051-3054and the IC dies1171-1174, respectively. In some embodiments, the dummy structures3051-3054may be formed using similar materials and methods as the dummy structures1211-1214described above with reference toFIGS.1A and1B, and the description is not repeated herein. In some embodiments, the stacked dummy structures303may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure101. Accordingly, the stacked dummy structures303may also be referred to as heat dissipation structures303. Referring further toFIGS.3A and3B, the stacked dummy structures303and the base structure115may have a rectangular shape in a top view. In some embodiments, a sidewall of each stacked dummy structure303is substantially coplanar with a respective sidewall of the base structure115. In some embodiments, a first width W6of the stacked dummy structures303is less than a first width W1of the base structure115and a second width W7of the stacked dummy structures303is less than a second width W2of the base structure115. In some embodiments, the width W6may be between about 3 mm and about 9 mm. In some embodiments, the width W7may be between about 1 mm and about 4 mm. In some embodiments, a ratio W1/W6may be between about 1.6 and about 1.1. In some embodiments, a ratio W1/W7may be between about 5 and about 2.5. In some embodiments, a ratio W2/W6may be between about 2.3 and about 1.6. In some embodiments, a ratio W2/W7may be between about 7.0 and about 3.75. In some embodiments, a ratio W6/W7may be between about 3 and about 2.25. In some embodiments, the IC package300may be formed using a method described below with reference toFIGS.21A-21H, and the detailed description of the IC package300is provided at that time. FIGS.4A and4Billustrate top and cross-sectional views of an IC package400in accordance with some embodiments.FIG.4Aillustrates a top view, whileFIG.4Billustrated a cross-sectional view along a line BB′ inFIG.4A. To highlight differences between the IC package400and the IC package100(seeFIGS.1A and1B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package400comprises a first IC die structure101bonded to a second IC die structure401. In some embodiments, the first IC die structure101is electrically connected to the second IC die structure401. The second IC die structure401comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the second IC die structure401further comprises stacked dummy structures403, such that the die stack113is interposed between the adjacent stacked dummy structures403. In some embodiments, each stacked dummy structure403comprises a stack of dummy structures4051-4054, such that the encapsulants1231-1234are interposed between the dummy structures4051-4054and the IC dies1171-1174, respectively. In some embodiments, the dummy structures4051-4054may be formed using similar materials and methods as the dummy structures1211-1214described above with reference toFIGS.1A and1B, and the description is not repeated herein. In some embodiments, the stacked dummy structures403may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure101. Accordingly, the stacked dummy structures403may also be referred to as heat dissipation structures403. Referring further toFIGS.4A and4B, the stacked dummy structures403and the base structure115may have a rectangular shape in a top view. In some embodiments, two sidewalls of each stacked dummy structure403are substantially coplanar with respective two sidewall of the base structure115. In some embodiments, the stacked dummy structures403(such as stacked dummy structures4031and4032) disposed at opposite corners of the base structure115have different dimensions. In some embodiments, a first width W9of the stacked dummy structures4031is less than a first width W1of the base structure115. In some embodiments, a first width W8of the stacked dummy structures4032is less than the first width W1of the base structure115. In some embodiments, the width W8is different from the width W9. In other embodiments, the width W8may be substantially equal to the width W9. In some embodiments, a second width of the stacked dummy structures4031may equal to a second width of the stacked dummy structures4032and may equal to a width W10. In some embodiments, the width W10is less than a second width W2of the base structure115. In some embodiment, a sum of the widths W8and W9is less than the width W1. In some embodiments, the width W8may be between about 2 mm and about 4.5 mm. In some embodiments, the width W9may be between about 2 mm and about 4.5 mm. In some embodiments, the width W10may be between about 1 mm and about 4 mm. In some embodiments, a ratio W1/W8may be between about 2.5 and about 2. In some embodiments, a ratio W1/W9may be between about 2.5 and about 2. In some embodiments, a ratio W1/W10may be between about 5 and about 2.5. In some embodiments, a ratio W2/W8may be between about 3.5 and about 3. In some embodiments, a ratio W2/W9may be between about 3.5 and about 3. In some embodiments, a ratio W2/W10may be between about 7 and about 3.75. In some embodiments, a ratio W8/W9may be between about 1 and about 2.5. In some embodiments, a ratio W8/W10may be between about 2 and about 1. In some embodiments, a ratio W9/W10may be between about 2 and about 1. In some embodiments, the IC package400may be formed using a method described below with reference toFIGS.21A-21H, and the detailed description of the IC package400is provided at that time. FIGS.5A and5Billustrate top and cross-sectional views of an IC package500in accordance with some embodiments.FIG.5Aillustrates a top view, whileFIG.5Billustrated a cross-sectional view along a line BB′ inFIG.5A. To highlight differences between the IC package500and the IC package100(seeFIGS.1A and1B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package500comprises a first IC die structure501bonded to a second IC die structure503. In some embodiments, the first IC die structure501is electrically connected to the second IC die structure503. In some embodiment, the first IC die structure501is similar to the first IC die structure101(seeFIGS.1A and1B) with the distinction that the first IC die structure501and the first IC die structure101have different backside structures. In some embodiments, the IC die structure501may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the IC die structure501is provided at that time. In some embodiments, the second IC die structure503is similar to the second IC die structure103(seeFIGS.1A and1B) with the distinction that the structure comprising the die stack113, the stacked dummy structures119, and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113and the dummy structures1214of the stacked dummy structures119are bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package500may be formed using a method described below with reference toFIGS.22A-22D, and the detailed description of the IC package500is provided at that time. FIGS.6A and6Billustrate top and cross-sectional views of an IC package600in accordance with some embodiments.FIG.6Aillustrates a top view, whileFIG.6Billustrated a cross-sectional view along a line BB′ inFIG.6A. To highlight differences between the IC package600and the IC package200(seeFIGS.2A and2B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package600comprises a first IC die structure501bonded to a second IC die structure601. In some embodiments, the first IC die structure501is electrically connected to the second IC die structure601. In some embodiment, the first IC die structure501is similar to the first IC die structure101(seeFIGS.2A and2B) with the distinction that the first IC die structure501and the first IC die structure101have different backside structures. In some embodiments, the IC die structure501may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the IC die structure501is provided at that time. In some embodiments, the second IC die structure601is similar to the second IC die structure201(seeFIGS.2A and2B) with the distinction that the structure comprising the die stack113, the stacked dummy structures203, and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113and the dummy structures2054of the stacked dummy structures203are bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package600may be formed using a method described below with reference toFIGS.22A-22D, and the detailed description of the IC package600is provided at that time. FIGS.7A and7Billustrate top and cross-sectional views of an IC package700in accordance with some embodiments.FIG.7Aillustrates a top view, whileFIG.7Billustrated a cross-sectional view along a line BB′ inFIG.7A. To highlight differences between the IC package700and the IC package300(seeFIGS.3A and3B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package700comprises a first IC die structure501bonded to a second IC die structure701. In some embodiments, the first IC die structure501is electrically connected to the second IC die structure701. In some embodiment, the first IC die structure501is similar to the first IC die structure101(seeFIGS.3A and3B) with the distinction that the first IC die structure501and the first IC die structure101have different backside structures. In some embodiments, the IC die structure501may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the IC die structure501is provided at that time. In some embodiments, the second IC die structure701is similar to the second IC die structure301(seeFIGS.3A and3B) with the distinction that the structure comprising the die stack113, the stacked dummy structures303, and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113and the dummy structures3054of the stacked dummy structures303are bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package700may be formed using a method described below with reference toFIGS.22A-22D, and the detailed description of the IC package700is provided at that time. FIGS.8A and8Billustrate top and cross-sectional views of an IC package800in accordance with some embodiments.FIG.8Aillustrates a top view, whileFIG.8Billustrated a cross-sectional view along a line BB′ inFIG.8A. To highlight differences between the IC package800and the IC package400(seeFIGS.4A and4B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package800comprises a first IC die structure501bonded to a second IC die structure801. In some embodiments, the first IC die structure501is electrically connected to the second IC die structure801. In some embodiment, the first IC die structure501is similar to the first IC die structure101(seeFIGS.4A and4B) with the distinction that the first IC die structure501and the first IC die structure101have different backside structures. In some embodiments, the IC die structure501may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the IC die structure501is provided at that time. In some embodiments, the second IC die structure801is similar to the second IC die structure401(seeFIGS.4A and4B) with the distinction that the structure comprising the die stack113, the stacked dummy structures403, and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113and the dummy structures4054of the stacked dummy structures403are bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package800may be formed using a method described below with reference toFIGS.22A-22D, and the detailed description of the IC package800is provided at that time. FIGS.9A and9Billustrate top and cross-sectional views of an IC package900in accordance with some embodiments.FIG.9Aillustrates a top view, whileFIG.9Billustrated a cross-sectional view along a line BB′ inFIG.9A. To highlight differences between the IC package900and the IC package100(seeFIGS.1A and1B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package900comprises a first IC die structure901bonded to a second IC die structure903. In some embodiments, the first IC die structure901is electrically connected to the second IC die structure903. In some embodiments, the first IC die structure901is similar to the first the IC structure101(seeFIGS.1A and1B) with the distinction that the IC die105is encapsulated only in the encapsulant107and the encapsulant109is omitted. In some embodiments, the IC die structure901may be formed using a method described below with reference toFIGS.20A and20B, and the detailed description of the IC die structure901is provided at that time. The second IC die structure903comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, second IC die structure903further comprises an encapsulant907encapsulating the base structure115, the die stack113, and the encapsulants1231-1234. In some embodiments, the encapsulant907may comprise a suitable insulating material. In some embodiments, the encapsulant907and encapsulants1231-1234may comprise a same material. In other embodiments, the encapsulant907and encapsulants1231-1234may comprise different materials. In some embodiments, the second IC die structure903further comprises dummy structures905, such that the die stack113is interposed between adjacent dummy structures905. In some embodiments, the dummy structures905may be formed using similar materials and methods as the dummy structures1211-1214, described above with reference toFIGS.1A and1B, and the description is not repeated herein. In some embodiments, the dummy structures905may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure901. Accordingly, the dummy structures905may also be referred to as heat dissipation structures905. Referring further toFIGS.9A and9B, the dummy structures905and the first IC die structure901may have a rectangular shape in a top view. In some embodiments, three sidewalls of each dummy structure905are substantially coplanar with respective three sidewalls of the first IC die structure901. In some embodiments, a first width of the dummy structures905is substantially equal to a first width W11of the first IC die structure901and a second width W13of the dummy structures905is less than a second width W12of the first IC die structure901. In some embodiments, the width W11may be between about 5 mm and about 10 mm. In some embodiments, the width W12may be between about 7 mm and about 15 mm. In some embodiments, the width W13may be between about 1 mm and about 4 mm. In some embodiments, a ratio W11/W12may be between about 0.7 and about 0.6. In some embodiments, a ratio W11/W13may be between about 5 and about 2.5. In some embodiments, a ratio W12/W13may be between about 7 and about 3.75. In some embodiments, the IC package900may be formed using a method described below with reference toFIGS.23A-23F, and the detailed description of the IC package900is provided at that time. FIGS.10A and10Billustrate top and cross-sectional views of an IC package1000in accordance with some embodiments.FIG.10Aillustrates a top view, whileFIG.10Billustrated a cross-sectional view along a line BB′ inFIG.10A. To highlight differences between the IC package1000and the IC package900(seeFIGS.9A and9B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1000comprises a first IC die structure901bonded to a second IC die structure1001. In some embodiments, the first IC die structure901is electrically connected to the second IC die structure1001. In some embodiments, the second IC die structure1001comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the second IC die structure1001further comprises an encapsulant907encapsulating the base structure115, the die stack113, and the encapsulants1231-1234. In some embodiments, the second IC die structure1001further comprises dummy structures1003, such that the die stack113is interposed between adjacent dummy structures1003. In some embodiments, the dummy structures1003may be formed using a similar materials and methods as the dummy structures905described above with reference toFIGS.9A and9B, and the description is not repeated herein. In some embodiments, the dummy structures1003may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure901. Accordingly, the dummy structures1003may also be referred to as heat dissipation structures1003. Referring further toFIGS.10A and10B, the dummy structures1003and the first IC die structure901may have a rectangular shape in a top view. In some embodiments, two sidewalls of each dummy structure1003are substantially coplanar with respective two sidewalls of the first IC die structure901. In some embodiments, a first width W14of the dummy structures1003is less than a first width W11of the first IC die structure901and a second width W15of the dummy structures1003is less than a second width W12of the first IC die structure901. In some embodiments, the width W14may be between about 4 mm and about 9.5 mm. In some embodiments, the width W15may be between about 1 mm and about 4 mm. In some embodiments, a ratio W11/W14may be between about 1.25 and about 1.5. In some embodiments, a ratio W11/W15may be between about 5 and about 2.5. In some embodiments, a ratio W12/W14may be between about 1.75 and about 1.5. In some embodiments, a ratio W12/W15may be between about 7 and about 3.75. In some embodiments, a ratio W14/W15may be between about 5 and about 2.5. In some embodiments, the IC package1000may be formed using a method described below with reference toFIGS.23A-23F, and the detailed description of the IC package1000is provided at that time. FIGS.11A and11Billustrate top and cross-sectional views of an IC package1100in accordance with some embodiments.FIG.11Aillustrates a top view, whileFIG.11Billustrated a cross-sectional view along a line BB′ inFIG.11A. To highlight differences between the IC package1100and the IC package900(seeFIGS.9A and9B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1100comprises a first IC die structure901bonded to a second IC die structure1101. In some embodiments, the first IC die structure901is electrically connected to the second IC die structure1101. In some embodiments, the second IC die structure1101comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the second IC die structure1101further comprises an encapsulant907encapsulating the base structure115, the die stack113, and the encapsulants1231-1234. In some embodiments, the second IC die structure1101further comprises dummy structures1103, such that the die stack113is interposed between adjacent dummy structures1103. In some embodiments, the dummy structures1103may be formed using a similar materials and methods as the dummy structures905described above with reference toFIGS.9A and9B, and the description is not repeated herein. In some embodiments, the dummy structures1103may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure901. Accordingly, the dummy structures1103may also be referred to as heat dissipation structures1103. Referring further toFIGS.11A and11B, the dummy structures1103and the first IC die structure901may have a rectangular shape in a top view. In some embodiments, a sidewall of each dummy structure1103is substantially coplanar with a respective sidewall of the first IC die structure901. In some embodiments, a first width W16of the dummy structures1103is less than a first width W11of the first IC die structure901and a second width W17of the dummy structures1103is less than a second width W12of the first IC die structure901. In some embodiments, the width W16may be between about 3 mm and about 9 mm. In some embodiments, the width W17may be between about 1 mm and about 4 mm. In some embodiments, a ratio W11/W16may be between about 1.6 and about 1.1. In some embodiments, a ratio W11/W17may be between about 5 and about 2.5. In some embodiments, a ratio W12/W16may be between about 2.3 and about 1.6. In some embodiments, a ratio W12/W17may be between about 7 and about 3.75. In some embodiments, a ratio W16/W17may be between about 3 and about 2.25. In some embodiments, the IC package1100may be formed using a method described below with reference toFIGS.23A-23F, and the detailed description of the IC package1000is provided at that time. FIGS.12A and12Billustrate top and cross-sectional views of an IC package1200in accordance with some embodiments.FIG.12Aillustrates a top view, whileFIG.12Billustrated a cross-sectional view along a line BB′ inFIG.12A. To highlight differences between the IC package1200and the IC package900(seeFIGS.9A and9B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1200comprises a first IC die structure901bonded to a second IC die structure1201. In some embodiments, the first IC die structure901is electrically connected to the second IC die structure1201. In some embodiments, the second IC die structure1201comprises a die stack113bonded to a base structure115. In some embodiments, the die stack113comprises IC dies1171-1174that are encapsulated in encapsulants1231-1234, respectively. In some embodiments, the second IC die structure1201further comprises an encapsulant907encapsulating the base structure115, the die stack113, and the encapsulants1231-1234. In some embodiments, the second IC die structure1201further comprises dummy structures1203, such that the die stack113is interposed between adjacent dummy structures1203. In some embodiments, the dummy structures1203may be formed using a similar materials and methods as the dummy structures905described above with reference toFIGS.9A and9B, and the description is not repeated herein. In some embodiments, the dummy structures1203may be configured as heat dissipation structures that transfer heat away from the IC die105of the first IC die structure901. Accordingly, the dummy structures1203may also be referred to as heat dissipation structures1203. Referring further toFIGS.12A and12B, the dummy structures1203and the first IC die structure901may have a rectangular shape in a top view. In some embodiments, two sidewalls of each dummy structure1203are substantially coplanar with respective two sidewall of the first IC die structure901. In some embodiments, the dummy structures1203(such as dummy structures12031and12032) disposed at opposite corners of the first IC die structure901have different dimensions. In some embodiments, a first width W19of the dummy structures12031is less than a first width W11of the first IC die structure901. In some embodiments, a first width W18of the dummy structures12032is less than a first width W11of the first IC die structure901. In some embodiments, the width W18is different from the width W19. In other embodiments, the width W18may be substantially equal to the width W19. In some embodiments, a second width of the dummy stacks12031may equal to a second width of the dummy stacks12032and may equal to a width W20. In some embodiments, the width W20is less than a second width W12of the second IC die structure901. In some embodiment, a sum of the widths W18and W19is less than the width W11. In some embodiments, the width W18may be between about 2 mm and about 4.5 mm. In some embodiments, the width W19may be between about 2 mm and about 4.5 mm. In some embodiments, the width W20may be between about 1 mm and about 4 mm. In some embodiments, a ratio W11/W18may be between about 2.5 and about 2. In some embodiments, a ratio W11/W19may be between about 2.5 and about 2. In some embodiments, a ratio W11/W20may be between about 5 and about 2.5. In some embodiments, a ratio W12/W18may be between about 3.5 and about 3. In some embodiments, a ratio W12/W19may be between about 3.5 and about 3. In some embodiments, a ratio W12/W20may be between about 7 and about 3.75. In some embodiments, a ratio W18/W19may be between about 1 and about 2.5. In some embodiments, a ratio W18/W20may be between about 2 and about 1. In some embodiments, a ratio W19/W20may be between about 2 and about 1. In some embodiments, the IC package1200may be formed using a method described below with reference toFIGS.23A-23F, and the detailed description of the IC package1200is provided at that time. FIGS.13A and13Billustrate top and cross-sectional views of an IC package1300in accordance with some embodiments.FIG.13Aillustrates a top view, whileFIG.13Billustrated a cross-sectional view along a line BB′ inFIG.13A. To highlight differences between the IC package1300and the IC package900(seeFIGS.9A and9B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1300comprises a first IC die structure1301bonded to a second IC die structure1303. In some embodiments, the first IC die structure1301is electrically connected to the second IC die structure1303. In some embodiment, the first IC die structure1301is similar to the first IC die structure901(seeFIGS.9A and9B) with the distinction that the first IC die structure1301and the first IC die structure901have different backside structures. In some embodiments, the first IC die structure1301may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the first IC die structure1301is provided at that time. In some embodiments, the second IC die structure1303is similar to the second IC die structure903(seeFIGS.9A and9B) with the distinction that the structure comprising the die stack113and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113is bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package1300may be formed using a method described below with reference toFIGS.24A-24C, and the detailed description of the IC package1300is provided at that time. FIGS.14A and14Billustrate top and cross-sectional views of an IC package1400in accordance with some embodiments.FIG.14Aillustrates a top view, whileFIG.14Billustrated a cross-sectional view along a line BB′ inFIG.14A. To highlight differences between the IC package1400and the IC package1000(seeFIGS.10A and10B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1400comprises a first IC die structure1301bonded to a second IC die structure1401. In some embodiments, the first IC die structure1301is electrically connected to the second IC die structure1401. In some embodiment, the first IC die structure1301is similar to the first IC die structure901(seeFIGS.10A and10B) with the distinction that the first IC die structure1301and the first IC die structure901have different backside structures. In some embodiments, the first IC die structure1301may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the first IC die structure1301is provided at that time. In some embodiments, the second IC die structure1401is similar to the second IC die structure1001(seeFIGS.10A and10B) with the distinction that the structure comprising the die stack113and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113is bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package1400may be formed using a method described below with reference toFIGS.24A-24C, and the detailed description of the IC package1400is provided at that time. FIGS.15A and15Billustrate top and cross-sectional views of an IC package1500in accordance with some embodiments.FIG.15Aillustrates a top view, whileFIG.15Billustrated a cross-sectional view along a line BB′ inFIG.15A. To highlight differences between the IC package1500and the IC package1100(seeFIGS.11A and11B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1500comprises a first IC die structure1301bonded to a second IC die structure1501. In some embodiments, the first IC die structure1301is electrically connected to the second IC die structure1501. In some embodiment, the first IC die structure1301is similar to the first IC die structure901(seeFIGS.11A and11B) with the distinction that the first IC die structure1301and the first IC die structure901have different backside structures. In some embodiments, the first IC die structure1301may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the first IC die structure1301is provided at that time. In some embodiments, the second IC die structure1501is similar to the second IC die structure1101(seeFIGS.11A and11B) with the distinction that the structure comprising the die stack113and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113is bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package1500may be formed using a method described below with reference toFIGS.24A-24C, and the detailed description of the IC package1500is provided at that time. FIGS.16A and16Billustrate top and cross-sectional views of an IC package1600in accordance with some embodiments.FIG.16Aillustrates a top view, whileFIG.16Billustrated a cross-sectional view along a line BB′ inFIG.16A. To highlight differences between the IC package1600and the IC package1200(seeFIGS.12A and12B), the common features of these packages are labeled by same numerical references and their description is not repeated herein. In some embodiments, the IC package1600comprises a first IC die structure1301bonded to a second IC die structure1601. In some embodiments, the first IC die structure1301is electrically connected to the second IC die structure1601. In some embodiment, the first IC die structure1301is similar to the first IC die structure901(seeFIGS.12A and12B) with the distinction that the first IC die structure1301and the first IC die structure901have different backside structures. In some embodiments, the first IC die structure1301may be formed using a method described below with reference toFIGS.19A-19G, and the detailed description of the first IC die structure1301is provided at that time. In some embodiments, the second IC die structure1601is similar to the second IC die structure1201(seeFIGS.12A and12B) with the distinction that the structure comprising the die stack113and the encapsulants1231-1234is vertically flipped, such that a backside of the IC die1174of the die stack113is bonded to the base structure115. Furthermore, a front side of the IC die1171of the die stack113is bonded to the backside of the IC die105. In some embodiments, the IC package1600may be formed using a method described below with reference toFIGS.24A-24C, and the detailed description of the IC package1600is provided at that time. FIGS.17A-17Cillustrate cross-sectional views of various processing steps during fabrication of integrated circuit dies (such as, for example, the IC dies105and1171illustrated inFIGS.1B-16B) in accordance with some embodiments. Referring toFIG.17A, a portion of a wafer1700having die regions1701separated by scribe lines1703(also referred to as dicing lines or dicing streets) is illustrated. As described below in greater detail, the wafer1700will be diced along the scribe lines1703to form individual integrated circuit dies (such as the IC dies1719illustrated inFIG.17C). In some embodiments, the wafer1700comprises a substrate1705, one or more active and/or passive devices (not shown) on the substrate1705, and an interconnect structure1707over the substrate1705and the one or more active and/or passive devices. In some embodiments, the substrate1705may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The substrate1705may also be in the form of silicon-on-insulator (SOI). The SOI substrate may comprise a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide and/or the like), which is formed on a silicon substrate. In addition, other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like. In some embodiments, the substrate1705may comprise through vias (TVs)1709that extend from a front surface of the substrate1705toward a backside surface of the substrate1705. In some embodiments, the TVs1709may be formed by forming openings in the substrate1705and filling the openings with suitable conductive materials. In some embodiments, the openings may be formed using suitable photolithography and etching methods. In some embodiments, the openings may be filled with copper, a copper alloy, silver, gold, tungsten, tantalum, aluminum, a combination thereof, or the like, using physical vapor deposition (PVD), atomic layer deposition (ALD), electro-chemical plating, electroless plating, or a combination thereof, the like. In some embodiments, a liner layer and/or an adhesive/barrier layer may be formed in the openings before filling the openings with suitable conductive materials. In some embodiments, a planarization process may be performed on the conductive material of the TVs1709, such that topmost surfaces of the TVs1709are substantially level or coplanar with the front surface of the substrate1705. The planarization process may comprise a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, the one or more active and/or passive devices may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and/or the like. The interconnect structure1707may comprise a plurality of dielectric layers1711(such an inter-layer dielectric (ILD)/inter-metal dielectric layers (IMDs)) and interconnects1713(such as conductive lines and vias) within the dielectric layers1711. The dielectric layers1711may be formed, for example, of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), FSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as a spin-on coating method, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), a combination thereof, or the like. In some embodiments, interconnects1713may be formed in the dielectric layers1711using, for example, a damascene process, a dual damascene process, a combination thereof, or the like. In some embodiments, interconnects1713may comprise copper, a copper alloy, silver, gold, tungsten, tantalum, aluminum, a combination thereof, or the like. In some embodiments, the interconnects1713may provide electrical connections between the one or more active and/or passive devices formed on the substrate1705. Referring further toFIG.17A, contact pads1715are formed over the interconnect structure1707. The contact pads1715may be electrically coupled to the one or more active and/or passive devices through the interconnects1713. In some embodiments, the contact pads1715may comprise a conductive material such as aluminum, copper, tungsten, silver, gold, a combination thereof, or the like. In some embodiments, a conductive material may be formed over the interconnect structure1707using, for example, PVD, ALD, electro-chemical plating, electroless plating, a combination thereof, or the like. Subsequently, the conductive material is patterned to form the contact pads1715. In some embodiments, the conductive material may be patterned using suitable photolithography and etching methods. Referring toFIG.17B, an insulating layer1717is formed over the interconnect structure1707and the contact pads1715. In some embodiments, the insulating layer1717may comprise one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like. In other embodiments, the insulating layer1717may comprise one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using a spin-on coating process, or the like. Such photo-patternable insulating materials may be patterned using similar photolithography methods as a photoresist material. In some embodiments, the insulating layer1717is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring toFIG.17C, the wafer1700is singulated along the scribe lines1703(seeFIG.17B) to form individual IC dies1719. In some embodiments, the wafer1700may be singulated into individual IC dies1719, for example, by sawing, laser ablation, etching, a combination thereof, or the like. FIGS.18A and18Billustrate cross-sectional views of various processing steps during fabrication of integrated circuit dies (such as, for example, the IC dies1172-1174illustrated inFIGS.1B-16B) in accordance with some embodiments.FIG.18Aillustrates a wafer1800after preforming various processing steps on the wafer1700illustrated inFIG.17Bin accordance with some embodiments. In some embodiments, an insulating layer1801is formed over the insulating layer1717. In some embodiments, the insulating layer1801may be formed using similar materials and methods as the insulating layer1717described above with reference toFIG.17B, and the description is not repeated herein. In some embodiments, the insulating layer1801is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, the insulating layer1801and the insulating layer1717may comprise a same material. In other embodiments, the insulating layer1801and the insulating layer1717may comprise different materials. Referring further toFIG.18A, bond pads1805and corresponding vias1803are formed in the insulating layers1717and1801. In some embodiments, the bond pads1805are formed in the insulating layer1801and the vias1803are formed in the insulating layer1717. In some embodiments, the bond pads1805and the vias1803may be formed using similar materials and methods as the interconnects1713described above with reference toFIG.17A, and the description is not repeated herein. In some embodiments, the bond pads1805and the insulating layer1801are planarized, such that topmost surfaces of the bond pads1805are substantially level or coplanar with a topmost surface of the insulating layer1801. In some embodiments, the vias1803are in direct electrical contact with the interconnects1713. In other embodiments, the vias1803may be in direct electrical contact with the contact pads1715and may be electrically connected to the interconnects1713through the contact pads1715. Referring toFIG.18B, the wafer1800is singulated along the scribe lines1703(seeFIG.18A) to form individual IC dies1807. In some embodiments, the wafer1800may be singulated into the individual IC dies1807, for example, by sawing, laser ablation, etching, a combination thereof, or the like. FIGS.19A-19Gillustrate cross-sectional views of various processing steps during fabrication of integrated circuit die structures (such as, for example, the IC die structures501and1301illustrated inFIGS.5B-8B and13B-16B, respectively) in accordance with some embodiments. Referring toFIG.19A, the IC dies105are bonded to a carrier1901to start forming a wafer-level die structure1900. In some embodiments, the carrier1901may comprise similar materials as the substrate1705described above with reference toFIG.17A, and the description is not repeated herein. In other embodiments, the carrier1901may comprise a suitable insulating material. In some embodiments, the IC dies105may be similar to the IC dies1719and may be formed using a method described above with reference toFIGS.17A-17C, with similar features of the IC dies1719and105being referred to with similar numerical references. Referring further toFIG.19A, an insulating layer1903is formed over the carrier1901. In some embodiments, the insulating layer1903may be formed using similar materials and methods as the insulating layer1717described above with reference toFIG.17B, and the description is not repeated herein. In some embodiments, the insulating layer1903is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, the IC dies105are bonded to the carrier1901by bonding the insulating layers1717of the IC dies105to the insulating layer1903. In some embodiments, the insulating layers1717may be bonded to the insulating layer1903using a direct bonding method, such a fusion bonding method. In some embodiments, surface treatment processes may be performed on the insulating layers1717and the insulating layer1903prior to bonding the insulating layers1717to the insulating layer1903. In other embodiments, the insulating layers1717may be bonded to the insulating layer1903using other suitable bonding methods or using an adhesive. In some embodiments, an annealing process may be performed after bonding the IC dies105to the carrier1901to strengthen the bond. Referring toFIG.19B, an encapsulant107is formed over and surrounding the IC dies105. In some embodiments, the encapsulant107may be formed using similar materials and methods as the insulating layer1717described above with reference toFIG.17B, and the description is not repeated herein. In other embodiments, the encapsulant107may comprise a molding compound, such as an epoxy, a resin, a moldable polymer, a combination thereof, or the like. The molding compound may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In other embodiments, the molding compound may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around and between the IC dies105. Referring toFIG.19C, the encapsulant107and the IC dies105are planaraized, such that backside surfaces105bof the IC dies105are substantially level or coplanar with a topmost surface of the encapsulant107. In some embodiments, the planarization process may comprise a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiment, the planarization process exposes the TVs1709of the IC dies105, such that exposed surfaces of the TVs1709are substantially level or coplanar with the backside surfaces105bof the IC dies105and the topmost surface of the encapsulant107. Referring toFIG.19D, the backside surfaces105bof the IC dies105are recessed below the topmost surface of the encapsulant107to form recesses1905. In some embodiments, the backside surfaces105bof the IC dies105may be recessed using a suitable etching process, such as a selective dry or wet etching process that is selective to the material of the substrate1705of the IC dies105. In some embodiments, sidewalls of the TVs1709of the IC dies105are exposed within the recesses1905. Referring toFIG.19E, insulating layers1907are formed in the recesses1905(seeFIG.19D). In some embodiments, the insulating layers1907may be formed using similar materials and methods as the insulating layer1717described above with reference toFIG.17B, and the description is not repeated herein. In some embodiments, an insulating material of the insulating layers1907is deposited in the recesses1905and over the encapsulant107. Subsequently, portions of the insulating material overfilling the recesses1905are removed to form insulating layers1907, such that topmost surfaces the insulating layer1907are substantially level or coplanar with the topmost surface of the encapsulant107. In some embodiments, the portions of the insulating material overfilling the recesses1905may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiment, the removal process exposes the TVs1709of the IC dies105, such that exposed surfaces of the TVs1709are substantially level or coplanar with the topmost surfaces of the insulating layers1907and the topmost surface of the encapsulant107. Referring toFIGS.19F and19G, the wafer-level die structure1900is singulated to form individual (chip-level or die-level) IC die structures1911, which are intermediate structures in forming the IC die structures501and1301(seeFIGS.5B-8B and13B-16B, respectively) in accordance with some embodiments. Referring first toFIG.19F, the encapsulant107, the insulating layer1903and the carrier1901are patterned to form recesses1909. The recesses1909are interposed between the adjacent IC dies105and partially extend into the carrier1901, such that the recesses1909partially singulate the carrier1901. In some embodiments, the patterning process for forming the recesses1909may comprise suitable photolithography and etching methods. Referring toFIG.19G, the carrier1901is thinned to remove un-singulated portions of the carrier1901, thereby fully singulating the carrier1901and forming the individual IC die structures1911. In some embodiments, the carrier1901may be thinned using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In other embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. FIGS.20A and20Billustrate cross-sectional views of various processing steps during fabrication of integrated circuit die structures (such as, for example, the IC die structures101and901illustrated inFIGS.1B-4B and9B-12B, respectively) in accordance with some embodiments.FIG.20Aillustrates a wafer-level die structure2000after preforming various processing steps on the wafer-level die structure1900illustrated inFIG.19E, in accordance with some embodiments. In some embodiments, an insulating layer2001is formed over the IC dies105and the encapsulant107. In some embodiments, the insulating layer2001may be formed using similar materials and methods as the insulating layer1717described above with reference toFIG.17B, and the description is not repeated herein. In some embodiments, the insulating layer2001and the insulating layer1907may comprise a same material. In other embodiments, the insulating layer2001and the insulating layer1907may comprise different materials. In some embodiments, bond pads2003are formed in the insulating layer2001in electrical contact with respective TVs1709of the IC dies105. In some embodiments, bond pads2003may be formed using similar materials and methods as the interconnects1713described above with reference toFIG.17A, and the description is not repeated herein. In some embodiments, the bond pads2003are planarized, such that topmost surfaces of the bond pads2003are substantially level or coplanar with the topmost surface of the insulating layer2001. In some embodiments, the planarization process may comprise a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring toFIG.20B, the wafer-level die structure2000is singulated to form individual (chip-level or die-level) IC die structures2005, which are intermediate structures in forming the IC die structures101and901(seeFIGS.1B-4B and9B-12B, respectively) in accordance with some embodiments. In some embodiments, the wafer-level die structure2000may be singulated using a method described above with reference toFIGS.19F and19G, and the description is not repeated herein. FIGS.21A-21Hillustrate top and cross-sectional views of various processing steps during fabrication of integrated circuit packages (such as, for example, the IC packages100-400illustrated inFIGS.1A and1B,2A and2B,3A and3B, and4A and4B, respectively) in accordance with some embodiments. Referring toFIG.21A, a method of forming a wafer-level die structure2100starts with forming an insulating layer2103over a carrier2101. In some embodiments, the carrier2101may be formed using similar materials and methods as the carrier1901described above with reference toFIG.19A, and the description is not repeated herein. In some embodiments, the insulating layer2103may be formed using similar materials and methods as the insulating layer1903described above with reference toFIG.19A, and the description is not repeated herein. In some embodiments, IC dies1171are bonded to the insulating layer2103. In some embodiments, the IC dies1171may be similar to the IC dies1719and may be formed using a method described above with reference toFIGS.17A-17C, with similar features of the IC dies1171and1719being referred to with similar numerical references. In some embodiments, the IC dies1171are bonded to the insulating layer2103by bonding the insulating layers1717of the IC dies1171to the insulating layer2103. In some embodiments, the insulating layers1717may be bonded to the insulating layer2103using a direct bonding method, such a fusion bonding method. In some embodiments, surface treatment processes may be performed on the insulating layers1717and the insulating layer2103prior to bonding the insulating layers1717to the insulating layer2103. In other embodiments, the insulating layers1717may be bonded to the insulating layer2103using other suitable bonding methods or using an adhesive. In some embodiments, an annealing process may be performed after bonding the IC dies1171to the carrier2101to strengthen the bond. In some embodiments, the insulating layers1717and the insulating layer2103may a same materials. In other embodiments, the insulating layers1717and the insulating layer2103may comprise different materials. Referring further toFIG.21A, dummy structures21051are bonded to the insulating layer2103, such that each IC die1171is interposed between adjacent dummy structures21051. In some embodiments, the dummy structures21051may comprise a same material as the substrate1705of the IC dies1171. In some embodiments, dummy structures21051may not comprise active and/or passive devices, and may not provide additional electrical functionality to the resulting IC packages. In some embodiments, each dummy structure21051may comprise an insulating layer21071on one side. In some embodiments, the insulating layers21071may be formed using similar materials and methods as the insulating layer1717described above with reference toFIG.17B, and description is not repeated herein. In some embodiments, the insulating layers21071and the insulating layer2103may comprise a same material. In other embodiments, the insulating layers21071and the insulating layer2103may comprise different materials. In some embodiments, the dummy structures21051are bonded to the insulating layer2103by bonding the insulating layers21071of the dummy structures21051to the insulating layer2103. In some embodiments, the insulating layers21071may be bonded to the insulating layer2103using a direct bonding method, such a fusion bonding method. In some embodiments, surface treatment processes may be performed on the insulating layers21071and the insulating layer2103prior to bonding the insulating layers21071to the insulating layer2103. In other embodiments, the insulating layers21071may be bonded to the insulating layer2103using other suitable bonding methods or using an adhesive. In some embodiments, an annealing process may be performed after bonding the dummy structures21051to the carrier2101to strengthen the bond. FIG.21Billustrates a top view of the wafer-level die structure2100illustrated inFIG.21Ain accordance with some embodiments. In some embodiments, the carrier2101is separated into die regions2113i(where i=1, . . . , N, with N being the total number of die regions) by scribe lines2109and2111. In some embodiments, the scribe lines2109are perpendicular to the scribe lines2111. In such embodiments, the die regions2113i(where i=1, . . . , N) have rectangular shapes in a top view. In other embodiments, the scribe lines2109and the scribe lines2111form angles different from 90 degrees. In such embodiments, the die regions2113i(where i=1, . . . , N) have shapes of a parallelogram in a top view. In some embodiments, the dummy structures21051have rectangular shapes in a top view. In some embodiments, the dummy structures21051overlap with respective scribe lines2111, such the dummy structures21051are shared between a subset of the die regions2113i(where i=1, . . . , N) separated by the respective scribe lines2111. In some embodiments, the dummy structures21051may form continuous structures extending along an entirety of the usable portion (such as the portion comprising the die regions2113i) of the carrier2101, such that each scribe line2111is overlapped by a respective single continuous dummy structure21051. As described below in greater detail, the wafer-level die structure2100is singulated along the scribe lines2109and2111to form individual packages. Such a singulation process also singulates the dummy structures21051and forms individual (chip-level or die-level) dummy structures for respective individual packages. In some embodiments, by forming the dummy structures21051that overlap with the scribe lines2111, a time for forming the individual IC packages may be reduced. For example, the time for forming the individual IC packages may be reduced by a time that would be required to place and bond individual (chip-level or die-level) dummy structures within each die region of the carrier2101before performing a singulation process. Accordingly, a wafer per hour (WPH) yield may be increased and production cost may be reduced during the production of IC packages. FIG.21Cillustrates a top view of the wafer-level die structure2100illustrated inFIG.21Ain accordance with alternative embodiments. The embodiment illustrated inFIG.21Cis similar to the embodiment illustrated inFIG.21B, with like elements being labeled with like numerical references, and the detailed description is not repeated herein. In the embedment illustrated inFIG.21C, the dummy structures21051do not form continuous structures extending along the entirety of the usable portion of the carrier2101. Instead, each scribe line2111is overlapped by a plurality of disconnected dummy structures21051of varying lengths. Referring toFIG.21D, the IC dies1171and the dummy structures21051are encapsulated in an encapsulant1231. Subsequently, insulating layers21151are formed over the IC dies1171, and insulating layers211′71are formed over the dummy structures21051. In some embodiments, topmost surfaces of the insulating layers21151and topmost surfaces of the insulating layers21171are substantially level or coplanar with a topmost surface of the encapsulant1231. In some embodiments, the encapsulant1231may be formed using similar materials and methods as the encapsulant107described above with reference toFIGS.19B and19C, and the description is not repeated herein. In some embodiments, the insulating layers21151and the insulating layers21171may be formed using similar materials and methods as the insulating layer1907described above with reference toFIGS.19D and19E, and the description is not repeated herein. In some embodiments, the insulating layers21151and the insulating layers211′71may comprise a same material. In other embodiments, the insulating layers21151and the insulating layers21171may comprise different materials. The IC dies1171with corresponding insulating layers21151, the dummy structures21051with corresponding insulating layers21071and21171, and the encapsulant1231form a tier1structure21191over the carrier2101. Referring toFIG.21E, the IC dies1172are bonded to the IC dies1171. In some embodiments, the IC dies1172may be similar to the IC dies1807and may be formed using a method described above with reference toFIGS.18A and18B, with similar features of the IC dies1172and the IC dies1807being referred to with similar numerical references. In some embodiments, the IC dies1172are bonded to the IC dies1171using a direct bonding method, such as a hybrid bonding method. In such embodiments, the TVs1709of the IC dies1172are direct bonded to the bond pads1805of the IC dies1172, and the insulating layers21151of IC dies1171are direct bonded to the insulating layers1801of the IC dies1172. In some embodiments, after bonding the IC dies1172to the IC dies1171, an annealing process may be performed to strengthen the bond between the IC dies1171and the IC dies1172. The bonds between the TVs1709of the IC dies1171and the bond pads1805of the IC dies1172provide electrical connections between the IC dies1171and the IC dies1172. In some embodiments, the TVs1709of the IC dies1171and the bond pads1805of the IC dies1172may comprise a same material. In other embodiments, the TVs1709of the IC dies1171and the bond pads1805of the IC dies1172may comprise different materials. In some embodiments, the insulating layers21151of IC dies1171and the insulating layers1801of the IC dies1172may comprise a same material. In other embodiments, the insulating layers21151of IC dies1171and the insulating layers1801of the IC dies1172may comprise different materials. In some embodiments, dummy structures21052are bonded to the dummy structures21051. In some embodiments, the dummy structures21052may be formed using similar materials and methods as the dummy structures21051described above with reference toFIG.21D, and the description is not repeated herein. In some embodiments, the dummy structures21052may be bonded to the dummy structures21051by bonding the insulating layers21072of the dummy structures21052to the insulating layers21171of the dummy structures21051. In some embodiments, the insulating layers21072may be bonded to the insulating layers21171using a direct bonding method, such a fusion bonding method. In some embodiments, surface treatment processes may be performed on the insulating layers21072and the insulating layers21171prior to bonding the insulating layers21072to the insulating layer21171. Subsequently, an annealing process may be performed to strengthen the bond between the dummy structures21052and the dummy structures21051. In some embodiments, the insulating layers21072and the insulating layer21171may comprise a same material. In other embodiments, the insulating layers21072and the insulating layer21171may comprise different materials. In some embodiments, the dummy structures21052may have same shapes in a top view as respective the dummy structures21051illustrated inFIGS.21B and21C, and the description is not repeated herein. Subsequently, the IC dies1172and the dummy structures21052are encapsulated in an encapsulant1232, insulating layers21152are formed over the IC dies1172, and insulating layers21172are formed over the dummy structures21052. In some embodiments, the encapsulant1232may be formed using similar materials and methods as the encapsulant1231described above with reference toFIG.21D, and the description is not repeated herein. In some embodiments, the insulating layers21152and insulating layers21172may be formed using similar materials and methods as the insulating layers21151and insulating layers211′71, respectively, described above with reference toFIG.21D, and the description is not repeated herein. In some embodiments, the insulating layers21152and insulating layers21172may comprise a same material. In other embodiments, the insulating layers21152and insulating layers21172may comprise different materials. The IC dies1172with corresponding insulating layers21152, the dummy structures21052with corresponding insulating layers21072and21172, and the encapsulant1232form a tier2structure21192over the tier1structure21191. Referring further toFIG.21E, a tier3structure21193comprising IC dies1173with corresponding insulating layers21153, the dummy structures21053with corresponding insulating layers21073and21173, and the encapsulant1233is formed over the tier2structure21192. In some embodiments, the IC dies1173may be similar to the IC dies1807and may be formed using a method described above with reference toFIGS.18A and18B, with similar features of the IC dies1173and the IC dies1807being referred to with similar numerical references. In some embodiments, the dummy structures21053may be formed using similar materials and methods as the dummy structures21051described above with reference toFIG.21D, and the description is not repeated herein. In some embodiments, the tier3structure21193may be formed using similar methods as the tier2structure21192described above, and the description is not repeated herein. Subsequently, a tier4structure21194comprising IC dies1174with corresponding insulating layers21154, the dummy structures21054with corresponding insulating layers21074and21174, and the encapsulant1234is formed over the tier3structure21193. In some embodiments, the IC dies1174may be similar to the IC dies1807and may be formed using a method described above with reference toFIGS.18A and18B, with similar features of the IC dies1174and the IC dies1807being referred to with similar numerical references. In some embodiments, the dummy structures21054may be formed using similar materials and methods as the dummy dies21051described above with reference toFIG.21D, and the description is not repeated herein. In some embodiments, the tier4structure21194may be formed using similar methods as the tier2structure21192described above, and the description is not repeated herein. In some embodiments, the dummy structures21053and21054may have same shapes in a top view as respective the dummy structures21051illustrated inFIGS.21B and21C, and the description is not repeated herein. The stacks of dummy structures21051-21054form may also be referred to as the stacked dummy structures2121and the stacks of IC dies1171-1174may also be referred to as the die stacks113. Referring toFIG.21F, the IC die structures2005(seeFIG.20B) are bonded to the IC dies1174of the die stacks113. In some embodiments, IC die structures2005are bonded to the IC dies1174using a direct bonding method, such as a hybrid bonding method. In such embodiments, the TVs1709of the IC dies1174are direct bonded to the bond pads2003of the IC die structures2005, and the insulating layers21154of IC dies1174are direct bonded to the insulating layers2001of the IC die structures2005. Furthermore, the insulating layers2001of the IC die structures2005may be direct bonded to the insulating layers21174formed over the dummy structures21054. In some embodiments, after bonding the IC die structures2005to the IC dies1174and the dummy structures21054, an annealing process may be performed to strengthen the bond. The bonds between the TVs1709of the IC dies1174and the bond pads2003of the IC die structures2005provide electrical connections between the IC die structures2005and IC dies1174. In some embodiments, the TVs1709of the IC dies1174and the bond pads2003of the IC die structures2005may comprise a same material. In other embodiments, the TVs1709of the IC dies1174and the bond pads2003of the IC die structures2005may comprise different materials. In some embodiments, the insulating layers2001of the IC die structures2005and the insulating layers21154of the IC dies1174may comprise a same material. In other embodiments, the insulating layers2001of the IC die structures2005and the insulating layers21154of the IC dies1174may comprise different materials. In some embodiments, the insulating layers2001and the insulating layers21174may comprise a same material. In other embodiments, the insulating layers2001and the insulating layers21174may comprise different materials. Referring toFIG.21G, an encapsulant109is formed over and between the IC die structures2005. In some embodiments, the encapsulant109may be formed using similar materials and methods as the encapsulant107described above with reference toFIG.19B, and the description is not repeated herein. In some embodiments, the carriers1901and the insulating layers1903(seeFIG.21F) of the IC die structures2005and portions of the encapsulant109are removed to expose the insulating layers1717of the IC dies105, such that exposed surfaces of the insulating layers1717are substantially level or coplanar with a topmost surface of the encapsulant109. In some embodiments, the carriers1901, the insulating layers1903and portions of the encapsulant109may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring toFIG.21H, connectors111are formed over and electrically coupled to the respective contact pads1715of the IC dies105. In some embodiments, each of the connectors111may comprise a conductive pillar bump2123and a solder element2127over the conductive pillar bump2123. In some embodiments, the conductive pillar bumps2123may comprise a conductive material such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. In some embodiments, the solder elements2127may comprise lead-based solders such as PbSn compositions, lead-free solders including InSb, tin, silver, and copper (“SAC”) compositions, and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solders, SAC solders of varying compositions may be used, such as SAC105(Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC305, and SAC405, as examples. Lead-free solders also include SnCu compounds, without the use of silver (Ag), and SnAg compounds, without the use of copper (Cu). In some embodiments, a method of forming the conductive pillar bumps2123may comprise forming openings in the insulating layers1717to expose respective contact pads1715, forming a conductive seed layer over the insulating layers1717and in the openings of the insulating layers1717, forming a sacrificial material (such as a photoresist material) over the conductive seed layer, patterning the sacrificial material to form openings in the sacrificial layer such that the openings of the sacrificial layer are aligned with respective openings of the insulating layers1717and are forming combined openings, depositing a conductive material in the combined openings using an electro-chemical plating process, an electroless plating process, ALD, PVD, a combination thereof, or the like to form the conductive pillar bumps2123, removing the sacrificial layer, and removing exposed portions of the conductive seed layer. In some embodiments, before removing the sacrificial layer, a solder material is formed over the conductive material of the conductive pillar bumps2123in the combined openings using evaporation, an electro-chemical plating process, an electroless plating process, printing, solder transfer, a combination thereof, or the like to form the solder elements2127. In other embodiments, the connectors111may be solder balls, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. In some embodiments where the connectors111comprise solder materials, a reflow process may be performed in order to shape the solder material into the desired bump shapes. Referring further toFIG.21H, after forming the connectors111, the wafer-level die structure2100is singulated along the scribe lines2109and2111(seeFIGS.21B and21C) into individual IC packages2125, such that each IC packages2125comprises the IC die105with the respective die stack113and portions of the stacked dummy structures2121. In some embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. In some embodiments, the IC package2125corresponding to the die region21131(seeFIGS.21B and21C) forms the IC package200(seeFIGS.2A and2B). In some embodiments, the IC package2125corresponding to the die region21132(seeFIGS.21B and21C) forms the IC package100(seeFIGS.1A and1B). In some embodiments, the IC package2125corresponding to the die region21133(seeFIG.21C) forms the IC package400(seeFIGS.4A and4B). In some embodiments, the IC package2125corresponding to the die region21134(seeFIG.21C) forms the IC package300(seeFIGS.3A and3B). FIGS.22A-22Dillustrate cross-sectional views of various processing steps during fabrication of integrated circuit packages (such as, for example, the IC packages500-800illustrated inFIGS.5A and5B,6A and6B,7A and7B, and8A and8B, respectively) in accordance with some embodiments. To highlight differences between the embodiment illustrated inFIGS.22A-22Dand the embodiment illustrated inFIGS.21A-21H, the common features of these embodiments are labeled by same numerical references. Furthermore, the detailed descriptions of the common features (described above with reference toFIGS.21A-21H) are not repeated herein. Referring toFIG.22A, the wafer-level die structure2100illustrated inFIG.21Eis bonded to a carrier2201before forming the insulating layers21154and21174to start forming a wafer-level die structure2200. In some embodiments, an insulating layer2203is formed over the carrier2201and the wafer-level die structure2100is bonded to the insulating layer2203using a direct bonding method, such as a fusion bonding method, for example. In other embodiments, the insulating layer2203may be omitted and the wafer-level die structure2100may be bonded to the carrier2201using a direct bonding method, such as a fusion bonding method, for example. In some embodiments, the carrier2201may be formed using similar materials and methods as the carrier2101described above with reference toFIG.21A, and the description is not repeated herein. In some embodiments, the insulating layer2203may be formed using similar materials and methods as the insulating layer2103described above with reference toFIG.21A, and the description is not repeated herein. Referring toFIG.22B, the carrier2101and the insulating layer2103are removed to expose the insulating layers1717of the IC dies1171. In some embodiments, the carrier2101and the insulating layer2103may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, an insulating layer2205is formed over the die stacks113and the stacked dummy structures2121, and bond pads2209and corresponding vias2207are formed in the insulating layers1717and2205. In some embodiments, the bond pads2209are formed in the insulating layer2205and the vias2207are formed in the insulating layers1717. In some embodiments, the insulating layer2205may be formed using similar materials and methods as the insulating layer1801described above with reference toFIG.18A, and the description is not repeated herein. In some embodiments, the bond pads2209and the vias2207may be formed using similar materials and methods as the bond pads1805and the vias1803, respectively, described above with reference toFIG.18A, and the description is not repeated herein. In some embodiments, the vias2207are in direct electrical contact with the respective interconnects1713of the IC dies1171. In other embodiments, the vias2207may be in direct electrical contact with the respective contact pads1715of the IC dies1171and may be electrically connected to the respective interconnects1713of the IC dies1171through the respective contact pads1715of the IC dies1171. Referring toFIG.22C, the IC die structures1911(seeFIG.19G) are bonded to the IC dies1171of the die stacks113. In some embodiments, IC die structures1911are bonded to the respective IC dies1171using a direct bonding method, such as a hybrid bonding method. In such embodiments, the bond pads2209are direct bonded to respective TVs1709of the IC dies105of the IC die structures1911, and the insulating layer2205is direct bonded to the insulating layers1907of the IC dies105of the IC die structures1911. In some embodiments, after bonding the IC die structures1911to the respective die stacks113, an annealing process may be performed to strengthen the bond. The bonds between the TVs1709of the IC dies105and the bond pads2009provide electrical connection between the IC die structures1911and the die stacks113. In some embodiments, the TVs1709of the IC dies105and the bond pads2209may comprise a same material. In other embodiments, the TVs1709of the IC dies105and the bond pads2209may comprise different materials. In some embodiments, the insulating layer2205and the insulating layers1907of the IC die structures1911may comprise a same material. In other embodiments, the insulating layer2205and the insulating layers1907of the IC die structures1911may comprise different materials. Referring toFIG.22D, an encapsulant109is formed over and between the IC die structures1911. In some embodiments, the encapsulant109may be formed using similar materials and methods as the encapsulant107described above with reference toFIG.19B, and the description is not repeated herein. In some embodiments, the carriers1901and the insulating layers1903(seeFIG.22C) of the IC die structures1911and portions of the encapsulant109are removed to expose the insulating layers1717of the IC dies105, such that exposed surfaces of the insulating layers1717are substantially level or coplanar with a topmost surface of the encapsulant109. In some embodiments, the carriers1901, the insulating layers1903and portions of the encapsulant109may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, after removing the carriers1901and the insulating layers1903, connectors111are formed over and electrically coupled to the respective contact pads1715of the IC dies105as described above with reference toFIG.21H, and the description is not repeated herein. In some embodiments, after forming the connectors111, the wafer-level die structure2200is singulated along the scribe lines2109and2111(seeFIGS.21B and21C) into individual IC packages2211, such that each IC package2211comprises the IC die105with the respective die stack113and portions of the stacked dummy structures2121. In some embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. In some embodiments, the IC package2211corresponding to the die region21131(seeFIGS.21B and21C) forms the IC package600(seeFIGS.6A and6B). In some embodiments, the IC package2211corresponding to the die region21132(seeFIGS.21B and21C) forms the IC package500(seeFIGS.5A and5B). In some embodiments, the IC package2211corresponding to the die region21133(seeFIG.21C) forms the IC package800(seeFIGS.8A and8B). In some embodiments, the IC package2211corresponding to the die region21134(seeFIG.21C) forms the IC package700(seeFIGS.7A and7B). FIGS.23A-23Fillustrate top and cross-sectional views of various processing steps during fabrication of integrated circuit packages (such as, for example, the IC packages900-1200illustrated inFIGS.9A and9B,10A and10B,11A and11B, and12A and12B, respectively) in accordance with some embodiments. To highlight differences between the embodiment illustrated inFIGS.23A-23Fand the embodiment illustrated inFIGS.21A-21H, the common features of these embodiments are labeled by same numerical references. Furthermore, the detailed descriptions of the common features (described above with reference toFIGS.21A-21H) are not repeated herein. In the embodiment illustrated inFIGS.21A-21H, the IC dies105are bonded to the respective die stacks113, such that the die stacks113are parts of the un-singulated wafer-level die structure2100(see, for example,FIG.21F), while the IC dies105are parts of the singulated IC die structures2005(see, for example,FIG.21F). As described below in greater detail, in the embodiment illustrated inFIGS.23A-23F, the IC dies105are bonded to the die stacks113, such that the die stacks113are parts of the singulated die structures (see, for example,FIG.23B), while the IC dies105are parts of the un-singulated wafer-level die structure (see, for example,FIG.23B). Referring toFIG.23A, a wafer-level die structure2300is illustrated. In some embodiments, the wafer-level die structure2300is similar to the wafer-level die structure2100illustrated inFIG.21E, with like features labeled with like numerical references and with the distinction that the stacked dummy structures2121have been omitted. In some embodiments, the wafer-level die structure2300may be formed as described above with reference toFIGS.21A-21E, without forming the stacked dummy structures2121, and the description is not repeated herein. In some embodiments, the wafer-level die structure2300is singulated into individual (chip-level or die-level) IC die structures2301. In some embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. Referring toFIG.23B, in some embodiments, the IC die structures2301are bonded to respective IC dies105, while the IC dies105are still part of the un-singulated wafer-level die structure2000(seeFIG.20A) to start forming a wafer-level die structure2307. In some embodiments, the IC die structures2301are bonded to respective IC dies105as described above with reference toFIG.21F, and the description is not repeated herein. In some embodiments, dummy structures2303are bonded to the insulating layer2001of the wafer-level die structure2000, such that each IC die structure2301is interposed between adjacent dummy structures2303. In some embodiments, the dummy structures2303may be formed using similar materials and methods as the dummy structures21051described above with reference toFIG.21A, and the description is not repeated herein. In some embodiments, each dummy structure2303may comprise an insulating layer2305on one side. In some embodiments, the insulating layers2305may be formed using similar materials and methods as the insulating layers21071described above with reference toFIG.21A, and description is not repeated herein. In some embodiments, the insulating layers2305and the insulating layer2001may comprise a same material. In other embodiments, the insulating layers2305and the insulating layer2001may comprise different materials. In some embodiments, the dummy structures2303may be bonded to the insulating layer2001by bonding the insulating layers2305of the dummy structures2303to the insulating layer2001. In some embodiments, the insulating layers2305may be bonded to the insulating layer2001using a direct bonding method, such a fusion bonding method. In some embodiments, surface treatment processes may be performed on the insulating layers2305and the insulating layer2001prior to bonding the insulating layers2305to the insulating layer2001. Subsequently, an annealing process may be performed to strengthen the bond between the dummy structures2303and the wafer-level die structure2000. FIG.23Cillustrates a top view of the wafer-level die structure2307illustrated inFIG.23Bin accordance with some embodiments. In some embodiments, the wafer-level die structure2000is separated into die regions2313, (where i=1, . . . , N, with N being the total number of die regions) by scribe lines2309and2311. In some embodiments, the scribe lines2309are perpendicular to the scribe lines2311. In such embodiments, the die regions2313, (where i=1, . . . , N) have rectangular shapes in a top view. In other embodiments, the scribe lines2309and the scribe lines2311may form angles different from 90 degrees. In such embodiments, the die regions2313i(where i=1, . . . , N) have shapes of a parallelogram in a top view. In some embodiments, the dummy structures2303have rectangular shapes in a top view. In some embodiments, the dummy structures2303overlap with respective scribe lines2311, such that the dummy structures2303are shared between a subset of the die regions2113i(where i=1, . . . , N) separated by the respective scribe lines2311. In some embodiments, the dummy structures2303may form continuous structures extending along an entirety of the usable portion (such as the portion comprising the die regions2113i) of the wafer-level die structure2000, such that each scribe line2311is overlapped by a respective single continuous dummy structure2303. As described below in greater detail, the wafer-level die structure2307is singulated along the scribe lines2309and2311to form individual IC packages. Such a singulation process also singulates the dummy structures2303and forms individual (chip-level or die-level) dummy structures for respective individual IC packages. In some embodiments, by forming the dummy structures2303that overlap with the scribe lines2311, a time for forming the individual IC packages may be reduced. For example, the time for forming the individual IC packages may be reduced by a time that would be required to place and bond individual (chip-level or die-level) dummy structures within each die region of the wafer-level die structure2000before the singulation process. Accordingly, a wafer per hour (WPH) yield may be increased and production cost may be reduced during the production of IC packages. FIG.23Dillustrates a top view of the wafer-level die structure2307illustrated inFIG.23Bin accordance with alternative embodiments. The embodiment illustrated inFIG.23Dis similar to the embodiment illustrated inFIG.23C, with like elements being labeled with like numerical references, and the detailed description is not repeated herein. In the embedment illustrated inFIG.23D, the dummy structures2303do not form continuous structures extending along the entirety of the usable portion of the wafer-level die structure2000. Instead, each scribe line2311is overlapped by a plurality of disconnected dummy structures2303of varying lengths. Referring toFIG.23E, an encapsulant907is formed over and surrounding the IC die structures2301and the dummy structures2303. In some embodiments, the encapsulant907may be formed using similar materials methods as the encapsulant107described above with reference toFIG.19B, and the description is not repeated herein. Subsequently, the encapsulant907, the IC die structures2301and the dummy structures2303are planarized, such that topmost surfaces of the IC die structures2301are substantially level or coplanar with topmost surfaces of the dummy structures2303and a topmost surface of the encapsulant907. In some embodiments, the planarization process may comprise a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring toFIG.23F, in some embodiments, the carrier1901and the insulating layer1903(seeFIG.23E) are removed from the wafer-level die structure2000to expose the insulating layers1717of the IC dies105and the encapsulant107, such that exposed surfaces of the insulating layers1717are substantially level or coplanar with the exposed surface of the encapsulant107. In some embodiments, the carrier1901and the insulating layer1903may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring further toFIG.23F, connectors111are formed over and electrically coupled to the respective contact pads1715of the IC dies105as described above with reference toFIG.21H, and the description is not repeated herein. After forming the connectors111, the wafer-level die structure2307is singulated along the scribe lines2309and2311(seeFIGS.23C and23D) into individual IC packages2315, such that each IC package2315comprises the IC die105with the respective die stack113and portions of the respective dummy structures2303. In some embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. In some embodiments, the IC package2315corresponding to the die region23131(seeFIGS.23C and23D) forms the IC package1000(seeFIGS.10A and10B). In some embodiments, the IC package2315corresponding to the die region23132(seeFIGS.23C and23D) forms the IC package900(seeFIGS.9A and9B). In some embodiments, the IC package2315corresponding to the die region23133(seeFIG.23D) forms the IC package1200(seeFIGS.12A and12B). In some embodiments, the IC package2315corresponding to the die region23134(seeFIG.23D) forms the IC package1100(seeFIGS.11A and11B). FIGS.24A-24Cillustrate cross-sectional views of various processing steps during fabrication of integrated circuit packages (such as, for example, the IC packages1300-1600illustrated inFIGS.13A and13B,14A and14B,15A and15B, and16A and16B, respectively) in accordance with some embodiments. To highlight differences between the embodiment illustrated inFIGS.24A-24Cand the embodiment illustrated inFIGS.23A-23F, the common features of these embodiments are labeled by same numerical references. Furthermore, the detailed descriptions of the common features (described above with reference toFIGS.23A-23F) are not repeated herein. Referring toFIG.24A, a wafer-level die structure2400is illustrated. In some embodiments, the wafer-level die structure2400is similar to the wafer-level die structure2200illustrated inFIG.22B, with like features labeled with like numerical references and with the distinction that the stacked dummy structures2121have been omitted. In some embodiments, the wafer-level die structure2400may be formed as described above with reference toFIGS.22A and22B, without forming the stacked dummy structures2121, and the description is not repeated herein. In some embodiments, the wafer-level die structure2400is singulated into individual (chip-level or die-level) IC die structures2401. In some embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. Referring toFIG.24B, in some embodiments, the IC die structures2401are bonded to respective IC dies105, while the IC dies105are still part of the un-singulated wafer-level die structure1900(seeFIG.19E) to start forming a wafer-level die structure2403. In some embodiments, the IC die structures2401are bonded to respective IC dies105of the wafer-level die structure1900as described above with reference toFIG.22C, and the description is not repeated herein. In some embodiments, dummy structures2303are bonded to the wafer-level die structure1900such that each IC die structure2401is interposed between adjacent dummy structures2303. In some embodiments, the dummy structures2303may be bonded to the wafer-level die structure1900by bonding the insulating layers2305of the dummy structures2303to the wafer-level die structure1900. In some embodiments, the insulating layers2305may be bonded to the wafer-level die structure1900using a direct bonding method, such a fusion bonding method. Subsequently, an annealing process may be performed to strengthen the bond between the dummy structures2303and the wafer-level die structure1900. Referring further toFIG.24B, an encapsulant907is formed over and surrounding the IC die structures2401and the dummy structures2303. Subsequently, the encapsulant907, the IC die structures2401and the dummy structures2303are planarized, such that topmost surfaces of the IC die structures2401are substantially level or coplanar with topmost surfaces of the dummy structures2303and a topmost surface of the encapsulant907. In some embodiments, the planarization process may comprise a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring toFIG.24C, the carrier1901and the insulating layer1903(seeFIG.24B) of the wafer-level die structure1900are removed to expose the insulating layers1717of the IC dies105and the encapsulant107, such that exposed surfaces of the insulating layers1717are substantially level or coplanar with the exposed surface of the encapsulant107. In some embodiments, the carrier1901and the insulating layer1903may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. Referring to further toFIG.24C, connectors111are formed over and electrically coupled to the respective contact pads1715of the IC dies105as described above with reference toFIG.21H, and the description is not repeated herein. After forming the connectors111, the wafer-level die structure2403is singulated along the scribe lines2309and2311(seeFIGS.23C and23D) into individual IC packages2405, such that each IC package2405comprises the IC die105with the respective die stack113and portions of the respective dummy structures2303. In some embodiments, the singulation process may comprise sawing, laser ablation, etching, a combination thereof, or the like. In some embodiments, the IC package2405corresponding to the die region23131(seeFIGS.23C and23D) forms the IC package1400(seeFIGS.14A and14B). In some embodiments, the IC package2405corresponding to the die region23132(seeFIGS.23C and23D) forms the IC package1300(seeFIGS.13A and13B). In some embodiments, the IC package2405corresponding to the die region23133(seeFIG.23D) forms the IC package1600(seeFIGS.16A and16B). In some embodiments, the IC package2405corresponding to the die region23134(seeFIG.23D) forms the IC package1500(seeFIGS.15A and15B). FIG.25is a flow diagram illustrating a method2500of forming of integrated circuit packages (such as, for example, IC packages100-800illustrated inFIGS.1A and1B,2A and2B,3A and3B,4A and4B,5A and5B,6A and6B,7A and7B,8A and8B, respectively) in accordance with some embodiments. The method starts with step2501, where a first die structure (such as, for example, the IC die structures103inFIGS.1A and1B) is formed as described above with reference toFIGS.21A-21E. In step2521a second die structure (such as, for example, the IC die structures101inFIGS.1A and1B) is formed as described above with reference toFIGS.20A and20B. In step2523, the first die structure is bonded to the second die structure as described above with reference toFIG.21F. A method of forming the first die structure starts with step2503, where a first IC die (such as, for example, the IC die1171illustrated inFIG.21A) is bonded to a carrier (such as, for example, the carrier2101illustrated inFIG.21A) as described above with reference toFIG.21A. In step2505, a first dummy structure (such as, for example, the dummy structure21051illustrated inFIG.21A) is bonded to the carrier as described above with reference toFIG.21A. In step2507, a first encapsulant (such as, for example, the encapsulant1231illustrated inFIG.21D) is formed surrounding the first IC die and the first dummy structure as described above with reference toFIG.21D. In step2509, a second IC die (such as, for example, the IC die1172illustrated inFIG.21E) is bonded to the first IC die as described above with reference toFIG.21E. In step2511, a second dummy structure (such as, for example, the dummy structure21052illustrated inFIG.21E) is bonded to the first dummy structure as described above with reference toFIG.21E. In step2513, a second encapsulant (such as, for example, the encapsulant1232illustrated inFIG.21E) is formed surrounding the second IC die and the second dummy structure as described above with reference toFIG.21E. In some embodiments, the stacking process may continue until the desired number of IC dies and the desired number of dummy structures are bonded to the carrier. In step2515, a topmost IC die (such as, for example, the IC die1174illustrated inFIG.21E) is bonded to a previous IC die (such as, for example, the IC die1173illustrated inFIG.21E) as described above with reference toFIG.21E. In step2517, a topmost dummy structure (such as, for example, the dummy die21054illustrated inFIG.21E) is bonded to a previous dummy structure (such as, for example, the dummy structure21053illustrated inFIG.21E) as described above with reference toFIG.21E. In step2519, a topmost encapsulant (such as, for example, the encapsulant1234illustrated inFIG.21E) is formed surrounding the topmost die IC die and the topmost dummy structure as described above with reference toFIG.21E. FIG.26is a flow diagram illustrating a method2600of forming of integrated circuit packages (such as, for example, the IC package900-1600illustrated inFIGS.9A and9B,10A and10B,11A and11B,12A and12B,13A and13B,14A and14B,15A and15B,16A and16B, respectively) in accordance with some embodiments. The method starts with step2601, where a first die structure (such as, for example, the IC die structure2301illustrated inFIG.23A) is formed as described above with reference toFIG.23A. In step2615, a second die structure (such as, for example, the wafer-level die structure2000illustrated inFIG.23B) is formed as described above with reference toFIGS.20A and20B. In step2617, the first die structure is bonded to the second die structure as described above with reference toFIG.23B. In step2619, a dummy structure (such as, for example, the dummy structure2303illustrated inFIG.23B) is bonded to the second die structure as described above with reference toFIG.23B. In step2621, a first encapsulant (such as, for example, the encapsulant907illustrated inFIG.23E) is formed surrounding the first die structure and the dummy structure as described above with reference toFIG.23E. A method of forming the first die structure starts with step2603, where a first IC die (such as, for example, the IC die1171illustrated inFIG.23A) is bonded to a carrier (such as, for example, the carrier2101illustrated inFIG.23A) as described above with reference toFIG.23A. In step2605, a second encapsulant (such as, for example, the encapsulant1231illustrated inFIG.23A) is formed surrounding the first IC die as described above with reference toFIG.23A. In step2607, a second IC die (such as, for example, the IC die1172illustrated inFIG.23A) is bonded to the first IC die as described above with reference toFIG.23A. In step2609, a third encapsulant (such as, for example, the encapsulant1232illustrated inFIG.23A) is formed surrounding the second IC die as described above with reference toFIG.23A. In some embodiments, the stacking process may continue until the desired number of IC dies is bonded to the carrier. In step2611, a topmost IC die (such as, for example, the IC die1174illustrated inFIG.23A) is bonded to a previous IC die (such as, for example, the IC die1173illustrated inFIG.23A) as described above with reference toFIG.23A. In step2613, a topmost encapsulant (such as, for example, the encapsulant1234illustrated inFIG.23A) is formed surrounding the topmost die IC die as described above with reference toFIG.23A. In accordance with an embodiment, a method includes: forming a first die structure, the first die structure including a first die stack and a stacked dummy structure bonded to a carrier; forming a second die structure, the second die structure including a first integrated circuit die; bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the first die stack to the first integrated circuit die, the topmost integrated circuit die of the first die stack being a farthest integrated circuit die of the die first stack from the carrier; and performing a singulation process on the first die structure to form a plurality of individual die structures, where the singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures. In an embodiment, forming the first die structure includes: bonding a front side of a second integrated circuit die to the carrier; bonding a first dummy structure to the carrier adjacent the second integrated circuit die; encapsulating the second integrated circuit die and the first dummy structure in a first encapsulant; bonding a front side of a third integrated circuit die to a backside of the second integrated circuit die, the backside of the second integrated circuit die being opposite the front side of the second integrated circuit die; bonding a second dummy structure to the first dummy structure; and encapsulating the third integrated circuit die and the second dummy structure in a second encapsulant. In an embodiment, the front side of the second integrated circuit die is bonded to the carrier using a fusion bonding method. In an embodiment, the front side of the third integrated circuit die is bonded to the backside of the second integrated circuit die using a hybrid bonding method. In an embodiment, the second dummy structure is bonded to the first dummy structure using a fusion bonding method. In an embodiment, the topmost integrated circuit die of the first die stack is bonded to the first integrated circuit die using a hybrid bonding method. In an embodiment, the stacked dummy structure is configured as a heat dissipation structure. In an embodiment, the first die structure further includes a second die stack bonded to the carrier, and the stacked dummy structure is disposed over a scribe line of the carrier between the first die stack and the second die stack. In accordance with another embodiment, a method includes: forming a first die structure, the first die structure including a die stack bonded to a carrier; forming a second die structure, the second die structure including a first integrated circuit die; bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die, the topmost integrated circuit die of the die stack being a farthest integrated circuit die of the die stack from the carrier; bonding a first dummy structure to the second die structure adjacent the first die structure; encapsulating the first die structure in a first encapsulant; and performing a singulation process on the second die structure to form a plurality of individual die structures, where the singulation process singulates the first dummy structure into a plurality of individual dummy structures. In an embodiment, forming the first die structure includes: bonding a front side of a second integrated circuit die to the carrier; encapsulating the second integrated circuit die in a second encapsulant; bonding a front side of a third integrated circuit die to a backside of the second integrated circuit die, the backside of the second integrated circuit die being opposite the front side of the second integrated circuit die; and encapsulating the third integrated circuit die in a third encapsulant. In an embodiment, the topmost integrated circuit die of the die stack is bonded to the first integrated circuit die using a hybrid bonding method. In an embodiment, the first dummy structure is bonded to the second die structure using a fusion bonding method. In an embodiment, forming the second die structure includes encapsulating the first integrated circuit die in a second encapsulant. In an embodiment, the first dummy structure is configured as a heat dissipation structure. In an embodiment, the method further includes bonding a second dummy structure to the second die structure, the first die structure being interposed between the first dummy structure and the second dummy structure. In accordance with yet another embodiment, a semiconductor structure includes: a die stack bonded to a base structure, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the base structure; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a first side of the first integrated circuit die being in physical contact with a second side of the second integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack, a sidewall of the heat dissipation structure being substantially coplanar with a sidewall of the die structure; and an encapsulant extending along sidewalls of the die stack. In an embodiment, the heat dissipation structure includes a stack of dummy structures. In an embodiment, the sidewall of the heat dissipation structure is free from the encapsulant. In an embodiment, a topmost surface of the base structure is substantially level with a topmost surface of the heat dissipation structure, the topmost surface of the base structure being a farthest surface of the base structure from the die structure, the topmost surface of the heat dissipation structure being a farthest surface of the heat dissipation structure from the die structure. In an embodiment, a topmost surface of the heat dissipation structure is substantially level with a topmost surface of the encapsulant, the topmost surface of the heat dissipation structure being a farthest surface of the heat dissipation structure from the die structure, the topmost surface of the encapsulant being a farthest surface of the encapsulant from the die structure. In accordance with yet another embodiment, a method includes: forming a wafer-level die structure, the wafer-level die structure including a plurality of integrated circuit dies encapsulated in a first encapsulant; forming a first die structure, the first die structure including a plurality of tiers over a carrier, each of the plurality of tiers including an encapsulated integrated circuit die; bonding the first die structure to the wafer-level die structure, the plurality of tiers being interposed between the wafer-level die structure and the carrier; bonding a dummy structure to the wafer-level die structure adjacent the first die structure; encapsulating the first die structure and the dummy structure in a second encapsulant; and performing a singulation process on the wafer-level die structure to form a plurality of individual die structures, wherein the singulation process separates the dummy structure into a plurality of individual dummy structures. In accordance with yet another embodiment, a semiconductor structure includes: a die stack bonded to a base structure, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the base structure; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a first side of the first integrated circuit die being in physical contact with a second side of the second integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack, a sidewall of the heat dissipation structure being substantially coplanar with a sidewall of the die structure; and a first encapsulant extending along sidewalls of the die stack. In accordance with yet another embodiment, a semiconductor structure includes: a die structure including a first integrated circuit die; a die stack bonded to the die structure, the die stack including a second integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack, a top surface of the heat dissipation structure being substantially level with a top surface of the die stack; a base structure bonded to the die stack and the heat dissipation structure, the second integrated circuit die being interposed between the first integrated circuit die and the base structure; and a first encapsulant interposed between the die stack and the heat dissipation structure. In accordance with yet another embodiment, a semiconductor structure includes: a die structure including a first integrated circuit die encapsulated in a first encapsulant; a die stack attached to the die structure; a heat dissipation structure attached to the die structure at an interface between the first integrated circuit die and the first encapsulant, a sidewall of the heat dissipation structure being substantially coplanar with a sidewall of the first encapsulant; a base structure attached to the die stack and the heat dissipation structure, the die stack being interposed between the first integrated circuit die and the base structure; and a second encapsulant interposed between the die stack and the heat dissipation structure, a top surface of the second encapsulant being substantially level with a top surface of the die stack. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 122,163 |
11862606 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A package and the method of forming the package are provided in accordance with various exemplary embodiments. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. FIG.1illustrates a cross-sectional view of package20in accordance with some embodiments. Package20includes package100and package200over and bonded to package100. In some embodiments, package100includes device dies102, with the front sides of device dies102facing down and bonded to Redistribution Layers (RDLs)132/134/136. Throughout the description, the term “RDL” also refers to the redistribution lines in the redistribution layers. In alternative embodiments, package100includes a single device die or more than two device dies. Device die102may include semiconductor substrate108, and integrated circuit devices104(such as active devices, which include transistors, for example) at the front surface (the surface facing down) of semiconductor substrate108. Device die102may include a logic die such as a Central Processing Unit (CPU) die, a Graphic Processing Unit (GPU) die, a mobile application die, or the like. Device dies102are molded in molding material120, which surrounds each of device dies102. Molding material120may be a molding compound, a molding underfill, a resin, or the like. The bottom surface120A of molding material120may be level with the bottom ends of device dies102. The top surface120B of molding material120may be level with or higher than back surface108A of semiconductor substrate108. In some embodiments, back surface108A of semiconductor substrate108is overlapped by die-attach film110, which is a dielectric film adhering device die102to the overlying dielectric layer118. Device die102further includes metal pillars/pads106(which may include copper pillars, for example) in contact with, and bonded to, RDLs132. Package100may include bottom-side RDLs132/134/136underlying device dies102, and top-side RDLs116overlying device dies102. Bottom-side RDLs132/134/136are formed in dielectric layers114, and top-side RDLs116are formed in dielectric layers118. RDLs132/134/136and116may be formed of copper, aluminum, nickel, titanium, alloys thereof, or multi-layers thereof. In some embodiments, dielectric layers114and118are formed of organic materials such as polymers, which may further include polybenzoxazole (PBO), benzocyclobutene (BCB), polyimide, or the like. In alternative embodiments, dielectric layers114and118are formed of inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. Through-Vias122are formed to penetrate through molding material120. In some embodiments, through-vias122have top surfaces level with the top surface120B of molding material120, and bottom surfaces level with the bottom surface120A of molding material120. Through-Vias122electrically couple bottom-side RDLs132/134/136to top-side RDLs116. Through-Vias122may also be in physical contact with bottom-side RDLs132and top-side RDLs116. Electrical connectors124, which are formed of a non-solder metallic material(s), are formed at the bottom surface of package100. In some embodiments, electrical connectors124include Under-Bump Metallurgies (UBMs), which are also metal pads. In alternative embodiments, electrical connectors124are metal pads, metal pillars, or the like. Metal pads124may comprise copper, aluminum, titanium, nickel, palladium, gold, or multi-layers thereof. In some embodiments, the bottom surfaces of metal pads124extend below the bottom surface of the bottom dielectric layer114, as shown inFIG.1. Solder regions126may be attached to the bottom surfaces of metal pads124. In some embodiments, RDLs132/134/136include portions (including132and134) in more than one metal layers and vias136interconnecting the RDLs in different metal layers. For example,FIG.1illustrates RDLs132, which are closest to through-vias122. The bottom surfaces of through-vias122are in contact with some of RDLs132. Furthermore, metal pillars106of device die102are also in contact with some of RDLs132. Electrical connectors124are electrically coupled to, and may be in physical contact with, RDLs134. Hence, RDLs134may be in the metal layer that is closest to electrical connectors124. Vias136are disposed between, and electrically interconnect, RDLs132and RDLs134. FIG.2illustrates a bottom view of one of RDLs134. The illustrated RDL134includes main pad region138, metal trace142, and bird-beak region140connecting main pad region138to metal trace142. In accordance with some embodiments, main pad region138has a round bottom-view shape. In alternative embodiments, main pad region138may have other applicable shapes including, and not limited to, rectangles, hexagons, octagons, and the like. bird-beak region140is the region that has widths gradually and/or continuously transition from the width of main pad region138to the width of metal trace142. Metal trace142has one end connected to one of vias136, which leads to RDLs132(FIG.1). Arrow144is drawn to show the direction pointing from the center of main pad region138to the center (FIGS.3,4, and6-8) of bird-beak region140. Direction144may also point from the center of main pad region138to the connecting point between bird-beak region140and metal trace142. Main pad region138and bird-beak region140in combination form an RDL pad146for supporting and connecting to electrical connector124(FIG.1). Throughout the description, direction144is referred to the bird-beak direction of the respective RDL pad146and the bird-beak direction of the respective RDL134. FIG.3illustrates an exemplary bottom view of bottom package100, wherein RDL pads146(and some of RDL traces) are illustrated. RDLs134include center-facing pads (sometimes referred to as center-facing metal pads hereinafter)146A and randomly-pointed pads146B. InFIGS.3through9J, circles are used to schematically represent randomly-pointed RDL pads146B. Center-facing pads146A, however, are illustrated with more details to indicate their bird-beak directions. For example, the main pad region, the bird-beak region, and the respective bird-beak direction of center-facing pads146A are schematically illustrated. FIG.5illustrates the bottom views (or top views) of exemplary randomly-pointed RDL pads146B with more details, wherein the randomly-pointed RDL pads146B are shown inFIGS.3,4, and6through9J.FIG.5schematically illustrate an inner region153(also refer toFIGS.3and4) of package100and the randomly-pointed RDL pads146B therein. As shown inFIG.5, randomly-pointed RDL pads146B may have the similar shapes as center-facing pads146A. For example, randomly-pointed RDL pads146B may also include main pad regions, and bird-beak regions connected to the respective main pad regions. There are also metal traces connected to the bird-beak regions, with the metal traces further connected to vias136. As shown inFIG.5, the bird-beak directions of randomly-pointed RDL pads146B are randomly disposed, and can be in any directions. Therefore, each of the bird-beak directions of randomly-pointed pads146B may be in any direction, including center-facing and non-center-facing. For example, the bird-beak directions of randomly-pointed RDL pads146B do not necessarily point to the center of package100(FIGS.1and3), and do not necessarily point to the center of any device die in package100. Furthermore, neighboring randomly-pointed RDL pads146B may have different bird-beak directions. Referring back toFIG.3, bottom package100includes four corners148. The corner RDL pads146, which are closer to the respective corners148than all other metal pads, are center-facing pads146A, which have their bird-beak directions pointing to (or substantially pointing to) center150of package100. Other RDL pads146that are farther away from the respective corners148than the corner RDL pads146A are randomly-pointed RDL pads146B. In some embodiments, there may be more than one center-facing pad146A at each corner148. For example,FIG.4illustrates three center-facing pads146A at each corner148. FIG.4also illustrates the bottom view of bottom package100and RDL pads146in accordance with alternative embodiments. In the bottom view, bottom package100has neutral-stress point150, which is the point that is substantially free from stresses from all lateral directions that are parallel to the bottom surface of package100. At neutral-stress point150, the lateral stresses from opposite directions are cancelled out. In some embodiments, neutral-stress point150is at or close to the center (also marked as150) of bottom package100(in the bottom view). The distance of each of RDL pads146to neutral-stress point150is referred to as a Distance to Neutral Point (DNP), wherein the distance to the RDL pads146may be measured from a point of the RDL pad146that is farthest to neutral-stress point150. For example, DNPs DNP1and DNP2are illustrated as examples inFIG.4. Referring toFIGS.3and4, circle152is drawn with the neutral-stress point150as the center, wherein circle152has radius r. In accordance with the embodiments of the present disclosure, all RDL pads146with the DNPs equal to or smaller than radius r may be designed as randomly-pointed RDL pads146B, and all RDL pads146with DNPs greater than radius r are designed to be center-facing pads146A. Some or all RDL pads146with the DNPs equal to or smaller than radius r may also be designed as center-facing pads146A. As illustrated inFIG.3, if radius r is large, then the center-facing pads146A may only include a single corner RDL pad146at each corner148. InFIG.4, radius r is reduced, and more corner RDL pads146are designed as center-facing pads146A, while the RDL pads146with the DNPs equal to or smaller than radius r are randomly pointed, and do not necessarily point to the center150. The optimum radius r of circle152may be determined by simulation or experiment (by forming physical chips), so that the reliability of the RDLs146inside the circle152meets design specification. InFIG.4, the center-facing pads146A at the same corner may have their bird-bird directions parallel to each other. This means that the bird-beak directions of some of center-facing pads146A (marked as146A′) are actually slightly offset from the center150. In alternative embodiments, all center-facing pads146A at the same corner148may have bird-beak directions pointing right at center150of package100, which means that their bird-beak directions are substantially, but not exactly, parallel to each other. FIG.6illustrates the design of RDL pads146in accordance with yet alternative embodiments. In these embodiments, four corner regions154of bottom package100are defined, each extending from one of corners148inwardly. The four corner regions154may have rectangular shapes, and may have sizes the same as each other. The RDL pads146inside corner regions154are designed as center-facing pads146A. The RDLs outside corner regions154may be designed as randomly-pointed RDL pads146B, or may be designed as center-facing pads146A. In some embodiments as inFIG.6, circle152is also drawn according to simulation or experiment results. The radius of circle152may be small, and hence some of RDL pads146that are outside of corner regions154are also outside of circle152. Accordingly, as shown inFIG.6, some of RDL pads146(marked as146″) that are outside of the circle152are also center-facing pads146A, while the RDL pads146that are outside of corner regions154, but inside circle152, are randomly-pointed RDL pads146B. FIGS.7and8illustrate the bottom views of package100in the embodiments in which the RDL pads146adjacent to the corners of device die(s)102(FIG.1) are also designed as center-facing pads146A. These embodiments may be combined with the embodiments inFIGS.3,4, and6, so that the center-facing pads146A as shown inFIGS.3,4, and6may also be designed as center-facing pads146A, in additional to the RDL pads146A adjacent to the corners of device die(s)102. Referring toFIG.7, device die102is illustrated. Device die102includes corners102A. At each of corners102A, device die102overlaps (Refer toFIG.1) at least a portion of one RDL pad146A. The neighboring RDL pads146adjacent to corners102A are designed as center-facing pads146A, wherein the neighboring RDL pads146are referred to as corner RDL pads146hereinafter. The corner RDL pads146of device die102, instead of having bird-beak directions pointing to the center150of package100, have bird-beak directions pointing to center156of device die102. The corner RDL pads146, which are center-facing pads, may be fully surrounded by randomly-pointed RDL pads. Similarly, the corner RDL pads146A close to the same corner of device die102may have their bird-beak directions parallel to each other, although the bird-beak directions may also point exactly to center156, hence are substantially, but not exactly, parallel to each other. Hence, throughout the description, when an RDL pad146is referred to as “center-facing,” the bird-beak direction of the RDL pad146may point to the center of the respective package, or the center of a device die, depending on where the RDL pad is located. FIG.8illustrates the bottom view of package100in accordance with alternative embodiments. These embodiments are similar to the embodiments inFIG.7, except that there are two device dies102disposed in bottom package100. The corner RDL pads146that are adjacent to the corners of each of device dies102are designed as center-facing pads146A. For each of the device dies102, the respective corner RLD pads146A have their bird-beak directions pointing to the center156of the respective device die102. FIGS.9A through9Jare the exemplary embodiments for defining what are the corner RDL pads of the device dies. ThroughoutFIG.9A through9J, nine RDL pads146are illustrated, and are marked with sequence numbers range from0to8, with the one with the sequence number 0 (referred to as the 0thRDL pad146hereinafter) being the central one of the nine RDL pads146. Furthermore, throughoutFIGS.9Athrough9J, dx represents the X-direction distance from the center of the 0thRDL pad146to the vertical edge102B1of device die102, and dy represents the Y-direction distance from the center of the 0thRLD pad146to the horizontal edge102B2. Pitch P1represents the pitches of neighboring RDL pads146, which are, for example, the distances between the centers of the main pad region138(FIG.2) of neighboring RDL pads146. Furthermore, in subsequently recited equations, the value “a” represents the diameter of RDL pads146, as shown inFIG.2. In each of theFIGS.9A through9J, the RDL pads146in rectangular region158(referred to as corner region hereinafter) are defined as corner RDLs, and are designed as center-facing pads. Hence, the center-facing pads include the 0th, the 1st, the 2nd, and the 4thRDL pads146. The 1st, the 2nd, and the 4thRDL pads146are the pads that are not overlapped by device die102, and are closest to corner102A. The remaining RDL pads146may be randomly-pointed RDL pads, which may include the 3rd, the 5th, the 6th, the 7th, and the 8thRDL pads146. FIGS.9A,9B, and9Cillustrate the embodiments wherein the 0thRDL pad146is fully overlapped by device die102, and rest of the corner RDL pads146are not overlapped by device die102. For example, if one of RDL pads146satisfies both of the following two relationships: a/2≤dx≤(P1−a/2) [Eq. 1] a/2≤dy≤(P1−a/2) [Eq. 2] the respective RDL pad146is the 0thRDL, and the respective corner region158and the RDL pads in the corner region158can be identified, as illustrated. InFIG.9A, the 0thRDL pad146does not have any point overlapped by edges102B1and102B2. InFIG.9B, the 0thRDL pad146has a point aligned to edge102B1, and the 0thRDL pad146and device die102have no overlap. InFIG.9C, dx is equal to (P1−a/2), which means that the 4thRDL pad146has a point aligned to edge102B1, and the 4thRDL pad146and device die102have no overlap. FIGS.9D,9E, and9Fillustrate the embodiments wherein the 0thRDL pad146are partially overlapped by the respective device die102. Furthermore, the corner102A of device die102also overlaps the 0thRDL pad146. For example, if one of RDL pads146satisfies both of the following two relationships: dx<a/2 [Eq. 3] dy<a/2 [Eq. 4] the respective RDL pads146is the 0thRDL, and the respective corner region158and the RDL pads in the corner region158can be identified. InFIGS.9D and9E, the centers of the 0thRDL pad146are not overlapped by the respective device dies102. InFIG.9F, the center of the 0thRDL pad146is overlapped by device die102. FIGS.9G through9Jillustrate the embodiments wherein the 0thRDL pad146is partially overlapped by device die102. Furthermore, edge102B2overlaps the 0thRDL pad146, while the corner102A of device die102does not overlap the 0thRDL pad146. For example, if one of RDL pads146satisfies both of the following two relationships: a/2≤dx≤(P1−a/2) [Eq. 5] dy<a/2 [Eq. 6] the respective RDL pads146is the 0thRDL pad, and the respective corner region158and the RDL pads in the corner region158can be identified. InFIGS.9G,9H, and9I, the centers of the respective 0thRDL pads146are overlapped by the respective device dies102. Furthermore,FIGS.9G,9H, and9Iillustrate the embodiments in which dx is equal to, smaller than, and greater than, (P1)/2. InFIG.9J, the center of the 0thpad RDL pad146is not overlapped by device die102. The embodiments of the present disclosure have several advantageous features. The RDL pads that are close to the corners of package100and device die102suffer from high stresses, and hence the RDL traces of these RDL pads are more likely to be broken by the stresses. Experiment results and simulation results indicate that the center-facing pads are more reliable, and the stresses suffered by the traces connected to the center-facing pads are lower than the stresses suffered by the randomly-pointed RDL pads. Accordingly, by designing the RDL pads that suffer from higher stresses as center-facing, the reliability of the respective package is improved. On the other hand, the RDL pads suffer from low stresses may have their bird-beak directions pointing randomly to improve the flexibility in RDL routing. In accordance with some embodiments of the present disclosure, a package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package. In accordance with alternative embodiments of the present disclosure, a package includes at least one first dielectric layer, a first plurality of redistribution lines in the at least one first dielectric layer, a device die over and electrically coupled to the first plurality of redistribution lines, a molding material molding the device die therein, a through-via penetrating through the molding material, and at least one second dielectric layer over the device die. A second plurality of redistribution lines is in the at least one second dielectric layer. The second plurality of redistribution lines is electrically coupled to the first plurality of redistribution lines through the through-via. A plurality of metal pads is underlying the device die and electrically coupled to the second plurality of redistribution lines. The plurality of metal pads includes a first center-facing metal pad and a non-center-facing metal pad. In accordance with yet alternative embodiments of the present disclosure, a package includes a plurality of dielectric layers, a plurality of redistribution lines in the plurality of dielectric layers, a device die over and electrically coupled to the plurality of redistribution lines, and a plurality of metal pads underlying and electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad, wherein the corner metal pad has a first bird-beak direction pointing to a first center of a package that includes the plurality of metal pads and the device die. The plurality of metal pads further includes an inner metal pad adjacent to a corner of the device die, wherein the inner electrical has a second bird-beak direction pointing to a second center of the device die. The plurality of metal pads also includes a plurality of non-center-facing metal pads surrounding the inner metal pad. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 23,167 |
11862607 | DETAILED DESCRIPTION Specific details of several embodiments of composite dielectric structures for semiconductor die assemblies, and associated systems and methods are described below. The term “semiconductor device or die” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices (or dies) include logic devices or dies, memory devices or dies, controllers, or microprocessors (e.g., central processing unit (CPU), graphics processing unit (GPU)), among others. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. Further, the term “semiconductor device or die” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished functional device. Depending upon the context in which it is used, the term “substrate” may include a semiconductor wafer, a package substrate, a semiconductor device or die, or the like. Suitable steps of the methods described herein can be performed with processing steps associated with fabricating semiconductor devices (wafer-level and/or die-level) and/or manufacturing semiconductor packages. Various computing systems or environments, e.g., high-performance computing (HPC) systems, require high bandwidth and low power consumption. Certain schemes of forming interconnects between semiconductor dies (e.g., a direct bonding scheme) may facilitate satisfying the requirements, as well as providing form-factors suitable for scaling physical dimensions (e.g., heights) of semiconductor die assemblies of the HPC systems. The direct bonding scheme includes individual conductive components (e.g., copper pads, conductive pads) of a first semiconductor die (or a first wafer including the first semiconductor die) aligned and directly bonded to corresponding one of conductive components of a second semiconductor die (or a second wafer including the second semiconductor die). Further, a dielectric material surrounding each of the conductive components of the first semiconductor die can be directly bonded to another dielectric material surrounding each of the conductive components of the second semiconductor die. In other words, the bonding interface includes two or more dissimilar materials of the first semiconductor die directly bonded to corresponding materials of the second semiconductor die (e.g., between dielectric materials, between conductive materials) to form interconnects and surrounding dielectric layers. As such, the direct bonding scheme may also be referred to a combination bonding scheme, a hybrid bonding scheme, or the like. In some embodiments, the conductive materials include copper (or other suitable conductive materials or metals, such as tungsten (W)) as a primary constituent, and the dielectric materials include silicon oxides (e.g., SiO2), silicon nitrides (e.g., Si3N4), silicon carbon nitrides (e.g., SiCN), silicon carbonates (e.g., SiCO), or the like. During the direct bonding process, the dielectric materials of the first and second semiconductor dies (or the first and second wafers including the first and second semiconductor dies) are brought together such that the dielectric materials adhere to each other. Subsequently, the semiconductor dies are annealed at an elevated temperature such that the conductive materials of the first and second semiconductor dies are conjoined to form permanent bonding—e.g., metallurgical bonding. Additionally, the dielectric materials may enhance their bonding strength during the annealing process. If any irregularities (e.g., defects, particles) exist at the bonding interface (which may also be referred to as a mating interface or a bond line), such irregularities would weaken the bonding strength between the semiconductor dies (or the wafers), for example by forming voids surrounding the irregularities, at least due to stiffness and/or brittleness of the dielectric materials. In some cases, even if the direct bonding forms to hold the two semiconductor dies (or wafers) bonded together, the voids present at the bonding interface may interfere with forming robust interconnects between the conductive components. If portions of conductive components are not conjoined (e.g., fused) due to the voids, the interconnects including partially conjoined conductive components may have higher than desired resistance values. If the conductive components fail to form continuous conductive paths, the interconnects may suffer from electrical opens. In some cases, the voids may include the conductive materials that originate from the conductive components connected to the voids—e.g., through various mechanisms causing the conductive materials to migrate, such as extension, extrusion, diffusion, or the like. If the voids are large enough to reach multiple conductive components, the voids may serve as conduits for the conductive materials (e.g., Cu) to migrate such that undesired leakage paths and/or electrical shorts can occur between the conductive components. Accordingly, the environment for the direct bonding process needs to be ultra clean in order to avoid the particles at the bonding surfaces, which in turn, tends to increase the manufacturing cost. The present technology mitigates risks associated with forming compromised bonding interfaces (e.g., voids weakening bonding strength, interconnects having partially conjoined conductive components, lateral leakage paths and/or electrical shorts between interconnects) by providing composite dielectric structures at the bonding interface. The composite dielectric structure includes a dielectric surface layer suitable for the direct bonding scheme (e.g., silicon oxides, silicon nitrides, silicon carbonates, etc.) such that the bonding strength provided by the dielectric surface layer can be maintained. Additionally, the composite dielectric structure includes a layer with elastic properties that can tolerate the irregularities (e.g., particles, defects) at the bonding interface—e.g., conforming to the shapes of the irregularities. In some embodiments, the layer with elastic properties may include a polymer material that is flexible to deform in response to localized pressure generated by the irregularities during the bonding process. For example, a chemical vapor deposition (CVD) process may be used to deposit a flexible dielectric layers to reduce and/or eliminate voids caused by the irregularities at the bonding interface—e.g., applying siloxane derivatives (e.g., hexamethyldisiloxane (HMDSO)) as a precursor. In this manner, the composite dielectric structure can avoid forming the voids and/or substantially reduce sizes of the voids despite the irregularities that may be present at the bonding interface. As a result, the bonding interface can be improved to have enhanced bonding strength at least due to increased bonding areas, reduced quantities of interconnects having high resistance, reduced probabilities of forming leakage paths between interconnects, among others. Additionally, or alternatively, the direct bonding process employing the composite dielectric structures may be carried out in an environment with relatively lenient requirements directed to the particles, which in turn, may reduce the manufacturing cost. As used herein, the terms “front,” “back,” “vertical,” “lateral,” “down,” “up,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor device assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. FIG.1is an example schematic diagram100of a semiconductor die assembly. The diagram100illustrates a bonding interface105between semiconductor dies101(also identified individually as101a/b) directly bonded to each other. The semiconductor dies101are depicted to include substrates110(also identified individually as110a/b) and dielectric layers120(also identified individually as120a/b). Moreover, the semiconductor dies101include through-substrate vias (TSVs)115(also identified individually as115a/b) coupled to integrated circuitry (not shown) of the semiconductor dies101. The TSVs115are also connected to corresponding conductive components125(also identified individually as125a/b) of the semiconductor dies101. As such, the conductive components125are operatively coupled to the integrated circuitry. At the bonding interface105, the dielectric layers120a/bare directly bonded (e.g., conjoined, fused) to form the dielectric-to-dielectric bonding130. Also, the conductive components125a/bare directly bonded (e.g., conjoined, fused) to form the metal-to-metal bonding135at the bonding interface105. Accordingly, the bonding interface105includes both the dielectric-to-dielectric bonding130and the metal-to-metal bonding135, and may be referred to as combinational bonding interface or a hybrid bonding interface. The diagram100illustrates interconnects140(also identified individually as140a-c) that each includes the conjoined conductive components125. In some cases, the bonding interface105may include irregularities (e.g., defects, particles). For example, the diagram100illustrates an irregularity145at the bonding interface105. The dielectric layers120(e.g., including SiO2, SiCN) tend to be stiff and/or brittle such that the dielectric layers120may not locally conform to the irregularity145during the direct bonding process. As a result, voids (e.g., the void150depicted in the diagram100) may form around the irregularity145at the bonding interface105. As such, although overall direct bonding between the dielectric layers120may be established to bond the semiconductor dies101together, the bonding interface105may include such voids associated with the irregularities. Presence of the voids reduces overall area of the dielectric-to-dielectric bonding130, and thus decreases the bonding strength of the bonding interface105. In some cases, certain voids formed at the bonding interface105may be sufficiently large to interfere with (hinder, impede) forming the metal-to-metal bonding135. For example, the void150may expand (encroach) into the interconnect140csuch that the metal-to-metal bonding of the interconnect140cis compromised. As a result, the interconnect140cmay have a higher resistance than other interconnects140(e.g., the interconnect140a). Such variations in electrical characteristics of the interconnects140may degrade performance of the semiconductor die assembly. If the size of the void150is large enough to prevent the interconnects140to form continuous current paths (e.g., resulting in electrical opens), such interconnects140may cause the semiconductor die assembly to fail to operate. In some embodiments, the metal-to-metal bonding135may be formed by thermally expanding (e.g., through volume expansion in response to thermal energy applied during the direct bonding process) the conductive materials of the conductive components125(e.g., copper) after the semiconductor dies101are brought in contact with each other. Accordingly, the voids, if connected to the conductive components125, may serve as conduits, through which the conductive materials can migrate. If the void150is large enough to bridge (or otherwise connect) two or more interconnects140as illustrated in the diagram100, the void150including traces of conductive materials may result in undesired leakage paths and/or electrical shorts between the interconnects—e.g., between the interconnect140band the interconnect140c. FIG.2is a schematic diagram of a composite dielectric structure260in accordance with embodiments of the present technology. The composite dielectric structure260may facilitate tolerating the irregularities during the direct bonding process such that the quality of the bonding interface may be improved—e.g., mitigating adverse effects originating from the irregularities. The composite dielectric structure260includes a first dielectric layer265, a second dielectric layer270, and a third dielectric layer275between the first dielectric layer265and the second dielectric layer270. The first and second dielectric layers265and270may include at least one of silicon oxides (e.g., SiO2), silicon nitrides (e.g., Si3N4), silicon carbon nitrides (e.g., SiCN), silicon carbonates (e.g., SiCO), or the like. The first and second dielectric layers265and270are configured to provide robust bonding strength in contact with other dielectric layers as described in more detail with reference toFIGS.3and4—e.g., a dielectric layer directly bonded to the second dielectric layer270, a dielectric layer upon which the first dielectric layer265is deposited to form the composite dielectric structure260. The third dielectric layer275may be configured to conform to one or more irregularities that may be present at the bonding interface—e.g., the surface of the second dielectric layer270. In some embodiments, the third dielectric layer275includes a polymer material that is flexible to deform in response to localized pressure generated by the one or more irregularities. In other words, the third dielectric layer275may have elastic properties that can tolerate the particles and/or defects present at the bonding interface. As such, the third dielectric layer275may be represented as a “resistive” or “spring-like” layer as depicted inFIG.2. In this manner, the composite dielectric structure260can provide both the bonding strength of the dielectric material of the second dielectric layer270, as well as the flexibility of the third dielectric layer275to tolerate the irregularities at the bonding interface. In this regard, the localized pressure stemming from the irregularities may be applied to (transferred to) the third dielectric layer275through the second dielectric layer270located at the bonding interface (e.g., the bonding interface405described with reference toFIG.4). In some embodiments, a CVD process may be used to deposit the first, second, and third dielectric layers as depicted inFIG.2. For example, a semiconductor die (e.g., a semiconductor die301described with reference toFIG.3or a wafer including the semiconductor die301, semiconductor dies401described with reference toFIG.4or a wafer including the semiconductor dies401) may be placed in a CVD chamber configured to receive a first gas having oxygen (O2) and a second gas having a precursor (e.g., hexadimethylsiloxane (HDMSO)) including the polymer material (e.g., polydimethylsiloxane (PDMS)). Subsequently, the first dielectric layer265(e.g., including SiO2) may be formed by providing the first and second gases to the CVD chamber with a first ratio between the oxygen and the precursor. The first ratio can be configured to deposit SiO2on the semiconductor die (or the semiconductor wafer) to form the first dielectric layer265. After a desired thickness of the first dielectric layer265is achieved, the third dielectric layer275(e.g., including PDMS) may be formed by modifying (e.g., decreasing) an amount of the first gas provided to the CVD chamber to establish a second ratio between the oxygen and the precursor. The second ratio can be configured to deposit the polymer material (e.g., PDMS) on the first dielectric layer265to form the third dielectric layer275. After a desired thickness of the third dielectric layer275is achieved, the second dielectric layer270may be formed on the third dielectric layer275by restoring the amount of the first gas provided to the CVD chamber to establish the first ratio to deposit SiO2to form the second dielectric layer270on the third dielectric layer275. As described herein, process conditions for the CVD process may be modified by modifying the ratio between O2and the precursor (e.g., HDMSO, other suitable siloxane derivatives) to vary relative contents of the polymer material and the SiO2. In some embodiments, the third dielectric layer275includes the polymer material only. In other embodiments, the third dielectric layer275primarily includes the polymer material—e.g., the third dielectric layer275may partially include SiO2as well. Although the foregoing example CVD process utilizes the precursor configured to deposit SiO2and PDMS (a polymer material) based on the ratio between O2and the precursor (HDMSO) in the CVD chamber, in other embodiments, different precursors (and/or one or more gases other than O2) may be provided to the CVD chamber so as to deposit the polymer material and at least one of silicon oxides (e.g., SiO2), silicon nitrides (e.g., Si3N4), silicon carbon nitrides (e.g., SiCN), silicon carbonates (e.g., SiCO), or the like. FIG.3is a schematic diagram of a semiconductor die301including a composite dielectric structure (e.g., the composite dielectric structure260described with reference toFIG.2) in accordance with embodiments of the present technology. The semiconductor die301may include aspects of the semiconductor dies101described with reference toFIG.1. For example, the semiconductor die301includes the substrate110including integrated circuitry (not shown). The semiconductor die301also includes TSVs115(one of which is depicted inFIG.3) coupled to the integrated circuitry. Further, the semiconductor die301includes a dielectric layer320having the composite dielectric structure260over the substrate110. In some embodiments, the dielectric layer320includes an additional dielectric layer380formed on the substrate110, on which the composite dielectric structure260is formed. In some embodiments, the dielectric layer380may be formed using process steps utilizing tetraethyl orthosilicates (TEOS) or other suitable techniques to deposit dielectric materials—e.g., high plasma density (HDP) oxides. The semiconductor die301also includes conductive components125(one of which is depicted inFIG.3) coupled to the TSV115. The conductive component125may also be referred to as conductive pads and configured to have physical dimensions (e.g., surface area, thickness) to provide adequate volume of conductive materials (e.g., copper) to form robust interconnects (e.g., the interconnects440depicted inFIG.4) during the direct bonding process. In some embodiments, the conductive pads125can be formed in the dielectric layer320—e.g., after the composite dielectric structure260(and the dielectric layer380) is formed over the substrate110. As such, each conductive pad125extends through the composite dielectric structure260and is surrounded by the composite dielectric structure260(e.g., surrounded by the first, second, and third dielectric layers of the composite dielectric structure260). The composite dielectric structure260includes the first dielectric layer265located at a first side261of the composite dielectric structure260facing the substrate110, the second dielectric layer270located at a second side262of the composite dielectric structure260opposite to the first side261, and the third dielectric layer275between the first dielectric layers265and the second dielectric layer270. In other words, the third dielectric layer275is sandwiched between the first and second dielectric layers265and270. The second side262would form a bonding interface (e.g., the bonding interface405described with reference toFIG.4) if directly bonded with another semiconductor die (e.g., the semiconductor die101, the semiconductor die401) as depicted inFIG.4. The third dielectric layer275may be configured to conform to one or more irregularities at the second side262—e.g., at the bonding interface during the direct bonding process. In some embodiments, the third dielectric layer275includes a polymer material (e.g., PDMS) that is flexible (e.g., having elastic material properties) to deform in response to localized pressure generated by the one or more irregularities (e.g., defects, particles) at the second side262during the direct bonding process. As such, the localized pressure may be applied to the third dielectric layer275through the second dielectric layer270. As described with reference toFIG.2, the first, second, and third dielectric layers may be deposited during a CVD process by modifying the amounts of gas flows (e.g., the gas flows providing O2and the precursor). In some embodiments, the third dielectric layer275includes the polymer material only. In other embodiments, the third dielectric layer275primarily includes the polymer material—e.g., having partial SiO2contents. Further, the second dielectric layer270may be configured to conform to the one or more irregularities at the second side262. As such, in some embodiments, the second dielectric layer270may be configured to include partial polymer material contents. In other embodiments, the second dielectric layer270may not include any polymer material contents. In such embodiments, the second dielectric layer270may be formed thin enough to be flexible to deform in response to localized pressure generated by one or more irregularities. Further, the second dielectric layer270can be configured to directly bond to another dielectric layer in contact with the second dielectric layer270during the direct bonding process—e.g., if a second semiconductor die is directly bonded to the semiconductor die301as depicted inFIG.4. In some embodiments, the second dielectric layer270is at least 50 nm thick (denoted as t3inFIG.3), and the third dielectric layer275is at least twice thick (denoted as t2inFIG.3) as the second dielectric layer270. In other embodiments, the second dielectric layer270is at least 100 nm thick, and the thickness of the third dielectric layer275may range between 200 to 500 nm. In some embodiments, the thickness of the third dielectric layer275is determined by the sizes of the one or more irregularities—e.g., based on the cleanroom environment, in which the direct bonding process is carried out. In some embodiments, the first dielectric layer265may be configured to provide an adequate transition and/or adhesion between the dielectric layer380and the composite dielectric structure260—e.g., the transition between the TEOS process depositing the dielectric layer380and the CVD process depositing the composite dielectric structure260, the adhesion between the SiO2layer formed by the TEOS process and the first dielectric layer265. In some embodiments, the total thickness of the composite dielectric structure260(denoted as T inFIG.3) may range between 1 to 2 micrometers (μm). In some embodiments, the thickness of the dielectric layer380(denoted as t0inFIG.3) may be determined to provide adequate thickness of the conductive pads125such that the conductive pads125can form robust interconnects (e.g., the interconnects440) during the direct bonding process. FIG.4is a schematic diagram400of a semiconductor die assembly configured in accordance with embodiments of the present technology. The diagram400illustrates a bonding interface405between semiconductor dies401a/bdirectly bonded to each other. The semiconductor dies401a/bmay be examples of the semiconductor die301described with reference toFIG.3—i.e., the semiconductor dies401a/binclude the composite dielectric structure260described with reference toFIGS.2and3as part of their dielectric layers420a/b. In this regard, the orientation of the dielectric layer420acorresponds to that of the dielectric layer320depicted inFIG.3, while the orientation of the dielectric layer420bis upside down (e.g., flipped) with respect to the dielectric layer320depicted inFIG.3. Similar to the bonding interface105described with reference toFIG.1, the bonding interface405may include irregularities (e.g., defects, particles). For example, the diagram400illustrates an irregularity145at the bonding interface405. As described herein, the dielectric layer420a(and the dielectric layer420b) includes the composite dielectric structure260configured to conform to one or more irregularities at the bonding interface405. As such, a void associated with the irregularity145may be absent at the bonding interface405(or substantially reduced in its size (not shown)). In this manner, the bonding interface405may be improved when compared to the bonding interface105. For example, the bonding interface405, in comparison to the bonding interface105, may have enhanced bonding strength at least due to increased bonding areas, reduced quantities of interconnects440having high resistance, reduced probabilities of forming leakage paths between interconnects440, among others. Additionally, or alternatively, the direct bonding process may be carried out in an environment with relatively lenient requirements directed to the particles (e.g., particle sizes and/or distributions), which in turn, may reduce the manufacturing cost of the semiconductor die assembly. Although the foregoing example embodiment ofFIG.4includes both semiconductor dies (e.g., the semiconductor dies401) having the composite dielectric structure260, the present technology is not limited thereto. For example, in some embodiments, the semiconductor die401bmay be replaced with the semiconductor die101—i.e., a semiconductor die not including the composite dielectric structure260as part of its dielectric layer120. In such embodiments, the composite dielectric structure260of the semiconductor die401amay be modified (e.g., by increasing the thickness t2of the third dielectric layer275) such that the adverse effect due to the irregularity145can be mitigated by the single composite dielectric structure260of the semiconductor die401a. In some embodiments, a semiconductor die assembly includes a package substrate and a die (e.g., the semiconductor die401a) attached to the package substrate. The die includes a semiconductor substrate having integrated circuitry, and a dielectric structure (e.g., the composite dielectric structure206) over the semiconductor substrate. Further, the dielectric structure includes a first dielectric layer located at a first side of the dielectric structure facing the semiconductor substrate, a second dielectric layer located at a second side of the dielectric structure opposite to the first side, and a third dielectric layer between the first and second dielectric layers, the third dielectric layer configured to conform to one or more irregularities at the second side. In some embodiments, the third dielectric layer includes a polymer material that is flexible to deform in response to localized pressure generated by the one or more irregularities. In some embodiments, the semiconductor die assembly further includes one or more conductive pads formed in the dielectric structure, each conductive pad extending through the dielectric structure and configured to couple with at least one through-substrate via (TSV) coupled to the integrated circuitry. In some embodiments, the die is a first die, and the semiconductor die assembly further includes a second die (e.g., the semiconductor die101) directly bonded to the first die at the second side, where the second die includes a fourth dielectric layer directly bonded to the second dielectric layer, the second die being exclusive of the polymer material. In some embodiments, the die is a first die and the dielectric structure is the first dielectric structure, and the semiconductor die assembly further includes a second die (e.g., the semiconductor die401b) directly bonded to the first die, wherein the second die includes a second dielectric structure (e.g., the composite dielectric structure260) having a fourth dielectric layer directly bonded to the second dielectric layer at the second side, a fifth dielectric layer next to the fourth dielectric layer, the fifth dielectric layer configured to conform to the one or more irregularities at the second side, and sixth dielectric layer next to the fifth dielectric layer, the sixth dielectric layer facing a second semiconductor substrate of the second die. FIG.5is a block diagram schematically illustrating a system500including a semiconductor die assembly configured in accordance with embodiments of the present technology. The system500can include a semiconductor device assembly570, a power source572, a driver574, a processor576, and/or other subsystems or components578. The semiconductor device assembly570can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is the system500shown schematically inFIG.5. The semiconductor die assembly described with reference toFIG.4may be included in the semiconductor device assembly570of the system500. The semiconductor device assembly570can have features generally similar to the semiconductor die assembly described herein with reference toFIG.4. For example, the semiconductor device assembly570may include two semiconductor dies that are directly bonded to each other. At least one of the semiconductor dies may include a composite dielectric structure having a flexible dielectric layer that can tolerate irregularities (e.g., defects, particles) present at the bonding interface. The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during the direct bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor. The resulting system570can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems570can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system570may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system570can also include remote devices and any of a wide variety of computer readable media. FIG.6is a flowchart600of a method of making a composite dielectric structure in accordance with embodiments of the present technology. The flowchart600may include aspects of methods as described with reference toFIGS.2through5. The method comprises providing a semiconductor die including a substrate having integrated circuitry (box610). The method further comprises forming a dielectric structure over the substrate, the dielectric structure including a first dielectric layer located at a first side of the dielectric structure facing the substrate, a second dielectric layer located at a second side of the dielectric structure opposite to the first side, and a third dielectric layer between the first and second dielectric layers, the third dielectric layer configured to conform to one or more irregularities at the second side (box615). In some embodiments, forming the dielectric structure over the substrate includes depositing the first dielectric layer over the substrate in a chemical vapor deposition (CVD) chamber, depositing the third dielectric layer on the first dielectric layer in the CVD chamber without breaking a vacuum of the CVD chamber, and depositing the second dielectric layer on the third dielectric layer in the CVD chamber without breaking the vacuum of the CVD chamber. In some embodiments, the third dielectric layer includes a polymer material that is flexible to deform in response to localized pressure generated by the one or more irregularities. In some embodiments, forming the dielectric structure over the substrate includes placing the semiconductor die in a chemical vapor deposition (CVD) chamber configured to receive a first gas having oxygen and a second gas having a precursor including the polymer material, providing the first and second gases to the CVD chamber with a first ratio between the oxygen and the precursor, the first ratio configured to deposit a first silicon oxide material on the semiconductor die, the first silicon oxide material corresponding to the first dielectric layer, modifying an amount of the first gas provided to the CVD chamber to establish a second ratio between the oxygen and the precursor, the second ratio configured to deposit the polymer material on the silicon oxide, the polymer material corresponding to the third dielectric layer, and restoring the amount of the first gas provided to the CVD chamber to establish the first ratio to deposit a second silicon oxide material on the polymer material, the second silicon oxide material corresponding to the second dielectric layer. In some embodiments, the method may further include forming one or more conductive pads in the dielectric structure, each conductive pad extending through the dielectric structure and configured to couple with at least one through-substrate via (TSV) coupled to the integrated circuitry. It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined. From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, while in the illustrated embodiments certain features or components have been shown as having certain arrangements or configurations, other arrangements and configurations are possible. Moreover, certain aspects of the present technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. The devices discussed herein, including a semiconductor device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means. As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.” From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology. | 37,000 |
11862608 | DETAILED DESCRIPTION Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. FIG.1Aillustrates an X-Z plane of a semiconductor package100according to an embodiment of the present disclosure, andFIG.1Billustrates a Y-Z plane of the semiconductor package100illustrated inFIG.1A. Referring toFIGS.1A and1B, a semiconductor package100of an embodiment may include a package substrate110, at least a pair of semiconductor chips101and102, and at least a pair of support members121and122, a stack structure130, and an encapsulant140. In addition, the semiconductor package100may further include a plurality of connection bumps150disposed under the package substrate110. The package substrate110may include a first insulating layer111, wiring layers112, and second insulating layers113. The package substrate110may further include a via structures electrically connecting the wiring layers112disposed at different levels. The package substrate110may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, or the like. The first insulating layer111may include an insulating resin. The insulating resin may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin obtained by impregnating an inorganic filler or/and glass fiber (e.g., glass cloth or glass fabric) with these resins, for example, prepreg, Ajinomoto build-up film (ABF), glass-reinforced epoxy laminate material (e.g., NEMA grade FR-4), bismaleimide triazine (BT), or the like. The insulating resin may include a photosensitive resin such as a photo-imageable dielectric (PID) resin. For example, when the package substrate110is a PCB substrate, the first insulating layer111may be a core insulating layer (e.g., a prepreg) of a copper clad laminate. The first insulating layer111may have a form in which a greater number of insulating layers are stacked in a vertical direction (Z-axis direction) than that illustrated in the drawing. In this case, a boundary between the first insulating layers at different levels may not be apparent according to processes. The wiring layers112may be disposed on the first insulating layer111and may form an electrical path in the package substrate110. The wiring layers112may include at least one of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), an alloy including two or more metals thereof, or other conductive materials. The wiring layers112may be provided with fewer or more layers (e.g., one layer or three or more layers) than those illustrated in the drawings. The wiring layers112is disposed adjacent to at least a pair of semiconductor chips101and102and may include a plurality of wiring pads (e.g., “112P” inFIG.6A) electrically connected to the semiconductor chips101and102. The second insulating layers113may be disposed on the first insulating layer111and may cover at least a portion of the wiring layers112. The second insulating layers113may include an insulating resin or an insulating material different from the first insulating layer111. For example, the second insulating layers113may include a solder resist disposed above and below the first insulating layer111to protect the wiring layers112. The second insulating layers113may include a plurality of holes113H1exposing at least a portion (e.g., a wiring pad) of the wiring layers112and an opening113H2exposing at least a portion of the first insulating layer111positioned between the pair of semiconductor chips101and102. The opening113H2is filled with the encapsulant140, and accordingly, the encapsulant140may directly contact the first insulating layer111through the opening113H2. In the present disclosure, the first insulating layer111may include an insulating resin having a greater adhesion to the encapsulant140than the second insulating layers113. The plurality of holes113H1and the opening113H2may be formed by removing portions of the second insulating layers113by photolithography or the like. The second insulating layers113may include a first mounting region113R1corresponding to at least a pair of support members121and122and a second mounting region113R2corresponding to at least a pair of semiconductor chips101and102. In an embodiment, in a region in which non-filling and swelling of the encapsulant140might occur, the opening113H2may increase a height of a passage through which the encapsulant140in an uncured state flows and induce contact between the encapsulant140and the first insulating layer111, thereby preventing non-filling and swelling of the encapsulant140. For example, the first insulating layer111may have a first region111R1positioned between the pair of semiconductor chips101and102and a second region111R2positioned between the pair of semiconductor chips101and102and the pair of support members121and122. The opening113H2may include a first recess region (See “113H2” ofFIG.1C) exposing at least a portion of the first region111R1and extending in a first direction (e.g., the X-axis direction). A tunnel structure T may be formed on the first and second regions111R1and111R2. A side surface of the tunnel structure T may be surrounded by at least portions of the pair of semiconductor chips101and102and the pair of support members121and122and an upper surface thereof may be covered by the stack structure130. Therefore, when the uncured encapsulant140passes on the first and second regions111R1and111R2or through the tunnel structure T, a flow of the encapsulant140may be obstructed and voids might occur. However, according to embodiments of the present disclosure, flowability of the encapsulant140on the first and second regions111R1and111R2and adhesion of the encapsulant140and the package substrate110may be increased to prevent the occurrence of a void and swelling. In an example, in the third direction (Z-axis direction), substantially perpendicular to the first direction (X-axis direction) and the second direction (Y-axis direction), a height h1from an upper surface of the second insulating layers113to an upper surface of each of the pair of semiconductor chips101and102and the pair of support members121and122may range from about 40 μm to about 100 μm, and a height h2of the opening113H2on the first and/or second regions111R1and111R2may range from about 10 μm to about 30 μm or from about 15 μm to about 30 μm. In addition, in an example, the first insulating layer111may be a prepreg, the second insulating layers113may be a solder resist, and the encapsulant140may be an epoxy molding compound (EMC). After the encapsulant140was attached to each of the first and second insulating layers111and113, shear stress was measured as illustrated in Table 1 below. In Examples 1 to 3, the encapsulant140in the form of a lump was attached to and cured on the first insulating layer111and shear stress between the encapsulant140and the first insulating layer111was measured by applying a shear force. In Comparative Examples 1 to 3, shear stress was measured under the same conditions as in Examples 1 to 3, except that the encapsulant140was positioned on the second insulating layers113, respectively. Referring to Table 1, an average shear stress in Examples 1 to 3 is greater than an average shear stress in Comparative Examples 1 to 3, which may be understood that adhesion between the encapsulant140and the first insulating layer111is stronger than adhesion between the encapsulant140and the second insulating layers113. TABLE 1Shear stress (kgf)ClassificationMinimumMaximumAverageExample 15.29.26.9Example 26.18.37.0Example 35.19.56.4Comparative Example 12.57.45.4Comparative Example 23.56.54.9Comparative Example 33.07.35.2 At least a pair of semiconductor chips101and102may be disposed between a pair of support members121and122and may be spaced apart from each other in a second direction (Y-axis direction). For example, at least a pair of semiconductor chips101and102may be disposed between first and second support members121and122spaced apart in the first direction (X-axis direction) on the package substrate110and may face each other in the second direction (Y-axis direction). At least a pair of semiconductor chips101and102is attached on the second insulating layers113of the package substrate110by adhesive members101F and102F (e.g., DAF) and may be electrically connected to the wiring layers112of the package substrate110by a bonding wire W. The at least a pair of semiconductor chips101and102may include a control unit that controls a signal for at least one third semiconductor chip131included in the stack structure130. For example, when the third semiconductor chip131is a memory chip, the first and second semiconductor chips101and102may separately include a memory controller and a frequency boosting interface (FBI) chip. The memory controller may determine a data processing order of the memory chip and prevent errors and bad sectors, and an FBI chip may speed up an I/O. At least a pair of support members121and122may be positioned on the package substrate110and may be spaced apart from each other in the first direction (X-axis direction). For example, the first and second support members121and122may be disposed to face each other in the first direction, and the first and second semiconductor chips101and102facing each other in the second direction (Y-axis direction), substantially perpendicular to the first direction (X-axis direction), between the first and second support members121and122. The at least a pair of support members121and122may have a height substantially equal to or greater than the at least a pair of semiconductor chips101and102so as to support the stack structure130. For example, heights from the upper surface of the second insulating layers113to upper surfaces of the first and second semiconductor chips101and102and the first and second support members121and122may be substantially the same. The at least a pair of support members121and122may be attached to the package substrate110by the adhesive members121F and122F and may be a dummy semiconductor chip including a semiconductor material. In the present disclosure, the at least a pair of support members121and122are not particularly limited in a shape and material and may have various shapes and include various materials in consideration of a relationship with surrounding elements (e.g., coefficient of thermal expansion, modulus of elasticity, etc.). The stack structure130may include at least one third semiconductor chip131. The at least one third semiconductor chip131may be stacked on the at least a pair of semiconductor chips101and102and the at least a pair of support members121and122in the vertical direction (Z-axis direction). For example, a plurality of third semiconductor chips131attached to each other by an adhesive member131F may be stacked on at least a pair of semiconductor chips101and102and at least a pair of support members121and122. The at least one third semiconductor chip131may include a logic chip such as a central processor (CPU), a graphic processor (GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter (ADC), and an application-specific IC (ASIC), or a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), and a flash memory. In an example, the at least one third semiconductor chip131may include a NAND flash memory. Each semiconductor chip131may have a wire W that extends from a top surface of the semiconductor chip131through a hole113H1to a wiring layer112, without limitation thereto. The encapsulant140may be positioned on the package substrate110and may fill a space between at least a pair of support members121and122and a space between at least a pair of semiconductor chips101and102. The encapsulant140may include an insulating material, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a prepreg including an inorganic filler or/and a glass fiber, Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), EMC, and the like. As described above, a non-filling and swelling phenomenon of the encapsulant140may occur on the first and second regions111R1and111R2in which a flow space of the encapsulant140is not sufficient. However, in an embodiment, the encapsulant140may be in contact with at least a portion of the first and/or second regions111R1and111R2of the first insulating layer111between the pair of support members121and122and between the pair of semiconductor chips101and102, thereby increasing adhesion with the package substrate110. The plurality of connection bumps150may have a land, a ball, or a pin shape. The plurality of connection bumps150may include, for example, tin (Sn) or an alloy containing tin (Sn) (e.g., Sn—Ag—Cu). The plurality of connection bumps150may be electrically connected to the wiring layers112of the package substrate110and may be electrically connected to an external device such as a module substrate, a system board, etc. Hereinafter, the relationship among the pair of support members121and122, the pair of semiconductor chips101and102, and the package substrate110in the package100of an embodiment will be described in detail with reference toFIG.1C.FIG.1Cillustrates some components of the semiconductor package100illustrated inFIGS.1A and1B.FIG.1Cillustrates the first and second support members121and122, the first and second semiconductor chips101and102, and the package substrate110of the semiconductor package100. Lines I-I′ and II-II′ inFIG.1Crepresent cross-sections corresponding toFIGS.1A and1B, respectively. Referring toFIGS.1A and1Btogether withFIG.1C, the semiconductor package of an embodiment includes the package substrate110including the first insulating layer111and the second insulating layers113, a pair of support members121and122positioned to face each other on the second insulating layer of the package substrate110, and at least a pair of semiconductor chips101and102electrically connected to the package substrate110. Here, the second insulating layers113may have the opening113H2surrounding at least a portion of each of the pair of semiconductor chips101and102on the X-Y plane. For example, the opening113H2may have a form of a trench extending in the first direction (X-axis direction) between the first semiconductor chip101and the second semiconductor chip102and exposing at least a portion of the first region111R1of the first insulating layer111in the third direction (Z-axis direction). In the drawing, the opening113H2is positioned between the first semiconductor chip101and the second semiconductor chip102, but embodiments of the present disclosure are not limited thereto. In an example, the opening113H2may be disposed adjacent the first semiconductor chip101and the second semiconductor chip102except therebetween. In an example, a width of the opening113H2in the second direction (Y-axis direction) may be smaller than a width of the first region111R1, and a length of the opening113H2in the first direction (X-axis direction) may be greater than a width of the first and second semiconductor chips101and102. For example, the opening113H2may extend to the second region111R2ofFIG.1A. The trench-shaped opening113H2illustrated inFIG.1Cmay be formed in a portion where the non-filling phenomenon of the encapsulant140is concentrated to increase flowability of the encapsulant140and prevent non-filling and swelling. In addition, the second insulating layers113is disposed between the first insulating layer111and the pair of support members121and122and the pair of semiconductor chips101and102to provide mounting regions113R1and113R2of the support members121and122and the semiconductor chips101and102and protect the wiring layers112. Hereinafter, a modification of the semiconductor package100illustrated inFIG.1Awill be described with reference toFIG.1D.FIG.1Dillustrates an alternate embodiment modification of the semiconductor package illustrated inFIG.1A. InFIG.1D, components having the same reference numerals as those ofFIGS.1A and1Bhave substantially the same or similar features as those described above, and thus redundant descriptions may be omitted. Referring toFIG.1D, an alternate embodiment semiconductor package100′ may include a third support substrate123disposed between the stack structure130and the first and second support members121and122. The third support member123may be a dummy semiconductor chip formed of a material which is the same as or similar to the first and second support members121and122. The third support member123may be attached on the first and second support members121and122by an adhesive member123F. In an embodiment, the adhesive member123F may be formed above wires W1and W2that extend from top surfaces of the semiconductor chips101and102, respectively, through a hole113H1to a wiring layer112, without limitation thereto. In another embodiment, the wires W1and W2may extend from side or edge surfaces of the semiconductor chips101and102through the holes113H1. In yet another embodiment, portions of the wires W1and W2may pass through the adhesive member123F. The third support member123may have an area for covering the first and second support members121and122and the first and second semiconductor chips101and102between the first and second support members121and122on the X-Y plane. A height of the third support member123may be smaller than heights of the first and second support members121and122and the first and second semiconductor chips101and102. For example, the height of each of the first and second support members121and122and the first and second semiconductor chips101and102may range from about 30 μm to about 70 μm, and the height of the third support member123may range from about 20 μm to about 60 μm. FIG.2Aillustrates some components of a semiconductor package100aaccording to an embodiment of the present disclosure,FIG.2Billustrates the components illustratedFIG.2A,FIG.3Aillustrates a view taken along line A1-A1′ ofFIG.2B, andFIG.3Billustrates a view taken along line A2-A2′ ofFIG.2B.FIG.2Aillustrates a relationship among the first and second support members121and122, the first and second semiconductor chips101and102, and the package substrate110. InFIGS.2A through3B, components having the same reference numerals as those ofFIGS.1A to1Chave substantially the same or similar features as those described above, and thus, redundant descriptions thereof will be omitted. Referring toFIGS.2A through3B, in the semiconductor package100aof an embodiment, the opening113H2may have a form of a recess or cavity exposing the first region111R1of the first insulating layer111between the first semiconductor chip101and the second semiconductor chip102. Here, the opening113H2may expose the first region111R1in a range in which the opening113H2does not overlap the first and second semiconductor chips101and102in the third direction (Z-axis direction). For example, as illustrated inFIG.3A, a width of the opening113H2in the first direction (X-axis direction) may be substantially equal to a width of the first region111R1or the first and second semiconductor chips101and102. In addition, as illustrated inFIG.3B, a width of the opening113H2in the second direction (Y-axis direction) may be substantially equal to a width of the first region111R1or a width of the first and second semiconductor chips101and102. Depending on the arrangement of the first and second support members121and122and the first and second semiconductor chips101and102, a non-filling phenomenon of the encapsulant140may concentratively appear on the first region111R1. In an embodiment, the opening113H2may be formed to provide the mounting region113R2of the first and second semiconductor chips101and102on the second insulating layers113and protect a wiring layer disposed under the first and second semiconductor chips101and102, while maximizing an exposure area of the first region111R1. FIG.4Aillustrates some components of a semiconductor package100baccording to an embodiment of the present disclosure,FIG.4Billustrates the components illustratedFIG.4A,FIG.5Aillustrates a view taken along line B1-B1′ ofFIG.4B, andFIG.5Billustrates a view taken along line B2-B2′ ofFIG.4B.FIG.4Aillustrates a relationship among the second support members121and122, the first and second semiconductor chips101and102, and the package substrate110. InFIGS.4A through5B, components having the same reference numerals as those ofFIGS.1A to1Chave substantially the same or similar features as those described above, and thus, redundant descriptions thereof will be omitted. Referring toFIGS.4A to5B, in a semiconductor package100bof an embodiment, the opening113H2may further include a second recess region extending from one end of a first recess region corresponding to the first region111R1in the second direction (Y-axis direction) and exposing at least a portion of the second region111R2. Here, the opening113H2may expose at least portions of the respective first region111R1and second region111R2within a range not overlapping the first and second semiconductor chips101and102a wiring pad (“112P” ofFIG.5B). For example, as illustrated inFIG.5A, the width of the opening113H2in the first direction (X-axis direction) may be greater than the width of the first region111R1or the first and second semiconductor chips101and102. In addition, as illustrated inFIG.5B, the opening113H2may not extend to one end of the wiring pad112P to which the first and second semiconductor chips101and102are connected, in the first direction (X-axis direction), and may be covered by the second insulating layers113. However, in embodiments of the present disclosure, the wiring pad112P is not limited to a solder mask defined (SMD) form and may be configured in a non-solder mask defined (NSMD) form. Depending on the arrangement of the first and second support members121and122and the first and second semiconductor chips101and102, a non-filling phenomenon of the encapsulant140may appear even in the second region111R2, as well as in the first region111R1. In an embodiment, the opening113H2may be formed to protect the wiring pad112P, while exposing a portion of the second region111R2. FIG.6Aillustrates some components of a semiconductor package100caccording to an embodiment of the present disclosure,FIG.6Billustrates the components illustratedFIG.6A,FIG.7Aillustrates a view taken along line C1-C1′ ofFIG.6B, andFIG.7Billustrates a view taken along line C2-C2′ ofFIG.6B.FIG.6Aillustrates a relationship among the first and second support members121and122, the first and second semiconductor chips101and102, and the package substrate110. InFIGS.6A through7B, components having the same reference numerals as those ofFIGS.1A through1Chave substantially the same or similar features as the aforementioned contents, and thus redundant descriptions thereof will be omitted. Referring toFIGS.6A through7B, in a semiconductor package100caccording to an embodiment, the opening113H2may extend to edges of the first and second support members121and122to expose a plurality of wiring pads112P on the second region111R2. Here, the opening113H2may expose at least a portion of each of the first region111R1and the second region111R2within a range not overlapping the first and second semiconductor chips101and102and the first and second support members121and122. For example, as illustrated inFIG.7A, a width of the opening113H2in the first direction (X-axis direction) may be substantially the same as a width of the first region111R1and the second region111R2. In addition, as illustrated inFIG.7B, the opening113H2may extend to a region not overlapping the first and second support members121and122, while exposing the wiring pad112P to which the first and second semiconductor chips101and102are connected. Depending on an arrangement of the first and second support members121and122and the first and second semiconductor chips101and102, flowability of the encapsulant140may be maintained on the second region111R2. In an embodiment, the opening113H2may provide a mounting region113R1of the first and second support members121and122on the second insulating layers113, while maximizing an exposed region of the second region111R2. FIG.8Aillustrates some components of a semiconductor package100daccording to an embodiment of the present disclosure,FIG.8Billustrates the components illustratedFIG.8A, andFIG.9illustrates a view taken along line D1-D1′ ofFIG.8B.FIG.8Aillustrates a relationship among the first and second support members121and122, the first and second semiconductor chips101and102, and the package substrate110. InFIGS.8A through9, components having the same reference numerals as those ofFIGS.1A through1Chave substantially the same or similar features as those described above, and thus redundant descriptions will be omitted. Referring toFIGS.8A through9, in a semiconductor package100daccording to an embodiment, the first insulating layer111includes a third region111R3positioned at both ends of a second region111R2in the second direction (Y-axis direction), and the opening113H2may further include a third recess region extending from one end of the second recess region exposing the second region111R2and exposing at least a portion of the third region111R3. Here, the opening113H2may surround the first and second semiconductor chips101and102on the X-Y plane, and the mounting region111R2of the second insulating layers113on which the first and second semiconductor chips101and102are mounted may be substantially or fully separated from the second insulating layers113of another region. For example, as illustrated inFIG.9, the mounting region111R2of the second insulating layers113may be separated from the second insulating layers113by the opening113H2exposing the first region111R1and the third region111R3of the mounting region113R2of the second insulating layers113disposed between the first and second semiconductor chips101and102and the first insulating layer111. Depending on the arrangement of the first and second support members121and122and the first and second semiconductor chips101and102, if the width of the first region111R1and the second region111R2is reduced, the opening113H2may extend to an outer side (third region0of the tunnel structure formed between the first and second support members121and122to increase flow of the encapsulant. FIG.10Aillustrates some components of a semiconductor package100eaccording to an embodiment of the present disclosure, andFIG.10Billustrates the components illustratedFIG.10A.FIG.10Aillustrates a relationship among the first and second support members121and122, the first and second semiconductor chips101and102, and the package substrate110. InFIGS.10A and10B, components having the same reference numerals as those ofFIGS.1A through1Chave substantially the same or similar features as the aforementioned contents, and thus redundant descriptions thereof will be omitted. Referring toFIGS.10A and10B, the semiconductor package100eaccording to an embodiment may include a pair of first support members121aand121band a pair of second support members122aand122bspaced apart from each other in the second direction (Y-axis direction). Here, when an interval L3between the pair of first support members121aand121band the interval L3between the pair of second support members122aand122bare sufficiently secured, the opening113H2may not be formed between the pair of first support members121aand121band the pair of second support members122aand122b. For example, an interval L2between one of the pair of first support members121aand121band the pair of second support members122aand122band the first and second semiconductor chips101and102in the first direction (X-axis direction) and an interval L1between the first and second semiconductor chips101and102in the second direction (Y-axis direction) may range from about 500 μm to about 1500 μm, and the interval L3between the support members121a,121b,122a, and122bmay be about 2000 μm or more. According to embodiments of the present disclosure, a semiconductor package having an increased production yield by preventing non-filling and swelling of an encapsulant may be provided. While embodiments have been shown and described above by way of example, it will be apparent to those of ordinary skill in the pertinent art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims. | 28,833 |
11862609 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range. In semiconductor packages, upper and lower dies may be connected with a connection circuit that includes a through-silicon via (TSV) structure. A conventional TSV structure may typically involve forming a trench in a semiconductor substrate, forming a liner over the walls of the trench, and subsequently filling the lined trench with a conductive metal, for example, entirely with copper (Cu). Other device structures such as fuses, anti-fuses, resistors, and capacitors are conventionally located distal to the formed TSV. For example, such device structures may be formed in a back-end-of-the-line (BEOL) region of the die, such as in an interconnect structure. After electrical testing, a fuse structure may be used to interrupt current flow through the connection circuit. The fuse structure may electrically disconnect a defective die and/or according to customer needs. A conventional fuse structure may be electrically connected to an interconnect structure, and may be located some distance from a TSV structure. As a result of the distal location of the fuse structure, current may still be provided to at least a portion of the interconnect structure and/or other device structures, resulting in unnecessary power consumption. The present disclosure is directed to semiconductor devices, and specifically to semiconductor packages and dies that include a fuse structure configured to break a connection circuit, at a contact point between a TSV and an interconnect structure. As such, unnecessary power consumption may be prevented in a disconnected die. FIG.1Ais a vertical cross-sectional view of a first semiconductor die100, according to various embodiments of the present disclosure.FIG.1Bis an enlarged view of a portion P1ofFIG.1A. Referring toFIGS.1A and1B, the first die100may be, for example, an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chip. In some embodiments, the first die100may be an active component or a passive component. In some embodiments, the first die100includes a first semiconductor substrate102, a first dielectric structure104, a first interconnect structure110embedded within the first dielectric structure104, a first seal ring130, a first TSV structure162, and a first fuse structure180. In some embodiments, the first semiconductor substrate102may include an elementary semiconductor such as silicon or germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide. In some embodiments, the first semiconductor substrate102may be a semiconductor-on-insulator (SOI) substrate. In various embodiments, the first semiconductor substrate102may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to people having ordinary skill in the art. Depending on the requirements of design, the first semiconductor substrate102may be a P-type substrate or an N-type substrate and may have doped regions therein. The doped regions may be configured for an N-type device or a P-type device. In some embodiments, the first semiconductor substrate102includes isolation structures defining at least one active area, and a first device layer may be disposed on/in the active area. The first device layer may include a variety of devices. In some embodiments, the devices may include active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuits devices. The devices may be, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the first device layer includes a gate structure, source/drain regions, spacers, and the like. The first dielectric structure104may be disposed on a front side of the first semiconductor substrate102. In some embodiments, the first dielectric structure104may include silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. Other suitable dielectric materials may be within the contemplated scope of disclosure. The first dielectric structure104may be a single layer or a multiple-layer dielectric structure. For example, as shown inFIG.1B, the first dielectric structure104may include multiple dielectric layers104A-104F, which may include a substrate oxide layer104A, inter-layer dielectric (ILD) layers104B-104F, and a passivation layer104G. However, whileFIG.1Billustrates seven dielectric layers, the various embodiments of the present disclosure are not limited to any particular number of layers. Fewer or additional dielectric layers may be included in the first dielectric structure104. The first dielectric structure104may be formed by any suitable deposition process. Herein, “suitable deposition processes” may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma CVD (HDPCVD) process, a metalorganic CVD (MOCVD) process, a plasma enhanced CVD (PECVD) process, a sputtering process, laser ablation, or the like. A first interconnect structure110may be formed in the first dielectric structure104. The first interconnect structure110may include first metal features106disposed in the first dielectric structure104. The first metal features106may be any of a variety of metal lines and via structures that electrically connect the metal lines of adjacent ILD layers104B-104F. The first metal features106may be electrically connected to substrate electrodes108disposed on the first semiconductor substrate102, such that the first interconnect structure110may electrically interconnect semiconductor devices formed on the first semiconductor substrate102. In some embodiments, the substrate electrodes108may include metal gates of transistors formed in the device layer of the first semiconductor substrate102. The interconnect structure110may be formed of any suitable electrically conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, silver (Ag), combinations thereof, or the like. For example, the interconnect structure110may be preferably include copper at an atomic percentage greater than 80%, such as greater than 90% and/or greater than 95%, although greater or lesser percentages of copper may be used. Other suitable electrically conductive materials are within the contemplated scope of disclosure. In some embodiments, barrier layers (not shown) may be disposed between the first metal features106and the dielectric layers of first dielectric structure104, to prevent the material of the first metal features106from migrating to the first semiconductor substrate102. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof, for example. Other suitable barrier layer materials may be within the contemplated scope of disclosure. The first seal ring130may extend around the periphery of the first die100. For example, the first seal ring130may be disposed in the first dielectric structure104and may laterally surround the interconnect structure110. The first seal ring130may be configured to protect the interconnect structure110from contaminant diffusion and/or physical damage during device processing, such as plasma etching and/or deposition processes. The first seal ring130may include copper at an atomic percentage greater than 80%, such as greater than 90% and/or greater than 95% although greater or lesser percentages may be used. The first seal ring130may include conductive lines and via structures that are connected to each other, and may be formed simultaneously with the conductive lines106L and via structures106V of the first metal features106of the interconnect structure110. The first seal ring130may be electrically isolated from the first metal features106. Other suitable first seal ring materials may be within the contemplated scope of disclosure. In some embodiments, the first metal features106and/or the first seal ring130may be formed by a dual-Damascene process or by multiple single Damascene processes. Single-Damascene processes generally form and fill a single feature with copper per Damascene stage. Dual-Damascene processes generally form and fill two features with copper at once, e.g., a trench and overlapping through-hole may both be filled with a single copper deposition using dual-Damascene processes. In alternative embodiments, the first metal features106and/or the first seal ring130may be formed by an electroplating process. For example, the Damascene processes may include patterning the first dielectric structure104to form openings, such as trenches and/or though-holes (e.g., via holes). A deposition process may be performed to deposit a conductive metal (e.g., copper) in the openings. A planarization process, such as chemical-mechanical planarization (CMP) may then be performed to remove excess copper (e.g., overburden) that is disposed on top of the first dielectric structure104. In particular, the patterning, metal deposition, and planarizing processes may be performed for each of the ILD layers104B-104F, in order to form the interconnect structure110and/or the first seal ring130. For example, a first ILD layer104B may be deposited and patterned to form openings in the ILD layer. A deposition process may then be performed to fill the openings in the ILD layer104B. A planarization process may then be performed to remove the overburden and form metal features106in the ILD layer104B. These process steps may be repeated to form the ILD layers104C-104F and the corresponding metal features106, and thereby complete the first interconnect structure110and/or first seal ring130. A first bonding layer150A may be disposed over the first dielectric structure104. The first bonding layer150A may be formed of a dielectric material. One or more first die bonding pads152A may be formed in the first bonding layer150A. The first bonding layer150A may be formed by depositing a dielectric material, such as silicon oxide, silicon nitride, a polymer, or a combination thereof, using any suitable deposition process. Other suitable dielectric materials may be within the contemplated scope of disclosure. The first die bonding pads152A may be disposed in the first bonding layer150A. The first die bonding pads152A may be electrically conductive features formed of the same materials as the first metal features106. For example, the first die bonding pads152A may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, or a combination thereof, or the like. The first die bonding pads152A may be formed in the first bonding layer150A by a dual-Damascene processes, or by one or more single-Damascene processes, as described above. In alternative embodiments, the first die bonding pads152A may be formed by an electroplating process. The first TSV structure162may extend through a trench formed in the first semiconductor substrate102. The first TSV structure162may be formed during a middle-end-of-line (MEOL) process, and may be formed of suitable electrically conductive material, such as, copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, silver (Ag), tungsten (W), combinations thereof, or the like. For example, the first TSV structure162may preferably include copper at an atomic percentage greater than 80%, such as greater than 90% and/or greater than 95%, although greater or lesser percentages of copper may be used. In some embodiments, a barrier layer may be disposed between the first TSV structure162and the first semiconductor substrate102and the dielectric structure104. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof, for example. Other suitable barrier layer materials may be within the contemplated scope of disclosure. The first fuse structure180may be disposed between the first TSV structure162and the interconnect structure110. In particular, the first fuse structure180may be formed in the substrate oxide layer104A. The first fuse structure180may include a resistance control layer182, a contact etch stop layer (CESL)184, and a contact structure186. The first TSV structure162may directly contact a first surface of the resistance control layer182that faces the first semiconductor substrate102. The resistance control layer182may be formed of an electrically conductive material having a higher electrical resistance than the material(s) used to form the metal features106and/or TSV structure162. In some embodiments, the resistance control layer182may have a higher electrical resistance than copper. For example, the resistance control layer182may be formed of materials such as SiGe, W, TiN, TaN, combinations thereof, or the like. In some embodiments, the resistance control layer182and the substrate electrodes108may be formed during the same process and/or of the same materials. The CESL layer184may be formed of an etch-stop material such as silicon nitride, silicon carbide, silicon carbon nitride, combinations thereof, or the like. The CESL layer184may be formed as a single layer or multiple layers of the etch-stop material. The contact structure186may directly contact a second surface of the resistance control layer182that is distal from the first semiconductor substrate102. The contact structure186may be configured to electrically connect the resistance control layer182and/or the CESL layer184to a metal line106L disposed in the ILD layer104B. The contact structure186may be formed of a high melting point conductive material, such as tungsten or the like. Other suitable high melting point materials may be within the contemplated scope of disclosure. The contact structure186may be formed of one or more pillars186P that extend through the substrate oxide layer104A and contact the second surface of the resistance control layer182. For example, as shown inFIG.1B, the contact structure may include four pillars186P. However, the present disclosure is not limited to any particular number of pillars. For example, the contact structure186may include from1to20pillars186P, in various embodiments. An interface formed between the TSV structure162and the first surface of the resistance control layer182may have a first surface area. An interface formed between the contact structure186and the second surface of the resistance control layer182may have a second surface area. The first surface area may be greater than the second surface area. For example, the first surface area may be at least ten times greater than the second surface area. Accordingly, the contact structure186may be configured to concentrate current flowing between the interconnect structure110and the first TSV structure162in the relatively small second surface region. As such, applying a higher voltage may generate localized heating sufficient to melt and/or vaporize the resistance control layer182, thereby opening the first fuse structure180and electrically disconnect the interconnect structure110from the first TSV structure162. In some embodiments, the heated resistance control layer material may migrate into adjacent layers of the first die100, such that electrical contact between the contact structure186and the TSV structure162is broken. FIG.2is a flow chart showing the operations of a method of forming a TSV162in a first die100, according to various embodiments of the present disclosure.FIGS.3A-3Hare cross-sectional views showing operations of the method ofFIG.2, of whichFIGS.3C-3Hare enlarged views of a portion P ofFIG.3B. The first die100may be similar to the first die100shown inFIGS.1A and1B. For example, the first die100may include a first semiconductor substrate102, a dielectric structure104, an interconnect structure110, a first bonding layer150A, and a first fuse structure180. Referring toFIGS.2and3A, in operation702the first die100may be inverted and bonded to a carrier310. In particular, the first bonding layer150A may be bonded to a carrier bonding layer312. The carrier310may be any suitable carrier substrate, such as a silicon wafer or a sapphire substrate. Other suitable carrier substrate materials are within the contemplated scope of disclosure. Referring toFIGS.2and3B, in operation704a protection layer60may be deposited on the first die100. A gap fill layer62may then be deposited on the protection layer60. The protection layer60and/or the gap fill layer62may be formed of a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, combinations thereof, or the like and may be deposited using any suitable deposition method. The protection layer60and gap fill layer62may form a die encapsulation layer. Referring toFIGS.2and3C, in operation706a photoresist layer PR may be formed over the backside of the semiconductor substrate102. For example, a photoresist material may be deposited on gap fill layer62, exposed, and patterned to form the photoresist layer PR. The photoresist layer PR may have an opening that faces the first fuse structure180. Referring toFIGS.2and3D, in addition as part of operation706, a wet or dry etching process may then be performed, using the photoresist layer PR as a mask, to form a trench164that exposes the first fuse structure180. In some embodiments, a first etching process may be performed to etch the first semiconductor substrate102, and a second etching process may be performed to etch the substrate oxide layer104A disposed over the first fuse structure180. As such, the trench164may extend through the first semiconductor substrate102and the substrate oxide layer104A. The photoresist layer PR may subsequently be removed by ashing or the like. Referring toFIGS.2and3E, in operation708a barrier material190M may be deposited in the trench164and on the gap fill layer62, using any suitable deposition process. In some embodiments, the barrier material190M may include Ta, TaN, Ti, TiN, CoW, or combinations thereof, for example. Other suitable barrier materials may be within the contemplated scope of disclosure. Referring toFIGS.2and3F, in operation710an etch-back process may be performed to remove the barrier material190M from the bottom of the trench and the upper surface of the gap-fill layer62, to form a barrier layer190. The etch-back process may also remove any portion of the substrate oxide layer104A remaining on the first fuse structure180. Any suitable etch-back process, such as reactive ion etching or the like, may be used. Referring toFIGS.2and3G, in operation712, a seed layer162S may be deposited in the trench164and a TSV material layer162M may be formed on the seed layer162S. The seed layer162S may be formed by electrodeposition of a seed material, such as Ti, TiN, Cu, alloys thereof, or the like, and may be formed by any suitable method, such as by electrodeposition or the like. In step714, the TSV material layer162M may be formed of a conductive material such as Cu, Au, Ag, alloys thereof, or the like, and may be grown on the seed layer162S using an electrochemical plating process, or the like. Referring toFIGS.2and3H, in operation716, a planarization process, such as chemical-mechanical planarization (CMP) may be performed to planarize the die100. In particular, portions of the seed layer162S and the TSV material layer162M disposed outside of the trench164on the upper surface of the gap-fill layer62may be removed to form a first TSV structure162. While the first TSV structure162is shown to include a distinct seed layer162S and TSV metal layer162M, such distinct layers may not be present, as the materials thereof may become inter-dispersed. FIG.4Ais simplified top view of a semiconductor package10, according to various embodiments of the present disclosure.FIG.4Bis a cross-sectional view taken along line I-I′ ofFIG.4A. Referring toFIGS.4A and4B, the semiconductor package10may include at least one second die200stacked on the first die100ofFIGS.1A and1B. For example, the semiconductor package10may include three second dies200,200′,200″ stacked on the first die100. For convenience, only one second die200is described in detail below with respect to the cross sectional view ofFIG.4B. The second die200may be disposed over and bonded to the first die100. The second die200may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chip, for example. The second die200and the first die100may be the same type of dies or different types of dies. In some embodiments, the second die200may be an active component or a passive component. In some embodiments, the second die200may be smaller than the first die100. In some embodiments, the second die200is similar to the first die100. For example, the second die200may include a second semiconductor substrate202, a second dielectric structure204, a second interconnect structure210, a second seal ring230, a second TSV structure262, and a second fuse structure280. In some embodiments, the second die200may also include a third TSV structure263and a third fuse structure281. The second dielectric structure204may be disposed over a first side (e.g., front side) of the second semiconductor substrate202. The second dielectric structure204may have a single-layer or multi-layer structure. For example, the second dielectric structure204may include multiple ILD layers. The second interconnect structure210may be formed in the second dielectric structure204. Specifically, the second interconnect structure210may be overlapped with and electrically connected to an integrated circuit region of the second semiconductor substrate202. In some embodiments, the second interconnect structure210includes second metal features, such as metal lines and via structures. The second interconnect structure210may electrically connect semiconductor devices formed on the second semiconductor substrate202. The second seal ring230may be similar to the first seal ring130. For example, the second seal ring230may include copper at an atomic percentage greater than 80%, such as greater than 90% and/or greater than 95%, although greater or lesser percentages of copper may be used. The second seal ring230may be disposed over the first side (e.g., front side) of the second semiconductor substrate202. Specifically, the second seal ring230may surround the second interconnect structure210, may extend through the second dielectric structure204, and may be electrically insulated from circuit elements of the second semiconductor substrate202. In some embodiments, the second seal ring230may be formed during the formation of the second dielectric structure204. The semiconductor package10may include a first dielectric encapsulation (DE) layer50, a second DE layer52, a first bonding structure65, and a passivation layer70. The semiconductor package10may be bonded to a carrier310by a carrier bonding layer312. The first DE layer50may surround sidewalls of the first die100. The second DE layer52may surround sidewalls of the second die200. In some embodiments, the first DE layer50and the second DE layer52may include a molding compound comprising a resin and a filler. In alternative embodiments, the first DE layer50and the second DE layer52may include silicon oxide, silicon nitride, or a combination thereof. The first DE layer50and the second DE layer52may be formed by spin-coating, lamination, deposition processes, or the like. The bonding structure65may be configured to bond the first die100and the second die200. The bonding structure65may include one or more layers of a curable bonding material, such as an epoxy resin or the like. At least one die bonding pad67may be disposed in the bonding structure65. The die bonding pad67may be configured to electrically connect the first TSV structure162to the second interconnect structure210. In some embodiments, the die bonding pad67may be formed of the same type of metals as the first interconnect structure110and/or the second interconnect structure210. The passivation layer70may be disposed on the second DE layer52and may cover the second die200. The passivation layer70may be formed of a dielectric material, such as silicon nitride, silicon oxide, or the like. Device bonding pads72may be disposed in the passivation layer70. In some embodiments, the device bonding pads72may be under bump metallization (UBM) pads for mounting conductive connectors74, such as solder balls, metal pillars, micro-bumps or the like. The device bonding pads72may include a metal or a metal alloy. The device bonding pads72may include aluminum, copper, nickel, an alloy thereof, or the like, for example. Other suitable pad materials may be within the contemplated scope of disclosure. The second fuse structure280may electrically connect the second TSV structure262to the second interconnect structure210. The third fuse structure281may electrically connect the third TSV structure263to the second interconnect structure210. The second fuse structure280and the third fuse structure281may have the same structure and elements as shown in first fuse structure180. During assembly, the second die200may be flipped (e.g., turned upside down) and mounted onto the first die100. In particular, a second wafer including a plurality of the second dies200may be positioned over a first wafer including a plurality of the first dies100. In other embodiments, the second wafer may be diced to singulate the second dies200, and the second dies200may be individually placed on the first wafer, over respect first dies100. In some embodiments, the first die100and the second die200may be face-to-back bonded, as shown inFIG.4B. In other embodiments, the first die100and the second die200may be face-to-face bonded. In some embodiments, the first die100and the second die200may be aligned using an optical sensing method. After the alignment is achieved, a hybrid bonding process that includes a metal-to-metal bonding and a dielectric-to-dielectric bonding may be used to bond the first die100and the second die200. In various embodiments, a dicing process may be performed to singulate the three-dimensional device structure10. In some embodiments, a relatively high voltage may be applied to the first fuse structure180to open the first fuse structure180and electrically disconnect the first die100and the second die200. For example, if the second die200is determined to be defective, the second die200may be electrically disconnected from the first die100. The second fuse structure280may be used to respectively electrically disconnect the second TSV structure262from the second interconnect structure210. The third fuse structure281may be used to electrically disconnect the third TSV structure263from the second interconnect structure210. For example, if the second TSV structure262is determined to be defective, the second fuse structure may be opened to electrically disconnect the second TSV structure262from the second interconnect structure210, and the third TSV structure263may be used to electrically connect the second die200to an external device. Various embodiments provide a first die100that may include: a first semiconductor substrate102; a first interconnect structure110disposed on a front side of the first semiconductor substrate102; a first through-substrate via (TSV) structure162extending through the first semiconductor substrate102; and a first fuse structure180disposed between and electrically connecting the first TSV structure162and the first interconnect structure110. In one embodiment, the first fuse structure180may include: a contact structure186electrically connected to the first interconnect structure110; and a resistance control layer182having a first surface that contacts the first TSV structure162and an opposing second surface that contacts the contact structure186. In one embodiment, an interface between the first TSV structure162and the first surface of the resistance control layer182has a first surface area; an interface between the contact structure186and the second surface of the resistance control layer182has a second surface area; and the first surface area is greater than the second surface area. In one embodiment, the first surface area may be at least ten times greater than the second surface area. In one embodiment, the resistance control layer182may have a higher electrical resistance than at least one of the first interconnect structure110and the first TSV structure162. In one embodiment, the first interconnect structure110may include copper, a copper alloy, aluminum, an aluminum alloy, silver, or a combination thereof; the first TSV structure162may include copper, a copper alloy, aluminum, an aluminum alloy, silver, or a combination thereof; and the resistance control layer182may include silicon-germanium, tungsten, titanium nitride, tantalum nitride, or a combination thereof. In one embodiment, the first interconnect structure110and the first TSV structure162may include at least 90% Cu; and the resistance control layer182may include silicon germanium, tungsten, titanium nitride, tantalum nitride, or a combination thereof. In one embodiment, the contact structure186comprises at least one pillar that extends between a metal line of the first interconnect structure110and the resistance control layer182. In one embodiment, the first fuse structure180further includes a contact etch stop layer (CESL)184disposed on the second surface of the resistance control layer182. In one embodiment, the CESL184may include a single layer or multiple layers of an etch-stop material comprising silicon nitride, silicon carbide, silicon carbon nitride, a combination thereof. In one embodiment, the first fuse structure180may further include a barrier layer190disposed between the first TSV structure162and the first semiconductor substrate102. In one embodiment, the first die may further include a first dielectric structure104comprising a substrate oxide layer104A disposed directly on the front side of the first semiconductor substrate102and inter-layer dielectric (ILD) layers104B-104F disposed on the substrate oxide layer104A, wherein: the first interconnect structure110is embedded in the ILD layers104B-104F; and the first fuse structure180may be embedded in the substrate oxide layer104A, between the first TSV structure162and the first interconnect structure110. Various embodiments provide a semiconductor package that may include a first die100, where the first die100may include: a first semiconductor substrate102; a first dielectric structure104comprising a substrate oxide layer104A disposed directly on a front side of the first semiconductor substrate102and inter-layer dielectric (ILD) layers104B-104F disposed on the substrate oxide layer104A; a first interconnect structure110embedded in the first dielectric structure104; a first through-substrate via (TSV) structure162extending through the first semiconductor substrate102; and a first fuse structure180embedded in the substrate oxide layer104F and electrically connecting the first TSV structure162to the first interconnect structure110. In one embodiment, the first fuse structure180may include: a contact structure186electrically connected to the first interconnect structure110; and a resistance control layer182having a first surface that contacts the first TSV structure162and an opposing second surface that contacts the contact structure186. In one embodiment, an interface between the first TSV structure162and the first surface of the resistance control layer182has a first surface area; an interface between the contact structure186and the second surface of the resistance control layer182has a second surface area; and the first surface area may be at least ten times greater than the second surface area. In one embodiment, the resistance control layer182may have a higher electrical resistance than at least one of the first interconnect structure110and the first TSV structure162. Various embodiments further provide a method of forming a back-side through-silicon via structure, the method comprising: forming a trench164in a back side of a first semiconductor substrate102, such that the trench exposes a first fuse structure180disposed in a substrate oxide layer104A formed on a front side of the first semiconductor layer102; depositing a barrier material190M on the backside of the first semiconductor substrate102and in the trench164; performing an etch-back process to remove the barrier material190M from a bottom of the trench164and form a barrier layer190covering sidewalls of the trench164; depositing a seed layer162S in the trench164; and forming a TSV metal layer162M on the seed layer162S to form a TSV structure162in the trench164. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 35,490 |
11862610 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range. The present disclosure is directed to semiconductor devices, and particularly to a semiconductor die packaging process for forming fan-out wafer level packages that are resistant to stress cracking. During fabrication of fan-out wafer level packages, an array of complementary die sets may be arranged over a carrier wafer, and an array of primary semiconductor dies may be bonded to the array of complementary die sets. Each complementary die set includes at least one complementary semiconductor die. Each primary semiconductor die may be a system-on-integrated-circuit (SoIC) die that is configured to be bonded to a respective complementary die set. Molding compound layers laterally surround bonded assemblies of a primary semiconductor die and a complementary die set. This configuration is prone to mechanical damage due to structural stress concentration the stacking process and the dicing process. In this embodiment, fragments may be generated from the semiconductor dies and the carrier wafer. According to an aspect of the present disclosure, major crystallographic direction in the carrier wafer, the primary semiconductor die, and/or the complementary dies may be azimuthally offset from the horizontal directions of the sidewalls of the primary semiconductor dies. Generally, major crystallographic directions may be directions along which cracks may propagate within the carrier wafer, within the primary semiconductor dies, and within the complementary dies. Since the dicing channels are parallel to the sidewalls of the primary semiconductor dies in embodiments in which the primary semiconductor dies have orthogonal sidewalls, major crystallographic direction in the carrier wafer, the primary semiconductor die, and/or the complementary dies may be azimuthally offset from the directions of the dicing channels, and mechanical stress during dicing may be reduced. Generally, sidewalls of a semiconductor die that are arranged along a direction of periodicity within an array of semiconductor dies are prone to mechanical damage during stacking and during dicing. According to another aspect of the present disclosure, the primary semiconductor dies and the complementary dies may be oriented during stacking such that sidewalls of the primary semiconductor dies and the complementary dies are not parallel to the direction of periodicity during formation of an array of bonded semiconductor dies. For example, the primary semiconductor dies may be system-on-integrated-circuit (SoIC) dies, which are arranged as an array over a single crystalline silicon carrier substrate such that the major horizontal crystallographic directions of the single crystalline silicon carrier substrate are azimuthally offset from the two orthogonal directions of periodicity of the array of primary semiconductor dies. The azimuthal offset angle may be greater than 0.5 degree. As used herein, two directions are azimuthally offset from each other if the two directions differ by a finite angle (i.e., an azimuthal rotation angle around a vertical direction) in a plan view along a vertical direction, which is a view along a direction that is perpendicular to the top surface of the carrier substrate100in this embodiment. As used herein, all tilt angles between two directions, such as azimuthal offset angles, are measured between a pair of straight lines such that the measured value of the tilt angles is in a range from 0 degrees to 90 degrees. In other words, it is understood that all angle measurements are made such that the measured angle is zero, an acute angle, or an orthogonal angle (90 degrees). In another example, major crystallographic directions of the single crystalline substrate of each SoIC die may be azimuthally offset from the directions of the sidewalls of a respective SoIC die. In some embodiments, the azimuthal offset angle between the major crystallographic directions of the single crystalline substrate of an SoIC die and the sidewall of the SoIC die may be greater than 0.5 degree, and may be 45 degrees. In this embodiment, the silicon lattice directions (such as <100> directions) of the single crystalline substrate of an SoIC die may be different from the directions of the periodicity in the array of primary semiconductor dies, and thus, cracking of the primary semiconductor dies during stacking and dicing may be minimized. In some embodiments, the sizes and/or directions of some semiconductor dies (such as the complementary dies) may be inconsistent and/or incongruent with the size and the direction of another semiconductor die (such as the primary semiconductor die). In some embodiments, the major horizontal crystallographic directions of substrates of the semiconductor dies within each bonded set of semiconductor dies may be different from one another, and/or may be different from the major crystallographic directions of the carrier substrate, and/or may be different from the directions of periodicity in a rectangular array of bonded semiconductor dies as formed over the carrier substrate. The various embodiments of the present disclosure are now described in detail with reference to accompanying drawings. Referring toFIGS.1A and1B, a carrier substrate100for performing a fan-out wafer-level packaging process thereupon is provided. The carrier substrate100may be a semiconductor substrate, an insulating substrate, a conductive substrate, or a composite substrate including a stack of at least two different materials. According to an embodiment of the present disclosure, the carrier substrate100may be a single crystalline semiconductor carrier substrate such as a single crystalline silicon carrier substrate, i.e., a carrier substrate composed of single crystalline silicon material. In one embodiment, the carrier substrate100may comprise a commercially available silicon wafer. In one embodiment, the carrier substrate100may be a (100) silicon wafer, i.e., a single crystalline silicon wafer having a planar major surface including a (100) crystallographic plane so that a [100] crystallographic direction of the single crystalline material of the single crystalline silicon wafer is perpendicular to the physically exposed planar (100) crystallographic plane. In this embodiment, the (100) silicon wafer may include a [010] direction and a [001] direction selected from a pair of orthogonal in-plane horizontal directions, i.e., a pair of horizontal directions that are contained within the plane including the top surface of the silicon wafer. Alternatively, the (100) silicon wafer may include a [011] direction (which is a <110> direction) and a [0 1-1] direction (which is another <110> direction) selected from a pair of orthogonal in-plane horizontal directions. Alternatively, the carrier substrate100may be a (110) silicon wafer, i.e., a single crystalline silicon wafer having a planar major surface including a (110) crystallographic plane so that a [110] crystallographic direction of the single crystalline material of the single crystalline silicon wafer is perpendicular to the physically exposed planar (110) crystallographic plane. In this embodiment, the (110) silicon wafer may include a [1-1 0] direction (which is one of <110> direction) and a [001] direction selected from a pair of orthogonal in-plane horizontal directions. Alternatively, the (110) silicon wafer may include a [1-1 2] direction (which is one of <112> direction) and a [1-1-1] direction (which is one of <111> directions) selected from a pair of orthogonal in-plane horizontal directions. In a further alternative, the carrier substrate100may be a (111) silicon wafer, i.e., a single crystalline silicon wafer having a planar major surface including a (111) crystallographic plane so that a [111] crystallographic direction of the single crystalline material of the single crystalline silicon wafer is perpendicular to the physically exposed planar (111) crystallographic plane. In this embodiment, the (111) silicon wafer may include a [1-1 0] direction (which is one of <110> directions) and a [1 1-2] direction (which is one of <112> directions) selected from a pair of orthogonal in-plane horizontal directions. As used herein, any in-plane crystallographic direction that may be included in a set of two orthogonal in-plane crystallographic directions with lowest Miller indices (i.e., Miller indices of which the sum of absolute values of the components of the Miller indices is the lowest) for a (100) semiconductor wafer, a (110) semiconductor wafer, and a (111) semiconductor wafer is herein referred to as a “major” in-plane crystallographic direction. Thus, the major in-plane crystallographic directions of a single crystalline silicon substrate may include <100> directions, <110> directions, <111> directions, and <112> directions for the purposes of the present disclosure. An adhesion layer101may be applied to a top surface of the carrier substrate100. The adhesion layer101includes an adhesive material that may be subsequently removed after dicing an assembly of the carrier substrate100and structures attached thereupon. For example, the adhesion layer101may include a polymer material. An array of complementary die sets70may be subsequently attached to the carrier substrate100. Each complementary die (71,72,73,74) is disposed within a respective package area PA, which may be a rectangular area. Each complementary die set70includes at least one complementary die (71,72,73,74), which may be a single complementary die or a plurality of complementary dies. As used herein, a complementary die refers to any die that may be attached directly or indirectly (e.g., through an intermediate complementary die) to another die (which is referred to as a primary semiconductor die). Thus, designation of a semiconductor die as a “complementary die” does not mean that the functionality of the semiconductor die is complementary to the functionality of another die, but merely mean that the semiconductor die may be combined with an additional semiconductor die (for example, through bonding) to provide enhanced functionality. The array of complementary die sets70may be arranged on the adhesion layer101as a periodic rectangular array having a first periodicity along a first horizontal direction hd1and having a second periodicity along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. According to an embodiment of the present disclosure, the carrier substrate100may comprise a single crystalline semiconductor carrier substrate (such as a single crystalline silicon carrier substrate) and may have a planar top surface contained within a (100) plane, a (110) plane, or a (111) plane selected from the crystallographic planes of the a single crystalline semiconductor carrier substrate. In this embodiment, each of major in-plane crystallographic directions within the single crystalline semiconductor carrier substrate may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by a respective azimuthal offset angle a, which may be at least 0.5 degree, and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees. In an illustrative example, the single crystalline semiconductor carrier substrate may be a (100) substrate, a first major in-plane crystallographic direction mcd1may be a [010] direction and a second major in-plane crystallographic direction mcd2may be a [001] direction. Alternatively, a first major in-plane crystallographic direction mcd1may be a [011] direction and a second major in-plane crystallographic direction mcd2may be a [0 1-1] direction. In this embodiment, the first horizontal direction hd1and the second horizontal direction hd2may be selected such that azimuthal offset angles a from the in-plane <100> directions and the in-plane <110> directions is at least 22.5 degrees. Generally, non-zero azimuthal offset angles α between the major in-plane crystallographic directions of the carrier substrate100and the directions of periodicity in the array of complementary die set70reduces deleterious effects (such as cracking of the carrier substrate100) due to mechanical stress during subsequent packaging process (e.g., application of molding compounds and dicing) by directing the mechanical stress along a direction that is different from the major in-plane crystallographic directions of the carrier substrate100. Each complementary die (71,72,73,74) within a complementary die set70may be arranged within the area of a respective primary die to be subsequently attached to the complementary die set70. Each complementary die (71,72,73,74) within a complementary die set70may have a respective pair of lengthwise sidewalls extending along a respective lengthwise direction, and a respective pair of widthwise sidewalls extending along a respective widthwise direction that is perpendicular to the respective lengthwise direction. In one embodiment, each complementary die (71,72,73,74) may have a respective horizontal cross-sectional shape of a rectangle, a rounded rectangle, or a shape derived from a rectangle by cutting corner edges. Generally, each complementary die (71,72,73,74) may be orientated such that the lengthwise sidewalls and the widthwise sidewalls may be parallel to the first horizontal direction hd1and the second horizontal direction hd2(i.e., the directions of periodicity of the two-dimensional rectangular array of the complementary die sets70), or alternatively, at least one of the complementary die (71,72,73,74) within each complementary die set70has a lengthwise sidewall or a widthwise sidewall that is not parallel to, and is not orthogonal to, any of the first horizontal direction hd1and the second horizontal direction hd2. While the embodiment illustrated inFIG.1Adescribes a configuration in which the each complementary die (71,72,73,74) is orientated such that the lengthwise sidewalls and the widthwise sidewalls are parallel to the first horizontal direction hd1and the second horizontal direction hd2, embodiments are expressly contemplated herein (and is indeed described in a subsequent section) in which the at least one of the complementary die (71,72,73,74) within each complementary die set70has a lengthwise sidewall or a widthwise sidewall that is not parallel to, and is not orthogonal to, any of the first horizontal direction hd1and the second horizontal direction hd2. In embodiments in which a complementary die set70includes a plurality complementary dies (71,72,73,74), the plurality of complementary dies (71,72,73,74) may be arranged in a manner that does not have an areal overlap with the plurality of complementary dies (71,72,73,74). Alternatively, at least two of the plurality of complementary dies (71,72,73,74) may be stacked vertically, provided that the height of the stack remains comparable to the height of another complementary die or there is no other complementary die within the complementary die set70. In one embodiment, one of the complementary dies (71,72,73,74) may comprise a dummy complementary die74, which takes up volumes and provide mechanical support and does not provide any electrical functionality. Generally, at least one, a plurality, and/or each, of the complementary dies (71,72,73,74) may include a respective semiconductor substrate (which is herein referred to as a complementary semiconductor substrate701), a respective set of semiconductor devices (which is herein referred to as complementary semiconductor devices702), a respective set of metal interconnect structures (which is herein referred to as complementary metal interconnect structures703), a respective set of dielectric material layers (which is herein referred to as complementary dielectric material layers704), and a respective array of metal bump structures (which is herein referred to complementary metal bump structures705). According to an embodiment of the present disclosure, each of the complementary dies (71,72,73,74) may be manufactured and diced prior to placement within the two-dimensional rectangular array of the complementary die sets70such that the straight sidewalls (such as the lengthwise sidewalls and the widthwise sidewalls) of at least one, or each, of the complementary semiconductor substrates701has a respective set of major in-plane crystallographic directions that are not parallel to, and are not orthogonal to, each of the first horizontal directions hd1and the second horizontal directions hd2. In other words, each of the <100> directions, the <110> directions, the <111> directions, and the <112> directions of the single crystalline semiconductor materials of the complementary semiconductor substrates701, if present within the horizontal plane that is parallel to the planar surfaces of the complementary semiconductor substrates701contacting the adhesion layer101, is azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by a respective azimuthal offset angle, which is herein referred to as a complementary substrate crystallographic offset angle. In one embodiment, each of the complementary substrate crystallographic offset angles may be at least 0.5 degree, and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees. In an illustrative example, if a complementary semiconductor substrate701includes a (100) silicon substrate, the [010] direction of the complementary semiconductor substrate701may be azimuthally offset from the first horizontal direction hd1by 22.5 degrees clockwise and the [110] direction of the complementary semiconductor substrate701may be azimuthally offset from the first horizontal direction hd1by 22.5 degrees counterclockwise. Generally, non-zero complementary substrate crystallographic offset angles between the major in-plane crystallographic directions of the complementary semiconductor substrates701and the directions of periodicity (i.e., the first horizontal direction hd1and the second horizontal direction hd2) in the array of complementary die set70reduces deleterious effects (such as cracking of the complementary semiconductor substrates701) due to mechanical stress during subsequent packaging process (e.g., application of molding compounds and dicing) by directing the mechanical stress along a direction that is different from the major in-plane crystallographic directions of the complementary semiconductor substrates701. Generally, each of the complementary dies (71,72,73,74) may be any semiconductor die or a dummy die. In an illustrative example, one or more of the complementary dies (71,72,73,74) may include a system-on-chip (SoC) die such as an application processor die, a central processing unit die, a graphic processing unit die, or a memory die such as a high bandwidth memory (HBM) die that includes a vertical stack of static random access memory dies. In one embodiment, the complementary dies (71,72,73,74) may comprise a complementary die (herein referred to as a first complementary die) that comprises a high bandwidth memory (HBM) die including a vertical stack of static random access memory (SRAM) dies are interconnected to one another through microbumps. A continuous complementary-level molding compound layer110may be formed around the array of complementary die sets70and over the carrier substrate100. For example, an epoxy molding compound (EMC) may be applied to the gaps between the complementary dies (71,72,73,74) that are attached to the carrier substrate100. The EMC may include an epoxy-containing compound that may be hardened (i.e., cured) to provide a dielectric material portion having sufficient stiffness and mechanical strength. The EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. The EMC may be provided in a liquid form or in a solid form depending on the viscosity and flowability. Liquid EMC provides better handling, good flowability, less voids, better fill, and less flow marks. Solid EMC provides less cure shrinkage, better stand-off, and less die drift. A high filler content (such as 85% in weight) within an EMC may shorten the time in mold, lower the mold shrinkage, and reduce the mold warpage. Uniform filler size distribution in the EMC may reduce flow marks, and may enhance flowability. The curing temperature of the EMC may be lower than the release (debonding) temperature of the adhesive layer101if the adhesive layer includes a thermally debonding material. For example, the curing temperature of the EMC may be in a range from 125° C. to 150° C. The EMC may be cured at a curing temperature to form a first EMC matrix that laterally surrounds and embeds each of the complementary dies (71,72,73,74). The first EMC matrix is the continuous complementary-level molding compound layer110, which is a layer of a molding compound that continuous extends around the complementary dies, of which the level is herein referred to as a complementary level. According to an aspect of the present disclosure, each of the complementary dies (71,72,73,74) may comprise a respective array of complementary metal bump structures705. For example, if a complementary die set70includes a first complementary die71, a second complementary die72, and a third complementary die73, etc., each of the first complementary dies71comprises a respective first array of complementary metal bump structures705, each of the second complementary dies72comprises a respective second array of complementary metal bump structures705, each of the third complementary dies73comprises a respective third array of complementary metal bump structures705, etc. Each array of complementary metal bump structures705may comprise an array of metal pads or an array of copper pillar bumps. In one embodiment, at least one, or each, of the complementary dies (71,72,73,74) may comprise a rectangular periodic array of complementary metal bump structures705that are arranged with a first periodicity along a horizontal direction extending along the lengthwise sidewalls of a respective complementary die (71,72,73,74) and arranged with a second periodicity along another horizontal direction extending along the widthwise sidewalls of the respective complementary die (71,72,73,74). In embodiments in which each lengthwise sidewall and each widthwise sidewall of the complementary dies (71,72,73,74) are parallel to the first horizontal direction hd1or the second horizontal direction hd2, each rectangular periodic array of complementary metal bump structures705may have a periodicity along the first horizontal direction hd1and along the second horizonal direction hd2. An array of solder portions706may be formed on each array of complementary metal bump structures705. A continuous underfill layer, which is herein referred to as a continuous inter-mold underfill layer120, is formed around the array of solder portions706and over the continuous complementary-level molding compound layer110. Referring toFIGS.2A and2B, an array of primary semiconductor dies80may be attached to the array of complementary die sets70. As used herein, a primary semiconductor die refers to any semiconductor die to which another semiconductor die (such as a complementary semiconductor die) may be attached. Thus, designation of a semiconductor die as a “primary semiconductor die” does not mean that the functionality of the semiconductor die is primary, i.e., more important than the functionality of another die, but merely mean that the semiconductor die may be combined with an additional semiconductor die (for example, through bonding) to provide enhanced functionality. In one embodiment, the primary semiconductor die80of the present disclosure may comprise a system-on-chip (SoC) die. In an illustrative example, each primary semiconductor die80may include a semiconductor substrate (which is herein referred to as a primary semiconductor substrate801), a set of semiconductor devices (which is herein referred to as primary semiconductor devices802), a set of metal interconnect structures (which is herein referred to as primary metal interconnect structures803) that are embedded in dielectric material layers (which are herein referred to as primary dielectric material layers804). A set of through-substrate via structures805may vertically extend through the primary semiconductor substrate801. At least one set of metal bump structures, which is herein referred to as at least one set of primary metal bump structures806, may be attached to the through-substrate via structures805. Each set of primary metal bump structures806may be arranged with the same periodicity as a complementary metal bump structure705within a respective one of the complementary dies (71,72,73,74). The number of sets of primary metal bump structures806in each primary semiconductor die80may be the same as the total number of complementary dies (71,72,73,74) that are subsequently directly attached to the primary semiconductor die80. In one embodiment, the area of a primary semiconductor die80may have an areal overlap with a predominant fraction (i.e., more than 50%) of each complementary die (71,72,73,74). In one embodiment, the area of a primary semiconductor die80may have an areal overlap with more than 80%, and/or more than 90%, of each complementary die (71,72,73,74). In one embodiment, the area of a primary semiconductor die80may include the entirety of the area of a respective complementary die set70. Generally, each of the primary semiconductor dies80comprises at least one array of primary metal bump structures806, and the at least one array of primary metal bump structures806is attached to the array(s) of solder portions706within a respective package area PA. Each array of solder portions706attached to the complementary dies (71,72,73,74) may be bonded to the primary metal bump structures806. Thus, the array of primary semiconductor dies80may be bonded to the array of complementary die sets70. Each complementary die (71,72,7374) may be bonded to a respective one of the primary semiconductor dies80through an array of metal bonding structures that comprises a rectangular array of solder balls (comprising solder portions706) bonded to a respective mating pair of metal pads or a rectangular array of solder material portions bonded to a respective pair of copper pillar bumps. A continuous primary-level molding compound layer130may be formed around the array of primary semiconductor dies80and over the continuous inter-mold underfill layer120. For example, an epoxy molding compound (EMC) may be applied to the gaps between the primary semiconductor dies80. The composition of the EMC may be selected from any material composition that may be used for the continuous complementary-level molding compound layer110. The material compositions of the continuous complementary-level molding compound layer110and the continuous primary-level molding compound layer130may be the same, or may be different. In one embodiment, the continuous complementary-level molding compound layer110may be more rigid (i.e., have a higher Young's modulus) than the continuous primary-level molding compound layer130. Referring toFIGS.3A and3B, a dielectric passivation layer141, such as a silicon nitride layer or a polyimide layer, may be deposited over the primary-level molding compound layer130. The thickness of the dielectric passivation layer141may be in a range from 100 nm to 5,000 nm, although lesser and greater thicknesses may also be used. The dielectric passivation layer141may be patterned to form openings, within which bonding pads807of the primary semiconductor dies80may be physically exposed. An array of solder balls, which is herein referred to an array of packaging-substrate-side solder balls90, may be formed on each array of physically exposed bonding pads807of the primary semiconductor dies80. An underfill material layer, which is herein referred to as a packaging-substrate-side underfill material layer142, may be formed around the arrays of packaging-substrate-side solder balls90. The bonded assembly including the array of primary semiconductor dies80, the continuous primary-level molding compound layer130, the array of complementary die sets70, the continuous complementary-level molding compound layer110, and the carrier substrate100may be diced along first dicing channels DC1that are parallel to the first horizontal direction hd1, and along second dicing channels DC2that are parallel to the second horizontal direction hd2. The diced portion of the bonded assembly comprise a plurality of fan-out packages, i.e., a plurality of fan-out wafer-level packages (FOWLPs). Subsequently, diced portions of the carrier substrate100and the adhesion layer101may be removed from each of the fan-out wafer-level packages. A fan-out wafer-level package is illustrated inFIG.4after removal of the diced portions of the carrier substrate100and the adhesion layer101. Subsequently, each fan-out wafer-level package may be attached to a packaging substrate (not illustrated) using the arrays of packaging-substrate-side solder balls90. Each diced portion of the continuous complementary-level molding compound layer110constitutes a complementary-level molding compound layer110′ that laterally surrounds a complementary die set70. Each diced portion of the continuous primary-level molding compound layer130constitutes a primary-level molding compound layer130′ that laterally surrounds a primary semiconductor die80. Each diced portion of the continuous inter-mold underfill layer120constitutes an inter-mold underfill layer120′ that laterally surrounds at least one array of solder balls (comprising solder portions706), which may be a plurality of arrays of solder balls. In one embodiment, sidewalls of the complementary-level molding compound layer110′, the inter-mold underfill layer120′, and the primary-level molding compound layer130′ may be vertically coincident, i.e., may be located within a same vertical plane. Generally, the various in-plane major crystallographic directions of the carrier substrate100(in embodiments in which a single crystalline semiconductor material is present therein), the complementary semiconductor substrate(s)701of each complementary die (71,72,73,74), and the primary semiconductor substrate801of the primary semiconductor die80within a fan-out wafer-level package may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree, and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees. Further, the various in-plane major crystallographic directions of the carrier substrate100(in embodiments in which a single crystalline semiconductor material is present therein), the complementary semiconductor substrate(s)701of each complementary die (71,72,73,74), and the primary semiconductor substrate801of the primary semiconductor die80within a fan-out wafer-level package may be azimuthally offset from one another at least 0.5 degree, and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees. Referring toFIGS.5A and5B, a second exemplary structure according to a second embodiment of the present disclosure may be derived from the first exemplary structure illustrated inFIGS.1A and1Bby tilting sidewalls of at least one complement die (71,72,73) within each complementary die set70so that lengthwise sidewalls and widthwise sidewalls of the at least one complementary die (71,72,73) are not parallel to the first horizontal direction hd1and are not parallel to the second horizontal direction hd2. In other words, the sidewalls of at least one complement die (71,72,73) within each complementary die set70are tilted such that lengthwise sidewalls and widthwise sidewalls of the at least one complementary die (71,72,73) are not parallel to the directions of periodicity within the array of complementary die sets70. In one embodiment, upon attaching an array of complementary die sets70to a carrier substrate100, the array of complementary die sets70has a first periodicity along the first horizontal direction hd1and has a second periodicity along the second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. Each complementary die set70comprises a first complementary die71that has a first pair of complementary-die sidewalls laterally extending along a third horizontal direction hd3that is not parallel to the first horizontal direction hd1or the second horizontal direction hd2, and has a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction hd4that is perpendicular to the third horizontal direction hd3. The angle by which the first pair of complementary-die sidewalls of the first complementary die71is azimuthally offset from the first horizontal direction hd1is herein referred to as a first complementary die azimuthal rotation angle b1, and is greater than 0 degrees and is less than 90 degrees, and may be in a range from 0.5 degree to 89.5 degrees, such as from 1 degrees to 89 degrees, and/or from 3 degrees to 87 degrees, and/or from 5 degrees to 85 degrees, and/or from 10 degrees to 80 degrees. In one embodiment, each complementary die set70may comprise a second complementary die72that has a third pair of complementary-die sidewalls laterally extending along a fifth horizontal direction hd5that is not parallel to the first horizontal direction hd1, the second horizontal direction hd2, the third horizontal direction hd3, or the fourth horizonal direction hd4, and has a fourth pair of complementary-die sidewalls laterally extending along a sixth horizontal direction hd6that is perpendicular to the fifth horizontal direction hd5. The angle by which the third pair of complementary-die sidewalls of the second complementary die72is azimuthally offset from the first horizontal direction hd1is herein referred to as a second complementary die azimuthal rotation angle b2, and is greater than 0 degrees and is less than 90 degrees, and may be in a range from 0.5 degree to 89.5 degrees, such as from 1 degrees to 89 degrees, and/or from 3 degrees to 87 degrees, and/or from 5 degrees to 85 degrees, and/or from 10 degrees to 80 degrees. In one embodiment, each complementary die set70may comprise a third complementary die73that has a fifth pair of complementary-die sidewalls laterally extending along a seventh horizontal direction hd7that is not parallel to the first horizontal direction hd1or the second horizontal direction hd2, and has a sixth pair of complementary-die sidewalls laterally extending along an eighth horizontal direction hd8that is perpendicular to the seventh horizontal direction hd7. The angle by which the fifth pair of complementary-die sidewalls of the third complementary die73is azimuthally offset from the first horizontal direction hd1is herein referred to as a third complementary die azimuthal rotation angle β3, and is greater than 0 degrees and is less than 90 degrees, and may be in a range from 0.5 degree to 89.5 degrees, such as from 1 degrees to 89 degrees, and/or from 3 degrees to 87 degrees, and/or from 5 degrees to 85 degrees, and/or from 10 degrees to 80 degrees. In one embodiment, the first complementary die azimuthal rotation angle β1, the second complementary die azimuthal rotation angle β2, and the third complementary die azimuthal rotation angle β3may differ from one another at least by 0.5 degree. In one embodiment, the area of a primary semiconductor die80may have an areal overlap with a predominant fraction (i.e., more than 50%) of each complementary die (71,72,73). In one embodiment, the area of a primary semiconductor die80may have an areal overlap with more than 80%, and/or more than 90%, of each complementary die (71,72,73). In one embodiment, the area of a primary semiconductor die80(to be subsequently bonded to a respective complementary die set70and is illustrated with a dotted line) may include the entirety of the area of a respective complementary die set70. In other words, the entire area of each complementary die (71,72,73) overlaps within an area of the primary semiconductor die80to be subsequently bonded in a plan view (i.e., a view along the vertical direction). In one embodiment, each complementary die (71,72,73) may be laterally spaced apart without areal overlap thereamongst. Alternatively, one or more sets of at least two complementary dies (71,72,73) may be vertically stacked. As a structure derived from the first exemplary structure, the second exemplary structure may include any, each, and/or all features of the first exemplary structure ofFIGS.1A and1Bother than alignment of sidewalls of the complementary dies (71,72,73) along the first horizontal direction hd1or along the second horizontal direction hd2within the first exemplary structure ofFIGS.1A and1B. In one embodiment, the carrier substrate100may be a single crystalline semiconductor carrier substrate, and each of major in-plane crystallographic directions within the single crystalline semiconductor carrier substrate may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree. As discussed above and illustrated inFIG.1B, each of the complementary dies (71,72,73) may comprise a respective array of complementary metal bump structures705. For example, if a complementary die set70includes a first complementary die71, a second complementary die72, and a third complementary die73, etc., each of the first complementary dies71comprises a respective first array of complementary metal bump structures705, each of the second complementary dies72comprises a respective second array of complementary metal bump structures705, each of the third complementary dies73comprises a respective third array of complementary metal bump structures705, etc. Each array of complementary metal bump structures705may comprise an array of metal pads or an array of copper pillar bumps. In one embodiment, at least one, or each, of the complementary dies (71,72,73) may comprise a rectangular periodic array of complementary metal bump structures705that are arranged with a respective first periodicity along a horizontal direction extending along the lengthwise sidewalls of a respective complementary die (71,72,73) and arranged with a respective second periodicity along another horizontal direction extending along the widthwise sidewalls of the respective complementary die (71,72,73). Within the second exemplary structure illustrated inFIGS.5A and5B, each lengthwise sidewall and each widthwise sidewall of the complementary dies (71,72,73) may be independently azimuthally tiled relative to the first horizontal direction hd1and the second horizontal direction hd2. Thus, rectangular periodic array of complementary metal bump structures705of each complementary die (71,72,73) may have a periodicity along respective horizontal directions that are tilted from the first horizontal direction hd1and from the second horizonal direction hd2by a respective non-orthogonal angle. For example, each of the first complementary dies71comprises a respective first array of complementary metal bump structures705, which may be a rectangular array having a bump periodicity along the third horizontal direction hd3and another bump periodicity along the fourth horizontal direction hd4. Each of the second complementary dies72comprises a respective second array of complementary metal bump structures705, which may be a rectangular array having a bump periodicity along the fifth horizontal direction hd5and another bump periodicity along the sixth horizontal direction hd6. Each of the third complementary dies73comprises a respective third array of complementary metal bump structures705, which may be a rectangular array having a bump periodicity along the seventh horizontal direction hd7and another bump periodicity along the eighth horizontal direction hd8. In some embodiments, a complementary die (e.g., the third complementary die73) may be bonded to another complementary die (e.g., the first complementary die71) through a respective array of complementary metal bump structures (not shown), an array of solder portions (not shown), and an array of mating metal bump structures (not shown) of the other semiconductor die. An array of solder portions706may be formed on each array of complementary metal bump structures705. A continuous underfill layer, which is herein referred to as a continuous inter-mold underfill layer120, may be formed around the array of solder portions706and over the continuous complementary-level molding compound layer110. Referring toFIGS.6A and6B, an array of primary semiconductor dies80may be attached to the array of complementary die sets70. In one embodiment, the primary semiconductor die80of the present disclosure may comprise a system-on-chip (SoC) die. Each primary semiconductor die80may include a set of components illustrated inFIG.2Band described above. At least one set of primary metal bump structures806may be attached to the through-substrate via structures805. According to an aspect of the present disclosure, each set of primary metal bump structures806may be arranged with the same tilt angle with respective to the first horizontal direction hd1and with respect to the second horizontal direction hd2, and with the same periodicity, as a mating array of complementary metal bump structures705. The number of sets of primary metal bump structures806in each primary semiconductor die80may be the same as the total number of complementary dies (71,72,73) that are subsequently directly attached to the primary semiconductor die80. In one embodiment, at least one array of primary metal bump structures806may be a respective rectangular array having a respective first direction of periodicity along the horizontal direction of lengthwise sidewalls of a respective complementary die (71,72,73) and having a respective second direction of periodicity along the horizontal direction of widthwise sidewalls of the respective complementary die (71,72,73). In one embodiment, the area of a primary semiconductor die80may have an areal overlap with a predominant fraction (i.e., more than 50%) of each complementary die (71,72,73). In one embodiment, the area of a primary semiconductor die80may have an areal overlap with more than 80%, and/or more than 90%, of each complementary die (71,72,73). In one embodiment, the area of a primary semiconductor die80may include the entirety of the area of a respective complementary die set70. Generally, each of the primary semiconductor dies80comprises at least one array of primary metal bump structures806, and the at least one array of primary metal bump structures806is attached to the array(s) of solder portions706within a respective package area PA. Each array of solder portions706attached to the complementary dies (71,72,73) may be bonded to the primary metal bump structures806. Thus, the array of primary semiconductor dies80may be bonded to the array of complementary die sets70. Each complementary die (71,72,73) may be bonded to a respective one of the primary semiconductor dies80through an array of metal bonding structures that comprises a rectangular array of solder balls (comprising solder portions706) bonded to a respective mating pair of metal pads or a rectangular array of solder material portions bonded to a respective pair of copper pillar bumps. In one embodiment, each of the primary semiconductor dies80within the rectangular array of primary semiconductor dies80may comprise a first pair of primary-die sidewalls that are parallel to the first horizontal direction hd1and a second pair of primary-die sidewalls that are parallel to the second horizontal direction hd2. In one embodiment, a plurality of complementary dies (71,72,73) including a first complementary die71and a second complementary die72may be attached to a primary semiconductor die80. In one embodiment, each first complementary die71may be bonded to a respective one of the primary semiconductor dies80through an array of metal bonding structures that comprises a rectangular array of solder balls (comprising solder portions706) bonded to a respective mating pair of metal pads, or a rectangular array of solder material portions (comprising solder portions706) bonded to a respective pair of copper pillar bumps. Each rectangular array of solder balls or solder material portions used to attach the first complementary die71to the primary semiconductor die80has a bump periodicity along the third horizontal direction hd3and an additional bump periodicity along the fourth horizontal direction hd4. Each second complementary die72may be bonded to the respective one of the primary semiconductor dies80through an array of metal bonding structures that comprises a rectangular array of solder balls (comprising solder portions706) bonded to a respective mating pair of metal pads, or a rectangular array of solder material portions (comprising solder portions706) bonded to a respective pair of copper pillar bumps. Each rectangular array of solder balls or solder material portions used to attach the second complementary die72to the primary semiconductor die80has a bump periodicity along the fifth horizontal direction hd5and an additional bump periodicity along the sixth horizontal direction hd6. A continuous primary-level molding compound layer130may be formed around the array of primary semiconductor dies80and over the continuous inter-mold underfill layer120. For example, an epoxy molding compound (EMC) may be applied to the gaps between the primary semiconductor dies80. The composition of the EMC may be selected from any material composition that may be used for the continuous complementary-level molding compound layer110. The material compositions of the continuous complementary-level molding compound layer110and the continuous primary-level molding compound layer130may be the same, or may be different. In one embodiment, the continuous complementary-level molding compound layer110may be more rigid (i.e., have a higher Young's modulus) than the continuous primary-level molding compound layer130. Referring toFIG.7, a dielectric passivation layer141, an array of packaging-substrate-side solder balls90, and a packaging-substrate-side underfill material layer142(which are illustrated inFIG.3B) may be formed. The bonded assembly including the array of primary semiconductor dies80, the continuous primary-level molding compound layer130, the array of complementary die sets70, the continuous complementary-level molding compound layer110, and the carrier substrate100may be diced along first dicing channels DC1that are parallel to the first horizontal direction hd1, and along second dicing channels DC2that are parallel to the second horizontal direction hd2. The diced portion of the bonded assembly comprise a plurality of fan-out packages, i.e., a plurality of fan-out wafer-level packages (FOWLPs). Subsequently, diced portions of the carrier substrate100and the adhesion layer101may be removed from each of the fan-out wafer-level packages. A fan-out wafer-level package is illustrated inFIG.8after removal of the diced portions of the carrier substrate100and the adhesion layer101. Subsequently, each fan-out wafer-level package may be attached to a packaging substrate (not illustrated) using the arrays of packaging-substrate-side solder balls90. As illustrated inFIG.4, each diced portion of the continuous complementary-level molding compound layer110constitutes a complementary-level molding compound layer110′ that laterally surrounds a complementary die set70. Each diced portion of the continuous primary-level molding compound layer130constitutes a primary-level molding compound layer130′ that laterally surrounds a primary semiconductor die80. Each diced portion of the continuous inter-mold underfill layer120constitutes an inter-mold underfill layer120′ that laterally surrounds at least one array of solder balls (comprising solder portions706), which may be a plurality of arrays of solder balls. In one embodiment, sidewalls of the complementary-level molding compound layer110′, the inter-mold underfill layer120′, and the primary-level molding compound layer130′ may be vertically coincident, i.e., may be located within a same vertical plane. Generally, the various in-plane major crystallographic directions of the carrier substrate100(in embodiments in which a single crystalline semiconductor material is present therein), the complementary semiconductor substrate(s)701of each complementary die (71,72,73,74), and the primary semiconductor substrate801of the primary semiconductor die80within a fan-out wafer-level package may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree, and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees. Further, the various in-plane major crystallographic directions of the carrier substrate100(in embodiments in which a single crystalline semiconductor material is present therein), the complementary semiconductor substrate(s)701of each complementary die (71,72,73,74), and the primary semiconductor substrate801of the primary semiconductor die80within a fan-out wafer-level package may be azimuthally offset from one another at least 0.5 degree, and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees. Referring toFIGS.9A and9B, a third exemplary structure according to a third embodiment of the present disclosure may be derived from the second exemplary structure ofFIGS.5A and5Bby reducing the azimuthal offset angle a within the second exemplary structure ofFIGS.5A and5Bto zero, or by using a carrier substrate100that does not have any major in-plane crystallographic directions such as a carrier substrate comprising an amorphous material (such as silicon oxide or a polymer material). Other than a change in the azimuthal offset angle a to zero or replacement of a crystalline substrate material with an amorphous substrate material for the carrier substrate100, the third exemplary structure may have the same features as the second exemplary structure ofFIGS.5A and5B. Referring toFIG.10, the processing steps ofFIGS.6A and6Bmay be performed to attach a periodic array of primary semiconductor dies80having a first periodicity along the first horizontal direction hd1and having a second periodicity along the second horizontal direction hd2. The periodic array of complementary die sets70and the periodic array of primary semiconductor dies80have the same periodicity. A continuous primary-level molding compound layer130may be formed around the array of primary semiconductor dies80and over the continuous inter-mold underfill layer120. The material compositions of the continuous complementary-level molding compound layer110and the continuous primary-level molding compound layer130may be the same, or may be different. In one embodiment, the continuous complementary-level molding compound layer110may be more rigid (i.e., have a higher Young's modulus) than the continuous primary-level molding compound layer130. Referring toFIG.11, a dielectric passivation layer141, an array of packaging-substrate-side solder balls90, and a packaging-substrate-side underfill material layer142(which are illustrated inFIG.3B) may be formed. The bonded assembly including the array of primary semiconductor dies80, the continuous primary-level molding compound layer130, the array of complementary die sets70, the continuous complementary-level molding compound layer110, and the carrier substrate100may be diced along first dicing channels DC1that are parallel to the first horizontal direction hd1, and along second dicing channels DC2that are parallel to the second horizontal direction hd2. The diced portion of the bonded assembly comprise a plurality of fan-out packages, i.e., a plurality of fan-out wafer-level packages (FOWLPs). Subsequently, diced portions of the carrier substrate100and the adhesion layer101may be removed from each of the fan-out wafer-level packages. A fan-out wafer-level package is illustrated inFIG.8after removal of the diced portions of the carrier substrate100and the adhesion layer101. Subsequently, each fan-out wafer-level package may be attached to a packaging substrate (not illustrated) using the arrays of packaging-substrate-side solder balls90. Referring collectively toFIGS.1A-11, a fan-out package is provided, which may include a primary semiconductor die80that includes a primary single crystalline semiconductor substrate having a <100> crystallographic direction along a first crystallographic lattice direction and may be laterally surrounded by a primary-level molding compound layer130′, wherein the primary semiconductor die80may include a first pair of primary-die sidewalls that are parallel to a first horizontal direction hd1and a second pair of primary-die sidewalls that are parallel to a second horizontal direction hd2and perpendicular to the first horizontal direction hd1; and a first complementary die71that overlies or underlies, and is bonded to, the primary semiconductor die80, may be laterally surrounded by a complementary-level molding compound layer110′, and may include a first pair of complementary-die sidewalls laterally extending along a third horizontal direction hd3and includes a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction hd4that is perpendicular to the first pair of complementary-die sidewalls. The primary semiconductor die80may include a primary single crystalline semiconductor substrate (as embodied as a primary semiconductor substrate801) having a <100> crystallographic direction along a first crystallographic lattice direction. The first complementary die71may include a complementary single crystalline semiconductor substrate (comprising a complementary semiconductor substrates701) having a <100> crystallographic direction along a second crystallographic lattice direction. According to an aspect of the present disclosure, the fan-out package comprises at least one feature selected from: a first feature that the third horizontal direction hd3is not parallel to the first horizontal direction hd1or the second horizontal direction hd2; a second feature that the first crystallographic lattice direction is azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree; and a third feature that the second crystallographic lattice direction is azimuthally offset from the third horizontal direction hd3and from the fourth horizontal direction hd4by at least 0.5 degree. In one embodiment, the fan-out package may comprise the first feature only, the second feature only, or the third feature only. In another embodiment, the fan-out package may comprise the first feature and the second feature, the first feature and the third feature, or the second feature and the third feature. In another embodiment, the fan-out package may include the first feature, the second feature, and the third feature. In one embodiment, the third horizontal direction hd3is azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 0.5 degree to 89.5 degrees. In one embodiment, the third horizonal direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 3 degrees to 87 degrees. In one embodiment, the third horizonal direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 5 degrees to 85 degrees. In one embodiment, the third horizonal direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 3 degrees to 42 degrees or in a range from 48 degrees to 87 degrees. In one embodiment, the third horizonal direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 5 degrees to 43 degrees or in a range from 50 degrees to 85 degrees. In one embodiment, the primary single crystalline semiconductor substrate may comprises a (100) silicon substrate (i.e., a silicon substrate having a <100> direction, such as a [001] direction, as a surface normal direction), and/or the complementary single crystalline semiconductor substrate may comprises a (100) silicon substrate (i.e., a silicon substrate having a <100> direction, such as a [001] direction. In one embodiment, the first crystallographic lattice direction is azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 0.5 degree to 89.5 degrees. In one embodiment, the first crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 3 degrees to 87 degrees. In one embodiment, the first crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 5 degrees to 85 degrees. In one embodiment, the first crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 3 degrees to 42 degrees or in a range from 48 degrees to 87 degrees. In one embodiment, the first crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 5 degrees to 43 degrees or in a range from 50 degrees to 85 degrees. Alternatively or additionally, the second crystallographic lattice direction is azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 0.5 degree to 89.5 degrees. In one embodiment, the second crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 3 degrees to 87 degrees. In one embodiment, the second crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 5 degrees to 85 degrees. In one embodiment, the second crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 3 degrees to 42 degrees or in a range from 48 degrees to 87 degrees. In one embodiment, the second crystallographic lattice direction may be azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle in a range from 5 degrees to 43 degrees or in a range from 50 degrees to 85 degrees. In one embodiment, the primary-level molding compound layer130′ comprises a first pair of primary-mold sidewalls that are parallel to the first horizontal direction hd1and a second pair of primary-mold sidewalls that are parallel to the second horizontal direction hd2. The complementary-level molding compound layer110′ comprises a first pair of complementary-mold sidewalls that are parallel to the first horizontal direction hd1and a second pair of complementary-mold sidewalls that are parallel to the second horizontal direction hd2. In one embodiment, the first pair of primary-mold sidewalls and the first pair of complementary-mold sidewalls are located entirely within a pair of first vertical planes, which may be a pair of Euclidean two-dimensional planes that are perpendicular to the second horizontal direction hd2. The second pair of primary-mold sidewalls and the second pair of complementary-mold sidewalls are located entirely within a pair of second vertical plane, which may be a pair of Euclidean two-dimensional planes that are perpendicular to the first horizontal direction hd1. In one embodiment, the fan-out package comprises an inter-mold underfill layer120′ located between the primary-level molding compound layer130′ and the complementary-level molding compound layer110′ and laterally surrounding an array of metal bonding structures providing electrical connection between the primary semiconductor die80and the first complementary die71. In one embodiment, the array of metal bonding structures comprises a rectangular array of solder balls bonded to a respective mating pair of metal pads or a rectangular array of solder material portions bonded to a respective pair of copper pillar bumps; and the rectangular array of solder balls has a first periodicity along the third horizontal direction hd3and a second periodicity along the fourth horizontal direction hd4(for example, as illustrated inFIG.8). In one embodiment, the second crystallographic lattice direction may be azimuthally offset from the first crystallographic lattice direction; and the fan-out package comprises at least one feature selected from: a first additional feature that the primary-level molding compound layer130′ comprises a first pair of primary-mold sidewalls that are parallel to the first horizontal direction hd1and a second pair of primary-mold sidewalls that are parallel to the second horizontal direction hd2, and a second feature that the complementary-level molding compound layer110′ may include a first pair of complementary-mold sidewalls that are parallel to the first horizontal direction hd1and a second pair of complementary-mold sidewalls that are parallel to the second horizontal direction hd2. In one embodiment, the fan-out package comprises a second complementary die72that overlies or underlies, and is bonded to, the primary semiconductor die80, laterally surrounded by the complementary-level molding compound layer110′, laterally spaced from the first complementary die71, and comprising a third pair of complementary-die sidewalls laterally extending along a fifth horizontal direction hd5that is not parallel to the first horizontal direction hd1, the second horizontal direction hd2, the third horizontal direction hd3, or the fourth horizontal direction hd4, and comprising a fourth pair of complementary-die sidewalls laterally extending along a sixth horizontal direction hd6that is perpendicular to the fifth horizontal direction hd5. In one embodiment, the fan-out package comprises an additional complementary die (such as a third complementary die73) that overlies or underlies, and is bonded to, the first complementary die71, laterally surrounded by the complementary-level molding compound layer110′, and comprising a first additional pair of complementary-die sidewalls laterally extending along a first additional horizontal direction (such as the seventh horizontal direction hd7) that is not parallel to the first horizontal direction hd1, the second horizontal direction hd2, the third horizontal direction hd3, or the fourth horizontal direction hd4(and optionally not parallel to the fifth horizontal direction hd5and the sixth horizontal direction hd6), and comprising a second additional pair of complementary-die sidewalls laterally extending along a second additional horizontal direction (such as the eighth horizontal direction hd8) that is perpendicular to the first additional horizontal direction. In one embodiment, sidewalls of the inter-mold underfill layer120′ may be vertically coincident with the primary-mold sidewalls of the primary-level molding compound layer130′ and with the complementary-mold sidewalls of the complementary-level molding compound layer110′. In one embodiment, all major in-plane crystallographic directions of the primary semiconductor die80may be azimuthally offset at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees) from each major in-plane crystallographic direction of the complementary dies (71,72,73). Additionally or alternatively, all major in-plane crystallographic directions of the primary semiconductor die80may be azimuthally offset at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees) from each major in-plane crystallographic direction of a carrier substrate100that is used during the manufacture process in embodiments in which the carrier substrate100comprises a single crystalline material such as a single crystalline semiconductor material. Additionally or alternatively, all major in-plane crystallographic directions of the complementary semiconductor substrates701of the complementary dies (71,72,73,74) may be azimuthally offset from one another at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees). Additionally or alternatively, lengthwise sidewalls and widthwise sidewalls of the complementary semiconductor substrates701of the complementary dies (71,72,73,74) may be azimuthally offset from the directions of periodicity used during manufacture (such as the first horizontal direction hd1and the second horizontal direction hd2illustrated inFIGS.1A,1B,2A,2B,5A,5B,6A,6B,9A, and9B) at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees). Additionally or alternatively, lengthwise sidewalls and widthwise sidewalls of the complementary semiconductor substrates701of the complementary dies (71,72,73,74) may be azimuthally offset from one another at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees). While the present disclosure is described using an embodiment in which an array of complementary die sets70and an array of primary semiconductor dies80are bonded to each other, at least one additional array of additional complementary die sets (not shown) may be vertically stacked above, or below, the stack of the array of complementary die sets70and the array of primary semiconductor dies80. In this embodiment, additional complementary dies may be incorporated into each fan-out package of the present disclosure. As discussed above, the major in-plane crystallographic directions of such additional complementary dies may be azimuthally offset from the directions of periodicity used during manufacture (such as the first horizontal direction hd1and the second horizontal direction hd2illustrated inFIGS.1A,1B,2A,2B,5A,5B,6A,6B,9A, and9B) at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees). Additionally or alternatively, lengthwise sidewalls and widthwise sidewalls of complementary semiconductor substrates of such additional complementary dies may be azimuthally offset from one another, and from the horizontal directions of sidewall of the primary semiconductor die80and the complementary dies (71,72,73), at least by 0.5 degree (and/or at least 1.0 degrees, and/or at least 2 degrees, and/or at least 3 degrees, and/or at least 4 degrees, and/or at least 5 degrees, and/or at least 6 degrees, and/or at least 8 degrees, and/or at least 10 degrees). FIG.12is a first flowchart illustrating steps for forming the first or second exemplary structure according to an embodiment of the present disclosure. Referring to step1210andFIGS.1A,1B,5A, and5B, an array of complementary die sets70may be attached to a carrier substrate100(within may be a single crystalline semiconductor carrier substrate). The array of complementary die sets70has a first periodicity along a first horizontal direction hd1and has a second periodicity along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. Each complementary die set may include a first complementary die71comprising a first pair of complementary-die sidewalls laterally extending along a third horizontal direction hd3and comprising a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction hd4that is perpendicular to the third horizontal direction hd3. In some embodiments, the carrier substrate100may comprise a single crystalline semiconductor carrier substrate such as a (100) silicon substrate, and the array of complementary die sets70may be attached to the ingle crystalline semiconductor carrier substrate with an azimuthal tilt of sidewalls of the complementary dies within the complementary die sets70relative to major in-plane crystallographic directions of the single crystalline semiconductor carrier substrate100. In one embodiment, each of major in-plane crystallographic directions within the single crystalline semiconductor carrier substrate may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree. The azimuthal tilt angle between the major in-plane crystallographic directions within the single crystalline semiconductor carrier substrate and the first horizontal direction hd1may be in a range from 0.5 degree to 44.5 degrees such as from 3 degrees to 42 degrees and/or from 5 degrees to 40 degrees, or may be in a range from 45.5 degrees to 89.5 degrees such as from 48 degrees to 87 degrees and/or from 50 degrees to 85 degrees. Referring to step1220andFIGS.1A,1B,5A, and5B, a continuous complementary-level molding compound layer110may be formed around the array of complementary die sets70and over the single crystalline semiconductor carrier substrate100. Referring to step1230and FIGS.FIGS.2A,2B,6A, and6B, an array of primary semiconductor dies80may be attached to the array of complementary die sets70. Referring to step1240and FIGS.FIGS.2A,2B,6A, and6B, a continuous primary-level molding compound layer130may be formed around the array of primary semiconductor dies80. Referring to step1250andFIGS.3A,3B,4,7, and8, a bonded assembly including the array of primary semiconductor dies80, the continuous primary-level molding compound layer130, the array of complementary die sets70, the continuous complementary-level molding compound layer110, and the single crystalline semiconductor carrier substrate100may be diced into a plurality of fan-out packages by cutting the bonded assembly along first dicing channels that are parallel to the first horizontal direction hd1and along second dicing channel that are parallel to the second horizontal direction hd2. According to an aspect of the present disclosure, the method of the present disclosure as described inFIG.12may include at least one feature selected from: a first feature that the third horizontal direction hd3is not parallel to the first horizontal direction hd1or the second horizontal direction hd2; a second feature that each of the primary semiconductor dies80comprises a respective primary single crystalline semiconductor substrate, and a <100> crystallographic direction of each of the primary single crystalline semiconductor substrate is aligned along a primary <100> crystallographic lattice direction (i.e., a <100> crystallographic lattice direction of a respective primary single crystalline semiconductor substrate) that may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree (such as an azimuthal offset angle in a range from 0.5 degree to 44.5 degrees and/or from 3 degrees to 42 degrees and/or from 5 degrees to 40 degrees, or an azimuthal offset angle in a range from 45.5 degrees to 89.5 degrees and/or from 48 degrees to 87 degrees and/or from 50 degrees to 85 degrees); a third feature that each of the first complementary dies71comprises a respective complementary single crystalline semiconductor substrate, and a <100> crystallographic direction of each of the complementary single crystalline semiconductor substrates is aligned along a complementary <100> crystallographic lattice direction (i.e., a <100> crystallographic lattice direction of a respective complementary single crystalline semiconductor substrate) that may be azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by at least 0.5 degree such as an azimuthal offset angle in a range from 0.5 degree to 44.5 degrees and/or from 3 degrees to 42 degrees and/or from 5 degrees to 40 degrees, or an azimuthal offset angle in a range from 45.5 degrees to 89.5 degrees and/or from 48 degrees to 87 degrees and/or from 50 degrees to 85 degrees); and a fourth feature that the carrier substrate comprises a single crystalline carrier semiconductor substrate having a <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction hd1and from the second horizontal direction hd2by an azimuthal offset angle that is greater than 0.5 degree (such as an azimuthal offset angle in a range from 0.5 degree to 44.5 degrees and/or from 3 degrees to 42 degrees and/or from 5 degrees to 40 degrees, or an azimuthal offset angle in a range from 45.5 degrees to 89.5 degrees and/or from 48 degrees to 87 degrees and/or from 50 degrees to 85 degrees). In one embodiment, each of the primary semiconductor dies80within the array of primary semiconductor dies80may include a first pair of primary-die sidewalls that are parallel to the first horizontal direction hd1and a second pair of primary-die sidewalls that are parallel to the second horizontal direction hd2; and the method comprises a feature selected from: a first additional feature that the third horizontal direction hd3may be parallel to the first horizontal direction hd1, and the fourth horizontal direction may be parallel to the second horizontal direction hd2; and a second additional feature that the third horizontal direction hd3is azimuthally offset from the first horizontal direction hd1by an azimuthal offset angle, the fourth horizontal direction hd4may be azimuthally offset from the second horizontal direction hd2by the azimuthal offset angle, and the azimuthal offset angle is in a range from 0.5 degree to 89.5 degrees. In one embodiment, the azimuthal offset angle may be in a range from 0.5 degree to 44.5 degrees and/or from 3 degrees to 42 degrees and/or from 5 degrees to 40 degrees, or in a range from 45.5 degrees to 89.5 degrees and/or from 48 degrees to 87 degrees and/or from 50 degrees to 85 degrees). FIG.13is a second flowchart illustrating steps for forming the second or third exemplary structure according to an embodiment of the present disclosure. Referring to step1310andFIGS.5A,5B,9A, and9Band relevant portions ofFIGS.1A and1B, an array of complementary die sets70may be attached to a carrier substrate100with a tilt angle greater than 0.5 degree between sidewalls of a first complementary die71within each of the complementary die sets70relative to directions of periodicity in the array of complementary die sets70. Referring to step1320andFIGS.5A,5B,9A, and9Band relevant portions ofFIGS.1A and1B, a continuous complementary-level molding compound layer110may be formed around the array of complementary die sets70and over the carrier substrate100. Referring to step1330andFIGS.6A,6B, and10and relevant portions ofFIGS.2A and2B, an array of primary semiconductor dies80may be attached to the array of complementary die sets70. Referring to step1340andFIGS.6A,6B, and10and relevant portions ofFIGS.2A and2B, a continuous primary-level molding compound layer130may be formed around the array of primary semiconductor dies80. Referring to step1350andFIGS.7,8, and11and relevant portions ofFIGS.3A,3B, and4, a bonded assembly including the array of primary semiconductor dies80, the continuous primary-level molding compound layer130, the array of complementary die sets70, the continuous complementary-level molding compound layer110, and the carrier substrate100may be diced into a plurality of fan-out packages by cutting the bonded assembly along first dicing channels that are parallel to a first direction of periodicity of the array of complementary die sets70(such as the first horizontal direction hd1) and along second dicing channel that are parallel to a second direction of periodicity of the array of complementary die sets70(such as the second horizontal direction hd2). Generally, the non-coincidence of the various in-plane major crystallographic directions of the carrier substrate100, the complementary semiconductor substrate(s)701, and the primary semiconductor substrate801from one another and relative to the directions of periodicity in the arrays of bonded sets of a primary semiconductor die80and a complementary die set70provides the benefit of frustrating continuous stress accumulation during assembly and dicing of the primary semiconductor dies80and the complementary die sets70. Stress fractures and fragmentation during assembly and dicing processes may be avoided. The embodiments of the present disclosure may increase the stress resistance of the system-on-integrated-chip wafer and the fan-out wafer-level packages. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 81,279 |
11862611 | DETAILED DESCRIPTION Specific details of several embodiments of the present technology are described below with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure (“TTS”) conducts heat away from the stack of semiconductor dies. Additionally, the semiconductor die assembly includes molded walls composed of a molded material (e.g., epoxy, phenol formaldehyde resin, etc.). The molded walls support the thermal transfer structure as well as provide a dam for underfill material in the semiconductor die assembly. Used herein, the term “semiconductor die” generally refers to a die having integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. For example, semiconductor dies can include integrated circuit memory and/or logic circuitry. Semiconductor dies and/or other features in semiconductor die packages can be said to be in “thermal contact” with one another if the two structures can exchange energy through heat via, for example, conduction, convection, and/or radiation. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference toFIGS.1-6. As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor dies having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation. Various Embodiments of a Semiconductor Die Assembly FIG.1is a cross-sectional view illustrating a semiconductor die assembly100(“assembly100”) in accordance with embodiments of the present technology. The assembly100includes a support substrate102, a first semiconductor die104(“first die104”) mounted to the support substrate102, a plurality of second semiconductor dies106(“second die(s)106”) arranged in a stack108mounted on the first die104, and a plurality of capacitors105mounted to the substrate102. The assembly100has an underfill material110positioned between the second dies106, and between the first die104and bottom second die106. The assembly100also has molded walls115a-baround at least a portion of the stack108and a thermal transfer structure (“TTS”)116. The molded walls115a-bdefine a molded support structure that supports the TTS116and a dam that inhibits the movement of underfill material110. The molded walls115a-b(e.g., epoxy or resin) are inexpensive comp are d to metal, and can be fabricated with precision to a height nearly equal to the height of the stack108. The TTS116conducts heat away from assembly100and covers components of the assembly100. As shown inFIG.1, the support substrate102can be an interposer or printed circuit board that includes semiconductor components (e.g., doped silicon wafers or gallium arsenide wafers), nonconductive components (e.g., various ceramic substrates, such as aluminum oxide (Al2O3), etc.), aluminum nitride, and/or conductive portions (e.g., interconnecting circuitry, TSVs, etc.). Also, support substrate102can be operatively coupled to the first die104with solder balls114. In addition to or in alternative to solder balls, the first die104can be operatively coupled to the stack108with electrical connectors such as wires, vias, through-silicon vias (TSVs), conductive bumps and pillars, conductive epoxies, and/or other suitable electrically conductive elements (not shown inFIG.1). The stack108shown inFIG.1includes four second dies106electrically coupled together with electrically conductive elements such as solder balls114. In some embodiments, the electrically conductive elements can have various suitable structures, such as pillars, columns, studs, bumps, etc., and can be made from copper, nickel, solder (e.g., SnAg-based solder), conductor-filled epoxy, and/or other electrically conductive materials. For example, the electrically conductive elements can be copper pillars or bump-on-nitride structures. In other embodiments, the stack108can include more or fewer than four second dies (e.g., two, six, eight, or more dies) with electrically conductive elements between and/or connecting the second dies. The second die106located the farthest away from substrate102can be referred to as “the top second die”106, and the second die106located closest to the substrate102can be referred to as “the bottom second die”106. The assembly100can further include a plurality of capacitors105operatively coupled to the first die104and second dies106to stabilize the electronic signals passing through or coming from the second dies106, the first die104, and/or a processor (not shown inFIG.1) connected to the assembly100. Also, the plurality of capacitors105improve signal integrity because they increase capacitance for the assembly100. The assembly100can also include other electrical elements, such as diodes and/or inductors, that are operatively coupled to the support substrate102, the first die104, and the stack108. The first die104and the second dies106can include various types of semiconductor components and functional features, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, other forms of integrated circuit memory, processing circuits, imaging components, and/or other semiconductor features. In various embodiments, for example, the assembly100is a hybrid memory cube (HMC) in which the stacked second dies106are DRAM dies or other memory dies that provide data storage and the first die104is a high-speed logic die that provides memory control (e.g., DRAM control) within the HMC. In addition, the assembly100includes underfill material110between each of the second dies106. The underfill material110is typically a flowable material that fills the interstitial spaces between the second dies106. The underfill material110can be a nonconductive epoxy paste (e.g., XS8448-171 manufactured by Namics Corporation of Niigata, Japan), a capillary underfill, a nonconductive film, and/or it can include other suitable electrically insulative materials. The underfill material110can alternatively be a dielectric underfill, such as FP4585 manufactured by Henkel of Dusseldorf, Germany. In some embodiments, the underfill material110can be selected based on its thermal conductivity to enhance heat dissipation through the stack108. As shown inFIG.1, underfill material110can be injected into the region between the molded walls115a-band the stack108. The underfill material110typically flows into the gap between the first die104and the bottom second die106and the gaps between the second dies106in the stack108. Although not shown inFIG.1, the amount of underfill material110injected into the assembly100may be based on desired coverage of underfill material for the first die104and second dies106. Because underfill material110is viscous, it can move (e.g., when heated up), and the molded walls115a-bact as a dam to inhibit movement of underfill material110. The TTS116transfers heat away from the first die104and the stack108. The TTS116is also known as “heat spreader,” “lid,” or “thermal lid”. The TTS116can be composed of copper (Cu), nickel (Ni), another metal with relatively high thermal conductivity, and/or any combination thereof. In some embodiments, the composition (e.g., percentage Cu or Ni) of the TTS116is varied to decrease the cost of producing the TTS116or to increase (e.g., optimize) the thermal transfer coefficient of the TTS116. For example, the TTS116can be composed of 55% copper and 45% nickel. Accordingly, the TTS116covers, encloses, and otherwise protects the stack108. Also as shown inFIG.1, the TTS116is relatively long and flat, increasing contact between the components of the assembly100and the providing a large thermally conductive surface area to better dissipate heat from the assembly100. The TTS116is attached to the molded wall115a-bby an adhesive120. The molded walls115a-bcan be composed of epoxy, phenol formaldehyde resin, or another moldable compound with relatively good heat transfer properties. In general, the molded walls115a-bsupport the TTS116and function as a dam for the underfill material110. In some embodiments, a high-conductivity mold material can also be used to fabricate molded walls to enhance heat dissipation from the first die104and the stack108. Additionally, the molded walls115a-bcan also include phenolic hardeners, silicas, pigments, and catalysts to accelerate cure reactions when fabricating the molded walls115a-b. Also as shown inFIG.1, the molded walls115a-bhave a recessed surface to enclose the plurality of capacitors105. In general, the molded walls115a-bare composed of a non-metal to reduce cost and enable molding of the walls115a-baround the first and second dies104and106and over the capacitors105. There are several expected advantages to the molded walls115a-bcompared to an all-metal enclosure. The molded walls115a-bcan reduce the cost of manufacturing the assembly100because mold material is less expensive than metal. Additionally, it is easier to fabricate the molded walls115a-bto encapsulate the plurality of capacitors105as compared to etching and/or shaping metal to cover the capacitors. Also, adding molding around the capacitors increases the thickness of the molded walls115a-b, which provides additional structural support to the TTS116. Additionally, the molded walls115a-benable higher stacks (e.g., more dies) because the dam effect enables underfill material to easily cover upper dies in large stacks (e.g., four or more dies). Overall, molded walls have tight dimensional tolerances, good reliability, and high yield. Other advantages will become apparent to those having ordinary skill in the art based on this disclosure. Also, all of the advantages of the present technology may not be included in all embodiments described below. To attach the TTS116to the assembly100, the adhesive120is applied. Adhesive120can be a thermal interface material (“TIM”) or another adhesive including a silicone-based grease, gel, or adhesive that is doped with conductive materials (e.g., carbon nanotubes, solder materials, diamond-like carbon, etc.). In some implementations, the adhesive120can include phase-change materials. As shown inFIG.1, the first die104includes peripheral regions112(also referred to as the “porch” or “shelf”) that extend laterally outboard of the other dies in stack108. The peripheral regions112are defined by the relative dimensions of the first die104and the position of the stack108. In the embodiment illustrated inFIG.1, the stack108is centered with respect to the length of the first die104such that the peripheral regions112extend laterally beyond two opposing sides of the stack108. For example, if the length of the first die104is approximately 1.0 mm greater than the length of the second dies106, the peripheral regions112will extend about 0.5 mm beyond either side of the centered second dies106. In other embodiments, the stack108may be offset with respect to the center of the support substrate102. In further embodiments, the first die104and the second dies106can be circular, and therefore the relative diameters of the first and second dies104and106define the peripheral regions112. Also, the first die104and second dies106can be rectangular, circular, and/or other suitable shapes and may have various different dimensions. The first die104can have a length of about 12-13 mm (e.g., 12.67 mm) and a width of about 8-9 mm (e.g., 8.5 mm, 8.6 mm, etc.). For example, the individual second dies106can each have a length of about 10-11 mm (e.g., 10.7 mm) and a width of about 8-9 mm (e.g., 8.6 mm, 8.7 mm). In other embodiments, the first and second dies can have other suitable dimensions and/or the individual second dies106may have different dimensions from one another. Although not shown inFIG.1, the first die104and second dies106may be the same size, resulting in no peripheral region112, or the second dies106may be shifted to change the size of the peripheral regions112. Method of Manufacturing a Semiconductor Die Assembly FIGS.2A-2Billustrate aspects of a method of manufacturing the assembly100as shown inFIG.1. InFIG.2A, the plurality of capacitors105are electrically coupled to the support substrate102. The plurality of capacitors105can undergo a reflow process to be electronically coupled to the substrate102. After the plurality of capacitors105are electronically coupled to the substrate102, the molded walls115a-bare formed on the substrate102to encapsulate the plurality of capacitors105and form a cavity117. In some embodiments, an encapsulation or packaging tool is used to attach the molded walls115a-bto the plurality of capacitors105and the substrate102. Alternatively, a molding machine can be used to fabricate molded walls115a-bdirectly on the substrate102. Overall, the height of the molded walls115a-bcan be determined with precision and at a low cost because mold material is generally easy to shape and is less expensive than other materials such as metal. As shown inFIG.2B, after the molded walls115a-bare attached, the first die104is attached to the substrate112by solder balls114and the second dies106are then stacked over the first die104. The dies104and106are placed in the cavity117formed by the molded walls115a-b. FIG.2Cis a top view of the semiconductor die assembly shown inFIG.2B. As shown from the top view, the molded walls115a-bprovide support in a rectangular shape that extends around the complete perimeter of the stack108. In other embodiments, the molded walls115a-bextend around only a portion of the perimeter of the stack108. In some embodiments, molded walls115a-bare relatively thick because the plurality of capacitors105are encapsulated in the molded walls115a-b. Thick molded walls115a-benable increased contact with the TTS116, which in turn increases structural support. FIG.2Dis a side cross-sectional view showing the assembly after the underfill material110has been injecting into the cavity117(FIG.2C) between the molded wall115a-band the first and second dies104and106. In this embodiment, the underfill material110covers the peripheral region112(FIG.1) of the first die104and fills the space between the molded walls115a-band the first and second dies104and106. The underfill material110also flows between the dies104and106via capillary action to fill the gaps between the dies. As described above, the molded wall115a-bprovide a dam that restricts the lateral flow of the underfill material110. In the embodiment shown inFIG.2D, the top surface of the underfill material110can be co-planar with the top surface of the top second die106, but in other embodiments the top surface of the underfill material110can have a different height either above or below the top surface of the top second die106. After injecting the underfill material110into the cavity117, the TTS116(FIG.1) can be attached to form the assembly100shown inFIG.1. The TTS116can be attached to the top surface of the molded walls115a-b, the top surface of the top second die106and the top surface of the underfill material110by an adhesive. In some embodiments, the assembly can be heated (e.g., baked) to strengthen the adhesion of the adhesive120to the molded walls115a-band to the top surface of the second dies106. The adhesive can be a thermal interface material having high thermal conductivity. Additional Various Embodiments of a Semiconductor Die Assembly FIG.3is a cross-sectional view of a semiconductor die assembly (“assembly300”) configured in accordance with embodiments of the present technology. The assembly300has generally the same components as the assembly100ofFIG.1except the assembly300includes a thermal transfer structure (TTS)316with a different configuration compared to the TTS116ofFIG.1. The embodiment of the TTS316shown inFIG.3has a first portion322and a second portion324. The first portion322extends in a first direction (e.g., horizontally as shown inFIG.1) at least generally parallel to the first die104and the support substrate102. The second portion324can be defined by two panels that extend from the first portion322in a second direction (e.g., vertically as shown inFIG.1) toward the first die104and the support substrate102. The TTS316can be made from a material having a high thermal conductivity, such as copper, aluminum, other metals, or silicon. The bottom surface of the second portion324is attached to the peripheral region112of the first die104by an adhesive120, such as a TIM, to provide good thermal conduction from the first die104to the second portion324of the TTS316. As shown inFIG.3, the TTS316conducts a relatively high amount of heat away from the first die104. For example, the first die104can be a logic die. Logic dies typically operate at a higher power level than memory dies (e.g., 5.24 W compared to 0.628 W, respectively). As a result of operating at a high power, the logic die configuration generally concentrates a significant amount of heat at the peripheral regions112of the first die104. The logic die may also have a higher power density at the peripheral regions112, resulting in further concentration of heat and higher temperatures at the peripheral regions112. As such, by coupling a large percentage of the peripheral regions112of the first die104to the highly conductive (e.g., metal) second portion324of the TTS316, the heat can be efficiently removed from the peripheral regions112of the first die104and from the stack108. Various Embodiments of a Thermal Transfer Structure (TTS) FIG.4Ais a cross-sectional view of an embodiment of the TTS316shown inFIG.3having a plurality of holes405through one of the panels of the second portion324. As shown inFIG.4A, the holes405(also referred to as “passages”) can be drilled or stamped through second portion324of the TTS316. The holes405provide a passage through which underfill material110can flow. For example, as underfill material110is injected into the cavity (FIG.3), some of the underfill material110can flow through the holes405and into the space between the stack108and the second portion324. The underfill material110within the second portion324can then fill the gaps between the dies. FIG.4Bshows an alternative embodiment of a TTS416that can have a similar composition to the TTS316shown inFIG.4A, but a different configuration. In particular, the second portion324of the TTS416includes fins415a,415b, and415cseparated by passages417. The fins415a,415b, and415ccan be formed by cutting or stamping the TTS416before it is positioned in an assembly. The passages417enable underfill material to flow through the second portion324and between the second dies106of the stack108. The fins415a,415b, and415ctransfer heat from the peripheral region of the first die104and from the stack108. The width and size of the fins415a-ccan be increased or decreased based on design specifications (e.g., cost of material, desired heat transfer properties such as increasing surface contact of the TTS with the stack108). FIG.5is a cross-sectional view of a semiconductor die assembly500having the TTS316(FIG.4A) attached to the molded walls115a-b, the first die104and the top second die106.FIG.5further illustrates that the TTS316includes an inlet501and a vent502for filling the cavity117and the gaps between the dies with underfill material110. The underfill material110is injected into the cavity117through inlet501. As the underfill material110fills the cavity117, a portion of the underfill material flows through holes405(e.g., passages) and into the space between the stack108of second semiconductor dies106and the second portion324of the TTS316. The underfill material further fills the gap between the first die104and the bottom second die106as well as the gaps between the second semiconductor dies106. As the underfill materials the cavity117, air is displaced through the vent502. Although not shown inFIG.5, the TTS416(FIG.4B) can also have an inlet and an outlet to inject the underfill material110into the cavity117and between the dies. FIG.6is a cross-sectional view of a semiconductor die assembly configured in accordance with embodiments of the present technology. Similar to assembly100inFIG.1, the assembly600inFIG.6includes a support substrate102, a first die104mounted to the support substrate102, a plurality of second dies106arranged in a stack108, underfill material110between the dies, and a plurality of capacitors105. In contrast to the assembly100inFIG.1, the assembly600includes a molded wall605that covers the capacitors105and the peripheral region112of the first die. The molded wall605defines a cavity617that is smaller than the first die104and configured to receive the stack108of second dies106such that a small gap exists between the molded wall605and the sides of the stack108of second dies106. The molded wall605may be comprised of epoxy, phenol formaldehyde resin, or another moldable compound with relatively good heat transfer properties. When the molded wall is made from a dielectric material having a high thermal conductivity, one expected advantage of the molded wall605is that it provides an inexpensive was to dissipate heat away from the first die104and the stack108. The cavity617and spaces between the second dies106is filled with the underfill material110, and the TTS116can be attached to the molded wall605and the top second die106with an adhesive120, such as a TIM. Any one of the stacked semiconductor die assemblies described above with reference toFIGS.1-6can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system700shown schematically inFIG.7. The system700can include a semiconductor die assembly705, a power source710, a driver715, a processor720, and/or other subsystems or components725. The semiconductor die assembly705can include features generally similar to those of the stacked semiconductor die assemblies described above. The resulting system700can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems700can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, and appliances. Components of the system700may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system700can also include remote devices and any of a wide variety of computer readable media. CONCLUSION From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, although many of the embodiments of the semiconductor die assemblies are described with respect to HMCs, in other embodiments the semiconductor die assemblies can be configured as other memory devices or other types of stacked die assemblies. In addition, the semiconductor die assemblies illustrated inFIGS.1-6include a plurality of first semiconductor dies arranged in a stack on the second semiconductor die. In other embodiments, however, the semiconductor die assemblies can include one first semiconductor die stacked on one or more of the second semiconductor dies. Certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein. | 24,710 |
11862612 | DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some embodiments, an integrated passive device (IPD) comprises a single monolithic semiconductor substrate and a trench capacitor embedded in the substrate. The trench capacitor comprises a plurality of capacitor electrodes and a plurality of capacitor dielectric layers. The capacitor electrodes and the capacitor dielectric layers are alternatingly stacked and define a trench segment extending or protruding into the substrate. Further, the capacitor electrodes are alternatingly and electrically coupled to a first terminal of the trench capacitor and a second terminal of the trench capacitor by wires and vias. The IPD may be used for, among other things, mobile devices and access processors. Mobile devices and access processors continuously seek to scale down. As such, mobile devices and access processors continuously seek smaller and smaller IPDs. To decrease the size of the IPD, the size of the trench capacitor may be decreased by increasing the capacitance density of the trench capacitor. The capacitance density corresponds to capacitance per unit area in a two-dimensional (2D) projection of the trench capacitor onto a horizontal or XY plane (e.g., a footprint of the trench capacitor). Capacitance density may be increased by increasing the depth of the trench segment (e.g., how deep the trench segment extends into the substrate) in a vertical or Z dimension. However, semiconductor manufacturing processes used to form the IPD may limit the depth and may hence limit the capacitance density. Increasing the depth of the trench segment increases an aspect ratio of the trench segment (e.g., a ratio of height to width) and hence increases an aspect ratio of a trench within which the trench segment is formed. At high aspect ratios, material may cluster around top corners of the trench during deposition of layers from which the trench segment is formed. This phenomenon may be known as trench necking. The clustering may pinch off a top of the trench before the deposition completes. As such, a void may form in the trench. Further, some layers from which the trench segment is formed may be restricted to a top of the trench, which may decrease electrode surface area and may hence decrease the capacitor density. Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor for IPDs, as well as a method for forming the 3D trench capacitor. In some embodiments, a semiconductor structure in which the 3D trench capacitor is arranged includes a first IC die, a second IC die, and a pair of through substrate vias (TSVs). The first IC die includes a first substrate, a first interconnect structure underlying the first substrate, and a first trench capacitor. The first trench capacitor extends into the first substrate and is between the first substrate and the first interconnect structure. The second IC die is under and directly bonded to the first IC die. Further, the second IC die includes a second substrate, a second interconnect structure overlying the second substrate, and a second trench capacitor. The second trench capacitor extends into the second substrate and is between the second substrate and the second interconnect structure. The first and second trench capacitors collectively define the 3D trench capacitor. The TSVs extend through the first substrate and are electrically coupled to the first and second trench capacitors by the first and second interconnect structures. The bonding may space the first and second trench capacitors in a vertical or Z dimension. As such, a two-dimensional projection of the 3D trench capacitor onto a horizontal or XY plane may occupy a small area. In other words, the 3D trench capacitor may have a small footprint. Further, the bonding and/or the TSVs may electrically couple the first and second trench capacitors in parallel so a capacitance of the 3D trench capacitor is a sum of the individual capacitances of the first and second trench capacitors. Because the capacitance of the 3D trench capacitor may be a sum of the capacitances of multiple trench capacitors, the 3D trench capacitor may have a high capacitance. As a result of the high capacitance and the small footprint, the 3D trench capacitor may have a high capacitance density. That is to say, a capacitance per unit area in the footprint of the 3D trench capacitor may be high. With reference toFIG.1, a cross-sectional view100of some embodiments of a semiconductor structure is provided in which a 3D trench capacitor102is arranged. The semiconductor structure may, for example, be an integrated circuit (IC), an IPD, or some other suitable semiconductor structure. The 3D trench capacitor102comprises a plurality of trench segments104spread across a plurality of IC dies106, and the IC dies106are hybrid bonded together at a front side bond interface108. The front side bond interface108includes both a metal-to-metal bond and a dielectric-to-dielectric. The plurality of IC dies106comprises a first IC die106aand a second IC die106bunderlying the first IC die106a. The IC dies106comprise corresponding substrates110, corresponding device layers112, and corresponding interconnect structures114. The device layers112and the interconnect structures114are respectively on front sides116of the substrates110. The substrates110may, for example, be bulk monocrystalline silicon substrates or some other suitable semiconductor substrates. The device layers112are levels of devices in a vertical or Z dimension. The interconnect structures114directly contact at the front side bond interface108and surround and electrically couple to the device layers112. The interconnect structures114comprise corresponding interconnect dielectric layers118, corresponding wires120, and corresponding vias122. The wires120and the vias122are alternatingly stacked in the interconnect dielectric layers118to define conductive paths from the trench segments104to the front side bond interface108. The interconnect dielectric layers118may be or comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, a low k dielectric, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the interconnect dielectric layers118are or comprise silicon oxide and/or silicon oxynitride at the front side bond interface108. Other suitable dielectric(s) are, however, amenable. The wires120and the vias122may be or comprise, for example, metal and/or some other suitable conductive material(s). The trench segments104are spread across the device layers112. Further, the trench segments104extend or protrude respectively into the front sides116of the substrates110respectively towards back sides124of the substrates110. The trench segments104individually define two-dimensional (2D) trench capacitors126. A 2D trench capacitor is a trench capacitor limited to a single device layer, whereas a 3D trench capacitor is a trench capacitor spanning multiple device layers. The 2D trench capacitors126are electrically coupled in parallel by the wires120and the vias122, such that a capacitance of the 3D trench capacitor102is a sum of the capacitances of the 2D trench capacitors126. Because the trench segments104are spread across multiple device layers (e.g., the device layers112of the first and second IC dies106a,106b) in the vertical or Z dimension, a 2D projection of the 3D trench capacitor102onto a horizontal or XY plane may occupy a small area. In other words, the 3D trench capacitor102may have a small footprint. Further, because the capacitance of the 3D trench capacitor102is a sum of the capacitances of multiple 2D trench capacitors (e.g., the sum of the capacitances of the 2D trench capacitors126), the 3D trench capacitor102may have a high capacitance. As a result of the high capacitance and the small footprint, the 3D trench capacitor102may have a high capacitance density. That is to say, a capacitance per unit area in the footprint of the 3D trench capacitor102may be high. In some embodiments, the 3D trench capacitor102has a capacitance density that is about 30% or more higher, about 50% or more higher, or some other suitable percentage higher than a maximum capacitance density for a 2D trench capacitor. In some embodiments, a maximum capacitance density for a 2D trench capacitor is about 850 nanofarad, about 1100 nanofarad, or some other suitable value. With continued reference toFIG.1, the trench segments104are defined by corresponding capacitor electrodes128and corresponding capacitor dielectric layers130. The capacitor electrodes128are alternatingly stacked with the capacitor dielectric layers130, such that the capacitor dielectric layers130separate the capacitor electrodes128from each other and from the substrates110. The capacitor electrodes128may be or comprise, for example, metal, doped polysilicon, some other suitable conductive material(s), or any combination of the foregoing. The capacitor dielectric layers130may be or comprise, for example, silicon oxide, a high k dielectric, some other suitable dielectric(s), or any combination of the foregoing. Notwithstanding that the trench segments104are illustrated as each being defined by two capacitor electrodes and two capacitor dielectric layers, additional capacitor electrodes and/or additional capacitor dielectric layers are amenable. Further, notwithstanding that four trench segments are illustrated, more or less trench segments are amenable. For example, there may be three trench segments on each of the IC dies106. Further yet, notwithstanding that the IC dies106have the same number of trench segments, different numbers of trench segments are amenable. For example, the first IC die106amay have three trench segments, whereas the second IC die106bmay have two or four trench segments. TSVs132extend through the substrate110of the first IC die106a(e.g., the first substrate110a) to TSV wires120ain the interconnect structure114of the first IC die106a(e.g., the first interconnect structure114a). While not fully visible, the TSV wires120aelectrically couple the TSVs132to a remainder of the wires120and a remainder of the vias122, which electrically couple the TSV wires120a(and hence the TSVs132) respectively to terminals of the 3D trench capacitor102. In some embodiments, the TSVs132are electrically coupled to the 2D trench capacitors126of the second IC die106band/or the 2D trench capacitors of the first IC die106aonly through the TSV wires120a. The TSVs132respectively provide access to a first terminal T1of the 3D trench capacitor102and a second terminal T2of the 3D trench capacitor102from the back side124of the first substrate110a. The TSVs132are separated from the first substrate110aby corresponding TSV dielectric layers134and may be or comprise, for example, metal and/or some other suitable conductive material(s). The TSV dielectric layers134may be or comprise, for example, silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. The first and second terminals T1, T2of the 3D trench capacitor102may respectively be an anode of the 3D trench capacitor102and a cathode of the 3D trench capacitor102or vice versa. In some embodiments, the first and second terminals T1, T2are respectively and electrically coupled to a power supply voltage (e.g., VDD) and ground, or vice versa, during use of the 3D trench capacitor102. In other embodiments, the first and second terminals T1, T2are electrically coupled to some other suitable voltages. The trench segments104of the first IC die106ahave a first depth D1, and the trench segments104of the second IC die106bhave a second depth D2. A portion of the first depth D1is in the first interconnect structure114aand a remainder of the first depth D1is in the first substrate110a. Further, the second depth D2is wholly or substantially in the substrate110of the second IC die106b(e.g., the second substrate110b). As such, the trench segments104of the first IC die106alaterally contact the first interconnect structure114a, whereas the trench segments104of the second IC die106bdo not laterally contact the interconnect structure114of the second IC die106b(e.g., the second interconnect structure114b). In some embodiments, the interconnect dielectric layer118of the first interconnect structure114ais or comprises silicon oxide and/or some other suitable oxide(s) at the trench segments104of the first IC die106a. Other suitable dielectric(s) is/are, however, amenable. Because a portion of the first depth D1is in the first interconnect structure114a, the first depth D1may be larger than it would be if wholly or substantially in the first substrate110a. As such, the 2D trench capacitors126of the first IC die106amay have larger capacitances than they would otherwise have. Further, because the TSVs132are formed in the first substrate110a, process limits (discussed in detail hereafter) while forming the TSVs132may limit a thickness Tfsof the first substrate110ato a small value. For example, the first thickness Tfsmay be small relative to a second thickness Tssof the second substrate110b. Therefore, if the first depth D1was wholly or substantially in the first substrate110a, the first depth D1may be small. However, because a portion of the first depth D1is in first interconnect structure114a, the negative effects from the small thickness are mitigated and the 2D trench capacitors126may have high capacitances. For example, the first depth D1may be the same as or larger than the second depth D2and/or the 2D trench capacitors126of the first IC die106amay have the same or larger capacitances as the 2D trench capacitors126of the second IC die106b. In some embodiments, the first depth D1is about 4 micrometers or less, about 6 micrometers or less, about 8 micrometers or less, about 4-8 micrometers, or some other suitable value. In some embodiments, the second depth D2is about 4 micrometers or less, about 6 micrometers or less, about 4-6 micrometers, or some other suitable value. If the first and second depths D1, D2are too low (e.g., less than about 4 micrometers or some other suitable value), the capacitances of the 2D trench capacitors126may be low and hence the capacitance density of the 3D trench capacitor102may be low. If the first and second depths D1, D2are too high (e.g., greater than about 6 micrometers, 8 micrometers, or some other suitable value), aspect ratios of trenches within which the trench segments104are formed may be high. In some embodiments, the portion of the first depth D1in the first interconnect structure114ais about equal to, or within about 5 percent, 10 percent, 20 percent, or some other suitable percentage of, a difference between the first and second thicknesses Tfs, Tss. In some embodiments, the portion of the first depth D1in the first interconnect structure114ais 20-60 percent, about 20-40 percent, about 40-60 percent, or some other suitable percentage of the first depth D1. If the portion of the first depth D1in the first interconnect structure114amakes up too small a percentage of the first depth D1(e.g., less than about 20 percent or some other suitable value), increased manufacturing costs may not outweigh the benefit from increased capacitance. At high aspect ratios, material may cluster around top corners of the trenches during deposition of layers from which the trench segments104are formed. This phenomenon may be known as trench necking. The clustering may pinch off tops of the trenches before the deposition completes. As such, voids may form in the trenches. Further, some layers from which the trench segments104are formed may be restricted to tops of the trenches, which may decrease electrode surface area and may hence decrease the capacitor density. With reference toFIG.2, a top layout200of some embodiments of the TSV wires120aofFIG.1is provided. Additionally, for illustrative purposes, the TSVs132, the 2D trench capacitors126, and some of the vias122are shown in phantom. The top layout200ofFIG.2may, for example, be taken along line A-A′ inFIG.1and/or the cross-sectional view100ofFIG.1may, for example, be taken along line B-B′ inFIG.2. The TSV wires120ainclude corresponding fingers202that are interdigitated. In some embodiments, the TSV wires120aare mirror images of each other. The TSV wires120adirectly and respectively contact the TSVs132and some of the vias122respectively at the fingers202to electrically couple the TSVs132respectively to the vias. The wires120, including the TSV wires120a, and the vias122define conductive paths leading from the TSVs132respectively to terminals of the 2D trench capacitors126to electrically couple the 2D trench capacitors126to the TSVs132. Further, as noted above, the wires120and the vias122electrically couple the 2D trench capacitors126in parallel with each other. Notwithstanding the specific top layouts shown for the TSV wires120a, the 2D trench capacitors126, the TSVs132, and some of the vias122, it is to be appreciated that other top layouts are amenable. With reference toFIG.3, a circuit diagram300of some embodiments of the 3D trench capacitor102ofFIG.1is provided. The 2D trench capacitors126are electrically coupled in parallel from the first terminal T1of the 3D trench capacitor102to the second terminal T2of the 3D trench capacitor102. Further, the 2D trench capacitors126are grouped by IC die. With reference toFIG.4A, a cross-sectional view400A of some alternative embodiments of the semiconductor structure ofFIG.1is provided in which the first and second thicknesses Tfs, Tssrespectively of the first and second substrates110a,110bare the same or substantially the same. Further, the first depth D1is greater than the second depth D2. With reference toFIG.4B, a cross-sectional view400B of some alternative embodiments of the semiconductor structure ofFIG.1is provided in which a portion of the second depth D2is in the second interconnect structure114b. As such, the trench segments104of the second IC die106blaterally contact the second interconnect structure114b. Because a portion of the first depth D2is in the second interconnect structure114b, the second depth D2may be larger than it would be if wholly or substantially in the second substrate110b. As such, the 2D trench capacitors126of the second IC die106bmay have larger capacitances. With reference toFIG.4C, a cross-sectional view400C of some alternative embodiments of the semiconductor structure ofFIG.1is provided in which the first depth D1is wholly or substantially in the first substrate110a. Further, a portion of the second depth D2is in the second interconnect structure114b. As such, the trench segments104of the second IC die106blaterally contact the second interconnect structure114b, but the trench segments104of the first IC die106ado not laterally contact the first interconnect structure114a. With reference toFIG.4D, a cross-sectional view400D of some alternative embodiments of the semiconductor structure ofFIG.1is provided in which the first depth D1is wholly or substantially in the first substrate110a. As such, the trench segments104of the first IC die106ado not laterally contact the first interconnect structure114a. With reference toFIG.4E, a cross-sectional view400E of some alternative embodiments of the semiconductor structure ofFIG.4Dis provided in which some of the capacitor dielectric layers130are omitted and some of the capacitor electrodes128are omitted. Further, the 2D trench capacitors126have corresponding well regions402in the substrates110. The well regions402are doped regions of the substrates110that line the trench segments104and that serve as capacitor electrodes. In some embodiments, the well regions402have opposite doping types (e.g., p-type vs. n-type) as adjoining regions of the substrates110. The well regions402may also be known as substrate-type capacitor electrodes, whereas the capacitor electrodes128may also be known as in-trench-type capacitor electrodes. WhileFIGS.1and4A-4Dare not illustrated with the well regions402ofFIG.4E, it is to be appreciated that alternative embodiments ofFIGS.1and4A-4Dmay include the well regions402. Further, while the top layout200ofFIG.2is described with regard to the cross-sectional view100ofFIG.1, the top layout200is applicable to the cross-sectional views400A-400E ofFIGS.4A-4E. In other words, the top layout200ofFIG.2may alternatively be taken along line A-A′ in any one ofFIGS.4A-4Eand/or the cross-sectional views400A-400E ofFIGS.4A-4Emay alternatively be taken along line B-B′ inFIG.2. With reference toFIG.5A, a cross-sectional view500A of some alternative embodiments of the semiconductor structure ofFIG.1is provided in which there is a one-to-many correspondence between the 2D trench capacitors126and the trench segments104. Additionally, the 2D trench capacitors126are defined by more capacitor electrodes and more capacitor dielectric layers than inFIG.1. The capacitor electrodes128and the capacitor dielectric layers130are alternatingly and vertically stacked with widths decreasing towards the interconnect structures114. Further, the capacitor electrodes128are electrically coupled so each of the 2D trench capacitors126may be modeled as multiple capacitors (e.g., a capacitor for each pair of neighboring capacitor electrodes) electrically coupled in parallel. The increased number of capacitor electrodes may, for example, increase capacitances of the 2D trench capacitors126and may hence increase a capacitance density of the 3D trench capacitor102. Sidewall spacers502are respectively on sidewalls of the capacitor electrodes128. First capping layers504are between the substrates110protrude respectively into the 2D trench segments104. Second capping layers506are between and respectively on the first capping layers504. The sidewall spacers502may be or comprise, for example, silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. The first capping layers504may be or comprise, for example, silicon oxide, metal, some other suitable material(s), or any combination of the foregoing. The second capping layers506may be or comprise, for example, silicon nitride and/or some other suitable dielectric(s). First etch stop layers (ESLs)508and second ESLs510are between the substrates110and are between the 2D trench capacitors126. The first ESLs508respectively cover the substrates110and respectively cover the 2D trench capacitors126on the front sides116of the substrates110. The second ESLs510respectively cover the first ESLs508on the front sides116of the substrates110. The first ESLs508may be or comprise, for example, silicon oxide and/or some other suitable dielectric(s). The second ESLs510may be or comprise, for example, silicon nitride and/or some other suitable dielectric(s). With reference toFIG.5B, a cross-sectional view500B of some alternative embodiments of the semiconductor structure ofFIG.5Ais provided in which the 2D trench capacitors126are limited to a single trench segment. Further, capacitor dielectric layers130aat the substrates110blanket the substrates110and have greater thicknesses than a remainder of the capacitor dielectric layers130. Further yet, the sidewall spacers502and the second capping layer506are omitted and gaps512are at the trench segments104due to high aspect of the trench segments104. In alternative embodiments, the semiconductor structure may include the sidewall spacers502as inFIG.5Aand/or may include the second capping layer506as inFIG.5A. In alternative embodiments, the gaps512may be omitted. While the trench segments104ofFIGS.5A and5Bare wholly or substantially in the substrates110, respectively, one, some, or all of the trench segments104may be partially in the interconnect structures114, respectively, as inFIGS.1and4A-4C. For example, the trench segments104of the first IC die104amay be partially in the first interconnect structure114aas inFIG.1in alternative embodiments ofFIGS.5A and5B. With reference toFIG.6, a top layout600of some embodiments of the TSV wires120aofFIG.5Ais provided. Additionally, for illustrative purposes, the TSVs132, the 2D trench capacitors126, and some of the vias122are shown in phantom. The top layout600ofFIG.6may, for example, be taken along line C-C′ inFIG.5Aand/or the cross-sectional view500A ofFIG.5Amay, for example, be taken along line D-D′ inFIG.6. The TSV wires120awrap around each other and contact the TSVs132and some of the vias122to electrically couple the TSVs132respectively to the vias. The wires120, including the TSV wires120a, and the vias122define conductive paths leading from the TSVs132respectively to terminals of the 2D trench capacitors126to electrically couple the 2D trench capacitors126to the TSVs132. Despite the specific top layouts shown for the TSV wires120a, the TSVs132, and some of the vias122, it is to be appreciated that other top layouts are amenable. Further, while the top layout600ofFIG.6is described with regard to the cross-sectional view500A ofFIG.5A, the top layout600is applicable to the cross-sectional view500B ofFIG.5B. In other words, the top layout600ofFIG.6may alternatively be taken along line C-C′ inFIG.5Band/or the cross-sectional view500B ofFIG.5Bmay alternatively be taken along line D-D′ inFIG.6. With reference toFIG.7, a cross-sectional view700of some alternative embodiments of the semiconductor structure ofFIG.1is provided in which the IC dies106are fusion bonded together, instead of hybrid bonded together, at the front side bond interface108. As such, there is no metal-to-metal bond at the front side bond interface108. Further, the IC dies106comprise corresponding TSV wires120aand the TSVs132electrically couple the 2D trench capacitors126in parallel through the TSV wires120a. In alternative embodiments, there is a metal-to-metal bond at the front side bond interface108, but it's not employed for electrically coupling the 2D trench capacitors126in parallel. In some embodiments, the interconnect dielectric layer118is or comprises silicon oxide and/or some other suitable oxide at the front side bond interface108. Other suitable dielectric(s) are, however, amenable. The TSVs132extend through the first IC die106aand terminate in the second IC die106b. At the first interconnect structure114a, the TSVs132extend respectively through the TSV wires120aof the first IC die106aand laterally and directly contact the TSV wires. The TSV wires120aof the first IC die106aand the vias122of the first IC die106aelectrically couple the TSVs132respectively to terminals of the 2D trench capacitors126of the first IC die106a. At the second interconnect structure114b, the TSVs132terminate respectively at the TSV wires120aof the second IC die106b. The TSV wires120aof the second IC die106band the vias122of the second IC die106aelectrically couple the TSVs132respectively to terminals the 2D trench capacitors126of the second IC die106a. In some embodiments, the 2D trench capacitors126of the first IC die106aare electrically coupled to the 2D trench capacitors126of the second IC die106bonly through the TSVs132. In other words, but for the TSVs132, the 2D trench capacitors126of the first IC die106awould be electrically separated from the 2D trench capacitors126of the second IC die106b. In some embodiments, conductive paths from the 2D trench capacitors126of the first IC die106ato the TSVs132are non-overlapping with conductive paths from the 2D trench capacitors126of the second IC die106bto the TSVs132. By using fusion bonding in place of the hybrid bonding ofFIG.1, process difficulties with the hybrid bonding may be mitigated. The hybrid bonding may be more difficult to implement than the fusion bonding because it depends upon alignment between the wires at the front side bond interface108(see, e.g.,FIG.1) to electrically couple the IC dies106together, whereas the fusion bonding does not. On the other hand, by using the hybrid bonding ofFIG.1in place of the fusion bonding, process difficulties with forming the TSVs132may be mitigated. The TSVs132terminate in the first interconnect structure114awhen using the hybrid bonding, so the TSVs132have lesser heights than when using the fusion bonding. These lesser heights reduce aspect ratios of via openings within which the TSVs132are formed and hence reduce the process difficulties with forming the TSVs132. With reference toFIG.8A, a cross-sectional view800A of some alternative embodiments of the semiconductor structure ofFIG.7is provided in which the first and second thicknesses Tfs, Tssrespectively of the first and second substrates110a,110bare the same or substantially the same. With reference toFIGS.8B-8E, cross-sectional views800B-800E of some alternative embodiments of the semiconductor structure ofFIG.7are provided in which the trench segments104are varied respectively as inFIGS.1,4B,4C, and4E. WhileFIGS.7and8A-8Dare not illustrated with the well regions402ofFIG.8E, it is to be appreciated that alternative embodiments ofFIGS.7and8A-8Dmay include the well regions402. Further, while the top layout200ofFIG.2is described with regard to the TSV wires120aofFIG.1, the top layout200is applicable to the TSV wires120aofFIGS.7and8A-8E. For example, alternative embodiments ofFIG.2may be taken along line E-E′ in any one ofFIGS.7and8A-8Eand/or along line F-F′ in any one ofFIGS.7and8A-8E. Alternative embodiments ofFIG.2along line E-E′ may, for example, be the same as the embodiments ofFIG.2, except that the TSVs132extend through the TSV wires120aof the first IC die106aand some of the vias122are omitted. Alternative embodiments ofFIG.2along line F-F′ may, for example, be the same as the embodiments ofFIG.2, except that some of the vias122are be omitted. Notwithstanding that the TSV wires120aofFIGS.7and8A-8Emay have top layouts similar to the TSV wires120aofFIG.2, other top layouts are amenable. With reference toFIGS.9A and9B, cross-sectional views900A,900B of various alternative embodiments of the semiconductor structure ofFIG.7are provided in which the trench segments104are defined by more capacitor electrodes and more capacitor dielectric layers than inFIG.1. The semiconductor structures ofFIGS.9A and9Bmay, for example, respectively be as the semiconductor structures ofFIGS.5A and5Bare described, except that the IC dies106are fusion bonded together at the front side bond interface108and the TSVs132electrically couple the 2D trench capacitors126in parallel. While the top layout600ofFIG.6is described with regard to the TSV wires120aofFIG.5A, the top layout600is applicable to the TSV wires120aofFIGS.9A and9B. For example, alternative embodiments ofFIG.6may be taken along line G-G′ in any one ofFIGS.9A and9Band/or along line H-H′ in any one ofFIGS.9A and9B. Alternative embodiments ofFIG.6along line G-G′ may, for example, be the same as the embodiments ofFIG.6, except that the TSVs132extend through the TSV wires120aof the first IC die106aand some of the vias122are omitted. Alternative embodiments ofFIG.6along line H-H′ may, for example, be the same as the embodiments ofFIG.6, except that some of the vias122are omitted. Notwithstanding that the TSV wires120aofFIGS.9A and9Bmay have top layouts similar to the TSV wires120aofFIG.6, other top layouts are, however, amenable. With reference toFIG.10A, a cross-sectional view1000A of some embodiments of a semiconductor structure is provided in which a 3D trench capacitor102is arranged within at least four IC dies106. The semiconductor structure may, for example, be an IC, an IPD, or some other suitable semiconductor structure. The 3D trench capacitor102comprises a plurality of 2D trench capacitors126spread across the at least four IC dies106and electrically coupled in parallel, such that a capacitance of the 3D trench capacitor102is a sum of individual capacitances of the 2D trench capacitors126. The at least four IC dies106comprise a first IC die106a, a second IC die106b, a third IC die106c, and a fourth IC die106d. The first and second IC dies106a,106bare respectively as the first and second IC dies106a,106bofFIG.1are described, except TSVs132and TSV wires120aare at both the first and second IC dies106a,106b. The TSV wires120aof the first IC die106aelectrically couple the TSVs132of the first IC die106ato the 2D trench capacitors126of the first IC die106athrough a remainder of the wires120and a remainder of the illustrated vias122in the first IC die106a. The TSV wires120aof the second IC die106belectrically couple the TSVs132of the second IC die106bto the 2D trench capacitors126of the second IC die106bthrough a remainder of the wires120and a remainder of the vias122in the second IC die106b. The TSV wires120aof the first IC die106aand/or the TSV wires120aof the second IC dies106bmay, for example, have the same top layout(s) as inFIG.2or some other suitable top layouts. The third and fourth IC dies106c,106dare respectively as the first and second IC dies106a,106bofFIG.1are described. A bond structure1002is between the second and third IC dies106b,106cand bonds and electrically couples the second and third IC dies106b,106ctogether. The bond structure1002includes bond dielectric layers1004, bond wires1006, and bond vias1008. The bond wires1006correspond to the second and third IC dies106b,106cand directly contact at a back side bond interface1010. The bond dielectric layers1004correspond to the second and third IC dies106b,106cand directly contact at the back side bond interface1010. The bond vias1008extend respectively from the bond wires1006to the TSVs132of the second and third IC dies106b,106c. Other bond structures are amenable in alternative embodiments. Because the 2D trench capacitors126are spread across at least four device layers112in the vertical or Z dimension, a 2D projection of the 3D trench capacitor102onto a horizontal or XY plane may occupy a small area. Further, because the 2D trench capacitors126are electrically coupled in parallel, the capacitance of the 3D trench capacitor102is a sum of the capacitances of multiple 2D trench capacitors and may therefore be high. Because the 3D trench capacitor102may occupy a small area and may have a high capacitance, the 3D trench capacitor102may have a high capacitance density. With reference toFIG.10B, a cross-sectional view1000B of some alternative embodiments of the semiconductor structure ofFIG.10Ais provided in which the IC dies106are fusion bonded together and the TSVs132electrically couple the 2D trench capacitors126in parallel. The first and second dies106a,106bare respectively as the first and second IC dies106a,106bofFIG.7are described, except TSVs132are at the substrates110of both the first and second IC dies106a,106b. The third and fourth IC dies106c,106dare respectively as the first and second IC dies106a,106bofFIG.7are described. With reference toFIG.10C, a cross-sectional view1000C of some alternative embodiments of the semiconductor structure ofFIG.10Ais provided in which the third and fourth IC dies106c,106dare fusion bonded together and the TSVs132of the third and fourth IC dies106c,106delectrically couple the 2D trench capacitors126of the third and fourth IC dies106c,106din parallel. Further, the third and fourth IC dies106c,106dare respectively as the first and second IC dies106a,106bofFIG.7are described. WhileFIGS.10A-10Cillustrate the 2D trench capacitors126of the first and second IC dies106a,106bas being configured as inFIGS.1and7, the 2D trench capacitors126may alternatively be configured as in any one ofFIGS.4A-4E,5A,5B,8A-8E,9A, and9B. Similarly, whileFIGS.10A-10Cillustrate the 2D trench capacitors126of the third and fourth IC dies106c,106das being configured as inFIGS.1and7, the 2D trench capacitors126may alternatively be configured as in any one ofFIGS.4A-4E,5A,5B,8A-8E,9A, and9Bare amenable. While the 3D trench capacitor102is illustrated with four device layers112, more or less device layers are amenable in alternative embodiments. With reference toFIG.11, a cross-sectional view1100of some embodiments of a semiconductor structure package is provided in which a composite capacitor1102comprises multiple 2D trench capacitors126localized to a single device layer112and electrically coupled in parallel. Further, a depth D of the 2D trench capacitors126is partially in an interconnect structure114and partially in a substrate110. Because a portion of the depth D is in the interconnect structure114, the depth D may be larger than if wholly or substantially in the substrate110. As such, the 2D trench capacitors126may have larger capacitances than they would other otherwise have. The semiconductor structure package may, for example, be an IC package, an IPD package, or some other suitable semiconductor structure package. In some embodiments, the depth D is about 4 micrometers or less, about 6 micrometers or less, about 8 micrometers or less, about 4-8 micrometers, or some other suitable value. If the depth D is too low (e.g., less than about 4 micrometers or some other suitable value), the capacitances of the 2D trench capacitors126may be low. If the depth D is too high (e.g., greater than about 6 micrometers, 8 micrometers, or some other suitable value), aspect ratios of trenches within which the trench segments104are formed may be high. In some embodiments, the portion of the depth D in the interconnect structure114is about 20-60 percent, about 20-40 percent, about 40-60 percent, or some other suitable percentage of the depth D. If the portion of the depth D in the interconnect structure114makes up too small a percentage of the depth D (e.g., less than about 20 percent or some other suitable value), the increased manufacturing costs may not outweigh the benefit from increased capacitance. In some embodiments, the portion of the depth D in the interconnect structure114is about 10-50 percent, about 10-20 percent, about 20-30 percent, about 30-40 percent, about 40-50 percent, or some other suitable percentage of a thickness T of the substrate110. The 2D trench capacitors126and the substrate110are as described with regard toFIG.1. Further, the interconnect structure114is as described with regard toFIG.1, except for the layout of the wires120and the vias122. The wires120and the vias122are alternatingly stacked in the interconnect dielectric layer118to define conductive paths extending from the 2D trench capacitors126to under bump metallization (UBM) layers1104along a top of the semiconductor structure package. Note that the conductive paths are not fully visible. Further, the wires120and the vias122define conductive paths electrically coupling the 2D trench capacitors126in parallel. In alternative embodiments, the 2D trench capacitors126are electrically separated from each other. Further, in some embodiments, wires120bbordering the 2D trench capacitors126respectively have the same top layouts as the TSV wires120aofFIG.2. For example,FIG.2may be taken along line I-I′. Other suitable top layouts are amenable. The UBM layers1104extend through a passivation layer1106overlying the interconnect structure114, and bumps1108overlie the UBM layers1104. The UBM layers1104and the bumps1108may be or comprise, for example, metal and/or some other suitable conductive material(s). The passivation layer1106may be or comprise, for example, silicon oxide and/or some other suitable dielectric(s). With reference toFIGS.12-20, a series of cross-sectional views1200-2000of some embodiments of a method for forming the semiconductor structure ofFIG.1is provided. The semiconductor structure has trench segments that are on at least two substrates and that are electrically coupled together by hybrid bonding. Notwithstanding that the method forms the semiconductor structure ofFIG.1, the method and variations of the method may be employed to form the semiconductor structure in any one ofFIGS.4A-4E,5A,5B,10A, and10Cor to form some other suitable semiconductor structure. As illustrated by the cross-sectional view1200ofFIG.12, a first interconnect dielectric layer118ais deposited on a front side116of a first substrate110a. The first interconnect dielectric layers118amay be or comprise, for example, silicon oxide, some other suitable oxide, some other suitable dielectric, or any combination of the foregoing. In alternative embodiments, the first interconnect dielectric layer118ais omitted. In alternative embodiments, well regions are formed in the first substrate110abefore depositing the first interconnect dielectric layer118aand subsequently formed 2D trench capacitors are formed in the well regions. See, for example, the well regions402ofFIG.4E. Also illustrated by the cross-sectional view1200ofFIG.12, the first interconnect dielectric layer118aand the first substrate110aare patterned to form a pair of trenches1202. In alternative embodiments, more or less trenches are formed. The trenches1202have a first depth D1partially in the first interconnect dielectric layer118aand partially in the first substrate110a. Because a portion of the first depth D1is in first interconnect dielectric layer118a, the first depth D1may be larger than it would be if wholly or substantially in the first substrate110a. As such, 2D trench capacitors subsequently formed in the trenches1202may have larger capacitances than they would otherwise have. The patterning may, for example, be performed by or comprise a photolithography/etching process and/or some other suitable process(es). As illustrated by the cross-sectional view1300ofFIG.13, a plurality of conductive layers1302and a plurality of dielectric layers1304are alternatingly deposited over the first interconnect dielectric layer118aand lining the trenches1202(see, e.g.,FIG.12). In alternative embodiments, one or more conductive layers and/or one or more dielectric layers is/are deposited. The conductive layers1302may, for example, be or comprise metal and/or some other suitable conductive material(s). The dielectric layers1304may, for example, be or comprise silicon oxide, a high k dielectric, some other suitable dielectric(s), or any combination of the foregoing. As illustrated by the cross-sectional view1400ofFIG.14, the conductive layers1302(see, e.g.,FIG.13) and the dielectric layers1304(see, e.g.,FIG.13) are patterned to form a plurality of 2D trench capacitors126defining a first device layer112a. In alternative embodiments, more or less 2D trench capacitors126are formed. For example, a single 2D trench capacitor126may be formed in alternative embodiments. The 2D trench capacitors126comprise corresponding capacitor electrodes128and corresponding capacitor dielectric layers130that are alternatingly stacked and respectively formed from the conductive layers1302and the dielectric layers1304. Further, the 2D trench capacitors126have corresponding trench segments104. The trench segments104are defined by the capacitor electrodes128and the capacitor dielectric layers130and are respectively at the first trenches1202(see, e.g.,FIG.12). Because the trenches1202are formed with the first depth D1, the trench segments104are formed with the first depth D1. As such, the trench segments104laterally contact both the first interconnect dielectric layer118aand the first substrate110a. Further, because a portion of the first depth D1is in first interconnect dielectric layer118a, the first depth D1may be larger than it would be if wholly or substantially in the first substrate110a. As such, the 2D trench capacitors126may have larger capacitances than they would otherwise have. The patterning of the conductive layers1302and the dielectric layers1304may, for example, comprise: 1) performing a planarization into a top conductive layer1302a(see, e.g.,FIG.13) and a top dielectric layer1304a(see, e.g.,FIG.13) to uncover a lower conductive layer1302b(see, e.g.,FIG.13); and 2) performing a photolithography/etching process on the lower conductive layer1302band a lower dielectric layer1304b(see, e.g.,FIG.13). Other processes for performing the patterning are, however, amenable. As illustrated by the cross-sectional view1500ofFIG.15, a second interconnect dielectric layer118band a third interconnect dielectric layer118care formed over the 2D trench capacitors126. The second and third interconnect dielectric layers118b,118cmay be or comprise, for example, silicon oxide, silicon nitride, a low k dielectric, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the third interconnect dielectric layer118cis or comprise silicon oxide, some other suitable oxide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing. Also illustrated by the cross-sectional view1500ofFIG.15, a plurality of wires120and a plurality of vias122are formed in the second and third interconnect dielectric layers118b,118cwhile forming the second and third interconnect dielectric layers118b,118c. The wires120and the vias122are alternatingly stacked in the second and third interconnect dielectric layers118b,118cto define conductive paths electrically coupling the 2D trench capacitors126in parallel. Further, TSV wires120adefine pads1502to receive subsequently formed TSVs and electrically couple the pads1502to a remainder of the wires120and a remainder of the illustrated vias122. The remainder of the wires120and the remainder of the illustrated vias122, in turn, electrically couple the TSV wires120ato terminals of the 2D trench capacitors126. In some embodiments, the TSV wires120ahave the same top layout as inFIG.2. For example,FIG.2may be taken along line A-A′. In alternative embodiments, the TSV wires120ahave some other suitable top layout. The first, second, and third interconnect dielectric layers118a-118c, the wires120, and the vias122collectively define a first interconnect structure114a. For ease of illustration, the first, second, and third interconnect dielectric layers118a-118care hereafter shown (e.g., inFIG.16onward) as a single layer and are hereafter referred to collectively as an interconnect dielectric layer118. The first interconnect structure114a, the first device layer112a, and the first substrate110acollectively define a first IC die106a. While the first IC die106ais formed as illustrated as inFIG.1, the first IC die106amay alternatively be formed as illustrated in any one ofFIGS.4A-4E,5A, and5B. As illustrated by the cross-sectional view1600ofFIG.16, the first IC die106ais flipped vertically and the first substrate110ais thinned from a back side124of the first substrate110a. Further, the first IC die106ais patterned from the back side124of the first substrate110ato form via openings1602respectively exposing the pads1502. The thinning reduces a thickness Tfsof the first substrate110aand may, for example, be performed by a CMP or some other suitable planarization. The patterning may, for example, be performed by a photolithography/etching process or some other suitable patterning process. Because the via openings1602extend through the first substrate110a, an aspect ratio (e.g., a ratio of height to width) of the via openings1602may be high. However, if the aspect ratio is too high, it may be difficult to reliably form the via openings1602and/or it may be difficult to subsequently form TSVs in the via openings1602. For example, material may cluster around top corners of the via openings1602during deposition of layers from which the TSVs are formed. This phenomenon may be known as trench necking. The clustering may pinch off tops of the via openings1602before the deposition completes and may hence lead to voids forming in the via openings1602. The voids may lead to the TSVs having high resistances that increase power consumption and/or shift operating parameters out of specification. To mitigate the aforementioned concerns, the thinning is performed. By reducing the thickness Tfs, the thinning reduces the aspect ratio of the via openings1602. However, by reducing the thickness Tfs, the thinning also limits how far into the first substrate110athe trench segments104may extend. In other words, the thinning limits the portion of the first depth D1in the first substrate110a. If the trench segments104were wholly or substantially in the first substrate110a, the thinning would limit the first depth D1and would hence limit the capacitance of the 2D trench capacitors126. However, because a portion of the first depth D1is also in the interconnect dielectric layer118, the negative effects from the thinning are mitigated and the 2D trench capacitors126may have high capacitances. As illustrated by the cross-sectional view1700ofFIG.17, TSVs132and TSV dielectric layers134are formed in the via openings1602(see, e.g.,FIG.16). The TSVs132correspond to a first terminal T1of the 3D trench capacitor being formed and a second terminal T2of the 3D trench capacitor. Further, the TSVs132are electrically coupled respectively to terminals of the 2D trench capacitors126by the wires120and the vias122. The TSV dielectric layers134separate the TSVs132from the first substrate110a. A process for forming the TSV dielectric layers134may, for example, comprise: 1) depositing a dielectric layer over the first substrate110aand further lining and partially filling the via openings1602; and 2) etching back the dielectric layer to expose the back side124of the first substrate110aand the pads1502. A process for forming the TSVs132may, for example, comprise: 1) depositing a conductive layer over the first substrate110aand the TSV dielectric layers134and further filling a remainder of the via openings1602; and 2) performing a planarization into the conductive layer from the back side124of the first substrate110ato expose the back side124of the first substrate110a. The planarization may, for example, be or comprise a CMP or some other suitable planarization. Other processes for forming the TSV dielectric layers134and/or the TSVs132is/are, however, amenable. As illustrated by the cross-sectional view1800ofFIG.18, a second device layer112bis formed over a second substrate110b. The second device layer112bcomprises a plurality of 2D trench capacitors126. In alternative embodiments, more or less 2D trench capacitors126are formed. For example, a single 2D trench capacitor126may be formed in alternative embodiments. The 2D trench capacitors126comprise corresponding capacitor electrodes128and corresponding capacitor dielectric layers130that are alternatingly stacked and that define trench segments104. The trench segments104extend or protrude into the second substrate110band have a second depth D2wholly or substantially in the second substrate110b. This is in contrast with the trench segments104of the first IC die106a(see, e.g.,FIG.17), which have a first depth D1partially in the first substrate110a. Also illustrated by the cross-sectional view1800ofFIG.18, a second interconnect structure114bis formed over and electrically coupled to the second device layer112b. The second interconnect structure114bcomprises an interconnect dielectric layer118and further comprises a plurality of wires120and a plurality of vias122. The wires120and the vias122are alternatingly stacked in the interconnect dielectric layer118to define conductive paths electrically coupling the 2D trench capacitors126in parallel. Further, bond wires120cat a top of the second interconnect structure114bhave the same top layout as their counterparts in the first IC die106a(also labeled120cinFIG.17). The second interconnect structure114b, the second device layer112b, and the second substrate110bcollectively define a second IC die106b. In some embodiments, the second IC die106bis formed by the same process described atFIGS.12-15, except that the wires120and the vias122have a different layout. Further, the first interconnect dielectric layer118aatFIG.14is not formed so the trench segments104are wholly or substantially in the second substrate110b. In alternative embodiments, the second IC die106bis formed by the same process described atFIGS.12-15or by some other suitable process. Further, while the second IC die106bis formed as illustrated as inFIG.1, the second IC die106bmay alternatively be formed as illustrated in any one ofFIGS.4A-4E,5A, and5B. As illustrated by the cross-sectional view1900ofFIG.19, bond surfaces1902of the first and second interconnect structures114a,114bare pre-treated and then coarsely aligned. In alternative embodiments, the course alignment and/or the pre-treatment is/are omitted. The pre-treatment may, for example, comprise a cleaning process, plasma treatment, some other suitable pre-treatment process(es) for hybrid bonding, or any combination of the foregoing. In some embodiments, the plasma treatment cleans the bond surfaces1902. Also illustrated by cross-sectional view1900ofFIG.19, the bond surfaces1902are hybrid bonded together. A process for performing the hybrid bonding may, for example, comprise: 1) finely aligning the first IC die106ato the second IC die106bso the bond wires120cof the first IC die106arespectively overlie and are aligned to the bond wires120cof the second IC die106b; and 2) bringing the bond surfaces1902into direct contact. Other processes for performing the hybrid bonding are, however, amenable. As illustrated by the cross-sectional view2000ofFIG.20, the first and second IC dies106a,106bare annealed to strength a front side bond interface108at which the first and second IC dies106a,106bdirectly contact. The 2D trench capacitors126of the first IC die106aare electrically coupled in parallel with the 2D trench capacitors126of the second IC die106bthrough the front side bond interface108by the wires120and the vias122in the first and second IC dies106a,106b. Further, the wires120of the first IC die106aand the vias122of the first IC die106aelectrically couple the 2D trench capacitors126of the first and second IC dies106a,106bto the TSVs132. Collectively, the 2D trench capacitors126of the first and second IC dies106a,106bdefine a 3D trench capacitor102. Because the 2D trench capacitors126are spread across the multiple device layers (e.g., the first and second device layers112a,112b) in the vertical or Z dimension, the 3D trench capacitor102may have a small footprint. Further, because the capacitance of the 3D trench capacitor102is a sum of the capacitances of multiple 2D trench capacitors (e.g., the sum the capacitances of the 2D trench capacitors126in the first and second IC dies106a,106b), the 3D trench capacitor102may have a high capacitance. As a result of the high capacitance and the small footprint, the 3D trench capacitor102may have a high capacitance density. That is to say, a capacitance per unit area in the footprint of the 3D trench capacitor102may be high. WhileFIGS.12-20are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.12-20are not limited to the method but rather may stand alone separate of the method. WhileFIGS.12-20are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.12-20illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.21, a block diagram2100of some embodiments of the method ofFIGS.12-20is provided. At2102, a first interconnect dielectric layer is deposited covering a first substrate on a front side of the first substrate. See, for example,FIG.12. In alternative embodiments, the depositing of the first interconnect dielectric layer is omitted. At2104, a first trench capacitor is formed extending through the first interconnect dielectric layer into the first substrate on the front side of the first substrate. See, for example,FIGS.12-14. At2106, a first interconnect structure is formed covering and electrically coupled to the first trench capacitor on the front side of the first substrate, wherein the first interconnect structure comprises a plurality of wires and a plurality of vias that are alternatingly stacked. See, for example,FIG.15. At2108, a pair of TSVs is formed extending through the first substrate to the first interconnect structure from a back side of the first substrate, wherein the TSVs electrically couple respectively to terminals of the first trench capacitor through the wires and the vias. See, for example,FIGS.16and17. At2110, a second trench capacitor is formed extending into a second substrate on a front side of the second substrate. See, for example,FIG.18. At2112, a second interconnect structure is formed covering and electrically coupled to the second trench capacitor on the front side of the second substrate, wherein the second interconnect structure comprises a plurality of wires and a plurality of vias that are alternatingly stacked. See, for example,FIG.18. At2114, bond surfaces respectively of the first and second interconnect structures are pre-treated. See, for example,FIG.19. At2116, the first and second interconnect structures are aligned to each other. See, for example,FIG.19. At2118, the bond surfaces respectively of the first and second interconnect structures are hybrid bonded to each other at a front side bond interface, wherein the wires and the vias electrically couple the first and second trench capacitors to the TSVs and in parallel through the front side bond interface. See, for example,FIG.19. Collectively, the first and second trench capacitors define a 3D trench capacitor. Because the first and second trench capacitors are spread across multiple substrates in the vertical or Z dimension, the 3D trench capacitor may have both a small footprint and a high capacitance. As a result of the high capacitance and the small footprint, the 3D trench capacitor may have a high capacitance density. At2120, the front side bond interface is annealed to strength the front side bond interface. See, for example,FIG.20. While the block diagram2100ofFIG.21is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. With reference toFIGS.22-27, a series of cross-sectional views2200-2700of some embodiments of a method for forming the semiconductor structure ofFIG.7is provided. The semiconductor structure has trench segments that are on at least two substrates and that are electrically coupled together by TSVs. Notwithstanding that the method forms the semiconductor structure ofFIG.7, the method and variations of the method may be employed to form the semiconductor structure in any one ofFIGS.8A-8E,9A,9B,10B, and10Cor to form some other suitable semiconductor structure. As illustrated by the cross-sectional views2200,2300ofFIGS.22and23, a first IC die106a(see, e.g.,FIG.22) and a second IC die106b(see, e.g.,FIG.23) are respectively formed. A first device layer112ais on a front side116of a first substrate110a, whereas a second device layer112bis on a front side116of a second substrate110b. The first and second device layers112a,112bcomprise corresponding 2D trench capacitors126. The 2D trench capacitors126comprise corresponding capacitor electrodes128and corresponding capacitor dielectric layers130that are alternatingly stacked and that define trench segments104. The trench segments104of the first IC die106aextend into the first substrate110ato a first depth D1and are wholly or substantially within the first substrate110a. The trench segments104of the second IC die106bextend into the second substrate110bto a second depth D2and are wholly or substantially within the second substrate110b. In some embodiments, the first depth D1is less than the second depth D2because the thickness Tfsof the first substrate110amay be limited by subsequently formed TSVs, as described above with regard toFIGS.16and17. A first interconnect structure114acovers and electrically couples to the 2D trench capacitors126of the first IC die106aon the front side116of the first substrate110a. Similarly, a second interconnect structure114bcovers and electrically couples to the 2D trench capacitors126of the second IC die106bon the front side116of the second substrate110b. The first and second interconnect structures114a,114bcomprise corresponding interconnect dielectric layers118, as well as corresponding wires120and corresponding vias122. The wires120and the vias122are alternatingly stacked in the interconnect dielectric layers118to define conductive paths electrically coupling the 2D trench capacitors126in parallel. Further, TSV wires120adefine pads1502to receive subsequently formed TSVs and electrically couple the pads1502to a remainder of the wires120and a remainder of the vias122. The remainder of the wires120and the remainder of the vias122, in turn, electrically couple the TSV wires120ato terminals of the 2D trench capacitors126. In some embodiments, the TSV wires120ahave the same top layout as inFIG.2. For example,FIG.2may be taken along line E-E′ and/or along line F-F′. In alternative embodiments, the TSV wires120ahave some other suitable top layout. In some embodiments, the first and second IC dies106a,106bare symmetrical and/or are formed by the same process. Forming the first and second IC dies106a,106bby the same process may, for example, reduce manufacturing costs because there is only one process, instead of two separate processes, for the first and second IC dies106a,106b. Further, in some embodiments, the first and second IC dies106a,106bare individually formed by the process described atFIGS.12-15, except that the first interconnect dielectric layer118aatFIG.14is not formed and the wires120and the vias122have a different layout. As to the latter, wires are omitted at bond surfaces1902of the first and second IC dies106a,106b, such that the bond surfaces1902are limited to dielectric material. In alternative embodiments, the first IC die106aand/or the second IC die106bis/are formed by some other suitable process. While the first IC die106ais formed as illustrated as inFIG.7, the first IC die106amay alternatively be formed as illustrated in any one ofFIGS.8A-8E,9A, and9B. Similarly, while the second IC die106bis formed as illustrated as inFIG.7, the second IC die106bmay alternatively be formed as illustrated in any one ofFIGS.8A-8E,9A, and9B. As illustrated by the cross-sectional view2400ofFIG.24, the first IC die106ais vertically flipped. Further, the bond surfaces1902of the first and second interconnect structures114a,114bare pre-treated and coarsely aligned. In alternative embodiments, the course alignment and/or the pre-treatment is/are omitted. The pre-treatment may, for example, comprise a cleaning process, plasma treatment, some other suitable pre-treatment process(es) for fusion bonding, or any combination of the foregoing. Also illustrated by cross-sectional view2400ofFIG.24, the bond surfaces1902are fusion bonded together. A process for performing the fusion bonding may, for example, comprise: 1) finely aligning the first IC die106ato the second IC die106bso the pads1502of the first IC die106arespectively overlie and are aligned to the pads1502of the second IC die106b; and 2) bringing the bond surfaces1902into direct contact. Other processes for performing the fusion bonding are, however, amenable. As illustrated by the cross-sectional view2500ofFIG.25, the first and second IC dies106a,106bare annealed to strength a front side bond interface108at which the first and second IC dies106a,106bdirectly contact. In contrast withFIG.20, the 2D trench capacitors126of the first IC die106aare not yet electrically coupled to each other. As illustrated by the cross-sectional view2600ofFIG.26, the first substrate110ais thinned from a back side124of the first substrate110a. The thinning reduces a thickness Tfsof the first substrate110aand may, for example, be performed by a CMP or some other suitable planarization. As with described with regard toFIG.16, the thinning may, for example, be performed to reduce an aspect ratio of subsequently formed TSVs and to mitigate challenges associated with high aspect ratios. Also illustrated by the cross-sectional view2600ofFIG.26, the first and second IC dies106a,106bare patterned from the back side124of the first substrate110ato form via openings2602extending through the pads1502of the first IC die106aand respectively exposing the pads1502of the second IC die106b. Further, TSV dielectric layers134are formed on sidewalls of the via openings2602at the first IC die. A process for forming the via openings2602and the TSV dielectric layers134may, for example, comprise: 1) performing a photolithography/etching process into the back side124of the first substrate110auntil the pads1502of the first IC die106aare reached; 2) depositing a dielectric layer over the first substrate110aand further lining and partially filling the via openings2602; 3) etching back the dielectric layer to expose the pads1502of the first IC die106aand to form the TSV dielectric layers134; and 4) performing an etching process through the pads1502of the first IC die106ato the pads1502of the second IC die106b. The TSV dielectric layers134may, for example, serve as a lateral etch stop during the etching at step 4). Notwithstanding the foregoing process for patterning the first and second IC dies106a,106band forming the TSV dielectric layers134, other processes are, however, amenable. As illustrated by the cross-sectional view2700ofFIG.27, TSVs132are formed respectively in the via openings2602(see, e.g.,FIG.26). The TSVs132electrically couple the 2D trench capacitors126of the first IC die106ain parallel with the 2D trench capacitors126of the second IC die106b. Collectively, the 2D trench capacitors126of the first and second IC dies106a,106bdefine a 3D trench capacitor102having a first terminal T1and a second terminal T2accessible from the back side124of the first substrate110a. Because the 2D trench capacitors126are spread across the first and second device layers112a,112bin the vertical or Z dimension, the 3D trench capacitor102may have a small footprint. Further, because the capacitance of the 3D trench capacitor102is the sum of the capacitances of the 2D trench capacitors126in the first and second IC dies106a,106b, the 3D trench capacitor102may have a high capacitance. As a result of the high capacitance and the small footprint, the 3D trench capacitor102may have a high capacitance density. Additionally, because the first and second IC dies106a,106bare bonded together by fusion bonding and electrically coupled together by the TSVs132, technical challenges associated with hybrid bonding (see, e.g., the method ofFIGS.12-21) may be avoided. WhileFIGS.22-27are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.22-27are not limited to the method but rather may stand alone separate of the method. WhileFIGS.22-27are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.22-27illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. With reference toFIG.28, a block diagram2800of some embodiments of the method ofFIGS.22-27is provided. At2802, a first trench capacitor is formed extending into a first substrate on a front side of a first substrate. See, for example,FIG.22. At2804, a first interconnect structure is formed covering and electrically coupled to the first trench capacitor on the front side of the first substrate, wherein the first interconnect structure comprises a plurality of wires and a plurality of vias that are alternatingly stacked. See, for example,FIG.22. At2806, a second trench capacitor is formed extending into a second substrate on a front side of a second substrate. See, for example,FIG.23. At2808, a second interconnect structure is formed covering and electrically coupled to the second trench capacitor on the front side of the second substrate, wherein the second interconnect structure comprises a plurality of wires and a plurality of vias that are alternatingly stacked. See, for example,FIG.23. At2810, bond surfaces respectively of the first and second interconnect structures are pre-treated. See, for example,FIG.24. At2812, the first and second interconnect structures are aligned to each other. See, for example,FIG.24. At2814, the bond surfaces respectively of the first and second interconnect structures are fusion bonded to each other at a front side bond interface, wherein the first and second interconnect structures are electrically isolated from each other upon completion of the fusion bond. See, for example,FIG.24. At2816, the front side bond interface is annealed to strengthen the front side bond interface. See, for example,FIG.25. At2818, a pair of TSVs are formed extending through the first substrate and the first interconnect structure to the second interconnect structure from a back side of the first substrate, wherein the TSVs electrically couple to the first and second trench capacitors through the wires and the vias. See, for example,FIGS.26and27. Collectively, the first and second trench capacitors define a 3D trench capacitor. Because the 2D trench capacitors are spread across multiple substrates in the vertical or Z dimension, the 3D trench capacitor may have both a small footprint and a high capacitance. As a result of the high capacitance and the small footprint, the 3D trench capacitor may have a high capacitance density. While the block diagram2800ofFIG.28is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. In some embodiments, the present disclosure provides a semiconductor structure including: a first substrate and a second substrate; a first trench capacitor and a second trench capacitor extending respectively into a front side of the first substrate and a front side of the second substrate, wherein the front sides of the first and second substrates face each other; a plurality of wires and a plurality of vias stacked between and electrically coupled to the first and second trench capacitors; and a first TSV extending through the first substrate from a back side of the first substrate opposite the front side of the first substrate, wherein the wires and the vias electrically couple the first TSV to the first and second trench capacitors. In some embodiments, the semiconductor structure further includes a first dielectric layer between the first trench capacitor and the first substrate, wherein the first trench capacitor extends completely through the first dielectric layer into the front side of the first substrate. In some embodiments, a thickness of the first dielectric layer is about equal to a difference between thicknesses of the first and second substrates. In some embodiments, the plurality of wires and the plurality of vias are grouped into a first alternating stack of wires and vias and a second alternating stack of wires and vias, and wherein the first and second alternating stacks are spaced from each other and electrically coupled together by the first TSV. In some embodiments, the plurality of wires and the plurality of vias define a first conductive path extending from the first TSV to the first trench capacitor and further define a second conductive path extending from the first TSV to the second trench capacitor, and wherein the first and second conductive paths are non-overlapping. In some embodiments, the plurality of wires and the plurality of vias are grouped into a first alternating stack of wires and vias and a second alternating stack of wires and vias, wherein the first and second alternating stacks directly contact at a hybrid bond interface, and wherein the first TSV extends through the first substrate, from the back side of the first substrate, and terminates between the hybrid bond interface and the first substrate. In some embodiments, the plurality of wires and the plurality of vias define a first conductive path extending from the first TSV to the first trench capacitor and further define a second conductive path extending from the first TSV to the second trench capacitor, and wherein the first and second conductive paths partially overlap. In some embodiments, the semiconductor structure further includes a second TSV extending through the first substrate from the back side of the first substrate, and wherein the wires and the vias electrically couple the second TSV to the first and second trench capacitors. In some embodiments, the first trench capacitor includes: a first electrode having a columnar profile; a capacitor dielectric layer wrapping around the first electrode and separating the first electrode from the first substrate; and a second electrode wrapping around the capacitor dielectric layer and separating the capacitor dielectric layer from the first substrate. In some embodiments, the present disclosure provides an IC including: a first IC die including a first substrate, a first interconnect structure underlying the first substrate, and a first trench capacitor, wherein the first trench capacitor extends into the first substrate and is between the first substrate and the first interconnect structure; a second IC die under and directly bonded to the first IC die, wherein the second IC die includes a second substrate, a second interconnect structure overlying the second substrate, and a second trench capacitor, and wherein the second trench capacitor extends into the second substrate and is between the second substrate and the second interconnect structure; and a pair of TSVs extending through the first substrate and electrically coupled to the first and second trench capacitors by the first and second interconnect structures. In some embodiments, the TSVs are localized to the first IC die. In some embodiments, the TSVs extend completely through the first IC die and terminate in the second IC die, wherein the TSVs each directly contact sidewalls of first TSV wires in the first interconnect structure, and wherein the TSVs each directly contact and terminate at top surfaces of second TSV wires in the second interconnect structure. In some embodiments, the present disclosure provides a method for forming a 3D trench capacitor, the method including: forming a first trench capacitor extending into a front side of a first substrate; forming a first interconnect structure covering and electrically coupled to the first trench capacitor on the front side of the first substrate; forming a second trench capacitor extending into a front side of a second substrate; forming a second interconnect structure covering and electrically coupled to the second trench capacitor on the front side of the second substrate; bonding the first and second interconnect structures together at a bond interface at which the first and second interconnect structures directly contact each other; and forming a first TSV extending through the first substrate from a back side of the first substrate, wherein the first TSV electrically couples to the first and second trench capacitors through the first and second interconnect structures. In some embodiments, the first and second trench capacitors are electrically coupled in parallel by the bonding. In some embodiments, the bonding is performed by a hybrid bonding process in which metal and dielectric material of the first interconnect structure respectively and directly contact metal and dielectric material of the second interconnect structure at the bond interface. In some embodiments, the method further includes: performing an etch into the back side of the first substrate before the bonding, wherein the etch forms an opening and stops on a TSV wire in the first interconnect structure; and filling the opening with a conductive material to define the first TSV in the opening. In some embodiments, the first and second trench capacitors are electrically isolated from each other upon completion of the bonding, and wherein the forming of the first TSV electrically couples the first trench capacitor to the second trench capacitor. In some embodiments, the bonding is performed by a fusion bonding process in which dielectric material of the first interconnect structure directly contacts dielectric material of the second interconnect structure at the bond interface, and wherein the bond interface is devoid of conductive material. In some embodiments, the method further includes: performing an etch into the back side of the first substrate after the bonding, wherein the etch forms an opening and stops on a TSV wire in the second interconnect structure; and filling the opening with a conductive material to define the first TSV in the opening. In some embodiments, the method further includes: depositing a dielectric layer on the front side of the first substrate; performing an etch into the dielectric layer and the first substrate from the front side of the first substrate to form a trench; forming a multi-layer capacitor film filling the trench; and patterning the multi-layer capacitor film into the first trench capacitor. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 80,720 |
11862613 | DETAILED DESCRIPTION Hereinafter, example embodiments of the present inventive concept will be described with reference to the accompanying drawings. FIG.1is a schematic cross-sectional view of a semiconductor package according to example embodiments.FIG.2is a partially enlarged view of a semiconductor package according to example embodiments.FIG.3is a partially enlarged view of a semiconductor package according to example embodiments.FIG.2is an enlarged view of region “I” ofFIG.1.FIG.3illustrates a region corresponding to region “II” ofFIG.1.FIG.4is a plan view of a semiconductor package according to example embodiments.FIG.5Ais a schematic plan view of an upper pad structure, a lower bonding pad, and a connection pad pattern of a semiconductor package according to example embodiments. Referring toFIGS.1through5A, a semiconductor package1may include a stacked chip structure CS including a plurality of semiconductor chips100,200,300, and400spaced apart from each other in the z direction. The semiconductor package1may further include a passivation layer102, an under bump metal101, and a chip bump BP disposed under the stacked chip structure CS. In an example embodiment, the plurality of semiconductor chips100,200,300, and400may be memory semiconductor chips. The number of the plurality of semiconductor chips100,200,300, and400is not limited to the number shown in the drawings. For example, the plurality of semiconductor chips100,200,300, and400may include a larger number of semiconductor chips than two semiconductor chips or four semiconductor chips as depicted in the drawings. In an example, the plurality of semiconductor chips100,200,300, and400may be the same semiconductor chips. For example, the plurality of semiconductor chips100,200,300, and400may be memory semiconductor chips such as DRAMs or memory semiconductor chips such as NAND flash memories. The types of the plurality of semiconductor chips100,200,300, and400are not limited to the aforementioned DRAMs or NAND flash memories. For example, the plurality of semiconductor chips100,200,300, and400may be PRAMS, resistance change memories (ReRAM), or magnetoresistive memories (MRAM). In another example, the plurality of semiconductor chips100,200,300, and400may include different types of semiconductor chips. For example, one of the plurality of semiconductor chips100,200,300, and400may be a logic semiconductor chip or a processor chip, and one or more of the remaining chips may be memory semiconductor chips. For example, the plurality of semiconductor chips100,200,300, and400may include a lower chip that may be a logic semiconductor chip or a process chip and one or more of memory semiconductor chips disposed on the lower chip. Each of the plurality of semiconductor chips100,200,300, and400may include a first region B and second regions A and C. As illustrated in the plan view ofFIG.4, the first region B may be a region in which through-electrode structures120and220penetrating semiconductor bodies110and210of semiconductor chips are disposed. The second regions A and C may be regions in which the through-electrode structures120and220are not disposed. For example, memory cells may be formed in the second regions A and C. In an example embodiment, the first region B may be disposed at the center of the semiconductor chips and the second regions A and C may be disposed outside the first region. However, the arrangement is not limited thereto and may be variously modified. In some embodiments of the present inventive concept, internal circuit structures ICS1and ICS2may be formed in the second regions A and C in which the through-electrode structures120and220are not disposed, and the internal circuit structures ICS1and ICS2and the through-electrode structures120and220disposed in the first region B may be electrically connected to enhance voltage characteristics. As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to the other (although such electrical signal may be attenuated in strength as it is transferred and may be selectively transferred). The plurality of semiconductor chips100,200,300, and400may include a first semiconductor chip100and a second semiconductor chip200disposed on the first semiconductor chip100. According to embodiments of the present inventive concept, the first semiconductor chip100may be considered to be a lower chip located below the second semiconductor chip200, and the second semiconductor chip200may be considered to be an upper chip located above the first semiconductor chip100. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe positional relationships, such as illustrated in the figures, e.g.,FIGS.1-3and6-9. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. The first semiconductor chip100may include a first semiconductor body110having a front surface110fand a rear surface110bopposite each other, an upper insulating layer185disposed on the rear surface110bof the semiconductor body110, an upper pad structure PS disposed on the rear surface110bof the semiconductor body110, first through-electrode structures120penetrating the first semiconductor body110, and a first internal circuit structure ICS1. For example, the front surface110fof the first semiconductor body110may be a lower surface of the first semiconductor body110facing downwards, and the rear surface110bof the first semiconductor body110may be an upper surface of the first semiconductor body110facing upwards. In addition, the first semiconductor chip100may further include an electrode connection wiring140, a circuit wiring150electrically connected to the electrode connection wiring140, and a first lower internal insulating layer130covering the electrode connection wiring140and the circuit wiring150. For example, the electrode connection wiring140may be a portion of wiring vertically overlapping (e.g., overlapping from a plan view) the first through-electrode structure120, and the circuit wiring150may be a wiring formed in the first region B of the first semiconductor chip100and in a region non-overlapping (e.g., from a plan view) the first through-electrode structure120. The second semiconductor chip200may include a second semiconductor body210having a front surface210fand a rear surface210bopposite each other, an upper insulating layer285disposed on the rear surface210bof the second semiconductor body210, upper pad structure PS disposed on the rear surface210bof the second semiconductor body210, second through-electrode structures220penetrating the second semiconductor body210and electrically connected to the upper pad structure PS, a lower insulating layer215disposed on the front surface210fof the second semiconductor body210, lower bonding pads PAD3disposed on the front surface210fof the second semiconductor body210, and a second internal circuit structure ICS2. For example, the front surface210fof the second semiconductor body210may be a lower surface of the second semiconductor body210facing downwards, and the rear surface210bof the second semiconductor body210may be an upper surface of the second semiconductor body210facing upwards. In addition, the second semiconductor chip200may further include an electrode connection wiring240, a circuit wiring250electrically connected to the electrode connection wiring240, and a second lower internal insulating layer230covering the electrode connection wiring240and the circuit wiring250. For example, the electrode connection wiring240may be a portion of wiring vertically overlapping the second through-electrode structure220, and the circuit wiring250may be a wiring formed in the first region B of the second semiconductor chip200and in a region non-overlapping the second through-electrode structure220. The first and second semiconductor bodies110and210may be semiconductor substrates. For example, the first and second semiconductor bodies110and210may be silicon substrates. The upper pad structure PS may include upper bonding pads PAD1and PAD2and connection wirings180. The upper bonding pads PAD1and PAD2may include a first upper bonding pad PAD1disposed in the first region B and overlapping the first through-electrode structure120and a second upper bonding pad PAD2disposed in the second region A and C and not overlapping the first through-electrode structure120. Each of first upper bonding pads PAD1of the first semiconductor chip100may be coupled to and in contact with a lower bonding pad PAD3of the second semiconductor chip200disposed in a position corresponding to the first upper bonding pad PAD1of the first semiconductor chip100. The second upper bonding pads PAD2may be in contact with and coupled to connection pad patterns265. For example, at least one of connection pad patterns265may perform the same function as the lower bonding pads PAD3. For example, the connection pad patterns265may be used to bond the first and second semiconductor chips100and200. The first upper bonding pad PAD1may be electrically connected to the first through-electrode122. Since the first and second semiconductor chips100and200are bonded by the upper and lower bonding pads PAD1, PAD2, and PAD3and the connection pad patterns265disposed at corresponding positions, a gap between the first and second semiconductor chips100and200may be minimized. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. The upper bonding pads PAD1and PAD2and the lower bonding pads PAD3may be formed of a conductive material that may be coupled/bonded with each other, while contacting each other, e.g., copper or the like. The connection wirings180may be disposed to be electrically connected to the second internal circuit structure ICS2disposed in the second regions A and C. The connection wirings180may be electrically connected to the upper bonding pads PAD1and PAD2and the first through-electrode structures120. At least one of the connection wirings180of the first semiconductor chip100extends in a direction opposite to the first region B in which the first through-electrode structures120are disposed from the first upper bonding pad PAD1, so as to be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200. At least one of the connection wirings180is disposed between the first upper bonding pad PAD1and the second upper bonding pad PAD2and electrically connect the first upper bonding pad PAD1and the second upper bonding pad PAD2. At least one of the connection wirings180may be electrically connected to the second upper bonding pad PAD2. As shown inFIG.5A, the connection wirings180may extend from the first upper bonding pad PAD1to connect the first upper bonding pad PAD1and the second upper bonding pad PAD2. InFIG.5A, it is illustrated that the sizes of the lower bonding pad PAD3and the connection pad pattern265are larger than those of the upper bonding pads PAD1and PAD2but are not limited thereto and may be substantially the same or smaller. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. In an example embodiment, the connection wiring180extending from the first upper bonding pad PAD1, among the connection wirings180of the first semiconductor chip100, may be in contact with the connection pad pattern265of the second semiconductor chip200. At least a portion of the connection wiring180extending from the first upper bonding pad PAD1may be in contact with the lower insulating layer215of the second semiconductor chip200. In an example embodiment, the connection wirings180may be disposed on the same level as the upper bonding pads PAD1and PAD2, but are not limited thereto. The connection wirings180may include or be formed of a conductive material, e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The connection wirings180may perform various functions depending on designs. For example, the connection wirings180may include a ground pattern GND, a power pattern PWR, and a signal pattern S. A ground signal may be applied to the ground pattern GND, and a power signal may be applied to the power pattern PWR. The signal pattern S may transmit various signals other than a ground signal and a power signal. For example, the signal pattern S may transmit a data signal. In the embodiments of the present inventive concept, since a gap between the first and second semiconductor chips100and200can be minimized, the upper pad structure PS electrically connected to the first through-electrode122of the first semiconductor chip100may extend to a region, in which the first through-electrodes122are not disposed, so as to be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200in the second regions A and C and form a separate electrical connection path in the regions other than the first region B. The upper insulating layer185of the first semiconductor chip100may be in contact with and coupled to the lower insulating layer215of the second semiconductor chip200. The upper insulating layer185of the first semiconductor chip100and the lower insulating layer215of the second semiconductor chip200may be formed of an insulating material that may be bonded while contacting each other. For example, the upper insulating layer185and the lower insulating layer215may be formed of silicon oxide. In certain embodiments, the upper insulating layer185and the lower insulating layer215may be formed of SiCN or the like, without being limited to the silicon oxide. The through-electrode structures120and220may include a first through-electrode structure120and a second through-electrode structure220. The through-electrode structures120and220may electrically connect the electrode connection wirings140and240and the pad structure PS respectively. The through-electrode structures120and220may include through-electrodes122a,122b,222a, and222band insulating spacers124and224surrounding side surfaces of the through-electrodes122a,122b,222a, and222b, respectively. The through-electrodes122a,122b,222a, and222bmay be formed of a conductive material such as copper or the like. The insulating spacers124and224may be formed of an insulating material. The insulating spacers124and224may insulate each of the through-electrodes122a,122b,222a, and222bfrom the semiconductor bodies110and210. Since the through-electrode structures120and220of the present inventive concept include through-electrodes122a,122b,222a,222b, the description of the present inventive concept for the through-electrode structure may also be interpreted as a description for the through-electrodes. The through-electrodes122a,122b,222a, and222bmay include power through-electrodes122aand222aand signal through-electrodes122band222b. As shown inFIG.2, in a region adjacent to the second region C, the through-electrode122aelectrically connected to the second internal circuit structure ICS2of the second semiconductor chip200through the upper pad structure PS of the first semiconductor chip100may be a power through-electrode. For example, the through-electrode122aelectrically connected to the second internal circuit structure ICS2of the second semiconductor chip200through the connection wirings180of the upper pad structure PS may be a power through-electrode. For example, the power through-electrode may be a path through which a power signal is transferred. For example, a power signal may be applied to the power through-electrode. As shown inFIG.3, in a region adjacent to the second region A, the through-electrode122belectrically connected to the second internal circuit structure ICS2of the second semiconductor chip200through the upper pad structure PS of the first semiconductor chip100may be a signal through-electrode. For example, the through-electrode122belectrically connected to the second internal circuit structure ICS2of the second semiconductor chip200through the connection wirings180of the upper pad structure PS of the first semiconductor chip100may be a signal through-electrode. For example, signal through-electrode may be a path through which a data signal or a control signal is transferred. For example, a data signal or a control signal may be applied to the signal through-electrode. In the stacked chip structure CS, a through-electrode of the lower chip electrically connected to the internal circuit structure of the upper chip through the upper pad structure PS of the lower chip may be a power through-electrode122aor a signal through-electrode122b. The electrode connection wirings140and240may be disposed to overlap the through-electrode structures120and220. The electrode connection wirings140and240may be electrically connected to the through-electrode structures120and220. The electrode connection wirings140and240may include or be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The electrode connection wirings140and240may perform various functions depending on designs. For example, electrode connection wirings140and240may include a ground pattern GND, a power pattern (PWR), and a signal pattern S. The signal pattern S may transmit various signals other than a ground signal and a power signal. For example, the signal pattern S may transmit a data signal. The internal circuit structures ICS1and ICS2may include internal circuit wirings160and260, circuit elements170and270, and connection pad patterns265. The internal circuit wirings160and260, the circuit elements170and270, and the connection pad patterns265may be covered by the lower internal insulating layer230. In an example embodiment, the internal circuit structures ICS1and ICS2may further include information storage structures175and275that store information. The internal circuit structures (e.g., ICS1and ICS2) may be disposed on the front surfaces of the plurality of semiconductor chips100,200,300and400in the second regions A and C. For example, the internal circuit structures ICS1and ICS2may be respectively disposed on the front surfaces110fand210fof the first and second semiconductor bodies110and210. The internal circuit structures ICS1and ICS2may be disposed in a region in which the internal circuit structures ICS1and ICS2do not overlap the through-electrode structures120and220. The internal circuit structures ICS1and ICS2may be disposed in the lower internal insulating layers130and230. The second internal circuit structure ICS2of the second semiconductor chip200may be electrically connected to the through-electrode structure120of the first semiconductor chip100through the connection wirings180of the first semiconductor chip100. For example, the second internal circuit structure ICS2of the second semiconductor chip200may be electrically connected to the first through-electrode122of the first semiconductor chip100through at least one of the upper bonding pads PAD1and PAD2and the connection wirings180. In the second regions A and C, the internal circuit wirings160and260may be arranged in a mesh form but are not limited thereto and may be variously modified and arranged. The connection pad patterns265may be disposed at substantially the same level as the lower bonding pad PAD3. The connection pad pattern265of the second semiconductor chip200may be electrically connected to the internal circuit wirings260of the second semiconductor chip200and the upper pad structure PS of the first semiconductor chip100. Also, the connection pad pattern265of the second semiconductor chip200may be in contact with and couple to the second upper bonding pad PAD2of the first semiconductor chip100, like the lower bonding pad PAD3, e.g., contacting the first upper bonding pad PAD1. The circuit elements170and270may include active elements such as transistors and passive elements such as resistors and capacitors. In an example embodiment, each of the information storage structures175and275may be a memory cell capacitor of a DRAM. Chip pads105may be disposed under the stacked chip structure CS and may be electrically connected to the electrode connection wiring140and the first internal circuit structure ICS1. For example, some chip pads105may be electrically connected to the electrode connection wiring140, and some other chip pads105may be electrically connected to the first internal circuit structure ICS1. The passivation layer102may be disposed under the lowermost semiconductor chip100. The passivation layer102may be disposed on the lower internal insulating layer130of the first semiconductor chip100. The passivation layer102may have an opening exposing at least a portion of a chip pad105. The passivation layer102may include or be formed of an insulating material. For example, the passivation layer102may be ABF (Ajinomoto Build-up Film) or an epoxy resin layer, but is not limited thereto and may include other types of insulating materials. The under bump metal101may be disposed in an opening of the passivation layer102and may be electrically connected to a portion of the chip pad105exposed by the opening of the passivation layer102. The under bump metal101may be formed by a metallization method using a metal, but is not limited thereto. Chip bumps BP may be electrically connected to the chip pad105, the electrode connection wiring140, and the internal circuit structure ICS1through the under bump metal101. The chip bumps BP may physically and/or electrically connect the semiconductor package1to the outside. The chip bumps BP may include a low melting point metal, e.g., tin (Sn) or an alloy including tin (Sn) (e.g., Sn—Ag—Cu). The chip bumps BP may be a land, a ball, or a pin. The chip bumps BP may include or may be copper pillars or solders. Next, various modifications of the upper pad structure PS of the first semiconductor chip100and the connection pad pattern265of the second semiconductor chip200according to example embodiments will be described with reference toFIGS.5B and5C.FIG.5Bis a schematic plan view showing a modification of the upper pad structure PS and the connection pad pattern265of the semiconductor package according to example embodiments, andFIG.5Cis a schematic plan view showing another modification of the pad structure PS and the connection pad pattern265. In a modification, referring toFIG.5B, the upper pad structure PS of the first semiconductor chip100disposed below the connection pad pattern265may include a pair of second upper bonding pads PAD2aand PAD2bspaced apart from each other in the second regions A and C, and the connection pad pattern265of the second semiconductor chip200disposed above the upper pad structure PS may be bonded to the pair of second upper bonding pads PAD2aand PAD2b. The connection pad pattern265may include bonding portions265aand265bbonded to the second upper bonding pads PAD2aand PAD2band a connection portion265cextending from the bonding portions265aand265bto electrically connect the bonding portions265aand265bto each other. InFIG.5B, the bonding portions265aand265bof the connection pad pattern265are shown to be larger than the upper bonding pads PAD2aand PAD2b, but the present disclosure is not limited thereto and the bonding portions265aand265bmay be substantially the same as or smaller to the upper bonding pads PAD2aand PAD2bin size. In a modification, referring toFIG.5C, the upper pad structure PS of the first semiconductor chip100disposed lower than the connection pad pattern265may include a pair of second upper bonding pads PAD2a′ and PAD2b′ spaced apart from each other, and a pad connection portion PAD2cextending from the pair of second upper bonding pads PAD2a′ and PAD2b′ to electrically connect the pair of second bonding upper pads PAD2a′ and PAD2b′. The connection pad pattern265of the second semiconductor chip200disposed above the upper pad structure PS may be bonded to the second upper bonding pads PAD2a′ and PAD2b′ and may include the connection pad patterns265a′ and265b′ spaced apart from each other. InFIG.5C, the connection pad patterns265a′ and265b′ are shown to be larger than the upper bonding pads PAD2a′ and PAD2b′, but the present disclosure is not limited thereto and the connection pad patterns265a′ and265b′ may be substantially the same as or smaller to the upper bonding pads PAD2a′ and PAD2b′ in size. FIG.6is a partially enlarged view of a semiconductor package according to example embodiments.FIG.6shows a region corresponding to region “I” ofFIG.1. Referring toFIG.6, only modified parts compared to the example embodiment ofFIG.5Awill be described, and for the same components as the ones described above, the descriptions ofFIGS.1through5Amay be equally applied. Referring toFIG.6, in a semiconductor package2, the upper pad structure PS may consist of a plurality of layers. The connection wirings180may consist of a plurality of layers. InFIG.6, two layers are shown, but the present inventive concept is not limited thereto. The connection wirings180of the first semiconductor chip100may be disposed to be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200disposed in the second regions A and C. The connection wirings180may be electrically connected to the first through-electrode structure120. The connection wirings180may further include a first upper pattern182, a second upper pattern184, and a connection portion186electrically connecting the first upper pattern182and the second upper pattern184. The first upper pattern182may be disposed to overlap the first upper bonding pad PAD1, and the second upper pattern184may be disposed to overlap the second upper bonding pad PAD2. The first upper pattern182may be disposed to overlap the lower bonding pad PAD3disposed in the first region B, and the second upper pattern184may be disposed to overlap the connection pad pattern265. The connection wirings180may be disposed at a level lower than the upper bonding pads PAD1and PAD2. For example, the first and second upper patterns182and184may be disposed at a level lower than the upper bonding pads PAD1and PAD2. A plurality of first upper patterns182and a plurality of second upper patterns184may be provided in each of the semiconductor chips100,200,300and400. For example, the first and second upper patterns182and184may be provided in a plurality of layers. At least one of the first upper patterns182may be in contact with the first through-electrode structure120. At least one of the connection wirings180may include a connection portion186extending from the first upper pattern182and electrically connecting the first upper pattern182and the second upper pattern184. When the connection wirings180electrically connect the first region and the second region at the level lower than the upper bonding pads PAD1and PAD2, the connection wirings180may not be disposed between the upper bonding pads PAD1and PAD2. An upper insulating layer185may be disposed between the first upper bonding pads PAD1and the second upper bonding pads PAD2. FIG.7is a schematic cross-sectional view of a semiconductor package according to example embodiments.FIG.7shows a region corresponding to region “II” ofFIG.1. Referring toFIG.7, only a modified part compared to the example embodiment ofFIG.5Awill be described, and for the same components as the ones described above, the descriptions ofFIGS.1through5Amay be equally applied. Referring toFIG.7, in a semiconductor package3, unlike the semiconductor package1ofFIGS.1to5A, the signal through-electrode122bof the first semiconductor chip100may not be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200by the upper pad structure PS. The signal through-electrode122bof the first semiconductor chip100may be in contact with the first upper bonding pad PAD1. The signal through-electrode122bof the first semiconductor chip100may be electrically connected to the first upper bonding pad PAD1and the lower bonding pad PAD3of the second semiconductor chip200. The signal through-electrode122bof the first semiconductor chip100may be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200through the electrode connection wiring240of the second semiconductor chip200electrically connected to the lower bonding pad PAD3. For example, as shown inFIG.5A, the power through-electrode122amay be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200by the connection wirings180of the upper pad structure PS in some embodiments. In certain embodiments, as shown inFIG.7, since the first upper bonding pad PAD1and the second upper bonding pad PAD2are not connected by a connection wiring180, the signal through-electrode122bmay not be electrically connected to the second internal circuit structure ICS2of the second semiconductor chip200by the connection wirings180. For example, the signal through-electrode122bmay be electrically connected to the second circuit structure ICS2of the second semiconductor chip200by a wiring other than the connection wiring180. FIG.8is a schematic cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.8, a semiconductor package4may include a molded layer500covering the stacked chip structure CS and an underfill material layer450disposed on the substrate50. The stacked chip structure CS of the semiconductor package4may be one of the stacked chip structures CS of the semiconductor packages1,2, and3described above with reference toFIGS.1through7. In an example embodiment, the semiconductor package4may include a substrate50disposed under chip bumps BP disposed under the stacked chip structure CS, first substrate pads55disposed on an upper surface of the substrate50, second substrate pads45disposed on a lower surface of the substrate50, and internal electrodes50T electrically connecting the first substrate pads55and the second substrate pads45. The internal electrodes50T may be through-electrodes or internal wirings. The semiconductor package4may further include a first lower passivation layer51disposed on the upper surface of the substrate50and covering at least a portion of the first substrate pads55and a first bump metal52in contact with the chip bumps BP. The molded layer500may be disposed on the underfill material layer450. The molded layer500may be formed of an epoxy molding compound (EMC) including a filler. The underfill material layer450may surround a side surface of each of the chip bumps BP and fill a portion between the stacked chip structure CS and the first lower passivation layer51on the substrate50. The underfill material layer450may include an epoxy resin and a filler. In an example embodiment, the semiconductor package4may further include a second lower passivation layer41disposed on a lower surface of the substrate50and covering at least a portion of the second substrate pads45, a second bump metal42, and substrate bumps35. In an example embodiment, the substrate50may be a printed circuit board (PCB), an interposer, or a semiconductor chip (e.g., a logic semiconductor chip). The first and second substrate pads55and45and the internal electrodes50T may be formed of a conductive material. The first lower passivation layer51may have an opening exposing at least a portion of the first substrate pads55. The first lower passivation layer51may include or be formed of an insulating material. The second lower passivation layer41may have an opening exposing at least a portion of the second substrate pads45. The second lower passivation layer41may include or be formed of an insulating material. The first bump metal52may be disposed in the opening of the first lower passivation layer51and may be electrically connected to a portion of the first substrate pads55exposed by the opening of the first lower passivation layer51. The second bump metal42may be disposed in the opening of the second lower passivation layer41and may be electrically connected to a portion of the second substrate pads45exposed by the opening of the second lower passivation layer41. The first and second bump metals52and42may be formed by a metallization method using a metal, but are not limited thereto. The substrate bumps35may be electrically connected to the second substrate pads45and the internal electrodes50T through the second bump metal42. The substrate bumps35may include or be formed of a low melting point metal, e.g., tin (Sn), an alloy including tin (Sn) (e.g., Sn—Ag—Cu), etc. The substrate bumps35may be lands, balls, or pins. The substrate bumps35may include or may be copper pillars or solders. FIG.9is a schematic cross-sectional view of a semiconductor package according to example embodiments. Referring toFIG.9, a semiconductor package5may include a package substrate1000, a connection substrate700on the package substrate1000, a stacked semiconductor chip structure CS3disposed on the connection substrate700, and one or more stacked chip structures CS1and CS2spaced apart from the stacked semiconductor chip structure CS3in a horizontal direction on the connection substrate700. The stacked chip structures CS1and CS2may be the same as or similar to the semiconductor package4described above with reference toFIG.8. For example, the stacked chip structures CS1and CS2of the present embodiment may include the stacked chip structures CS of the semiconductor packages1,2, and3described above with reference toFIGS.1through7. The semiconductor package5may further include intermediate connection conductive bumps760electrically connecting the package substrate1000and the connection substrate700and disposed between the package substrate1000and the connection substrate700, first connection conductive bumps35aelectrically connecting the connection substrate700and the stacked semiconductor chip structure CS3and disposed between the connection substrate700and the stacked semiconductor chip structure CS3, and second connection conductive bumps35belectrically connecting the connection substrate700and the stacked chip structures CS1and CS2and disposed between the connection substrate700and the stacked chip structures CS1and CS2. The semiconductor package5may further include a first underfill material layer50afilling a portion between the connection substrate700and the stacked semiconductor chip structure CS3and surrounding side surfaces of the first connection conductive bumps35aand a second underfill material layer50bfilling a portion between the connection substrate700and the stacked chip structures CS1and CS2and surrounding side surfaces of the second connection conductive bumps35b. The package substrate1000may include a package body1100, upper pads1200disposed at an upper portion of the package body1100and electrically connected to the connection conductive bumps760, lower pads1300disposed at a lower portion of the package body1100, a package internal wiring1350electrically connecting the upper pads1200and the lower pads1300and disposed inside the package body1100, and lower solder balls1400in contact with the lower pads1300under the lower pads1300. The connection substrate700may be an interposer substrate or a redistribution substrate. The connection substrate700may include a semiconductor substrate710, a through via720, a wiring region/layer730, and a third lower passivation layer750. The connection substrate700may include lower pads740disposed on a lower surface of the semiconductor substrate710and electrically connected to and in contact with the connection conductive bumps760and upper pads745disposed on an upper surface of the semiconductor substrate710and electrically connected to and in contact with the first and second connection conductive bumps35aand35b. The semiconductor substrate710may be formed of a semiconductor material such as silicon. The through vias720may be through silicon vias (TSVs) penetrating the semiconductor substrate710in a vertical direction. For example, each of the through vias720may include a conductive via pattern penetrating the semiconductor substrate710in a vertical direction and an insulating via spacer surrounding a side surface of the conductive via pattern. The wiring region730may be disposed on the semiconductor substrate710. The wiring region730may include an insulating layer732and wirings735aand735bembedded in the insulating layer732. In the connection substrate700, the wirings735aand735bmay include first wirings735aand second wirings735b. The first wirings735amay electrically connect some of the upper pads745and the through vias720. The second wirings735bmay electrically connect stacked semiconductor chip structure CS3and the stacked chip structures CS1and CS2. The third lower passivation layer750may be disposed on a bottom surface of the semiconductor substrate710. In one example, at least one of the stacked chip structures CS1and CS2may include the plurality of semiconductor chips described above with reference toFIGS.1through7and may include a volatile memory device such as a dynamic RAM (DRAM), a non-volatile memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a flash memory device, or a high-performance memory device such as a high bandwidth memory (HBM) or a hybrid memory cubic (HMC). In one example, at least one of the plurality of semiconductor chips of the stacked semiconductor chip structure CS3may be a logic chip such as a central processor (CPU), a graphic processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, or an application-specific IC (ASIC). According to example embodiments of the present inventive concept, the semiconductor package including the pads in direct contact with each other and coupled to each other and insulating layers in direct contact with each other and coupled each other may be provided. The stacked chip structure described above may have improved reliability, while being reduced in size or volume. According to example embodiments of the present inventive concept, since the connection wiring disposed on the rear surface of the lower semiconductor chip body is electrically connected to the internal circuit structure disposed on the front surface of the upper semiconductor chip body in a region in which the through-electrode structure is not disposed, thus improving power characteristics. While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims. | 39,817 |
11862614 | DETAILED DESCRIPTION FIG.1is a step flow chart of a manufacturing method of a micro LED display device S100according to an embodiment of the present disclosure. InFIG.1, the manufacturing method of the micro LED display device S100includes a covering step S101, a disposing step S102, a removing step S103and a curing step S104. FIG.2is a schematic view of the covering step S101according to the embodiment inFIG.1. According toFIGS.1and2, in the covering step S101, a plurality of conductive pads111are disposed on the substrate110, each of conductive connecting portions112is disposed on the each of the conductive pads111, and a transparent insulation layer130covers the substrate110. FIG.3is a schematic view of the disposing step S102according to the embodiment inFIG.1. Further, according toFIGS.1and3, in the disposing step S102, a plurality of micro LED units120are picked by a transposing unit (not shown), the transposing unit and the micro LED units120are disposed into the transparent insulation layer130, and the micro LED units120are disposed on the substrate110. In particular, the transparent insulation layer130is in a flow state in both of the covering step S101and the disposing step S102, wherein the processing temperature of the disposing step S102is between the glass transition temperature of the transparent insulation layer130and the curing temperature of the transparent insulation layer130. Therefore, the micro LED units120can be smoothly disposed into the transparent insulation layer130and electrically connected to the substrate110. According to the embodiment ofFIG.1, it should be mentioned that the micro LED units120are disposed on and electrically connected with the substrate110via the eutectic die bonding of the flip chip process, but the present disclosure is not limited thereto. In detail, the micro LED units120are pressed into the transparent insulation layer130in the disposing step S102, and electrodes of the micro LED units120contact with the conductive pads111of the substrate110. FIG.4is a schematic view of the removing step S103and the curing step S104according to the embodiment inFIG.1. Further, inFIGS.1and4, the transposing unit is removed from the transparent insulation layer130in the removing step S103, the transparent insulation layer130is cured in the curing step S104, and the transparent insulation layer130covers the micro LED units120to form the micro LED display device100. In detail, a time interval from the disposing step S102to the curing step S104is 10 seconds to 60 seconds. Therefore, the micro LED units120are fixed on the substrate110by forming the eutectic die bonding, and the luminous brightness of the micro LED units120and the display are controlled by the electrical signal of the substrate110. In particular, a required heating time for curing the transparent insulation layer130is longer than a required heating time for soldering by the conductive connecting portions112. Hence, in the disposing step S102, when the micro LED units120are connected to the conductive pads111, the transparent insulation layer130is not entirely cured, and the micro LED units120can be smoothly and electrically connected to the conductive pads111of the substrate110. According to the embodiment ofFIG.1, the required heating time for curing the transparent insulation layer130is about 10 minutes to 120 minutes. Moreover, when the micro LED units120are disposed into the transparent insulation layer130, the transparent insulation layer130is in the flow state in the disposing step S102, hence the micro LED units120can be disposed into the transparent insulation layer130, and the transparent insulation layer130is located between the conductive connecting portions112of the substrate110during the disposition of the micro LED units120by heating and pressing. A gap between the conductive connecting portions112is filled by the transparent insulation layer130so as to avoid the short circuit between the conductive connecting portions112. Further, the liquid damping effect can be obtained by the transparent insulation layer130in the flow state, which is favorable for fixing the location of the micro LED units120. Therefore, the skew disposition of the micro LED units120on the substrate110can be further avoided so as to promote the connection strength and the precision between the micro LED units120and the substrate110and increase the luminous efficiency. FIG.5is a schematic view of the micro LED display device100according to the embodiment inFIG.1. InFIG.5, the micro LED display device100includes the substrate110, the micro LED units120and the transparent insulation layer130. The substrate110includes the conductive pads111and the conductive connecting portions112, wherein the conductive pads111are disposed on the substrate110, and each of the conductive connecting portions112is correspondingly connected to one of the conductive pads111. Each of the micro LED units120includes a semiconductor epitaxial structure121and two electrodes (that is, a first electrode126and a second electrode127), and each of the electrodes is disposed on the semiconductor epitaxial structure121and connected to one of the conductive connecting portions112which are adjacent to each other. The transparent insulation layer130is disposed on the substrate110and covers the conductive pads111, the conductive connecting portions112and the micro LED units120, and the transparent insulation layer130is filled between the electrodes (that is, the first electrode126and the second electrode127) of each of the micro LED units120. In other words, a top of each of the micro LED units120is not exposed, and the top of each of the micro LED units120is entirely filled with the transparent insulation layer130. In general, a refractivity of a material of the transparent insulation layer130is higher than a refractivity of each of the micro LED units120. Hence, when a light-emitting surface of the top of each of the micro LED units120is covered by the transparent insulation layer130, the total reflection can be efficiently avoided to promote the display quality. InFIG.4, the transparent insulation layer130relative to a surface121aon each of the semiconductor epitaxial structures121is of a first thickness d1 and a second thickness d2, and the first thickness d1 is different from the second thickness d2. Furthermore, according to the embodiment ofFIG.5, the transparent insulation layer130relative to the surface121aon each of the semiconductor epitaxial structures121is separated into a peripheral area Ap and a covering area Ac, wherein the peripheral area Ap is of the first thickness d1, and the covering area Ac is of the second thickness d2. The first thickness d1 is larger than the second thickness d2, and the peripheral area Ap covers a portion of the surface121aon each of semiconductor epitaxial structures121. That is, in the disposing step S102, the micro LED units120are disposed into the transparent insulation layer130before the removing step S103and the curing step S104, so as a portion of the transparent insulation layer130corresponding to each of the micro LED units120being concave. In particular, the transparent insulation layer130can include a thermosetting resin material. A thickness range of the transparent insulation layer130is 10 micrometers to 50 micrometers, further can be 10 micrometers to 20 micrometers. It should be mentioned that the thickness range of the transparent insulation layer130is a maximal thickness from the transparent insulation layer130to the substrate110. Therefore, the transmittance of the transparent insulation layer130can be maintained at least 80% in the aforementioned thickness range. Each of the conductive connecting portions112can include a metal material or an anisotropic conductive adhesive material, wherein the metal material can be a gold material, a tin-lead material, an indium material or a combination of the aforementioned materials, but the material of each of the conductive connecting portions112is not limited thereto. FIG.6is a schematic view of the micro LED unit120according to the embodiment inFIG.1. InFIGS.5and6, each of the micro LED units120includes the semiconductor epitaxial structure121, the first electrode126and the second electrode127, wherein the semiconductor epitaxial structure121can include a first semiconductor122, a light-emitting layer123, a second semiconductor124and an insulation layer125, but the micro LED unit120is not limited to the embodiment ofFIG.6. According to the embodiment ofFIG.6, each of the first electrode126and the second electrode127of the micro LED unit120has a bonding surface, and the bonding surface of the first electrode126and the bonding surface of the second electrode127are substantially coplanar. In other words, the micro LED display device100of the present disclosure can be applied to the embodiment of the flip chip or the embodiment of the traditional lateral chip, but the present disclosure is not limited thereto. FIG.7is a disposing schematic view of the micro LED display device100according to the embodiment inFIG.1.FIG.8is another disposing schematic view of the micro LED display device100according to the embodiment inFIG.1. InFIGS.7and8, the micro LED units120can be disposed on the substrate110by two disposing forms. In particular, according to the embodiment ofFIG.7, three of the micro LED units120are disposed on one pixel area P, and each of the micro LED units120is separated into a red sub-pixel, a green sub-pixel and a blue sub-pixel; according to the embodiment ofFIG.8, six of the micro LED units120are disposed on one pixel area P, on which a number of the micro LED units120with the same color is two, that is, each color of the sub-pixels includes one micro LED unit120for reserve, but the present disclosure is not limited to the disposition as described herein. FIG.9is a schematic view of a micro LED display device200according to another embodiment of the present disclosure. InFIG.9, the micro LED display device200includes a substrate210, a plurality of micro LED units220and a transparent insulation layer230. The substrate210includes a plurality of conductive pads211and a plurality of conductive connecting portions212, wherein the conductive pads211are disposed on the substrate210, and each of the conductive connecting portions212is correspondingly connected to one of the conductive pads211. Each of the micro LED units220includes a semiconductor epitaxial structure221and two electrodes226,227, wherein the electrodes226,227are disposed on the semiconductor epitaxial structure221, and each of the electrodes226,227is connected to one of the conductive connecting portions212which are adjacent to each other. The transparent insulation layer230is disposed on the substrate210and covers the conductive pads211, the conductive connecting portions212and the micro LED units220, and the transparent insulation layer230is filled between the electrodes226,227of each of the micro LED units220. The transparent insulation layer230relative to a surface221aon each of the semiconductor epitaxial structures221is of a first thickness d1 and a second thickness d2, and the first thickness d1 is different from the second thickness d2. Furthermore, the transparent insulation layer230relative to the surface221aon each of the semiconductor epitaxial structures221is separated into a peripheral area Ap and a covering area Ac, wherein the peripheral area Ap is of the first thickness d1, and the covering area Ac is of the second thickness d2. The first thickness d1 is larger than the second thickness d2, and the peripheral area Ap covers a portion of the surface221aon each of semiconductor epitaxial structures221. In other words, a portion of the transparent insulation layer230corresponding to each of the micro LED units220is concave, and a surface of the transparent insulation layer230is uneven by a curing step of a manufacturing method of the micro LED display device. The uneven surface of the transparent insulation layer230may be regarded as a roughened surface structure of each of the micro LED units220, so as to broaden an effective light-emitting surface of each of the micro LED units220. Therefore, the luminous efficiency of the micro LED display device200can be promoted. Further, all of other structures and dispositions according to the embodiment ofFIG.9are the same as the structures and the dispositions according to the embodiment ofFIG.5, and will not be described again herein. FIG.10is a step flow chart of a manufacturing method of a micro LED display device S300according to still another embodiment of the present disclosure. InFIG.10, the manufacturing method of the micro LED display device S300includes a covering step S301, a disposing step S302, a removing step S303and a curing step S304. FIG.11is a schematic view of the covering step S301according to the embodiment inFIG.10. According toFIGS.10and11, in the covering step S301, a plurality of conductive pads311are disposed on the substrate310, each of conductive connecting portions312is disposed on the each of the conductive pads311, and a transparent insulation layer330covers the substrate310. FIG.12is a schematic view of the disposing step S302according to the embodiment inFIG.10. Further, according toFIGS.10and12, in the disposing step S302, a plurality of micro LED units320are picked by a transposing unit C, the transposing unit C and the micro LED units320are disposed into the transparent insulation layer330, and the micro LED units320are disposed on the substrate310. In particular, the transparent insulation layer330is in a flow state in both of the covering step S301and the disposing step S302, wherein the processing temperature of the disposing step S302is between the glass transition temperature of the transparent insulation layer330and the curing temperature of the transparent insulation layer330. Therefore, the micro LED units320can be smoothly disposed into the transparent insulation layer330and electrically connected to the substrate310. According to the embodiment ofFIG.12, the micro LED units320are disposed on and electrically connected with the substrate310via the eutectic die bonding of the flip chip process, but the present disclosure is not limited thereto. FIG.13Ais a schematic view of the removing step S303and a first transparent insulation area forming step S305according to the embodiment inFIG.10.FIG.13Bis a schematic view of a second transparent insulation area forming step S306according to the embodiment inFIG.10. Further, inFIGS.10,13A and13B, the curing step S304can include the first transparent insulation area forming step S305and the second transparent insulation area forming step S306. A time interval from the disposing step S302to the curing step S304is 10 seconds to 60 seconds. In particular, according to the embodiment ofFIG.13A, the time interval from the disposing step S302to the first transparent insulation area forming step S305is 10 seconds to 60 seconds. InFIGS.10and13A, the transposing unit C is removed from the transparent insulation layer330in the removing step S303, and the transparent insulation layer330is cured and covers the micro LED units320to form a plurality of first transparent insulation areas331and a plurality of disposing spaces S in the first transparent insulation area forming step S305. InFIG.13A, when the transposing unit C is removed from the transparent insulation layer330, the transparent insulation layer330flows inwards in a flow direction F owing to the gravity after the transparent insulation layer330stood for a while. Then, the transparent insulation layer330covers the micro LED units320. According toFIG.13B, in the second transparent insulation area forming step S306, a transparent insulation material (its reference numeral is omitted) is filled into the disposing spaces S and cured to form a plurality of second transparent insulation areas332, wherein the first transparent insulation areas331and the second transparent insulation areas332cover the micro LED units320. InFIGS.13A and13B, the micro LED display device300includes the substrate310, the micro LED units320and the transparent insulation layer330. The substrate310includes the conductive pads311and the conductive connecting portions312, wherein the conductive pads311are disposed on the substrate310, and each of the conductive connecting portions312is correspondingly connected to one of the conductive pads311. Each of the micro LED units320includes a semiconductor epitaxial structure321and two electrodes326,327, wherein the electrodes326,327are disposed on the semiconductor epitaxial structure321, and each of the electrodes326,327is connected to one of the conductive connecting portions312which are adjacent to each other. The transparent insulation layer330is disposed on the substrate310and covers the conductive pads311, the conductive connecting portions312and the micro LED units320, and the transparent insulation layer330is filled between the electrodes326,327of each of the micro LED units320. In detail, the transparent insulation layer330includes the first transparent insulation areas331and the second transparent insulation areas332. The first transparent insulation areas331cover the substrate310and a portion of a surface321aof each of the semiconductor epitaxial structures321. The second transparent insulation areas332are connected to the first transparent insulation areas331, and cover on the surface321aof each of the semiconductor epitaxial structures321. Furthermore, the transparent insulation layer330relative to the surface321aon each of the semiconductor epitaxial structures321is separated into a peripheral area Ap and a covering area Ac, and the peripheral area Ap covers a portion of the surface321aon each of semiconductor epitaxial structures321. According to the embodiment ofFIG.13B, the covering area Ac is covered by the first transparent insulation areas331and the second transparent insulation areas332of the transparent insulation layer330, and the peripheral area Ap is only covered by the first transparent insulation areas331. Moreover, each of the first transparent insulation areas331can include a thermosetting resin material, and each of second transparent insulation areas332can include the thermosetting resin material or a quantum dot material. A material of each of the first transparent insulation areas331can be different from a material of each of the second transparent insulation areas332, but the present disclosure is not limited thereto. Further, the quantum dot material can be similar to a color filter to convert the color of the light. For example, the micro LED unit320which is a blue sub-pixel can be converted to a red sub-pixel or a green sub-pixel by the quantum dot material, and the light converted by the quantum dot material is with high color purity. FIG.14is a step flow chart of a manufacturing method of a micro LED display device S400according to another embodiment of the present disclosure. InFIG.14, the manufacturing method of the micro LED display device S400includes a covering step S401, a disposing step S402, a first transparent insulation area forming step S403, a removing step S404and a second transparent insulation area forming step S405. In detail, each of the covering step S401and the disposing step S402according to the embodiment ofFIG.14can be referred to the embodiments ofFIGS.11and12. Because the covering step S401and the disposing step S402according to the embodiment ofFIG.14are the same as the covering step S301and the disposing step S302according to the embodiment ofFIG.10, they will not be described again herein. FIG.15Ais a schematic view of the first transparent insulation area forming step S403and the removing step S404according to the embodiment inFIG.14. InFIGS.14and15A, a transparent insulation layer430(shown inFIG.15B) is cured to form a plurality of first transparent insulation areas431and a plurality of disposing spaces S in the first transparent insulation area forming step S403, and the transposing unit (not shown) is removed from the transparent insulation layer430in the removing step S404. In particular, when micro LED units420are disposed on a substrate410by the transposing unit, the first transparent insulation area forming step S403is performed to cure the transparent insulation layer430to form the first transparent insulation areas431. Then, after curing the transparent insulation layer430, the removing step S404is performed to remove the transposing unit to form the disposing spaces S, thereby the disposing spaces S can be obtained without the exposing step, the developing step and the etching step, and a surface421aas a portion of the top surface of each semiconductor epitaxial structure421is exposed. Further, the sequence of the removing step and the first transparent insulation area forming step can be altered on demand so as to flexibly form the disposing spaces S according to the embodiment toFIG.13Aor the disposing spaces S according to the embodiment toFIG.15A. FIG.15Bis a schematic view of the second transparent insulation area forming step S405according to the embodiment inFIG.14. According toFIGS.14and15B, in the second transparent insulation area forming step S405, a transparent insulation material (its reference numeral is omitted) is filled into the disposing spaces S and cured to form a plurality of second transparent insulation areas432, wherein the first transparent insulation areas431and the second transparent insulation areas432(that is, the transparent insulation layer430) cover the micro LED units420. Further, all of other structures and dispositions according to the embodiments ofFIGS.15A and15Bare the same as the structures and the dispositions according to the embodiments ofFIGS.13A and13B, and will not be described again herein. InFIGS.15A and15B, the micro LED display device400includes the substrate410, the micro LED units420and the transparent insulation layer430. The substrate410includes a plurality of conductive pads411and a plurality of conductive connecting portions412, wherein the conductive pads411are disposed on the substrate410, and each of the conductive connecting portions412is correspondingly connected to one of the conductive pads411. Each of the micro LED units420includes the semiconductor epitaxial structure421and two electrodes426,427, wherein the electrodes426,427are disposed on the semiconductor epitaxial structure421, and each of the electrodes426,427is connected to one of the conductive connecting portions412which are adjacent to each other. The transparent insulation layer430is disposed on the substrate410and covers the conductive pads411, the conductive connecting portions412and the micro LED units420, and the transparent insulation layer430is filled between the electrodes426,427of each of the micro LED units420. In detail, the transparent insulation layer430includes the first transparent insulation areas431and the second transparent insulation areas432. The first transparent insulation areas431cover the substrate410and a portion of the surface421aof each of the semiconductor epitaxial structures421. The second transparent insulation areas432are connected to the first transparent insulation areas431, and cover on the surface421aof each of the semiconductor epitaxial structures421. Furthermore, the transparent insulation layer430relative to the surface421aon each of the semiconductor epitaxial structures421is separated into a peripheral area Ap and a covering area Ac, and the peripheral area Ap covers the portion of the surface421aon each of semiconductor epitaxial structures421. According to the embodiment ofFIG.15B, the covering area Ac is covered by the second transparent insulation areas432, and the peripheral area Ap is covered by the first transparent insulation areas431. Further, all of other structures and dispositions according to the embodiment ofFIG.14are the same as the structures and the dispositions according to the embodiments ofFIGS.5,10, and will not be described again herein. In summary, by the disposition of the transparent insulation layer, the short circuit owing to gap-free between the conductive connecting portions can be avoided, and the issue that the skew disposition of each of the micro LED units on the substrate can be solved, therefore the connection strength and the precision between the micro LED units and the substrate can be promoted, and further to increase the luminous efficiency of the micro LED units. The foregoing description, for purpose of explanation, has been described with reference to specific examples. It is to be noted that Tables show different data of the different examples; however, the data of the different examples are obtained from experiments. The examples were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various examples with various modifications as are suited to the particular use contemplated. The examples depicted above and the appended drawings are exemplary and are not intended to be exhaustive or to limit the scope of the present disclosure to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. | 25,485 |
11862615 | DETAILED DESCRIPTION Various embodiments of SSL devices and associated methods of manufacturing SSL devices are described below. The term “SSL emitter” generally refers to solid state components that convert electrical energy into electromagnetic radiation in the visible, ultraviolet, infrared and/or other spectra. SSL emitters include “LEDs,” which are semiconductor diodes that convert electrical energy into electromagnetic radiation in a desired spectrum. The term “phosphor” generally refers to a material that can continue emitting light after exposure to energy (e.g., electrons and/or photons). A person skilled in the relevant art will also understand that the technology may have additional embodiments and/or may be practiced without several of the details of the embodiments described below with reference toFIGS.3A,3B,4A,5A and6-11. FIG.3Ais a cross-sectional view andFIG.3Bis a top plan view of an SSL device100in accordance with an embodiment of the technology.FIG.3A, more specifically, is a cross section along line3A-3A ofFIG.3B. Referring toFIG.3A, this particular embodiment of the SSL device100includes a support110and a plurality of SSL emitters120(identified individually by reference numbers120aand120b). The SSL device100can optionally include a converter material130over the SSL emitters120and a conditioning element140(e.g., a lens and/or diffuser). In this embodiment, the SSL emitters120are arranged on the support110such that size, shape, spacing, intensity and/or other parameter of the SSL emitters in a central region of the emitter array is different than at least one of the corresponding parameters of the SSL emitters in a peripheral region of the emitter array. The support110can have a front surface112, a back surface114, a first portion116a, and a second portion116b. The first and second portions116a-bare not necessarily separate components, but rather they can be integral sectors of the same printed circuit device, metal base, or other type of support structure. Referring toFIGS.3A and3B, the front surface112of the support110can have a first emission area118aand a second emission area118bcorresponding to the first portion116aand the second portion116bof the support110, respectively. The second emission area118bis outward of the first emission area118a, and in several embodiments the second emission area118bsurrounds the first emission area118a. The first emission area118acan accordingly define a central region and the second emission area118bcan define a peripheral region. The second emission area118b, more specifically, can be the peripheral-most region of the active lighting area of the SSL device100. The SSL emitters120can include a set of first SSL emitters120ain the first emission area118aand a set of second SSL emitters120bin the second emission area118b. All of the first and second SSL emitters120a-bcan be identical, or in other embodiments the first SSL emitters120acan have a different size, shape, color, intensity and/or other parameter than the second SSL emitters120b. The parameters of the SSL emitters120a-bcan also be mixed in both regions118aand118b. As described in further detail below, the first and second SSL emitters120a-bcan be arranged in the first and second emission areas118a-bto provide a more uniform light output than conventional multi-LED devices. The first set of SSL emitters120acover a first proportion of the first emission area118ato define a first coverage area ratio and the second set of SSL emitters120bcover a second proportion of the second emission area118bto define a second coverage area ratio different than the first coverage area ratio. In several embodiments of the SSL device100, the first coverage area ratio is less than the second coverage area ratio. The coverage area ratios for each of the first and second emission areas118aand118bare selected to provide the desired light distribution across the array of SSL emitters. In applications that require additional output at the perimeter of the array, the second coverage area ratio is selected to be sufficiently greater than the first coverage area ratio such that the combined light from the first and second emission areas118aand118bis more uniform across the array compared to arrays that have a constant coverage area ratio from the center to the perimeter of the array. The SSL device100is not limited to having only two emission area118aand118b, but rather the array can be divided into any number of emission areas in which the coverage area ratios are selected to provide a desired light intensity distribution. This can be useful in arrays where the light output at the corners of the array is substantially less than center of the array or at the midpoints along the sides of the array perimeter. For example, one embodiment of the SSL device100shown inFIG.3Bhas third emission areas118cat the corners of the array with a third coverage area ratio greater than either first or the second coverage area ratios. The different coverage area ratios of the SSL emitters in different emission areas of the array can be achieved by appropriately selecting one or more of the following: (a) density of SSL emitters, (b) spacing between neighboring SSL emitters, (c) vacant regions between emission areas, (d) size of the SSL emitters, (e) shape of the SSL emitters, (f) intensity of the SSL emitters, and/or other parameters related to the cumulative light output of the SSL emitter array. For example,FIG.3Bshows that neighboring (e.g., adjacent) first SSL emitters120aare spaced apart by a first distance S1 and neighboring second SSL emitter120bare spaced apart by a second distance S2 less than S1. As shown inFIG.3B, the second SSL emitters120bcan be spaced apart from other neighbors in the second emission area118bby other distances as well, but when viewed as a whole the number of second SSL emitters120bper unit surface area (e.g., the density of SSL emitters) is greater in the second emission area118bthan that of first SSL emitters120ain the first emission area118a. The spacing between the SSL emitters120can vary in one dimension of the array (e.g., one-dimensional spacing), or as shown inFIG.3Bthe spacing can vary in two dimensions of the array (e.g., two-dimensional spacing). Referring toFIG.3A, the individual SSL emitters120a-bin both the first and second emission areas118a-bhave a primary emission direction E along which an intensity of light from the SSL emitters120a-bis the highest. The primary emission direction E of each emitter is generally perpendicular to the face of each emitter. In the embodiment illustrated inFIG.3A, the primary emission direction E of the first SSL emitters120ain the first emission area118ais at least substantially the same direction as the primary emission direction E of the second SSL emitters120bin the second emission area118b. The first and second emission areas118a-bthat define the central and peripheral regions accordingly face outwardly such that light projects away from the first and second emission areas118a-bof the support110. FIG.4Ais a cross-sectional view illustrating the operation of an embodiment of the SSL device100described above with reference toFIGS.3A and3B, andFIG.4Bis a cross-sectional view illustrating the operation of the conventional multi-LED device50described above with reference toFIGS.2A and2B.FIGS.4A and4Bshow the light received along a plane at points B above the perimeter of the array and at a point A above the center of the array from within a distance of half of the total array width. The intensity of light from a given SSL emitter is greatest along its primary emission axis (i.e., the axis perpendicular to the face of the SSL emitter) and decreases as a square of the distance from the SSL emitter. Referring toFIG.4B, the intensity of light at points B for the multi-LED device50is less than the intensity of light at point A because point A receives more light on or near the primary emission axes of more LEDs than points B, and point A is closer to more of the LEDs than points B. Several embodiments of the SSL device100shown inFIG.4Areduce or eliminate the difference in the light intensity between point A and points B because the different coverage area ratios of the first and second SSL emitters120a-bdecreases the density of SSL emitters proximate to point A relative to points B. FIG.5Ais a plot of the intensity distribution for an embodiment of the SSL device100, andFIG.5Bis a plot of the intensity distribution for the multi-LED device50. In comparingFIGS.5A and5B, the light intensity is higher and more uniform across more of the array area of the SSL device100than the conventional multi-LED device50. Several embodiments of the SSL device100accordingly provide a highly uniform light output across a significant portion of the surface area of the array that reduces dark spots or other irregularities of the light output. Additionally, several embodiments of the SSL device100can provide such uniformity without a diffusion material over the center of the array that reduces the light output from the center of the array. Several embodiments of the SSL device100are thus more efficient than conventional multi-LED devices with diffusion layers over the center of the array. FIG.6is a top plan view of an SSL device100in accordance with another embodiment of the technology. In this embodiment, the SSL emitters120are arranged such that the coverage area ratio increases progressively with increasing distance from the center of the SSL array. For example, the spacing between each successive row and/or column of SSL emitters120can decrease from the center such that S1>S2>S3 . . . Sn−1>Sn, where S1 is the spacing between the center-most SSL emitter120and adjacent emitters and Sn is the spacing between the peripheral-most SSL emitters120and adjacent emitters toward the center of the array. The spacing between the SSL emitters120in the embodiment shown inFIG.6can decrease symmetrically along both the X and Y dimensions (i.e., two-dimensional coverage area ratio variation) or along only one of the X or Y dimensions (i.e., one-dimensional coverage area ratio variation). In other embodiments, the spacing between neighboring or adjacent SSL emitters120can change asymmetrically along one or both of the X and/or Y dimensions of the array. The SSL emitter array of the SSL device100shown inFIG.6can have any number of different emission areas depending on the application. For example, the surface of the array can be mapped into three emission areas that define the first emission area118a, second emission area118b, and third emission area118c. The SSL emitters120can accordingly have first SSL emitters120ain the first emission area118a, second SSL emitters120bin the second emission area118b, and third SSL emitters120cin the third emission area118c. The embodiment of the SSL device100shown inFIG.6can have a first coverage area ratio in the first emission area118aand a second coverage area ratio in the second emission area118bgreater than the first coverage area. Similarly, the SSL device100shown inFIG.6can have a third coverage area ratio in the third emission area118cgreater than the second coverage area ratio. The SSL device100can also have fourth emission areas118din the corners that have a fourth coverage area ratio higher than the second coverage area ratio, and in some embodiments the fourth coverage area ratio is also greater than the third coverage area ratio. FIG.7is a schematic view illustrating a cross-section of the SSL device100shown inFIG.6. The spacing S1, S2, Sn between adjacent SSL emitters120can be determined empirically using light output models. For example, the output of each SSL emitter120can be modeled for a number of points P−n . . . P0 . . . Pn at a target surface T spaced apart from the array by a distance h. The sum of the light outputs from the all of the SSL emitters120for each point is then determined, and the arrangement of the SSL emitters120is adjusted such that the cumulative light output at the points across the target surface T provides the desired light intensity distribution across the SSL emitter array. In another embodiment, the spacing between adjacent SSL emitters120can be calculated assuming that the light from the SSL emitters120has a Lambertian Angular distribution. FIG.8is a top plan view of another embodiment of the SSL device100in accordance with the technology in which the SSL emitters120are arranged along radians projecting from the center of the array instead of in rows and columns of an X-Y grid. In the embodiment of the SSL device shown inFIG.8, the SSL emitters120are arranged along16radians spaced apart from each other by 22.5°, and the number and spacing of the SSL emitters120can vary along different radians. The arrangement of SSL emitters120shown inFIG.8is merely illustrative such that many other configurations of SSL emitters120along fewer or more radians can be selected in a manner similar to the process described above with respect toFIG.7. FIG.9is a top plan view of an SSL device100in accordance with another embodiment of the technology. In this embodiment, the SSL emitter array has a first emission area118awith first SSL emitters120a, a second emission area118bwith second SSL emitters120b, and a vacant region119between the first and second emission areas118a-b. The first and second SSL emitters120a-bcan be arranged in the first and second emission areas118a-bsuch that the first coverage area ratio in the first emission area118ais less than the second coverage area ratio in the second emission area118bas described above with respect to other embodiments of the SSL device100. However, in some embodiments, the vacant region119can be configured such that coverage area ratio of the first and second emission areas118a-bis the same. FIG.10is a top plan view of another embodiment of the SSL device100in accordance with the technology. In this embodiment, the SSL device100has a plurality of first SSL emitters120ahaving a first size in the first emission area118aand a plurality of second SSL emitters120bin the second emission area118bhaving a second size different than the first size. For example, the second size of the second SSL emitters120bcan be greater than the first size of the first SSL emitters120asuch that the coverage area ratio of the second SSL emitters120bin the second emission area118bis greater than the coverage area ratio of the first SSL emitters120ain the first emission area118a. In the embodiment shown inFIG.10, the first and second SSL emitters120a-bare also arranged along eight radians R1-R8spaced from each other by 45°, the first SSL emitters120aare spaced apart from each other by a distance of S1, and the second SSL emitters120bare spaced apart from the first SSL emitters120aby distance S2 less than S1 along radians R1, R3, R5and R7. In other embodiments, the SSL emitters120a-bof different sizes can be spaced apart from each other by the same distance and/or be arranged in an X-Y grid or other configuration. FIG.11is a side cross-sectional view of another embodiment of the SSL device100in accordance with the technology. In this embodiment, the SSL device100has a support110with first-third portions116a-c, respectively, that define first-third emission areas118a-c, respectively. The support110is configured such that the second emission area118bis an inclined surface that slopes downwardly from the first emission area118ato the third emission area118c. The SSL device100inFIG.11also has a set of first SSL emitters120ain the first emission area118a, a set of second SSL emitters120bin the second emission area118b, and a set of third SSL emitters120cin the third emission area120c. The coverage ratios of the SSL emitters120b-cin the second and third emission areas118b-ccan be different from each other and different from the coverage area ratio in the first emission area118a. In the embodiment shown inFIG.11, the coverage area ratios in the second and third emission areas118b-care equal to each other and greater than the coverage area ratio in the first emission area118a. The first-third emission areas118a-call face outwardly relative to the SSL device100such that the primary emission directions E of the individual SSL emitters120a-call project away from the central region of the support110. Several additional configurations of first and second emitters120a-bare also in accordance with the technology. For example, an SSL device can have a number “n” of first emitter(s)120aand a number “p” of second emitters120bwhere p>n such that the overall light distribution corresponds to a desired profile. In one embodiment, n can equal 1 and p can be 2 or more. In other embodiments, n can be greater than 1 and p greater than n. The support110of any of the foregoing embodiments of the technology can be a printed circuit board having traces that define leads for providing power to the SSL emitters120. In an alternative embodiment, the support110can be a base made from copper, aluminum, or another type of metal that has a first metal portion defining either an anode or a cathode, and a second metal portion electrically isolated from the first portion that defines the other of the cathode or anode. In still other embodiments, the support110can have a base made from ceramic or another suitable dielectric material and traces on the base. The front surface112of the support110can be flat, or in other embodiments the support110can include a plurality of depressions in which one or more of the SSL emitters120are positioned. The depressions, for example, can be cavities sized and shaped to receive a single SSL emitter120. Suitable supports110for the SSL device110are shown and described in commonly owned U.S. Pat. No. 8,552,438, entitled “Multi-Lens Solid State Lighting Devices,” which is incorporated herein by reference. The SSL emitters120of any of the foregoing embodiments can be LEDs configured to emit light in a desired spectrum. For example, the SSL emitters120can be configured to emit light in one or more of the following spectra: visible spectrum (e.g., from about 450 nm to about 650 nm); infrared spectrum (e.g., from about 680 nm to about 970 nm); near infrared spectrum (e.g., from about 1050 nm to about 1550 nm); and/or other suitable spectra. The SSL emitters120can be the same as the LED4shown inFIG.1B; in other embodiments, the SSL emitters120can be vertical type LEDs in which one contact can be wire bonded to either the anodic or cathodic leads and the other contact can be surface mounted to the other of the anodic or cathodic leads. For example, contacts formed from copper (Cu), aluminum (Al), tungsten (W), stainless steel or other suitable metals or metal alloys on the backside of the SSL emitters120can be surface mounted to corresponding surface mount contacts on the support110. In other embodiments, an n-type GaN material at the bottom of the SSL emitters120can define the backside contacts for surface mounting the SSL emitters to one of the leads. Suitable surface mounting configurations are shown and described in commonly owned U.S. Pat. No. 8,441,020 entitled “Light Emitting Diode Wafer-Level Package with Self-Aligning Features,” which is incorporated herein by reference. The optional converter material130of any of the foregoing embodiments (e.g.,FIG.3A) is selected to emit light at a wavelength that combines with the light from the SSL emitters120to create a desired color of light. The converter material130, for example, can have a composition that emits light at a desired wavelength under stimulation such that the combination of the emissions from the SSL emitters120and the converter material130emulates a white light. For example, in one embodiment, the converter material130can include a phosphor containing cerium(III)-doped yttrium aluminum garnet (YAG) at a particular concentration for emitting a range of colors including green, yellow and/or red under photoluminescence. In other embodiments, the converter material130can include neodymium-doped YAG, neodymium-chromium double-doped YAG, erbium-doped YAG, ytterbium-doped YAG, neodymium-cerium double-doped YAG, holmium-chromium-thulium triple-doped YAG, thulium-doped YAG, chromium(IV)-doped YAG, dysprosium-doped YAG, samarium-doped YAG, terbium-doped YAG, and/or other suitable phosphor compositions. When light and/or energized particles from the SSL emitters120irradiates the converter material130, the phosphor is energized and emits light with desired characteristics. The conditioning element140of any of the foregoing embodiments (e.g.,FIG.3A) is optional and can be a lens configured to focus the light or a diffuser that diffuses the light. The conditioning element140can include a transmissive material made from silicone, polymethylmethacrylate (PMMA), resin, or other materials with suitable properties for transmitting the radiation emitted by the SSL emitters120. The conditioning element140can further include an optional converter material, such as phosphor, that emits light at a different frequency to produce the perception of white light or another desired color to the human eye. The converter material in the conditioning element140can be in addition to or in lieu of the converter material130. From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, any of the features of the embodiments of the SSL devices100shown inFIGS.3A,3B,4A,5A and6-11can be interchanged and matched together to provide the desired light intensity distribution. Accordingly, the invention is not limited except as by the appended claims. | 21,874 |
11862616 | DETAILED DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so as to fully convey the spirit of the present disclosure to those skilled in the art to which the present disclosure pertains. Accordingly, the present disclosure is not limited to the embodiments disclosed herein and can also be implemented in different forms. In the drawings, widths, lengths, thicknesses, and the like of devices can be exaggerated for clarity and descriptive purposes. When an element or layer is referred to as being “disposed above” or “disposed on” another element or layer, it can be directly “disposed above” or “disposed on” the other element or layer or intervening devices or layers can be present. Throughout the specification, like reference numerals denote like devices having the same or similar functions. A light emitting device according to one or more embodiments includes a short wavelength light emitting portion, a long wavelength light emitting portion, and a coupling layer combining the short wavelength emitting portion and the long wavelength light emitting portion. Each of the short wavelength light emitting portion and the long wavelength light emitting portion includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The active layer of the long wavelength light emitting portion contains more In than the active layer of the short wavelength light emitting portion, and the short wavelength light emitting portion emits light of a shorter wavelength than that of light emitted from the long wavelength light emitting portion. Since the short wavelength light emitting portion and the long wavelength light emitting portion are combined, a light emitting device capable of emitting multi wavelength light, such as white light, may be provided without a phosphor. The light emitting device may further include a substrate disposed on a side of the short wavelength light emitting portion or the long wavelength light emitting portion. In at least one variant, the short wavelength light emitting portion may emit blue light, and the long wavelength light emitting portion may emit yellow light. In another variant, the short wavelength light emitting portion may also emit ultraviolet light. Light emitted from the long wavelength light emitting portion may be emitted through the short wavelength light emitting portion. As such, light loss may be reduced. The coupling layer may be an insulation layer or a transparent electrode. The light emitting device may further include a first bonding pad commonly electrically connected to the short wavelength light emitting portion and the long wavelength light emitting portion and a second bonding pad and a third bonding pad electrically connected to the short wavelength light emitting portion and the long wavelength light emitting portion, respectively. The light emitting device may be flip-bonded using the first, second, and third bonding pads. In at least one variant, the first bonding pad is commonly electrically connected to the first conductivity type semiconductor layers of the short wavelength light emitting portion and the long wavelength light emitting portion. The second bonding pad is electrically connected to the second conductivity type semiconductor layer of the short wavelength light emitting portion. The third bonding pad is electrically connected to the second conductivity type semiconductor layer of the long wavelength light emitting portion. Moreover, the light emitting device may further include buried vias electrically connecting the first, second, and third bonding pads to the first and second conductivity type semiconductor layers. The light emitting device may further include a planarization layer, in which the buried vias may pass through the planarization layer, and the first, second, and third bonding pads may be disposed on the planarization layer. In another variant, the first bonding pad is commonly electrically connected to the second conductivity type semiconductor layers of the short wavelength light emitting portion and the long wavelength light emitting portion. The second bonding pad is electrically connected to the second conductivity type semiconductor layer of the short wavelength light emitting portion, and the third bonding pad is electrically connected to the second conductivity type semiconductor layer of the long wavelength light emitting portion. In further another variant, the short wavelength light emitting portion and the long wavelength light emitting portion may be independently driven. In another variant, the short wavelength light emitting portion and the long wavelength light emitting portion may be driven together. The light emitting device may further include a substrate, and a plurality of light emitting cells disposed on the substrate. Each of the light emitting cells may include the short wavelength light emitting portion, the long wavelength light emitting portion, and the coupling layer. Moreover, the light emitting device may further include connectors for electrically connecting the plurality of light emitting cells. In another variant, the plurality of light emitting cells may be connected in series-parallel to one another. A method of fabricating a light emitting device according to one or more embodiments includes steps of forming a first LED stack on a first substrate; forming a second LED stack on a second substrate, combining the first LED stack and the second LED stack using a coupling layer, and removing the first substrate or the second substrate. Each of the first and second LED stacks includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and the first LED stack is configured to emit light of a shorter wavelength than that of light emitted from the second LED stack. In at least one variant, the first LED stack may be configured to emit blue light, and the second LED stack may be configured to emit yellow light. The method of fabricating a light emitting device may further include forming a first transparent electrode and a second transparent electrode on the first LED stack and the second LED stack, respectively, before combining the first LED stack and the second LED stack. The method of fabricating a light emitting device may further include forming a lower p-electrode pad on the first transparent electrode. In addition, the method of fabricating a light emitting device may further include; before combining the first LED stack and the second LED stack, exposing the first conductivity type semiconductor layer of the first LED stack by patterning the first transparent electrode and the first LED stack; and forming a lower n-electrode on the exposed first conductivity type semiconductor layer. The method of fabricating a light emitting device may further include forming an upper p-electrode pad on the second transparent electrode. Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. FIG.2is a schematic cross-sectional view illustrating a light emitting device according to one or more embodiments. Referring toFIG.2, the light emitting device according to one or more embodiments includes a short wavelength light emitting portion BL, a long wavelength light emitting portion YL, and an insulation layer50. The short wavelength light emitting portion BL may include a first LED stack20, and may further include a first transparent electrode29. The long wavelength light emitting portion YL may include a second LED stack30, and may further include a second transparent electrode39. The first LED stack20may include a first conductivity type semiconductor layer23, an active layer25, and a second conductivity type semiconductor layer27. In some forms, each of the first conductivity type semiconductor layer23, the active layer25, and the second conductivity type semiconductor layer27may be a gallium nitride-based semiconductor layer. Additionally, or alternatively, each of the first and second conductivity type semiconductor layers23and27may be a single layer or a multiple layer. The active layer25may have a multiple quantum well structure, and a material and a thickness thereof may be selected to emit light in a wavelength range of, for example, 365 nm to 460 nm. The second LED stack30may include a first conductivity type semiconductor layer33, an active layer35, and a second conductivity type semiconductor layer37. In some forms, each of the first conductivity type semiconductor layer33, the active layer35, and the second conductivity type semiconductor layer37may be a gallium nitride-based semiconductor layer. Additionally, or alternatively, each of the first and second conductivity type semiconductor layers33and37may be a single layer or multiple layers. The active layer35may have a multiple quantum well structure, and a material and a thickness thereof may be selected to emit light in a wavelength range of, for example, 500 nm to 600 nm. A well layer of the active layer35may contain more Indium (In) than a well layer of the active layer25. The first conductivity type semiconductor layers23and33of the LED stacks20and30are n-type semiconductor layers, respectively, and the second conductivity type semiconductor layers27and37thereof are p-type semiconductor layers. The first transparent electrode29is in contact with the second conductivity type semiconductor layer27of the first LED stack20. The first transparent electrode29may be formed using a transparent conductive oxide (TCO) or a metal layer. The transparent conductive oxide layer may include SnO2, InO2, ITO, ZnO, IZO, or the like. The first transparent electrode29transmits light generated in the first LED stack20or the second LED stack30. The second transparent electrode39is in contact with the second conductivity type semiconductor layer37of the second LED stack30. The second transparent electrode39may be formed using a transparent conductive oxide (TCO) or a metal layer. The transparent conductive oxide layer may include SnO2, InO2, ITO, ZnO, IZO, or the like. The second transparent electrode39transmits light generated in the first LED stack20or the second LED stack30. The insulation layer50is disposed between the short wavelength light emitting portion BL and the long wavelength light emitting portion YL. The insulation layer50may combine the short wavelength light emitting portion BL and the long wavelength light emitting portion YL. For example, the insulation layer50may combine the short wavelength light emitting portion BL and the long wavelength light emitting portion YL between the first transparent electrode29and the second transparent electrode39. The insulation layer50may be formed of a transparent organic material layer or a transparent inorganic material layer. The organic material layer may be SU8, poly(methylmethacrylate); PMMA, polyimide, parylene, benzocyclobutene (BCB), or the like, and the inorganic material layer may include Al2O3, SiO2, SiNx, or the like. In addition, the insulation layer50may be formed of spin-on-glass (SOG). In one or more embodiments, the light emitting device, as illustrated inFIG.3, may further include a first substrate21. The first substrate21may be disposed on a side of the short wavelength light emitting portion BL. The first substrate21may be a substrate that can be used to grow the first LED stack20, such as a sapphire substrate, a SiC substrate, or a GaN substrate. In one or more embodiments, the first substrate21may be a flat sapphire substrate, but may be a patterned sapphire substrate. Light generated from the short wavelength light emitting portion BL and the long wavelength light emitting portion YL may be emitted to the outside through the first substrate21, and thus, the first substrate21may be a transparent substrate that transmits light generated from the short wavelength light emitting portion BL and the long wavelength light emitting portion YL. However, the inventive concepts are not limited thereto, and light generated from the short wavelength emission portion BL and the long wavelength emission portion YL may be emitted to an opposite side of the first substrate21. In this case, the first substrate21may be an opaque substrate. In another exemplary embodiment, the light emitting device, as illustrated inFIG.4, may further include a second substrate31. The second substrate31may be disposed on a side of the long wavelength light emitting portion YL. The second substrate31may be a substrate that can be used to grow the second LED stack30, such as a sapphire substrate, a SiC substrate, or a GaN substrate. In one or more embodiments, the second substrate31may be a flat sapphire substrate, but may be a patterned sapphire substrate. Light generated from the short wavelength light emitting portion BL and the long wavelength light emitting portion YL may be emitted to the outside through the second substrate31, and thus, the second substrate31may be a transparent substrate that transmits light generated from the short wavelength light emitting portion BL and the long wavelength light emitting portion YL. However, the inventive concepts are not limited thereto, and light generated from the short wavelength light emitting portion BL and the long wavelength light emitting portion YL may be emitted to an opposite side of the second substrate31. In this case, the second substrate31may be an opaque substrate. The light emitting device may be formed by, for example, bonding the first transparent electrode29and the second transparent electrode39using the insulation layer50so that the first transparent electrode29and the second transparent electrode39face each other, after growing the first conductivity type semiconductor layers23and33, the active layers25and35, and the second conductivity type semiconductor layers27and37on the first substrate21and the second substrate31, respectively, and forming the first transparent electrode29and the second transparent electrode39on the second conductivity type semiconductor layers27and37, respectively. Thereafter, the second substrate31may be separated to fabricate the light emitting device as illustrated inFIG.3, or the first substrate21may be separated to fabricate the light emitting device as illustrated inFIG.4. Both the first substrate21and the second substrate31are removed, and another substrate may be attached. Before the bonding process, the first LED stack20or the second LED stack30may be patterned, and additional electrode pads may be formed on the first transparent electrode29or the second transparent electrode39. FIG.5is a schematic cross-sectional view illustrating a light emitting device according to one or more embodiments. Referring toFIG.5, the light emitting device according to the exemplary embodiment is substantially similar to the light emitting device ofFIG.4, but an insulation layer50combines a first transparent electrode29and a first conductivity type semiconductor layer33in the exemplary embodiment. An active layer35is located on the first conductivity type semiconductor layer33, and a second conductivity type semiconductor layer37is located on the active layer35. A second transparent electrode39may be located on the second conductivity type semiconductor layer37. In the illustrated embodiment, light generated in the second LED stack30may be emitted through a first substrate21, and in this case, light does not need to proceed through the second transparent electrode39. Accordingly, a reflective metal layer (not shown) may be disposed on the second conductivity type semiconductor layer37, instead of the second transparent electrode39or in addition to the second transparent electrode39. The light emitting device according to the illustrated exemplary embodiment may be fabricated by, for example, combining the second LED stack30and the first LED stack20after transferring the second LED stack30and the second transparent electrode39grown on a second substrate31onto a temporary substrate, and separating the second substrate31first. The temporary substrate may be separated after the second LED stack30and the first LED stack20are combined, and thus, a light emitting device in which the second transparent electrode39is disposed far from the insulation layer50may be provided. The light emitting device, in which the first substrate21remains and the second substrate31is removed, is exemplarily described, but through the similar process, the second substrate31may remain, and the first substrate21may be removed, as illustrated inFIG.6. In the exemplary embodiment ofFIG.6, the second transparent electrode39will be transparent to light generated in the first LED stack20or the second LED stack30. In addition, when light generated in the first LED stack20and the second LED stack30is emitted to the outside through the second substrate31in the exemplary embodiment ofFIG.6, a reflective metal layer may be disposed on a second conductivity type semiconductor layer27, instead of the first transparent electrode29, or in addition to the first transparent electrode29. FIG.7is a schematic cross-sectional view illustrating a light emitting device according to one or more embodiments. Referring toFIG.7, the light emitting device according to the exemplary embodiment is substantially similar to the light emitting device described with reference toFIG.2, but a short wavelength light emitting portion BL and a long wavelength light emitting portion YL are combined by a transparent electrode59instead of an insulation layer50in the exemplary embodiment. For example, the transparent electrode59ofFIG.7may be formed by directly bonding the first transparent electrode29and the second transparent electrode39ofFIG.3. The transparent electrode59is commonly electrically connected to second conductivity type semiconductor layers27and37, and thus, the second conductive type semiconductor layer27of the first LED stack20and the second conductive type semiconductor layer37of the second LED stack30are electrically connected to each other. Meanwhile, in the illustrated exemplary embodiment, a first substrate21may be disposed on a side of a first conductivity type semiconductor layer23, and a second substrate31may be disposed on a side of a first conductivity type semiconductor layer33. In the above, a stacked structure of various light emitting devices in which the short wavelength light emitting portion BL and the long wavelength light emitting portion YL are combined by the insulation layer50or the transparent electrode layer59has been described. However, the inventive concepts are not limited to these light emitting devices, and various other light emitting devices may also be possible. Meanwhile, at least two electrodes may be disposed to supply external power to the short wavelength light emitting portion BL and the long wavelength light emitting portion YL. Hereinafter, light emitting devices having various structures in which three or four electrodes are formed will be described in detail. FIG.8is a schematic plan view illustrating a light emitting device100according to one or more embodiments,FIG.9Ais a schematic cross-sectional view taken along line A-A′ ofFIG.8, andFIG.9Bis a schematic cross-sectional view taken along line B-B′ ofFIG.8. For convenience of description, bonding pads67a,67b, and67care illustrated and described as being disposed at an upper side, but the inventive concepts are not limited thereto. For example, in some exemplary embodiments, the light emitting device may be flip-bonded on a circuit board, and in this case, the bonding pads67a,67b, and67cmay be disposed at a lower side. Referring toFIGS.8,9A, and9B, the light emitting device100includes a first LED stack20, a second LED stack30, a first transparent electrode29, and a second transparent electrode39, a lower p-electrode pad47, an upper p-electrode pad57, an insulation layer50, a planarization layer61, a sidewall insulation layer63, buried vias65a,65b,65c, and65d, and first, second, and third bonding pads67a,67b, and67c. Further, the light emitting device100may include through holes H1(FIG.9A) and H2(FIG.9B) passing through the second LED stack30, a through hole H3(FIG.9B) partially passing through the second LED stack30, and a through hole H4(FIG.9A) located on the LED stack30. The light emitting device100has a basic layer structure of a short wavelength light emitting portion BL and a long wavelength light emitting portion YL is similar to that described with reference toFIG.5, but the lower p-electrode pad47and the upper p-electrode pad57may be added on a first transparent electrode29and a second transparent electrode39, respectively. As illustrated inFIGS.9A and9B, in the exemplary embodiments, the first and second LED stacks20and30are stacked in the vertical direction. The first LED stack20is disposed on a substrate21, and the second LED stack30is combined to the first LED stack20. Before the second LED stack30is combined to the first LED stack20, the lower p-electrode pad47may be formed on the first transparent electrode29. The lower p-electrode pad47may be formed using, for example, a lift-off technique. The lower p-electrode pad47may be formed of a metal layer. The lower p-electrode pad47may be formed of, for example, Cr/Au/Ti, but the inventive concepts are not particularly limited thereto. The lower p-electrode pad47may be omitted. Meanwhile, the second LED stack30is grown on a second substrate, and thereafter, may be bonded to the first LED stack20using the insulation layer50using a TBDB (temporary bonding debonding) technology. The second transparent electrode39may be formed before bonding, or may be formed after bonding. The upper p-electrode pad57may be partially formed on the second transparent electrode39. The upper p-electrode pad57may be formed of a metal layer, and a material thereof is not particularly limited. The upper p-electrode pad57may be formed of an identical material as that of the lower p-electrode pad47. The upper p-electrode pad57may be disposed not to be overlapped with the lower p-electrode pad47. The planarization layer61may cover the second transparent electrode39and the upper p-electrode pad57. The planarization layer61may have a flat upper surface. The planarization layer61is disposed over a second conductivity type semiconductor layer37. A side surface of the planarization layer61may be flush with the second conductivity type semiconductor layer37, but the inventive concepts are not limited thereto, and as illustrated inFIGS.9A and9B, may be recessed inwardly from an edge of the second LED stack30. Further, the side surface of the planarization layer61may be flush with a side surface of the second transparent electrode39. The planarization layer61may be patterned by photolithography and etching processes, and in this case, the second transparent electrode39may be patterned together. As such, the second conductivity type semiconductor layer37may be exposed around the planarization layer61. The planarization layer61may be formed of an aluminum oxide film, a silicon oxide film, or a silicon nitride film. Through holes H1, H2, H3, and H4may be formed to provide an electrical path to the short wavelength light emitting portion BL and the long wavelength light emitting portion YL. The through holes H1, H2, H3, and H4are spaced apart from one another. Since the through holes H1, H2, H3, and H4have different depths from one another, they may be formed using different processes from one another. The through hole H1may pass through the planarization layer61, the second transparent electrode39, the second LED stack30, the insulation layer50, a first transparent electrode29, a second conductivity type semiconductor layer27, and an active layer25, and may expose a first conductivity type semiconductor layer23. The through hole H2may pass through the planarization layer61, the second transparent electrode39, the second LED stack30, and the insulation layer50to expose the lower p-electrode pad47. The through hole H3may pass through the planarization layer61, the second transparent electrode39, the second conductivity type semiconductor layer37, and the active layer35to expose the first conductivity type semiconductor layer23. The through hole H4may pass through the planarization layer61to expose the upper p-electrode pad57. The sidewall insulation layer63covers sidewalls of the through holes H1, H2, H3, and H4, and has openings exposing bottoms of the through holes H1, H2, H3, and H4. The sidewall insulation layer63may be formed using, for example, a chemical vapor deposition technique or an atomic layer deposition technique, and may be formed of, for example, aluminum oxide, silicon oxide, or silicon nitride. After the through holes H1, H2, H3, and H4are formed, the sidewall insulation layer63may be formed to cover the planarization layer61and the inside of the through holes H1, H2, H3, and H4, and thereafter, openings exposing bottom surfaces may be formed by removing the sidewall insulation layer formed at the bottoms of the through holes H1, H2, H3, and H4through blanket etching. Buried vias65a,65b,65c, and65dmay fill the through holes H1, H2, H3, and H4, respectively. The buried vias65a,65b, and65care insulated from inner walls of the through holes H1, H2, and H3by the sidewall insulation layer63to prevent an electrical short. The buried via65ais electrically connected to the first conductivity type semiconductor layer23of the first LED stack20. The buried via65bmay be electrically connected to the lower p-electrode pad47, and may be electrically connected to the second conductivity type semiconductor layer27through the lower p-electrode pad47and the first transparent electrode29, as shown inFIG.9B. The buried via65cmay be electrically connected to a first conductivity type semiconductor layer33of the second LED stack30, and the buried via65dmay be electrically connected to the upper p-electrode pad57. The buried vias65a,65b,65c, and65dmay be formed using a chemical mechanical polishing technique. For example, after forming a seed layer and filling the through holes H1, H2, H3, and H4with a conductive material such as Cu using a plating technique, the buried vias65a,65b,65c, and65dmay be formed by removing metal layers on the planarization layer61using the chemical mechanical polishing technique. As illustrated inFIGS.9A and9B, the buried vias65a,65b, and65cmay have a relatively wider width at inlets of the through holes H1, H2, and H3than the bottom surfaces thereof, and thus, electrical connections may be strengthened. Meanwhile, the buried via65dmay have a column shape in which upper and bottom surfaces thereof have substantially the same size. The buried vias65a,65b,65c, and65dmay be formed together through an identical process. As such, the upper surfaces of the buried vias65a,65b,65c, and65dmay be substantially flush with the planarization layer61. The bonding pads67a,67b, and67cmay be disposed on respective regions of the planarization layer61. The first bonding pad67amay be electrically connected to the buried via65a, and may also extend in the lateral direction to be electrically connected to the buried via65c. As such, the first conductivity type semiconductor layer23of the first LED stack20and the first conductivity type semiconductor layer33of the second LED stack30may be commonly electrically connected. The first bonding pad67amay cover the buried vias65aand65c(seeFIG.8). The second bonding pad67bis electrically connected to the buried via65b. The second bonding pad67bmay cover the buried via65b. The third bonding pad67cis electrically connected to the buried via65d. The third bonding pad67cmay cover the buried via65d. In the illustrated exemplary embodiment, all of the first, second, and third bonding pads67a,67b, and67care disposed on the planarization layer61. The first, second, and third bonding pads67a,67b, and67cmay be formed together through an identical process, and thus, elevations of upper surfaces thereof may be identical. In the illustrated exemplary embodiment, when the light emitting device100is bonded to a circuit board, the first, second, and third bonding pads67a,67b, and67cmay be bonded to pads on the circuit board by a bonding material such as solder paste. Alternatively, bumps may be additionally formed on the first, second, and third bonding pads67a,67b, and67c, and the light emitting device100may be bonded to the circuit board using the bumps. The light emitting device100according to the exemplary embodiment may emit light of a short wavelength of ultraviolet or blue light using the first LED stack20, and may emit light of a long wavelength of green light or yellow light using the second LED stack30. The light emitting device100may implement mixed color light by a combination of long wavelength light and short wavelength light, and may implement white light, for example, by a combination of blue light and yellow light. Further, since the first conductivity type semiconductor layer23of the first LED stack20and the first conductivity type semiconductor layer33of the second LED stack30are commonly electrically connected, the first conductivity type semiconductor layers23and33may be electrically connected to a single boding pad67a. As such, the first LED stack20and the second LED stack30may be independently driven using three bonding pads. Moreover, the buried vias65aand65belectrically connected to the first conductivity type semiconductor layer23and the second conductivity type semiconductor layer27of the first LED stack20are disposed in the diagonal direction in the light emitting device100. In addition, the buried vias65cand65delectrically connected to the first conductivity type semiconductor layer33and the second conductivity type semiconductor layer37of the second LED stack30are disposed in the diagonal direction in the light emitting device100. Since the buried vias65aand65bconnected to the first LED stack20and the buried vias65cand65delectrically connected to the second LED stack30are disposed in the diagonal direction, current spread in the first LED stack20and the second LED stack30may be assisted, and thus, luminous efficiency of the light emitting device100may be increased. In the illustrated exemplary embodiment, although the first conductivity type semiconductor layer23of the first LED stack20and the first conductivity type semiconductor layer33of the second LED stack30are commonly electrically connected, the inventive concepts are not limited thereto. For example, the second conductivity type semiconductor layer27of the first LED stack20and the second conductivity type semiconductor layer37of the second LED stack30may be commonly electrically connected. For example, the first bonding pad67ais divided and disposed on the buried vias65aand65c, respectively, and the second bonding pad67band the third bonding pad67care connected to each other, and thus, the second conductivity type semiconductor layer27of the stack20and the second conductivity type semiconductor layer37of the second LED stack30may be commonly electrically connected. In another exemplary embodiment, the second conductivity type semiconductor layer27of the first LED stack20and the second conductivity type semiconductor layer37of the second LED stack30may also be electrically connected to a single bonding pad. In this case, the first LED stack20and the second LED stack30may be simultaneously driven using two bonding pads. FIG.10is a schematic plan view illustrating a light emitting device200according to another exemplary embodiment,FIG.11Ais a schematic cross-sectional view taken along line C-C′ ofFIG.10, andFIG.11Bis a schematic cross-sectional view taken along line D-D′ ofFIG.10. Referring toFIGS.10,11A, and11B, the light emitting device200according to the exemplary embodiment is substantially similar to the light emitting device100described with reference toFIGS.8,9A, and9B, but a first LED stack20is patterned and the light emitting device200further includes a lower n-electrode pad47aas shown inFIG.10. More particularly, a first transparent electrode29, a second conductivity type semiconductor layer27, and an active layer25shown inFIGS.11A and11Bare patterned to expose a first conductivity type semiconductor layer23. The lower n-electrode pad47amay be formed on the exposed first conductivity type semiconductor layer23. The lower n-electrode pad47amay be formed of a material layer in ohmic contact with the first conductivity type semiconductor layer23, such as Cr/Au/Ti. Meanwhile, a lower p-electrode pad47bmay be disposed on the first transparent electrode29. An elevation of an upper surface of the lower p-electrode pad47bmay be substantially similar to that of an upper surface of the lower n-electrode pad47a. A through hole H1may expose the lower n-electrode pad47ainstead of exposing the first conductivity type semiconductor layer23. Since the elevation of the upper surface of the lower n-electrode pad47ais substantially similar to that of the upper surface of the lower p-electrode pad47b, through holes H1and H2may be formed together through an identical process. In the illustrated exemplary embodiment, the patterning of the first LED stack20may be performed before the first LED stack20and the second LED stack30are bonded using an insulation layer50. Therefore, the insulation layer50may cover the exposed first conductivity type semiconductor layer20, and may cover side surfaces of the first transparent electrode29, the second conductivity type semiconductor layer27, and the active layer25along with an upper surface of the first transparent electrode29. In the illustrated exemplary embodiment, although the first LED stack20is exemplarily described as being patterned, the second LED stack30may also be patterned to expose a first conductivity type semiconductor layer33, and an upper n-electrode pad may be formed on the exposed first conductivity type semiconductor layer33. In addition, an upper p-electrode pad57bis disposed on a second transparent electrode39. An elevation of an upper surface of the upper p-electrode pad57band that of an upper surface of the upper n-electrode pad formed on the first conductivity type semiconductor layer33may be substantially similar, and thus, through holes H3and H4may also be formed together through an identical process. FIGS.12A and12Bare schematic cross-sectional views illustrating a light emitting device300according to another exemplary embodiment. Referring toFIGS.12A and12B, the light emitting device300according to the exemplary embodiment is substantially similar to the light emitting device100described with reference toFIGS.8,9A, and9B, but a second transparent electrode39is disposed on a side of an insulation layer50, and a first conductivity type semiconductor layer33is disposed far from the insulation layer50in the light emitting device300. More particularly, a stack sequence of a first LED stack20, a second LED stack30, a first transparent electrode29, and the second transparent electrode39disposed on a first substrate21is similar to that of those in the light emitting device described with reference toFIG.3, and detailed descriptions thereof will be omitted. A planarization layer161covers the first conductivity type semiconductor layer33. The planarization layer161may be formed of an aluminum oxide layer, a silicon oxide layer, or a silicon nitride layer. As described with reference toFIGS.8,9A, and9B, the planarization layer161may be recessed to expose an edge of the first conductivity type semiconductor layer33. In the illustrated exemplary embodiment, a through hole H1(FIG.12A) may expose a first conductivity type semiconductor layer23. In another exemplary embodiment, as described with reference toFIG.10, the first LED stack20may be patterned and formed on the first conductivity type semiconductor layer23to which a lower n-electrode pad is exposed, and the through hole H1may expose the lower n-electrode pad. A through hole H2(FIG.12B) may expose the first transparent electrode29. In another exemplary embodiment, as described with reference toFIG.8or10, a lower p-electrode pad may be disposed on the first transparent electrode29, and the through hole H2may expose the lower p-electrode pad. A through hole H3may expose the first conductivity type semiconductor layer33. An upper n-electrode pad may be added on the first conductivity type semiconductor layer33, and the through hole H3may expose the upper n-electrode pad. A through hole H4may pass through the planarization layer161and the second LED stack30, and expose the second transparent electrode39. A sidewall insulation layer63may cover inner walls of the through holes H1, H2, H3, and H4, and expose bottom surfaces thereof. In addition, as described above, buried vias65a,65b,65c, and65dmay be formed in the through holes H1, H2, H3, and H4, respectively, and bonding pads67a,67b, and67cmay be disposed on the planarization layer161to cover the buried vias65a,65b,65c, and65d. According to the illustrated exemplary embodiment, the first bonding pad67aelectrically connects the buried vias65aand65c, and thus, the first conductivity type semiconductor layers23and33of the first LED stack20and the second LED stack30are commonly electrically connected. Meanwhile, the second bonding pad67bmay be electrically connected to a second conductivity type semiconductor layer27through the buried via65band the first transparent electrode29, and the third bonding pad67cmay be electrically connected to a second conductivity type semiconductor layer37through the buried via65dand the second transparent electrode39. In another exemplary embodiment, the second conductivity type semiconductor layers27and37of the first LED stack20and the second LED stack30may be commonly electrically connected, and the first conductivity type semiconductor layers23and33may be electrically spaced apart. In another exemplary embodiment, the first conductivity type semiconductor layers23and33of the first LED stack20and the second LED stack30are commonly electrically connected, and the second conductivity type semiconductor layers27and37are also commonly electrically connected. FIGS.13A and13Bare schematic cross-sectional views illustrating a light emitting device400according to another exemplary embodiment. Referring toFIGS.13A and13B, the light emitting device400according to the exemplary embodiment includes a transparent electrode59that combines a first LED stack20and a second LED stack30to each other. More particularly, the first LED stack20and the second LED stack30are bonded by the transparent electrode59. The transparent electrode59is commonly electrically connected to a second conductivity type semiconductor layer27of the first LED stack20and a second conductivity type semiconductor layer37of the second LED stack30. A through hole H1exposes the transparent electrode59, a through hole H2exposes a first conductivity type semiconductor layer23, and a through hole H3exposes a first conductivity type semiconductor layer33. In the illustrated exemplary embodiment, the light emitting device400may have three through holes H1, H2, and H3, and a fourth through hole H4may be omitted. As described above, a sidewall insulation layer63is formed, buried vias165a,165b, and165cmay be formed in the through holes H1, H2, and H3, and bonding pads167a,167b, and167cmay be formed on a planarization layer161. In the illustrated exemplary embodiment, the first bonding pad167amay be commonly electrically connected to the second conductivity type semiconductor layers27and37through the transparent electrode59, and the second and third bonding pads167band167cmay be electrically connected to the first conductivity type semiconductor layer23and the first conductivity type semiconductor layer33, respectively. FIG.14is a schematic plan view illustrating a light emitting device500according to another exemplary embodiment,FIG.15Ais a schematic cross-sectional view taken along line E-E′ ofFIG.14,FIG.15Bis a schematic cross-sectional view taken along line F-F′ ofFIG.14, andFIG.16is a schematic circuit diagram of the light emitting device500ofFIG.14. Referring toFIGS.14,15A, and15B, the light emitting device500according to the exemplary embodiment is substantially similar to the light emitting device100described with reference toFIGS.8,9A, and9B, but the light emitting device500includes a plurality of light emitting cells C1and C2. Since a layer structure of each of the light emitting cells C1and C2is substantially similar to that of the light emitting device100, detailed descriptions thereof will be omitted. The light emitting cells C1and C2are spaced apart from one another on a substrate21. After a first LED stack20and a second LED stack30are bonded using an insulation layer50, the light emitting cells C1and C2spaced apart from one another may be formed by sequentially etching a second transparent electrode39, the second LED stack30, and the insulation layer50. As shown inFIG.15A, a planarization layer261may cover the substrate21in an isolation region between the light emitting cells C1and C2together with the light emitting cells C1and C2. An upper surface of the planarization layer261may be flat. Through holes H1, H2, H3, and H4and sidewall insulation layers63are formed in each of the light emitting cells C1and C2as described with reference toFIGS.8,9A, and9B, and buried vias265a,265b,265c, and265dare formed in the through holes H1, H2, H3, and H4. In addition, as described with reference toFIGS.8,9A, and9B, the buried vias265aand265belectrically connected to a first conductivity type semiconductor layer23and a second conductivity type semiconductor layer27of the first LED stack20are disposed in the diagonal direction in each of the light emitting cells C1and C2. In addition, the buried vias265cand265delectrically connected to a first conductivity type semiconductor layer33and a second conductivity type semiconductor layer37of the second LED stack30are disposed in the diagonal direction in each of the light emitting cells C1and C2. Since the buried vias265aand265bconnected to the first LED stack20and the buried vias265cand265delectrically connected to the second LED stack30are disposed in the diagonal direction, current spread in the first LED stack20and the second LED stack30may be assisted, and thus, luminous efficiency may be increased. Subsequently, connectors267eand267fmay be formed together with bonding pads267a,267b, and267c. The bonding pads267amay be disposed on the second light emitting cell C2, and may be electrically connected to the first conductivity type semiconductor layers23and33through the buried vias265aand265cin the second light emitting cell C2. The bonding pad267band the bonding pad267cmay be disposed on the first light emitting cell C1, and may be electrically connected to the buried vias265band265d, respectively. Meanwhile, the connectors267eand267felectrically connect the first light emitting cell C1and the second light emitting cell C2. Specifically, the connector267eelectrically connects the buried vias265aand265cof the first light emitting cell C1and the buried via265dof the second light emitting cell C2to one another, and the connector267felectrically connects the buried vias265aand265cand the buried via265cof the second light emitting cell C2to one another. As such, as illustrated inFIG.16, the light emitting device500in which a short wavelength light emitting portion BL1and a long wavelength light emitting portion YL1of the first light emitting cell C1, and a short wavelength light emitting portion BL2and a long wavelength light emitting portion YL2of the second light emitting cell C2are connected in series-parallel. In particular, the short wavelength light emitting portion BL1of the first light emitting cell C1and the first conductivity type semiconductor layers23and33of the long wavelength light emitting portion YL1are electrically connected to one another, and further, the short wavelength light emitting portion BL2of the second light emitting cell C2and the second conductivity type semiconductor layers27and37of the long wavelength light emitting portion YL2are also electrically connected. In the illustrated exemplary embodiment, although the through holes H1, H2, H3, and H4are exemplarily illustrated and described as being formed in each of the light emitting cells C1and C2, the inventive concepts are not limited thereto. Instead of forming the through holes, the first and second conductivity type semiconductor layers23,33,27, and37or the first and second transparent electrodes29and39may be exposed using various techniques such as mesa etching, and an electrical connection may be formed thereto. A method of connecting the plurality of light emitting cells C1and C2may be various. Hereinafter, light emitting devices connecting the light emitting cells C1and C2will be described using a circuit diagram. FIGS.17through19are schematic circuit diagrams illustrating light emitting devices600,700, and800according to some exemplary embodiments. First, referring toFIG.17, the light emitting device600according to the exemplary embodiment is substantially similar to the light emitting device500described with reference toFIG.16, but a short wavelength light emitting portion BL1of a first light emitting cell C1and first conductivity type semiconductor layers23and33of a long wavelength light emitting portion YL1are electrically separated from one another. Further, a short wavelength light emitting portion BL2of a second light emitting cell C2and second conductivity type semiconductor layers27and37of the long wavelength light emitting portion YL2are also electrically spaced apart. For example, the connectors267eand267fin the exemplary embodiment ofFIG.14may be separated from each other to provide the light emitting device600of the circuit diagram ofFIG.17. Referring toFIG.18, the light emitting device700according to the exemplary embodiment is substantially similar to the light emitting device500described with reference toFIG.16, but in the light emitting device700, a short wavelength light emitting portion BL1of a first light emitting cell C1and second conductivity type semiconductor layers27and37of a long wavelength light emitting portion YL1are commonly electrically connected, and a short wavelength light emitting portion BL2of a second light emitting cell C2and second conductivity type semiconductor layers27and37of a long wavelength light emitting portion YL2are electrically spaced apart from one another. The short wavelength light emitting portion BL1of the first light emitting cell C1and first conductivity type semiconductor layers23and33of the long wavelength light emitting portion YL1are commonly electrically connected, and the short wavelength light emitting portion BL2of the second light emitting cell C2and the first conductivity type semiconductor layers23and33of the long wavelength light emitting portion YL2are electrically connected to one another. Referring toFIG.19, in the light emitting device800according to the illustrated exemplary embodiment, a short wavelength light emitting portion BL1of a first light emitting cell C1is connected in series with a short wavelength light emitting portion BL2of a second light emitting cell C2, and a long wavelength light emitting portion YL1of a first light emitting cell C1is connected in series with a long wavelength light emitting portion YL2of the second light emitting cell C2. Meanwhile, the short wavelength light emitting portions BL1and BL2and the long wavelength light emitting portions YL1and YL2are electrically spaced apart from one another. From above, although it has been described in some exemplary embodiments that the short wavelength light emitting portion BL1and the long wavelength light emitting portion YL1of the first light emitting cell C1, and the short wavelength light emitting portion BL2and the long wavelength light emitting portion YL2of the second light emitting cell C2are connected, the inventive concepts are not limited to the specific exemplary embodiments described above. Although some embodiments have been described herein, it should be understood that these embodiments are provided for illustration only and are not to be construed in any way as limiting the present disclosure. It should be understood that features or components of one or more embodiments can also be applied to other embodiments without departing from the spirit and scope of the present disclosure. | 48,965 |
11862617 | DETAILED DESCRIPTION To make the objects, technical solutions and advantages of the present disclosure more clear, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Those skilled in the art should understand that embodiments in the present disclosure and features in the embodiments may be combined with each other arbitrarily if there is no conflict. FIG.1is a schematic structural diagram of a display panel. As shown inFIG.1, the display panel includes a plurality of sub-panels10tiled in sequence along a first direction X (inFIG.1, the first direction is from right to left). For convenience of illustration and description, only one row of pixels is shown inFIG.1. Due to the existence of assembly accuracy, there is a seam50between two adjacent sub-panels10. The width of the seam50is w1. The sub-panel10includes a plurality of columns of third pixels13along the first direction X. The width of a third pixel13in the first direction X is a third width p. An effective display body135is provided in the third pixel13. The width of the effective display body135in the first direction X is p5. At a position other than the seam50, the spacing d0 between two adjacent columns of effective display bodies135is equal to p1+p4. However, at the seam50, the spacing d1 between the effective display bodies135on both sides of the seam50is equal to p1+p4+w1. As shown inFIG.1, due to the existence of the seam50, the spacing between the effective display bodies135on both sides of the seam50increases to d1. The width w1 of the seam50is larger due to the assembly tolerance and the dimensional tolerance of the display panel. In this way, the spacing d1 between the effective display bodies135on both sides of the seam50is much larger than the spacing d0 between the effective display bodies135at the position other than the seam. As a result, when the display panel displays, the seam50is visualized as a very wide black strip, as shown inFIG.1, which affects the display effect of the display panel and reduces the uniformity of the display effect. FIG.2is a schematic structural diagram of the sub-panels inFIG.1.FIG.3is a schematic structural diagram of a third pixel inFIG.2. As shown inFIG.2, the sub-panels include a plurality of third pixels13. The plurality of third pixels13are arranged in an array of m rows and n columns. As shown inFIG.3, a third pixel13includes a first boundary131, a third boundary133, a second boundary132, and a fourth boundary134connected in sequence. The third pixel13also includes an effective display body135within the boundaries. The effective display body135may include a plurality of LED chips, such as mini LEDs or micro LEDs. In an exemplary embodiment, the effective display body135may include three LED chips, such as a R, a G and a B. In an exemplary embodiment, the effective display body135may include six LED chips, such as two R, two G and two B, as shown inFIG.3, in which three LEDs are redundant. In an exemplary embodiment, the effective display body135may include four LED chips, such as one R, one G and one B, and one R or G or B, in which one LED is redundant. The effective display body135may further include a bank structure1351. The bank structure1351is arranged around each LED. The material of the bank structure1351may be a white material with high reflectivity, such as white glue or epoxy resin and the like. As a result, the bank structure1351may make the light emitted from each LED converge toward its center, avoid LED light from scattering into the ambiance, and improve light-emitting efficiency and uniformity of display. As shown inFIG.3, in the third pixel13, the width of the effective display body135in the first direction is p5. The distance between the effective display body135and the first boundary131is p1. The distance between the effective display body135and the second boundary132is p4. The distance between the effective display body135and the third boundary133is p2. The distance between the effective display body and the fourth boundary134is p3. The values of p1, p4, p2 and p3 may be determined as required. In an exemplary embodiment, p1=p4, and p2=p3. A black light-shielding material130is provided between the effective display body135and the boundaries of the third pixel13. InFIG.3, in order to clearly illustrate the distance between the effective display body and the boundaries of the pixel, the black light-shielding material130is illustrated as white. Those skilled in the art may understand that when the black light-shielding material130is provided between the effective display body and the boundaries of the pixel, the area between the effective display body and the boundaries of the pixel is actually black. The width of the third pixel13in the first direction is the third width p. InFIG.3, the third width p is equal to p1+p4+p5. As shown inFIG.2, a channel region60is arranged on the upper side of the sub-panels. A MUX region70is arranged in the right side of the sub-panels. The width of the channel region60may be wc. The width of the MUX region70may be wm. The wm may be equal to p1. InFIG.2, in the first direction X, the pitch between two adjacent third pixels13is p. That is, the third pixels13have an arrangement period of p in the first direction X. As shown inFIG.2, in the sub-panel10, the spacing d0 between two adjacent columns of effective display bodies135is equal to p1+p4. FIG.4is a schematic structural diagram of a display panel according to an exemplary embodiment. For convenience of description, only one row of pixels is shown inFIG.4. As shown inFIG.4, in an exemplary embodiment, the display panel includes a plurality of sub-panels20tiled in sequence along a first direction X. A sub-panel20has a first edge201and a second edge202in the first direction X. In the first direction X, the sub-panel20includes a plurality of columns of pixels. The plurality of columns of pixels include a column of first pixels21closest to the first edge201, a column of second pixels22closest to the second edge202, and a plurality of columns of third pixels13between the column of first pixels21and the column of second pixels22. An effective display body135is provided in each of the first pixels21, the second pixels22and the third pixels13. A sum of the distance between an effective display body in the first pixel and the first edge and the distance between an effective display body in the second pixel and the second edge is smaller than the spacing between effective display bodies in two adjacent columns of third pixels. In the display panel according to an embodiment of the present disclosure, as shown inFIG.4, the distance between an effective display body in the first pixel21and the first edge201is p8. The distance between an effective display body in the second pixel22and the second edge202is p9. As shown inFIG.3, the third pixel13has a first boundary131towards the first edge201and a second boundary132towards the second edge202. The distance between an effective display body in the third pixel13and the first boundary131is p1. The distance between the effective display body in the third pixel13and the second boundary132is p4. The sum of the distance between an effective display body in the first pixel and the first edge and the distance between an effective display body in the second pixel and the second edge is smaller than the spacing between effective display bodies in two adjacent columns of third pixels. That is, the sum of p8 and p9 is smaller than the sum of p1 and p4. Therefore, in the display panel according to an embodiment of the present disclosure, at the seam50between the two sub-panels20, the spacing d2 between the effective display bodies on both sides of the seam50is equal to p8+p9+w1. Compared with d1 in the display panel ofFIG.1, which is equal to p1+p4+w1, the sum of p8 and p9 is smaller than the sum of p1 and p4, so that d2 is less than d1. That is, in an embodiment of the present disclosure, the spacing between the effective display bodies on both sides of the seam50is smaller than the spacing between the effective display bodies on both sides of the seam50inFIG.1, thus reducing the spacing between the effective display bodies at the seam. As a result, the spacing between the effective display bodies at the seam is closer to the spacing between the effective display bodies at the position other than the seam, thereby reducing or even eliminating the black strip effect at the seam, improving the display effect of the display panel at the seam, and improving the uniformity of the display effect of the display panel. In an exemplary embodiment, in the first direction, the width of the seam between two adjacent sub-panels is w1. The difference between the sum of p1 and p4 and the sum of p8 and p9 is substantially equal to w1. That is, the value of (p1+p4)−(p8+p9) is substantially equal to that of w1. Those skilled in the art may understand that there are process errors when tiling two sub-panels, so the value of (p1+p4)−(p8+p9) is substantially equal to that of w1. That is, the values of (p1+p4)−(p8+p9) and w1 are within the allowable range of process errors, the value of (p1+p4)−(p8+p9) may be deemed to be equal to that of w1. In an exemplary embodiment, [(p1+p4)−(p8+p9)]/w1 is 95% to 105%, or w1/[(p1+p4)−(p8+p9)] is 95% to 105%. In this way, the spacing between the effective display bodies on both sides of the seam50is substantially equal to the spacing between the effective display bodies at the position other than the seam50, thereby improving uniformity of the display effect of the display panel. As shown inFIG.4, the distance between an effective display body in the first pixel21and the first edge201is p8. The distance between an effective display body in the second pixel22and the second edge202is p9. The third pixel13has a first boundary131towards the first edge201and a second boundary132towards the second edge202. The distance between an effective display body in the third pixel13and the first boundary131is p1. The distance between an effective display body in the third pixel13and the second boundary132is p4. The distance between an effective display body in the first pixel21and a boundary of the first pixel21towards the second edge202is p24. The distance between an effective display body in the second pixel22and a boundary of the second pixel22towards the first edge201is p21. In an exemplary embodiment, p9<p4, p8=p1, p24=p4, and p21=p1. In such a display panel, the spacings between adjacent effective display bodies at the positions not close to the seam50are equal, which further improves uniformity of the display effect of the display panel. In an exemplary embodiment, as shown inFIG.4, the difference between p4 and p9 (i.e., pc1) may be equal to the width of the seam50between adjacent sub-panels. In this way, the spacing between the effective display bodies on both sides of the seam50is equal to the spacing between the effective display bodies at the position other than the seam50, thereby improving uniformity of the display effect of the display panel. In an exemplary embodiment, p9<p4, p8=p1, p21=p1, and p24=p4. The sub-panel10may be further processed to obtain the sub-panel20. As shown inFIG.3, in an exemplary embodiment, the sub-panel10shown inFIG.2may be processed by a grinding or cutting process to obtain a sub-panel20. For example, the left edge of the sub-panel10shown inFIG.2is ground or cut by a grinding or cutting process. To prevent the cutting from affecting the effective display body, the cutting distance pc1 is required to be smaller than p4, i.e., pc1<p4. The grinding or cutting accuracy is pt, where pt<p4−pc1, i.e., pt<p9. As a result, the sub-panel20is obtained, in which the width p7 of the second pixel22in the first direction X is smaller than the width p of the third pixel13in the first direction X. That is, p7<p, and p7=p−pc1. In an exemplary embodiment, when the two sub-panels20are tiled along the first direction X, the assembly accuracy is pa, and thus, for cutting on one side, the width w1 of the seam is equal to pt+pa. In an exemplary embodiment, pa is about 0.02 mm, and pt is about 0.02 mm. Those skilled in the art may understand that the value of pa is determined according to different assembly conditions. For example, 0.005≤pa≤0.05. For example, inFIG.2, p=1 mm, p5=0.8 mm and p4=0.1 mm, then the cutting distance pc1=w1=0.04 mm. The left edge of the display panel inFIG.2is cut by 0.04 mm, and thus the sub-panel20inFIG.4may be obtained, with p9 of the sub-panel20being equal to 0.06 mm. In an exemplary embodiment, as shown inFIG.4, p9<p4, p21<p1, p8=p1, and p24=p4. In such a display panel, the value of p21 is reduced, so that the spacing between the effective display body in the second pixel22and the effective display body in the third pixel13is reduced, but p9>0 is ensured. In this way, when the second pixel22is formed by a cutting or grinding process, the left edge of the second pixel22may not affect the effective display body in the second pixel22, and may not affect the display effect of the display panel. In an exemplary embodiment, for example, the sub-panel10may be further modified to obtain the sub-panel20. In an exemplary embodiment, a sub-panel shown inFIG.2may be modified to obtain the sub-panel20. For example, the distance between a leftmost effective display body inFIG.2and the first boundary may be reduced from p1 to p21, and then the left edge of the sub-panel may be ground or cut by a grinding and cutting process. For example, inFIG.2, p=0.6 mm, p5=0.5 mm, P4=0.05 mm, pa is about 0.02 mm, and pt is about 0.02 mm, and thus the cutting distance pc1 is equal to 0.04 mm. If p21=p1, then p9=0.05-0.04=0.01 mm, which may not meet pt<p9. Therefore, p21 should be adjusted so that p21<p1. In an exemplary embodiment, p1−p21≤p*δ, and 3%≤δ≤5%. For example, δ is equal to 5% or 3%. In an exemplary embodiment, δ=3%, (p1−p21)/p=δ, then p9=0.01+0.018=0.028 mm, which meets pt<p9. Therefore, p1 of the leftmost pixel of the sub-panel inFIG.2may be adjusted to p21 (that is, p1 is reduced by 0.018), and the left edge of the sub-panel is cut by 0.04 mm. As a result, as shown inFIG.4, the spacing between an effective display body in the second pixel22and an effective display body in the adjacent third pixel13is p21+p4. If p1−p21=L (L≤p*δ), the spacing between the effective display body in the second pixel22and the effective display body in the adjacent third pixel13is d3, and d3 is equal to p1+p4−L, thus ensuring p9>pt. In this way, when the second pixel22is formed by a cutting or grinding process, the left edge of the second pixel22may not affect the effective display body in the second pixel22, and may not affect the display effect of the display panel. FIG.5is a schematic structural diagram of a display panel according to an exemplary embodiment. In an exemplary embodiment, as shown inFIG.5, the sub-panel may further include k columns of fourth pixels24between the second pixels22and the third pixels13. The k is a natural number greater than or equal to 1. An effective display body is provided in a fourth pixel24. A fourth pixel24has a first boundary241towards the first edge201and a second boundary242towards the second edge202. The distance between an effective display body in the fourth pixel24and the first boundary241of the fourth pixel24is p22. The distance between an effective display body in the fourth pixel24and the second boundary242of the fourth pixel24is p23. In an exemplary embodiment, p21<p22, and p22<p1. The width of the fourth pixel24in the first direction X is p (i.e., p is equal to the width of the third pixel13in the first direction X). p1−p22≤p*δ, (p1+p4)−(p21+p23)≤p*δ, and 3%≤δ≤5%. In an exemplary embodiment, a sub-panel shown inFIG.2may be modified to obtain the sub-panel20shown inFIG.5. For example, p=0.5 mm, p5=0.40 mm, and p1=p4=0.05 mm. The pa is about 0.02 mm and pt is about 0.02 mm, and thus the cutting distance pc1 is equal to pa+pt, where pa+pt=0.04 mm. If p21=p22=p1, then p9=0.01, which may not meet pt<p9. Therefore, if p21 may be adjusted and decreased by 0.02, that is, p21=0.03 mm, then p9=0.03 satisfies pt<p9. If p22=p1, then (p1+p4)−(p21+p23)=0.02, which may not meet (p1+p4)−(p21+p23)≤p*δ, and 3%≤δ≤5%, so p22 needs to be reduced. The p22 may be reduced by 0.01, so that p23=0.06 mm, (p1+p4)−(p21+p23)=0.01, which may meet (p1+p4)−(p21+p23)≤p*δ, and 3%≤δ≤5%. Therefore, p=0.5 mm, p5=0.40 mm, p1=p4=0.05 mm, p21=0.03 mm, p9=0.03 mm, p22=0.04 mm and p23=0.06 mm. The number of columns of the fourth pixels24is one, i.e., k=1. FIG.6is a schematic structural diagram of a display panel according to an exemplary embodiment. As shown inFIG.6, the distance between an effective display body in the first pixel21and the first edge201is p8. The distance between an effective display body in the second pixel22and the second edge202is p9. In an exemplary embodiment, as shown inFIG.6, p8<p1, p9=p4, p24=p4, and p21=p1. The width p7 of the second pixel22in the first direction X is equal to p. The width p6 of the first pixel21in the first direction X is less than p. In an exemplary embodiment, as shown inFIG.6, the difference between p1 and p8 may be equal to the width of the seam50between adjacent sub-panels. In this way, the spacing between the effective display bodies on both sides of the seam50is equal to the spacing between the effective display bodies at the position other than the seam50, thereby improving uniformity of the display effect of the display panel. In an exemplary embodiment, p9=p4, p8<p1, p21=p1, and p24=p4. The sub-panel10may be further processed to obtain a sub-panel20. As shown inFIG.3, in an exemplary embodiment, the sub-panel10shown inFIG.2may be processed by a grinding or cutting process to obtain the sub-panel20. For example, the right edge of the sub-panel10shown inFIG.2is ground or cut by a grinding or cutting process. To prevent the cutting from affecting the effective display body, the cutting distance pc2 is required to be smaller than p1, i.e., pc2<p1. The grinding or cutting accuracy is pt, where pt<p1−pc2, i.e., pt<p8. As a result, the sub-panel20is obtained, in which the width p6 of the first pixel21in the first direction X is smaller than the width p of the third pixel13in the first direction X. That is, p6<p. In an exemplary embodiment, when the two sub-panels20are tiled along the first direction X, the assembly accuracy is pa, and thus, for cutting on one side, the width w1 of the seam is equal to pt+pa. In an exemplary embodiment, pa is about 0.02 mm, and pt is about 0.02 mm. Those skilled in the art may understand that the value of pa is determined according to different assembly conditions. For example, 0.005≤pa≤0.05. For example, inFIG.2, p=1 mm, p5=0.8 mm and p1=0.1 mm, then the cutting distance pc2 is equal to w1, where w1=0.04 mm. The right edge of the display panel inFIG.2is cut by 0.04 mm, and thus the sub-panel20inFIG.4may be obtained, with p8 of the sub-panel20being equal to 0.06 mm. FIG.7is a schematic structural diagram of a display panel according to an exemplary embodiment. As shown inFIG.7, the distance between an effective display body in the first pixel21and the first edge201is p8. The distance between an effective display body in the second pixel22and the second edge202is p9. In an exemplary embodiment, as shown inFIG.7, p8<p1, p9<p4, p24=p4, and p21=p1. The width p7 of the second pixel22in the first direction X is less than p. The width p6 of the first pixel21in the first direction X is less than p. In an exemplary embodiment, as shown inFIG.7, the difference between the sum of p1 and p4 and the sum of p8 and p9 may be equal to the width of the seam50between adjacent sub-panels, i.e., (p1+p4)−(p8+p9)=w1. In this way, the spacing between the effective display bodies on both sides of the seam50is equal to the spacing between the effective display bodies at the position other than the seam50, thereby improving uniformity of the display effect of the display panel. The sub-panel20shown inFIG.7may be obtained by processing the sub-panel10shown inFIG.2. For example, the left side and the right side of the sub-panel10inFIG.2may be ground or cut respectively to obtain the sub-panel20shown inFIG.7. The accuracy of the grinding or cutting process is pt, and assembly accuracy is pa. When cutting on both sides, the width w1 of the seam is equal to pa+pt. In an exemplary embodiment, pa is about 0.02 mm and pt is about 0.02 mm, so that the width w1 of the seam is equal to 0.04 mm. InFIG.2, p=1 mm, p5=0.8 mm, p1=0.1 mm and p4=0.1 mm. The sub-panel10shown inFIG.2may be processed by a grinding or cutting process to obtain a sub-panel20. The sub-panel10is cut on both sides, with a cutting distance of w½ on each side. That is, a cutting distance on one side is 0.02 mm. In another word, the sub-panel20shown inFIG.7may be obtained by respectively cutting the left edge and right edge of the sub-panel10inFIG.2by 0.02 mm. FIG.8is a schematic structural diagram of a display panel according to an exemplary embodiment. In an exemplary embodiment, as shown inFIG.8, the display panel may further include a plurality of sub-panels20tiled in sequence along a second direction Y (a direction perpendicular to the first direction X). A sub-panel20has a third edge203and a fourth edge204in the second direction Y. In the second direction Y, the sub-panel20includes a plurality of rows of pixels. The plurality of rows of pixels include a row of fifth pixels25closest to the third edge203, a row of sixth pixels26closest to the fourth edge204, and third pixels13between the row of fifth pixels25and the row of sixth pixels26. An effective display body135is provided in each of the fifth pixels25and the sixth pixels26. A sum of the distance between effective display bodies in the fifth pixels and the third edge and the distance between effective display bodies in the sixth pixels and the fourth edge is smaller than the spacing between the effective display bodies in two adjacent rows of third pixels. Those skilled in the art may understand that for convenience of illustration, only the tiling of two rows and two columns of sub-panels20is shown inFIG.8. The display panel has a seam50between two adjacent columns of sub-panels in the first direction X, and a seam60between two adjacent rows of sub-panels in the second direction Y. As shown inFIG.8, the distance between an effective display body in a fifth pixel25and the third edge203is p31. The distance between an effective display body in a sixth pixel26and the fourth edge204is p34. As shown inFIG.3, in the third pixel13, the distance between the effective display body135and the third boundary133is p2. The distance between the effective display body135and the fourth boundary134is p3. A sum of the distance between an effective display body in the fifth pixel and the third edge and the distance between an effective display body in the sixth pixel and the fourth edge is smaller than the spacing between the effective display bodies in two adjacent rows of third pixels. That is, the sum of p31 and p34 is smaller than the sum of p3 and p2, i.e., p31+p34<p3+p2. In this way, the spacing between the effective display bodies on both sides of the seam60may be reduced, so that the spacing between the effective display bodies in the second direction Y at the seam60is closer to the spacing between the effective display bodies in the second direction Y at the position other than the seam60, which improves the display effect of the display panel at the seam60and the uniformity of the display effect of the display panel. In an exemplary embodiment, as shown inFIG.8, the width of the seam between two adjacent sub-panels in the second direction Y is w2. The difference between the sum of p3 and p2 and the sum of p31 and p34 is substantially equal to w2. That is, the value of (p3+p2)−(p31+p34) are substantially equal to that of w2. Those skilled in the art may understand that there are process errors when tiling two sub-panels, and thus the value of (p3+p2)−(p31+p34) is generally equal to that of w2. That is, the values of (p3+p2)−(p31+p34) and w2 are within the allowable range of process errors, the value of (p3+p2)−(p31+p34) may be deemed to be equal to that of w2. In an exemplary embodiment, [(p3+p2)−(p31+p34)]/w2 is 95% to 105%, or w2/[(p3+p2)−(p31+p34)] is 95% to 105%. The width of the seam is the size of the seam in the direction perpendicular to the extending direction of the seam. As shown inFIG.8, the distance between an effective display body in the fifth pixel25and a boundary of the fifth pixel25towards the fourth edge204is p32. The distance between an effective display body in the sixth pixel26and a boundary of the sixth pixel26towards the third edge203is p33. In an exemplary embodiment, p31<p3, p34=p2, p32=p2, and p33=p3. In an exemplary embodiment, p31=p3, p34<p2, p32=p2, and p33=p3. In an exemplary embodiment, p31<p3, p34<p2, p32=p2, and p33=p3. Those skilled in the art may understand that in the sub-panel20, as shown inFIG.8, the distance between the right effective display body and the first edge201(left edge) is p8. The distance between the left effective display body and the second edge202(left edge) is p9. The distance between the lower effective display body and the third edge203(lower edge) is p31. The distance between the upper effective display body and the fourth edge204(upper edge) is p34. Therefore, the row of fifth pixel25close to the third edge203as described herein indicates that the size of each pixel in this row in the second direction Y is consistent, thus collectively referring to the fifth pixels, which cannot be understood as limiting the size of each pixel in this row in the first direction X. The row of sixth pixels26close to the fourth edge204as described herein indicates that the size of each pixel in this row in the second direction Y is consistent, thus collectively referring to the sixth pixels, which cannot be understood as limiting the size of each pixel in this row in the first direction X. The column of first pixels21close to the first edge201as described herein indicates that the size of each pixel in this column in the first direction X is consistent, thus collectively referring to the first pixels, which cannot be understood as limiting the size of each pixel in this column in the second direction Y. The column of second pixels22close to the second edge202as described herein indicates that the size of each pixel in this column in the first direction X is consistent, thus collectively referring to the second pixels, which cannot be understood as limiting the size of each pixel in this column in the second direction Y. FIG.9is a schematic sectional structural diagram of a display panel according to an exemplary embodiment. In an exemplary embodiment, as shown inFIG.9, the display panel includes a carrier base substrate41. A plurality of sub-panels20are tiled in sequence on the carrier base substrate41. The display panel further includes a fixing glue42provided between the sub-panel20and the carrier base substrate41, and a control circuit board43electrically connected to the sub-panel20. The sub-panel20includes a driving substrate28and a plurality of LED chips arranged on a side of the driving substrate28. The plurality of LED chips are located in a corresponding pixel. In an exemplary embodiment, as shown inFIG.9, the material of the carrier base substrate41may be transparent glass with a thickness of about 1.0 mm. The size of the carrier base substrate41may be determined as required. If it is needed to assemble n*m sub-panels in an applicable situation, the carrier base substrate41may be directly customized to meet the size requirements (if the customized size of the carrier base substrate41is too large, tiling of a plurality of carrier base substrates41may be available), and then the n*m sub-panels are assembled onto the carrier base substrate41. The fixing glue42is used to fix the sub-panel20and the carrier base substrate41. The fixing glue42may be a transparent optical glue (OCA glue or OCR glue). The micro LED or mini LED may include a red, a green and a blue LED. The driving substrate28is used to drive the LED to operate. Metal traces made of copper may be provided on the driving substrate28. The sub-panel inFIG.9may be a sub-panel as shown inFIG.7. Both the first edge and the second edge of the sub-panel are ground. As shown inFIG.9, G1=pt+pa, where pt is grinding accuracy and pa is assembly accuracy. In the case that pt=0.02 mm and pa=0.01 mm, the designed value of G1 is 0.03 mm. In order to ensure that the spacing deviation between the effective display bodies on both sides of the seam is less than 10 μm, the width of the driving substrate28is required to be 30 microns smaller than the designed size. FIG.10is a schematic top view of the sub-panels assembled on a carrier base substrate. As shown inFIG.10, during assembly, a mark70may be formed by exposing and developing at a certain corner on the carrier base substrate, and a mark may be formed by exposing and developing at a corresponding position of the sub-panel. Through assembly by optical focusing, the assembly accuracy is within 10 μm. If the size of the display panel is very large, tiling of a plurality of carrier base substrates41may be available.FIG.11is a schematic structural diagram of tiling of a plurality of display panels. As shown inFIG.11, the gap between the carrier base substrates is designed as follows: G2=dimensional tolerance A of the sub-panel+dimensional tolerance B of the carrier base substrate+assembly tolerance C of the sub-panel and the carrier base substrate; G3=dimensional tolerance B of the carrier base substrate. In order to ensure that the spacing between the effective display bodies on both sides of the seam is equal to, or has a deviation of less than or equal to p*δ from, the spacing between the adjacent effective display bodies at the position other than the seam. The sizes of the sub-panel and the carrier base substrate are required to be smaller than preset sizes. The specific values are as follows: reduction value of the sub-panel size being equal to A+B+C; reduction value of the carrier base substrate size being B. A seamless tiling method may include the following steps, as shown inFIG.10andFIG.9. S11: at least one cross mark70is formed on the carrier base substrate by exposing and developing. For example, four marks70may be formed. A cross mark is formed at a corresponding position of the sub-panel. S12: the carrier base substrate is cut or ground to a corresponding designed value, and a fixing glue is attached onto the carrier base substrate, where the thickness of the fixing glue is about 0.2 mm. S13: the first cross mark70serves as a datum point, and at the same time the cross mark at the corresponding position of the sub-panel is located, and the first sub-panel is assembled to a side of the carrier base substrate provided with the fixing glue by optical focusing. S14: the assembly equipment moves a preset step length to assemble a second sub-panel, and other sub-panels are assembled in the same manner. S15: the fixing glue is cured and defoamed. Subsequently, the carrier base substrate is fixed with a box body. In an exemplary embodiment, a seamless tiling method may include the following steps. S21: a cross mark70is respectively formed on the carrier base substrate at a preset position for the first sub-panel by exposing and developing processes, and a mark is formed at the corresponding position of the sub-panel. S22: the carrier base substrate is cut or ground to a corresponding designed value, and a fixing glue is attached onto the carrier base substrate, where the thickness of the fixing glue is about 0.2 mm. S23: the first cross mark70serves as a datum point, and at the same time the cross mark at the corresponding position of the sub-panel is located, and the first sub-panel is assembled to a side of the carrier base substrate provided with the fixing glue by optical focusing. S24: other sub-panels are assembled onto a side of the carrier base substrate provided with the fixing glue according to the method of S23. S25: the fixing glue is cured and defoamed. The principle of a method for eliminating defects of the display panel is to adjust the display time of each LED in the pixel one by one (lower or less than a standard value), so as to adjust the brightness of the LED for uniformity compensation. The method for eliminating the defects of the display panel may include the following steps. S31: each LED of the display panel is assigned a unique number in a system. S32: turn on each LED of the display panel. S33: a CCD camera may be used to shoot a cloud picture of the brightness of the whole display area. If the ratio of the brightness at the seam to the brightness at the center of the display panel is less than 1−δ, a duty ratio of the display time of the LED at the seam is increased, and the brightness of the LED at the seam is increased to more than 1−δ of the brightness at the center. If the ratio of the brightness at the seam to the brightness at the center of the display panel is greater than 1+δ, the duty ratio of the display time of LED at the seam is reduced, and the brightness of LED at the seam is reduced to below 1+δ of the brightness at the center, so as to control the brightness of the whole display area in a range from 1−δ to 1+δ of the brightness at the center, where 3%≤δ≤5%. FIG.12is a schematic structural diagram of a display panel according to an exemplary embodiment. In an exemplary embodiment, as shown inFIG.12, the display panel may further include a touch layer44. The touch layer44may be located between the carrier base substrate41and the fixing glue42. When a user presses on a certain position of the carrier base substrate, the touch layer transmits positional information of the pressing point to a touch circuit to realize response. In another aspect, the present disclosure also provides a display apparatus, including a display panel according to the aforementioned embodiments. The display apparatus may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. In the description of the present disclosure, it should be understood that, an orientational or positional relationship indicated by terms “inside”, “outside” or the like is based on the orientational or positional relationship shown in the drawings, and it is only for ease of description of the present disclosure and simplification of the description, rather than indicating or implying that the referred apparatus or element must have a specific orientation, or be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. In the description of the present disclosure, it should be noted that unless otherwise explicitly specified and defined, a term “connect” should be understood broadly, for example, it may be an electrical connection; it may be a direct connection, or it may be an indirect connection through an intermediate medium, or it may be an internal communication of two elements. For those of ordinary skills in the art, the specific meanings of the above terms in the present disclosure may be understood according to specific situations. Although implementations disclosed in the present disclosure are as the above, the described contents are only implementations used for facilitating the understanding of the present disclosure, and are not used to limit the present disclosure. Any person skilled in the art to which the present disclosure pertains may make any modifications and variations in the forms and details of implementation without departing from the spirit and the scope of the present disclosure, but the patent protection scope shall still be subject to the scope defined in the appended claims. | 36,263 |
11862618 | It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given example embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature. DETAILED DESCRIPTION Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. FIG.1is a schematic sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Referring toFIG.1, a semiconductor package100may include a first semiconductor chip C1including a logic structure IC and a second semiconductor chip C2including a power decoupling capacitor. The first semiconductor chip C1may include a first semiconductor substrate10, the logic structure IC provided on a first surface10aof the first semiconductor substrate10, a power delivery network PDN or a power distribution network, which is provided on a second surface of the first semiconductor substrate10and is connected to the logic structure IC through a plurality of penetration vias TSV, and first bonding pads BP1. The first bonding pads BP1may be provided in the uppermost metal layer of the power delivery network PDN. The first semiconductor chip C1may be a micro electro mechanical systems (MEMS) device, an optoelectronic device, or a logic chip including processors (e.g., a central processing unit (CPU), a graphic processing unit (GPU), a mobile application chip, or a digital signal processor (DSP)). In this disclosure, the terms “uppermost” and “lowermost” may refer to positions relative to a bottom surface of the semiconductor package100at which outer connection terminals150are attached, or positions relative to the bottom of each of the figures. The second semiconductor chip C2may include a second semiconductor substrate20, a capacitor layer PDC provided on the second semiconductor substrate20, and second bonding pads BP2. The second bonding pads BP2may be provided in the uppermost metal layer of the capacitor layer PDC. The semiconductor package100may include chip pads111, which are provided on a bottom surface of the second semiconductor chip C2, and the outer connection terminals (or alternatively, connection terminals)150may be attached to the chip pads. The semiconductor package100may be a chip-to-chip (C2C) structure, which is formed by fabricating the first semiconductor chip C1on a first wafer, fabricating the second semiconductor chip C2on a second wafer different from the first wafer, and connecting the first semiconductor chip C1to the second semiconductor chip C2in a bonding manner. In the bonding manner, the first bonding pads BP1of the first semiconductor chip C1may be electrically connected to the second bonding pads BP2of the second semiconductor chip C2. For example, in the case where the first and second bonding pads BP1and BP2are formed of copper (Cu), the bonding manner may be a Cu-to-Cu bonding manner, but in an example embodiment, the first and second bonding pads BP1and BP2may be formed of aluminum (Al) or tungsten (W). In an example embodiment, the first and second semiconductor chips C1and C2may be connected to each other using connection terminals (not shown) (e.g., conductive bumps, conductive pillars, and solder balls), which are provided between the first and second bonding pads BP1and BP2. FIG.2is a layout diagram illustrating a logic structure of a semiconductor package according to an example embodiment of the inventive concepts.FIG.3is a sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIGS.4A and4Bare enlarged sectional views illustrating a portion P ofFIG.3. Referring toFIGS.2and3, the first semiconductor chip C1may include the first semiconductor substrate10, the logic structure IC, and the power delivery network PDN. The logic structure IC may include logic devices, which are integrated on a first surface10aof the first semiconductor substrate10, and signal lines INC1, which are connected to the logic devices. The logic devices may include at least one of an AND circuit, an OR circuit, a NOR circuit, an inverter circuit, or a latch circuit. Further, the logic devices may include field effect transistors, resistors, or the like. For example, the first semiconductor substrate10may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate. As an example, the first semiconductor substrate10may be a silicon wafer. Buried power rails BPR1, BPR2, and BPR3may be provided in the first semiconductor substrate10. The buried power rails BPR1, BPR2, and BPR3may be extended in a first direction D1and parallel to each other. In an example embodiment, the buried power rails BPR1, BPR2, and BPR3may include first, second, and third buried power rails BPR1, BPR2, and BPR3. The first and third buried power rails BPR1and BPR3may be interconnection lines, to which a power voltage is applied, and the second buried power rail BPR2may be an interconnection line, to which a ground voltage is applied. The first semiconductor substrate10may include a first logic circuit region R1between the first and second buried power rails BPR1and BPR2and a second logic circuit region R2between the second and third buried power rails BPR2and BPR3. Each of the first and second logic circuit regions R1and R2may include first and second active regions NR and PR. As an example, PMOS field effect transistors may be provided on the first active region NR, and NMOS field effect transistors may be provided on the second active region PR. The first and second active regions NR and PR of the first semiconductor substrate10may be doped with dopants of different conductivity types. A plurality of first active patterns AP1may be provided in the first active region NR to extend in the first direction D1and may be spaced apart from each other in a second direction D2crossing the first direction D1. A plurality of second active patterns AP2may be provided in the second active region PR to extend in the first direction D1and may be spaced apart from each other in the second direction D2. The first and second active patterns AP1and AP2may be portions of the first semiconductor substrate10and may be defined by first trenches, which are formed in the first semiconductor substrate10. An example, in which three first active patterns AP1are provided, is illustrated, but the number of the first active patterns AP1is not limited thereto and is variously changed. This is the same for the second active patterns AP2. In an example embodiment, each of the first and second active patterns AP1and AP2may include a plurality of channel patterns, which are vertically stacked to be spaced apart from each other. The stacked channel patterns may be vertically overlapped with each other. The channel patterns may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). A device isolation layer11may be disposed between the first active patterns AP1and between the second active patterns AP2. The device isolation layer11may separate the first and second active patterns AP1and AP2from each other in the second direction D2. The first and second active patterns AP1and AP2may include upper portions, which are exposed by the device isolation layer11. For example, the device isolation layer11may have a top surface that is located at a level lower than top surfaces of the first and second active patterns AP1and AP2, and the upper portions of the first and second active patterns AP1and AP2may protrude above the top surface of the device isolation layer11. Gate structures GS may be extended in the second direction D2to cross the first and second active patterns AP1and AP2of the first and second active regions NR and PR. The gate structures GS may be arranged with a uniform pitch. In other words, the gate structures GS may have substantially the same width and may be spaced apart from each other by a uniform distance in the first direction D1. In the case where each of the first and second active patterns AP1and AP2includes the channel patterns that are vertically stacked, the gate structure GS may include a gate electrode (not shown), which is provided to surround each of the channel patterns. The gate electrode may be provided to face or cover top, bottom, and opposite side surfaces of each of the channel patterns. In other words, the logic device may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET), in which the gate electrode is provided to three-dimensionally surround the channel patterns. Furthermore, as shown inFIGS.2and3, first and second active contacts AC1and AC2may be provided on the first and second active patterns AP1and AP2and at both sides of the gate structures GS. The active contacts AC1and AC2may be in direct contact with the first and second active patterns AP1and AP2or may be connected to the first and second active patterns AP1and AP2through source/drain patterns (not shown). Here, the source/drain patterns may be epitaxial patterns that are formed by a selective epitaxial growth process. In an example embodiment, the active contacts AC1and AC2may include first active contacts AC1, which are connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3, and second active contacts AC2, which are connected to the signal lines INC1. The first, second, and third buried power rails BPR1, BPR2, and BPR3may be partially buried in the first semiconductor substrate10. The first, second, and third buried power rails BPR1, BPR2, and BPR3may be provided in the device isolation layer11. The first, second, and third buried power rails BPR1, BPR2, and BPR3may be in direct contact with the first active contacts AC1. The first, second, and third buried power rails BPR1, BPR2, and BPR3may have top surfaces that are located at a level lower than the top surfaces of the first and second active patterns AP1and AP2. A buried signal line BS1may be provided at the same level as the first, second, and third buried power rails BPR1, BPR2, and BPR3. Input/output signals, which are input through chip pads111, may be delivered to the signal lines INC1through the buried signal line BSI and the penetration via TSV. A first interlayer insulating layer13may be provided to fill spaces between the gate structures GS and between the active contacts AC1and AC2. The first interlayer insulating layer13may be provided to cover the first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI. A second interlayer insulating layer15may be disposed on the first interlayer insulating layer13. The signal lines INC1, which are electrically connected to the logic devices, may be provided on the second interlayer insulating layer15. The signal lines INC1may be electrically connected to the gate structures GS or the second active contacts AC2through a plurality of contact plugs. The signal lines INC1may include a plurality of metal lines, which are stacked with inter-metal insulating layers IMD1interposed therebetween. A surface insulating layer120may be disposed on a second surface10bof the first semiconductor substrate10, and the penetration vias TSV may be provided to penetrate the surface insulating layer120and the first semiconductor substrate10and may be coupled to the first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI. The penetration vias TSV may have a diameter of about 50 nm to about 150 nm. The penetration vias TSV may have a vertical length of about 300 nm to about 1 μm. Although not shown, an insulating layer (not shown) may be interposed between side surfaces of the penetration vias TSV and the first semiconductor substrate10. The penetration vias TSV may be formed of or include at least one of metallic materials (e.g., W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB). The power delivery network PDN may be provided on the second surface10bof the first semiconductor substrate10. The power delivery network PDN may include a plurality of power lines INC2, which are stacked with inter-metal insulating layers IMD2interposed therebetween. The power lines INC2may be interconnection lines, which are used to deliver a power voltage or a ground voltage. The power lines INC2may be electrically connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3through the penetration vias TSV, which are provided to penetrate the first semiconductor substrate10. The power lines INC2may be formed of or include at least one of metallic materials. The first bonding pads BP1may be provided in the uppermost metal layer of the power delivery network PDN. The first bonding pads BP1may be electrically connected to the power lines INC2. The first bonding pads BP1may be formed of or include at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN). The second semiconductor chip C2may include the capacitor layer PDC, which is integrated on the second semiconductor substrate20. The second semiconductor substrate20may be a semiconductor substrate including silicon, germanium, silicon-germanium, or the like or a compound semiconductor substrate. In an example embodiment, the second semiconductor substrate20may be a silicon wafer. Referring toFIGS.3,4A, and4B, the capacitor layer PDC may be provided on a front surface of the second semiconductor substrate20(e.g., a first surface of the second semiconductor substrate20facing the power delivery network PDN), and the chip pads111may be provided on a rear surface of the second semiconductor substrate20(e.g., a second surface of the second semiconductor substrate20opposite to the first surface of the second semiconductor substrate20). The outer connection terminals150may be attached to the chip pads111. The chip pads111may be formed of or include at least one of metallic materials (e.g., copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or alloys thereof). The capacitor layer PDC may include lower and upper interconnection lines INCa and INCb and power decoupling capacitors CAP. The lower and upper interconnection lines INCa and INCb may be formed of or include at least one of metallic materials (e.g., copper, tungsten, and/or titanium). The power decoupling capacitors CAP may be arranged in rows and columns to form an array. The power decoupling capacitors CAP may include a plurality of capacitors that are connected in parallel to each other. For example, referring toFIG.4A, the power decoupling capacitor CAP may be provided between a bottom electrode pad BCP and a top electrode pad TCP and may include a plurality of bottom electrodes BE, a capacitor dielectric layer DIL, and a top electrode TE. The bottom electrodes BE may have a pillar shape, as shown inFIG.4A. The bottom electrodes BE may have top surfaces that are substantially coplanar with each other. The bottom electrodes BE may have a uniform top width. The bottom electrodes BE may be arranged in a shape of zigzag or honeycomb on the bottom electrode pad BCP. Because the bottom electrodes BE are arranged in the zigzag or honeycomb shape, it may be easy to increase diameters of the bottom electrodes BE or it may be possible to increase an integration density of the bottom electrodes BE. As another example, the bottom electrodes BE may be spaced apart from each other by a specific distance in two different directions (e.g., first and second directions) and be arranged in a matrix shape. The bottom electrodes BE may be connected in common to the bottom electrode pad BCP, and the bottom electrode pad BCP may be connected to the lower interconnection lines INCa through contact plugs. The lower interconnection lines INCa may be provided on the second semiconductor substrate20with an insulating layer25interposed therebetween. The capacitor dielectric layer DIL may cover outer surfaces of the bottom electrodes BE with a uniform thickness. The capacitor dielectric layer DIL may also cover the bottom electrode pad BCP between the bottom electrodes BE. The top electrode TE may be provided on the capacitor dielectric layer DIL to conformally cover the bottom electrodes BE. In an example embodiment, the top electrode TE may be provided on the capacitor dielectric layer DIL to fill a space between the bottom electrodes BE. The top electrode TE may cover an entirety of the bottom electrodes. The bottom electrodes BE and the top electrode TE may be formed of or include at least one of high melting point metals (e.g., cobalt, titanium, nickel, tungsten, and molybdenum) and/or metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tungsten nitride (WN)). The capacitor dielectric layer DIL may be formed of at least one selected from the group consisting of metal oxides (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and perovskite dielectric materials (e.g., SrTiO3(STO), (Ba,Sr)TiO3(BST), BaTiO3, PZT, and PLZT) and may have a single- or multi-layered structure. The top electrode pad TCP may be disposed on the top electrode TE. The top electrode pad TCP may be provided on an interlayer insulating layer ILD to be in direct contact with portions of the top electrode TE. The top electrode pad TCP may be formed of or include at least on one of conductive materials, which is different from the top electrode TE, or doped semiconductor materials. The top electrode pad TCP may be formed of or include at least one of, for example, doped polysilicon, silicon germanium, and/or metals (e.g., tungsten, copper, aluminum, titanium, and tantalum). As another example, referring toFIG.4B, each of the bottom electrodes BE of the power decoupling capacitor CAP may have a cylindrical shape including a bottom portion and a sidewall portion, which is vertically extended from the bottom portion to define an empty space. Each of the bottom electrodes BE may have a cup shape conformally covering inner surfaces of openings of a mold insulating layer ML. The capacitor dielectric layer DIL and the top electrode TE may be sequentially disposed on the mold insulating layer ML to conformally cover the bottom electrodes BE. The capacitor dielectric layer DIL may be formed to cover inner surfaces of the bottom electrodes BE with a uniform thickness. The top electrode TE may be provided on the capacitor dielectric layer DIL to cover the bottom electrodes BE. Further, the top electrode TE may cover a surface of the capacitor dielectric layer DIL with a uniform thickness. In an example embodiment, the top electrode TE may be provided to define gap regions in the openings of the mold insulating layer ML. Referring back toFIG.3, the power decoupling capacitors CAP may be electrically connected to the chip pads111and the second bonding pads BP2through the lower and upper interconnection lines INCa and INCb. The second bonding pads BP2may be provided in the uppermost metal layer of the capacitor layer PDC. The second bonding pads BP2may be directly bonded to the first bonding pads BP1of the first semiconductor chip C1. Further, a surface of an insulating layer IMD3of the capacitor layer PDC may be directly bonded to a surface of an insulating layer IMD2of the power delivery network PDN. In other words, the first and second semiconductor chips C1and C2may be bonded to have a hybrid bonding structure. The hybrid bonding structure may mean a bonding structure, in which two materials of the same kind are fused at an interface therebetween. FIGS.5A and5Bare sectional views illustrating a semiconductor package according to an example embodiment of the inventive concepts. According to the example embodiment shown inFIG.5A, the semiconductor package100may include the first and second semiconductor chips C1and C2, connection terminals30therebetween, and a mold layer50. The first and second semiconductor chips C1and C2may be configured to have substantially the same technical features as the first and second semiconductor chips C1and C2described with reference toFIG.3, and thus a detailed description thereof may be omitted. The connection terminals30may be provided between and attached to the first bonding pads BP1of the first semiconductor chip C1and the second bonding pads BP2of the second semiconductor chip C2. An under-fill layer35may be provided to fill a space between the first and second semiconductor chips C1and C2and between the connection terminals30. The under-fill layer35may be formed of or include at least one of, for example, thermosetting resins or photo-curable resins. The under-fill layer35may include an inorganic filler or an organic filler. As another example, the under-fill layer35may be omitted, and the mold layer50may be provided to fill a space between the first and second semiconductor chips C1and C2. The mold layer50may be provided on the power delivery network PDN of the first semiconductor chip C1to cover the second semiconductor chip C2. The mold layer50may have a side surface that is aligned to a side surface of the first semiconductor chip C1. The mold layer50may have a top surface that is substantially coplanar with the rear surface (or a bottom surface) of the second semiconductor substrate20. The mold layer50may be formed of or include at least one of insulating polymers (e.g., an epoxy molding compound). In the case where the under-fill layer35is omitted, the space between the first and second semiconductor chips C1and C2may be filled with the mold layer50. According to the example embodiment shown inFIG.5B, the semiconductor package100may include the first and second semiconductor chips C1and C2that are bonded to each other, and the first semiconductor chip C1may include the first semiconductor substrate10, the logic structure IC, and the power delivery network PDN, as described with reference toFIG.3. The second semiconductor chip C2may include the capacitor layer PDC integrated on the second semiconductor substrate20. In an example embodiment, the capacitor layer PDC may include the lower and upper interconnection lines INCa and INCb and metal-insulator-metal (MIM) capacitors CAP. For example, the MIM capacitors CAP may include the bottom electrode BE, the top electrode TE, and the capacitor dielectric layer DIL therebetween. The bottom electrode BE, the capacitor dielectric layer DIL, and the top electrode TE may be disposed to be parallel to a top surface of the second semiconductor substrate20. The bottom electrode BE may be connected to the lower interconnection lines through the contact plugs. The bottom electrode BE may be formed by depositing a metal layer on an insulating layer and patterning the metal layer. The capacitor dielectric layer DIL and the top electrode TE may be sequentially stacked on the bottom electrode BE. The top electrode TE may be connected to the upper interconnection lines through the contact plugs. FIG.6is a schematic sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIG.7is a sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. For concise description, elements previously described with reference toFIGS.1to5may be identified by the same reference number without repeating an overlapping description thereof. Referring toFIGS.6and7, the semiconductor package100may include the first and second semiconductor chips C1and C2, which are bonded to each other. Here, the first semiconductor chip C1may include the logic structure IC, and the second semiconductor chip C2may include the capacitor layer PDC and the power delivery network PDN. The first semiconductor chip C1may include the first semiconductor substrate10, the logic structure IC, which is provided on the first surface of the first semiconductor substrate10, the penetration vias TSV, which penetrates the first semiconductor substrate10and are connected to the logic structure IC, and the first bonding pads BP1, which are provided on the second surface of the first semiconductor substrate10. A polymer layer, which is formed of or includes an insulating material, may be provided between the first bonding pads BP1. The surface insulating layer120may be disposed on the second surface of the first semiconductor substrate10, and the penetration vias TSV may penetrate the surface insulating layer120and the first semiconductor substrate10and may be connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI. The second semiconductor chip C2may include the second semiconductor substrate20, the capacitor layer PDC, which is provided on the second semiconductor substrate20, the power delivery network PDN, which is provided on the capacitor layer PDC, and the second bonding pads BP2. The second bonding pads BP2may be provided in the uppermost metal layer of the power delivery network PDN. The capacitor layer PDC may include the lower and upper interconnection lines INCa and INCb and the power decoupling capacitors CAP, as described above. The power delivery network PDN may include the power lines INC2, which are stacked with inter-metal insulating layers interposed therebetween. The power lines INC2may be electrically connected to the lower and upper interconnection lines INCa and INCb and the power decoupling capacitors CAP of the capacitor layer PDC through the contact plugs. The power delivery network PDN may be electrically connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3of the first semiconductor chip C1through the first and second bonding pads BP1and BP2. The semiconductor package100may include the chip pads111, which are provided on the bottom surface of the second semiconductor chip C2, and connection terminals150may be attached to the chip pads111. FIG.8is a schematic sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIG.9is a sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Referring toFIGS.8and9, the first semiconductor chip C1may include the first semiconductor substrate10, the logic structure IC, and the power delivery network PDN, and the second semiconductor chip C2may include the second semiconductor substrate20and the capacitor layer PDC. The first semiconductor chip C1may include the first bonding pads BP1, which are provided in the uppermost metal layer of the logic structure IC, and the second semiconductor chip C2may include the second bonding pads BP2, which are provided in the lowermost metal layer of the capacitor layer PDC. The first and second bonding pads BP1and BP2of the first and second semiconductor chips C1and C2may be bonded to each other. Further, the first semiconductor chip C1of the semiconductor package100may include the chip pads111, which are provided in the lowermost metal layer of the power delivery network PDN. The power delivery network PDN of the first semiconductor chip C1may be provided on the second surface (e.g., a bottom surface) of the first semiconductor substrate10and may be electrically connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3through the penetration vias TSV. FIG.10is a sectional view illustrating a semiconductor package module including a semiconductor package, according to an example embodiment of the inventive concepts. Referring toFIG.10, a semiconductor package module1000may include the first semiconductor package100, second semiconductor packages200, a redistribution substrate300, a package substrate500, and a heat-dissipation structure600. The first and second semiconductor packages100and200may be disposed on a top surface of the redistribution substrate300. The first semiconductor package100may have substantially the same structure as the semiconductor package100in the previously-described example embodiment. For example, the first semiconductor package100may include the first and second semiconductor chips C1and C2, which are bonded to each other, and the first and second semiconductor chips C1and C2may include the logic structure IC and the capacitor layer PDC, respectively. The second semiconductor packages200may be disposed on the redistribution substrate300to be spaced apart from the first semiconductor package100. Each of the second semiconductor packages200may include a plurality of memory chips210, which are vertically stacked. The memory chips210may be electrically connected to each other through lower and upper chip pads221and223, chip through vias225, and connection bumps230. The memory chips210may be stacked on the redistribution substrate300in such a way that side surfaces thereof are aligned to each other. An adhesive layer may be provided between each adjacent pair of the memory chips210. For example, the adhesive layer may be a polymer tape including an insulating material. The adhesive layer may be interposed between the connection bumps230to mitigate or prevent a short circuit issue from occurring between the connection bumps230. The first and second semiconductor packages100and200may be connected to the redistribution substrate300through first connection terminals150. The first connection terminals150may be attached to the lower chip pads111and221of the first and second semiconductor packages100and200. The first connection terminals150may include at least one of solder balls, conductive bumps, or conductive pillars. The first connection terminals150may be formed of or include at least one of copper, tin, or lead. For example, the first connection terminals150may have a thickness of about 30 μm to about 70 μm. A mold layer400may be provided on the redistribution substrate300to cover the first and second semiconductor packages100and200. A side surface of the mold layer400may be aligned to a side surface of the redistribution substrate300. A top surface of the mold layer400may be substantially coplanar with top surfaces of the first and second semiconductor packages100and200. The mold layer400may be formed of or include at least one of insulating polymers (e.g., an epoxy molding compound). A first under-fill layer may be interposed between the first semiconductor package100and the redistribution substrate300and between the second semiconductor packages200and the redistribution substrate300. The first under-fill layer may be provided to fill a space between the first connection terminals150. The first under-fill layer may be formed of or include at least one of, for example, thermosetting resins or photo-curable resins. The first under-fill layer may further include an inorganic filler or an organic filler. In an example embodiment, the first under-fill layer may be omitted, and the spaces between the first and second semiconductor packages100and200and the redistribution substrate300may be filled with the mold layer400. The redistribution substrate300may be disposed on the package substrate500and may be connected to the package substrate500through second connection terminals350. The redistribution substrate300may include a plurality of insulating layers, which are sequentially stacked, and redistribution patterns, which are provided in each of the insulating layers. The redistribution patterns, which are provided in different insulating layers, may be electrically connected to each other through via portions. The second connection terminals350may be attached to lower pads of the redistribution substrate300. The second connection terminals350may be solder balls, which are formed of tin, lead, copper, or the like. The second connection terminals350may have a thickness of about 40 μm to about 80 μm. The package substrate500may be, for example, a printed circuit board, a flexible substrate, a tape substrate, or the like. In an example embodiment, the package substrate500may be one of a flexible printed circuit board, a rigid printed circuit board, or combinations thereof, in which internal lines521are provided. The package substrate500may have a top surface and a bottom surface, which are opposite to each other, and may include upper coupling pads511, outer coupling pads513, and the internal lines521. The upper coupling pads511may be arranged on the top surface of the package substrate500, and the outer coupling pads513may be arranged on the bottom surface of the package substrate500. The upper coupling pads511may be electrically connected to the outer coupling pads513through the internal lines521. Outer coupling terminals550may be attached to the outer coupling pads513. A ball grid array (BGA) may be provided as the outer coupling terminals550. The heat-dissipation structure600may be formed of or include at least one of thermally conductive materials. The thermally conductive materials may include metallic materials (e.g., copper and/or aluminum) or carbon-containing materials (e.g., graphene, graphite, and/or carbon nanotube). The heat-dissipation structure600may have a relatively high thermal conductivity. As an example, a single metal layer or a plurality of stacked metal layers may be used as the heat-dissipation structure600. As another example, the heat-dissipation structure600may include a heat sink or a heat pipe. As other example, the heat-dissipation structure600may be realized using a water cooling method. A heat conduction layer650may be interposed between the first and second semiconductor packages100and200and the heat-dissipation structure600. The heat conduction layer650may be in contact with the top surfaces of the first and second semiconductor packages100and200and a bottom surface of the heat-dissipation structure600. The heat conduction layer650may be formed of or include a thermal interface material (TIM). The thermal interface material may include, for example, polymer and thermally conductive particles. The thermally conductive particles may be dispersed in the polymer. During the operation of the semiconductor package, heat produced in the semiconductor package may be transferred to the heat-dissipation structure600through the heat conduction layer650. FIGS.11to15are sectional views illustrating a method of fabricating a semiconductor package, according to an example embodiment of the inventive concepts. Referring toFIG.11, the first semiconductor substrate10may be provided. For example, the first semiconductor substrate10may be a silicon substrate. The first semiconductor substrate10may include chip regions CR and a scribe line region between the chip regions CR. The first semiconductor substrate10may include the first surface10aand the second surface10b, which are opposite to each other. In each of the chip regions CR, the first and second active patterns AP1and AP2may be formed on the first surface10aof the first semiconductor substrate10. The first and second active patterns AP1and AP2may be line-shaped patterns, which are extended in the first direction D1and parallel to each other, as previously described with reference toFIG.2. The first and second active patterns AP1and AP2may be defined by trenches, which are formed by patterning the first semiconductor substrate10. For example, the first and second active patterns AP1and AP2may be portions of the first semiconductor substrate10, which are defined by the trenches formed in the first semiconductor substrate10. The device isolation layer11may be formed between the first and second active patterns AP1and AP2. The device isolation layer11may be formed to have a top surface, which is lower than top surfaces of the first and second active patterns AP1and AP2, and thereby to expose upper portions of the first and second active patterns AP1and AP2. The first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI may be formed before or after the formation of the first and second active patterns AP1and AP2. The first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI may be formed of or include at least one of metallic materials (e.g., tungsten, aluminum, titanium tantalum, titanium nitride, tantalum nitride, and/or tungsten nitride). The first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI may be formed by patterning the device isolation layer11and the first semiconductor substrate10to form trenches, filling the trenches with a metal layer, and recessing (or planarizing) the metal layer. The first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI may have top surfaces that are located at a level lower than the top surfaces of the first and second active patterns AP1and AP2. The first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI may have bottom surfaces that are located at a level lower than a bottom surface of the device isolation layer11. The gate structures GS (e.g., seeFIG.2) and the active contacts AC1and AC2may be formed after the formation of the first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI. The active contacts AC1and AC2may be formed to penetrate the first interlayer insulating layer13and to be in contact with the first or second active patterns AP1or AP2. Each of the active contacts AC1and AC2may include a barrier metal layer and a metal layer. The active contacts AC1and AC2may be formed to have top surfaces that are substantially coplanar with a top surface of the first interlayer insulating layer13. The second interlayer insulating layer15may be formed on the first interlayer insulating layer13to cover the top surfaces of the active contacts AC1and AC2. Referring toFIG.12, the signal lines INC1may be stacked on the second interlayer insulating layer15with an inter-metal insulating layer interposed therebetween. The signal lines INC1, which are vertically stacked, may be electrically connected to each other through contact plugs. Referring toFIG.13, a thinning process may be performed to reduce a thickness of the first semiconductor substrate10. The thinning process may include grinding or polishing the second surface10bof the first semiconductor substrate10and anisotropically and/or isotropically etching the first semiconductor substrate10. For the thinning process on the first semiconductor substrate10, a dummy substrate DMY may be attached to the uppermost insulating layer of the logic structure IC using an adhesive layer110. After the attachment of the dummy substrate DMY, the first semiconductor substrate10may be vertically inverted. A portion of the first semiconductor substrate10may be removed by the grinding or polishing process, and then, the anisotropic or isotropic etching process may be performed to remove surface defects from the remaining portion of the first semiconductor substrate10. The surface insulating layer120may be formed on the second surface10bof the first semiconductor substrate10, and then, the second surface10bof the first semiconductor substrate10may be patterned to form penetration holes exposing the first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI. The penetration holes may be formed to have a vertical length of about 1 μm or less. Next, a metallic material may be formed to fill the penetration holes, and the penetration vias TSV may be formed by planarizing the metallic material to expose the surface insulating layer120. Referring toFIG.14, the power delivery network PDN may be formed on the surface insulating layer120. The formation of the power delivery network PDN may include forming the power lines INC2with inter-metal insulating layers interposed therebetween. Further, the first bonding pads BP1may be formed in the uppermost metal layer of the power delivery network PDN. The first bonding pads BP1may be electrically connected to the power lines INC2. Referring toFIG.15, the second semiconductor substrate20including the capacitor layer PDC may be provided on the power delivery network PDN. For example, the second semiconductor substrate20may be a silicon substrate. The second semiconductor substrate20may include the chip regions CR and the scribe line region between the chip regions CR, similar to the first semiconductor substrate10. The power decoupling capacitors CAP may be formed on the chip regions CR of the second semiconductor substrate20. The lowermost metal layer of the capacitor layer PDC may include the second bonding pads BP2. The second semiconductor substrate20may be aligned to the first semiconductor substrate10such that the chip regions CR of the first semiconductor substrate10are vertically overlapped with the chip regions CR of the second semiconductor substrate20. The first bonding pads BP1and the second bonding pads BP2may be disposed to correspond to each other and may be directly bonded to each other. The first and second bonding pads BP1and BP2may be formed of or include at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN), and in the case where the first and second bonding pads BP1and BP2are formed of copper (Cu), the first and second bonding pads BP1and BP2may be physically and electrically connected to each other in a copper (Cu)-copper (Cu) bonding manner. Further, surfaces of the insulating layers of the capacitor layer PDC and the power delivery network PDN may be bonded to each other in a dielectric-dielectric bonding manner. For the bonding between the first and second bonding pads BP1and BP2, pressure and heat may be applied to the second semiconductor substrate20. For example, the first and second bonding pads BP1and BP2may be treated by an annealing process, which is performed at a temperature of about 100° C. to 500° C. under pressure lower than about 30 MPa. However, the inventive concepts are not limited to this example, and the pressure and temperature conditions for the bonding process may be variously changed. After the bonding between the first and second bonding pads BP1and BP2, a cutting process may be performed along the scribe line region to separate the chip regions CR of the first and second semiconductor substrates10and20from each other, and thus the semiconductor package100may be formed to have the same structure as described with reference toFIG.3. Here, the cutting process may be performed using a sawing blade or a laser beam. FIG.16is a sectional view illustrating a method of fabricating a semiconductor package, according to an example embodiment of the inventive concepts. Referring toFIG.16, the first semiconductor substrate10, on which the logic structure IC and the power delivery network PDN are formed, may be provided, as described with reference toFIGS.12to14. A plurality of second semiconductor chips C2may be provided on the chip regions CR of the first semiconductor substrate10, respectively. Each of the second semiconductor chips C2may include the second semiconductor substrate20and the capacitor layer PDC on the second semiconductor substrate20, as described above, and the second bonding pads BP2may be disposed in the lowermost metal layer of the capacitor layer PDC. The second semiconductor chips C2may be provided in such a way that the second bonding pads BP2thereof face the first bonding pads BP1on the first semiconductor substrate10. The first and second bonding pads BP1and BP2may be connected to each other through the connection terminals30. Next, the under-fill layer35may be formed to fill a space between the power delivery network PDN and the capacitor layer PDC, and the mold layer50(e.g., seeFIG.5A) may be formed on the insulating layer of the power delivery network PDN. The mold layer50(e.g., seeFIG.5A) may be formed to thickly cover the second semiconductor chips C2, and then a grinding process may be performed to expose the second semiconductor substrate20. After the formation of the mold layer50, a cutting process may be performed along the scribe line region to form the semiconductor package100described with reference toFIG.5A or5B. FIGS.17and18are sectional views illustrating a method of fabricating a semiconductor package, according to an example embodiment of the inventive concepts. Referring toFIG.17, the logic structure IC may be formed on the first surface10aof the first semiconductor substrate10, as previously described with reference toFIGS.11to13, and then, the penetration vias TSV may be formed to penetrate the first semiconductor substrate10and to be connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3. After the formation of the penetration vias TSV, the first bonding pads BP1may be formed on the second surface10bof the first semiconductor substrate10. Some of the first bonding pads BP1may be connected to the penetration vias TSV. Referring toFIG.18, the second semiconductor substrate20, on which the capacitor layer PDC and the power delivery network PDN are formed, may be provided on the first semiconductor substrate10. The capacitor layer PDC, which includes the power decoupling capacitors CAP, may be formed on a front surface of the second semiconductor substrate20(e.g., a first surface of the second semiconductor substrate20facing the power delivery network PDN), and the power delivery network PDN, which includes the power lines INC2electrically connected to the power decoupling capacitors CAP, may be formed on the capacitor layer PDC. The lowermost metal layer of the power delivery network PDN may be formed to include the second bonding pads BP2. Next, the first semiconductor substrate10and the second semiconductor substrate20may be bonded to each other such that the first bonding pads BP1of the first semiconductor substrate10are in direct contact with the second bonding pads BP2of the second semiconductor substrate20. Accordingly, the power lines INC2may be electrically connected to the buried power rails BPR1, BPR2, and BPR3through the first and second bonding pads BP1and BP2and the penetration vias TSV. After the bonding between the first and second bonding pads BP1and BP2, a cutting process may be performed along the scribe line region to separate the chip regions CR of the first and second semiconductor substrates10and20from each other, and thus the semiconductor package100may be formed to have the same structure as described with reference toFIGS.6and7. FIGS.19to22are sectional views illustrating a method of fabricating a semiconductor package, according to an example embodiment of the inventive concepts. Referring toFIG.19, the logic structure IC may be formed on the first surface10aof the first semiconductor substrate10, as described with reference toFIGS.10and11. The signal lines INC1may be formed on the first surface10aof the first semiconductor substrate10, and the first bonding pads BP1may be formed in the uppermost metal layer of the signal lines INC1. Referring toFIG.20, the second semiconductor substrate20including the capacitor layer PDC may be provided on the first semiconductor substrate10. The capacitor layer PDC may include the power decoupling capacitors CAP, and the lowermost metal layer of the capacitor layer PDC may include the second bonding pads BP2connected to the power decoupling capacitors CAP. The first semiconductor substrate10and the second semiconductor substrate20may be bonded to each other such that the first bonding pads BP1in the logic structure IC are directly bonded to the second bonding pads BP2in the capacitor layer PDC. Next, referring toFIG.21, the first semiconductor substrate10may be vertically inverted, and then a thinning process may be performed on the first semiconductor substrate10, as described with reference toFIG.13. After the thinning process, the surface insulating layer120may be formed on the second surface10bof the first semiconductor substrate10. Next, the second surface10bof the first semiconductor substrate10may be patterned to form the penetration vias TSV, which are electrically connected to the first, second, and third buried power rails BPR1, BPR2, and BPR3and the buried signal line BSI. Referring toFIG.22, the power delivery network PDN, which is electrically connected to the penetration vias TSV, may be formed on the surface insulating layer120. The formation of the power delivery network PDN may include forming insulating layers and the power lines INC2, which are interposed between the insulating layers, on the surface insulating layer120. The chip pads111may be formed in the uppermost metal layer of the power delivery network PDN and on each chip region CR. After the formation of the chip pads111, a cutting process may be performed along the scribe line region. Accordingly, the semiconductor package100may be formed to have the same structure as described with reference toFIGS.8and9. According to an example embodiment of the inventive concepts, a power decoupling capacitor may be provided adjacent to a power delivery network. Accordingly, when a semiconductor package executes a high frequency operation, a power noise may be reduced. Thus, operation characteristics of the semiconductor package may be improved. According to an example embodiment of the inventive concepts, a second semiconductor chip including the power decoupling capacitor may be bonded to a first surface of a first semiconductor substrate, on which a logic structure is integrated, and then the power delivery network may be formed on a second surface of the first semiconductor substrate. That is, a dummy substrate is not needed to form the power delivery network on the second surface of the first semiconductor substrate. While some example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims. | 51,169 |
11862619 | DESCRIPTION OF EMBODIMENTS The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims. The present description addresses example embodiments of a novel microelectronic device including a patch. Example patches can include multiple embedded dies. Each of the embedded dies can have a thickness different that the other embedded dies. In certain examples, the example patch can facilitate electrical connection of multiple surface die with an interposer/substrate that can connect the surface die to a motherboard, for example. The present description also addresses example embodiments of processes for manufacturing such a patch, as well as electronic systems incorporating the novel patch. In some examples as described herein, the patch houses one or more embedded die particularly suitable for improved yield in manufacturing. In many examples, the patch includes vertical contacts extending through a dielectric of the patch. In many examples, the patch may further include contacts extending from one or more surfaces to the one or more embedded die. The can be formed to include no more than a single transverse (i.e., in the lateral/horizontal direction) routing layer (i.e., a single layer containing one or more transverse routing traces). In some examples, conductive structures in the patch may be either vertical contacts extending completely through the patch or vertical contacts extending from either an upper surface or a lower surface to an embedded die. In other examples, a single transverse routing layer may be provided proximate an upper surface of the patch (either within the structure of the patch or disposed on a surface of the patch), proximate a lower surface of the patch (for example, in a lower metallization layer of the patch), or intermediate the patch (vertically offset from both the upper and lower surfaces of the substrate). The embedded die can be of various configurations. For example, in some examples the embedded die may be a “passive” component, providing only conductive pathways (referred to herein as a “bridge” die). In many such examples, such a bridge die may be used to provide interconnections between two or more surface semiconductor die secured above a surface of the patch (termed herein, “surface die”). In other example applications, the embedded die may include active circuit components beyond simple conductive interconnects. Such a die with active circuit components can include circuitry ranging from including relatively simple circuits (such as, for example, filters, voltage limiters, and the like), to much more complex circuits including, for example transistors, fuses or anti-fuses, and/or other programmable elements (such as programmable logic devices (PLMs), field programmable logic arrays (FPGAs), etc.), and/or processing (instruction executing) capabilities. For purposes of the present description, the terminology of a “bridge” die will be used for any die having only interconnect structures providing circuit pathways; and the terminology of an “active” die will be used for any die having circuit devices beyond those of a bridge die. Additionally, the current description uses the term “embedded die” to refer to a die which is, or will be, upon completion of the patch, embedded within the patch. In some examples, transverse redistribution/routing layers can be eliminated from the patch substrate, such that the patch substrate includes no more than a single transverse routing layer. In some examples, the patch can include multiple routing layers. In many examples, the patch can be coupled directly to the interposer through appropriate contact structures. The described structure with a single transverse routing layer can simplify manufacturing of the patch, thereby improving the potential yield of the patches. Additionally, as described later herein, the patches may be manufactured through a process offering improved dimensional control. Such dimensional control can assist in providing a bump top variation (BTV) of less than 10 microns and, in certain examples, less than 5 microns. Additionally, future generations of microelectronic devices are calling for much higher levels of heterogeneous integration. This higher level of heterogeneous integration may call for multiple die to be connected using a bridge die embedded in the substrate. To accommodate higher connections, a great number of die may need to be embedded in the substrate. The present subject matter can accommodate such higher level integration while also maintaining high yields by reducing BTV rejections. The interposer may be constructed in a conventional manner as is known to persons skilled in the art. In many examples, many of the contact pads or other contact structures at the upper and lower surfaces of the interposer may be at relatively wider pitches that at least some of the vertical vias in the patch (such as, for example, some vertical vias in the substrate extending to embedded die in the substrate). Referring now to the drawings in more detail, and particularly toFIG.1A, the figure depicts a simplified schematic representation of an example configuration of a microelectronic device100demonstrating the construction discussed above. Microelectronic device100includes a patch, indicated generally at102, housing a first embedded die104and a second embedded die105. In certain examples, the first embedded die can have a different thickness than the second embedded die105. Patch102is secured to an interposer, indicated generally at106. A first surface die108and a second surface die110are coupled over a first surface112of patch102. Patch102further includes first and second groups of vertical contacts, indicated generally at116and118, respectively, extending within a dielectric body, indicated generally at120. The first group of vertical contacts116form through contacts extending through the entire dimension of dielectric body120; while vertical contacts118can extend to engage one of the embedded dies104,105. As will be discussed in more detail relative toFIGS.2A-2R, patch102may include one or more types of dielectric material, such as, for example, any one or more of polyimide, polyamide, and epoxy resin (commonly with a filler, such as a silica filler, such as, for example, the epoxy resin sold under the trade name “Ajinomoto Build-up Film” (ABF)), as well as other dielectrics known to persons skilled in the art. Additionally, the dielectric material may be formed around the embedded dies104105. In some examples, the dielectric material and the conductive material of the first and second groups of vertical contacts116,118(or only a single group of contacts in some examples) may both be formed (at least in part) in multiple layers of such materials. Due in part to the greater vertical dimension of the first group of vertical contacts116, at least a portion of this group of contacts are arranged at a wider pitch relative to one another than are contacts118. In the depicted example, an insulative layer114, such as solder resist, is placed over the first surface112of patch102, and contact pads, as indicated generally at122and124, extend through insulative layer114to engage vertical contacts116and118, respectively. In other examples, the solder resist or other insulative layer114may be omitted, and a different configuration of contact structure may be utilized to facilitate electrical and mechanical coupling of one or more surface die108,110directly to patch102. Patch102includes an optional transverse routing trace126, extending transversely to redistribute signals between two laterally offset vertical locations (in the depicted illustrative example, extending between the vertical contact118(A) extending to embedded die104and a vertical contact116(A). Though a couple transverse routing traces126are depicted; persons skilled in the art will recognize that when such a layer is present, multiple routing traces may be formed in the layer to form connections between respective laterally offset locations. In the depicted example, the optional transverse routing trace126is formed in a layer at upper surface112of patch102. In other examples, the transverse routing layer may be formed internal to patch102(i.e. at some location between a surface112and lower surface of patch102). Interposer106is coupled to patch102to electrically communicate therewith. In the present example, interposer106may be configured to serve the function of a package substrate for microelectronic device100. As result, interposer106may be configured to provide a desired interconnect routing between patch102(and potentially devices coupled thereto, such as surface die108,110) and structures external to microelectronic device100. Interposer106provides upper contacts, indicated generally at130, and lower contacts, indicated generally at132, and provides electrical interface routing between the upper and lower contacts130,132. Appropriate layers of transverse redistribution structures (for example, three layers of transverse redistribution of traces are schematically represented134,136, and138) facilitate the redistribution. The example transverse redistribution of traces of each level may be connected directly to an adjacent level or to another vertically offset location) by vertical interconnects (such as micro-vias, or analogous structures, as known to persons skilled in the art). In some examples, interposer106may include one or more layers formed of one or more insulating layers, such as glass-reinforced epoxy (such as FR-4), polytetrafluorethylene (Teflon), cotton-paper reinforced epoxy (CEM-3), phenolic-glass (G3), paper-phenolic (FR-1 or FR-2), polyester-glass (CEM-5), as well as many other example dielectric materials, and combinations of the above. In many examples, interposer106may be formed through a buildup process, either on a core or in a coreless configuration; and a micro via formation process, such as laser drilling, followed by metal fill, can be used to form interconnections between conductive layers in the buildup and die bond pads. FIG.1Billustrates generally a simplified cross section of a schematic representation of an alternative embodiment of an example microelectronic device100′ having a patch102and an interposer106. Microelectronic device100′ differs from microelectronic device100ofFIG.1Aprimarily in the following respects: the second embedded die105′ is of an example configuration including a vertical through contact107(which in some examples may be a characteristic of any or all embedded die within a substrate), such as a TSV through the die; and substrate102includes an additional lower surface vertical contact114′ extending to through contact107of embedded die105′. Addressing second embedded die105′, as with the first embedded die104, second embedded die105′ may be either a bridge die or an active die, and can be of any desired configuration. Though first and second embedded die are depicted inFIGS.1A and1B, as will be apparent to persons skilled in the art, many more embedded die may be supported within patch102. As noted above in this example, for purposes of illustration, second embedded die105′ includes an example vertical through contact107. As will be apparent to persons skilled in the art, an embedded die may commonly include multiple vertical through contacts, at least some of which may be arranged in an array at a desired pitch relative to one another. The presence of a vertical through contact107may commonly result in the need for a lower surface vertical contact114′ extending to second embedded die105′ to facilitate connection to interposer106′ as shown. It is noted that the thickness of the first embedded die104and the thickness of the second embedded die105′ are different. The thickness being a dimensional measure of an embedded die as assembled in the patch102in a direction perpendicular to either the top surface112or bottom surface128. In addition to allowing a patch to accommodate embedded dies of differing thickness, the techniques discussed herein also allow for reduced bump top variation (BTV). FIGS.2A-2Rillustrate generally simplified schematic representations of sequential representative stages in an example process for forming an example patch incorporating the techniques and structures described herein. As depicted inFIG.2A, one or more initial patterned metallization layers202can be formed on a first carrier structure, indicated generally210. In some examples, carrier structure210can include a support structure defining a planar support surface over which the patch may be formed. In some examples, carrier structure210may also include a release layer or other surface layer on the planar surface of the support structure. For purposes of the present example, a seed layer206can be deposited on the carrier structure210. The metallization layers202can be of any desired form for forming a temporary bottommost portion of vertical contacts (or other conductive structure) of the patch. The metallization layer202can be formed through desired processes known to those skilled in the art. For example, for many materials, a semi-additive process (SAP), may be used to form the patterned structures for these lower metallization layers202. The patch may include a dielectric body in which the embedded die is retained. In some examples, a first portion of the dielectric body may define an upper surface of the dielectric body, and a second portion of the dielectric body may extend to encapsulate or embed the embedded dies104,105. In some examples both the first portion of the dielectric body and the second portion may have planarized surfaces, as described below. Such planarized surfaces may be formed by grinding, chemical mechanical polishing CMP), or another known technique, also as described below. Referring now toFIG.2B, a dielectric layer214can be deposited over the structure ofFIG.2Ato a dimension sufficient to cover metallization layer202as oriented inFIG.2B. The dielectric layer214can be any of the materials as discussed above, including polyamide, polyimide, epoxy resins, etc., as discussed above. The dielectric layer214can be planarized and polished, such as through grinding, CMP, etc., to form a planarized surface216. Thus, dielectric layer214forms the above-indicated first portion of the dielectric body of the patch that will be formed. The planarization (or other planarization process) may be configured to stop at the surface of metallization layers202such that planar surface216is formed in part by exposed upper surfaces of metallization layers202. The described formation of the first metallization layers202on the carrier prior to the forming of the dielectric layer offers significant advantages in many examples, in facilitating establishing a controlled dimension of the substrate above an embedded die, and providing a planar surface216for supporting the routing traces126and upper terminals of the patch. Referring now toFIG.2C, a second metallization layer/pillar218may be formed over at least some portion of patterned metallization layer202. In many examples, second metallization layer/pillar218may be formed over the portions of metallization layers202to form portions of vertical contacts222. If a portion of first metallization layers202were configured to be contacts for embedded dies, then second metallization layer/pillar218may not be formed over some or all of such portion of first metallization layers202. Again, second metallization layer/pillar218may be formed through SAP process to leave a metallization pillar structure or vertical contact222only on selected portions of first metallization layer202, as desired. In certain examples, metallization layer may be formed via multiple layering operations. The formation of vertical contacts222through the use of multiple metallization layers facilitates building a patch control vertical dimension, and with vertical contacts222that are externally accessible, simplifying integration of the patch into a microelectronic device. In certain examples, a surface treatment layer may be formed of a desired metal, with a conductive contact material212formed thereon. Such a surface treatment layer may include one or more of nickel, tin-silver etc. In many examples, the conductive contact material212may be copper, though other conductive metals or alloys may be utilized. Referring now toFIG.2D, the embedded dies204,205can be placed on planar surface216of dielectric layer214with the contacts of the embedded dies204,205adjacent the first carrier structure210. In some examples, a bonding layer231may be utilized to retain portions of the embedded dies204,205in a fixed relation relative to planar surface216during further processing. As shown inFIG.2E, additional dielectric230is then formed over the structure ofFIG.2D, in many examples to a dimension sufficient to completely encase both embedded dies204and205as well as vertical through contacts222. Additional dielectric230may be formed as a single layer, or as multiple layers, as best suits the materials used for the layer. The forming of additional dielectric230around the embedded dies204,205may be expected to result, in many examples, in a more uniform distribution of dielectric around the embedded dies204,205, pillars and other structures such that voids are minimized or eliminated. As shown inFIG.2F, dielectric230is planarized, again such as through use of grinding, CMP or another known technique, to form a planar upper surface232which includes upper surfaces of through vertical contacts222(as orientated inFIG.3G). As a result, dielectric230forms the identified second portion of the dielectric body of the patch. Referring now toFIG.2G, the exposed surfaces of the vertical contacts222can be protected by applying a layer of protective material234to the planar upper surface232of the dielectric body (as oriented inFIG.2G). In certain examples, the protective material can be titanium (Ti) or other suitable material. Referring toFIG.2H, a second carrier structure236can be attached to the layer of protective material234currently atop the assembly. In certain examples, the second carrier structure236can include a glass carrier. In some examples, the second carrier structure236can include a layer of bonding material238such as an adhesive to attach the second carrier to the surface of the assembly. AtFIG.2I, the first carrier structure210can be removed from the assembly such as by, but not limited to, laser de-bonding, thermal or mechanical means or combinations thereof. AtFIG.2J, at least a portion, if not the entire initial metallization layers214, can be removed using processes such as etching, for example. AtFIG.2K, the bond material231used to initially fix the embedded dies204,205can be removed such as by dry etching, for example. AtFIG.2L, the assembly can be flipped and a conductive routing layer240can be fabricated to for example, connect contacts of the embedded dies204,205with vertical contacts222, or to provide connection pads for contacts of the embedded dies204,205or vertical contacts222. AtFIG.2Man insulative layer242can be attached or formed to the exposed surfaces of the first portion214of the dielectric body and to the exposed surfaces of the conductive routing layer240. The insulative layer242can further be etched or drilled to allow formation of exposed connections244,245for the surface dies or other devices. In certain examples, the exposed connections244,245, for connection to the surface dies or other devices, can be arranged with a minimum pitch commensurate with a pitch of connection pads of the surface dies108,110(FIG.1) or bridge die204,205. In some examples, the first pitch can be on the order of 40 um or less. In certain examples, the first pitch can be on the order of 30 um or less. In certain examples, the material of the insulative layer242can include a solder resist. AtFIG.2N, stiffeners246can be attached to the material of the insulative layer242to stiffen the patch assembly. AtFIG.2O, the second carrier structure236can be removed. In certain examples, a laser can be used to ablate the adhesive layer238attaching the second carrier structure236to the patch assembly. AtFIG.2P, the protective layer234can be removed to expose portions of the vertical contacts222.FIGS.2Q and2Rillustrate options for fabricating terminals of the patch for connecting to the interposer. AtFIG.2Q, an second insulative layer248can be attached to the underside of the patch assembly and can further be etch or drilled to expose retracted contact areas of the vertical contacts222. AtFIG.2R, microballs250can be attached to the exposed portions of the vertical connectors222. FIGS.3A-3Dillustrate an alternative simplified schematic representations of sequential representative stages of an example process for forming a patch incorporating the techniques and structures described herein. The representative steps ofFIGS.2A-2Pcan precede the representative stage illustrated inFIG.3A. AtFIG.3A, the exposed vertical connectors222or some other mark can provide a fiducial to locate and etch or drill an access opening352to a TSV354of one of the embedded dies204. AtFIG.3B, a copper seed layer356and additional copper can be deposited within the opening352to extend an electrical connection of the TSV354. AtFIG.3C, the excess copper can be removed to again expose the vertical contacts222including a vertical contact358of the TSV354. AtFIG.3D, external terminals can be attached to the vertical connectors222,358. Such external terminals can include, but are not limited to, microballs350. FIG.4illustrates generally a flowchart of an example method400for fabricating a patch. At401, a first patterned conductive layer can be formed on a first carrier. The first carrier can be a dimensionally stable carrier such as a glass carrier. In certain examples, a dielectric can be formed over the patterned conductive layer and both the dielectric and the patterned conductive layer can be planarized and polished. In certain examples, conductive pillars can be formed on exposed portions of the first pattern conductive layer. Vertical contacts of the patch can include the conductive pillars. At403, two or more dies can be placed on exposed portions of the first patterned conductive layer. In some examples, a holding material on the contacts of the dies can hold each die in place on the first patterned conductive layer. At405, the dies can be embedded in a dielectric. In certain examples, the dielectric can be planarized to expose a top surface of the vertical contacts. In preparation for flipping the assembly, a protective material can be applied to the dielectric and the exposed surface of the vertical contacts. At407, a second carrier structure can be coupled to the protective material, and at409, the first carrier material can be removed. The carrier removal can be achieved by laser ablating the temporary bonding material of the carrier or other suitable method. At411, the assembly can be flipped and a layer routing traces can replace the first patterned conductive layer. At413, first terminals for connecting to one or more surface dies can be fabricated to connect to the routing traces. Such fabrication can include forming a solder resist to an upper side of the assembly opposite the second carrier. In some examples, stiffeners can be attached to the upper side of the assembly to maintain structural stiffness to the patch when the second carrier is removed. At415, second terminals for connecting the patch, and the surface dies, to an interposer can be fabricated opposite the first terminals. The second carrier can be removed prior to forming the second terminals. The removal of the second carrier can be achieved by laser ablating the temporary bonding material of the carrier or other suitable method. The second terminals can be fabricated using a larger pitch than the first terminals. The techniques described herein allow for efficient fabrication of a patch that can include two or more embedded dies of varying thickness while also maintaining relatively small BTV. Packages fabricated using the above techniques can be used in PoINT-type architectures for bump pitches of 30 um and below. Because the thickness of the embedded dies can vary, use of active dies embedded within the patch can open a multitude of applications while also providing excellent yields compared to conventional patch apparatus and methods. FIG.5illustrates a system level diagram, according to one embodiment of the invention. For instance,FIG.5depicts an example of an electronic device (e.g., system) including the microelectronic device embedded die package constructed as described herein. As noted above, the embedded die package having the molded component providing a planar surface independent of the contours of an underlying substrate are able to provide higher-yielding packages for incorporation into such systems.FIG.5is included to show an example of a higher level device application for the present invention. In one embodiment, system500includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system500is a system on a chip (SOC) system. In one embodiment, processor510has one or more processing cores512and512N, where512N represents the Nth processor core inside processor510where N is a positive integer. In one embodiment, system500includes multiple processors including510and505, where processor505has logic similar or identical to the logic of processor510. In some embodiments, processing core512includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor510has a cache memory516to cache instructions and/or data for system500. Cache memory516may be organized into a hierarchal structure including one or more levels of cache memory. In some embodiments, processor510includes a memory controller514, which is operable to perform functions that enable the processor510to access and communicate with memory530that includes a volatile memory532and/or a non-volatile memory534. In some embodiments, processor510is coupled with memory530and chipset520. Processor510may also be coupled to a wireless antenna578to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface578operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra-Wide Band (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol. In some embodiments, volatile memory532includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory534includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device. Memory530stores information and instructions to be executed by processor510. In one embodiment, memory530may also store temporary variables or other intermediate information while processor510is executing instructions. In the illustrated embodiment, chipset520connects with processor510via Point-to-Point (PtP or P-P) interfaces517and522. Chipset520enables processor510to connect to other elements in system500. In some embodiments of the invention, interfaces517and522operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used. In some embodiments, chipset520is operable to communicate with processor510,505N, display device540, and other devices572,576,574,560,562,564,566,577, etc. Chipset520may also be coupled to a wireless antenna578to communicate with any device configured to transmit and/or receive wireless signals. Chipset520connects to display device540via interface526. Display540may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor510and chipset520are merged into a single SOC. In addition, chipset520connects to one or more buses550and555that interconnect various elements574,560,562,564, and566. Buses550and555may be interconnected together via a bus bridge572. In one embodiment, chipset520couples with a non-volatile memory560, a mass storage device(s)562, a keyboard/mouse564, a network interface566, a smart TV576, consumer electronics577, etc., via interface524. In one embodiment, mass storage device562includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface566is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra-Wide Band (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol. While the modules shown inFIG.5are depicted as separate blocks within the system500, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory516is depicted as a separate block within processor510, cache memory516(or selected aspects of516) can be incorporated into processor core512. Additional Notes and Examples In Example 1, a method of making a multi-die patch can include forming a first patterned conductive layer defining multiple contact pads on a first carrier structure, placing a first die on a first plurality of contact pads of the multiple contact pads, placing a second die on a second plurality of contact pads of the multiple contact pads, embedding the first die and the second die in a dielectric disposed on the patterned conductive layer, attaching a second carrier structure to the dielectric on a surface of the dielectric opposite the first carrier, removing the first carrier structure, forming routing traces, the routing traces configured to electrically couple the first and second die with one or more surface die, forming first terminals connected with a first plurality of routing traces of the routing traces, the first terminals exposed at a first side of the dielectric, and forming second terminals connected with a second plurality of routing traces of the routing traces, the second terminals exposed at a second side of the dielectric, the second side opposite the first side. In Example 2, a thickness of the first die of Example 1 optionally is different than the thickness of the second die. In Example 3, the forming second terminals of any one or more of Examples 1-2 optionally includes removing the second carrier structure. In Example 4, the removing the second carrier structure of any one or more of Examples 1-3 optionally includes laser ablating an adhesive layer of the second carrier structure. In Example 5, the removing the second carrier structure of any one or more of Examples 1-4 optionally includes coupling a stiffener to the first side before removing the second carrier structure. In Example 6, the forming a patterned conductive layer of any one or more of Examples 1-5 optionally includes depositing a copper layer on a first carrier, and etching the multiple contact pads in the first copper layer. In Example 7, the method of any one or more of Examples 1-6 optionally includes laminating a first portion of the dielectric to the patterned conductive layer, and polishing the first portion of the dielectric. In Example 8, the method of any one or more of Examples 1-7 optionally includes forming a plurality of vertical contacts extending from a third plurality of contact pads of the multiple contact pads to the second side. In Example 9, the embedding the first die and the second die in a dielectric of any one or more of Examples 1-8 optionally includes embedding the vertical contacts in the dielectric. In Example 10, the embedding the first die and the second die in a dielectric of any one or more of Examples 1-9 optionally includes planarizing the dielectric to expose the vertical contacts. In Example 11, the embedding the first die and the second die in a dielectric of any one or more of Examples 1-10 optionally includes sputtering a protective layer over exposed portions of the vertical contacts. In Example 12, the first carrier structure of any one or more of Examples 1-11 optionally includes a glass carrier. In Example 13, the second carrier structure of any one or more of Examples 1-12 optionally includes a glass carrier. In Example 14, the forming first terminals of any one or more of Examples 1-13 optionally includes replacing at least a portion of the first patterned conductive layer with a second patterned conductive layer. In Example 15, the forming first terminals optionally includes attaching a solder resist material to the second patterned conductive layer, etching vias in the solder resist layer; and filling the vias with conductive material to form the first terminals. In Example 16, the forming first terminals of any one or more of Examples 1-15 optionally includes etching at least a portion of the first patterned conductive layer after the first carrier structure is removed. In Example 17, the forming first terminals of any one or more of Examples 1-16 optionally includes etching an attachment material from contacts of at least one of the first embedded die or the second embedded die. In Example 18, at least a portion of the first terminals to the first and second embedded dies of any one or more of Examples 1-17 optionally are arranged in a first pitch relative to one another, and wherein at least a portion of the second terminals are arranged at a second pitch relative to one another, and wherein the first pitch is narrower than the second pitch. In Example 19, a patch configured to electrically interconnect a first surface die with a second surface die and to interconnect at least one of the first surface die or the second surface die with an interposer or other device can include a dielectric, first terminals exposed on a first side of the dielectric, second terminals disposed in the dielectric and exposed on a second side of the dielectric, the second terminals configured to couple with the interposer, the second side opposite the first side, a first embedded die embedded in the dielectric and coupled to a first plurality of the first terminals, and a second embedded die embedded in the dielectric and coupled to a second plurality of the first terminals, and wherein a thickness of the first embedded die is different than a thickness of the second embedded die. In Example 20, the patch of any one or more of Examples 1-19 optionally includes traverse routing traces configured to electrically couple at least one of the first terminals with a terminal of at least one of the first embedded die or the second embedded die. In Example 21, the first embedded die of any one or more of Examples 1-20 optionally is a bridge die. In Example 22, the first embedded die of any one or more of Examples 1-21 optionally is an active die. In Example 23, the second embedded die of any one or more of Examples 1-22 optionally is a bridge die. In Example 24, the second embedded die of any one or more of Examples 1-23 optionally is an active die. In Example 25, the patch of any one or more of Examples 1-24 optionally includes a plurality of vertical contacts extending through the dielectric from the second terminals. In Example 26, at least one of the first embedded die or the second embedded die of any one or more of Examples 1-25 optionally includes one or more through silicon vias. In Example 27, the dielectric of any one or more of Examples 1-26 optionally comprises at least one contact extending from the second surface of the substrate to a respective through silicon via of the at least one of the first embedded die or the second embedded die. In Example 28, at least a portion of the first terminals of any one or more of Examples 1-27 optionally are arranged in a first pitch relative to one another, wherein at least a portion of the through second terminals are arranged at a second pitch relative to one another, and wherein the first pitch is narrower than the second pitch. In Example 29, a microelectronic device can include a patch housing at least a first embedded die and a second embedded die, the patch comprising through contacts extending from a first surface of the patch to an opposing second surface of the patch, and contacts extending from a first surface to the first embedded die, the patch having a layer of transverse routing traces. The microelectronic device further including at least one surface die retained above the first surface of the patch, the surface die electrically coupled to one or more of the contacts of the patch, an interposer retained proximate a second surface of the patch, the interposer having a first set of multiple interposer contacts on a first surface, the first set of multiple interposer contacts coupled to respective patch contacts, the interposer containing multiple conductive metal layers redistributing contacts of the first set of multiple interposer contacts to respective locations on an opposing second surface of the interposer; and wherein a thickness of the first embedded die is different than a thickness of the second embedded die. In Example 30, the patch of any one or more of Examples 1-29 optionally comprises a single layer of transverse routing traces. In Example 31, the single layer of transverse routing traces of any one or more of Examples 1-30 optionally is proximate a surface of the patch. In Example 32, the single layer of transverse routing traces of any one or more of Examples 1-31 optionally is proximate the first surface of the patch. In Example 33, the single layer of transverse routing traces of any one or more of Examples 1-32 optionally is formed internal to the patch. In Example 34, the first embedded die of any one or more of Examples 1-33 optionally is a bridge die. In Example 35, the first embedded die of any one or more of Examples 1-34 optionally is an active die. In Example 36, the microelectronic device of any one or more of Examples 1-35 optionally includes multiple contact surfaces proximate the second surface. In Example 37, at least a portion of the through contacts in the patch of any one or more of Examples 1-36 optionally extend to the contact surfaces proximate the second surface. In Example 38, the multiple contact surfaces proximate the second surface of any one or more of Examples 1-37 optionally are generally flush with the second surface. In Example 39, the patch optionally comprises a dielectric body in which the embedded die is retained. In Example 40, the dielectric body of any one or more of Examples 1-39 optionally comprises a first portion extending beneath the embedded die, wherein the first portion has a first planarized surface proximate the embedded die. In Example 41, the first planarized surface of any one or more of Examples 1-40 optionally is formed by grinding or chemical mechanical planarization. In Example 42, the first planarized surface of any one or more of Examples 1-41 optionally is formed at a level of a first metallization layer of the patch. In Example 43, the dielectric body of any one or more of Examples 1-42 optionally comprises a second portion extending above the first portion and above the first and second embedded dies. In Example 44, at least a portion of the through contacts of any one or more of Examples 1-43 optionally are arranged at a first pitch relative to one another, and wherein at least a portion of the contacts to the first embedded die are arranged in a second pitch relative to one another, wherein the second pitch is narrower than the first pitch. In Example 45, the embedded die of any one or more of Examples 1-44 optionally is completely encased within the patch, and is supported in spaced relation relative to the first surface. In Example 46, the patch of any one or more of Examples 1-45 optionally comprises multiple layers of laminations. In Example 47, at least one of the first embedded die or the second embedded die of any one or more of Examples 1-46 optionally includes one or more through silicon vias. In Example 48, the patch of any one or more of Examples 1-47 optionally comprises at least one contact extending from the second surface of the patch to a respective through silicon via of the embedded die. The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein. In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “where.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. | 45,123 |
11862620 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In today's standard-logic-cell based application specific integrated circuit (ASIC) design, the logic function of the chip is modeled and simulated in higher-level hardware description languages (e.g., VHDL or VERILOG). It is then synthesized in a silicon compiler (e.g. SYNOPSIS) to generate a netlist using standard logic cells from a targeted standard-cell library. The netlist will be used in the backend physical design phase to perform the “Place and Route” of standard logic cells, generating the full circuit layout of the ASIC for manufacturing. Header switches and footer switches (collectively, “power gating cells”) on a chip are used to cut off power supplies to certain standard logic cells in a standby mode or a sleep mode to save power consumption of the chip. Header switches and footer switches are typically low-leakage metal-oxide-silicon (MOS) transistors. In some embodiments, header switches and footer switches are fin field-effect transistors (FinFETs). Header switches and footer switches are generally placed in header cells and footer cells respectively beside standard logic cells. However, under the established architecture, layouts of header cells and footer cells require large chip areas, high costs and relatively high power consumption. In accordance with some aspects of the present disclosure, a power gating cell includes: a wide active region located in a central area of the power gating cell and multiple normal active regions located in a peripheral area surrounding the central area. A normal active region is an active region with one, two, or three fin structures, while a wide active regions is an active region with more than three fin structures. Since the wide active regions has a better usage of chip area, the power gating cell can result in a smaller chip area than conventional cell layouts do, under the same active region area. From another perspective, the power gating cell can have a larger active region area compared with conventional cells with the same size. As a result, the larger active region area of the wide active region results in a smaller IR drop of the power gating cell. In summary, the power gating cell with a wide active region in the central area can achieve a smaller chip area and better power conversion efficiency. FIG.1is a block diagram illustrating an integrated circuit (IC) layout that incorporates header cells and/or footer cells (collectively, “power gating cells”) in accordance with some embodiments. Header cells, footer cells, and standard logic cells are placed on the IC layout. The header cells and footer cells have various layout structures as described with reference toFIGS.2A to20(exceptFIGS.2B and2C). In the illustrated example inFIG.1, an IC layout100includes, among other things, multiple standard logic cells104, multiple header cells102hto the left of the multiple standard logic cells104, and multiple footer cells102fto the right of the multiple standard logic cells104. The multiple header cells102hand the multiple footer cells102fare collectively called power gating cells102. Each of the multiple standard logic cells104(e.g.,104-1) may fulfil its specific function(s). Each of the multiple standard logic cells104(e.g.,104-1) is connected to at least one header cell102h (e.g.,102h-1) and at least one footer cell102f(e.g.,102f-1) which is controlled to cut off the power supply to the controlled standard logic cell (e.g.,104-1) in a standby mode or a sleep mode. In one example, each of the header cells102h includes at least one low-leakage PMOS transistor, while each of the footer cells102f includes at least one low-leakage NMOS transistor. FIG.2Ais a diagram illustrating a power gating cell102in accordance with some embodiments.FIG.2Bis a diagram illustrating a first benchmark power gating cell292to be compared with the power gating cell102ofFIG.2A.FIG.2Cis a diagram illustrating a second benchmark power gating cell294to be compared with the power gating cell102ofFIG.2A. As shown inFIG.2A, the power gating cell102may be either a header cell102hor a footer cell102f, as shown inFIG.1. The power gating cell102, located on a substrate190, has a boundary218. There are multiple active regions202located within the boundary218. Fin structures204are disposed on the active regions202. The fin structures204extend in an X direction. The fin structures204may serve as gates, sources, or drains of transistors as needed. Gate strips (i.e., poly strips)208are disposed on the fin structures204or the active regions202. The gate strips208extend in a Y direction perpendicular to the X direction. The fin structures204that are under the gate strips208may serve as gates of transistors as needed. Generally, there are two categories of active regions202: wide active regions202wand normal active regions202n. A normal active region202nis an active region202with one, two, or three fin structures204. On the other hand, a wide active regions202wis an active region202with more than three fin structures204. In the illustrated example inFIG.2A, one wide active region202wis located in the middle of the power gating cell102. More specifically, the wide active region202wis located in a central area212of the power gating cell102within a boundary214. The illustrated wide active region202whas eight fin structures204. The illustrated wide active region202whas a length of X2in the X direction. On the other hand, ten normal active regions202nare located in a peripheral area216of the power gating cell102. The peripheral area216is the area outside the boundary214but inside the boundary218. Each of the ten normal active regions202nhas two fin structures204. Due to fabrication process limitations (e.g., fin structure pitch), there is an upper limit of the number of fin structures204within a chip of a unit size. As a result, there are fin grids206of an IC layout which reflects a situation in which the maximum number of fin structures204are placed. In other words, the fin grids206are references, and not a real fin structure204is necessarily placed at the location of each fin grid206. Assuming that a fin structure204has a width of w in the Y direction and the distance between two neighboring fin structures204is d, a fin structure pitch p is equal to (w+d). Distances s1, s2, and s3 shown inFIG.2Ahas the relationship below: s1≠s2≠s3≠(w+d)*n, where n is an integer. Generally, the normal active regions202nthat are located in the peripheral area216of the power gating cell102are off-grid due to fabrication process limitations, meaning that the fin structures204are not aligned with the fin grids206. In the illustrated example inFIG.2A, the ten normal active regions202nare all off-grid. The wide active region202w, on the other hand, is on-grid, meaning that the fin structures204of the wide active region202ware aligned with the fin grids206. For example, a fin structure204-1of the wide active region202wis aligned with a fin grid206-1. Other fin structure204of the wide active region202ware also aligned with one fin grid206, respectively. The power gating cell102can achieve smaller chip area and better power conversion efficiency, which is illustrated by the comparison with the first benchmark power gating cell292ofFIG.2Band the second benchmark power gating cell294ofFIG.2C. The first benchmark power gating cell292has the same active region area as that of the power gating cell102, but with a larger chip area than that of the power gating cell102. Different from the power gating cell102, the active regions202in a central area212′ of the first benchmark power gating cell292within a boundary214′ are both normal active regions202n. More specifically, both normal active regions202nhave two fin structures204. Since the normal active regions202nhave a gap therebetween, the length X1of the normal active regions202nis longer than the length X2of the wide active region202winFIG.2A, in order to have the same active region area. As a result, the overall cell area of the first benchmark power gating cell292is larger than that of the power gating cell102. As such, the power gating cell102can result in a smaller chip area than conventional cell layouts do, under the same active region area. From another perspective, the second benchmark power gating cell294has the same overall cell area as that of the power gating cell102, but with a smaller active region area than that of the power gating cell102. Different from the power gating cell102, the active regions202in a central area212″ of the second benchmark power gating cell294within a boundary214″ are both normal active regions202n. More specifically, both normal active regions202nhave two fin structures204. Since the normal active regions202nhave a gap therebetween, the active region area of the second benchmark power gating cell294is smaller than that of the wide active region202winFIG.2A, when the length X2of the normal active regions202nis the same as the length X2of the wide active region202w. As a result, the larger active region area of the wide active region202wresults in a smaller IR drop of the power gating cell102. In summary, the power gating cell102with the wide active region202wcan achieve a smaller chip area and higher power conversion efficiency. FIG.3is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.3, the wide active region202whas four fin structures204, and each of four normal active regions202nhas one fin structure. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H0 is a standard cell height (in the Y direction) for a one-fin-active-region cell. The cell102has a height of 2H0 (in the Y direction). Distances H0, a0, b0, c0 have the relationship below: H0≠a0≠b0≠c0≠p≠w, where p is the fin structure pitch and w is the width of a fin structure204. FIG.4is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.4, the wide active region202whas four fin structures204, and each of six normal active regions202nhas one fin structure. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H0 is a standard cell height (in the Y direction) for a one-fin-active-region cell. The cell102has a height of 2H0 (in the Y direction). Distances H0, a0, b0, c0 have the relationship below: H0≠a0≠b0≠c0≠p≠w, where p is the fin structure pitch and w is the width of a fin structure204. FIG.5is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.5, the wide active region202whas six fin structures204, and each of four normal active regions202nhas one fin structure. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H0 is a standard cell height (in the Y direction) for a one-fin-active-region cell. The cell102has a height of 2H0 (in the Y direction). Distances H0, a0, b0, c0 have the relationship below: H0≠a0≠b0≠c0≠p≠w, where p is the fin structure pitch and w is the width of a fin structure204. FIG.6is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.6, the wide active region202whas six fin structures204, and each of six normal active regions202nhas one fin structure. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H0 is a standard cell height (in the Y direction) for a one-fin-active-region cell. The cell102has a height of 2H0 (in the Y direction). Distances H0, a0, b0, c0 have the relationship below: H0≠a0≠b0≠c0≠p≠w, where p is the fin structure pitch and w is the width of a fin structure204. FIG.7is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.7, the wide active region202whas eight fin structures204, and each of four normal active regions202nhas two fin structures. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H1 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 2H1 (in the Y direction). Distances H1, a1, b1, c1 have the relationship below: H1≠a1≠b1≠c1≠p, where p is the fin structure pitch. FIG.8is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.8, the wide active region202whas eight fin structures204, and each of six normal active regions202nhas two fin structures. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H1 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 2H1 (in the Y direction). Distances H1, a1, b1, c1 have the relationship below: H1≠a1≠b1≠c1≠p, where p is the fin structure pitch. FIG.9is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.9, the wide active region202whas sixteen fin structures204, and each of six normal active regions202nhas two fin structures. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H1 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 3H1 (in the Y direction). Distances H1, a1, b1, c1 have the relationship below: H1≠a1≠b1≠c1≠p, where p is the fin structure pitch. FIG.10is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.10, the wide active region202whas sixteen fin structures204, and each of eight normal active regions202nhas two fin structures. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H1 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 3H1 (in the Y direction). Distances H1, a1, b1, c1 have the relationship below: H1≠a1≠b1≠c1≠p, where p is the fin structure pitch. FIG.11is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.11, the wide active region202whas twenty-four fin structures204, and each of eight normal active regions202nhas two fin structures. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H1 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 4H1 (in the Y direction). Distances H1, a1, b1, c1 have the relationship below: H1≠a1≠b1≠c1≠p, where p is the fin structure pitch. FIG.12is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.12, the wide active region202whas twenty-four fin structures204, and each of ten normal active regions202nhas two fin structures. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H1 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 4H1 (in the Y direction). Distances H1, a1, b1, c1 have the relationship below: H1≠a1≠b1≠c1≠p, where p is the fin structure pitch. FIG.13is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.13, the wide active region202whas eight fin structures204, and each of four normal active regions202nhas three fin structures. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H2 is a standard cell height (in the Y direction) for a three-fin-active-region cell. The cell102has a height of 2H2 (in the Y direction). Distances H2, a2, b2, c2 have the relationship below: H2≠a2≠b2≠c2≠p, where p is the fin structure pitch. FIG.14is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.14, the wide active region202whas eight fin structures204, and each of six normal active regions202nhas three fin structures. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H2 is a standard cell height (in the Y direction) for a three-fin-active-region cell. The cell102has a height of 2H2 (in the Y direction). Distances H2, a2, b2, c2 have the relationship below: H2≠a2≠b2≠c2≠p, where p is the fin structure pitch. FIG.15is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.15, the wide active region202whas sixteen fin structures204, and each of six normal active regions202nhas three fin structures. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H2 is a standard cell height (in the Y direction) for a three-fin-active-region cell. The cell102has a height of 3H2 (in the Y direction). Distances H2, a2, b2, c2 have the relationship below: H2≠a2≠b2≠c2≠p, where p is the fin structure pitch. FIG.16is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.16, the wide active region202whas sixteen fin structures204, and each of eight normal active regions202nhas three fin structures. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H2 is a standard cell height (in the Y direction) for a three-fin-active-region cell. The cell102has a height of 3H2 (in the Y direction). Distances H2, a2, b2, c2 have the relationship below: H2≠a2≠b2≠c2≠p, where p is the fin structure pitch. FIG.17is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.17, the wide active region202whas twenty-four fin structures204, and each of eight normal active regions202nhas three fin structures. The normal active regions202nat the top and the bottom of the power gating cell102are relatively long in the X direction. H2 is a standard cell height (in the Y direction) for a three-fin-active-region cell. The cell102has a height of 4H2 (in the Y direction). Distances H2, a2, b2, c2 have the relationship below: H2≠a2≠b2≠c2≠p, where p is the fin structure pitch. FIG.18is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.18, the wide active region202whas twenty-four fin structures204, and each of ten normal active regions202nhas three fin structures. The normal active regions202nat the right of the power gating cell102are relatively long in the X direction. H2 is a standard cell height (in the Y direction) for a three-fin-active-region cell. The cell102has a height of 4H2 (in the Y direction). Distances H2, a2, b2, c2 have the relationship below: H2≠a2≠b2≠c2≠p, where p is the fin structure pitch. FIG.19is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.19, there are two wide active region202w(one of them has eight fin structures204and the other of them has four fin structures204), and each of four normal active regions202nhas two fin structures. In this example, H3 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 2H3 (in the Y direction). Distances H3, a3, and b3 have the relationship below: H3≠a3≠b3≠p, where p is the fin structure pitch. FIG.20is a diagram illustrating a power gating cell102in accordance with some embodiments. In the illustrated example inFIG.20, the wide active region202whas twelve fin structures204, and each of four normal active regions202nhas two fin structures. No normal active region202nis located adjacent of the long sides in the X direction of the wide active region202w. In this example, H3 is a standard cell height (in the Y direction) for a two-fin-active-region cell. The cell102has a height of 2H3 (in the Y direction). Distances H3, a3, and b3 have the relationship below: H3≠a3≠b3≠p, where p is the fin structure pitch. FIG.21is flowchart diagram illustrating a method of generating a power gating cell layout in accordance with some embodiments.FIG.22is a block diagram of a system2200for implementing the method ofFIG.21, in accordance with some embodiments. Referring toFIG.21, at step2102, placement and spacing rules of the power gating cell are generated. The placement and spacing rules are a set of rules regarding spacing and placement of that must be following when generating a layout. For example, the relationship that H3≠a3≠b3≠p, as shown inFIG.20, is one placement and spacing rule. In some embodiments, the placement and spacing rules are performed for each new layout unit (e.g., a layout for one of the normal active regions202nas shown inFIG.2A). At step2104, a central area (e.g., the central area212as shown inFIG.2A) of the power gating cell and a peripheral area (e.g., the peripheral area216as shown inFIG.2A) of the power gating cell surrounding the central area are defined, based on the placement and spacing rules. Specifically, a boundary line (e.g., the boundary line214as shown inFIG.2A) is defined, and parameters of the central area and the peripheral area are stored. The placement and spacing rules are satisfied at step2104. For example, the peripheral area on the top of the central area cannot be too narrow to accommodate a normal active region. At step2106, a first active region layout is selected from a layout unit library. The first active region layout is a layout for a wide active region (e.g., the wide active region202was shown inFIG.2A). The layout unit library includes various layout units such as both layouts for normal active regions and layouts for wide active regions. Those layout units are used to build up a layout as needed. At step2108, the first active region layout selected at step2106is placed in the central area defined at step2104, based on the placement and spacing rules. At step2110, a plurality of active region layouts are selected from the layout unit library. The second active region layouts are layouts for normal active regions (e.g., the normal active region202nas shown inFIG.2A). At step2112, the second active region layouts selected at step2110are placed in the peripheral area defined at step2104, based on the placement and spacing rules. As such, a layout for a power gating cell (e.g., the power gating cell102as shown inFIG.2A) is generated. Referring toFIG.22, the system2200is usable for implementing the method ofFIG.21. The system2200includes a processor2202and a non-transitory, computer readable storage medium2204encoded with, i.e., storing, the computer program code2206, i.e., a set of executable instructions. The processor2202is electrically coupled to the computer readable storage medium2204via a bus2214. The processor2202is configured to execute the computer program code2206encoded in the computer readable storage medium2204in order to cause system2200to be usable for performing a portion or all of the operations as depicted inFIG.21. In some embodiments, the processor2202is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In some embodiments, the computer readable storage medium2204is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer readable storage medium2204may be a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk, though other types of computer readable storage medium may also be employed. The computer readable storage medium2204stores, among other things, placement and spacing rules2222, a layout unit library2224, a central area parameters storage2226, a peripheral area parameters storage2228, and a power gating cell layout2230, which are needed for performing the method ofFIG.21or generated during performing the method ofFIG.21. It should be noted, the computer readable storage medium2204may store other information as needed. The placement and spacing rules2222are a set of rules regarding spacing and placement of that must be following when generating a layout as mentioned above. The layout unit library2224stores various layout units that are used to build up a layout as needed. The central area parameters storage2226stores parameters (e.g., dimensional sizes, number of wide active regions in the central area) regarding the central area defined at step2104as mentioned above. The peripheral area parameters storage2228stores parameters (e.g., dimensional sizes, number of normal active regions in the peripheral area) regarding the peripheral area defined at step2104as mentioned above. The power gating cell layout2230is the layout generated by performing the method ofFIG.21. The power gating cell layout2230is stored in the computer readable storage medium2204. The power gating cell layout2230may later be used to be placed beside a standard logic cell to cut off power supplies to the standard logic cell in a standby mode or a sleep mode to save power consumption of the chip. The system2200further includes an input/output (I/O) interface2208and a network interface2210. The system2200is coupled to external circuitry via the I/O interface2208. The network interface2210is coupled to the processor2202. The network interface2210allows system2200to communicate with a network2212, to which one or more other computer systems are connected. Network interface2210may be wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. The system2200may further include fabrication tools2240for implementing the processes and/or methods stored in the storage medium2204. For instance, a synthesis may be performed on a design in which the behavior and/or functions desired from the design are transformed to a functionally equivalent logic gate-level circuit description by matching the design to standard cells selected from the layout unit library2224. The synthesis results in a functionally equivalent logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, a photolithographic mask may be generated that is used to fabricate the integrated circuit by the fabrication tools2240. Further aspects of device fabrication are disclosed in conjunction withFIG.24, which is a block diagram of IC manufacturing system2400, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the manufacturing system2400. FIG.23is a flowchart diagram illustrating a method of fabricating a power gating cell in accordance with some embodiments. As shown inFIG.23, at step2302, a substrate (e.g., the substrate190as shown inFIG.2A) is provided. There is a first active region and a plurality of second active regions on the substrate. The first active region is located in a central area of the power gating cell. The plurality of second active regions are located in a peripheral area of the power gating cell surrounding the central area. The first active region has a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction. Each second active region has a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction. In some examples, the substrate may be a bulk semiconductor substrate. In some embodiments, the semiconductor substrate is a silicon on insulator (SOI) substrate. In some embodiments, the substrate may include a plurality of epitaxial layers (i.e., a multilayer substrate). The substrate may include an elementary semiconductor such as silicon and germanium. Alternatively, the substrate may include a compound semiconductor such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and/or cadmium telluride; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. The substrate may include various regions that have been suitably doped (e.g., p-type or n-type conductivity). It should be noted that other types of substrate structures and semiconductor materials are also within the scope of the disclosure. At step2304, fin structures are formed over the first active region and the plurality of second active regions. The fin structures (e.g., the fin structures204as shown inFIG.2A) comprises any suitable material. In one example, the fin structure extends in a second direction (e.g., the X direction as shown inFIG.2A). In one example, the fin structure is a silicon fin structure. In another example, the fin structure may include multiple layers such as one or more epitaxial layers grown on the bulk semiconductor substrate and/or the bulk semiconductor substrate itself. The fin structure may be formed by any suitable process including various deposition, photolithography, etching, epitaxy, and/or other suitable processes. An exemplary photolithography process may include forming a photoresist layer (“resist”) overlying the substrate, exposing the resist to a pattern by using a mask, performing a post-exposure bake process, and developing the resist to form a masking element including the resist. The masking element may then be used for etching to form the fin structure. The etching process may be reactive ion etching (RIE) processes and/or other suitable processes. In another example, the fin structure may be formed by a double-patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced fin structure density. Various DPL methodologies may be used including double exposure (e.g., using two mask sets), forming spacers adjacent features and removing the features to provide a pattern of spacers, resist freezing, and/or other suitable processes. It should be noted that other types of fin structures and fin structure materials are also within the scope of the disclosure. At step2306, source/drain regions of the fin structures are doped. In one example, the source/drain regions of the fin structures are doped by performing implanting process to implant appropriate dopants to complement the dopants in the fin structures. In another example, the source/drain regions of the fin structures may be formed by forming a recess in the fin structure and epitaxially growing material in the recess. It should be noted that other types of source/drain structures and forming processes are within the scope of the disclosure. At step2308, gate structures are formed over the fin structures in the first active region and the plurality of second active regions. Each of the gate structures (e.g., the gate strips208as shown inFIG.2A) may include a gate dielectric layer, a gate electrode layer, and/or other suitable layers such as capping layers, interface layers, work function layers, diffusion/barrier layers, etc. A gate structures and/or a fin structure may be patterned such that the gate structure wraps around a portion of the fin structure. In one example, a gate structure may contact at least three surfaces of a fin structure (e.g., the top and opposing side surfaces). In another example, a gate structure wraps around or quasi-around a fin structure such that the gate structure contacts a fourth surface of the fin structure (e.g., the bottom surface). The gate dielectric layer comprises a dielectric material, such as silicon oxide, silicon nitride, high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The gate electrode includes any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. It should be noted that other gate structures and materials are within the scope of the disclosure. At step2310, contact structures are deposited, over the source regions and the drain regions, in the first active region and the plurality of second active regions. Specifically, depositing source contact structures and drain contact structures may include, for example, depositing a barrier layer such as titanium nitride, tantalum nitride, tungsten nitride, ruthenium, the like, or a combination thereof, and then depositing a conductive material, such as a metal like aluminum, copper, tungsten, the like, or a combination thereof. The deposition may be by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), the like, or a combination thereof. Excess barrier layer materials and/or conductive materials may be removed later, such as by chemical-mechanical polishing (CMP). In some embodiments, the source contact structures and the drain contact structures are deposited in an inter-layer dielectric (ILD) such as a low-k dielectric layer or extreme low-k dielectric layer. Specifically, the source contact structures and the drain contact structures are formed by forming the interlayer dielectric (ILD), patterning the ILD by using a mask to cover some portions of the ILD while leaving other portions of the ILD exposed, etching the ILD to remove the exposed portions of the ILD to form a recess, and depositing conductive materials in the recess. It should be noted that other types of forming processes and materials are within the scope of the disclosure. As such, individual FinFETs are fabricated in the first active region and the plurality of second active regions. At step2312, electrical interconnect structures are formed among the first active region and the plurality of second active regions. The electrical interconnect structures are configured to connect various features or structures of the individual FinFETs located in the first active region and the plurality of second active regions. In some embodiments, the electrical interconnect structures include a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. Those electrical interconnect structures are made of various conductive materials including, but not limited to, copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. As such, the individual FinFETs are connected to function as header switches or footer switches. FIG.24is a block diagram of IC manufacturing system in accordance with some embodiments. InFIG.24, the IC manufacturing system2400includes entities, such as a design house2420, a mask house2430, and an IC manufacturer/fabricator (“fab”)2450, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device2460, such as the power gating cell102disclosed above. The entities in the system2400are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of the design house2420, mask house2430, and IC fab2450is owned by a single larger company. In some embodiments, two or more of design house2420, mask house2430, and IC fab2450coexist in a common facility and use common resources. The design house (or design team)2420generates an IC design layout diagram2422. The IC design layout diagram2422includes various geometrical patterns, or IC layout diagrams designed for an IC device2460, e.g., an IC device including one or more of the disclosed power gating cells102, discussed above. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device2460to be fabricated. The various layers combine to form various IC features. For example, a portion of the IC design layout diagram2422includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house2420implements a design procedure to form an IC design layout diagram2422. The design procedure includes one or more of logic design, physical design or place and route. The IC design layout diagram2422is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram2422can be expressed in a GDSII file format or DFII file format. The mask house2430includes a data preparation2432and a mask fabrication2444. The mask house2430uses the IC design layout diagram2422to manufacture one or more masks2445to be used for fabricating the various layers of the IC device2460according to the IC design layout diagram2422. The mask house2430performs mask data preparation2432, where the IC design layout diagram2422is translated into a representative data file (“RDF”). The mask data preparation2432provides the RDF to the mask fabrication2444. The mask fabrication2444includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)2445or a semiconductor wafer2453. The design layout diagram2422is manipulated by the mask data preparation2432to comply with particular characteristics of the mask writer and/or requirements of the IC fab2450. InFIG.24, the mask data preparation2432and the mask fabrication2444are illustrated as separate elements. In some embodiments, the mask data preparation2432and the mask fabrication2444can be collectively referred to as a mask data preparation. In some embodiments, the mask data preparation2432includes an optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. The OPC adjusts the IC design layout diagram2422. In some embodiments, the mask data preparation2432includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, the mask data preparation2432includes a mask rule checker (MRC) that checks the IC design layout diagram2422that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram2422to compensate for limitations during the mask fabrication2444, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, the mask data preparation2432includes lithography process checking (LPC) that simulates processing that will be implemented by the IC fab2450to fabricate the IC device2460. LPC simulates this processing based on the IC design layout diagram2422to create a simulated manufactured device, such as the IC device2460. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine the IC design layout diagram2422. It should be understood that the above description of mask data preparation2432has been simplified for the purposes of clarity. In some embodiments, data preparation2432includes additional features such as a logic operation (LOP) to modify the IC design layout diagram2422according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram2422during data preparation2432may be executed in a variety of different orders. After the mask data preparation2432and during the mask fabrication2444, a mask2445or a group of masks2445are fabricated based on the modified IC design layout diagram2422. In some embodiments, the mask fabrication2444includes performing one or more lithographic exposures based on the IC design layout diagram2422. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)2445based on the modified IC design layout diagram2422. The mask2445can be formed in various technologies. In some embodiments, the mask2445is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of the mask2445includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask2445is formed using a phase shift technology. In a phase shift mask (PSM) version of the mask2445, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by the mask fabrication2444is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer2453, in an etching process to form various etching regions in the semiconductor wafer2453, and/or in other suitable processes. The IC fab2450includes wafer fabrication2452. The IC fab2450is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, the IC Fab2450is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (FEOL fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (BEOL fabrication), and a third manufacturing facility may provide other services for the foundry business. The IC fab2450uses mask(s)2445fabricated by the mask house2430to fabricate the IC device2460. Thus, the IC fab2450at least indirectly uses the IC design layout diagram2422to fabricate the IC device2460. In some embodiments, the semiconductor wafer2453is fabricated by the IC fab2450using mask(s)2445to form the IC device2460. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout diagram2422. The Semiconductor wafer2453includes a silicon substrate or other proper substrate having material layers formed thereon. The semiconductor wafer2453further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). In accordance with some disclosed embodiments, a power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction. In accordance with some disclosed embodiments, an integrated circuit is provided. The integrated circuit includes: a standard logic cell configured to fulfil a function; and a power gating cell coupled to the standard logic cell configured to disconnect a power supply to the standard logic cell in response to a control signal, the power gating cell having a central area and a peripheral area surrounding the central area. The power gating cell further includes: a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction. In accordance with further disclosed embodiments, a method of fabricating a power gating cell on an integrated circuit is provided. The method includes: providing a substrate, wherein there is a first active region and a plurality of second active regions on the substrate, the first active region located in a central area of the power gating cell and having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, the plurality of second active regions located in a peripheral area of the power gating cell surrounding the central area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction; forming fin structures over the first active region and the plurality of second active regions; doping source regions and drain regions of the fin structures; and forming gate structures over the fin structures in the first active region and the plurality of second active regions. This disclosure outlines various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 50,529 |
11862621 | DETAILED DESCRIPTION The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A delay circuit is included in an IC device to delay a signal for satisfying one or more timing and/or operational requirements. In some embodiments in accordance with a first aspect, an output connector is electrically coupled to an output of a delay circuit. As a result, in at least one embodiment, resistance and/or capacitance associated with the output connector impart(s) a further delay to the delayed signal. In some embodiments in accordance with a second aspect, a delay circuit comprises N-type and P-type transistors correspondingly formed over N-type and P-type active regions. One of the N-type and P-type active regions is a continuous active region, whereas the other of the N-type and P-type active regions is a discontinuous active region. As a result, in at least one embodiment, a saturation current of N-type or P-type transistors over the discontinuous active region is degraded, which, in turn, increases the delay and/or delay circuit/cell efficiency. In some embodiments in accordance with a third aspect, at least one via structure is arranged over and in electrical contact with a gate electrode of a transistor in a delay circuit, but is not electrically coupled to any another circuit element. The at least one via structure is further over an active region associated with the transistor. As a result, in at least one embodiment, a threshold voltage of the transistor is increased which, in turn, increases the delay and/or delay circuit/cell efficiency. Some embodiments include features corresponding to more than one, or all, of the first through third aspects. As a result, in at least one embodiment, advantages corresponding to more than one, or all, of the first through third aspects are achievable. FIG.1is a block diagram of an IC device100, in accordance with some embodiments. InFIG.1, the IC device100comprises, among other things, a macro102. In some embodiments, the macro102comprises one or more of a memory, a power grid, a cell or cells, an inverter, a latch, a buffer and/or any other type of circuit arrangement that may be represented digitally in a cell library. In some embodiments, the macro102is understood in the context of an analogy to the architectural hierarchy of modular programming in which subroutines/procedures are called by a main program (or by other subroutines) to carry out a given computational function. In this context, the IC device100uses the macro102to perform one or more given functions. Accordingly, in this context and in terms of architectural hierarchy, the IC device100is analogous to the main program and the macro102is analogous to subroutines/procedures. In some embodiments, the macro102is a soft macro. In some embodiments, the macro102is a hard macro. In some embodiments, the macro102is a soft macro which is described digitally in register-transfer level (RTL) code. In some embodiments, synthesis, placement and routing have yet to have been performed on the macro102such that the soft macro can be synthesized, placed and routed for a variety of process nodes. In some embodiments, the macro102is a hard macro which is described digitally in a binary file format (e.g., Graphic Database System II (GDSII) stream format), where the binary file format represents planar geometric shapes, text labels, other information and the like of one or more layout-diagrams of the macro102in hierarchical form. In some embodiments, synthesis, placement and routing have been performed on the macro102such that the hard macro is specific to a particular process node. The macro102includes a region104which comprises at least one delay circuit as described herein. In some embodiments, the region104comprises a semiconductor substrate having circuitry formed thereon, in a front-end-of-line (FEOL) fabrication. Furthermore, above and/or below the semiconductor substrate, the region104comprises various metal layers that are stacked over and/or under insulating layers in a Back End of Line (BEOL) fabrication. The BEOL provides routing for circuitry of the IC device100, including the macro102and the region104. FIG.2Ais a schematic block diagram of a circuit region200A of an IC device, in accordance with some embodiments. In at least one embodiment, the circuit region200A corresponds to a portion of the region104inFIG.1. In the example configuration inFIG.2A, the circuit region200A comprises flip-flops FF1, FF2, and a signal path201between the flip-flops FF1, FF2. The signal path201comprises processing circuitry202, and delay circuitry203. The flip-flop FF1comprises an input D1electrically coupled to receive input data D, an output Q1electrically coupled to an input of the processing circuitry202, and a clock input CK1electrically coupled to receive a clock signal clk. The flip-flop FF2comprises an input D2electrically coupled to an output of the delay circuitry203, an output Q2, and a clock input CK2electrically coupled to receive the clock signal clk. An output of the processing circuitry202is electrically coupled to an input of the delay circuitry203. Examples of one or more circuits, logics, or cells included in the processing circuitry202include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock, memory, or the like. Examples of delay circuitry203are described herein. Other configurations for processing circuitry and/or delay circuitry are within the scopes of various embodiments. The flip-flop FF1is configured to latch the received input data D and output the latched input data D as a signal204to the processing circuitry202in synchronization with active clock edges (e.g., rising edges or falling edges) of clock pulses in the clock signal clk. The processing circuitry202is configured perform data processing, e.g., one or more logic operations, on the latched input data D in the signal204received from the flip-flop FF1, and output processed data in a signal205to the delay circuitry203. The delay circuitry203is configured to add a time delay to the signal205, and output a delayed signal206to the flip-flop FF2. The flip-flop FF2is configured to latch the processed data in the received delayed signal206and output the latched processed data as output data Q to other circuitry in the IC device, or to external circuitry outside the IC device, in synchronization with active clock edges in the clock signal clk. In some situations, for a stable operation of the flip-flop FF2, there is a requirement that the signal at the input D2is stable, e.g., not changing between a high level and a low level, during a predetermined time period around an active clock edge of the clock signal clk. Such a predetermined time period includes a setup time and a hold time. The setup time is a predetermined minimum amount of time required for the signal at the input D2to be stable before an active clock edge. The hold time is a predetermined minimum amount of time required for the signal at the input D2to be stable after an active clock edge. In an IC design stage, a timing analysis is performed for the processing circuitry202electrically coupled between the flip-flops FF1, FF2. If the timing analysis indicates a hold time violation at the flip-flop FF2, an approach to correct such a timing error, in at least one embodiment, is to insert delay circuitry203between the processing circuitry202and the flip-flop FF2. In some embodiments, the delay circuitry203comprises one or more delay cells, each including one or more delay circuits. The time delay added by the delay circuitry203to the signal205is selectable or adjustable by a configuration and/or a number of delay cells or delay circuits in the delay circuitry203. Other applications for delay cells or delay circuits are within the scopes of various embodiments. FIG.2Bis a schematic circuit diagram of delay circuitry200B in a circuit region of an IC device, in accordance with some embodiments. In at least one embodiment, the delay circuitry200B corresponds to the delay circuitry203inFIG.2A. In the example configuration inFIG.2B, the delay circuitry200B comprises delay circuits210,220electrically coupled in series, so that a time delay of the delay circuit210is added to a time delay of the delay circuit220, resulting in a greater time delay required for correcting a timing error in one or more situations. The number of delay circuits in the delay circuitry200B is not limited to two. For example, in at least one embodiment, one delay circuit210or220in the delay circuitry200B is sufficient to provide a required time delay. In one or more embodiments, the delay circuitry200B comprises more than two delay circuits to obtain a greater required time delay. The delay circuits in the delay circuitry200B are electrically coupled in series, with an output of a preceding delay circuit being electrically coupled to an input of a succeeding delay circuit, as described with respect to the delay circuits210,220. The delay circuit210comprises an input211, an output212, and a plurality of transistors P1, P2, N1, N2electrically coupled together to delay an input signal Ai received at the input211to generate a delayed signal Ai+1 at the output212. Examples of transistors in the delay circuit210include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, nanosheet FETs, nanowire FETs, or the like. In the example configuration inFIG.2B, the delay circuit210comprises PMOS transistors P1, P2, and NMOS transistors N1, N2. In some embodiments, a PMOS transistor is referred to as a transistor of a first or second type, and an NMOS transistor is referred to as a transistor of the second or first type. Gates of all transistors P1, P2, N1, N2are electrically coupled to the input211to receive the signal Ai. For simplicity, internal connections between the gates of transistors P2, N2and the input211are omitted. The transistors P1and N1are electrically coupled in series between a first node213of a first power supply voltage, e.g., VDD, and a second node214of a second power supply voltage, e.g., VSS. For simplicity, the first node213and corresponding nodes or power rails having the first power supply voltage are referred to as “VDD,” and the second node214and corresponding nodes or power rails having the second power supply voltage are referred to as “VSS.” A source/drain of the transistor P1and a source/drain of the transistor N1are electrically coupled to a third node215, the other source/drain of the transistor P1is electrically coupled to VDD, and the other source/drain of the transistor N1is electrically coupled to VSS. The transistors P2and N2are electrically coupled in parallel between the third node215and the output212. A source/drain of the transistor P2and a source/drain of the transistor N2are electrically coupled to the third node215, and the other source/drain of the transistor P2and the other source/drain of the transistor N2are electrically coupled to the output212. The described circuit configuration of the delay circuit210is an example. Other delay circuit configurations are within the scopes of various embodiments. The delay circuit220comprises an input221, an output222, and a plurality of transistors P1, P2, N1, N2electrically coupled together as in the delay circuit210. The input221of the delay circuit220is electrically coupled to the output212of the delay circuit210through an output connector216to receive the signal Ai+1 output by the delay circuit210. The output222is electrically coupled to an output connector226. The plurality of transistors P1, P2, N1, N2are electrically coupled together to delay the signal Ai+1 received at the input221to generate a further delayed signal Ai+2 at the output222. In the example configuration inFIG.2B, the delay circuit220has the same circuit configuration as the delay circuit210. In some embodiments, the delay circuit220has a circuit configuration different from the circuit configuration of the delay circuit210. The delay circuit210is an example of a preceding delay circuit and the delay circuit220is an example of a succeeding delay circuit among a plurality of delay circuits in the delay circuitry200B. In at least one embodiment, the delay circuitry200B further comprises one or more delay circuits preceding the delay circuit210to generate the signal Ai input into the delay circuit210, and/or one or more delay circuits succeeding the delay circuit220to receive and further delay the signal Ai+2 output from the delay circuit220. FIG.2Cis a schematic equivalent circuit diagram200C of the delay circuitry200B, in accordance with some embodiments. In the equivalent circuit diagram200C, each of the delay circuits210,220is schematically represented by a corresponding inverter symbol, and each of the output connectors216,226is represented by a resistor-capacitor (RC) circuit. In some embodiments, the output connector216comprises one or more conductive patterns in one or more metal layers, and one or more via structures electrically coupling the conductive patterns with each other and/or with the output of the corresponding delay circuit210. The output connector216is represented in the equivalent circuit diagram200C by a resistor Ri corresponding to the resistance of the one or more conductive patterns in the output connector216(the resistance of the one or more via structures in the output connector216is negligible in at least one embodiment). The output connector216is further represented in the equivalent circuit diagram200C by a capacitor Ci corresponding to the parasitic capacitance formed by the one or more conductive patterns in the output connector216with other, adjacent conductive patterns in the IC device. As illustrated inFIG.2C, the resistor Ri is electrically coupled between the output of the delay circuit210and the input of the delay circuit220, and the capacitor Ci is electrically coupled between the input of the delay circuit220and the ground. Similarly, the output connector226is represented in the equivalent circuit diagram200C by corresponding resister Ri+1 and capacitor Ci+1. As can be seen inFIG.2C, the output connector216represented by the corresponding RC circuit of the resistor Ri and capacitor Ci causes an additional time delay equal to Ri×Ci between the output of the delay circuit210and the input of the delay circuit220, due to charging/discharging cycles in the RC circuit when the signal on the output connector216changes between a high level and a low level. In accordance with some embodiments, by configuring the output connector216to increase or decrease the corresponding resistance of resistor Ri and/or capacitance of capacitor Ci, it is possible to vary the additional time delay associated with the output connector216, and to vary the time delay imparted by the delay circuit210and the output connector216to the signal to be input into the delay circuit220. An additional time delay associated with the output connector226at the output of the delay circuit220is configurable in a similar manner, in one or more embodiments. FIG.3Ais a schematic view of a layout diagram of a delay cell300A in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell300A corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.2BandFIG.3Aare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell300A is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. As illustrated inFIG.3A, the delay cell300A comprises a plurality of active regions301,302. Active regions are sometimes referred to as oxide-definition (OD) regions or source/drain regions, and are schematically illustrated in the drawings with the label “OD.” In at least one embodiment, the active regions301,302are over a front side of a substrate as described herein. The active regions301,302are elongated along a first axis, e.g., the X-axis. The active regions301,302include P-type dopants and/or N-type dopants to form one or more circuit elements or devices. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, nanosheet FETs, nanowire FETs, or the like. An active region configured to form one or more PMOS devices is sometimes referred to as “PMOS active region,” and an active region configured to form one or more NMOS devices is sometimes referred to as “NMOS active region.” In the example configuration described with respect toFIG.3A, the active region301comprises a PMOS active region, and the active region302comprise an NMOS active region. Other configurations are within the scopes of various embodiments. In some embodiments, a PMOS active region is referred to as an active region of a first or second semiconductor type, and an NMOS active region is referred to as an active region of the second or first semiconductor type. The delay cell300A further comprises a plurality of gate regions311,312,318,319over the active regions301,302. The gate regions311,312,318,319are elongated along a second axis, e.g., the Y-axis, which is transverse to the X-axis. The gate regions311,312,318,319are arranged along the X axis at a regular pitch designated at CPP (contacted poly pitch) inFIG.3A. CPP is a center-to-center distance along the X axis between two directly adjacent gate regions. Two gate regions are considered directly adjacent where there are no other gate regions therebetween. The gate regions311,312,318,319comprise a conductive material, such as, polysilicon, which is sometimes referred to as “poly.” The gate regions311,312,318,319are schematically illustrated in the drawings with the label “PO.” Other conductive materials for the gate regions, such as metals, are within the scope of various embodiments. In the example configuration inFIG.3A, the gate regions311,312are functional gate regions which, together with the active regions301,302, configure a plurality of transistors as described herein. In some embodiments, the gate regions318,319are non-functional, or dummy, gate regions. Dummy gate regions are not configured to form transistors together with underlying active regions, and/or one or more transistors formed by dummy gate regions together with the underlying active regions are not electrically coupled to other circuitry in the delay cell300A and/or the IC device including the delay cell300A. In at least one embodiment, non-functional, or dummy, gate regions include dielectric material in a manufactured IC device. The delay cell300A further comprises a plurality of transistors configured by the gate regions311,312and the active regions301,302. For example, the transistors P1, P2are configured by the PMOS active region301together with the corresponding gate regions311,312. The transistors N1, N2are configured by the NMOS active region302together with the corresponding gate regions311,312. The gate region311corresponds to the gates of the transistors P1, N1, and the gate region312corresponds to the gates of the transistors P2, N2. Source/drains of the transistors P1, P2correspond to portions of the active region301on opposite sides of the corresponding gate regions311,312. Source/drains of the transistors N1, N2correspond to portions of the active region302on opposite sides of the corresponding gate regions311,312. The transistors P1, P2, N1, N2are electrically coupled into a delay circuit schematically indicated as310inFIG.3Aand corresponding to the delay circuit210. The delay cell300A further comprises contact structures over and in electrical contact with the corresponding source/drains in the active regions301,302. Contact structures are sometimes referred to as metal-to-device structures, and are schematically illustrated in the drawings with the label “MD.” An MD contact structure includes a conductive material formed over a corresponding source/drain in the corresponding active region to define an electrical connection from one or more devices formed in the active region to other internal circuitry of the IC or to outside circuitry. In the example configuration inFIG.3A, contact structures321,322,323are over the active region301, in electrical contact with the corresponding source/drains of the transistors P1, P2, and arranged alternatingly with the gate regions318,311,312along the X-axis. A pitch, i.e., a center-to-center distance along the X axis, between directly adjacent contact structures is the same as the pitch CPP between directly adjacent gate regions. Contact structures324,322,323are over the active region302, in electrical contact with the corresponding source/drains of the transistors N1, N2, and arranged alternatingly with the gate regions318,311,312along the X-axis. The contact structures321,324are aligned along the Y-axis and are each in electrical contact with a corresponding active region, i.e., either of the active regions301,302. The contact structures322,323extend continuously along the Y-axis to be in electrical contact with multiple active regions, i.e., to be in electrical contact with both the active regions301,302. The contact structures322,323that are in electrical contact with multiple active regions are referred to herein as extended contact structures. An example conductive material of the contact structures includes metal. Other configurations are within the scopes of various embodiments. In the example configuration inFIG.3A, the contact structure321corresponds to the source/drain of the transistor P1that is electrically coupled to VDD, the contact structure324corresponds to the source/drain of the transistor N1that is electrically coupled to VSS, the contact structures322corresponds to the node215, and the contact structure323corresponds to the source/drains of the transistors P2, N2to be electrically coupled to an output of the delay circuit310. The gates of the transistors P1, P2, N1, N2are to be electrically coupled to an input of the delay circuit310. The delay cell300A further comprises via structures over and in electrical contact with the corresponding gate regions or contact structures. A via structure over and in electrical contact with a contact structure is sometimes referred to as via-to-device (VD). A via structure over and in electrical contact with a gate region is sometimes referred to as via-to-gate (VG). VD and VG via structures are schematically illustrated in the drawings with the label “VD/VG.” In the example configuration inFIG.3A, a VD via structure325is over and in electrical contact with the contact structure323. VG via structures326,327are over and in electrical contact with the corresponding gate regions311,312. An example material of the VD and VG via structures includes metal. Other configurations are within the scopes of various embodiments. The delay cell300A further comprises VD rails328,329which, similarly to VD via structures, are configured to be over and in electrical contact with an MD contact structure. The VD rail328is over and in electrical contact with the contact structure321to electrically couple the contact structure321to VDD as described herein. The VD rail329is over and in electrical contact with the contact structure324to electrically couple the contact structure324to VSS as described herein. In at least one embodiment, the VD rails328,329fly over, but are not in electrical contact with, the gate regions311,312, e.g., as described with respect toFIG.4B. The VD rails are schematically illustrated in the drawings with the label “VDR.” A difference between VD rails and VD via structures resides in different shapes of VD rails and VD via structures in a X-Y plane. In some embodiments, a VD via structure has a shape of a square or close to a square, with a length to width ratio between 1:1 and 2:1, whereas a VD rail has an elongated shape with a length to width ratio greater than 2:1. In the example configuration inFIG.3A, the VD rails328,329extend along the X-axis over a whole length of the delay cell300A. In at least one embodiment, one or more VD rails328,329is/are omitted and/or replaced with VD via structures for electrically coupling the corresponding contact structures321,324correspondingly to VDD, VSS. In some embodiments, the delay cell300A comprises one or more backside via structures (not shown) as alternatives to VD rails328,329, e.g., for electrically coupling the source/drains corresponding to the contact structures321,324correspondingly to VDD, VSS. A backside via structure is a through via structure configured to extend through the substrate of an IC device comprising the delay cell300A from a back side of the substrate. Such a backside via structure is configured to be in electrical contact with the back side of a corresponding source/drain in a corresponding active region. Backside via structures are configured to electrically couple the corresponding source/drains to corresponding conductive patterns in a backside-metal-zero (BM0) layer, as described herein. An example material of backside via structures includes metal. Other configurations are within the scopes of various embodiments. The delay cell300A further comprises a plurality of metal layers and via layers sequentially and alternatingly arranged over the VD, VG via structures and VD rails. The lowermost metal layer immediately over and in electrical contact with the VD, VG via structures and VD rails is an M0(metal-zero) layer, a next metal layer immediately over the M0layer is an M1layer, a next metal layer immediately over the M1layer is an M2layer, or the like. A via layer VIAn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (VIA0or V0) layer is the lowermost via layer which is arranged between and electrically couple the M0layer and the M1layer. Other via layers are VIA1(or V1), VIA2(or V2), or the like. The M0layer is the lowermost metal layer over, or the closest metal layer to, the active regions301,302, on the front side of the substrate, as described herein. In the delay cell300A, the M0layer comprises M0conductive patterns331,332,333,334,335. The M0conductive pattern331is over and in electrical contact with the VG via structures326,327. The M0conductive pattern331is electrically coupled by the VG via structures326,327to the gates of the transistors P1, P2, N1, N2, and configures the input of the delay circuit310. The M0conductive pattern332is over and in electrical contact with the VD via structure325. The M0conductive pattern332is electrically coupled by the VD via structure325and MD contact structure323to the corresponding source/drains of the transistors P2, N2, and configures the output of the delay circuit310. The M0conductive pattern333is over and in electrical contact with the VD rail328. The M0conductive pattern333is electrically coupled by the VD rail328to the corresponding source/drain of the transistor P1, and is configured as a VDD power rail. The M0conductive pattern334is over and in electrical contact with the VD rail329. The M0conductive pattern334is electrically coupled by the VD rail329to the corresponding source/drain of the transistor N1, and is configured as a VSS power rail. The M0conductive pattern335is part of an output connector associated with the delay circuit310, as described herein. In at least one embodiment, the M0conductive pattern335is the input of a succeeding delay circuit (e.g., a delay circuit corresponding to the delay circuit220). For example, VG via structures similar to the VG via structures326,327are under and in electrical contact with the M0conductive pattern335to electrically couple the M0conductive pattern335to gates of transistors in the succeeding delay circuit. The delay cell300A further comprises, in the VIA0layer over the M0layer, VIA0via structures336,337over and in electrical contact with the corresponding M0conductive patterns332,335. In the example configuration inFIG.3A, the VIA0via structure336overlaps the VD via structure325. Other configurations are within the scopes of various embodiments. The delay cell300A further comprises, in the M1layer over the VIA0layer, an M1conductive pattern338over and in electrical contact with the VIA0via structures336,337. In the example configuration inFIG.3A, the M1conductive pattern338overlaps the MD contact structure323. Other configurations are within the scopes of various embodiments. The delay cell300A further comprises a boundary (or cell boundary)340which comprises edges341,342,343,344. The edges341,342are elongated along the X axis, and the edges343,344are elongated along the Y axis. The edges341,342,343,344are connected together to form the closed boundary340. In a place-and-route operation (also referred to as “automated placement and routing (APR)”) described herein, cells are placed in an IC layout diagram in abutment with each other at their respective boundaries. The boundary340is sometimes referred to as “place-and-route boundary” and is schematically illustrated in the drawings with the label “prBoundary.” The rectangular shape of the boundary340is an example. Other boundary shapes for various cells are within the scope of various embodiments. In some embodiments, the edges341,342coincide with centerlines of the corresponding VD rails328,329, and/or centerlines of the corresponding M0conductive patterns333,334. In some embodiments, the edges343,344coincide with centerlines of dummy or non-functional gate regions318,319. Between the edges341,342and along the Y axis, the delay cell300A contains one PMOS active region, i.e.,301, and one NMOS active region, i.e.,302, and is considered to have a height corresponding to one cell height. As described with respect toFIGS.5A-5F, another cell or circuit region containing along the Y axis two PMOS active regions and two NMOS active regions is considered to have a height corresponding to two cell heights, or double cell height. In at least one embodiment, the delay cell300A comprises more than one delay circuits. For example, one or more further delay circuits corresponding to the delay circuit220are electrically coupled in series to the output of the delay circuit310through the M0conductive pattern335. Such one or more further delay circuits are schematically illustrated inFIG.3Aby an ellipsis symbol339. In at least one embodiment, the delay circuit310is the only delay circuit in the delay cell300A, and the M0conductive pattern335is configured to electrically couple the delay cell300A with another circuitry or cell. In the delay cell300A, the M0conductive pattern332, which is the output of the delay circuit310, is electrically coupled sequentially through the VIA0via structure336, the M1conductive pattern338, the VIA0via structure337to the M0conductive pattern335. In some embodiments, other than the VD via structure325and the VIA0via structure336, the M0conductive pattern332is not in direct electrical contact with another circuit element. The M0conductive pattern335, VIA0via structures336,337and the M1conductive pattern338together configure an output connector corresponding to the output connector216and electrically coupled to the output (i.e., the M0conductive pattern332) of the delay circuit310. An example configuration of an output connector in an IC device is described herein with respect toFIG.4A. In the delay cell300A, the M0layer is an example of a first metal layer having therein the output (i.e., the M0conductive pattern332) of the delay circuit310and a first conductive pattern (e.g., the M0conductive pattern335). The M1layer is an example of a second metal layer different from the first metal layer, and having therein a second conductive pattern (e.g., the M1conductive pattern338) which electrically couples the output (e.g.,332) to the first conductive pattern (e.g.,335). Although in the example configuration inFIG.3A, the first metal layer (e.g., M0layer) is under the second metal layer (e.g., M1layer), other configurations in which the first metal layer is over the second metal layer are within the scopes of various embodiments. In at least one embodiment, the first metal layer having the output of a delay circuit is any metal layer in an IC device, and the second metal layer is any other metal layer in the IC device. In some embodiments, because a further conductive pattern (e.g., M1conductive pattern338) in a metal layer different from the metal layer including an output (e.g., M0conductive pattern332) of a delay circuit (e.g., delay circuit310) is included as part of an output connector electrically coupled to the output of the delay circuit, it is possible to increase the resistance and/or capacitance of the output connector due to the further conductive pattern. As a result, an additional further time delay is obtainable by the output connector, as described with respect toFIG.2C. Such an additional time delay is added to the time delay provided by the delay circuit310, and makes it possible, in at least one embodiment, to reduce the number of delay circuits in a delay cell or the number of delay cells in delay circuitry (e.g., delay circuitry203) needed to provide a required time delay to satisfy a timing requirement. Consequently, in at least one embodiment, a chip (or wafer) area needed for the delay circuitry is reduced which, in turn, increases delay cell efficiency (e.g., a ratio of time delay to delay cell area). Further, in some embodiments, because the M1conductive pattern338overlaps the MD contact structure323as described herein, the addition of the M1conductive pattern338does not increase a dimension of the delay cell300A, especially along the X-axis. As a result, a greater time delay is obtainable without increasing the delay cell area, in at least one embodiment. One or more of the described advantages in accordance with some embodiments are improvements over other approaches which do not include a further conductive pattern like the M1conductive pattern338and which directly use the output or M0conductive pattern332for electrical connection to the succeeding delay circuit. FIG.3Bis a schematic view of a layout diagram of a delay cell300B in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell300B corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.3AandFIG.3Bare designated by the same reference numerals. For simplicity, the cell boundary of the delay cell300B, which is similar to the boundary340of the delay cell300A is omitted inFIG.3B. In at least one embodiment, the layout diagram of the delay cell300B is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell300B differs from the delay cell300A in the configuration of the output connector electrically coupled to the output of the delay circuit310. Specifically, the output connector in the delay cell300B comprises a shorter M1conductive pattern348than the corresponding M1conductive pattern338in the delay cell300A. The output connector in the delay cell300B further comprises a VIA0via structure347and an M0conductive pattern345corresponding to the VIA0via structure337and M0conductive pattern335in the delay cell300A. While the VIA0via structure337and M0conductive pattern335in the delay cell300A are arranged over the active region301, the corresponding VIA0via structure347and M0conductive pattern345in the delay cell300B are arranged over a spacing or intermediate region between the active regions301,302, due to the shorter M1conductive pattern348. In the example configuration inFIG.3B, the M0conductive pattern331which is the input of the delay circuit310is aligned along the X-axis with the M0conductive pattern345which is to be electrically coupled to an input of a succeeding delay circuit. Other configurations are within the scopes of various embodiments. In some embodiments, the shorter M1conductive pattern348provides smaller resistance and/or capacitance to the output connector in the delay cell300B than in the delay cell300A. As a result, the output connector in the delay cell300B provides a smaller additional time delay than the output connector in the delay cell300A. Nevertheless, in at least one embodiment, one or more advantages described herein with respect to the delay cell300A are achievable in the delay cell300B. In at least one embodiment, it is possible to adjust the additional time delay associated with an output connector by switching from one output connector configuration (e.g., in the delay cell300A or300B) to another output connector configuration (e.g., in the delay cell300B or300A). This time delay adjustability or customizability is a further advantage, in one or more embodiments. FIG.3Cis a schematic view of a layout diagram of a delay cell300C in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell300C corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.3AandFIG.3Care designated by the same reference numerals. For simplicity, the cell boundary of the delay cell300C, which is similar to the boundary340of the delay cell300A is omitted inFIG.3C. In at least one embodiment, the layout diagram of the delay cell300C is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell300C comprises a VD via structure353, an M0conductive pattern352, a VIA0via structure356, an M1conductive pattern358, a VIA0via structure357, and an M0conductive pattern355corresponding to the VD via structure325, M0conductive pattern332, VIA0via structure336, M1conductive pattern338, VIA0via structure337, and M0conductive pattern335in the delay cell300A. In the delay cell300C, the M0conductive pattern352is the output of the delay circuit310and is over the active region301. This is different from the delay cell300A in which the output of the delay circuit310is the M0conductive pattern332which is over the active region302. Further, in the delay cell300C, the M0conductive pattern355which is to be electrically coupled to the input of a succeeding delay circuit is over the active region302. This is different from the delay cell300A in which the corresponding M0conductive pattern335is over the active region301. In at least one embodiment, one or more advantages described herein with respect to the delay cell300A and/or delay cell300B are achievable in the delay cell300C. FIG.3Dis a schematic view of a layout diagram of a delay cell300D in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell300D corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.3CandFIG.3Dare designated by the same reference numerals. For simplicity, the cell boundary of the delay cell300D, which is similar to the boundary340of the delay cell300A is omitted inFIG.3D. In at least one embodiment, the layout diagram of the delay cell300D is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell300D differs from the delay cell300C in the configuration of the output connector electrically coupled to the output of the delay circuit310. Specifically, the output connector in the delay cell300D comprises a shorter M1conductive pattern368than the corresponding M1conductive pattern358in the delay cell300C. The output connector in the delay cell300D further comprises a VIA0via structure367and an M0conductive pattern365corresponding to the VIA0via structure357and M0conductive pattern355in the delay cell300C. While the VIA0via structure357and M0conductive pattern355in the delay cell300C are arranged over the active region302, the corresponding VIA0via structure367and M0conductive pattern365in the delay cell300D are arranged over a spacing or intermediate region between the active regions301,302, due to the shorter M1conductive pattern368. In at least one embodiment, one or more advantages described herein with respect to the delay cell300A and/or delay cell300B and/or delay cell300C are achievable in the delay cell300D. FIG.4Ais a schematic cross-sectional view, taken along line IV-IV inFIG.3A, of an IC device400, in accordance with some embodiments. The IC device400comprises a circuit region corresponding to the delay cell300A described with respect toFIG.3A. Components inFIG.4Ahaving corresponding components inFIG.3Aare designated by the reference numerals ofFIG.3Aincreased by100. For example, the IC device400comprises MD contact structure423, VD via structure425, VD rails428,429, M0conductive patterns432,433,434,435, VIA0via structures436,437, and M1conductive pattern438corresponding to the MD contact structure323, VD via structure325, VD rails328,329, M0conductive patterns332,333,334,335, VIA0via structures336,338, and M1conductive pattern338in the delay cell300A. As illustrated inFIG.4A, the IC device400comprises a substrate450over which the circuit region corresponding to the delay cell300A is formed. The substrate450has a thickness direction along a Z-axis. P-type and N-type dopants are added to the substrate450to correspondingly form a P-doped region451and an N-doped region452corresponding to the active regions301,302, and to also form an N well453in which the P-doped region451is formed. In some embodiments, isolation structures are formed between adjacent P well/P-doped regions and N well/N-doped regions. For simplicity, isolation structures are omitted fromFIG.4A. The P-doped region451defines a source/drain of a transistor corresponding to the transistor P2. The N-doped region452defines a source/drain of a transistor corresponding to the transistor N2. The IC device400further comprises contact structures for electrically coupling the source/drains of the transistors together and/or to other circuit elements in the circuitry of the IC device400. For example, the MD contact structure423is over and in electrical contact with the P-doped region451and N-doped region452. The IC device400further comprises VD, VG via structures and VD rails over and in electrical contact with corresponding MD contact structures and/or gate regions. For example, the VD via structure425is over and in electrical contact with the MD contact structure423. The IC device400further comprises an interconnect structure460which is over the VD, VG via structures and VD rails. The interconnect structure460comprises a plurality of metal layers M0, M1, . . . and a plurality of via layers V0, V1, . . . arranged alternatingly in the thickness direction of the substrate450, i.e., along the Z axis. The interconnect structure460further comprises various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The metal layers and via layers of the interconnect structure460are configured to electrically couple various elements or circuits of the IC device400with each other, and with external circuitry. For simplicity, metal layers and via layers above the M1layer are omitted inFIG.4A. The M0layer comprises M0conductive patterns432,444,434correspondingly over and in electrical contact with the VD via structure425, and the VD rails428,429. The M0layer further comprises the M0conductive patterns435. The VIA0layer comprises VIA0via structures436,437correspondingly over and in electrical contact with the M0conductive patterns432,435in the M0layer. The M1layer comprises an M1conductive pattern438correspondingly over and in electrical contact with the VIA0via structures436,437. In at least one embodiment, the IC device400further comprises one or more backside via structures (not shown) as described herein, a BM0layer (not shown) in electrical contact with the backside via structures, and/or one or more further via layers, dielectric layers and metal layers (not shown) under the BM0layer to form interconnections among circuit elements of the IC device400and/or to form electrical connections to external circuitry. Via layers and metal layers from the BM0layer and below are sometimes referred to as backside via layers and backside metal layers. In the IC device400, the M0conductive pattern432is the output of a delay circuit corresponding to the delay circuit310in the IC device400. The M0conductive pattern435is configured to be electrically coupled to the input of a succeeding delay circuit. The VIA0via structures436,437, the M1conductive pattern438and the M0conductive pattern435together configure an output connector416corresponding to the output connector216inFIGS.2B-2C, and/or the output connector described with respect toFIG.3A. FIG.4Bis a schematic cross-sectional view, taken along line IV′-IV′ inFIG.3A, of the IC device400, in accordance with some embodiments. Components inFIG.4Bhaving corresponding components inFIG.3Aare designated by the reference numerals ofFIG.3Aincreased by100. For example, the IC device400, inFIG.4B, further comprises a gate electrode411, an MD contact structure421corresponding to the gate region311and the MD contact structure321in the delay cell300A. As illustrated inFIG.4B, the IC device400further comprises a gate stack including gate dielectric layers454,455, and the gate electrode411. In at least one embodiment, a gate dielectric layer replaces multiple gate dielectric layers454,455. Example materials of the gate dielectric layer or layers include HfO2, ZrO2, or the like. Example materials of the gate electrode411include polysilicon, metal, or the like. As illustrated inFIG.4B, the VD rail428flies over, but is not in electrical contact with, the gate electrode411. In at least one embodiment, one or more advantages described herein with respect toFIG.3Aare achievable in the IC device400. FIG.5Ais a simplified schematic view of a layout diagram of a delay cell500A in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell500A corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.2BandFIG.5Aare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell500A is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. As illustrated inFIG.5A, the delay cell500A comprises a plurality of active regions501,502,503,504extending along the X-axis. In the example configuration inFIG.5A, the active regions501,503are PMOS active regions, and the active regions502,504are NMOS active regions. Other configurations are within the scopes of various embodiments. The PMOS active regions501,503are adjacent each other along the Y-axis, and are formed in a common N well. In at least one embodiment, the active regions501,502correspond to the active regions301,302described with respect toFIG.3A. The delay cell500A further comprises a plurality of gate regions extending along the Y-axis over the active regions501-504. For simplicity, not all gate regions in the delay cell500A are shown or given a reference numeral inFIG.5A. Some of the gate regions of the delay cell500A are indicated as gate regions511-519. The gate regions of the delay cell500A are arranged along the X axis at a regular pitch CPP as described herein. In the example configuration inFIG.5A, the gate regions511,512are functional gate regions, the gate regions518,519are dummy gate regions, and the gate regions513,514,515,516,517are configured as functional or dummy gate regions, as described herein. The delay cell500A further comprises a plurality of cut-poly regions521-527of a cut-poly mask which extend along the X axis and indicate areas where the gate regions are disconnected. The cut-poly regions521-527are schematically illustrated in the drawings with the label “CPO.” For example, the cut-poly region523extends across all gate regions, and indicates that each of the gate regions is separated by the cut-poly region523into an upper part over the active regions503,504and a lower part over the active regions501,502. The cut-poly region524extends across the lower parts of the gate regions513-515, and indicates that the lower part of each of the gate regions513-515is further separated into two disconnected gates. For example, the lower part of the gate region513is separated into gates P3d, N3, the lower part of the gate region514is separated into gates P4d, N4, and the lower part of the gate region515is separated into gates P5d, N5. The cut-poly regions521,527extend along edges of a boundary540described herein. In some embodiments, the layout of the delay cell500A has an upper part over the active regions503,504with a configuration similar to a configuration of a lower part over the active regions501,502. In at least one embodiment, the delay cell500A is symmetrical across a longitudinal center line of the cut-poly region523 The delay cell500A further comprises a boundary (or cell boundary)540similar to the boundary340described with respect toFIG.3A. The boundary540comprises a pair of edges (not numbered for simplicity) elongated along the X axis, and overlapping the cut-poly regions521,527. The boundary540comprises a further pair of edges (not numbered for simplicity) elongated along the Y axis, and overlapping the dummy gate regions518,519. In at least one embodiment, the edges elongated along the Y axis coincide correspondingly with center lines of the dummy gate regions518,519. The rectangular shape of the boundary540is an example. Other boundary shapes for various cells are within the scope of various embodiments. Between the edges elongated along the X axis, the delay cell500A contains two PMOS active regions, i.e.,501,503, and two NMOS active regions, i.e.,502,504, and is considered to have a double cell height. The delay cell500A further comprises various MD contact structures, VD/VG via structures, VD rails, M0conductive patterns, VIA0via structures, M1conductive patterns, further via and metal layers similar to corresponding features described with respect toFIGS.3A-3D. For simplicity, MD contact structures and various features above the MD contact structures and gate regions are omitted fromFIG.5A. A difference between the delay cell500A and the delay cell300A is that, while the delay cell300A comprises active regions301,302which are both continuous along the X-axis, the delay cell500A comprises one or more active regions which are discontinuous along the X-axis. For example, the active region501extends discontinuously along the X-axis, and comprises at least a first portion531and a second portion532spaced from each other along the X-axis by a spacing or intermediate region533. Doped regions and/or doped wells of the active region501are not formed in the intermediate region533. In other words, the intermediate region533is not configured to form, together with a gate region extending thereover, a transistor. In the example configuration inFIG.5A, the active region501comprises disconnected portions531,532,534,536,538arranged along the X-axis alternatingly with intermediate regions533,535,537,539. The number of intermediate regions inFIG.5Ais an example, and any natural number of intermediate regions in a delay cell is within the scopes of one or more embodiments. For example, in at least one embodiment, the delay cell500A has a single intermediate region533in the active region501over the whole length of the delay cell500A along the X-axis. In the example configuration inFIG.5A, the portion531is an end portion of the active region501at one end of the delay cell500A along the X-axis, extends between center lines of the gate regions518,511, and has a dimension A. The portion538is another end portion of the active region501at the other end of the delay cell500A along the X-axis, extends between center lines of the gate regions517,519, and has a dimension A. Each of the portions532,534,536of the active region501between the end portions531,538is referred to as a middle portion, extends between center lines of corresponding gate regions, and has a dimension C. For example, the middle portion532extends between center lines of the gate regions512,516. Each of the intermediate regions533,535,537,539extends between center lines of corresponding gate regions, and has a dimension B. For example, the intermediate region533extends between center lines of the gate regions513,515. In the example configuration inFIG.5A, the end portions531,538have the same dimension A, the intermediate regions533,535,537,539have the same dimension B, and the middle portions532,534,536have the same dimension C, where A>C>B. In an example, A≥9 CPP, B≥2 CPP and C≤9 CPP. A reason for the end portions531,538to have a greater dimension than the middle portions532,534,536is that, in some embodiments, the end portions531,538are configured to match with other cells when the delay cell500A is placed in abutment with the other cells. However, other configurations are within the scopes of various embodiments. For example, in some embodiments, the end portions531,538have different dimensions, and/or one or more of the intermediate regions533,535,537,539have a dimension different from the other intermediate regions, and/or one or more of the middle portions532,534,536have a dimension different from the other middle portions532,534,536. In one or more embodiments, the described relationship A>C>B is not necessarily observed. In at least one embodiment, A≥1 CPP, B≥1 CPP and C≥1 CPP. In one or more embodiments, the active region503is a discontinuous active region similar to the active region501. The active region502is a continuous active region that extends continuously along the X-axis. Along the Y-axis, the active region502overlaps the disconnected portions531,532,534,536,538of the active region501, as well as the intermediate regions533,535,537,539therebetween. In one or more embodiments, the active region504is a continuous active region similar to the active region502. The delay cell500A further comprises a plurality of transistors configured by the described gate regions and active regions. Further, the plurality of transistors are electrically coupled into one or more delay circuits. For example, the lower part of the gate region511over the active regions501,502configures gates P1, N1for corresponding transistors P1, N1. For simplicity, a gate and a corresponding transistor are referred to by the same reference numeral. The lower part of the gate region512over the active regions501,502configures gates P2, N2for corresponding transistors P2, N2. In some embodiments, the transistors P1, P2, N1, N2in the delay cell500A correspond to the transistors P1, P2, N1, N2described with respect toFIGS.2B and3A-3D. The gates N3, N4, N5over the active region502configure corresponding transistors N3, N4, N5which are NMOS transistors. The gates P3d, P4d, P5dare over the intermediate region533which is not configured to form a transistor. As a result, no transistors are formed by gates P3d, P4d, P5dover the intermediate region533. The gates P3d, P4d, P5dare sometimes referred to as dummy gates. The transistors P1-P2and N1-N5are electrically coupled into a delay circuit by various MD contact structures, VD/VG via structures, VD rails, M0conductive patterns, VIA0via structures, and/or M1conductive pattern, which are similar to those described with respect to one or more ofFIGS.3A-3D, but are not shown inFIG.5Afor simplicity. In the example configuration inFIG.5A, the transistors P1-P2and N1-N5are electrically coupled into a delay circuit510A which is similar to the delay circuit210with the addition of transistors N3-N5electrically coupled in series with the transistor N1. In some embodiments, the delay cell500A comprises an output connector as described with respect to one or more ofFIGS.3A-3D, and electrically coupled to the output of the delay circuit510A. In one or more embodiments, such an output connector is omitted, e.g., the output of the delay circuit510A and an input of a succeeding delay circuit are configured by the same conductive pattern in a metal layer. In one or more embodiments, the delay cell500A further comprises one or more delay circuits preceding to and/or one or more delay circuits succeeding the delay circuit510A. For example, one or more gate regions over the portion531of the active region501and a corresponding portion of the active region502configure further transistors which are electrically coupled into one or more delay circuits preceding to the delay circuit510A. For another example, one or more gate regions over at least one of the portions532,534,536,538of the active region501and a corresponding portion of the active region502configure further transistors which are electrically coupled into one or more delay circuits succeeding the delay circuit510A. The delay circuits formed over the active regions501,502in the delay cell500A are electrically coupled in series to add up the time delays of the delay circuits to obtain a required time delay for satisfying a timing requirement. In at least one embodiment, one or more delay circuits are configured over the active regions503,504and/or electrically coupled in a manner similar to that described for the active regions501,502. As described herein, the delay circuit510A is formed over a discontinuous active region501. In some situations, depending on one or more factors such as a dopant type (N-type or P-type) and/or technology for active region formation, a long continuous active region may experience high stress which potentially affects performance of the IC device. By configuring the active region501as a discontinuous active region, the stress on the active region501is reduced. A discontinuous active region also has a lower leakage current up to about 20% (e.g., the leakage current is reduced from 100% to about 80%). With the reduction of stress and/or leakage current in the active region501, a threshold voltage of transistors in the active region501is increased. As a result, in at least one embodiment, the time delay provided by the delay circuit510A becomes larger and/or the delay cell efficiency is increased. Further, because the transistors N3-N5are additionally electrically coupled in series with the transistor N1in the delay cell500A, the time delay provided by the delay circuit510A in one or more embodiments becomes larger and/or the delay cell efficiency is increased, compared to when the transistors N3-N5are not included in the delay circuit. One or more of the described advantages in accordance with some embodiments are improvements over other approaches which do not include a discontinuous active region and/or additional transistors in the delay circuit. In some embodiments, when one or more output connectors described with respect toFIGS.3A-3Dare included in the delay cell500A, one or more further advantages described with respect toFIGS.3A-3Dare additionally achievable in the delay cell500A. FIG.5Bis a schematic view of a layout diagram of a delay cell500B in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell500B corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.5AandFIG.5Bare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell500B is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell500B is similar to the delay cell500A, except that one of the gates N3-N5is configured as a dummy gate. For example, the gate N5in the delay cell500A is configured as a dummy gate Nd5in the delay cell500B. As a result, a delay circuit510B corresponding to the delay circuit510A no longer includes the transistor N5, and there are two additional transistors N3, N4electrically coupled in series to the transistor N1in the delay circuit510B. Compared to the delay circuit510A, the delay circuit510B has a smaller time delay. Nevertheless, in at least one embodiment, one or more advantages described herein with respect to the delay cell500A are achievable in the delay cell500B, compared to other approaches. In one or more embodiments, instead of the gate N5, either gate N3or N4in the delay cell500A is configured as a dummy gate to obtain the delay cell500B, with one or more similar advantages being achievable. FIG.5Cis a schematic view of a layout diagram of a delay cell500C in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell500C corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.5AandFIG.5Care designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell500C is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell500C is similar to the delay cell500A, except that two of the gates N3-N5are configured as dummy gates. For example, the gates N4, N5in the delay cell500A are configured as dummy gates Nd4, Nd5in the delay cell500C. As a result, a delay circuit510C corresponding to the delay circuit510A no longer includes the transistors N4, N5, and there is one additional transistor N3electrically coupled in series to the transistor N1in the delay circuit510C. Compared to the delay circuit510B, the delay circuit510C has a smaller time delay. Nevertheless, in at least one embodiment, one or more advantages described herein with respect to the delay cell500B are achievable in the delay cell500C, compared to other approaches. In one or more embodiments, instead of the gates N4and N5, another pair of gates N3and N5, or N3and N4, in the delay cell500A are configured as dummy gates to obtain the delay cell500C, with one or more similar advantages being achievable. In at least one embodiment, it is possible to adjust the time delay of a delay circuit by switching from one delay circuit configuration (e.g., one of the delay circuits510A,510B,510C) to another delay circuit configuration (e.g., another one of the delay circuits510A,510B,510C). This time delay adjustability or customizability is a further advantage, in one or more embodiments. FIG.5Dis a schematic view of a layout diagram of a delay cell500D in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell500D corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.5AandFIG.5Dare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell500D is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell500D is similar to the delay cell500A, except that PMOS active regions and transistors in the delay cell500A are replaced with NMOS active regions and transistors in the delay cell500D, and NMOS active regions and transistors in the delay cell500A are replaced with PMOS active regions and transistors in the delay cell500D. For example, the delay cell500D comprises NMOS active regions551,553corresponding to the PMOS active regions501,503of the delay cell500A. The delay cell500D further comprises PMOS active regions552,554corresponding to the NMOS active regions502,504of the delay cell500A. The PMOS active regions552,554of the delay cell500D are formed in separate N wells, as illustrated inFIG.5D. The delay cell500D comprises a delay circuit510D corresponding to the delay circuit510A. The delay circuit510D comprises transistors P1, P2, N1, N2electrically coupled together as described with respect toFIG.2B. The delay circuit510D comprises additional transistors P3-P5electrically coupled in series with the transistor P1in a manner similar to additional transistors N3-N5electrically coupled in series with the transistor N1in the delay circuit510A. In at least one embodiment, one or more advantages described herein with respect to the delay cell500A are achievable in the delay cell500D. FIG.5Eis a schematic view of a layout diagram of a delay cell500E in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell500E corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.5DandFIG.5Eare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell500E is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell500E is similar to the delay cell500D, except that one of the gates P3-P5is configured as a dummy gate. For example, the gate P5in the delay cell500D is configured as a dummy gate Pd5in the delay cell500E. As a result, a delay circuit510E corresponding to the delay circuit510D no longer includes the transistor P5, and there are two additional transistors P3, P4electrically coupled in series to the transistor P1in the delay circuit510E. Compared to the delay circuit510D, the delay circuit510E has a smaller time delay. Nevertheless, in at least one embodiment, one or more advantages described herein with respect to the delay cell500D are achievable in the delay cell500E, compared to other approaches. In one or more embodiments, instead of the gate P5, either gate P3or P4in the delay cell500D is configured as a dummy gate to obtain the delay cell500E, with one or more similar advantages being achievable. FIG.5Fis a schematic view of a layout diagram of a delay cell500F in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell500F corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.5DandFIG.5Fare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell500F is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell500F is similar to the delay cell500D, except that two of the gates P3-P5are configured as dummy gates. For example, the gates P4, P5in the delay cell500D are configured as dummy gates Pd4, Pd5in the delay cell500F. As a result, a delay circuit510F corresponding to the delay circuit510D no longer includes the transistors P4, P5, and there is one additional transistor P3electrically coupled in series to the transistor P1in the delay circuit510F. Compared to the delay circuit510E, the delay circuit510F has a smaller time delay. Nevertheless, in at least one embodiment, one or more advantages described herein with respect to the delay cell500E are achievable in the delay cell500F, compared to other approaches. In one or more embodiments, instead of the gates P4and P5, another pair of gates P3and P5, or P3and P4, in the delay cell500D are configured as dummy gates to obtain the delay cell500F, with one or more similar advantages being achievable. In at least one embodiment, it is possible to adjust the time delay of a delay circuit by switching from one delay circuit configuration (e.g., one of the delay circuits510D,510E,510F) to another delay circuit configuration (e.g., another one of the delay circuits510D,510E,510F). This time delay adjustability or customizability is a further advantage, in one or more embodiments. FIG.6Ais a schematic view of a layout diagram of a delay cell600A in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell600A corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.3AandFIG.6Aare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell600A is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. As illustrated inFIG.6Aand described with respect toFIG.3A, the delay cell600A comprises a first active region301of a first semiconductor type (e.g., PMOS) and extending along the X-axis, a second active region302of a different second semiconductor type (e.g., NMOS) and also extending along the X-axis, and a plurality of gate regions311,312,318,319extending along the Y-axis transverse to the X-axis and across the active regions301,302. The gate regions311,312configure, together with the active regions301,302, a plurality of transistors P1, P2, N1, N2which are electrically coupled into a delay circuit310configured to delay an input signal Ai at an input to generate a delayed signal Ai+1 at an output. The connections in the delay circuit310are established by various MD contact structures321,322,323,324, VD rails328,329, a VDD power rail configured by an M0conductive pattern333, a VSS power rail configured by an M0conductive pattern334, VG via structures326,327electrically coupling the corresponding gate regions311,312to the input configured by an M0conductive pattern331, and a VD via structure625electrically coupling the MD contact structure323to the output configured by an M0conductive pattern635. The delay cell600A has a boundary340as described with respect toFIG.3A. A difference between the delay cell600A and the delay cell300A is that an output connector of the delay cell300A as described with respect toFIG.3Ais not included in the delay cell600A. The output of the delay circuit310is configured by the M0conductive pattern635which, in at least one embodiment, is also the input to a succeeding delay circuit. The delay cell600A achieves an increased time delay by a different configuration. Specifically, in addition to the VG via structures326,327which are over and in electrical contact with the corresponding gate regions311,312to electrically couple the gate regions311,312to the M0conductive pattern331, the delay cell600A further comprises at least one VG via structure (referred to herein as “dummy VG via structure”) which is also over and in electrical contact with a gate region but is free of direct electrical contact with a conductive element other than the gate electrode. For example, the delay cell600A further comprises dummy VG via structures661,662over and in electrical contact with the corresponding gate regions311,312. However, besides the corresponding gate regions311,312, the dummy VG via structures661,662are not electrically coupled to any other circuit element. In at least one embodiment, a dummy VG via structure is not configured to electrically coupled the corresponding gate region to another circuit element; rather, the dummy VG via structure is configured to change a stress on an active region over which the dummy VG via structure is arranged. In the example configuration inFIG.6A, the dummy VG via structures661,662are arranged over the active region302and change a stress on the active region302. As a result, in at least one embodiment, a threshold voltage of the transistors N1, N2, configured by the active region302and the gate regions311,312over which the dummy VG via structures661,662are arranged, is increased. The increased threshold voltage of the transistors N1, N2causes an increase in the time delay of the delay circuit310in the delay cell600A, in one or more embodiments. One or more advantages associated with the increased time delay of a delay circuit are therefore achievable in the delay cell600A in accordance with some embodiments. FIG.6Bis a schematic view of a layout diagram of a delay cell600B in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell600B corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.6AandFIG.6Bare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell600B is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell600B differs from the delay cell600A in locations of dummy VG via structures. Specifically, in the delay cell600A, the dummy VG via structures661,662are arranged over the NMOS active region302to increase the threshold voltage of the corresponding NMOS transistors N1, N2. In the delay cell600B, dummy VG via structures663,664are formed over the corresponding gate regions311,312and over the PMOS active region301to increase the threshold voltage of the corresponding PMOS transistors P1, P2. As a result, the time delay of the delay circuit310in the delay cell600B is increased and one or more advantages associated with the increased time delay of a delay circuit are therefore achievable in the delay cell600B, in accordance with some embodiments. FIG.6Cis a schematic view of a layout diagram of a delay cell600C in an IC device, in accordance with some embodiments. In at least one embodiment, the delay cell600C corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIGS.6A-6Band inFIG.6Care designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell600C is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. The delay cell600C differs from the delay cells600A,600B in locations of dummy VG via structures. Specifically, in each of the delay cells600A,600B, dummy VG via structures are arranged over one active region301or302. In the delay cell600C, dummy VG via structures661,662,663,664are formed over both active regions301,302to increase the threshold voltage of the transistors P1, P2, N1, N2. As a result, the time delay of the delay circuit310in the delay cell600C is increased and one or more advantages associated with the increased time delay of a delay circuit are therefore achievable in the delay cell600C, in accordance with some embodiments. In the example configurations inFIGS.6A-6C, one dummy VG via structure is arranged over a gate region over an active region. For example, as illustrated inFIG.6C, one dummy VG via structure662is arranged over the gate region312over the active region302. However, in some embodiments, multiple dummy VG via structures are arranged over a gate region over an active region. For example, in addition to the dummy VG via structure662, in one or more embodiments, the delay circuit further includes one or more other dummy VG via structures also over the gate region312over the active region302. In at least one embodiment, the increased number of dummy VG via structure over a gate region over an active region leads to a further increase in the threshold voltage of the corresponding transistor which results in an associated further increase in the time delay of the delay circuit or delay cell. In at least one embodiment, it is possible to adjust the time delay of a delay circuit and the corresponding delay cell, by selecting whether to arrange dummy VG via structures and/or how many dummy VG via structures to arrange over which (i.e., PMOS and/or NMOS) active region. This time delay adjustability or customizability is a further advantage, in one or more embodiments. FIG.6Dis a schematic view of a layout diagram of a delay cell600D in an ID device, in accordance with some embodiments. In at least one embodiment, the delay cell600D corresponds to the delay circuitry200B, or to a part of the delay circuitry200B where the delay circuitry200B comprises multiple delay cells. Corresponding elements inFIG.6Cand inFIG.6Dare designated by the same reference numerals. In at least one embodiment, the layout diagram of the delay cell600D is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. Compared to the delay cell300A, the delay cell600D additionally comprises dummy VG via structures661,662,663,664. Thus, the delay cell600D comprises both an output connector as described with respect toFIG.3Aand dummy VG via structures as described with respect toFIG.6C. Other configurations are within the scopes of various embodiments. For example, in some embodiments, one or more dummy VG via structures are arranged over one or more active regions in one or more of the delay cells described with respect toFIGS.3A-3D,5A-5Fto achieve one or more advantages described herein. FIG.7Ais a schematic cross-sectional view, taken along line VII-VII inFIG.6A, of an IC device700, in accordance with some embodiments. Corresponding elements inFIG.4AandFIG.7Aare designated by the same reference numerals. As illustrated inFIG.7Aand described with respect toFIG.4A, the IC device700comprises a substrate450having therein a P-doped region451in an N well453, and an N-doped regions452. An MD contact structure423is an extended contact structure over and electrically coupling the P-doped region451and N-doped regions452. The MD contact structure423is electrically coupled to a VD via structure725corresponding to the VD via structure625inFIG.6A. The VD via structure725is further electrically coupled to an M0conductive pattern735corresponding to the output of the delay circuit310inFIG.6A. The IC device700further comprises VD rails428,429and corresponding power rails such as M0conductive patterns433,434in the M0layer as described with respect toFIG.4A. As illustrated inFIGS.4A,7A, the IC device700is different from the IC device400in that an output connector comprising an M1conductive pattern of the IC device400is not included in the IC device700. FIG.7Bis a schematic cross-sectional view, taken along line VII′-VII′ inFIG.6A, of the IC device700, in accordance with some embodiments. Corresponding elements inFIG.4BandFIG.7Bare designated by the same reference numerals. Components inFIG.7Bhaving corresponding components inFIG.4Bare designated by the reference numerals. As illustrated inFIG.7B, the IC device700further comprises a gate stack including gate dielectric layers454,455, and a gate electrode712corresponding to the gate region312inFIG.6A. The VD rails728,729fly over, but are not in electrical contact with, the gate electrode712. A VG via structure727corresponding to the VG via structure327inFIG.6Aelectrically couples the gate electrode712to an M0conductive pattern731corresponding to the input of the delay circuit310such as M0conductive pattern331inFIG.6A. A dummy VG via structure762corresponding to the dummy VG via structure662inFIG.6Ais over and in electrical contact with the gate electrode712. As illustrated inFIG.7B, the dummy VG via structure762is free of direct electrical contact with a conductive element other than the gate electrode712. In at least one embodiment, one or more advantages described herein with respect toFIG.6Aare achievable in the IC device700. FIG.8Ais a flowchart of a method800A of generating a layout diagram and using the layout diagram to manufacture an IC device, in accordance with some embodiments. Method800A is implementable, for example, using EDA system900(FIG.9, discussed below) and an integrated circuit (IC) manufacturing system1000(FIG.10, discussed below), in accordance with some embodiments. Regarding method800A, examples of the layout diagram include the layout diagrams disclosed herein, or the like. Examples of an IC device to be manufactured according to method800A include IC devices400,700. InFIG.8A, method800A includes blocks805,815. At block805, a layout diagram is generated which, among other things, include patterns represent one or more circuit regions, circuitry, circuits or cells as described with respect toFIGS.3A-3D,5A-5F,6A-6Dor the like. An example of an IC device corresponding to a layout diagram generated by block805includes IC device100,400or700. Block805is discussed in more detail below with respect toFIG.8B. From block805, flow proceeds to block815. At block815, based on the layout diagram, at least one of (A) one or more photolithographic exposures are made or (b) one or more semiconductor masks are fabricated or (C) one or more components in a layer of an IC device are fabricated. Block815is discussed in more detail below with respect toFIG.8C. FIG.8Bis a flowchart of a method800B of generating a layout diagram, in accordance with some embodiments. More particularly, the flowchart ofFIG.8Bshows additional blocks that demonstrates one example of procedures implementable in block805ofFIG.8A, in accordance with one or more embodiments. InFIG.8B, block805includes blocks825,835. At block825, at least one cell having at least one delay circuit is generated, or retrieved from a cell library. For example, a delay cell corresponding to one or more of the layout diagrams described with respect toFIGS.3A-3D,5A-5F,6A-6Dis generated, or retrieved from a cell library. In at least one embodiment, the delay cell is selected to be retrieved or generated based on a time delay required for satisfying a timing requirement and/or various customizable/selectable configurations as described herein. At block835, the at least one cell having at least one delay circuit is placed in abutment with another cell in the layout diagram. In some embodiments, multiple delay cells are placed in abutment to serially couple the delay circuits of the multiple abutted delay cells to achieve a required time delay. In at least one embodiment, the generated layout diagram of the IC device is stored on a non-transitory computer-readable medium. FIG.8Cis a flowchart of a method800C of fabricating one or more components of an IC device, based on the layout diagram, in accordance with some embodiments. More particularly, the flowchart ofFIG.8Cshows additional blocks that demonstrates one example of procedures implementable in block815ofFIG.8A, in accordance with one or more embodiments. InFIG.8C, block815includes blocks845,855,865. At block845, active regions and gate regions are formed over a substrate to configure a plurality of transistors. In some embodiments, the active regions, gate regions and/or transistors correspond to one or more of the active regions, gate regions and/or transistors described with respect toFIGS.2B-7B. An example manufacturing process starts from a substrate, such as the substrate450described with respect toFIG.4A. The substrate comprises, in at least one embodiment, silicon, silicon germanium (SiGe), gallium arsenic, or other suitable semiconductor materials. Active regions are formed in or over the substrate, using one or more masks corresponding to one or more active regions in the layout diagrams described herein. A gate dielectric material layer is deposited over the substrate. Example materials of the gate dielectric material layer include, but are not limited to, a high-k dielectric layer, an interfacial layer, and/or combinations thereof. In some embodiments, the gate dielectric material layer is deposited over the substrate by atomic layer deposition (ALD) or other suitable techniques. A gate electrode layer is deposited over the gate dielectric material layer. Example materials of the gate electrode layer include, but are not limited to, polysilicon, metal, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and/or other suitable conductive materials. In some embodiments, the gate electrode layer is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD or sputtering), plating, atomic layer deposition (ALD), and/or other suitable processes. A patterning process is then performed, using one or more masks corresponding to one or more gate electrodes in the layout diagrams described herein. As a result, the gate dielectric material layer is patterned in to one or more gate dielectric layers, such as the gate dielectric layers454,455, and the gate electrode layer is patterned into one or more gate electrodes, such as the gate electrode411described with respect toFIG.4B. In at least one embodiment, spacers are formed, by deposition and patterning, on opposite sides of each gate electrode. Example materials of the spacers include, but are not limited to, silicon nitride, oxynitride, silicon carbide and other suitable materials. Example deposition processes include, but are not limited to, plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), or the like. Example patterning processes include, but are not limited to, a wet etch process, a dry etch process, or combinations thereof. Drain/source regions, such as the doped regions451,452described with respect toFIG.4A, are formed in the active regions of the substrate. In at least one embodiment, the drain/source regions are formed by using the gate electrodes and the spacers as a mask. For example, the formation of the drain/source regions is performed by an ion implantation or a diffusion process. Depending on the type of the devices or transistors, the drain/source regions are doped with p-type dopants, such as boron or BF2, n-type dopants, such as phosphorus or arsenic, and/or combinations thereof. In some embodiments, at least one of the active regions is formed as a discontinuous active region, for example, as described with respect toFIGS.5A-5F. As a result, one or more advantages associated with discontinuous active regions, e.g., increased time delays and/or increased delay cell efficiency, are achievable in at least one embodiment. In some embodiments, the formation of discontinuous active regions is omitted. At block855, contact structures, via structures and one or more metal layers are formed to electrically couple the transistors into a delay circuit. In some embodiments, the delay circuit corresponds to one or more delay circuits described with respect toFIGS.2A-2C, and the contact structures, via structures and one or more metal layers that electrically couple the transistors into the delay circuit correspond to one or more contact structures, via structures and metal layers described with respect toFIGS.3A-7B. In an example manufacturing process, a conductive layer, e.g., a metal, is deposited over the substrate with the transistors formed thereon, thereby making electrical connections to the drain/source regions of the transistors. A planarizing process is performed to planarize the conductive layer, resulting in contact structures, such as the MD contact structures421,423described with respect toFIGS.4A,4B, in electrical contact with the underlying drain/source regions. The planarizing process comprises, for example, a chemical mechanical polish (CMP) process. A dielectric layer is deposited over the substrate with the drain/source contacts formed thereon. The dielectric layer is etched, and the etched portions are filled with a conductive material, such as a metal, to form one or more via structures, such as the VD and VG via structures425,725,727,762described with respect toFIGS.4A,7A,7B. In some embodiments, VD rails, such as VD rails428,429described with respect toFIGS.4A,4B, are also formed together with VD via structures. A planarizing process is performed. An M0layer including a conductive material, such as a metal, is deposited over the planarized structure and patterned to form various M0conductive patterns, such as the M0conductive patterns432-435described with respect toFIGS.4A-4B. In the example configurations described herein, an output of the delay circuit is an M0conductive pattern in the M0layer. However, other delay circuit configurations where the output of the delay circuit is in a metal layer different from the M0layer are within the scopes of various embodiments. In some embodiments, while forming VD, VG via structures that electrically couple the transistors into a delay circuit, one or more dummy VG via structures are also formed over one or more gate regions and active regions, for example, as described with respect toFIGS.6A-6D, to change a stress on the underlying active regions. As a result, one or more advantages associated with dummy VG via structures, e.g., increased time delays and/or increased delay cell efficiency, are achievable in at least one embodiment. In some embodiments, the formation of dummy VG via structures is omitted. At block865, an output connector is formed to include at least one conductive pattern in a metal layer different from the metal layer containing an output of the delay circuit. In some embodiments, the output connector comprises an M1conductive pattern in the M1layer different from the M0layer in which the output of the delay circuit is arranged, for example, as described with respect toFIGS.3A-4B. Other delay circuit configurations where the output connector comprises a conductive pattern in a metal layer different from the M1layer are within the scopes of various embodiments. In an example manufacturing process, a dielectric layer is deposited over the patterned M0layer. The dielectric layer is etched, and the etched portions are filled with a conductive material, such as a metal, to form one or more via structures in a VIA0layer. For example, the VIA0layer comprises the VIA0via structures436,437described with respect toFIG.4A. A planarizing process is then performed. An M1layer including a conductive material, such as a metal, is deposited over the planarized structure obtained at the end of the formation of the VIA0layer. The M1layer is patterned to form various M1conductive patterns, such as the M1conductive pattern438described with respect toFIG.4A. The M1conductive pattern438and the VIA0via structures436,437electrically couple the M0conductive pattern432, which is the output of the delay circuit, to a further M0conductive pattern435, as described with respect toFIG.4A. An output connector416is thus obtained. In some embodiments, the output connector increases the resistance and/or capacitance at the output of the delay circuit. As a result, one or more advantages associated with such increased resistance and/or capacitance, e.g., increased time delays and/or increased delay cell efficiency, are achievable in at least one embodiment. In some embodiments, the formation of an output connector is omitted. The described methods include example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure. In some embodiments, at least one method(s) discussed above is performed in whole or in part by at least one EDA system. In some embodiments, an EDA system is usable as part of a design house of an IC manufacturing system discussed below. FIG.9is a block diagram of an electronic design automation (EDA) system900in accordance with some embodiments. In some embodiments, EDA system900includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system900, in accordance with some embodiments. In some embodiments, EDA system900is a general purpose computing device including a hardware processor902and a non-transitory, computer-readable storage medium904. Storage medium904, amongst other things, is encoded with, i.e., stores, computer program code906, i.e., a set of executable instructions. Execution of instructions906by hardware processor902represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Processor902is electrically coupled to computer-readable storage medium904via a bus908. Processor902is also electrically coupled to an I/O interface910by bus908. A network interface912is also electrically connected to processor902via bus908. Network interface912is connected to a network914, so that processor902and computer-readable storage medium904are capable of connecting to external elements via network914. Processor902is configured to execute computer program code906encoded in computer-readable storage medium904in order to cause system900to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor902is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, computer-readable storage medium904is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium904includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium904includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, storage medium904stores computer program code906configured to cause system900(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904stores library907of standard cells including such standard cells as disclosed herein. EDA system900includes I/O interface910. I/O interface910is coupled to external circuitry. In one or more embodiments, I/O interface910includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor902. EDA system900also includes network interface912coupled to processor902. Network interface912allows system900to communicate with network914, to which one or more other computer systems are connected. Network interface912includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems900. System900is configured to receive information through I/O interface910. The information received through I/O interface910includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor902. The information is transferred to processor902via bus908. EDA system900is configured to receive information related to a UI through I/O interface910. The information is stored in computer-readable medium904as user interface (UI)942. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system900. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. FIG.10is a block diagram of an integrated circuit (IC) manufacturing system1000, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system1000. InFIG.10, IC manufacturing system1000includes entities, such as a design house1020, a mask house1030, and an IC manufacturer/fabricator (“fab”)1050, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1060. The entities in system1000are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050is owned by a single larger company. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050coexist in a common facility and use common resources. Design house (or design team)1020generates an IC design layout diagram1022. IC design layout diagram1022includes various geometrical patterns designed for an IC device1060. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1060to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1022includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1020implements a proper design procedure to form IC design layout diagram1022. The design procedure includes one or more of logic design, physical design or place-and-route operation. IC design layout diagram1022is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1022can be expressed in a GDSII file format or DFII file format. Mask house1030includes data preparation1032and mask fabrication1044. Mask house1030uses IC design layout diagram1022to manufacture one or more masks1045to be used for fabricating the various layers of IC device1060according to IC design layout diagram1022. Mask house1030performs mask data preparation1032, where IC design layout diagram1022is translated into a representative data file (“RDF”). Mask data preparation1032provides the RDF to mask fabrication1044. Mask fabrication1044includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1045or a semiconductor wafer1053. The design layout diagram1022is manipulated by mask data preparation1032to comply with particular characteristics of the mask writer and/or requirements of IC fab1050. InFIG.10, mask data preparation1032and mask fabrication1044are illustrated as separate elements. In some embodiments, mask data preparation1032and mask fabrication1044can be collectively referred to as mask data preparation. In some embodiments, mask data preparation1032includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1022. In some embodiments, mask data preparation1032includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, mask data preparation1032includes a mask rule checker (MRC) that checks the IC design layout diagram1022that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1022to compensate for limitations during mask fabrication1044, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, mask data preparation1032includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1050to fabricate IC device1060. LPC simulates this processing based on IC design layout diagram1022to create a simulated manufactured device, such as IC device1060. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1022. It should be understood that the above description of mask data preparation1032has been simplified for the purposes of clarity. In some embodiments, data preparation1032includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1022according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1022during data preparation1032may be executed in a variety of different orders. After mask data preparation1032and during mask fabrication1044, a mask1045or a group of masks1045are fabricated based on the modified IC design layout diagram1022. In some embodiments, mask fabrication1044includes performing one or more lithographic exposures based on IC design layout diagram1022. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1045based on the modified IC design layout diagram1022. Mask1045can be formed in various technologies. In some embodiments, mask1045is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1045includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1045is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1045, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1044is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1053, in an etching process to form various etching regions in semiconductor wafer1053, and/or in other suitable processes. IC fab1050is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1050is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. IC fab1050includes fabrication tools1052configured to execute various manufacturing operations on semiconductor wafer1053such that IC device1060is fabricated in accordance with the mask(s), e.g., mask1045. In various embodiments, fabrication tools1052include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein. IC fab1050uses mask(s)1045fabricated by mask house1030to fabricate IC device1060. Thus, IC fab1050at least indirectly uses IC design layout diagram1022to fabricate IC device1060. In some embodiments, semiconductor wafer1053is fabricated by IC fab1050using mask(s)1045to form IC device1060. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1022. Semiconductor wafer1053includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1053further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). Details regarding an integrated circuit (IC) manufacturing system (e.g., system1000ofFIG.10), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. In an embodiment, an integrated circuit (IC) device comprises at least one delay circuit comprising an input and an output, and an output connector electrically coupled to the output. The delay circuit further comprises a plurality of transistors electrically coupled with each other between the input and the output. The plurality of transistors is configured to delay an input signal received at the input to generate a delayed signal at the output. The output is in a first metal layer. The output connector comprises a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. The second conductive pattern electrically couples the output to the first conductive pattern. In an embodiment, an integrated circuit (IC) device comprises a first active region of a first semiconductor type, a second active region of a second semiconductor type different from the first semiconductor type, and a plurality of gate electrodes. The first active region extends discontinuously along a first axis, and comprises first and second portions spaced from each other along the first axis. The second active region extends continuously along the first axis. The second active region overlaps, along a second axis transverse to the first axis, the first and second portions of the first active region and a spacing between the first and second portions of the first active region. The plurality of gate electrodes extends along the second axis and across the first and second active regions. The plurality of gate electrodes and the first and second portions of the first active region are configured as a plurality of transistors of a first type. The plurality of gate electrodes and the second active region are configured as a plurality of transistor of a second type different from the first type. The plurality of transistors of the first type and the plurality of transistors of the second type are electrically coupled into at least one delay circuit configured to delay an input signal at an input to generate a delayed signal at an output. In an embodiment, an integrated circuit (IC) device comprises a first active region of a first semiconductor type and extending along a first axis, a second active region of a second semiconductor type different from the first semiconductor type and extending along the first axis, and a plurality of gate electrodes extending along a second axis transverse to the first axis and across the first and second active regions. The plurality of gate electrodes and the first active region are configured as a plurality of transistors of a first type. The plurality of gate electrodes and the second active region are configured as a plurality of transistor of a second type different from the first type. The plurality of transistors of the first type and the plurality of transistors of the second type are electrically coupled into at least one delay circuit configured to delay an input signal at an input to generate a delayed signal at an output. The IC device further comprises a plurality of via structures over and in electrical contact with a gate electrode among the plurality of gate electrodes. The plurality of via structures comprises at least one first via structure which is free of direct electrical contact with a conductive element other than the gate electrode, the at least one first via structure over one of the first and second active regions. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 114,862 |
11862622 | DETAILED DESCRIPTION To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. FIG.1shows a flow chart of a method10for forming an integrated circuit layout according to one embodiment of the present invention. The method10may be performed by using any kind of computer system, such as a personal computer, portable computer, workstation, computer terminal, network computer, or any suitable data processing system or device. As shown inFIG.1, the method10for forming an integrated circuit layout provided by the present invention includes performing step12, setting a default gate line pitch (the default gate line pitch P), a default gate line width (the default gate line width L), and a variable (for example, the first variable d1). Following, step14is performed, which includes generating a plurality (a set) of first gate lines arranged between two first cell boundaries based on that default gate line pitch and the default gate line width, and generating a plurality (a set) of second gate lines arranged between two second cell boundaries based on the default gate line pitch and a sum of the default gate line width and the variable. Following, step16is performed, which includes placing dummy gate lines on the two first cell boundaries and the two second cell boundaries to obtain a first standard cell and a second standard cell. According to an embodiment of the present invention, the step12may further include setting another variable (for example, the second variable d2), and the step14may further include generating a plurality (a set) of third gate lines arranged between two third cell boundaries based on the default gate line pitch and a sum of the default gate line width and the another variable (for example, the second variable d2). The step16may further include placing dummy gate lines on the two third cell boundaries to form a third standard cell. It should be understood that other variables may be set in step12for forming standard cells based on the default gate line pitch and the other variables according to design needs. Please refer toFIG.2,FIG.3, andFIG.4, which are schematic drawings showing some exemplary standard cells obtained by the method10shown inFIG.1. It should be noted that in each drawing, the standard cell shown in the upper portion and the standard cell shown in the lower portion have the same gate line pitch (the default gate line pitch P) and the same gate line width (the default gate line width L), but have different circuit designs for providing different functions. The standard cells shown in the upper portions ofFIG.2,FIG.3, andFIG.4have the same circuit design and function and the same gate line pitch (the default gate line pitch P), but have different gate line widths (the default gate line width L, a sum of the default gate line width L and the first variable d1, a sum of the default gate line width L and the second variable d2) for providing different speeds or powers. It should be noted that the layouts of the standard cells shown inFIG.2,FIG.3, andFIG.4are only examples, and the numbers of the gate lines, active region patterns are for the purpose of drawing and illustration, and should not be taken as limitation to the present invention. The present invention may be applied to standard cells that include a plurality of gate lines. In detail, the standard cell Cell-A1and the standard cell Cell-A2shown inFIG.2respectively include a pair of cell boundaries104that extend along a second direction D2and are parallel to each other, a pair of cell boundaries106that extend along a first direction D1perpendicular to the second direction D2and are parallel to each other, a plurality of active region patterns108that extend along the first direction D1and are arranged in parallel along the second direction D2, a plurality of gate lines102that extend along the second direction D2and are arranged along the first direction D1between the two cell boundaries104, and two dummy gate lines400that are overlapped with the cell boundaries104and are respectively distanced from the gate lines102by a dummy gate line space SA2and a dummy gate line space SA3between the edges of the dummy gate lines400and the edges of the adjacent gate lines102. According to an embodiment of the present invention, as shown inFIG.2, the distal ends of the active region patterns108are overlapped by the gate lines102or the dummy gate lines400and are not exposed. The gate lines102of the standard cell Cell-A1and the standard cell Cell-A2respectively have a gate line width LA and are distanced from each other by a default gate line pitch P. The default gate line pitch P is the sum of the gate line width LA and a gate line space SA1between the edges of two adjacent gate lines102. The active region patterns108of the standard cell Cell-A1and the standard cell Cell-A2have an active region width108aand are distanced from each other by an active region pitch108b. It is noteworthy that a cell width WA1of the standard cell Cell-A1between the cell boundaries104of the standard cell Cell-A1and a cell width WA2of the standard cell Cell-A2between the cell boundaries104of the standard cell Cell-A2are respectively integral multiples of the default gate line pitch P. The gate lines102of the standard cell Cell-A1are arranged between the cell boundaries104in a way that the cell width WA1may be divided into equal portions by the gate lines102. The gate lines102of the standard cell Cell-A2are arranged between the cell boundaries104in a way that the cell width WA2may be divided into equal portions by the gate lines102. In other words, along the center lines102aof the gate lines102, the standard cell Cell-A1and the standard cell Cell-A2may be divided into portions having the same width. It is also noteworthy that the cell boundaries104are substantially along the center lines of the dummy gate lines400, so that the dummy gate lines400are respectively divided into two half portions400aand400bby the cell boundaries104, wherein the half portion400ahas a half width Wa, the half portion400bhas a half width Wb, and the half width Wa and the half width Wb are the same. According to the above limitations, the dummy gate line space SA2and the dummy gate line space SA3may be the same, and the distances between the cell boundaries104and may be the same. As shown inFIG.3, the standard cell Cell-B1and the standard cell Cell-B2respectively include a pair of cell boundaries204that extend along the second direction D2and are parallel to each other, a pair of cell boundaries206that extend along the first direction D1and are parallel to each other, a plurality of active region patterns208that extend along the first direction D1and are arranged in parallel along the second direction D2, a plurality of gate lines202that extend along the second direction D2and are arranged along the first direction D1between the two cell boundaries204. According to an embodiment of the present invention, the standard cell Cell-B1and the standard cell Cell-B2as shown inFIG.3may have the dummy gate lines400the same as that of the standard cell Cell-A1and the standard cell Cell-A2shown inFIG.2. The cell boundaries204of the standard cell Cell-B1and the standard cell Cell-B2are overlapped with the dummy gate lines400, and the dummy gate lines400are distanced from the adjacent gate lines202by a dummy gate line space SB2and a dummy gate line space SB3between the edges of the dummy gate lines400and the edges of the adjacent gate lines202. The distal ends of the active region patterns208are overlapped by the gate lines202or the dummy gate lines400and are not exposed. The gate lines202of the standard cell Cell-B1and the standard cell Cell-B2respectively have a gate line width LB and are distanced from each other by a default gate line pitch P, wherein the gate line width LB is different from the gate line width LA, and the default gate line pitch P is the sum of the gate line width LB and a gate line space SB1between the edges of two adjacent gate lines202. The active region patterns208of the standard cell Cell-B1and the standard cell Cell-B2respectively have an active region width208aand are distanced from each other by an active region pitch208b. According to an embodiment of the present invention, the active region width208ais the same as the active region width108a, and the active region pitch208bis the same as the active region pitch108b. It is noteworthy that a cell width WB1of the standard cell Cell-B1between the cell boundaries204of the standard cell Cell-B1and a cell width WB2of the standard cell Cell-B2between the cell boundaries204of the standard cell Cell-B2are respectively integral multiples of the default gate line pitch P. The gate lines202of the standard cell Cell-B1are arranged between the cell boundaries204in a way that the cell width WB1may be divided into equal portions by the gate lines202. The gate lines202of the standard cell Cell-B2are arranged between the cell boundaries204in a way that the cell width WB2may be divided into equal portions by the gate lines202. In other words, along the center lines202aof the gate lines202, the standard cell Cell-B1and the standard cell Cell-B2may be divided into portions having the same width. It is also noteworthy that the cell boundaries204are substantially along the center lines of the dummy gate lines400, so that the dummy gate lines400of the standard cell Cell-B1and the standard cell Cell-B2are respectively divided into two half portions400aand400bby the cell boundaries204, wherein the half portion400ahas a half width Wa, the half portion400bhas a half width Wb, and the half width Wa and the half width Wb are the same. According to the above limitations, it should be understood that the dummy gate line space SB2and the dummy gate line space SB3may be the same, and the distances between the cell boundaries204and the same. As shown inFIG.4, the standard cell Cell-C1and the standard cell Cell-C2respectively include a pair of cell boundaries304that extend along the second direction D2and are parallel to each other, a pair of cell boundaries306that extend along the first direction D1and are parallel to each other, a plurality of active region patterns308that extend along the first direction D1and are arranged in parallel along the second direction D2, a plurality of gate lines302that extend along the second direction D2and are arranged along the first direction D1between the two cell boundaries304. According to an embodiment of the present invention, the standard cell Cell-C1and the standard cell Cell-C2shown inFIG.4may have the dummy gate lines400the same as that of the standard cell Cell-B1and the standard cell Cell-B2shown inFIG.3and the standard cell Cell-A1and the standard cell Cell-A2shown inFIG.2. The cell boundaries304of the standard cell Cell-C1and the standard cell Cell-C2are overlapped with the dummy gate lines400, and the dummy gate lines400are distanced from the adjacent gate lines302by a dummy gate line space SC2and a dummy gate line space SC3between the edges of the dummy gate lines400and the edges of the adjacent gate lines302. The distal ends of the active region patterns308are overlapped by the gate lines302or the dummy gate lines400and are not exposed. The gate lines302of the standard cell Cell-C1and the standard cell Cell-C2respectively have a gate line width LC and are distanced from each other by a default gate line pitch P, wherein the gate line width LC is different from the gate line width LA and the gate line width LB, and the default gate line pitch P is the sum of the gate line width LC and a gate line space SC1between the edges of two adjacent gate lines302. The active region patterns308of the standard cell Cell-C1and the standard cell Cell-C2respectively have an active region width308aand are distanced from each other by an active region pitch308b. According to an embodiment of the present invention, the active region width108a, the active region width128a, and the active region width308aare the same; the active region pitch108b, the active region pitch208b, and the active region pitch308bare the same. It is noteworthy that a cell width WC1of the standard cell Cell-C1between the cell boundaries304of the standard cell Cell-C1and a cell width WC2of the standard cell Cell-C2between the cell boundaries304of the standard cell Cell-C2are respectively integral multiples of the default gate line pitch P. The gate lines302of the standard cell Cell-C1are arranged between the cell boundaries304in a way that the cell width WC1may be divided into equal portions by the gate lines302. The gate lines302of the standard cell Cell-C2are arranged between the cell boundaries304in a way that the cell width WC2may be divided into equal portions by the gate lines302. In other words, along the center lines302aof the gate lines302, the standard cell Cell-C1and the standard cell Cell-C2may be divided into portions having the same width. It is also noteworthy that the cell boundaries304are substantially along the center lines of the dummy gate lines400, so that the dummy gate lines400of the standard cell Cell-C1and the standard cell Cell-C2are respectively divided into two half portions400aand400bby the cell boundaries204, wherein the half portion400ahas a half width Wa, the half portion400bhas a half width Wb, and the half width Wa and the half width Wb are the same. According to the above limitations, it should be understood that the dummy gate line space SC2and the dummy gate line space SC3may be the same, and the distances between the cell boundaries304the same. According to an embodiment of the present invention, the gate line width LC may be equal to the default gate line width L, the gate line width LA is equal to a sum of the default gate line width L and the first variable d1, and the gate line width LB is equal to a sum of the default gate line width L and the second variable d2. The width of the dummy gate line400(the sum of the half width Wa and the half width Wb) may be equal to the default gate line width L, the gate line width LC, the gate line width LA, or the gate line width LB. For example, the width of the dummy gate line400may be equal to the sum of the default gate line width L and the first variable d1, that is, equal to the gate line width LA. According to an embodiment of the present invention, in the step12of the method10, the default gate line width L for generating the gate lines of the standard cells may be the minimum gate line width in compliance with the design rule specification for the integrated circuit, the default gate line pitch P may be the minimum pitch that the process resolution may achieve when the default gate line width L is the minimum gate line width. For example, according to an embodiment of the present invention, the parameters set in the step12of the method10may include a default gate line width L of 16 nm, a default gate line pitch P of 96 nm, a first variable d1of 4 nm, and a second variable d2of 8 nm. Accordingly, the standard cells Cell-A1, Cell-A2, Cell-B1, Cell-B2, Cell-C1, and Cell-C2obtained after performing the step14and the step16may respectively include the dimensions as shown in Table-1. TABLE 1DefaultGateGateDummyDummyStandardgate linelinelinegate linegate lineHalfHalfCellpitchwidthspacespacespacewidthwidthCell-A1PLASA1SA2SA3WaWbCell-A296 nm20 nm76 nm76 nm76 nm10 nm10 nmCell-B1PLBSB1SB2SB3WaWbCell-B296 nm24 nm72 nm74 nm74 nm10 nm10 nmCell-C1PLCSC1SC2SC3WaWbCell-C296 nm16 nm80 nm78 nm78 nm10 nm10 nm The specific dimensions shown in Table-1 are for the purpose of understanding of the present invention, and should not be taken as limitations to the present invention. In other embodiments, the values of the default gate line width L, the default gate line pitch P, the first variable d1, and the second variable d2may be adjusted according to design needs. According to an embodiment of the present invention, the values of the default gate line width L, the default gate line pitch P, the first variable d1, and the second variable d2are all even numbers to obtain an all on-grid layout pattern. It is noteworthy that although the standard cells of the present invention have different gate line widths, all of the standard cells have the gate lines being arranged between the cell boundaries in such a way that the standard cells are divided into portions of the same width by the gate lines (more specifically, by the center line of the gate lines). Accordingly, the difference between the gate line spaces of any two of the standard cells is equal to the difference between gate line widths of the two standard cells. Furthermore, because the standard cells of the present invention have the same dummy gate lines, the difference between the dummy gate line spaces of any two of the standard cells is equal to ½ of the difference between gate line widths of the two standard cells. For example, please refer to standard cell Cell-C1and standard cell Cell-A1shown in Table-1. The gate line width LC of the standard cell Cell-C1is 16 nm, the gate line width LA of the standard cell Cell-A1is 20 nm, and the difference between the gate line width LC and the gate line width LA is 4 nm (the first variable d1). The dummy gate line space SC2of the standard cell Cell-C1is 78 nm, the dummy gate line space SA2of the standard cell Cell-A1is 76 nm, and the difference between the dummy gate line space SC2and the dummy gate line space SA2is 2 nm, which is ½ of the first variable d1. Please refer to standard cell Cell-C1and standard cell Cell-B1shown in Table-1. The gate line width LC of the standard cell Cell-C1is 16 nm, the gate line width LB of the standard cell Cell-A1is 24 nm, and the difference between the gate line width LC and the gate line width LB is 8 nm (the second variable d2). The dummy gate line space SC2of the standard cell Cell-C1is 78 nm, the dummy gate line space SB2of the standard cell Cell-B1is 74 nm, and the difference between the dummy gate line space SC2and the dummy gate line space SB2is 4 nm, which is ½ of the second variable d2. Please refer back toFIG.1. After obtaining the first standard cell and the second standard cell, step18of the method10is performed, including abutting the first standard cell and the second standard cell to produce an integrated circuit layout. According to an embodiment of the present invention, when the step16produce a first standard cell, a second standard cell, and a third standard cell, at least two of the first standard cell, the second standard cell, and the third standard cell may be used in step18to produce an integrated circuit layout. As previously illustrated, the standard cells of the present invention have the following features. First, different standard cells have the same default gate line pitch. Second, the cell widths of different standard cells are all integral multiples of the default gate line pitch. Third, the gate lines of each of the standard cells are equally spaced and arranged between the cell boundaries in a way that the cell width of each of the standard cells is divided into equal portions by the gate lines. Fourth, different standard cells have the same dummy gate lines, and the cell boundaries of each of the standard cells are along the center lines of the dummy gate lines, respectively. Based on the features of the standard cells, the layout of the integrated circuit obtained by abutting the standard cells may have the following features. First, when the cell boundaries of the standard cells abutting along the first direction D1are overlapped, the dummy gate lines of the standard cells on the overlapped cell boundaries may be completely overlapped with each other. Furthermore, the gate lines, dummy gate lines, and cell boundaries of the standard cells abutting along the second direction D2are aligned along the second direction D2. Additionally, when the active region patterns of the standard cells have the same active region width and the same active region pitch, the active region patterns of the standard cells may be aligned along the first direction D1. For the ease of understanding, the features of the layout of the integrated circuit of the present invention will be illustrated according to the embodiments shown inFIG.5,FIG.6,FIG.7andFIG.8, respectively. Please refer toFIG.5, which is a schematic plan view of an integrated circuit layout500according to an embodiment of the present invention. The integrated circuit layout500includes a plurality of standard cell Cell-C1and standard cell Cell-B1that are mixed and abutted along the first direction D1and the second direction D2. The standard cell Cell-C1and the standard cell Cell-B1abutting along the first direction D1have the cell boundaries304,204overlapped with each other and share a same dummy gate line400. The standard cell Cell-C1and the standard cell Cell-B1abutting along the second direction D2have the cell boundaries306,206overlapped with each other. Each standard cell Cell-C1has a plurality of gate lines302arranged along the first direction D1and between the cell boundaries304. The gate lines302of the standard cell Cell-C1have the gate line width LC and are distanced from each other by the default gate line pitch P (as shown in the upper portion ofFIG.4). Each standard cell Cell-B1has a plurality of gate lines202arranged along the first direction D1and between the cell boundaries204. The gate lines202of the standard cell Cell-B1have the gate line width LB and are distanced from each other by the default gate line pitch P (as shown in the upper portion ofFIG.3). The gate line width LC and the gate line width LB are different by a variable (for example, the second variable d2). The standard cell Cell-C1has a cell width WC1between the cell boundaries304, the standard cell Cell-B1has a cell width WB1between the cell boundaries204, and the cell width WC1and the cell width WB1are the same, and are integral multiples of the default gate line pitch P. In the embodiment shown inFIG.5, the gate lines302and the gate lines202are aligned, and the cell boundaries304and the cell boundaries204are aligned along the second direction D2. Please refer toFIG.6, which is a schematic plan view of an integrated circuit layout600according to an embodiment of the present invention. The integrated circuit layout600includes a plurality of standard cell Cell-C1and standard cell Cell-B2that are mixed and abutted along the first direction D1and the second direction D2. The standard cell Cell-C1and the standard cell Cell-B2abutting along the first direction D1have the cell boundaries304,204overlapped with each other and share a same dummy gate line400. The standard cell Cell-C1and the standard cell Cell-B2abutting along the second direction D2have the cell boundaries306,206overlapped with each other. Each standard cell Cell-C1has a plurality of gate lines302arranged along the first direction D1and between the cell boundaries304. The gate lines302of the standard cell Cell-C1have the gate line width LC and are distanced from each other by the default gate line pitch P (as shown in the upper portion ofFIG.4). Each standard cell Cell-B2has a plurality of gate lines202arranged along the first direction D1and between the cell boundaries204. The gate lines202of the standard cell Cell-B1have the gate line width LB and are distanced from each other by the default gate line pitch P (as shown in the lower portion ofFIG.3). The gate line width LC and the gate line width LB are different by a variable (for example, the second variable d2). The standard cell Cell-C1has a cell width WC1between the cell boundaries304, the standard cell Cell-B2has a cell width WB1between the cell boundaries204, and the cell width WC1and the cell width WB1are different, but both are integral multiples of the default gate line pitch P. In the embodiment shown inFIG.6, the gate lines202are aligned to a portion of the gate lines302, the cell boundaries204are respectively aligned to a gate line302or one of the cell boundaries304, and a portion of the dummy gate lines400are aligned to the gate lines202or the gate lines302along the second direction D2. Please refer toFIG.7, which is a schematic plan view of an integrated circuit layout700according to an embodiment of the present invention. Similar to embodiment shown inFIG.5, the integrated circuit layout700includes standard cells having the same cell width, the same default gate line pitch (such as the default gate line pitch P), but different gate line widths. The difference between the embodiments shown inFIG.5andFIG.7is that, the integrated circuit layout700includes three types of standard cells having different gate line widths, such as the standard cells Cell-C1, Cell-B1, and Cell-A1. As shown inFIG.7, the cell boundaries304,204and104of different standard cells are aligned along the second direction D2, The gate lines302,202,102, and the dummy gate lines400are also aligned along the second direction D2. Please refer toFIG.8, which is a schematic plan view of an integrated circuit layout800according to an embodiment of the present invention. Similar to embodiment shown inFIG.7, the integrated circuit layout800includes three types of standard cells having the same default gate line pitch (such as the default gate line pitch P) but different gate line widths. The difference between the embodiments shown inFIG.7andFIG.8is that, at least two of the three types of standard cells have different cell widths. For example, as shown inFIG.8, the integrated circuit layout800includes standard cells Cell-C1, Cell-B2, and Cell-A1, wherein a cell width WB2of the standard cells Cell-B2is different from the cell width WC1of the standard cells Cell-C1and the cell width WA1of the standard cells Cell-A1. Along the second direction D2, some of the cell boundaries304,204,104may be non-aligned, some of the gate lines302and the gate lines202may be aligned, some of the gate lines102and the gate lines202may be aligned, the cell boundaries204may be aligned to one of the gate lines302or one of the cell boundaries304, some of the dummy gate lines400may be aligned to the gate lines202, the gate lines302, and or the gate lines102. After obtaining the integrated circuit layout (after the step18of the method10), layout corrections such as optical proximity correction (OPC) may be performed to modify the layout patterns, and then the corrected layout patterns may be output from the computer system to a set of photomasks for fabricating the integrated circuit on a semiconductor substrate. For example, the patterns of the gate lines102,202,302may be used to form gate structures (for example, polysilicon gate structures or metal gate structures) on the semiconductor substrate. The patterns of the active region patterns108,208,308may be used to form the active regions (for example, fin-type active regions) on the semiconductor substrate. The dummy gate lines400may be used to form dummy gate structures on the semiconductor substrate, such as polysilicon dummy gate structures or dummy metal gate structures. It should be understood that the integrated circuit layout provided by the present invention may include other patterns such as contact patterns, dummy active region patterns, ion implanting patterns, which are not shown in the drawings for the sake of simplicity. In conclusion, the integrated circuit layout provided by the present invention includes standard cells having a same gate line pitch but different gate line widths. More important, the widths of the standard cells are integral multiples of the gate line pitch, and the gate lines are arranged along a row direction (the first direction D1) between the cell boundaries of the standard cells in a way that the cell widths of the standard cells may be divided into equal portions by the gate lines. In this way, when the standard cells are mixed arranged along the row direction (the first direction D1) and/or the column direction (the second direction D2) to form the integrated circuit layout, the gate lines and the dummy gate lines may be aligned along the column direction, allowing a higher degree of pattern regularity. Furthermore, by placing the dummy gate lines in a way that the cell boundaries are along the center lines of the dummy gate lines, the adjacent standard cells arranged along the row direction (the first direction D1) may share a same dummy gate line while maintaining the same gate line pitch without the need to adjust the patterns of the standard cells or unused layout areas generated between the standard cells, so that the layout area of the integrated circuit may be fully utilized. Overall, the layout of the integrated circuit provided by the present invention may have a neat and predictable pattern arrangement, which may reduce the burden of automated circuit layout process, and also save the time for layout corrections such as the optical proximity correction (OPC) performed after delivering the designed circuit layout to the foundry (tape-out). Furthermore, during the manufacturing process, the neat layout patterns of the present invention may provide a larger process window to form desired patterns on the wafer. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 30,247 |
11862623 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms including, for example, “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Field effect transistors (FETs) typically include active regions and gate structures over the active regions. Conductive features including, for example, contacts and vias, are formed on the FETs for providing electrical connection from a terminal (e.g., source/drain/gate) of an FET to, for example, terminal(s) of another FET. As semiconductor process technology continues to scale down, process variations have become more and more challenging in the manufacturing of integrated circuits (ICs). U.S. application Ser. No. 14/280,196, filed May 16, 2014, provides some embodiments about implementing gate vias in active regions of a semiconductor device. FIG.1Ais a top view of a schematic layout of a semiconductor structure101according to some embodiments of the present disclosure. The semiconductor structure101discussed in the present disclosure is given for illustrative purposes. In some embodiments, at least a portion of the semiconductor structure101illustrated inFIG.1A, and semiconductor structures as will be discussed with reference toFIG.2AandFIGS.4A-6, represents a standard cell. The standard cell, in some embodiments, refers to a pre-designed cell that has been laid out and stored in a circuit library that is in a form of a database. Moreover, the standard cell, in some embodiments, is stored in a tangible storage medium, including, for example, a hard drive. In the design of integrated circuits, the standard cell is retrieved from the circuit library, and is placed in a placement operation. The placement operation is performed, for example, using a computer, which runs the software for designing integrated circuits. The software includes a circuit layout tool, which has a function of placement and routing. In some embodiments, the semiconductor structure101, and the semiconductor structures as will be discussed with reference toFIG.2AandFIGS.4A-6, are implemented in a semiconductor device. In some other embodiments, the semiconductor structure101as shown inFIG.1A, and the semiconductor structures as will be discussed with reference toFIG.2AandFIGS.4A-6, are each an intermediate device fabricated during processing of an integrated circuit (IC) or a portion thereof. In some embodiments, the IC or the portion thereof includes static random access memory (SRAM) and/or other logic circuits, passive components including, for example, resistors, capacitors, and inductors, active components including, for example, p-type field effect transistors (PFET), n-type FET (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and/or combinations thereof. As illustrated inFIG.1A, the semiconductor structure101includes a first active region111and a second active region112that are formed on a substrate (not shown). The first active region111and the second active region112are spaced apart by a non-active region113. In some embodiments, the substrate is a silicon substrate. In some other embodiments, the substrate includes another elementary semiconductor including, for example, germanium; a compound semiconductor including, for example, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or the combinations thereof. In yet other embodiments, the substrate is a semiconductor on insulator (SOI). The types of the substrate discussed above are given for illustrative purposes. Various types of the substrate are within the contemplated scope of the present disclosure. In some embodiments, the first active region111and the second active region112are of the same type, for example, n-type or p-type. In some other embodiments, the first active region111and the second active region112are of different types, for example, one being n-type and the other being p-type. For illustration inFIG.1A, the semiconductor structure101further includes gate structures140-144and gate vias GV0-GV7. For simplicity of illustration, only the gate structures140-144and the gate vias GV0-GV7are shown inFIG.1A. Various numbers of the gate structures and the gate vias are within the contemplated scope of the present disclosure. The gate structures140-144are arranged on the first active region111, the second active region112and the non-active region113correspondingly, as shown inFIG.1A. For illustration, the gate structures140-144are arranged in parallel and extended longitudinally over the first active region111, the non-active region113, and the second active region112. The gate vias GV0-GV7are arranged on the gate structures140-144correspondingly, as shown inFIG.1A. In some embodiments, the gate vias GV0-GV7are electrically coupled with the gate structures140-144correspondingly. In some embodiments, at least one of the gate vias GV0-GV7is disposed above the first active region111, the second active region112, and/or the non-active region113. For illustration inFIG.1A, the gate vias GV0, GV1and GV7are disposed above the non-active region113; the gate vias GV2, GV4and GV6are disposed above the first active region111; and the gate vias GV3and GV5are disposed above the second active region112. In some embodiments, the gate structures140-144are formed of metal. In some other embodiments, the gate structures140-144are formed of non-metal conductive material including, for example, conductive polymeric material or grapheme material. In some embodiments, each one of the gate structures140,141,142,143and144includes an interfacial layer (not shown) and a polysilicon (or poly) layer (not shown) over the interfacial layer. In some embodiments, the gate structures140,141,142,143and144further include a gate dielectric layer (not shown) and a metal gate layer (not shown) disposed between the interfacial layer and the poly layer. In some embodiments, the gate structures140,141,142,143and144includes one or more metal layers in place of the poly layer. In various embodiments, the interfacial layer includes a dielectric material including, for example, silicon oxide (SiO2) or silicon oxynitride (SiON), and is able to be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. In some embodiments, the polysilicon layer is formed by suitable deposition processes including, for example, low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD). In some embodiments, the gate dielectric layer uses a high-k dielectric material including, for example, hafnium oxide (HfO2), Al2O3, lanthanide oxides, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, combinations thereof, or other suitable material, and the gate dielectric layer is formed by ALD and/or other suitable methods. The metal gate layer includes a p-type work function metal or an n-type work function metal, and is deposited by CVD, PVD, and/or other suitable process. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The one or more metal layers use aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), and/or other suitable materials; and are formed by CVD, PVD, plating, and/or other suitable processes. The formations and/or materials associated with the gate structures140-144are given for illustrative purposes. Various formations and/or materials associated with the gate structures140-144are within the contemplated scope of the present disclosure. As illustrated inFIG.1A, source/drain contacts130are disposed over the first active region111and the second active region112correspondingly. In some embodiments, the source/drain contacts130are spaced apart from the gate structures140-144, for illustration, by spacers152and spacer134shown inFIG.1B. For illustration inFIG.1A, between adjacent two of the gate structures140-144, one source/drain contact130over the first active region111and one source/drain contact130over the second active region112are arranged. In some embodiments, the semiconductor structure101further includes source/drain vias SDV. The source/drain vias SDV are electrically coupled with the source/drain contacts130. The source/drain vias SDV are arranged above the first active region111and the second active region112correspondingly, as shown inFIG.1A. In some embodiments, the gate vias GV0-GV7and the source/drain vias SDV are coupled to vias (not shown) in another portion of the semiconductor structure101. In some other embodiments, the gate vias GV0-GV7and the source/drain vias SDV are coupled through conductive features (not shown) in another layer of the semiconductor structure101, including, for example, metal interconnects, in order to form a semiconductor device. For simplicity of illustration, only a few of designations “SDV” are labeled inFIG.1A, and the like elements shown inFIG.1Aare also referred to as the source/drain vias SDV. Moreover, the term “source/drain” discussed above refers to a region that may be a source region or a drain region. FIG.1Bis a cross sectional view, along the “A-A” line, of the semiconductor structure101inFIG.1A, according to some embodiments of the present disclosure. With respect to the embodiments ofFIG.1A, like elements inFIG.1Bare designated with the same reference numbers for ease of understanding. With reference toFIG.1AandFIG.1B, in some embodiments, spacers152are formed around the gate structures140-144. For illustration inFIG.1B, the spacers152are formed around the gate structures141-143, and the spacers134are formed around the source/drain contacts130. The spacers152and the spacers134are disposed between the gate structures141-143and the corresponding source/drain contacts130. In some embodiments, the spacers152include dielectric materials including, for example, silicon oxide, silicon nitride, silicon oxynitride, other dielectric material, and/or combinations thereof. In some embodiments, gate opens153are disposed, for illustration inFIG.1B, above the gate structures141and143. In some embodiments, the gate opens153are intermediate products in order to form openings on the gate structures141-143. After the gate open153are removed, the gate structures141-143are able to be exposed. For illustration inFIG.1B, a gate open above the gate structure142, which is not shown inFIG.1B, is etched and removed, in order to receive the gate via GV2. In some embodiments, the gate opens153are formed of metal including, for example, aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), combinations thereof, or other suitable material. In some embodiments, the gate opens153are also referred to as “self-aligned contacts (SAC)” and are formed by a self-aligned formation process. The layout of the semiconductor structure101shown inFIG.1Aillustrates distributions of gates, sources and drains of transistors. Each of the transistors is formed with two source/drain contacts130and one corresponding gate structure, of the gate structure140-144, between the two source/drain contacts130. As illustrated inFIG.1B, there are source/drain regions131formed, for illustration, in corresponding portions of the first active region111inFIG.1B. The source/drain contacts130are disposed above the source/drain regions131. Correspondingly, there are also source/drain regions131formed in the second active region112, and for simplicity of illustration, they are not illustrated in figures. In some embodiments, as illustrated inFIG.1B, there are lightly doped diffusion (LDD) regions132formed, for illustration, around the source/drain regions131and in corresponding portions of the first active region111inFIG.1B. Referring toFIG.1B, the semiconductor structure101further includes a contact protection layer154over the source/drain contacts130in some embodiments. The contact protection layer154is formed to protect the source/drain contacts130from being accidentally coupled to, for illustration, the gate via GV2labeled inFIG.1B, during manufacturing processes. In some embodiments, the contact protection layer154includes a dielectric material. In various embodiments, the contact protection layer154is formed of titanium oxide (TiO2), silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN3), combinations thereof, or other suitable material. In some embodiments, a thickness of the contact protection layer154is different from a height of at least one of the gate structures140-144. For illustration inFIG.1B, the contact protection layer154is formed to have a thickness “H2,” and each one of the gate structures140-144has a height “H1.” In some embodiments, the thickness H2is at least 0.2 times the height H1, in order to ensure the electrically dielectric function. In some other embodiments, the thickness H2is no more than 1.7 times the height H1, in order to prevent from occupying too much space, and/or to prevent from an increasing delay time resulted from a high capacitance induced by the thickness H2. In alternative embodiments, the thickness H2of the contact protection layer154is about 0.2 to about 1.7 times the height H1of the gate structures140-144. In further embodiments, the thickness H2is about 0.2 to about 1.5 times the height H1. For illustration inFIG.1B, the semiconductor structure101further includes an inter-layer dielectric (ILD) layer150in some embodiments. The gate via GV2is formed in an opening through the ILD layer150. In such configurations, the gate via GV2provides connectivity between the gate structure142and other terminals of the semiconductor structure101. In some embodiments, the ILD layer150includes dielectric materials, including, for example, silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN3), and/or other suitable dielectric materials. In some embodiments, the semiconductor structure101further includes a barrier layer151. For illustration inFIG.1B, the barrier layer151is formed on sidewalls of the opening in which the gate via GV2is disposed, as discussed above. The barrier layer151is formed between the gate via GV2and the ILD layer150, for preventing the material of the gate via GV2from diffusing into the ILD layer150. In some embodiments, a local interconnect LIC is arranged over the non-active region113, between adjacent two of the gate structures140-144. For illustration inFIG.1A, the local interconnect LIC is arranged between the gate structures142and143. The local interconnect LIC is electrically coupled with two opposite corresponding source/drain contacts130that are separately disposed over the first active region111and the second active region112, as illustrated inFIG.1A. In some embodiments, the local interconnect LIC is formed by extending the corresponding source/drain contacts130as discussed above, in a longitudinal direction. For illustration inFIG.1A, the corresponding source/drain contact130disposed over the first active region111is extended in a longitudinal direction toward the second active region112, to form the local interconnect LIC over the non-active region113. Alternatively, the corresponding source/drain contact130disposed over the second active region112is extended in a longitudinal direction toward the first active region111, to form the local interconnect LIC over the non-active region113. Alternatively stated, the source/drain contacts130disposed over the corresponding first active region111and the corresponding second active region112are coupled to each other. In some embodiments, the local interconnect LIC is formed at a gap GP1inFIG.1Ato interconnect the source/drain contacts130over the corresponding first active region111and the corresponding second active region112. For illustration inFIG.1A, the gap GP1is located between the gate structures142and143above the non-active region113. There is no gate via disposed on gate structures142and143above the non-active region113, such that the local interconnect LIC disposed at the gap GP1is not adjacent to any gate via on neighboring gate structures142and143. FIG.2Ais a top view of a schematic layout of a semiconductor structure102according to some other embodiments of the present disclosure.FIG.2Bis a cross sectional view, along the “B-B” line, of the semiconductor structure102inFIG.2A, according to some embodiments of the present disclosure. With respect to the embodiments ofFIG.1AandFIG.1B, like elements inFIG.2AandFIG.2Bare designated with the same reference numbers for ease of understanding. The semiconductor structure102discussed in the present disclosure is given for illustrative purposes. Compared to the semiconductor structure101inFIG.1A, in some embodiments, the semiconductor structure102inFIG.2Afurther includes fin structures including, for illustration, fin structures FIN1, FIN2, FIN3and FIN4, without the first active region111and the second active region112. InFIG.2A, for simplicity of illustration, the fin structures FIN1, FIN2, FIN3and FIN4are shown inFIG.2A, and various numbers of fin structures implemented in the semiconductor structure102are within the contemplated scope of the present disclosure. In some embodiments, at least one of the fin structures FIN1, FIN2, FIN3and FIN4is formed of materials including, for example, silicon, silicon-germanium, and the like. Various materials to form the fin structures FIN1, FIN2, FIN3and FIN4are within the contemplated scope of the present disclosure. For illustration inFIG.2AandFIG.2B, the fin structure FIN2under the gate structure141is extended from where the gate structure140is disposed to where the gate structure142is disposed. The gate structure141and the source/drain contacts130A and130B are arranged to implement a Fin Field Effect Transistor (FinFET) with the fin structure FIN2. For corresponding illustration inFIG.2B, the fin structure FIN2is disposed on a substrate114. A Shallow Trench Isolation (STI) layer160is also disposed on the substrate114and located around the fin structure FIN2. An epitaxial source/drain layer161is disposed between the source/drain contact130A and the fin structure FIN2. Another epitaxial source/drain layer162is disposed between the source/drain contact130B and the fin structure FIN2. In some embodiments, the region for accommodating the fin structure FIN2is regarded as an active region. Correspondingly, regions for accommodating the fin structures FIN1, FIN3and FIN4are regarded as active regions. For corresponding illustration inFIG.2A, a non-active region113is located at an area where none of the fin structures FIN1-FIN4is disposed. In some embodiments, the source/drain contacts130,130A-130H are not extended over the non-active region113, as illustrated inFIG.2A. For corresponding illustration inFIG.2A, the fin structure FIN1under the gate structure142is extended from where the gate structure141is disposed to where the gate structure143is disposed. The gate structure142and the source/drain contacts130B and130F are arranged to implement a Fin Field Effect Transistor (FinFET) with the fin structure FIN1. The fin structure FIN3inFIG.2Aunder the gate structure141is extended from where the gate structure140is disposed to where the gate structure142is disposed. The gate structure141and the source/drain contacts130G and130H are arranged to implement another FinFET with the fin structure FIN3. The fin structure FIN4inFIG.2Aunder the gate structure143is extended from where the gate structure142is disposed to where the gate structure144is disposed. The gate structure143and the source/drain contacts130D and130E are arranged to implement another FinFET with the fin structure FIN4. In some embodiments, a local interconnect LIC is arranged over the non-active region113inFIG.2A. For illustration inFIG.2A, the local interconnect LIC is arranged between the gate structures142and143, to connect the source/drain contact130F and the source/drain contact130D, which are located on opposite sides of the non-active region113. The devices, in which the semiconductor structures discussed in the present disclosure are implemented, are given for illustrative purposes. Various devices, in which the semiconductor structures discussed in the present disclosure are implemented, are within the contemplated scope of the present disclosure. For example, the semiconductor structures discussed in the present disclosure are able to be implemented in planar FETs, three-dimensional devices, multi-gate devices including, for example, double gate FETs, FinFETs, tri-gate FETs, omega FETs, Gate-All-Around (GAA) devices, and vertical GAA devices, and the like. In various embodiments, some guidelines are provided in following paragraphs of the present disclosure for demonstrating when and/or where to arrange or form the local interconnect LIC in the semiconductor structure101inFIG.1Aand/or the semiconductor structure102inFIG.2A. FIG.3is a schematic diagram illustrating a cross-coupling structure CPS of four transistors T1, T2, T3and T4. In some embodiments, the cross-coupling structure CPS shown inFIG.3is utilized in some electronic circuits including, for example, a multiplexer, a memory, a decoder or any equivalent logic unit. As shown inFIG.3, the source/drain contacts of the transistors T1and T2are coupled to a node ND1, and the source/drain contacts of the transistors T3and T4are coupled to a node ND2. The two nodes ND1and ND2are coupled to each other, for illustration, by the local interconnect LIC as discussed above. To implement the cross-coupling structure CPS discussed above, whether to arrange the local interconnect LIC, for illustration inFIG.1AandFIG.2A, is determined. In some embodiments, a first guideline is provided to determine whether to arrange the local interconnect LIC. When the first guideline is followed, the local interconnect LIC, for illustration inFIG.1A, is able to be arranged, in order to realize the cross-coupling structure CPS inFIG.3. The first guideline is discussed below with reference to embodiments ofFIGS.4A-4E. FIGS.4A-4Eare each a top view of a schematic layout of a semiconductor structure corresponding to a portion of the semiconductor structure101inFIG.1A, in accordance with various embodiments of the present disclosure. With respect to the embodiments ofFIG.1AandFIG.3, like elements inFIGS.4A-4Eare designated with the same reference numbers for ease of understanding.FIGS.4A-4Eillustrate the embodiments in which at least one local interconnect is arranged when the first guideline is followed. As shown inFIG.4A, the gate vias GV2and GV4are arranged above the first active region111, and the gate vias GV3and GV5are arranged above the second active region112. The gate vias GV2and GV3are coupled with the gate structure142. The gate vias GV4and GV5are coupled with the gate structure143. The local interconnect LIC1is disposed in a region which is defined by, for illustration inFIG.4A, the first active region111, the second active region112, and the gate structures142and143. For illustration inFIG.4A, the gate vias GV2-GV5are not aligned to each other. The gate via GV2and the gate via GV3have a pitch Pa therebetween. The gate via GV4and the gate via GV5have a pitch Pb therebetween. In some embodiments, the pitch Pa is equal to the pitch Pb. In various embodiments, the pitch Pa is in a range between about 0.7*Pb and about 1.3*Pb, which, in some embodiments, indicates that the pitch Pa is substantially equal to the pitch Pb. Regarding the first guideline, there are three conditions to be followed in the first guideline. When three conditions are satisfied, the local interconnect LIC1is allowed to be formed. The first condition of the first guideline is that there is at least one gate via disposed outside the non-active region113. For illustration ofFIG.4A, the gate vias GV2-GV5are disposed outside the non-active region113. The second condition of the first guideline is that there is no gate via above the non-active region113around where the local interconnect LIC1to be formed. For illustration ofFIG.4A, there is no gate via on the gate structure142/143above the non-active region113. The third condition of the first guideline is that the pitches between gate vias on opposite sides of the local interconnect LIC1are substantially the same. For illustration ofFIG.4A, the pitch Pa between the gate via GV2and the gate via GV3is substantially the same to the pitch Pb between the gate via GV4and the gate via GV5. Aforementioned distributions and configurations of the gate vias GV2-GV5, and the relationship between the pitches Pa and Pb, are regarded as the first guideline in some embodiments. When the first guideline is followed, the local interconnect LIC1labeled inFIG.4Ais determined to be arranged in the region as discussed above, to connect the corresponding source/drain contacts130above the first active region111and the second active region112. In some embodiments, a separation spacer CPO1is arranged to isolate electronic signals transmitted through different gate vias. For illustration inFIG.4A, the separation spacer CPO1is disposed on the gate structure142, and is disposed between the gate vias GV2and GV3. With the separation spacer CPO1, the electronic signal transmitted through the gate via GV2is isolated from the electronic signal transmitted through the gate via GV3. In some embodiments, a separation spacer CPO2is also arranged to isolate electronic signals transmitted through different gate vias. For illustration, the separation spacer CPO2is disposed on the gate structure143, and is disposed between the gate vias GV4and GV5. With the separation spacer CPO2, the electronic signal transmitted through the gate via GV4is isolated from the electronic signal transmitted through the gate via GV5. In some embodiments, at least one of the separation spacers CPO1and CPO2is formed of a dielectric material. In some embodiments, the separation spacers CPO1and CPO2are poly cut layers, which are intermediate products during a semiconductor manufacturing procedure, and not existed in final products of the semiconductor circuit. A distance between the gate via GV4and the separation spacer CPO2is different from a distance between the gate via GV5and the separation spacer CPO2. As illustrated inFIG.4A, a cross-coupling structure CPS, corresponding to the cross-coupling structure CPS inFIG.3, is formed. In some embodiments, the cross-coupling structure CPS including the transistors T1-T4inFIG.3is implemented by the embodiments ofFIG.4A. In various embodiments, the cross-coupling structure CPS including the transistors T1-T4inFIG.3is also implemented by the embodiments illustrated below with reference toFIGS.4B-4E. Configurations of the transistors T1-T4are discussed below for illustration ofFIG.4A. The transistor T1includes two source/drain contacts130, the gate structure142and the gate via GV2, above the first active region111. The transistor T2includes two source/drain contacts130, the gate structure143and the gate via GV4, above the first active region111. The transistor T3includes two source/drain contacts130, the gate structure142and the gate via GV3, above the second active region112. The transistor T4includes two source/drain contacts130, the gate structure143and the gate via GV5, above the second active region112. As illustrated inFIG.4A, the transistors T1and T2share one source/drain contact130, which corresponds to the node ND1inFIG.3, and the transistors T3and T4share one source/drain contact130, which corresponds to the node ND2inFIG.3. The contacts130of the transistors T1-T4, in some embodiments, have locations that are staggered along a direction in which the first active region111extends. For connecting the nodes ND1and ND2as illustrated inFIG.3, the local interconnect LIC1inFIG.4Ais arranged as discussed above. For isolating gates of the transistors T1and T3and gates of the transistors T2and T4, the separation spacers CPO1and CPO2inFIG.4Aare arranged as discussed above. In some embodiments, the separation spacer CPO1, the separation spacer CPO2and the local interconnect LIC1inFIG.4Aare arranged within a width WD indicating three contacted poly pitches (3-CPP) to construct the cross-coupling structure CPS. As shown inFIG.4B, the configurations of the gate vias GV2-GV5, and the relationship between the pitches Pa and Pb, are similar to those illustrated inFIG.4A. Based on the discussion above, the first guideline is also followed. Compared to the embodiments inFIG.4A, the locations of the gate vias GV2-GV5inFIG.4Bare different from the locations of the gate vias GV2-GV5inFIG.4A. For illustration, the locations of the gate vias GV2and GV3are shifted toward the top ofFIG.4B, and the locations of the gate vias GV4and GV5are shifted toward the bottom ofFIG.4B, compared to those illustrated inFIG.4A. InFIG.4B, the pitch Pa between the gate vias GV2and GV3is still equal to the pitch Pb between the gate vias GV4and GV5in some embodiments, or is still substantially equal to the pitch Pb in some other embodiments as discussed above. By following the first guideline, the local interconnect LIC1is also able to be arranged in the corresponding region which is defined by, for illustration inFIG.4B, the first active region111, the second active region112, and the gate structures142and143, to connect the corresponding source/drain contacts130in the first active region111and the second active region112. As shown inFIG.4C, the distributions and configurations of the gate vias GV2-GV5, and the relationship between the pitches Pa and Pb, are similar to those illustrated inFIG.4A. Based on the discussion above, the first guideline is also followed. Compared to the embodiments inFIG.4A, an additional local interconnect LIC2inFIG.4Cis arranged. For illustration, the local interconnect LIC2is disposed in a region which is defined by, for illustration, the first active region111, the second active region112, and the gate structures141and142. The local interconnect LIC2is arranged to connect the corresponding source/drain contacts130above the first active region111sand the second active region112. As shown inFIG.4D, the distributions and configurations of the gate vias GV2-GV5, and the relationship between the pitches Pa and Pb, are similar to those illustrated inFIG.4C. Based on the discussion above, the first guideline is also followed. Compared to the embodiments inFIG.4C, without the local interconnect LIC2, an additional local interconnect LIC3inFIG.4Dis arranged. For illustration, the local interconnect LIC3is disposed in a region which is defined by, the first active region111, the second active region112, and the gate structures143and144. The local interconnect LIC3is arranged to connect the corresponding source/drain contacts130above the first active region111and the second active region112. As shown inFIG.4E, the distributions and configurations of the gate vias GV2-GV5, and the relationship between the pitches Pa and Pb, are similar to those illustrated inFIG.4D. Based on the discussion above, the first guideline is also followed. Compared to the embodiments inFIG.4CandFIG.4D, the embodiments inFIG.4Eincludes the local interconnect LIC2as illustrated inFIG.4C, and also includes the local interconnect LIC3as illustrated inFIG.4D. Based on the discussion above, the embodiments ofFIGS.4A-4Edemonstrate the first guideline, which is related to arranging the layout corresponding to the cross-coupling structure CPS inFIG.3. FIG.5is a top view of a schematic layout of a semiconductor structure103in accordance with some other embodiments of the present disclosure. With respect to the embodiments ofFIG.1A, like elements inFIG.5are designated with the same reference numbers for ease of understanding. For illustration inFIG.5, source/drain contacts130aand130care arranged above the first active region111, and source/drain contacts130band130dare arranged above the second active region112. The gate structures141and142are both arranged above the first active region111, the second active region112and the non-active region113. Gate vias GV8and GV9are disposed above the first active region111. InFIG.5, the source/drain contacts130aand130cabove the first active region111are spaced apart from the source/drain contacts130band130dabove the second active region112, by the non-active region113. In some embodiments, the source/drain contact130ais coupled through a connector171to a high-level interconnect181, and the source/drain contact130bis coupled through a connector172to the high-level interconnect181. Accordingly, the source/drain contacts130aand130bare coupled with each other through the connector171, the high-level interconnect181and the connector172. In some embodiments, the high-level interconnect181is formed in a metal one (M1) layer. In some embodiments, the connectors171and172are each a contact, and formed in a layer different from the metal one (M1) layer. In some embodiments, each of the connectors171and172is a via which is disposed between source/drain contacts130aand130b, respectively, and the high-level interconnect181, which is a metal one (M1) layer. As illustrated inFIG.5, in some other embodiments, the source/drain contact130cis coupled through a connector173to a high-level interconnect182, and the source/drain contact130dis coupled through a connector174to the high-level interconnect182. Accordingly, the source/drain contacts130cand130dare coupled with each other through the connector173, the high-level interconnect182and the connector174. In some embodiments, the high-level interconnect182is formed in the metal one (M1) layer. In some embodiments, the connectors173and174are each a contact, and formed in a layer different from the metal one (M1) layer. FIG.6is a top view of a portion of a schematic layout of a semiconductor structure104in accordance with alternative embodiments of the present disclosure. With respect to the embodiments ofFIG.5, like elements inFIG.6are designated with the same reference numbers for ease of understanding. In some embodiments, a second guideline is provided to determine whether to arrange a local interconnect LIC4as labeled inFIG.6.FIG.6illustrates some embodiments in which the local interconnect LIC4is arranged when the second guideline is followed. Compared to the embodiments ofFIG.5, the embodiments inFIG.6are constructed to have the local interconnect LIC4, without the connectors173and174. In some embodiments, the gate via GV9and the gate structure142inFIG.6are configured to receive a fixed voltage including, for example, a high system voltage VDD, a low system voltage VSS, a ground voltage GND, or the like. Aforementioned distribution of the gate via GV9, and the configuration of the gate via GV9to receive the fixed voltage, follow the second guideline to implement, for illustration, the local interconnect LIC4, to connect the source/drain contacts130cand130d. By following the second guideline, the local interconnect LIC4is determined to be arranged in a region which is defined by, for illustration inFIG.6, the first active region111, the second active region112, and the gate structures141and142. The distributions and configurations of the layouts illustrated inFIG.6are given for illustrative purposes. Various distributions and configurations of the layouts inFIG.6are within the contemplated scope of the present disclosure. For example, in various embodiments, the embodiments inFIG.6are further constructed without the gate via GV9. In such embodiments, the gate structure142is configured to be floated, as a floating gate. The distribution of the gate via GV8, and the configuration of the gate structure142as a floating gate, also follow the second guideline to implement the local interconnect LIC4in the region as discussed above. With the local interconnect LIC4, fewer connectors are required for the semiconductor structure104inFIG.6, compared to the semiconductor structure103using the layout inFIG.5. In some embodiments, the “floated” is also referred to as having a floating voltage, or being not connected electrically to another non-floated conductor. In some embodiments, a third guideline is further provided to determine whether to arrange the local interconnect LIC4inFIG.6. In some embodiments, for the third guideline, if at least one of the source/drain contacts130a-130dinFIG.6is an output drain of a standard cell, the local interconnect LIC4is banned and/or not arranged. In some embodiments, the standard cell includes, for example, an inverter cell, a NAND gate logic cell, a NOR gate logic cell, or any equivalent cell. In some approaches, when a local interconnect is formed around an output drain of a standard cell, the parasitic capacitance of the output drain increases. With the increased parasitic capacitance, a speed of accessing the output drain is reduced. Moreover, when there is an output drain, an access pin coupled to the output drain is required in related approaches, thus increasing the size of the entire semiconductor structure with the local interconnect. Based on the discussion above, under the third guideline, the local interconnect LIC4is banned and/or not arranged if at least one of the source/drain contacts130a-130dinFIG.6is an output drain of a standard cell. FIG.7is a flow chart illustrating a method700for design of layouts of semiconductor structures, according to some embodiments of the present disclosure. For illustration, the method700is applied for design of the layouts of the semiconductor structures inFIG.1A,FIG.2A, andFIGS.4A-6. In some embodiments, the method700is applied for verifying and/or adjusting layouts of semiconductor structures. In some embodiments, the method700is performed, for example, using a computer (not shown), which runs the software for designing integrated circuits. The software includes a circuit layout tool, which has a function of placement and routing. In some embodiments, the computer includes a tangible storage medium (not shown), including, for example, a hard drive, for storing a standard cell represented by at least a portion of the semiconductor structures as discussed above. In some embodiments, the computer includes a processing unit (not shown) for retrieving the standard cell from the tangible storage medium, and for performing layout and/or placement associated with the standard cell in a placement operation. For illustration inFIG.7, the method700is performed to determine if the local interconnect LIC as discussed above is to be arranged in the semiconductor structure. Accordingly, the method700is discussed below on the basis of no local interconnect LIC in the semiconductor structure. The method700is given for illustrative purposes. Various operations of the method700performed, for example, when the local interconnect LIC has been arranged in the semiconductor structure, are within the contemplated scope of the present disclosure. In operation S701, a layout of a semiconductor structure is inputted, for illustration, into the computer as discussed above. For illustration inFIG.1A, the layout of the semiconductor structure101is inputted to be verified, in order to determine if the local interconnect LIC is to be arranged in the semiconductor structure101. In operation S702, whether or not there is at least one gate via disposed above the first active region or the second active region is determined. For illustration inFIG.1A, whether or not there is at least one of the gate vias GV0-GV7disposed above the first active region111or the second active region112is determined. If not, the operation of the method700is terminated, because, without gate via, the guideline associated with distributions and configurations of gate vias does not have to be determined or followed. On the other hand, if so, operation S703is then performed. In operation S703, whether or not the layout of the semiconductor structure follows at least one of the first guideline and the second guideline as discussed above is determined. If so, the operation of the method700is terminated, because, when the layout follows at least one of the first guideline and the second guideline, operation S704is then performed. On the other hand, if not, the adjustment and/or re-design of the layout do not have to be performed. In operation S704, the layout is adjusted and/or re-designed by adding at least one local interconnect as discussed above, over, for illustration, the non-active region113inFIG.1A. With the local interconnect, the source/drain contacts on different active regions are connected across the non-active region, without implementing high-level connectors. The size of the semiconductor structure is able to be reduced, because it is not necessary to implement high-level connectors to interconnect the source/drain contacts on different active regions. For illustration inFIG.1A, if the layout of the semiconductor structure101follows the first guideline, the layout of the semiconductor structure101is adjusted and/or re-designed by adding the local interconnect LIC. For another illustration inFIG.6, if the layout of the semiconductor structure104follows the second guideline, the layout of the semiconductor structure104is adjusted and/or re-designed by adding the local interconnect LIC4. In some embodiments, in operation S703, whether or not the layout of the semiconductor structure follows both of the second guideline and the third guideline as discussed above is further determined. If so, the operation of the method700is terminated, because, as discussed above, when the layout follows the second guideline and the third guideline, the local interconnect is banned and/or not to be arranged. Accordingly, operation S704does not have to be performed. In some embodiments, a method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region. Also disclosed is a method is disclosed, including the following operations: arranging a plurality of gate structures above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure, wherein the first and second active regions are spaced apart by the non-active region; arranging a plurality of contacts above the first and second active regions; arranging a first separation spacer between the plurality of contacts; arranging at least one first gate via above the first active region or the second active region, wherein the at least one first gate via is electrically coupled with at least one of the plurality of gate structures; and selectively arranging at least one local interconnect over the non-active region, to couple a first contact of the plurality of contacts above the first active region to a second contact of the plurality of contacts above the second active region. Also disclosed is a method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed above the first active region and a second contact disposed above the second active region, wherein the first separation spacer overlaps the first local interconnect and has a width larger than a width of the first gate structure. The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 47,185 |
11862624 | DETAILED DESCRIPTION OF THE EMBODIMENTS FIG.1is a block diagram of an integrated circuit (IC) device10according to example embodiments. Referring toFIG.1, the IC device10may include a memory cell array20and a peripheral circuit30. The memory cell array20may include a plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, . . . , and BLKn may be connected to the peripheral circuit30through bit lines BL, word lines WL, string selection lines SSL, and a ground selection line GSL. The peripheral circuit30may include a row decoder32, a page buffer34, a data input/output (I/O) circuit36, a control logic38, and a common source line (CSL) driver39. Although not shown inFIG.1, the peripheral circuit30may further include various circuits, such as a voltage generation circuit configured to generate various voltages required for operations of the IC device10, an error correction circuit configured to correct errors in data read from the memory cell array20, and an I/O interface. The memory cell array20may be connected to the page buffer34through the bit lines BL and connected to the row decoder32through the word lines WL, the string selection lines SSL, and the ground selection line GSL. In the memory cell array20, each of the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn may be a flash memory cell. The memory cell array20may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include a plurality of NAND strings, each of which includes a plurality of memory cells respectively connected to a plurality of word lines WL stacked in a vertical direction. The peripheral circuit30may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the IC device10and transmit and receive data DATA to and from a device located outside the IC device10. The row decoder32may select at least one of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn in response to an address ADDR received from the outside and select a word line WL, a string selection line SSL, and a ground selection line GSL of the selected memory cell block. The row decoder32may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block. The page buffer34may be connected to the memory cell array20through the bit line BL. During a program (i.e., write) operation, the page buffer34may operate as a write driver and apply a voltage corresponding to data DATA to be stored in the memory cell array20to the bit line BL. During a read operation, the page buffer34may operate as a sense amplifier and sense the data DATA stored in the memory cell array20. The page buffer34may operate in response to a control signal PCTL provided from the control logic38. The data I/O circuit36may be connected to page buffer34through data lines DLs. In the program operation, the data I/O circuit36may receive data DATA from a memory controller (not shown) and provide program data DATA to the page buffer34based on a column address C_ADDR provided from the control logic38. In the read operation, the data I/O circuit36may provide read data DATA, which is stored in the page buffer34, to the memory controller based on the column address C_ADDR provided from the control logic38. The data I/O circuit36may transmit an input address or instruction to the control logic38or the row decoder32. The peripheral circuit30may further include an electrostatic discharge (ESD) circuit and a pull-up/pull-down driver. The control logic38may receive the command CMD and the control signal CTRL from the memory controller. The control logic38may provide a row address R ADDR to the row decoder32and provide a column address C_ADDR to the data I/O circuit36. The control logic38may generate various internal control signals used in the IC device10, in response to the control signal CTRL. For example, the control logic38may adjust voltage levels of voltages provided to the word line WL and the bit line BL during a memory operation, such as a program operation or an erase operation. The CSL driver39may be connected to the memory cell array20through the common source line CSL. The CSL driver39may apply a common source voltage (e.g., a power supply voltage) or a ground voltage to the common source line CSL via the control of the control logic38. In example embodiments, the CSL driver39may be under the memory cell array20. The CSL driver39may vertically overlap at least a portion of the memory cell array20. Advantageously, to prevent charges capable of generating a large current (e.g., due to arcing) from being accumulated in a conductive plate (e.g., a conductive plate110shown inFIG.11), the peripheral circuit30may further include an antenna diode (e.g. an antenna diode D40shown inFIG.11), which may bypass the charges to a lower substrate (e.g., a lower substrate52shown inFIG.11) through a wiring structure (e.g., a bypass wiring structure P81shown inFIG.11or a bypass wiring structure P280shown inFIG.12) under the memory cell array20. As will be understood by those skilled in the art, arcing refers to a breakdown phenomenon whereby an electric arc occurs between conductors, which are spaced apart from each other by an insulator, due to a potential difference caused between the conductors. For example, when a process using plasma is performed after a conductive plate (refer to110inFIG.17) is formed, charges may be accumulated due to plasma in a plate piece, which is a portion of the conductive plate110. Here, a plasma discharge path may be absent between the plate piece and the lower substrate52. The charges accumulated in the plate piece may cause an arc discharge, which can degrade the peripheral circuit30, such as the CSL driver39. Fortunately, the antenna diode D40shown inFIG.11may provide a plasma discharge path between the plate piece and the lower substrate52and prevent arcing from occurring. FIG.2is a schematic perspective view of an IC device10according to example embodiments. Referring toFIG.2, the IC device10may include a cell array structure CAS and a peripheral circuit structure PCS, which overlap each other in a vertical direction (Z direction). The cell array structure CAS may include the memory cell array20described with reference toFIG.1. The peripheral circuit structure PCS may include the peripheral circuit30described with reference toFIG.1. The cell array structure CAS may include a plurality of tiles24. Each of the plurality of tiles24may include a plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn. Each of the plurality of memory cell block BLK1, BLK2, BLKn may include memory cells arranged three-dimensionally. In some embodiments, two tiles24may constitute one mat, without being limited thereto. The memory cell array20described with reference toFIG.1may include a plurality of mats, for example, four mats, without being limited thereto. FIG.3is an equivalent circuit diagram of a memory cell array MCA of an IC device, according to example embodiments.FIG.3is an equivalent circuit diagram of an example of a vertical NAND (VNAND) flash memory device having a vertical channel structure. Each of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn shown inFIG.2may include a memory cell array MCA having a circuit configuration shown inFIG.3. Referring now toFIG.3, the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (or BL1, BL2, . . . , and BLm), a plurality of word lines WL (or WL1, WL2, . . . , WLn−1, and WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. A plurality of memory cell strings MS may be formed between the plurality of bit lines BL and the common source line CSL. AlthoughFIG.3illustrates a case in which each of the plurality of memory cell strings MS includes two string selection lines SSL, the inventive concept is not limited thereto. For instance, each of the plurality of memory cell strings MS may include one string selection line SSL. Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn. A drain region of the string selection transistor SST may be connected to the bit line BL, and a source region of the ground selection transistor GST may be connected to the common source line CSL. The common source line CSL may be a region to which source regions of a plurality of ground selection transistors GST are connected in common. The string selection transistor SST may be connected to the string selection line SSL, and the ground selection transistor GST may be connected to the ground selection line GSL. The plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn may be respectively connected to the plurality of word lines WL. FIG.4is a schematic plan view of an IC device1000according to example embodiments. Referring toFIG.4, the IC device1000may include a cell array structure CAS on a conductive plate110. The conductive plate110and the cell array structure CAS may constitute a memory cell array20of the IC device10shown inFIG.1. The conductive plate110may serve as the common source line CSL shown inFIG.3. The conductive plate110may support the cell array structure CAS. As used herein, the term “conductive plate” may also be referred to as a “plate CSL,” and the “conductive plate” and may be synonymous with the “plate CSL.” The cell array structure CAS may include a plurality of memory cell blocks BLK. A plurality of memory cell blocks BLK, which constitute one tile24in the cell array structure CAS, may include the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn shown inFIG.2. In example embodiments, the conductive plate110may provide a path through which a common source voltage is transmitted to the cell array structure CAS. The IC device1000may include a peripheral circuit structure (refer to PCS inFIG.2) under the cell array structure CAS. The peripheral circuit structure PCS may include the peripheral circuit30described with reference toFIG.1. The cell array structure CAS may overlap the peripheral circuit structure PCS with the conductive plate110therebetween in a vertical direction (Z direction). The cell array structure CAS may include a plurality of gate lines130, which are sequentially stacked on the conductive plate110in the vertical direction (Z direction). Areas of the plurality of gate lines130in an X-Y plane may be gradually reduced as a distance from the conductive plate110increases. The plurality of gate lines130may be divided into a plurality of blocks BLK by a plurality of word line cut regions WLC, which extend long in a first lateral direction (X direction). A plurality of gate lines130included in each of the plurality of blocks BLK may constitute a gate stack GS. Each of the plurality of block BLK may include a memory stack MST including one gate stack GS. In each of a plurality of memory stacks MST, the plurality of gate lines130may constitute the ground selection line GSL, the plurality of word lines WL, and the string selection line SSL, which are shown inFIG.3. FIG.5is a schematic plan view illustrating a planar arrangement of some components of an IC device1100, according to example embodiments. Referring toFIG.5, in the IC device1100, a lower substrate52and a conductive plate110may vertically overlap each other, and the conductive plate110may include a tile region110R located at a position corresponding to one tile24. An edge of the tile region110R, in which a cell array structure CAS is located, may be apart from an edge of the conductive plate110. The conductive plate110may further include an edge region110S surrounding the tile region110R. The edge region110S may be a portion of the conductive plate110between the edge of the tile region110R and the edge of the conductive plate110. The edge region110S may extend along the edge of the tile region110R and completely surround the tile region110R. The cell array structure CAS may be on the tile region110R of the conductive plate110, and a through electrode region TAA may be in a partial region of the conductive plate110, which is under the cell array structure CAS. At least one through hole PH may be formed in the through electrode region TAA. In some embodiments, the through electrode region TAA may extend long in a first lateral direction (X direction) parallel to the word line cut region WLC shown inFIG.11. The through hole PH may pass through the conductive plate110. The through electrode region TAA may be at any one of various positions in the tile region110R of the conductive plate110. For example, the through electrode region TAA may be substantially in a central portion of the tile region110R in a second lateral direction (Y direction), but the inventive concept is not limited thereto. The peripheral circuit structure PCS described with reference toFIG.2may be under the conductive plate110. The cell array structure CAS may overlap the peripheral circuit structure PCS with the tile region110R of the conductive plate110therebetween in a vertical direction (Z direction). A detailed configuration of the cell array structure CAS may be the same as that presented with reference toFIGS.2,3,4, and11. The through electrode region TAA may have the same configuration as the through electrode region TA shown inFIG.11. AlthoughFIG.5illustrates a case in which the tile region110R has a greater horizontal area than the cell array structure CAS, the tile region110R may refer to a portion of the conductive plate110in which the cell array structure CAS is located. For example, the tile region110R and the cell array structure CAS may have substantially the same horizontal area and completely vertically overlap each other. In addition, in some embodiments, a horizontal width and a horizontal area of the lower substrate52may be greater than those of the conductive plate110. An edge of the lower substrate52may be apart from the edge of the conductive plate110. A diode region40R, in which a plurality of antenna diodes D40are formed, may be under a portion of the edge region110S, which is adjacent to a vertex of the tile region110R. The diode region40R may be under a portion of the edge region110S, which is adjacent to a vertex of the conductive plate110. In some embodiments, each of the conductive plate110and the tile region110R may have a rectangular planar shape having four vertices. Four diode regions40R, which are apart from each other, may be under portions of the edge region110S of the conductive plate110corresponding to one tile24. Here, the portions of the edge region110S may be adjacent to four vertices of the tile region110R or vertices of the conductive plate110. That is, the diode regions40R may be under portions of the edge region110S, which are between vertices of the tile region110R and the vertices of the conductive plate110, which correspond to each other. In some embodiments, the diode region40R may have a rectangular planar shape, without being limited thereto. In some embodiments, the plurality of antenna diodes D40may be apart from each other in the diode region40R and arranged in rows and columns in a matrix form. FIG.6is a schematic plan view illustrating a planar arrangement of some components of an IC device1200, according to further embodiments. Referring toFIG.6, the IC device1200may have a diode region40Ra, which is different than the diode region40R included in the IC device1100shown inFIG.5. A plurality of antenna diodes D40may be formed in the diode region40Ra. In some embodiments, the diode region40Ra may have an L-shaped planar shape. In some embodiments, the plurality of antenna diodes D40may be apart from each other in the diode region40Ra and arranged in rows and columns in a matrix form. FIG.7is a schematic plan view illustrating a planar arrangement of some components of an IC device1300, according to example embodiments. Referring toFIG.7, instead of the diode region40R, which is under the portion of the edge region110S, which is adjacent to the vertex of the tile region110R in the conductive plate110of the IC device1100, as shown inFIG.5, the IC device1300may have a diode region40Rb, which is under a portion of an edge region110Sa of a conductive plate110a, which is adjacent to a vertex of a tile region110R. The edge region110Sa may be a portion of the conductive plate110abetween an edge of the tile region110R and an edge of the conductive plate110a. A plurality of antenna diodes D40may be formed in the diode region40Rb. The conductive plate110amay have a plate extension unit110E, which extends outward from a vertex portion of a plate main unit110M having a rectangular planar shape, as shown. The plate main unit110M may have a portion corresponding to the conductive plate110shown inFIGS.5and6. In some embodiments, the plate extension unit110E may have an L planar shape surrounding the vertex portion of the plate main unit110M having the rectangular planar shape. In the conductive plate110aof the IC device1300, the plate main unit110M corresponding to the conductive plate110of the IC device1100shown inFIG.5may be integrally formed with the plate extension unit110E. As shown in plan view, the diode region40Rb may be under the plate extension unit110E of the conductive plate110aand under a portion of the edge region110Sa adjacent to the plate extension unit110E. In some embodiments, the diode region40Rb may have a rectangular planar shape, without being limited thereto. In some other embodiments, the plurality of antenna diodes D40may be apart from each other in the diode region40Rb and arranged in rows and columns in a matrix form. FIG.8is a schematic plan view illustrating a planar arrangement of some components of an IC device1400, according to example embodiments. Referring toFIG.8, the IC device1400may include a first diode region40R and a second diode region40Rc instead of the diode region40R included the IC device1100shown inFIG.5. A conductive plate110bmay further include an edge region110Sb surrounding a tile region110R. The conductive plate110bmay include a plate extension unit110Ea and a plate connection unit110BR. The plate extension unit110Ea may be in an outer portion apart from at least one of four vertices of a plate main unit110M having a rectangular planar shape. The plate connection unit110BR may connect the plate main unit110M to the plate extension unit110Ea. In some embodiments, the plate extension unit110Ea may have a rectangular planar shape. In some embodiments, the plate connection unit110BR may have a bar-type planar shape. The first diode region40R and the second diode region40Rc may be under the edge region110Sb of the conductive plate110b. The second diode region40Rc may be under the plate extension unit110Ea. The first diode region40R may be under the edge region110Sb adjacent to a vertex to which the plate connection unit110BR configured to connect the plate main unit110M to the plate extension unit110Ea is not connected, from among the four vertices of the plate main unit110M. The first diode region40R may be substantially the same as the diode region40R shown inFIG.5. But, in some embodiments, the second diode region40Rc may have a rectangular planar shape. A plurality of antenna diodes D40may be formed in each of the first diode region40R and the second diode region40Rc.FIG.8illustrates an example in which three first diode regions40R and one second diode region40Rc are under one conductive plate110bin the IC device1400, but the inventive concept is not limited thereto. The sum of the number of first diode regions40R and the number of second diode regions40Rc in the IC device1400may be four. FIG.9is a schematic plan view illustrating a planar arrangement of some components of an IC device1500, according to example embodiments. Referring toFIG.9, the IC device1500may include a first diode region40Rb and a second diode region40Rc instead of the diode region40R included in the IC device1100shown inFIG.5. A conductive plate110cmay further include an edge region110Sc surrounding a tile region110R. The edge region110Sc of the conductive plate110cmay include a first plate extension unit110E, a second plate extension unit110Ea, and a plate connection unit110BR configured to connect a plate main unit110M to the second plate extension unit110Ea. The first plate extension unit110E may be substantially the same as the plate extension unit110E shown inFIG.7, and the second plate extension unit110Ea may be substantially the same as the plate extension unit110Ea shown inFIG.8. The first diode region40Rb may be substantially the same as the diode region40Rb shown inFIG.7, and the second diode region40Rc may be substantially the same as the diode region40Rc shown inFIG.8. FIG.9illustrates an example in which three first diode regions40Rb and one second diode region40Rc are under one conductive plate110cin the IC device1500, but the inventive concept is not limited thereto. The sum of the number of first diode regions40Rb and the number of second diode regions40Rc in the IC device1500may be four. FIG.10is a schematic plan view illustrating a planar arrangement of some components of an IC device1600, according to example embodiments. Referring toFIG.10, the IC device1600may include a diode region40Rc instead of the diode region40R included in the IC device1100shown inFIG.5. An edge region110Sd of a conductive plate110dmay include four plate extension units110Ea and four plate connection units110BR. The four plate extension units110Ea may be respectively in outer portions apart from four vertices of a plate main unit110M having a rectangular planar shape. The four plate connection units110BR may connect the plate main unit110M to the four plate extension units110Ea. The diode region40Rc may be under the plate extension unit110Ea. The diode region40Rc may be substantially the same as the second diode region40Rc shown inFIG.8orFIG.9. In the IC device1600, four diode regions40Rc may be under one conductive plate110d. That is, in the IC device1600, the four diode regions40Rc may be under four plate extension units110Ea of one conductive plate110d. FIG.11is a cross-sectional view of IC devices100and200according to example embodiments. Referring toFIG.11, the IC device100may include a memory cell region MR, and a diode region DR, which includes a plurality of antenna diodes as described herein. The memory cell region MR may be a portion in which a cell array structure CAS is vertically arranged (e.g., as a nonvolatile memory cell array). The diode region DR may be any one of the diode region40R shown inFIG.5, the diode region40Ra shown inFIG.6, the diode region40Rb shown inFIG.7, the first diode region40R and the second diode region40Rc shown inFIG.8, the first diode region40Rb and the second diode region40Rc shown inFIG.9, and the diode region40Rc shown inFIG.10. The memory cell region MR may include a through electrode region TA. The through electrode region TA may have substantially the same configuration as the through electrode region TAA shown inFIGS.5to10. A through hole PH may be formed in the through electrode region TA. In some embodiments, a plurality of through holes PH may be formed in the through electrode region TA. For example, in one through electrode region TA, some of the plurality of through holes PH may be linearly arranged along one straight line extending in a first lateral direction (X direction) and apart from each other, and the other through holes PH may be linearly arranged along another straight line, which is apart from the one straight line in a second lateral direction (Y direction), and apart from each other. The IC device100may include a peripheral circuit structure PCS and the cell array structure CAS, which is on the peripheral circuit structure PCS and overlaps the peripheral circuit structure PCS in a vertical direction (Z direction). As shown, the peripheral circuit structure PCS may extend between the conductive plate110and the semiconductor substrate52. As shown byFIG.11, the conductive plate110may extend between the peripheral circuit structure PCS and the cell array structure CAS, and may further function as the common source line CSL (see, e.g.,FIGS.1and3) for the CAS structure, which is electrically coupled to the antenna diodes. In some further embodiments, the conductive plate110may serve as a source region configured to supply current to vertical memory cells included in the cell array structure CAS. In some embodiments, the conductive plate110may have a stack structure of a lower metal plate110L and an upper semiconductor plate110U. The metal plate110L may include tungsten (W), and the semiconductor plate110U may include doped polysilicon, without being limited thereto. In some other embodiments, the conductive plate110may omit the metal plate110L and have a single layer structure including the semiconductor plate110U. The cell array structure CAS may include a memory stack MST of nonvolatile memory cells on the conductive plate110. The memory stack MST may include a gate stack GS. The gate stack GS may include a plurality of gate lines130, which extend parallel to each other in a lateral direction and overlap each other in the vertical direction (Z direction). An insulating film134may be between the conductive plate110and the plurality of gate lines130and between the plurality of gate lines130. On the conductive plate110, a plurality of word line cut regions WLC may intersect with the memory stack MST and extend lengthwise in the first lateral direction (X direction). Widths of the plurality of gate lines130in the second lateral direction (Y direction) may be defined by the plurality of word line cut regions WLC, respectively. Each of the plurality of word line cut regions WLC may be filled with an insulating film140, which may contact the conductive plate110, as shown. The plurality of gate lines130included in one gate stack GS may be stacked and overlap each other in the vertical direction (Z direction) between two adjacent word line cut regions WLC on the conductive plate110. The plurality of gate lines130included in one gate stack GS may constitute the ground selection line GSL, the plurality of word lines WL, and the string selection line SSL, which have been described with reference toFIG.3. From among the plurality of gate lines130, two gate lines130at an upper side may be separated from each other with a string selection line cut region SSLC therebetween in the second lateral direction (Y direction). Two gate lines130, which are separated from each other with the string selection line cut region SSLC therebetween, may respectively constitute the string selection lines SSL described with reference toFIG.3. The string selection line cut region SSLC may be filled by an insulating film150. A plurality of channel structures160may pass through the plurality of gate lines130and extend in the vertical direction (Z direction) on the conductive plate110. The plurality of channel structures160may be arranged a predetermined distance apart from each other in the first lateral direction (X direction) and the second lateral direction (Y direction). Each of the plurality of channel structures160may include a gate dielectric film162, a channel region164, a buried insulating film166, and a drain region168. The gate dielectric film162may include a tunneling dielectric film, a charge storage film, and a blocking dielectric film, which are sequentially formed in the channel region164. The channel region164may have a cylindrical shape. An inner space of the channel region164may be filled with the buried insulating film166. A plurality of drain regions168may be insulated from each other by a cover insulating film169. A plurality of bit lines BL may be on the plurality of channel structures160. One of the plurality of bit lines BL is illustrated inFIG.11. For example, the plurality of bit lines BL may extend long in the second lateral direction (Y direction) parallel to each other on the cell array structure CAS. The bit line BL may be apart from the conductive plate110with the cell array structure CAS therebetween. The plurality of channel structures160may be covered by an inter-wiring insulating film193. Each of the plurality of channel structures160may be connected to a corresponding one of the bit lines BL through one of a plurality of contact pads194passing through the inter-wiring insulating film193. Each of the plurality of through holes PH formed in the through electrode region TA of the conductive plate110may be filled with a buried insulating film112. A filling insulating film170may be on the buried insulating film112. The filling insulating film170may pass through the plurality of gate lines130and a plurality of insulating films134and extend in the vertical direction (Z direction). In the through electrode region TA, a through electrode THV may pass through the gate line130of the cell array structure CAS and extend in the vertical direction (Z direction). The through electrode THV may be electrically connected to a corresponding one of the bit lines BL and a structure within the underlying peripheral circuit structure PCS. The through electrode THV may pass through the conductive plate110via the through hole PH and extend long into the peripheral circuit structure PCS in the vertical direction (Z direction). The peripheral circuit structure PCS may include a lower substrate52, a plurality of peripheral circuits formed on a main surface52M of the lower substrate52, and a multilayered wiring structure MWS. Each of a plurality of through electrodes THV may be connected to at least one selected from the plurality of peripheral circuits through the multilayered wiring structure MWS included in the peripheral circuit structure PCS. The plurality of peripheral circuits included in the peripheral circuit structure PCS may include various circuits included in the peripheral circuit30described with reference toFIG.1. In some embodiments, the plurality of peripheral circuits included in the peripheral circuit structure PCS may include the row decoder32, the page buffer34, the data I/O circuit36, the control logic38, and the CSL driver39, which are shown inFIG.1. The plurality of through electrodes THV may be connected to a page buffer (refer to34inFIG.1) of the plurality of peripheral circuits included in the peripheral circuit structure PCS. The lower substrate52may include a semiconductor substrate. For example, the lower substrate52may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). An active region AC may be defined by a device isolation film54in the lower substrate52. A plurality of transistors TR may be formed on the active region AC and constitute the plurality of peripheral circuits. Each of the plurality of transistors TR may include a gate PG and a plurality of ion implantation regions PSD formed in the active region AC on both sides of the gate PG. Each of the plurality of ion implantation regions PSD may constitute a source region or a drain region of the transistor TR. At least one of the plurality of transistors TR may constitute the CSL driver (refer to39inFIG.1). The multilayered wiring structure MWS may include a plurality of peripheral circuit wiring layers (e.g., ML60, ML61, and ML62) and a plurality of peripheral circuit contacts (e.g., MC60, MC61, and MC62), which are connected to the plurality of peripheral circuits included in the peripheral circuit structure PCS. A least some of the peripheral circuit wiring layers ML60, ML61, and ML62may be connected to the transistor TR. The peripheral circuit contacts MC60, MC61, and MC62may connect the plurality of transistors TR to some selected from the peripheral circuit wiring layers ML60, ML61, and ML62. A lower surface of the through electrode THV may be connected to one of the peripheral circuit wiring layers ML60, ML61, and ML62. For example, the lower surface of the through electrode THV may be connected to the peripheral circuit wiring layer ML62, which is an uppermost layer of the plurality of peripheral circuit wiring layers ML60, ML61, and ML62, which is closest to the cell array structure CAS. AlthoughFIG.11illustrates an example in which the multilayered wiring structure MWS has three wiring layers in the vertical direction (Z direction), the inventive concept is not limited thereto. In some embodiments, the peripheral circuit wiring layers ML60, ML61, and ML62may have respectively different thicknesses in a vertical direction (Z direction). The peripheral circuit structure PCS may further include a plurality of antenna diodes D40formed in the lower substrate52in the diode region DR. Anode terminals of the plurality of antenna diodes D40may be electrically connected to the conductive plate110by a plurality of bypass wiring structures P81, so that an electrically conductive path (e.g., to remove charges accumulated on the conductive plate) is provided to the substrate52during fabrication. In some embodiments, in the diode region DR, the conductive plate110may be sequentially covered by the filling insulating film170, the cover insulating film169, and the inter-wiring insulating film193. The antenna diode D40may include a diode ion implantation region42(e.g., anode region). In some embodiments, the active region AC of the lower substrate52may include a first conductive type ion implantation region, and the diode ion implantation region42may include a second conductive type ion implantation region (e.g., anode region), which has a different conductive type from the first conductive type ion implantation region. The second conductive type ion implantation region and the first conductive type ion implantation region may form a P-N junction diode. In some embodiments, the diode ion implantation region42may have the same conductive type as the ion implantation region PSD of the transistor TR included in the CSL driver (refer to39inFIG.1). The plurality of bypass wiring structures P81may connect one of the edge regions110S,110Sa,100Sb, and110Sc described with reference toFIGS.5to10to the diode ion implantation regions42included in the plurality of antenna diodes D40. The bypass wiring structure P81may include a bypass via contact44having an upper surface in contact with a lower surface of the conductive plate110and a lower surface in contact with the diode ion implantation region42of the antenna diode D40. The upper surface of the bypass via contact44may be in contact with a lower surface of one of the edge regions110S,110Sa,100Sb, and110Sc described with reference toFIGS.5to10. In some embodiments, the bypass wiring structure P81and the antenna diode D40may bypass unwanted charges capable of generating a large current due to arcing to the lower substrate52to thereby prevent the charges from being accumulated in the conductive plate110. Accordingly, by avoiding arcing caused by the accumulation of undesired charges in the conductive plate110, the degradation of a plurality of peripheral circuits (e.g., the CSL driver39inFIG.1) including the plurality of transistors TR formed in the peripheral circuit structure PCS may be prevented. Each of the bypass via contact44, the plurality of peripheral circuit wiring layers ML60, ML61, and ML62, and the plurality of peripheral circuit contacts MC60, MC61, and MC62may include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. The plurality of transistors TR, the bypass via contact44, and the multilayered wiring structure MWS, which are included in the peripheral circuit structure PCS, may be covered by an interlayer insulating film70. The plurality of through electrodes THV may pass through a portion of the interlayer insulating film70and be in contact with an upper surface of the peripheral circuit wiring layer ML62. The interlayer insulating film70may include silicon oxide, silicon oxynitride (SiON), and/or silicon oxycarbonitride (SiOCN). The IC device100according to the present embodiment may be one of the IC device1100shown inFIG.5, the IC device1200shown inFIG.6, the IC device1300shown inFIG.7, the IC device1400shown inFIG.8, the IC device1500shown inFIG.9, and the IC device1600shown inFIG.10. Also, the diode region DR included in the IC device100according to the present embodiment may be one of the diode region40R included in the IC device1100shown inFIG.5, the diode region40Ra included in the IC device1200shown inFIG.6, the diode region40Rb included in the IC device1300shown inFIG.7, the first and second diode regions40R and40Rc included in the IC device1400shown inFIG.8, the first and second diode regions40Rb and40Rc included in the IC device1500shown inFIG.9, and the diode region40Rc included in the IC device1600shown inFIG.10. That is, the diode region DR may be in portions of the peripheral circuit structure PCS, which are adjacent to all four vertices of the tile region (refer to110R inFIGS.5to10) located at a position corresponding to the tile (refer to24inFIGS.5to10) included in the IC device100. A plurality of IC devices100may be simultaneously formed on a semiconductor wafer including the lower substrate52. A partial die (refer PD inFIG.18), which is a structure corresponding to a portion of the IC device100, may be formed in an edge portion of the semiconductor wafer. The partial die PD may include a plate piece corresponding to a portion of the conductive plate110. If sufficient undesired charges are accumulated in a conductive plate, any large current caused by arcing in response to the accumulation of charges may deteriorate the plurality of peripheral circuits including the plurality of transistors TR formed in the peripheral circuit structure PCS of the IC device100adjacent to the partial die PD. Fortunately, the diode region DR, in which the antenna diode D40is under each of portions adjacent to the four vertices of the tile region (refer to110R inFIGS.5to10), may be formed in the IC device100according to the present embodiment. Accordingly, at least a portion of the diode region DR in which the antenna diode D40is arranged may be formed also in the partial die PD formed in the edge portion of the semiconductor wafer. Thus, charges capable of generating a large current due to arcing may be bypassed to the lower substrate52through the antenna diode D40to prevent the unwanted and possibly catastrophic accumulation of charges. The IC device200may have substantially the same configuration as the IC device100except that the IC device200has portion B instead of portion A. However, the IC device200may include a bypass wiring structure P280instead of the bypass wiring structure P81. The bypass wiring structure P280may include a bypass via contact46and a middle wiring structure P84. The bypass via contact46may have an upper surface in contact with the lower surface of the conductive plate110and a lower surface, which is apart from the diode ion implantation region42of the antenna diode D40in the vertical direction (Z direction). The middle wiring structure P84may be connected between the bypass via contact46and the diode ion implantation region42. The upper surface of the bypass via contact46may be in contact with the lower surface of one of the edge regions110S,110Sa,100Sb, and110Sc described with reference toFIGS.5to10. The middle wiring structure P84may be a portion of the multilayered wiring structure MWS. The middle wiring structure P84may have a multilayered wiring structure.FIG.11illustrates an example in which the middle wiring structure P84includes the peripheral circuit wiring layers ML60, ML61, and ML62formed at different vertical levels and the peripheral circuit contacts MC60, MC61, and MC62configured to connect some of the peripheral circuit wiring layers ML60, ML61, and ML62to each other, and an uppermost wiring layer of the middle wiring structure P84is the peripheral circuit wiring layer ML62. However, the inventive concept is not limited thereto. For example, the uppermost wiring layer of the middle wiring structure P84may be the peripheral circuit wiring layer ML60or the peripheral circuit wiring layer ML61. An upper surface of the uppermost wiring layer of the middle wiring structure P84may be in contact with the lower surface of the bypass via contact46. The peripheral circuit contact MC60, which is at a lowermost portion of the middle wiring structure P84, may be in contact with the diode ion implantation region42. In some embodiments, the bypass wiring structure P280including the bypass via contact46and the middle wiring structure P84and the antenna diode D40may bypass charges capable of generating a large current due to arcing to the lower substrate52to prevent the charges from being accumulated in the conductive plate110. FIG.12is a cross-sectional view of IC devices300and400according to example embodiments. Referring toFIG.12, the IC device300may include a memory cell region MR, a connection region ER, a contact region CR, and a diode region DR. In the IC device300, the memory cell region MR and the diode region DR may have substantially the same configurations as the memory cell region MR and the diode region DR of the IC device100described with reference toFIG.11. In the connection region ER, a filling insulating film170may cover extensions EXT of a plurality of gate lines130on a conductive plate110. An upper surface of the filling insulating film170may be sequentially covered by a cover insulating film169and an inter-wiring insulating film193. Edge portions of the extensions EXT of the plurality of gate lines130may form a staircase structure. A plate contact900having a lower surface in contact with the conductive plate110may be in the contact region CR. The plate contact900may pass through the cover insulating film169and the filling insulating film170and be connected to an upper surface of the conductive plate110. The plate contact900may electrically connect a wiring pattern ML to the conductive plate110. A plate contact920may be connected to the wiring pattern ML through one contact pad194of a plurality of contact pads194. The wiring pattern ML may be at the same vertical level as the bit line BL. In some embodiments, the wiring pattern ML may include the same material as the bit line BL. For example, each of the wiring pattern ML and the bit line BL may be formed by patterning a single wiring material layer. For example, the wiring pattern ML may be a portion of the bit line BL. In some embodiments, to prevent undesired charges from being accumulated in the wiring material layer during a process of forming the wiring pattern ML and the bit line BL, the plate contact900may transmit charges to the conductive plate110and bypass the charges to a lower substrate52through a bypass wiring structure P81and an antenna diode D40. The IC device400may have substantially the same configuration as the IC device300except that the IC device400has portion B instead of portion A of the IC device300. However, the IC device400may include a bypass wiring structure P280instead of the bypass wiring structure P81. The bypass wiring structure P280may include a bypass via contact46having an upper surface in contact with a lower surface of the conductive plate110and a middle wiring structure P84connected between the bypass via contact46and a diode ion implantation region42. In some embodiments, to prevent undesired charges from being accumulated in the wiring material layer during the process of forming the wiring pattern ML and the bit line BL, the plate contact900may transmit charges to the conductive plate110and bypass the charges to the lower substrate52through the bypass wiring structure P280including the bypass via contact46and the middle wiring structure P84and the forward-biased antenna diode D40. FIGS.13to17are cross-sectional views of a process sequence of a method of manufacturing an IC device100, according to example embodiments. The method of manufacturing the IC device100shown inFIG.11, according to the example embodiment, will be described with reference toFIGS.13to17. Referring toFIG.13, a peripheral circuit structure PCS including a lower substrate52, a plurality of transistors TR, a multilayered wiring structure MWS, and an interlayer insulating film70may be formed. The peripheral circuit structure PCS may include a diode ion implantation region42of a common antenna diode D40formed in a diode region DR. Referring toFIG.14, a bypass via contact44may be formed in the diode region DR. The bypass via contact44may pass through the interlayer insulating film70and extend to the diode ion implantation region42of the antenna diode D40. The bypass via contact44may constitute a bypass wiring structure P81. Referring toFIG.15, a conductive plate110may be formed on the peripheral circuit structure PCS and the bypass via contact44, a through hole PH may be formed in a through electrode region TA of the conductive plate110, and a buried insulating film112may be formed to fill the through hole PH. In some embodiments, the conductive plate110may be formed to have a horizontal width and a horizontal area less than those of the lower substrate52. The buried insulating film112may fill spaces around edges of the conductive plate110. In some embodiments, the conductive plate110may be formed by sequentially forming a metal plate110L and a semiconductor plate110U. In some other embodiments, the conductive plate110may not include the metal plate110L but include only the semiconductor plate110U. Referring toFIG.16, a plurality of insulating films134and a plurality of sacrificial films PL may be alternately stacked one by one on the conductive plate110and the buried insulating film112. The plurality of sacrificial films PL may include silicon nitride, silicon carbide, or polysilicon. The plurality of sacrificial films PL may obtain spaces for forming a plurality of gate lines (refer to130inFIG.17) in a subsequent process. A portion of each of the plurality of insulating films134and the plurality of sacrificial films PL may be removed, the removed portion of each of the plurality of insulating films134and the plurality of sacrificial films PL may be filled with a filling insulating film170, and a cover insulating film169may be formed. The cover insulating film169may be formed to cover the insulating film134, which is an uppermost layer of the plurality of insulating films134, and the filling insulating film170. Thereafter, a plurality of channel structures160may be formed to pass through the cover insulating film169, the plurality of insulating films134, and the plurality of sacrificial films PL, and a string selection line cut region SSLC may be formed and filled with an insulating film150. Thereafter, a plurality of word line cut regions WLC may be formed to pass through the cover insulating film169, the plurality of insulating films134, and the plurality of sacrificial films PL. An upper surface of the conductive plate110may be exposed by the plurality of word line cut regions WLC (see also,FIG.11). Referring toFIGS.16and17, the plurality of sacrificial films PL may be replaced by the plurality of gate lines130due to the plurality of word line cut regions WLC. In some embodiments, to replace the plurality of sacrificial films PL by the plurality of gate lines130, the plurality of sacrificial films PL exposed by the plurality of word line cut regions WLC may be selectively removed to provide vacant spaces between the plurality of insulating films134. The vacant spaces may be filled with a conductive material to form the plurality of gate lines130. Afterwards, an insulating film140may be formed to fill the plurality of word line cut regions WLC. A through electrode THV may be formed to pass through the cover insulating film169, the filling insulating film170, the buried insulating film112, and the interlayer insulating film70and be in contact with an upper surface of a peripheral circuit wiring layer ML62. In some embodiments, the peripheral circuit wiring layer ML62, which is in contact with the through electrode THV, may be connected to the page buffer (refer to34inFIG.1) of the plurality of peripheral circuits formed in the peripheral circuit structure PCS. Afterwards, as shown inFIG.11, an inter-wiring insulating film193may be formed to cover an upper surface of the resultant structure including a plurality of through electrodes THV, and a plurality of contact pads194and a contact pad195may be formed to pass through the inter-wiring insulating film193. The plurality of contact pads194may be respectively connected to drain regions168of the plurality of channel structures160, and the contact pad195may be connected to the through electrode THV. Thereafter, a bit line BL may be formed on the plurality of contact pads194and the contact pad195, thereby completing the manufacture of the IC device100shown inFIG.11. The bit line BL may be connected to the plurality of channel structures160and the through electrode THV through the plurality of contact pads194and the contact pad195. Although the method of manufacturing the IC device100shown inFIG.11has been described with reference toFIGS.13to17, it will be understood that the IC device200shown inFIG.11, the IC devices300and400shown inFIG.12, and various IC devices having similar structures thereto may be manufactured by making various modifications and changes with reference to the descriptions ofFIGS.13to17within the scope of the inventive concept. For example, the formation of the IC device200shown inFIG.11and the IC device400shown inFIG.12may include forming a middle wiring structure P84during the process of forming the multilayered wiring structure MWS and forming a bypass via contact46instead of forming the bypass via contact44shown inFIG.14. Moreover, the formation of the IC devices300and400shown inFIG.12may include forming a plate contact900during the process of forming the through electrode THV. The plate contact900may pass through the cover insulating film169and the filling insulating film170and be in contact with the upper surface of the conductive plate110. FIG.18is a conceptual diagram of a method of manufacturing IC devices, according to example embodiments. Referring toFIG.18, a plurality of IC devices2000may be simultaneously formed on a semiconductor wafer WF including a lower substrate52. Each of the IC devices2000may include any one of the IC devices10,100,200,300,400,500,1000,1100,1200,1300,1400,1500, and1600, which have been described with reference toFIGS.1to17. A partial die PD, which is a structure corresponding to a portion of the IC device2000, may be formed in an edge portion of the semiconductor wafer WF. The partial die PD may include a plate piece110P corresponding to a portion of a conductive plate110. When undesired charges are accumulated in the plate piece110P, a large “arching” current may be generated and may severely deteriorate a plurality of peripheral circuits including a plurality of transistors formed in a peripheral circuit structure of the IC device2000adjacent to the partial die PD. However, a preferred diode region DR may be formed in the IC device200according to the present embodiment. In the diode region DR, antenna diodes D40may be respectively formed under portions of the conductive plate110, which are adjacent to four vertices of a tile region110R. Accordingly, at least a portion of the diode region DR in which the antenna diodes D40are arranged may be formed also in the partial die PD formed in the edge portion of the semiconductor wafer WF. Thus, charges capable of generating a large current due to arcing may be bypassed to the lower substrate52through the forward-biased antenna diode D40to prevent the charges from being accumulated in the plate piece110P. As a result, the plurality of peripheral circuits included in the IC device2000may be protected. FIG.19is a diagram illustrating a memory device500according to another example embodiment. Referring toFIG.19, a memory device500may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals may include copper (Cu) using a Cu-to-Cu bonding. The example embodiment, however, may not be limited thereto. For example, the bonding metals may also be formed of aluminum (Al) or tungsten (W). The IC device500may further include a diode region40R,40Ra,40Rb, or40Rc. A plurality of antenna diodes D40, which are substantially the same as described with reference toFIGS.1to17, may be arranged in portions of the diode region40R,40Ra,40Rb, or40Rc, which are adjacent to an edge of a first substrate210. Each of the peripheral circuit region PERI and the cell region CELL of the memory device500may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. The peripheral circuit region PERI may include a first substrate210, an interlayer insulating layer215, a plurality of circuit elements220a,220b, and220cformed on the first substrate210, first metal layers230a,230b, and230crespectively connected to the plurality of circuit elements220a,220b, and220c, and second metal layers240a,240b, and240cformed on the first metal layers230a,230b, and230c. In an example embodiment, the first metal layers230a,230b, and230cmay be formed of tungsten having relatively high electrical resistivity, and the second metal layers240a,240b, and240cmay be formed of copper having relatively low electrical resistivity. In an example embodiment illustrate inFIG.19, although only the first metal layers230a,230b, and230cand the second metal layers240a,240b, and240care shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers240a,240b, and240c. At least a portion of the one or more additional metal layers formed on the second metal layers240a,240b, and240cmay be formed of aluminum or the like having a lower electrical resistivity than those of copper forming the second metal layers240a,240b, and240c. The interlayer insulating layer215may be disposed on the first substrate210and cover the plurality of circuit elements220a,220b, and220c, the first metal layers230a,230b, and230c, and the second metal layers240a,240b, and240c. The interlayer insulating layer215may include an insulating material such as silicon oxide, silicon nitride, or the like. Lower bonding metals271band272bmay be formed on the second metal layer240bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals271band272bin the peripheral circuit region PERI may be electrically bonded to upper bonding metals371band372bof the cell region CELL. The lower bonding metals271band272band the upper bonding metals371band372bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals371band372bin the cell region CELL may be referred as first metal pads and the lower bonding metals5271band5272bin the peripheral circuit region PERI may be referred as second metal pads. The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate310and a common source line320. On the second substrate310, a plurality of word lines331to338(i.e.,330) may be stacked in a direction (a Z-axis direction), perpendicular to an upper surface of the second substrate310. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines330, respectively, and the plurality of word lines330may be disposed between the at least one string select line and the at least one ground select line. In the bit line bonding area BLBA, a channel structure CH may extend in a direction (a Z-axis direction), perpendicular to the upper surface of the second substrate310, and pass through the plurality of word lines330, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer350cand a second metal layer360c. For example, the first metal layer350cmay be a bit line contact, and the second metal layer360cmay be a bit line. In an example embodiment, the bit line360cmay extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate310. In an example embodiment illustrated inFIG.19, an area in which the channel structure CH, the bit line360c, and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line360cmay be electrically connected to the circuit elements220cproviding a page buffer393in the peripheral circuit region PERI. The bit line360cmay be connected to upper bonding metals371cand372cin the cell region CELL, and the upper bonding metals371cand372cmay be connected to lower bonding metals271cand272cconnected to the circuit elements220cof the page buffer393. In the word line bonding area WLBA, the plurality of word lines330may extend in a second direction (an X-axis direction), parallel to the upper surface of the second substrate310and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs341to347(i.e.,340). The plurality of word lines330and the plurality of cell contact plugs340may be connected to each other in pads provided by at least a portion of the plurality of word lines330extending in different lengths in the second direction. A first metal layer350band a second metal layer360bmay be connected to an upper portion of the plurality of cell contact plugs340connected to the plurality of word lines330, sequentially. The plurality of cell contact plugs340may be connected to the peripheral circuit region PERI by the upper bonding metals371band372bof the cell region CELL and the lower bonding metals271band272bof the peripheral circuit region PERI in the word line bonding area WLBA. The plurality of cell contact plugs340may be electrically connected to the circuit elements220bforming a row decoder394in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements220bof the row decoder394may be different than operating voltages of the circuit elements220cforming the page buffer393. For example, operating voltages of the circuit elements220cforming the page buffer393may be greater than operating voltages of the circuit elements220bforming the row decoder394. A common source line contact plug380may be disposed in the external pad bonding area PA. The common source line contact plug380may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line320. A first metal layer350aand a second metal layer360amay be stacked on an upper portion of the common source line contact plug380, sequentially. For example, an area in which the common source line contact plug380, the first metal layer350a, and the second metal layer360aare disposed may be defined as the external pad bonding area PA. Input-output pads205and305may be disposed in the external pad bonding area PA. Referring toFIG.19, a lower insulating film201covering a lower surface of the first substrate210may be formed below the first substrate210, and a first input-output pad205may be formed on the lower insulating film201. The first input-output pad205may be connected to at least one of the plurality of circuit elements220a,220b, and220cdisposed in the peripheral circuit region PERI through a first input-output contact plug203, and may be separated from the first substrate210by the lower insulating film201. In addition, a side insulating film may be disposed between the first input-output contact plug203and the first substrate210to electrically separate the first input-output contact plug203and the first substrate210. Referring toFIG.19, an upper insulating film301covering the upper surface of the second substrate310may be formed on the second substrate310, and a second input-output pad305may be disposed on the upper insulating layer301. The second input-output pad305may be connected to at least one of the plurality of circuit elements220a,220b, and220cdisposed in the peripheral circuit region PERI through a second input-output contact plug303. In the example embodiment, the second input-output pad305is electrically connected to a circuit element220a. According to embodiments, the second substrate310and the common source line320may not be disposed in an area in which the second input-output contact plug303is disposed. Also, the second input-output pad305may not overlap the word lines330in the third direction (the Z-axis direction). Referring toFIG.19, the second input-output contact plug303may be separated from the second substrate310in a direction, parallel to the upper surface of the second substrate310, and may pass through the interlayer insulating layer315of the cell region CELL to be connected to the second input-output pad305. According to embodiments, the first input-output pad205and the second input-output pad305may be selectively formed. For example, the memory device500may include only the first input-output pad205disposed on the first substrate210or the second input-output pad305disposed on the second substrate310. Alternatively, the memory device500may include both the first input-output pad205and the second input-output pad305. A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI. In the external pad bonding area PA, the memory device500may include a lower metal pattern273a, corresponding to an upper metal pattern372aformed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern372aof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern273aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern372a, corresponding to the lower metal pattern273aformed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern273aof the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. The lower bonding metals271band272bmay be formed on the second metal layer240bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals271band272bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals371band372bof the cell region CELL by a Cu-to-Cu bonding. Further, in the bit line bonding area BLBA, an upper metal pattern392, corresponding to a lower metal pattern252formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern252of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern392formed in the uppermost metal layer of the cell region CELL. In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the reinforcement metal pattern. FIG.20is a schematic diagram of an electronic system3000including an IC device3100, according to example embodiments. Referring toFIG.20, the electronic system3000according to an example embodiment may include an IC device3100and a controller3200electrically connected to the IC device3100. The electronic system3000may include a storage device including at least one IC device3100or an electronic device including the storage device. For example, the electronic system3000may include a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, which includes the at least one IC device3100. The at least one IC device3100may include a non-volatile memory device. For example, the IC device3100may include a NAND flash memory device including at least one of structures of the IC devices10,100,200,300,400,500,1000,1100,1200,1300,1400,1500,1600, and2000, which have been described above with reference toFIGS.1to19. The IC device3100may include a first structure3100F and a second structure3100S on the first structure3100F. In example embodiments, the first structure3100F may be beside the second structure3100S. The first structure3100F may include a peripheral circuit structure including a decoder circuit3110, a page buffer3120, and a logic circuit3130. The second structure3100S may include a memory cell structure including bit lines BL, a common source line CSL, a plurality of word lines WL, first and second upper gate lines UL1and UL2, first and second lower gate lines LL1and LL2, and a plurality of memory cell strings CSTR located between the bit lines BL and the common source line CSL. In the second structure3100S, each of the plurality of memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be variously changed according to embodiments. In example embodiments, the upper transistors UT1and UT2may include string selection transistors, and the lower transistors LT1and LT2may include ground selection transistors. The first and second lower gate lines LL1and LL2may be respectively gate electrodes of the lower transistors LT1and LT2. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1and UL2may be respectively gate electrodes of the upper transistors UT1and UT2. The common source line CSL, the first and second lower gate lines LL1and LL2, the plurality of word lines WL, and the first and second upper gate lines UL1and UL2may be electrically connected to the decoder circuit3110through a plurality of first connection wirings3115that extend to the second structure3100S in the first structure3100F. A plurality of bit lines BL may be electrically connected to the page buffer3120through a plurality of second connection wirings3125that extend to the second structure3100S in the first structure3100F. In the first structure3100F, the decoder circuit3110and the page buffer3120may perform a control operation on at least one of the plurality of memory cell transistors MCT. The decoder circuit3110and the page buffer3120may be controlled by the logic circuit3130. The IC device3100may communicate with the controller3200through an I/O pad electrically connected to the logic circuit3130. The I/O pad3101may be electrically connected to the logic circuit3130through an I/O connection wiring3135that extends to the second structure3100S in the first structure3100F. The controller3200may include a processor3210, a NAND controller3220, and a host interface (I/F)3230. In some embodiments, the electronic system3000may include a plurality of IC devices3100. In this case, the controller3200may control the plurality of IC devices3100. The processor3210may control all operations of the electronic system3000including the controller3200. The processor3210may operate according to predetermined firmware and access the IC device3100by controlling the NAND controller3220. The NAND controller3220may include a NAND I/F3221configured to process communication with the IC device3100. A control command for controlling the IC device3100, data to be written to the plurality of memory cell transistors MCT of the IC device3100, and data to be read from the plurality of memory cell transistor MCT of the IC device3100may be transmitted through the NAND I/F3221. The host I/F3230may provide a communication between the electronic system3000and an external host. When a control command is received from the external host through the host I/F3230, the processor3210may control the IC device3100in response to the control command. While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. | 70,260 |
11862625 | It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements. DETAILED DESCRIPTION A compact standard cell electrostatic discharge (ESD) protection device and associated methods of operation and fabrication are described for protecting an integrated circuit signal node against transient voltage events using a dual-diode protection scheme implemented with “dummy” n-FinFET and p-FinFET devices formed with centered well taps to integrate seamlessly within the standard cell integrated circuit. In selected embodiments, the ESD protection device is implemented as a standard cell-based charged device model (CDM) protection cell having centrally located n-well and p-well taps positioned internally within a pair of CDM diodes formed with “dummy” FinFET devices (e.g., a p-FinFET and n-FinFET), each having a supply-connected first diode terminal formed with the body well, and a signal node-connected second diode terminal formed with the shorted gate, source and drain regions. In particular, a first “dummy” n-FinFET may be connected as a FinFET/CDM diode between the signal node and a ground supply, and a second “dummy” p-FinFET may be connected as a FinFET/CDM diode between the signal node and a power supply. In embodiments where the signal node is coupled to a FinFET gate of a receiving circuit, the CDM protection cell provides CDM protection to prevent this gate from failing. As disclosed herein, the receiving FinFET may be located in another cell. Alternatively, the receiving FinFET may be located in a functional block of the CDM protection cell, such as a buffer, inverter, level-shifter, or the like. In such embodiments, the FinFET/CDM diode devices and the functional block may be partitioned and distributed in two portions placed on either sides of the CDM protection cell so that the n-well and p-well taps may be centrally placed in close proximity to both portions to make good well connections. Instead of using dedicated junction diodes which require substantial circuit area, the disclosed compact standard cell ESD protection device uses “dummy” FinFETs which can be readily integrated with the existing standard cell framework to achieve the same CDM protection performance with significant area savings compared to CDM protection designs using conventional diodes. While compatible with advanced 5 nm FinFET “continuous active” technologies, the floorplan of the standard cell-based CDM protection cell is universal and may be applied to CDM protection for cross-domain interfaces in any suitable technology. To provide additional details for a contextual understanding of the present disclosure, reference is now made toFIG.1which shows a simplified circuit diagram10of a ESD protection device implemented with complementary diodes15,16implemented with conventional P+/n-well and N+/p-well junctions. Connected in series between supply lines VDD2, GND2, the complementary diode pair15,16protects the FET gates MP2, NP2of the output circuit17against damage from voltage transient events generated at the output of the transmitting circuit11. In particular, the transmitting circuit11may be any input signal pad, pin or functional circuit connected between supply lines in a first domain (e.g., VDD1, GND1). For example, the transmitting circuit may be an inverter circuit MP1, MN1which is connected to receive an input signal12and to generate an inverted output signal13which is connected over an optional resistor R to an internal signal node14. Similarly, the protected output circuit17may be a buffer or inverter circuit MP2, MN2which is connected between supply lines in a second domain (e.g., VDD2, GND2) to receive the internal signal node14and to generate an output signal18. In operation, the complementary diodes15,16facilitate the absorption of both positive and negative voltage ESD voltages and currents generated at the transmitting circuit11. Depending on the polarity of ESD voltage, upon the occurrence of an ESD event, one of the two complementary diodes15,16will turn ON at the forward turn-on voltage of the diode (approximately 0.7 volts) so that the bulk of the ESD current will go through the forward biased diode. As will be appreciated, ESD protection circuits using diodes formed with conventional core P+/n-well and N+/p-well junctions are suitable for certain technologies where the active areas are arranged in continuous lines of alternating n-wells and p-wells. However, there are numerous design challenges and constraints with using conventional diode structures to protect against ESD events, especially with newer integrated circuit designs which use standard cell design layouts that can be disrupted by inserting an ESD protection circuit which requires a large circuit area. To provide an illustrative example of how the design constraints for standard cell integrated circuit layouts can be disrupted by including conventional ESD protection circuits, reference is now made toFIG.2which depicts, in plan view, a portion of a conventional layout architecture20of a standard cell form-factor integrated circuit which includes an ESD protection device cell22formed with a core P+/n-well diode28and a core N+/p-well diode29in series between supply lines to protect the output against voltage transients. In the depicted layout portion20, the outermost area21represents the region where standard cells are located, and surrounds the ESD protection cell22which includes a boundary cell region23and a diode grid24which surround the core P+/n-well diode28and a core N+/p-well diode29. Though not explicitly shown, the standard cell area21will include standard design cell which are generated by system designers using commercially available design tools, such as electronic design automation (EDA) and computer aided design (CAD) tools, to integrate different logic functions into an integrated circuit (IC) using standard design cells. Each standard cell may include a plurality of transistors, (e.g., complementary FinFET) devices that are used to implement logic functions, such as Boolean functions (e.g., AND, OR, and NOT), storage functions (e.g., flip-flops, latches, and buffers), and digital combinational functions (e.g., multiplexers and demultiplexers). With each standard cell having a predetermined geometry (width and height), the design tools include a library (known as a standard cell library) that stores the standard cell definitions for these logic functions which are selected and placed in rows and columns. Upon completing the placement, the semiconductor device design is simulated, verified, and subsequently transferred to a chip (i.e., formed in silicon). Surrounding the ESD protection cell22, the boundary cell region23is located to provide a transition between the standard cell area21and ESD protection cell22. With advanced designs, the insertion of boundary cells (or endcap cells) at the end of each row can be used to isolate the different blocks in a system-on-chip (SoC) by protecting each block from external signals, breaking the continuity of the n-well to prevent n-well spacing violations, managing substrate and well noise, and the like. In the ESD protection cell22, the core P+/n-well diode28may be formed by selectively implanting a P+ region or ring into a substrate n-well, thereby forming a p-diode in the n-well. In similar fashion, the core N+/p-well diode29may be formed by selectively implanting an N+ region or ring into a p-well or substrate, thereby forming an n-diode in the p-well/substrate. Though not explicitly shown, the ESD protection cell22may be connected with metal interconnect layers to connect the core P+/n-well diode28between a signal node and a first supply voltage (e.g., VDD2), and to connect the core N+/p-well diode29between the signal node and a second supply voltage (e.g., GND2). In the depicted ESD protection cell22, the total cell height25(10 rows, each including one n-well and one adjacent p-well) is defined by the heights of the diode grid24(8 rows) and the boundary cells23(2 rows) representing the minimal vertical spacing between two standard cell grids. In addition, the total cell width26is defined by the widths of the diode grid24and the boundary cells23representing the minimal horizontal spacing between two standard cell grids. As a result, even in the most area-compact implementation, this solution (in a standard cell form-factor) would occupy 10 standard cell rows to satisfy design rule checking (DRC) constraints. The large area requirement makes this solution unattractive and inefficient in terms of circuit area requirements. To address these shortcomings and deficiencies and others from the conventional ESD protection solutions, reference is now made toFIG.3which depicts a simplified circuit schematic diagram30of an ESD protection cell32to provide additional details for an improved understanding of selected embodiments of the present disclosure. Generally speaking the ESD protection circuit32is connected between an input transmitting circuit31and an output node39to provide a compact standard cell ESD protection device and associated method of operation for protecting against damage at the functional block37from voltage transient events generated by the input transmitting circuit31. As will be appreciated, the transmitting circuit31may be any functional circuit to generate the INPUT signal to the ESD protection cell32. For example, the transmitting circuit31may be an inverter circuit MP1, MN1which is connected between supply lines in a first domain (e.g., VDDx, VSSx) to receive an input signal38and to generate an inverted INPUT signal to the ESD protection cell32. However, the transmitting circuit31may also be a buffer, a level-shifter, or an external I/O pad or pin which generates an ESD event on the INPUT signal line. And while the transmitting circuit31is shown as being connected to supply lines VDDx, VSSx in a different domain than the supply lines VDDy, VSSy of the ESD protection cell32, ESD protection cell32may also be used if VDDx and VDDy were the same net or if VSSx and VSSy were the same net since ESD voltage transient events can also arise when the transmitting circuit31and the ESD protection cell32are in the same voltage domain but separated from one another by a long signal routing path (e.g., over 100 microns). At the ESD protection cell32, any transient voltage or ESD event stress from the received INPUT signal is limited or clamped by using the complementary CDM diode pair34,35to protect the input gates of the CMOS FETs MP2, MN2of the functional block37. At a minimum, the ESD protection cell32includes a pair of CDM diodes34,35formed with “dummy” FinFET devices (e.g., a p-FinFET and n-FinFET) connected in series between supply lines VDDy, VSSy. Each “dummy” FinFET has a supply-connected first diode terminal formed with the FinFET body well, and a signal node-connected second diode terminal formed with the shorted gate, source and drain regions of the FinFET. In particular, a first “dummy” p-FinFET34is connected as a FinFET/CDM diode between the signal node and a power supply VDDy, and a second “dummy” n-FinFET35is connected as a FinFET/CDM diode between the signal node and a ground supply VSSy. By directly coupling the body (well) of each “dummy” FinFET34,35to its respective supply rail VDDy, VSSy, a first diode terminal (e.g., cathode34A, anode35A) is formed. In addition, by shorting together the gate, source, and drain terminals of each FinFET34,35, a second diode terminal (e.g., anode34B, cathode35B) is formed and tied to the signal node36. As described hereinbelow, the complementary CDM diode pair34,35are formed to include p-well and n-well taps placed close to the dummy MOSFETs to make good well connections to a first diode terminal, where the second diode terminal is by the gate, source, and drain terminals of each FinFET34,35. In addition, the ESD protection cell32may include an optional passive element33, such as a resistor or capacitor, placed in the signal line before the CDM diodes34,35. As will be appreciated, the function of the optional passive element33is to enhance the protection against ESD events by helping absorb ESD voltages and currents generated at the transmitting circuit31, thereby further reducing the ESD stress on the receiving input gates of the CMOS FETs MP2, MN2. The depicted ESD protection cell32also includes a functional block37in which the protected CMOS FETs MP2, MN2are located. While the depicted functional block37includes an inverter circuit MP2, MN2which is connected between supply lines in a second domain (e.g., VDDy, VSSy) to receive the input signal node signal36and to generate an inverted OUTPUT signal39, it will be appreciated that the functional block37may also be a buffer, a level-shifter, or other functional circuitry requiring ESD protection of its input gates. In addition, the depicted functional block37is not required to be located inside the ESD protection cell32, but may also be located in another cell of the integrated circuit. One of the key innovative aspects is the implementation of the CDM diodes34,35as MOSFET dummy devices where the source/drain junctions act as the CDM diodes and where the gate terminals are shorted to the source/drain terminals to minimize parasitic capacitance between the signal node and the supply rails. Such “dummy” MOSFET devices can be placed inside a standard cell array, thereby offering a huge area benefit compared to using conventional diodes which would break the alternating well pattern of the standard cell area and which would be difficult to integrate. To provide additional details for an improved understanding of selected embodiments of the present disclosure, reference is now made toFIG.4which depicts, in plan view, a layout architecture of a CDM protection cell40as a single-row standard cell implementation where the dummy FinFETs and the functional block are partitioned and distributed in two portions placed on either sides of centrally located n-well and p-well taps. As will be appreciated, the layout features depicted in the CDM protection cell40do not include every element of the final device (such as gate layers or metal interconnects), but illustrate the relative location and placement of the active areas43,44where the P+ fins46and N+ fins47are positioned for use in forming the FinFET devices in the functional block, dummy FinFETs, and centered p-well and n-well tap regions. In particular, the upper portion of the CDM protection cell40includes two active P+ areas43A,43C formed over the n-well41at the peripheral sides of the cell40. In the active P+ areas43A,43C, one or more P+ fins46are formed to laterally extend across the cell40except for defined active break areas45A,45B. The upper portion of the CDM protection cell40also includes an active N+ area44C formed over the n-well41to be aligned with and separated from the active P+ areas43A,43C by the defined active break areas45A,45B. In the active N+ area44C, one or more N+ fins47formed the n-well tap48for coupling the n-well region41to a first supply voltage VDD. In similar fashion, the lower portion of the CDM protection cell40includes at least two active N+ areas44A,44D formed over the p-well42at the peripheral sides of the cell40. In the active N+ areas44A,44D, one or more N+ fins47are formed to laterally extend across the cell40except for defined active break areas45C,45D,45E. The lower portion of the CDM protection cell40also includes an active P+ area43B formed over the p-well42to be aligned with and separated from the active N+ areas44A,44D by at least the defined active break areas45C,45D. In the active P+ area43B, one or more P+ fins46formed the p-well tap49for coupling the p-well region42to a second supply voltage VSS. In the depicted example, three parallel rows of P+ and N+ fins46,47are shown, but it will be appreciated that additional or fewer fin rows may be formed. In addition, the design rules will require active area gaps45A-N between the p+ and n+ active regions43A-C,44A-D, though the arrangement, number, and placement of the gaps45can vary based on the design requirements. For example, an additional active area gap may be positioned in the p+ active area43A in alignment with the active area gaps45H,45C. Inside the CDM protection cell40, one or more gate electrode layers (not shown) are formed to vertically extend across the cell40to overlap with the P+ and N+ fins46,47, thereby forming p-FinFETs (in the active P+ areas43) and n-FinFETs (in the active N+ areas44). These gate electrode layers are typically placed with a regular pattern and a constant pitch over the standard cell area, and they may also be used to electrically isolate functional blocks from dummy FinFETs if both of them reside in the same active area. For example, “dummy” FinFETs5are isolated from functional block6by one or more gate electrodes that run vertically between the two regions. In addition, one or more source/drain contact layers (not shown) are formed to vertically extend across the cell40to make source/drain contacts with the P+ and N+ fins46,47. With the formation of additional metal interconnect layers (not shown), the p-FinFETs and n-FinFETs may be connected to provide the required circuit functionality of the CDM protection cell40. By partitioning the “dummy” FinFETs and functional blocks into first and second portions, the separate portions may be symmetrically distributed on both sides of the cell40. In particular, the required circuit functionality of the CDM protection cell40includes at least a pair of dummy FinFET portions2,5connected as CDM diodes located on opposite sides of centrally positioned p-well and n-well taps3,4. As will be appreciated, the CDM diodes are formed from the “dummy” FinFETs by routing one or more metal interconnect layers to short the gate, source and drain terminals of n-FinFETs and p-FinFETS located in the dummy FinFET diode portions2,5. And by positioning the dummy FinFET diode portions2,5around the p-well and n-well taps3,4in the center of the cell40, the well taps3,4not only break the continuous active regions43,44, but are positioned in close proximity to the dummy FinFETs to make good well connections. In addition to the dummy FinFET portions2,5, the circuit functionality of the CDM protection cell40may also include one or more functional circuit block portions1,6. As will be appreciated, any desired functional circuit (e.g., a buffer, level shifter, or inverter) may be formed from FinFETs in the functional circuit block portions1,6by routing one or more metal interconnect layers to connect the gate, source and drain terminals of n-FinFETs and p-FinFETS to provide the desired circuit functionality. Instead of placing the n-well and p-well tie regions at the end of the cell40(which could lead to DRC errors in typical standard cell abutment scenarios), the center placement of the taps48,49allows the dummy FinFETs (CDM diodes) to be symmetrically placed on both sides of the taps (1stand 2ndportions), thereby improving the diode performance (on-resistance and failure current). And by placing the outer functional circuit block portions1,6adjacent to the dummy FinFET portions2,5, the “dummy” FinFETs are formed to share active P+ and N+ regions with the functional blocks. By way of illustrating an example implementation, the total cell area for a single row implementation of the CDM protection cell40can be 0.332 μm2, including an internal N and P diode junction region having a perimeter of 1.384 μm and an area of 0.0212 μm2. In contrast, the total cell area for a conventional layout architecture of a standard cell 10-row implementation of the ESD protection cell22can be 14.24 μm2, including an internal N and P diode junction region having a perimeter of 1.63 μm and an area of 0.124 μm.2In this comparison, the diode sizes are not matched, but the single row implementation of the CDM protection cell40requires only 2.3% of the circuit area of the conventional ESD protection cell. In order to match the diode sizes, six of the CDM protection cells40would be used, resulting in a total cell area of 1.992 μm2which is only 13.98% of the circuit area of the conventional ESD protection cell. As will be appreciated, the single-row implementation of the CDM protection cell40may require defined cell edge spacing table rules for placement and routing (P&R) tools to avoid active area placement restrictions. For example, there may be architectures wherein active area breaks (e.g.,45A-E) inside a CDM protection cell40can lead to placement restrictions with regard to adjacent standard cells with active breaks that are placed above or below. Examples of such placement restrictions may disallow active area breaks in adjacent cells that do not align with the active area breaks45of the cell40, but otherwise allow adjacent active area breaks which align with the active area breaks45of the cell40. Since P&R tools (e.g., Cadence Innovus, Synopsys ICCII, etc.) support cell edge spacing table rules, proper definition of these cell edge spacing table rules would automatically resolve these adjacent cell placement restrictions at the SoC level. As disclosed herein, the specific placement and spacing of the dummy FinFET and well taps in the active P+ and N+ areas in the ESD protection cell will depend on the design layout restrictions required by the specific cell layout requirements, though generally speaking, the “dummy” p-FinFET and n-FinFET devices should be aligned for connection by a common gate electrode to short the gate, source, and drain regions together. In addition, the non-overlapping n-well and p-well taps should be positioned internally within a pair of CDM diodes formed with “dummy” p-FinFET and n-FinFET devices. If desired, the ESD protection cell may also include a functional circuit block portion placed on one or both outermost ends of the ESD protection cell. For an improved understanding of selected embodiments of the present disclosure, reference is now made toFIGS.5A-Bwhich depict perspective views of the PFET and NFET CDM diodes and well taps used to form a CDM protection cell in a p-type substrate51. In particular,FIG.5Adepicts a perspective view50A of a PFET CDM diode formed with first and second dummy p-FinFET portions58A,58B located on opposite sides of a centrally positioned N+/n-well tie59in accordance with selected embodiments of the present disclosure. The depicted first dummy PMOS FinFET portion58A is formed with a plurality of parallel P+ fin structures54A-B which are aligned in the x-direction to extend up (in the z-direction) from the underlying n-well region52formed in the p-substrate51. As formed, the parallel P+ fin structures54A-B protrude above the shallow trench isolation (STI) layer56so that they are separated in both the x-direction and y-direction by STI layers56. The depicted first dummy PMOS FinFET portion58A also includes one or more metal gate electrode layers57A extending perpendicularly in the y-direction to overlap with the parallel P+ fin structures54A-B, thereby forming P+ fin source regions54A and P+ fin drain regions54B. Completing the first dummy PMOS FinFET portion58A, one or more source/drain contact layers (not shown) may be formed to extend in the y-direction to make source/drain contacts with the P+ fin source/drain regions54A/B. At the source/drain junction between the P+ fin structures54A/B and the underlying n-well52, a PFET CDM diode is formed where the n-well region52forms one terminal of the PFET CDM diode. And with the formation of additional metal interconnect layers (not shown) over the first dummy PMOS FinFET portion58A, the gate57A and P+ fin source/drain regions54A/B are shorted to a second terminal of the PFET CDM diode and connected to a signal node. The depicted second “dummy” PMOS FinFET portion58B may be formed on the opposite end of the P+ active area with an identical structure, including a metal gate electrode57D and P+ fin source/drain regions54E/F which are connected to form another PFET CDM diode having a first terminal (formed in the n-well region) and a second terminal (formed by the shorted gate57D and P+ fin source/drain regions54E/F). By partitioning the dummy PMOS FinFETs into first and second portions, the separate portions may be symmetrically distributed on both sides of the N+/n-well tie59. Between the first and second dummy PMOS FinFET portions58A,58B, the N+/n-well tie59may be formed using the same basic structure, though connected differently through the metal interconnect layers. In particular, the depicted N+/n-well tie59is formed with a plurality of parallel N+ fin structures54C-D which are aligned in the x-direction to extend up from the underlying n-well region and to protrude above the shallow trench isolation (STI) layer56so that they are separated in both the x-direction and y-direction by STI layers56. The depicted N+/n-well tie59may also include one or more metal gate electrode layers57B extending perpendicularly in the y-direction to overlap with the parallel N+ fin structures54C-D. Completing the N+/n-well tie59, one or more source/drain contact layers (not shown) may be formed to extend in the y-direction to make contact with the N+ fin structures54C-D. With the formation of additional metal interconnect layers (not shown) over the N+/n-well tie59, the N+/n-well tie59is connected to a first supply voltage (e.g., VDD). In addition,FIG.5Bdepicts a perspective view50B of an NFET CDM diode formed with first and second dummy n-FinFET portions60A,60B located on opposite sides of a centrally positioned P+/p-well tap in accordance with selected embodiments of the present disclosure. The depicted first dummy NMOS FinFET portion60A is formed with a plurality of parallel N+ fin structures55A-B which are aligned in the x-direction to extend up (in the z-direction) from the underlying p-well region53formed in the p-substrate51. As formed, the parallel N+ fin structures55A-B protrude above the shallow trench isolation (STI) layer56so that they are separated in both the x-direction and y-direction by STI layers56. The depicted first dummy NMOS FinFET portion60A also includes one or more metal gate electrode layers57A extending perpendicularly in the y-direction to overlap with the parallel N+ fin structures54A-B, thereby forming N+ fin source regions55A and N+ fin drain regions55B. Completing the first dummy NMOS FinFET portion60A, one or more source/drain contact layers (not shown) may be formed to extend in the y-direction to make source/drain contacts with the N+ fin source/drain regions55A/B. At the source/drain junction between the N+ fin structures55A/B and the underlying p-well51, an NFET CDM diode is formed where the p-well region53forms one terminal of the NFET CDM diode. And with the formation of additional metal interconnect layers (not shown) over the first dummy NMOS FinFET portion60A, the gate57A and N+ fin source/drain regions55A/B are shorted to a second terminal of the NFET CDM diode and connected to a signal node. The depicted second dummy NMOS FinFET portion60B may be formed on the opposite end of the N+ active area with an identical structure, including a metal gate electrode57D and N+ fin source/drain regions55E/F which are connected to form another NFET CDM diode having a first terminal (formed in the n-well region) and a second terminal (formed by the shorted gate57D and N+ fin source/drain regions55E/F). By partitioning the dummy NMOS FinFETs into first and second portions, the separate portions may be symmetrically distributed on both sides of the P+/P-well tie61. And while the labeling of the metal gate electrode layers57A,57D in bothFIGS.5Aand B indicates that these may be part of the same gate electrode layer extending over both the PFET and NFET CDM diodes, this is not required in every embodiment. For example, separate gate electrode layers could be used for the first dummy PMOS FinFET portion58A and first dummy NMOS FinFET portion60A. Similarly, separate gate electrode layers could be used for the second dummy PMOS FinFET portion58B and second dummy NMOS FinFET portion60B. Between the first and second dummy NMOS FinFET portions60A,60B, the P+/p-well tie61may be formed using the same basic structure, though connected differently through the metal interconnect layers. In particular, the depicted P+/p-well tie61is formed with a plurality of parallel P+ fin structures55C-D which are aligned in the x-direction to extend up from the underlying p-well region and to protrude above the shallow trench isolation (STI) layer56so that they are separated in both the x-direction and y-direction by STI layers56. The depicted P+/p-well tie61may also include one or more metal gate electrode layers57C extending perpendicularly in the y-direction to overlap with the parallel N+ fin structures55C-D. Completing the P+/p-well tie61, one or more source/drain contact layers (not shown) may be formed to extend in the y-direction to make contact with the P+ fin structures55C-D. With the formation of additional metal interconnect layers (not shown) over the P+/p-well tie61, the P+/p-well tie61is connected to a second supply voltage (e.g., VSS). Though not shown, it will appreciated that additional functional circuitry and/or passive circuit components can be included in the ESD protection cell. For example, additional PMOS and NMOS FinFETs can be formed on either or both ends of the ESD protection cell with appropriate metal interconnect routing to form functioning CMOS circuits, such as buffers, inverters, and/or level shifters having input or receiving FET gates connected to the signal node for protection by the ESD protection circuit. In addition or in the alternative, an integrated circuit resistor may be formed as a polysilicon resistor and/or metal resistor in one or more of the metal interconnect layers. As will be appreciated, the embodiments disclosed herein are not limited to a particular material for the gate electrode, resistor or metal interconnect layers. For example, gate electrodes may be formed with one or more polysilicon or metal layers over a gate dielectric or insulating layer formed with a high-K dielectric material, such as hafnium based oxide, a hafnium based oxynitride, or a hafnium-silicon oxynitride, hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide. To further illustrate selected embodiments of the present disclosure, reference is now made toFIG.6which is a simplified schematic flow chart100illustrating various methods for fabricating an integrated circuit with a standard cell design for an electrostatic discharge (ESD) protection circuit. In describing the fabrication methodology100, the description is intended merely to facilitate understanding of various exemplary embodiments and not by way of limitation. Unless otherwise indicated, the identified processing steps101-106may be implemented with one or more individual fabrications steps, including but not limited to depositing, growing, masking, developing, exposing, patterning, implanting, doping, etching, cleaning, stripping, annealing, and/or polishing that are performed in any desired order. Since the steps illustrated inFIG.6and described below are provided by way of example only, it will be appreciated that alternative embodiments of fabrication method100may include additional steps, omit certain steps, substitute or alter certain steps, or perform certain steps in an order different than that illustrated inFIG.11. Once the fabrication methodology starts (step101), a standard cell design for an ESD protection circuit is received. In selected embodiments, the standard cell design includes a signal node and a CDM protection circuit block operably coupled to protect a functional circuit block against electrostatic discharge events at the signal node. The functional circuit block may be included in the standard cell, or may be included in another cell connected to the standard cell. At step103, a semiconductor substrate is provided or obtained. For example, a semiconductor wafer structure may be provided which is formed with a semiconductor substrate structure having a predetermined crystallographic orientation and thickness (e.g., approximately 0.6 mm). Depending on the type of transistor device being fabricated, the semiconductor substrate structure may be implemented as a bulk silicon substrate, single crystalline silicon (doped or undoped), epitaxial semiconductor material, SOI substrate, or any semiconductor material including, for example, Si, Si C, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other Group III-V compound semiconductors or any combination thereof, and may optionally be formed as the bulk handling wafer. As will be appreciated, the semiconductor substrate structure may be appropriately doped to provide n-type (electron) or p-type (hole) carriers. At step104, a sequence of steps are used to fabricate the standard cell design in the semiconductor substrate as an integrated circuit having a defined set of layout properties which include adjacent n-well and p-well regions extending across the standard cell. The layout properties also include a tap area with n-well and p-well ties, where the n-well tie is located in a central section of the n-well region for connecting the n-well to a first supply voltage, and where the p-well tie is located in a central section of the p-well region for connecting the p-well to a second supply voltage. The layout properties also include a dummy FinFET diode layout area positioned on one or both sides of the tap region. As formed, the dummy FinFET diode layout area includes a first p-FinFET formed in the n-well region and connected as a first diode between the first supply voltage and the signal node with the gate, source, and drain regions shorted of the first p-FinFET shorted to the signal node. The dummy FinFET diode layout area also includes a second n-FinFET formed in the p-well region and connected as a second diode between the second supply voltage and the signal node with the gate, source, and drain regions of the second n-FinFET shorted to the signal node. When fabricating the standard cell, the sequence of fabrication steps may include selectively implanting a single row standard cell area of the semiconductor substrate with the n-well and p-well regions. In addition, the fabrication steps may include selectively forming a plurality of semiconductor fins on the semiconductor substrate extending up from the n-well and p-well regions. As formed, the plurality of semiconductor fins may include P+ doped semiconductor fins formed over the n-well region in one or more defined P+ active areas of the dummy FinFET diode layout area, N+ doped semiconductor fins formed over the n-well region in the tap area, N+ doped semiconductor fins formed over the p-well region in one or more defined N+ active areas of the dummy FinFET diode layout area, and P+ doped semiconductor fins formed over the p-well region in the tap area. As will be appreciated, the fabrication steps may be formed with a combination of epitaxial semiconductor growth and/or selective etch processes. Non-limiting example of epitaxial growth include ultra-high vacuum chemical vapor deposition (UHV-CVD) at low temperature (e.g., around 550° C.), and/or low pressure chemical vapor deposition (LP-CVD) at higher temperature (e.g., around 900° C.) and by other means known in the art. In addition, the fabrication steps may include selectively forming one or more FinFET gate electrodes aligned perpendicularly to the plurality of semiconductor fins to define the first p-FinFET and second n-FinFET in the dummy FinFET diode layout area. Finally, the fabrication steps may include selectively forming one or more metal interconnect layers over the substrate to connect the first p-FinFET as the first diode, to connect the second n-FinFET as the second diode, to tie the N+ doped semiconductor fins formed over the n-well region to the first supply voltage, and to tie the P+ doped semiconductor fins formed over the p-well region to the second supply voltage. At step105, implanting and backend processing are performed before the fabrication methodology ends at step106. Such backend processing may include thermal treatments for the implanted regions are applied at some point in the fabrication sequence to activate the implanted regions and otherwise repair implantation damage. In addition, other circuit features may be formed on the wafer structure, such as transistor devices, using one or more of sacrificial oxide formation, stripping, isolation region formation, well region formation, gate dielectric and electrode formation, extension implant, halo implant, spacer formation, source/drain implant, heat drive or anneal steps, and polishing steps, along with conventional backend processing (not depicted), typically including formation of multiple levels of interconnect that are used to connect the transistors in a desired manner to achieve the desired functionality. Thus, the specific sequence of steps used to complete the fabrication of the semiconductor structures may vary, depending on the process and/or design requirements. Accordingly, the fabrication method100provides the overall process flow sequence for making a standard cell design for an ESD protection circuit. It should be understood that certain steps in the process flow sequence100may be performed in parallel with each other or with performing other processes. In addition, the particular ordering of the process flow sequence100may be modified, while achieving substantially the same result. Accordingly, such modifications are intended to be included within the scope of the inventive subject matter. By now it should be appreciated that there has been provided an integrated circuit having a compact standard cell electrostatic discharge (ESD) protection device and associated methods of operation and fabrication for protecting an integrated circuit signal node against transient voltage events using a dual-diode protection scheme implemented with “dummy” n-FinFET and p-FinFET devices formed with centered well taps to integrate seamlessly within the standard cell integrated circuit. As disclosed, the integrated circuit includes a signal node connected to receive an electrostatic discharge voltage from a transmitting circuit. In selected embodiments, the transmitting circuit may include an input signal pad, pin or functional circuit. In addition, the integrated circuit includes an electrostatic discharge (ESD) protection circuit connected between a first voltage supply and a second voltage supply, where the ESD protection circuit includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply. As fabricated, the first and second FinFET diodes are each formed with a finFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node. In selected embodiments, the first FinFET diode may be a p-FinFET diode formed with a p-FinFET device connected between the first voltage supply and the signal node, and the second FinFET diode may be a n-FinFET diode formed with a n-FinFET device connected between the second voltage supply and the signal node. The integrated circuit also includes a protected circuit having a first FinFET operably coupled to the signal node that is protected against electrostatic discharge voltage damage by the electrostatic discharge protection circuit. In selected embodiments, the electrostatic discharge protection circuit may be a standard cell design which includes a centrally located n-well tap positioned internally between first and second portions of the first FinFET diode formed, respectively, with a pair of p-FinFET devices. The standard cell design may also include a centrally located p-well tap positioned internally between first and second portions of the second FinFET diode formed, respectively, with a pair of n-FinFET devices. In selected embodiments, the standard cell design may also include a passive input element connected between the transmitting circuit and the signal node. In other embodiments, the standard cell design may also include the protected circuit. In such embodiments, the protected circuit may be positioned on one or more peripheral ends of the standard cell. In another form, there is provided an integrated circuit device and method of manufacture and operation wherein a compact standard cell electrostatic discharge (ESD) protection circuit block is operably connected in a standard cell to protect a functional circuit block against electrostatic discharge events at a signal node. As disclosed, the electrostatic discharge protection circuit block has a set of layout properties which include adjacent n-well and p-well regions extending across the standard cell. In selected embodiments, the adjacent n-well and p-well regions are formed in a single row standard cell. The layout properties also include a tap region which includes a n-well tie located in a central section of the n-well region for connecting the n-well to a first supply voltage, and a p-well tie located in a central section of the p-well region for connecting the p-well to a second supply voltage. In addition, the layout properties include a dummy FinFET diode layout region positioned on at least a first side of the tap region to include (1) a first p-FinFET formed in the n-well region and connected as a first diode between the first supply voltage and the signal node with the gate, source, and drain regions shorted of the first p-FinFET shorted to the signal node, and (2) a second n-FinFET formed in the p-well region and connected as a second diode between the second supply voltage and the signal node with the gate, source, and drain regions of the second n-FinFET shorted to the signal node. In selected embodiments, the dummy FinFET diode layout region is positioned on opposite sides of the tap region. In addition, selected embodiments of the first diode include (1) a first diode terminal formed in the n-well region of the first p-FinFET, and (2) a second diode terminal formed by shorting the gate, source, and drain regions of the first p-FinFET to the signal node. In selected embodiments, the dummy FinFET diode layout region may include a plurality of first p-FinFETs formed in the n-well region and connected as the first diode, and a plurality of second n-FinFETs formed in the p-well region and connected as the second diode. In addition, selected embodiments of the second diode include (1) a first diode terminal formed in the p-well region of the second n-FinFET, and (2) a second diode terminal formed by shorting the gate, source, and drain regions of the second n-FinFET to the signal node. In selected embodiments, the functional circuit block is included in the standard cell and peripherally positioned on at least one side of the tap region. In such embodiments, the dummy FinFET diode layout region may be positioned in the standard cell on opposite sides of the tap region, and the functional circuit block is positioned in the standard cell on outermost peripheral sides of the dummy FinFET diode layout region. In other embodiments, the functional circuit block and dummy FinFET diode layout region share an active P+ area and active N+ area in which the first p-FinFET and second n-FinFET are respectively formed. In selected embodiments, the layout properties may also include a passive input element in the standard cell which is connected between the signal node and an output of the transmitting circuit. In addition or in the alternative, the layout properties may include active break areas separating the tap region from the dummy FinFET diode layout region. In selected embodiments, the n-well tie is positioned between first and second portions of the dummy FinFET diode layout region which each include a first p-FinFET formed in the n-well region and connected as the first diode, and where the p-well tie is positioned between first and second portions of the dummy FinFET diode layout region which each include a first n-FinFET formed in the p-well region and connected as the second diode. In yet another form, there is provided an integrated circuit and method of manufacturing same. As disclosed, the fabrication method includes receiving a standard cell design for an electrostatic discharge (ESD) protection circuit comprising a signal node and an ESD protection circuit block operably coupled to protect a functional circuit block against electrostatic discharge events at the signal node. In addition, the fabrication method includes using a sequence of fabrication processing steps to form the standard cell as an integrated circuit having set of layout properties. As formed, the layout properties include adjacent n-well and p-well regions extending across the standard cell. The layout properties also include a tap area having a n-well tie located in a central section of the n-well region for connecting the n-well to a first supply voltage, and a p-well tie located in a central section of the p-well region for connecting the p-well to a second supply voltage. In addition, the layout properties include a dummy FinFET diode layout area positioned on at least a first side of the tap region. As formed, the dummy FinFET diode layout area includes a first p-FinFET formed in the n-well region and connected as a first diode between the first supply voltage and the signal node with the gate, source, and drain regions shorted of the first p-FinFET shorted to the signal node. The dummy FinFET diode layout area also includes a first n-FinFET formed in the p-well region and connected as a second diode between the second supply voltage and the signal node with the gate, source, and drain regions of the first n-FinFET shorted to the signal node. In selected embodiments, the sequence of fabrication processing steps for forming the standard cell includes obtaining a semiconductor substrate and selectively implanting a single row standard cell area of the semiconductor substrate with the n-well and p-well regions. The sequence of fabrication processing steps also includes selectively forming a plurality of semiconductor fins on the semiconductor substrate extending up from the n-well and p-well regions. As formed, the plurality of semiconductor fins includes P+ doped semiconductor fins formed over the n-well region in one or more defined P+ active areas of the dummy FinFET diode layout area; N+ doped semiconductor fins formed over the n-well region in the tap area; N+ doped semiconductor fins formed over the p-well region in one or more defined N+ active areas of the dummy FinFET diode layout area; and P+ doped semiconductor fins formed over the p-well region in the tap area. In addition, the sequence of fabrication processing steps includes selectively forming one or more FinFET gate electrodes aligned perpendicularly to the plurality of semiconductor fins to define the first p-FinFET and first n-FinFET in the dummy FinFET diode layout area. Finally, the sequence of fabrication processing steps includes selectively forming one or more metal interconnect layers over the substrate to connect the first p-FinFET as the first diode, to connect the first n-FinFET as the second diode, to tie the N+ doped semiconductor fins formed over the n-well region to the first supply voltage, and to tie the P+ doped semiconductor fins formed over the p-well region to the second supply voltage. Although the described exemplary embodiments disclosed herein are directed to an ESD protection cell design and methodology which provides CDM cross-domain protection benefits to the CMOS gates of a functional receiving circuit or block by using a dual-diode “dummy” FinFETs connected as CDM diodes, the present invention is not necessarily limited to the example embodiments which illustrate inventive aspects of the present invention that are applicable to a wide variety of circuit designs and operations. For example, the disclosed ESD protection cell design and methodology can provide HBM protection benefits for CMOS gates of a functional receiving circuit or block. In addition, the protected functional receiving circuit or block is not required to be on a separate domain from the transmitting circuit which generates the transient voltage event. For example, the transmitting circuit and protected functional receiving circuit or block may be connected to the same supply voltage lines VDD, VSS and still generate disruptive transient voltage event when separated from one another by a long signal routing path (e.g., over 100 microns). Thus, the particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Accordingly, the identification of the circuit design and layout configurations provided herein is merely by way of illustration and not limitation and other circuit arrangements may be used in order to provide ESD protection with an area-efficient standard cell design. Accordingly, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form. The preceding merely illustrates the principles of certain examples. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles and are included within their spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure. This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. | 52,948 |
11862626 | DETAILED DESCRIPTION Various exemplary embodiments of the present disclosure are described below with reference to the accompanying figures to enable a person of ordinary skill in the art to make and use the present disclosure. As would be apparent to those of ordinary skill in the art, after reading the present disclosure, various changes or modifications to the examples described herein can be made without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and/or hierarchy of steps in the methods disclosed herein are merely exemplary approaches. Based upon design preferences, the specific order or hierarchy of steps of the disclosed methods or processes can be re-arranged while remaining within the scope of the present disclosure. Thus, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or acts in a sample order, and the present disclosure is not limited to the specific order or hierarchy presented unless expressly stated otherwise. FIG.1illustrates a cross-sectional view of an exemplary wafer stack100for implementing a through substrate resistive component102, in accordance with some embodiments. As shown inFIG.1, the wafer stack100may use a back end-of-line (“BEOL”) fabrication process to fabricate a first conductive interconnect layer113. As such, the first conductive interconnect layer113may be used to interconnect components of integrated circuits (ICs) and other microdevices formed in a front-end-of-line (“FEOL”) portion of a FEOL and mid-end-of-line (“MEOL”) layer101. In other embodiments, the first conductive interconnect layer113may include contacts (pads)115, interconnect wires117, and vertical conductive paths (vias)119suitable for interconnecting the integrated circuits (ICs) and other micro devices formed in the FEOL portion of the FEOL and MEOL layer101. According to one embodiment, the first conductive interconnect layer113may also include contacts, insulating layers, multiple metal levels, and bonding sites configured to interconnect integrated circuits and micro devices fabricated in the FEOL portion of the FEOL and MEOL layer101. In further embodiments, the BEOL fabrication process may use a conductive material, such as aluminum (Al), copper (Cu) or a Cu-based alloy, to create metallization lines and vias in the first conductive interconnect layer113. Moreover, in deep-submicron BEOL processes, the first conductive interconnect layer113may be insulated using the high-density plasma (HDP) oxide that exhibits a good gap filling capability, low dielectric constant, and a low defect density. In further embodiments, the wafer stack100may use a MEOL fabrication process to fabricate the FEOL and MEOL layer101. In some embodiments, the FEOL and MEOL layer101may include gate contacts as well as contact structures fabricated in the source and drain regions of a MEOL portion of a FEOL and MEOL portion of layer101. In some embodiments, the FEOL and MEOL layer101is formed under the first conductive interconnect layer113. In further embodiments, the FEOL portion of the layer101may comprises a semiconductor substrate and the interconnect rails that are partially buried in the semiconductor substrate. In some embodiments, a substrate tap structure having a through substrate resistive component102may also be formed in the FEOL portion of the layer101. In accordance with some embodiments, the through substrate resistive component102may be connected in series with a drain terminal of a transistor formed in the FEOL and MEOL layer101. As such, the resistive component102provides an ESD immunity by enabling the drain of the transistor to tolerate higher ESD voltages and large hot carrier injections. One exemplary advantage of the above mentioned implementation of the substrate tap structure having the through substrate resistive component102is lower process impact and improved epitaxy control compared to prior approaches of extending the train terminal to implement an additional resistance in the FEOL and MEOL layer101. In various embodiments, the wafer stack100may include a backside layer103formed under the front-end-of-line (“FEOL”) and mid-end-of-line (“MEOL”) layer101. In some embodiments, the backside layer103may be formed using a backside back end-of-line (“B-BEOL”) process. In some embodiments, the B-BEOL process may be substantially similar to the BEOL. In further embodiments, the backside layer103may include a power delivery network (“PDN”)111configured to deliver power to the individual integrated circuits and micro devices. In some embodiments, the PDN111is formed under the FEOL and MEOL layer101. Moreover, the power delivery network in the PDN111may be connected to the buried interconnect rails of the FEOL and MEOL layer101by way of metal-filled TSVs (Through-Semiconductor Vias) or by way of damascene-type contacts. Moreover, the FEOL and MEOL layer101may also include layer interconnect vias configured to route signals from the PDN111to the first conductive interconnect layer. In some embodiments, the layer interconnect vias may be shielded from the integrated circuits and their interconnections formed in the FEOL and MEOL layer101. In some embodiments, the backside layer103may include one or more metal interconnect levels. As such, the one or more metal interconnect levels of backside layer103may be composed of copper (Cu), aluminum (Al) or an alloy thereof such as, for example, a Cu—Al alloy. The one or more metal interconnect levels can be formed utilizing a deposition process such as, for example, CVD, PECVD, sputtering, chemical solution deposition or plating. As illustrated inFIG.1, a passive component105may be formed in the backside layer103. In some embodiments, the backside layer103may be used to pattern the passive component105of a voltage-controlled oscillator (VCO), analog-to-digital converter (ADC), or filter. In some embodiments, the passive component105may be an inductor, capacitor, resistor, or a networks comprising of interconnected inductors, capacitors, and resistors. For example, the passive component105may be a planer resistor. As another example, the passive component105may be a vertical resistance with a tunable resistance values located between the metal interconnect levels. In yet another example, the passive component105may be a vertical parallel plate Metal-Oxide-Metal (MOM) capacitor formed on the one or more metal interconnect levels. In some embodiments, the MOM capacitor may be formed using multiple interdigitated fingers formed on the one or more metal interconnect levels. In further embodiments, the wafer stack100may also include multiple solder bump terminals109, called bump pads, which are used as the input/output (I/O) terminals as well as power supply (VDD and VSS) contacts. In one embodiment, the solder bump pads109may be formed over the bottom surface of the backside layer103. In some embodiments, the solder bump pads109may be linearly aligned bump pad arrays, where each linearly aligned bump pad array may have one or more I/O bump pads, one or more VDD bump pads, and one or more VSS bump pads. The relatively large resistive component102connected between the drain and PDN111provides improved protection against ESD events supplied at the input/output (I/O) terminals or the power supply (VDD and VSS) contacts109. As such, the resistive voltage drop across the resistive component102shields the drain terminal of the transistor from being directly stressed by the ESD pulse. More specifically, the resistive component102provides enough length to keep the voltage drop across it below a maximum nondestructive drain voltage. FIG.2illustrates a cross-sectional view of an exemplary FET device200with a drain terminal209connected in series with the through substrate resistive component102, in accordance with some embodiments. In some embodiments, the FET device200includes a gate terminal205, a source terminal211, and a drain terminal209. In some embodiments, a first contact terminal of the through substrate resistive component102may be connected to the PDN implemented in a backside layer201and a second contact terminal of the through substrate resistive component102may be connected to the drain terminal209through an interconnect207. Furthermore, the resistive component may be connected to the power supply VDD/VSS contacts215, through the PDN. In some embodiments, the interconnect207may be formed in a MEOL portion of a FEOL and MEOL layer203. The FEOL and MEOL layer203is fabricated in a substantially similar fashion as the FEOL and MEOL layer103described inFIG.1above. In some embodiments, the backside layer201may be formed below the FEOL and MEOL layer203. In further embodiments, the backside layer201may have multiple layers and may be formed by any method known in the art, including, but not limited to, chemical vapor deposition, sputter deposition, plating, and the like. In further embodiments, passive components of various other integrated circuits such as VSOs, ADCs, or filters may also be formed in the backside layer201using one or more layers of aluminum (Al), copper (Cu), or titanium, a layer silicon dioxide (SiO2), and a layer of high-resistance polysilicon. In some embodiments, substrate resistive component102may be implemented using a through-silicon via (TSV) fabrication process. In some embodiments, a length and width of the resistive component102may be selected to achieve a desired resistance value. In further embodiments, the resistive component102may have a tapered profile for achieving the desired resistance value. FIGS.3A-3Eillustrate cross-sectional views of a portion of a semiconductor device during a back side back end-of-line (“B-BEOL”) fabrication process, in accordance with some embodiments. In some embodiments, at a first stage of the B-BEOL fabrication process, a semiconductor structure may include a silicon (Si) substrate layer301with a structured masking layer303as shown in a cross-sectional view300aofFIG.3A. In accordance with some embodiments, the masking layer303may be, for example, an oxide or a nitride layer. This mask layer303may be deposited on the top side surface302of the silicon substrate301. According to some embodiments, at a second stage of the B-BEOL fabrication process, the semiconductor structure may include an etch mask, i.e., photoresist mask that is formed to expose the portion of the masking layer303that are to be etched to expose the underlying surface of the base semiconductor substrate301for a seed surface305for an epitaxial growth307as shown in a cross-sectional view300bofFIG.3B. In some embodiments, the etch process may be an anisotropic etch process, such as reactive ion etch (RIE). Other anisotropic etch processes that are suitable at this stage of the present disclosure include ion beam etching, plasma etching or laser ablation. In some embodiments, at least one resistive component is formed in the epitaxial growth structure307. At a third stage of the B-BEOL fabrication process, a back end-of-line (“BEOL”) layer311may be formed on top of the epitaxial growth structure307. In other embodiments, the BEOL layer311includes contacts (pads), interconnect wires, and vertical conductive paths (vias) suitable for interconnecting the integrated circuits (ICs) and other microdevices as shown in a cross-sectional view300cofFIG.3C. In further embodiments, at a fourth stage of the B-BEOL process, polishing processes, such as a chemical mechanical polishing (CMP) process may be used to polish a bottom surface309of the silicon substrate301as shown in a cross-sectional view300dofFIG.3D. At the fourth stage, the bottom surface309of the silicon substrate301is finished to clear the substrate surface309of any active ingredients from the polishing process. At the fifth stage of the B-BEOL process, the backside layer315may be formed on the semiconductor structure as shown in a cross-sectional view300eofFIG.3E. In some embodiments, a process of forming backside layer315may be substantially similar to the BEOL process. In further embodiments, the backside layer315may include a power delivery network (“PDN”) configured to deliver power to the individual integrated circuits and micro devices. In some embodiments, the backside layer315may also include one or more metal interconnect levels. As shown inFIG.3, a resistive component317may be formed between the BEOL layer311and the backside layer315. In some embodiments, the resistive component317may be connected to the drain terminal of a transistor and the power supply VDD/VSS contacts, through the PDN. FIG.4illustrates a flow diagram of a method of forming an electrostatic discharge (ESD) protection device, in accordance with some embodiments. Although the exemplary method shown inFIG.4is described in relation toFIGS.1-3, it will be appreciated that this exemplary method is not limited to such structures disclosed inFIGS.1-3and may stand alone independent of the structures disclosed inFIGS.1-3. In addition, some operations of the exemplary method illustrated inFIG.4may occur in different orders and/or concurrently with other operations or events apart from those illustrated and/or described herein. Moreover, not all illustrated operations may be required to implement one or more aspects or embodiments of the present disclosure. Further, one or more of the operations depicted herein may be carried out in one or more separate operations and/or phases. At operation401, a field effect transistor (FET) may be formed during a front-end-of-line (FEOL) process. In some embodiments, during the FEOL process, the layer203(FIG.2) may be formed which may comprise of a semiconductor substrate and formed FET. In further embodiments, a plurality of transistors may be formed on the semiconductor substrate. Moreover, the plurality of transistors may be connected in series between a high power supply rail and a low power supply rail. In some embodiments, the formed transistor devices may be part of an ESD power claim circuit, VSO, ADC, input/output buffer, or filter. At operation403, a metal interconnect layer (e.g.,113ofFIG.1) may be formed during a back-end-of-line (BEOL) process. In some embodiments, the metal interconnect layer may be used to interconnect the FET and other micro-devices formed during the FEOL process. In other embodiments, the metal interconnect layer may include contacts (pads), interconnect wires, and vertical conductive paths (vias) suitable for interconnecting the plurality of transistors. According to one embodiment, the metal interconnect layer may also include contacts, insulating layers, multiple metal levels, and bonding sites configured to interconnect the plurality of transistors. In further embodiments, during the operation403, a conductive material, such as aluminum (Al), copper (Cu) or a Cu-based alloy, may be used to create metallization lines and vias. At operation405, a backside layer, such as backside layer201(FIG.2) may be formed under the formed FET formed during the FEOL process at operation401. More specifically, the backside layer may be formed at a bottom surface of a semiconductor surfaced used for patterning the FET. In some embodiments, the backside layer may be formed by a backside back-end-of-line (B-BEOL) process that is substantially similar to the BEOL process. In some embodiments, the backside layer may include a power delivery network (PDN) layer that is configured to deliver power to the plurality of transistor devices formed during the operation401. In some embodiments, the one or more metal interconnect levels comprising of copper (Cu), aluminum (Al) or an alloy thereof such as, for example, a Cu—Al alloy may be formed in the backside layer. In addition, the one or more metal interconnect levels can be formed utilizing a deposition process such as, for example, CVD, PECVD, sputtering, chemical solution deposition or plating. At operation407, a through substrate resistive component102(FIG.2) is formed between the FEOL and B-BEOL layers. In some embodiments, a first contact of the through substrate resistive component may be connected to a drain terminal of the FET and a second contact of the through substrate resistive component is connected, through the PDN111(FIG.1), to a power supply rail. In further embodiments, at operation407, a resistance of the through substrate resistive component is configured to provide an ESD immunity for the FET to enable the drain of the FET to tolerate high ESD voltages. In accordance with some embodiments, a length and a width of the through substrate resistive component may be determined based on a predetermined resistance value that is desired to provide an ESD immunity during an ESD event. While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. Likewise, the various diagrams may depict an example architectural or configuration, which are provided to enable persons of ordinary skill in the art to understand exemplary features and functions of the present disclosure. Such persons would understand, however, that the present disclosure is not restricted to the illustrated example architectures or configurations, but can be implemented using a variety of alternative architectures and configurations. Additionally, as would be understood by persons of ordinary skill in the art, one or more features of one embodiment can be combined with one or more features of another embodiment described herein. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments. It is also understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient means of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element in some manner. Additionally, a person having ordinary skill in the art would understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits and symbols, for example, which may be referenced in the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. A person of ordinary skill in the art would further appreciate that any of the various illustrative logical blocks, modules, processors, means, circuits, methods and functions described in connection with the aspects disclosed herein can be implemented by electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two), firmware, various forms of program or design code incorporating instructions (which can be referred to herein, for convenience, as “software” or a “software module), or any combination of these techniques. To clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software, or a combination of these techniques, depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in various ways for each particular application, but such implementation decisions do not cause a departure from the scope of the present disclosure. In accordance with various embodiments, a processor, device, component, circuit, structure, machine, module, etc. can be configured to perform one or more of the functions described herein. The term “configured to” or “configured for” as used herein with respect to a specified operation or function refers to a processor, device, component, circuit, structure, machine, module, signal, etc. that is physically constructed, programmed, arranged and/or formatted to perform the specified operation or function. Furthermore, a person of ordinary skill in the art would understand that various illustrative logical blocks, modules, devices, components and circuits described herein can be implemented within or performed by an integrated circuit (IC) that can include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, or any combination thereof. The logical blocks, modules, and circuits can further include antennas and/or transceivers to communicate with various components within the network or within the device. A processor programmed to perform the functions herein will become a specially programmed, or special-purpose processor, and can be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other suitable configuration to perform the functions described herein. If implemented in software, the functions can be stored as one or more instructions or code on a computer-readable medium. Thus, the steps of a method or algorithm disclosed herein can be implemented as software stored on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program or code from one place to another. A storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In this document, the term “module” as used herein, refers to software, firmware, hardware, and any combination of these elements for performing the associated functions described herein. Additionally, for purpose of discussion, the various modules are described as discrete modules; however, as would be apparent to one of ordinary skill in the art, two or more modules may be combined to form a single module that performs the associated functions according embodiments of the present disclosure. Various modifications to the implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other implementations without departing from the scope of this disclosure. Thus, the disclosure is not intended to be limited to the implementations shown herein, but is to be accorded the widest scope consistent with the novel features and principles disclosed herein, as recited in the claims below. | 23,507 |
11862627 | DETAILED DESCRIPTION Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout. Throughout the disclosure, the expression “at least one of ‘a’, ‘b’ or ‘c’” indicates only ‘a’, only ‘b’, only ‘c’, both ‘a’ and ‘b’, both ‘a’ and ‘c’, both ‘b’ and ‘c’, all of ‘a’, ‘b’, and ‘c’, or variations thereof. Referring toFIG.1, the display device1includes a display area DA and a peripheral area PA outside the display area DA. The display device1may provide an image via the display area DA. The display device1may be a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a quantum dot light-emitting display, a field emission display, a surface-conduction electron-emitter display, a plasma display, a cathode ray display or the like. Hereinafter, an organic light-emitting display device will be described as an example of the display device1according to an embodiment FIGS.2A and2Billustrate cross-sectional views of a display device according to embodiments. Referring toFIGS.2A and2B, the display device1may include a display unit (or display panel)10, an input sensor40, an anti-reflection layer50, and a window60. The display10generates an image. The display10may generate a predetermined image by using red, green, blue or white light emitted from, for example, organic light-emitting diodes (OLEDs). The input sensor40may acquire coordinate information according to an external input, for example, a touch event. The input sensor40may be arranged above the display10and under the anti-reflection layer50, as illustrated inFIG.2A, or above the anti-reflection layer50, as illustrated inFIG.2B. The input sensor40may include a sensing electrode (or touch electrode) and a signal line (trace line) connected to the sensing electrode. According to an embodiment, the input sensor40may be disposed directly on the display unit10. The description “input sensor40disposed directly on the display unit10” indicates that no additional adhesive layer is interposed between the input sensor40and the display unit10and that elements of the input sensor40are directly patterned on the display unit10. In some implementations, the input sensor40may be formed in a separate process from the display unit10and then combined to the display unit10by using an adhesive material layer or the like. The anti-reflection layer50may reduce reflectivity of light incident from the outside onto the display unit10through the window60. The anti-reflection layer50may be disposed on the input sensor40as illustrated inFIG.2Aor under the input sensor40as illustrated inFIG.2B. According to an embodiment, the anti-reflection layer50may include a polarizer, a phase retarder, or the like. In some implementations, the anti-reflection layer50may include a black matrix and a color filter. When the anti-reflection layer50includes a polarizer or the like, the polarizer may be relatively thick. In this case, the anti-reflection layer50may be attached to the display unit10or the input sensor40using an adhesive material layer or the like. When the anti-reflection layer50includes a black matrix and a color filter, the anti-reflection layer50may have a relatively small thickness. In this case, the anti-reflection layer50may be directly disposed on the display unit10or the input sensor40. The window60may include a light transmitting area61corresponding to the display area DA and a light shielding area62corresponding to the peripheral area PA. FIGS.3A and3Billustrate cross-sectional views schematically illustrating a display unit according to an embodiment. Referring toFIG.3A, the display unit10may include a display element layer200disposed on a substrate100and an encapsulation member300covering the display element layer200. The substrate100may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate100maybe in a form of a single layer or may be a multi-layer structure of the above materials. In the case of a multi-layer structure, the substrate100may further include an inorganic layer. The substrate100may have flexible, rollable or bendable characteristics. The display element layer200includes pixels. Each pixel may include an organic light-emitting diode and a pixel circuit electrically connected to the organic light-emitting diode. The pixel circuit may include a thin film transistor and a storage capacitor and lines connected thereto. The pixel circuit may also include one or more insulating layers. The encapsulation member300may protect the display element layer200from external foreign substances such as moisture. The encapsulation member300may include a thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer may include, for example, a silicon oxide layer, a silicon nitride layer or/and a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic encapsulation layer may include, for example, an acrylic based organic material. WhileFIG.3Aillustrates that the encapsulation member300, which is a thin film encapsulation layer, includes first and second inorganic encapsulation layers310and330and an organic encapsulation layer320interposed therebetween, in some implementations, the stacking order of inorganic encapsulation layers and organic encapsulation layers or the like may be varied. Also, the encapsulation member300may be other than a thin film encapsulation layer. Referring toFIG.3B, the display unit10may include an encapsulation member300′ including a sealant310′ and an encapsulation substrate320′. The substrate100as illustrated inFIG.3Bmay include the above-described polymer resin, or may include glass or the like. The encapsulation substrate320′ may be disposed to face the substrate100, and a sealant310′ may be disposed between the substrate100and the encapsulation substrate320′. The sealant310′ may surround the display area DA. An inner space defined by the substrate100, the encapsulation substrate320′, and the sealant310′ may be separated from the outer space and penetration of moisture or impurities thereinto may be reduced or prevented. The encapsulation substrate320′ may include the above-described polymer resin or glass or the like, and a material such as a frit or an epoxy may be used as the sealant310′. FIG.4illustrates a plan view of a display unit according to an embodiment, andFIG.5illustrates an equivalent circuit diagram of a pixel according to an embodiment. Referring toFIG.4, the display unit10may include pixels P arranged in the display area DA. The pixels P may include a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC, as illustrated inFIG.5. A pixel electrode (e.g., an anode) of the organic light-emitting diode OLED may be connected to the pixel circuit PC. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may be connected to a second power ELVSS. The organic light-emitting diode OLED may emit light of a predetermined luminance based on a current supplied from the pixel circuit PC. The pixel circuit PC may include a thin film transistor and a capacitor. The pixel circuit PC may include first through fourth thin film transistors T1, T2, T3, and T4and a storage capacitor Cst, as illustrated inFIG.5. A gate electrode of the first thin film transistor T1may be connected to a scan line SL. A first electrode of the first thin film transistor T1may be connected to a data line DL, and a second electrode of the first thin film transistor T1may be connected to the storage capacitor Cst. The first thin film transistor T1may be turned on when a scan signal is supplied to the scan line SL. A gate electrode of the second thin film transistor T2may be connected to the storage capacitor Cst. A first electrode of the second thin film transistor T2may be connected to the storage capacitor Cst and a first power ELVDD. The second thin film transistor T2may control an amount of current flowing from the first power ELVDD to the second power ELVSS via the organic light-emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may generate light corresponding to the amount of current supplied from the second thin film transistor T2. A gate electrode of the third thin film transistor T3may be connected to an emission control line EL. A first electrode of the third thin film transistor T3may be connected to a second electrode of the second thin film transistor T2, and a second electrode of the third thin film transistor T3may be connected to the organic light-emitting diode OLED. The third thin film transistor T3may be turned off when an emission control signal is supplied to the emission control line EL and may be turned on when no emission control signal is supplied. The emission control signal may be supplied during a period during which a voltage corresponding to a data signal is charged in the storage capacitor Cst and during a period during which deterioration information of the organic light-emitting diode OLED is sensed. The fourth thin film transistor T4may be a sensing transistor and may be turned on during a period of a current sensing operation of the organic light-emitting diode OLED. A gate electrode of the fourth thin film transistor T4may be connected to a control line CL. A first electrode of the fourth thin film transistor T4may be connected to the second electrode of the third thin film transistor T3. A second electrode of the fourth thin film transistor T4may be connected to the data line DL. The fourth thin film transistor T4may be turned on when a control signal is supplied to the control line CL, and may be turned off otherwise. A control signal may be supplied during a period during which deterioration information of the organic light-emitting diode OLED is sensed. FIG.5illustrates an embodiment in which the pixel P includes four thin film transistors and one storage capacitor In some implementations, the pixel circuit PC may be include two, three or five or more thin film transistors or include two or more storage capacitors. Referring back toFIG.4, the peripheral area PA of the display unit10may surround the display area DA. The peripheral area PA may correspond to a non-display area that does not provide an image. A scan driving circuit110as a first peripheral circuit, a control driving circuit120as a second peripheral circuit, a terminal140, a first power supply wiring (or a first power voltage wiring)160, and a second power supply wiring (or a second power voltage wiring)170may be disposed in the peripheral area PA. The scan driving circuit110may be disposed on the peripheral area PA of the substrate100. The scan driving circuit110may be electrically connected to the scan line SL and may supply a predetermined scan signal to the scan line SL. According to an embodiment, when the pixel P includes the third thin film transistor T3that corresponds to an emission control thin film transistor as described with reference toFIG.5, the scan driving circuit110may supply an emission control signal to the emission control line EL. The control driving circuit120may be disposed on the peripheral area PA of the substrate100. The scan driving circuit110and the control driving circuit120may be arranged in parallel with each other with the display area DA therebetween. The scan driving circuit110may be disposed at a first side of the display area DA, and the control driving circuit120may be disposed at a second side of the display area DA opposite to the first side. The terminal140may be disposed at one end of the substrate100. The terminal140may not be covered by an insulating layer but be exposed and electrically connected to a printed circuit board PCB. The terminal140may be disposed on a side of the peripheral area PA where the scan driving circuit110and the control driving circuit120are not located. For example, the terminal140may be disposed in parallel with a third side of the display area DA. Terminal140may be connected to the scan driving circuit110via line111. Terminal140also may be connected to the control driving circuit120via line112. A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal140of the display unit10. The printed circuit board PCB may provide a signal of a controller or may provide power to the display unit10. Control signals generated in the controller may be transmitted to each of the scan driving circuit110(using line111) and the control driving circuit120(using line112) via the printed circuit board PCB. The controller may respectively provide the first power ELVDD and the second power ELVSS (seeFIG.5) to the first and second power supply wirings160and170through first and second connection wirings161and171. The first power ELVDD may be provided to each of the pixels P through a driving voltage line PL connected to the first power supply wiring160, and the second power ELVSS may be provided to opposite electrodes of the pixels P connected to the second power supply wiring170. The data driving circuit150may be electrically connected to the data line DL. A data signal of the data driving circuit150may be provided to each pixel P through a wiring151connected to the terminal140and a data line DL connected to the wiring151. The data driving circuit150may be disposed on the printed circuit board PCB, as illustrated inFIG.4. In some implementations, the data driving circuit150may be disposed on the substrate100. For example, the data driving circuit150may be disposed between the terminal140and the first power supply wiring160illustrated inFIG.4. The first power supply wiring160and the second power supply wiring170may be disposed in the peripheral area PA. The first power supply wiring160may be disposed adjacent to the third side of the display unit10. The second power supply wiring170may partially surround the display area DA along an edge of the display area DA. For example, the second power supply wiring170may have the form of an incomplete loop in which one side is open. The second power supply wiring170may be connected to the second connection wiring171that is connected to the terminal140. The second connection wiring171may have the form of an incomplete loop extending to partially surround the display area DA and being open at one side.FIG.4illustrates that, like the second power supply wiring170, the second connection wiring171may extend along a first side (left side inFIG.4), a fourth side (upper side inFIG.4), and a second side (right side inFIG.4) of the display area DA. In some implementations, the second connection wiring171may be connected only to an end of the second power supply wiring170. For example, a pair of second connection wirings171may be each connected to both ends of the second power supply wiring170adjacent to the third side of the display area DA. FIGS.6A through6Cillustrates plan views schematically depicting the input sensor40according to embodiments. Referring toFIG.6A, the input sensor40may include first sensing electrodes410, first signal lines415-1through415-4connected to the first sensing electrodes410, second sensing electrodes420, and second signal lines425-1through425-5connected to the second electrodes420. The input sensor40may sense an external input by using a mutual capacitance method or/and a self capacitance method. The first sensing electrodes410may be arranged in a y-direction, and the second sensing electrodes420may be arranged in an x-direction crossing the y-direction. The first sensing electrodes410arranged along the y-direction may respectively form first sensing lines410C1through410C4by connecting through a first connection electrode411, and the second sensing electrodes420arranged along the x-direction may respectively form second sensing lines420R1through420R5by connecting through a second connection electrode421. The first sensing lines410C1through410C4and the second sensing lines420R1through420R5may intersect each other. For example, the first sensing lines410C1through410C4and the second sensing lines420R1through420R5may be perpendicular to each other. The first sensing lines410C1through410C4and the second sensing lines420R1through420R5may be disposed on the display area DA and may be connected to a sensing signal pad440via the first and second signal lines415-1through415-4and425-1through425-5in the peripheral area PA. The first sensing lines410C1through410C4may be respectively connected to the first signal lines415-1through415-4, and the second sensing lines420R1through420R5may be respectively connected to the second signal lines425-1through425-5. The first signal lines415-1through415-4may each be connected to both an upper portion and a lower portion of the first sensing lines410C1through410C4, respectively, as illustrated inFIG.6A. Sensing sensitivity may be increased according to this structure. In some implementations, the first signal lines415-1through415-4may be connected to either the upper portion or the lower portion of the first sensing lines410C1through410C4. In some implementations, each of the first signal lines415-1through415-4may be simultaneously connected to both the upper and lower portions of the first sensing lines410C1through410C4, respectively, while also connected to the sensing signal pad440, as illustrated inFIG.6B. In some implementations, each of the second sensing lines420R1through420R5may be connected to the second signal lines425-1to425-5that are respectively provided on the left and right sides, as illustrated inFIG.6C. A layout of the first and second signal lines415-1to415-4and425-1through425-5may be provided in the peripheral area PA. In some implementations, the layout may be modified in according to the shape or size of the display area DA or a sensing method of the input sensor40. FIGS.7A and7Billustrate schematic cross-sectional views corresponding to line VII-VII′ ofFIG.6Aand depicting the second signal lines425-1through425-5, The first signal lines415-1through415-4may have the same cross-sectional structure as that of the second signal lines425-1through425-5.FIGS.7A and7Billustrate five second signal lines425-1through425-5as an example. Referring to one second signal line425-1illustrated inFIG.7A, the second signal line425-1may include a first signal line portion425aand a second signal line portion425b. The first and second signal line portions425aand425bmay be overlap with each other between insulating layers IL1, IL2, and IL3, and may be connected through a contact hole420H to reduce resistance. According to an embodiment, in the second signal line425-1, one of the first and second signal line portions425aand425bthat are formed on a different layer with the insulating layer420included therebetween inFIG.7Amay be omitted. For example, as illustrated inFIG.7B, the second signal line425-1may include a second signal line portion425b, and may further include a third signal line portion425cthereon. The second signal line425-1may be a conductive multi-layer in which, for example, a transparent conductive layer is disposed on the metal layer. According to an embodiment, the second signal line425-1may be a single layer. FIG.8illustrates a cross-sectional view of a display device according to an embodiment, in which a display unit and an input sensor overlap each other.FIG.9AandFIG.9Brespectively illustrate partial plan views depicting first and second shielding layers ofFIG.8.FIG.9Cillustrate a plan view depicting a state in which the first and second shielding layers overlap each other.FIG.8corresponds to a cross-section taken along line VIII-VIII′ ofFIG.4andFIG.6A. Referring to the display area DA ofFIG.8, the display element layer200and the encapsulation member300may be disposed on the substrate100. A buffer layer201may be formed on the substrate100. The buffer layer201may block penetration of foreign substances or moisture through the substrate100. The buffer layer201may include, for example, an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride, and may be formed as a single layer or as a multilayer. A thin film transistor TFT, a storage capacitor Cst, and an organic light-emitting diode OLED that is electrically connected to these elements may be disposed on the substrate100. The thin film transistor TFT may include a semiconductor layer Act and a gate electrode GE. The semiconductor layer Act may include polysilicon, amorphous silicon, an oxide semiconductor, an organic semiconductor material or the like. In an embodiment, the semiconductor layer Act may include a channel region CR overlapping the gate electrode GE and a source region CR and a drain region DR that are on opposite sides of the channel region CR and include an impurity having a higher concentration than the channel region CR. The impurity may include an N-type impurity or a P-type impurity. The source region SR and the drain region DR may be respectively understood as a source electrode and a drain electrode of the thin film transistor TFT. A gate insulating layer202may be disposed between the semiconductor layer Act and the gate electrode GE. The gate insulating layer202may be an inorganic layer such as silicon oxynitride, silicon oxide and/or silicon nitride, and the inorganic layer may be a single layer or a multilayer. The storage capacitor Cst may include first and second storage capacitor plates CE1and CE2overlapping each other. A first interlayer insulating layer203may be disposed between the first and second storage capacitor plates CE1and CE2. The first interlayer insulating layer203may have a predetermined permittivity. The first interlayer insulating layer203may be an inorganic layer such as silicon oxynitride (SiON), silicon oxide (SiOx), and/or silicon nitride (SiNx), and may be in a form of a single layer or a multilayer. In some implementations, the storage capacitor Cst may overlap the thin film transistor TFT and the first storage capacitor plate CE1may also be the gate electrode GE of the thin film transistor TFT, as illustrated inFIG.8. In some implementations, the storage capacitor Cst may not overlap with the thin film transistor TFT. Instead, the first storage capacitor plate CE1may be a separate independent component from the gate electrode GE of the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer204. The second interlayer insulating layer204may be an inorganic layer such as silicon oxynitride, silicon oxide, and/or silicon nitride, and may be in a form of a single layer or a multilayer. A driving voltage line PL may include a first driving voltage line PL1and a second driving voltage line PL2. The first driving voltage line PL1may include a same material as the data line DL. For example, the first driving voltage line PL1and the data line DL may include aluminum (Al), copper (Cu), titanium (Ti) or the like, and may be formed as a multilayer or single layer. In an embodiment, the first driving voltage line PL1and the data line DL may have a multilayer structure of Ti/Al/Ti. The second driving voltage line PL2may be disposed on the first driving voltage line PL1with the first insulating layer206therebetween. The second driving voltage line PL2may be electrically connected to the first driving voltage line PL1through a contact hole defined in the first insulating layer206. The second driving voltage line PL2may include aluminum (Al), copper (Cu), titanium (Ti) or the like, and may be formed as a multilayer or a single layer. In an embodiment, the second driving voltage line PL2may have a multilayer structure of Ti/Al/Ti. The first insulating layer206may include an organic insulating material such as, for example, an imide-based polymer, a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an aryl-ether based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or blends thereof. For example, the first insulating layer206may include polyimide. The driving voltage line PL may be covered by the second insulating layer207. The second insulating layer207may include an organic insulating material. For example, the second insulating layer207may include an imide-based polymer, polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an aryl-ether based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and blends thereof. According to an embodiment, the second insulating layer207may include polyimide. A pixel electrode221may be disposed on the second insulating layer207. A pixel defining layer208may be disposed on the pixel electrode221. The pixel defining layer208may have an opening corresponding to each pixel, for example, an opening exposing a portion of the pixel electrode221to thereby define each pixel. In addition, the pixel defining layer208may increase a distance between an edge of the pixel electrode221and the opposite electrode223to thereby prevent an arc or the like between the edge of the pixel electrode221and the opposite electrode223. The pixel defining layer208may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO). The intermediate layer222may include a low molecular material or a polymer material. When the intermediate layer222includes a low molecular material, the intermediate layer222may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL) or the like are stacked in a single structure or in a composite structure. The intermediate layer222may include various organic materials such as copper phthalocyanine (CuPc), N,N-di(naphthalene-N, N′-diphenyl-benzidine) (NPB), or tris-8-hydroxyquinoline aluminum (Alq3). These layers may be formed using a vacuum deposition method. When the intermediate layer222includes a polymer material, the intermediate layer222may typically have a structure including a hole transport layer (HTL) and an emission layer (EML). The hole transport layer may include PEDOT, and the emission layer may include a polymer material such as a poly-phenylenevinylene (PPV)-based material and a polyfluorene-based material. The intermediate layer222may have various structures. For example, at least one of the layers of the intermediate layer222may be integrally formed over a plurality of pixel electrodes221. In some implementations, the intermediate layer222may include layers that are patterned to respectively correspond to the plurality of pixel electrodes221. The opposite electrode223may be disposed above the display area DA and may be arranged to cover the display area DA. For example, the opposite electrode223may be integrally formed to cover a plurality of pixels. The encapsulation member300may be, for example, a thin film encapsulation layer. The encapsulation member300may cover the organic light-emitting diode OLED and may prevent damage that could occur due to moisture or oxygen penetrating from the outside. The thin film encapsulation layer may cover the display area DA and extend to the outside of the display area DA. The thin film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.FIG.8illustrates an embodiment in which the thin film encapsulation layer includes a first inorganic encapsulation layer310, an organic encapsulation layer320, and a second inorganic encapsulation layer330. A plurality of layers including a capping layer230may be interposed between the first inorganic encapsulation layer310and the opposite electrode223. WhileFIG.8illustrates that the capping layer230is provided, according to some implementations, the capping layer230may be omitted. When the capping layer230is omitted, the first inorganic encapsulation layer310may include at least two silicon oxynitride (SiON) layers having different properties. The first inorganic encapsulation layer310may be formed along the elements formed under the same. Accordingly, the first inorganic encapsulation layer310may have an uneven top surface. The organic encapsulation layer320may cover the first inorganic encapsulation layer310. Unlike the top surface of the first inorganic encapsulation layer310, a top surface of the organic encapsulation layer320may be substantially flat. For example, the top surface of the organic encapsulation layer320may be substantially flat in a portion corresponding to the display area DA. A sensing electrode may be disposed on the encapsulation member300. In this regard,FIG.8schematically illustrates the first sensing electrode410on the encapsulation member300. An insulating layer may be further disposed below and above the first sensing electrode410inFIG.8. In some implementations, the first sensing electrode410may include multiple layers. The first sensing electrode410may include an opening4100P corresponding to a light-emitting region of the organic light-emitting diode OLED such that light of the organic light-emitting diode OLED may be emitted to the outside. Referring to the peripheral area PA ofFIG.8, an inorganic insulating layer210may be disposed on the substrate100. The inorganic insulating layer210may include at least one of the buffer layer201, the gate insulating layer202, the first interlayer insulating layers203or the second interlayer insulating layers204described above. A second connection wiring171may be disposed on the inorganic insulating layer210. The second connection wiring171may include a same material as the data line DL and/or the first driving voltage line PL1, and may be disposed on a same level as the data line DL and/or the first driving voltage line PL1. The scan driving circuit110may be disposed on the substrate100. The scan driving circuit110may include thin film transistors TFT-P and may include a wiring connected to the thin film transistors TFT-P. The thin film transistors TFT-P may be formed in the same process as the thin film transistor TFT of the pixel circuit PC. The scan driving circuit110may include an insulating layer interposed between the elements of the thin film transistors TFT-P (for example, a semiconductor layer, a gate electrode, etc.). In an implementation, the scan driving circuit110may be covered by an inorganic protection layer205. The scan driving circuit110may overlap a first shielding layer1170and a second shielding layer1270disposed above the scan driving circuit110. The first shielding layer1170may be disposed above the scan driving circuit110with the first insulating layer206therebetween, and the second shielding layer1270may be disposed above the first shielding layer1170with the second insulating layer207therebetween. The first shielding layer1170may be disposed on a same level as and include a same material as the second driving voltage line PL2. The second shielding layer1270may be disposed on a same level as and include a same material as the pixel electrode221. A first width W1of the first shielding layer1170and a second width W2of the second shielding layer1270may be equal to or greater than a width of the scan driving circuit110, as shown inFIG.8. At least one of the first shielding layer1170or the second shielding layer1270may include a hole. One shielding layer of the first and second shielding layers1170and1270may includes a hole that overlaps the other shielding layer. In an embodiment, the first shielding layer1170may include first holes1170H as illustrated inFIGS.8and9A. The first holes1170H may be spaced apart from one another on a plane. The second shielding layer1270may include second holes1270H as illustrated inFIGS.8and9B. The second holes1270H may be spaced apart from each other on a plane. Each of the first and second holes1170H and1270H may be an outgassing passage of the first and second insulating layers206and207, which are disposed under the first and second shielding layers1170and1270. Accordingly, issues that may arise when the first and second holes1170H and1270H are not included, such as, for example, damage to the first and second shielding layers1170and1270or to the organic light-emitting diode OLED by gas in the first and second insulating layers206and207may be prevented or minimized. The first holes1170H and the second holes1270H may be arranged to be offset from each other in a plan view. As illustrated inFIGS.8and9C, a center of the first hole1170H and a center of the second hole1270H may be offset from each other and not coincident with each other. The first hole1170H and the second hole1270H may not overlap each other in a plan view. The first hole1170H of the first shielding layer1170may overlap with a portion1270P of the second shielding layer1270, and the second hole1270H of the second shielding layer1270may overlap with a portion1170P of the first shielding layer1170. In the present specification, the term “a portion of a shielding layer” refers to an area with no hole, formed of a same material for forming the shielding layer. Accordingly, the portion1170P of the first shielding layer1170may be regarded as a portion of the first shielding layer1170except where the first holes1170H are located, and the portion1270P of the second shielding layer1270may be regarded as a portion of the second shielding layer1270except where the second holes1270H are located. As described above, when one shielding layer that includes a hole overlapping a portion of the other shielding layer, when projected in a direction (z direction) perpendicular to a main surface of the substrate100, and where a hole in one shielding layer does not overlap any hole in the other shielding layer in a plan view (looking at the display device from the z direction), the scan driving circuit110may be entirely covered by the first and second shielding layers1170and1270. Damage to the scan driving circuit110that could occur due to external electrostatic discharge (ESD) may be prevented by the first and second shielding layers1170and1270. The first and second shielding layers1170and1270may have a same voltage level. Referring toFIG.8, the first and second shielding layers1170and1270may be electrically connected to the second connection wiring171. The first shielding layer1170may contact the second connection wiring171through an opening2060P of the first insulating layer206that exposes the second connection wiring171. The second shielding layer1270may contact the first shielding layer1170through an opening2070P of the second insulating layer207. The first and second shielding layers1170and1270electrically connected to the second connection wiring171may form a second power supply wiring170. The opposite electrode223may be connected to the second shielding layer1270. Accordingly, the second power ELVSS (see, for example,FIG.5) of the second power supply wiring170may be supplied to the opposite electrode223as. An end of the opposite electrode223may pass by a dummy pixel DPX and extend to the peripheral area PA. The opposite electrode223may contact the second shielding layer1270via a hole208H in a portion of the pixel defining layer208that extends to the peripheral area PA. As illustrated inFIG.8, the end of the opposite electrode223may extend toward an outer edge of the substrate100to cover at least a portion of the scan driving circuit110. A signal line connected to a sensing electrode may be disposed in the peripheral area PA. As illustrated inFIG.8, the second signal lines425-1through425-4may be arranged on the peripheral area PA. At least one of the second signal lines425-1through425-4may overlap the scan driving circuit110. The opposite electrode223and the first and second shielding layers1170and1270may be interposed between the scan driving circuit110and the second signal lines425-1through425-4. In a general display device, a signal generated in a scan driving circuit could affect signal lines of an input sensor located on a scan driving circuit. In this case, accuracy of an input sensor could be reduced. However, according to embodiments, the opposite electrode223covers a portion of the scan driving circuit110. Accordingly, the impact of a signal (e.g., noise) of the scan driving circuit110on the second signal lines425-1through425-4may be minimized. As a comparative example, if an effort were to be made to reduce or prevent signal interference caused by a scan driving circuit and affecting signal lines using only the opposite electrode223, the opposite electrode223would have to entirely cover the scan driving circuit110. Thus, the opposite electrode223would have to extend farther toward an edge of the substrate100, and in turn, the peripheral area PA, which is a dead zone, would have to be increased. As another comparative example, if an end of the opposite electrode223were disposed as illustrated inFIG.8to reduce the peripheral area PA, it could be difficult to place a signal line of the input sensor in an area RA corresponding to a portion between the end of the opposite electrode223and the edge of the substrate100. However, according to an embodiment, when the first and second shielding layers1170and1270are located between the second signal line425-1and the scan driving circuit110on the above-described area RA, an impact of a signal of the scan driving circuit110(e.g., noise) on the second signal line425-1may be prevented or minimized. Accordingly, a signal line, for example, the second signal line425-1, may also be arranged in the above-described area RA. In addition, when the scan driving circuit110and signal lines are disposed by fully utilizing the peripheral area PA as described above, the peripheral area PA, which is a dead zone, may be reduced. According to an embodiment, the first and second insulating layers206and207disposed in the peripheral area PA may respectively include valley holes206VH and207VH. Damage to the organic light-emitting diode OLED or the like due to penetration of external foreign matters through bulk of each of the first and second insulating layers206and207may be prevented through valley holes206VH and207VH.FIG.8illustrates that at least one dam180may be provided on the outer edge of the substrate100. The dam180may prevent a monomer, used in a process of forming the organic encapsulation layer320, from extending toward the end of the substrate100, thereby reducing or preventing the formation of edge tails of the organic encapsulation layer320.FIG.8illustrates a thin film encapsulation layer as the encapsulation member300, In some implementations, the encapsulation member300′ including the sealant310′ and the encapsulation substrate320′ may be included instead of the thin film encapsulation layer as described above with reference toFIG.3B. FIG.8illustrates an arrangement of the first shielding layer1170, the second shielding layer1270, and the second signal lines425-1through425-4with respect to the scan driving circuit110as a peripheral circuit disposed in the peripheral area PA. In some implementations, a stack structure on the control driving circuit120illustrated inFIG.4may also be substantially the same as the structure illustrated inFIG.8. For example, regarding the stack structure on the control driving circuit120, it may be understood that the control driving circuit120may be arranged instead of the scan driving circuit110ofFIG.8. The first signal line415-1through415-4(seeFIGS.6A and6B) or the second signal lines425-1through425-4(seeFIG.6C) may be disposed on the control driving circuit120to overlap with the control driving circuit120. FIG.10illustrates a plan view schematically depicting a display unit10′ according to another embodiment.FIG.11illustrates a partial plan view of a switching circuit130ofFIG.10and a portion around the switching circuit130.FIG.12illustrates a cross-sectional view of a display device according to another embodiment, in which a display unit and an input sensor overlap each other.FIG.12may correspond to a cross-section taken along line XII-XII′ ofFIG.11. The display unit10′ ofFIG.10may be substantially the same as the display unit10described above with reference toFIG.4, except that the display unit10′ further includes the switching circuit130as a third peripheral circuit. Thus, description will focus on the differences below. The display unit10′ may include a switching circuit130. The switching circuit130may be electrically connected to the data driving circuit150and a data line of a pixel. The switching circuit130may include a demultiplexer(s) demuxing a data signal output from the data driving circuit150and supplying the demuxed data signal to data lines. The switching circuit130may be disposed between the third side of the display area DA and the first power supply wiring160. For example, the switching circuit130may be disposed between the first power supply wiring160and an auxiliary power supply wiring162. The first power supply wiring160and the auxiliary power supply wiring162may be spaced apart from each other with the switching circuit130therebetween. The switching circuit130may overlap with a third shielding layer2170and a fourth shielding layer2270on the scan driving circuit110. A third width W3of the third shielding layer2170and a fourth width W4of the fourth shielding layer2270may be each equal to or greater than a width of the switching circuit130. The third width W3and the fourth width W4may be greater than the width of the switching circuit130, as illustrated inFIG.11. As illustrated inFIG.12, the third shielding layer2170may be disposed above the switching circuit130with the first insulating layer206therebetween, and the fourth shielding layer2270may be disposed above the third shielding layer2170with the second insulating layer207therebetween. As described with reference toFIG.8, the third shielding layer2170may be disposed on a same layer level as and include a same material as a second driving voltage line (PL2, seeFIG.8), and the fourth shielding layer2270may be disposed on a same level as and include a same material as a pixel electrode (221, seeFIG.8). At least one of the third shielding layer2170or the fourth shielding layer2270may include a hole. One shielding layer of the third and fourth shielding layers2170and2270that includes the hole may overlap the other shielding layer. The third shielding layer2170may have holes2170H and a portion2170P having a predetermined area. The fourth shielding layer2270may have fourth holes2270H and a portion2270P having a predetermined area. Each of the third and fourth holes2170H and2270H may serve as an outgassing passage of the first and second insulating layers206and207disposed under the third and fourth shielding layers2170and2270. The third holes2170H and the fourth holes2270H may be arranged to be offset from each other. As illustrated inFIG.12, a center of the third hole2170H and a center of the fourth hole2270H may be offset from each other and not coincident with each other. The third hole2170H and the fourth hole2270H may not overlap each other. For example, the third hole2170H of the third shielding layer2170may overlap with a portion2270P of the fourth shielding layer2270, and the fourth hole2270H of the fourth shielding layer2270overlaps with a third portion2170P of the third shielding layer2170. Thus, when projected in a direction perpendicular to the main surface of the substrate100, the switching circuit130may be entirely covered by the third and fourth shielding layers2170and2270. The third and fourth shielding layers2170and2270may have a same voltage level. The third and fourth shielding layers2170and2270may be electrically connected to the first power supply wiring160, as illustrated inFIG.12. The third and fourth shielding layers2170and2270may electrically connect the first power supply wiring160and the auxiliary power supply wiring162. The third shielding layer2170may contact the first power supply wiring160and the auxiliary power supply wiring162through a first contact hole206H1and a second contact hole206H2of the first insulating layer206. The fourth shielding layer2270may contact the third shielding layer2170through a third contact hole207H1and a fourth contact hole207H2of the second insulating layer207. The first power ELVDD (FIG.5) of the first power supply wiring160may be supplied to driving voltage lines of a pixel connected to the auxiliary power supply wiring162. A signal line of the input sensor40may be disposed on the switching circuit130. First signal lines415-1and415-2may be arranged on the peripheral area PA, as illustrated inFIG.12. At least one of the first signal lines415-1and415-2may overlap the switching circuit130. The third and fourth shielding layers2170and2270having the above-described structure may be interposed between the switching circuit130and the first signal lines415-1and415-2. Accordingly, an undesirable impact of a signal generated in the switching circuit130on the first signal lines415-1and415-2may be prevented or minimized. In some implementations, a display unit10″ may include the encapsulation member300′ described above with reference toFIG.3Binstead of a thin film encapsulation layer. FIGS.10through12illustrate that shielding layers on the switching circuit130, for example, the third and fourth shielding layers2170and2270are provided with a voltage corresponding to the first power ELVDD. In some implementations, shielding layers on the switching circuit130may be provided with a voltage corresponding to the second power ELVSS. FIG.13illustrates a plan view schematically illustrating a display unit10″ according to another embodiment, andFIG.14illustrates a partial plan view of a switching circuit130ofFIG.13and a portion around the switching circuit130.FIG.15illustrates a cross-sectional view illustrating a display device according to another embodiment, in which a display unit and an input sensor overlap each other.FIG.15corresponds to a cross-section taken along line XV-XV′ ofFIG.14. The display unit10″ ofFIG.13further includes the switching circuit130as a third peripheral circuit. The display unit10″ ofFIG.13is substantially the same as the display unit10described above with reference toFIG.4, except that first and second shielding layers1170′ and1270′ extend onto the switching circuit130Thus, descriptions thereof will focus on the differences below. The first and second shielding layers1170′ and1270′ may surround the display area DA entirely, as shown inFIG.13. For example, the first and second shielding layers1170′ and1270′ may be disposed to overlap the scan driving circuit110, the control driving circuit120, and the switching circuit130. A portion of the first and second shielding layers1170′ and1270′ overlapping the scan driving circuit110and the control driving circuit120may have a structure as described with reference toFIG.8, and thus, the description provided with reference toFIG.8and the like may be referred to regarding the structure. Hereinafter, overlapping between the first and second shielding layers1170′ and1270′ and the switching circuit130will be described. The first and second shielding layers1170′ and1270′ may be disposed on the switching circuit130. A first width W1′ of the first shielding layer1170′ and a second width W2‘of the second shielding layer1270’, each overlapping with the switching circuit130, may be equal to or greater than a width of the switching circuit130. InFIG.14, the first width W1′ and the second width W2′ may be greater than the width of the switching circuit130. As illustrated inFIG.15, the first shielding layer1170′ may be disposed on the switching circuit130with the first insulating layer206therebetween, and the second shielding layer1270′ may be disposed on the first shielding layer1170′ with the second insulating layer207therebetween. At least one of the first shielding layer1170′ or the second shielding layer1270′ may include a hole. One shielding layer of the first and second shielding layers1170′ and1270′ that includes the hole may overlap the other shielding layer. According to an embodiment, as illustrated inFIG.15, the first shielding layer1170′ may include first holes1170H′ and a portion1170P′ having a predetermined area, and the second shielding layer1270′ may include second holes1270H′ and a portion1270P′ having a predetermined area. The first holes1170H′ and the second holes1270H′ may be arranged to be offset from each other. As illustrated inFIG.15, a center of the first hole1170H′ and a center of the second hole1270H′ may be offset from each other and not coincident with each other. The first hole1170H′ and the second hole1270H′ may not overlap each other. The first hole1170H′ of the first shielding layer1170′ overlaps with the portion1270P′ of the second shielding layer1270′, and the second hole1270H′ of the second shielding layer1270′ overlaps with the portion1170P′ of the first shielding layer1170′. Thus, when projected in a direction perpendicular to a main surface of the substrate100, the switching circuit130may be entirely covered by the first and second shielding layers1170′ and1270′. The first and second shielding layers1170′ and1270′ may be electrically connected to the second connection wiring171as illustrated inFIG.13, as described above with reference toFIGS.4and8. A signal line of the input sensor may be disposed on the switching circuit130. In this regard,FIG.15illustrates first signal lines415-1and415-2arranged on the peripheral area PA. At least one of the first signal lines415-1and415-2may overlap with the switching circuit130. The first and second shielding layers1170′ and1270′ may be interposed between the switching circuit130and the first signal lines415-1and415-2. Accordingly, impact of a signal generated in the switching circuit130on the first signal lines415-1and415-2may be prevented or minimized. A thin film encapsulation layer is illustrated as the encapsulation member300inFIGS.13through15. In some implementations, the display unit10″ may include the encapsulation member300′ described above with reference toFIG.3B, instead of a thin film encapsulation layer. By way of summation and review, display devices include various circuits for providing an image. The circuits may be arranged in an area, generally referred to as a peripheral area or “dead zone” outside of the area where the image is provided. If general effort were to be made to reduce a size of the dead zone, a circuit arranged in a dead zone of a display device might overlap with various wirings, giving rise to the possibility that the circuit arranged in the dead zone could be damaged when the circuit is exposed to external static electricity. In addition, signal interference caused the circuit and wirings could decrease the quality of the display device. One or more embodiments include a display device that prevents damages to circuits and also signal interference with other wirings (for example, signal lines of an input sensor). According to embodiments, damage to the display device may be prevented or minimized through outgassing of the organic insulating layer, and damage to the peripheral circuit due to static electricity or the like may be prevented or minimized, or interference of signal lines of the input sensor due to a signal of the peripheral circuit may be prevented or minimized. Accordingly, a high-quality display device may be provided. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope thereof as set forth in the following claims. | 54,026 |
11862628 | DETAILED DESCRIPTION Memory devices may include various arrangements of memory arrays and supporting circuitry formed over a substrate. For example, a memory device may include one or more decks of one or more memory arrays over a substrate, where a deck may refer to a plane or level of memory cells (e.g., of a memory array) above and parallel to the substrate. In some examples, substrate-based circuitry that supports accessing or operating the memory arrays may be located below the memory arrays, which may refer to a location that is at least in part between the memory arrays and the substrate (e.g., in a vertical direction). For example, sensing circuitry, decoding circuitry, periphery circuitry, or other logic and circuitry may be located below the memory arrays but above the substrate and, in some examples, may include transistors that are formed at least in part by doping portions of the substrate (e.g., substrate-based transistors, transistors having channels formed from doped crystalline silicon or another semiconductor substrate). But as memory devices scale with a greater quantity of layers or decks of memory arrays above a substrate, the area of a substrate used for such substrate-based circuitry may increase, which may lead to various limitations (e.g., related to the limited area of a substrate to support a growing quantity of decks and, by extension, a growing quantity and area for such substrate-based circuitry, related to routing challenges associated with locating some circuitry below a stack of decks but not above the stack of decks). In accordance with examples as disclosed herein, a memory device may include a stack of decks of memory cells and circuitry for accessing or operating the stack of decks (e.g., substrate-based circuitry, CMOS circuitry) with some being located above the stack of decks and some being located below the stack of decks. For example, the memory device may include lower substrate-based circuitry formed at least in part by doping portions of a lower semiconductor substrate (e.g., a first or base substrate, a silicon substrate, a crystalline semiconductor substrate) to form a first set of transistors. Above the lower substrate-based circuitry, the memory device may include a stack of decks of memory cells and an upper semiconductor substrate (e.g., a second or supplemental substrate) bonded above the stack of decks. The upper substrate-based circuitry may be formed at least in part by doping portions of the upper semiconductor substrate to form a second set of transistors. The stack of decks may include a lower set of one or more decks that is coupled with the lower substrate-based circuitry and an upper set of one or more decks that is coupled with the upper substrate-based circuitry. A combination of lower substrate-based circuitry and upper substrate-based circuitry may support accessing or operating of the decks of memory cells in accordance with various techniques. In some examples, circuitry that is common to or shared by at least some if not each deck of the stack of decks (e.g., input/output circuitry, backend circuitry) may be coupled with lower substrate-based circuitry and upper substrate-based circuitry. Implementing substrate-based circuitry above and below a stack of decks of memory cells of a memory device may increase an area available for substrate-based circuitry compared to memory devices that include a single level of substrate-based circuitry, which may support leveraging substrate materials for a greater quantity of components or larger components, for circuitry such as sensing circuitry, decoding circuitry, or periphery circuitry, among other circuitry used for accessing or otherwise operating memory arrays of a memory device. In some examples, implementing such circuitry in multiple levels of substrate-based circuitry of a memory die may alleviate or mitigate area utilization challenges or routing challenges of a single substrate level, which may improve scaling in memory devices by supporting a greater quantity of decks for a given footprint, among other advantages. Features of the disclosure are initially described in the context of a memory device and related circuitry as described with reference toFIGS.1and2. Features of the disclosure are described in the context of a memory device layout and illustrative fabrication techniques with reference toFIGS.3-8. These and other features of the disclosure are further illustrated by and described with reference to flowcharts that relate to transistor configurations for multi-deck memory devices as described with references toFIGS.9and10. FIG.1illustrates an example of a memory device100that supports transistor configurations for multi-deck memory devices in accordance with examples as disclosed herein. The memory device100may also be referred to as an electronic memory apparatus. The memory device100may include memory cells105that are programmable to store different logic states. In some cases, a memory cell105may be programmable to store two logic states, denoted a logic 0 and a logic 1. In some cases, a memory cell105may be programmable to store more than two logic states (e.g., as a multi-level cell). The set of memory cells105may be part of a memory array110of the memory device100, where, in some examples, a memory array110may refer to a contiguous tile of memory cells105(e.g., a contiguous set of elements of a semiconductor chip). In some examples, a memory cell105may store an electric charge representative of the programmable logic states (e.g., storing charge in a capacitor, capacitive memory element, capacitive storage element). In one example, a charged and uncharged capacitor may represent two logic states, respectively. In another example, a positively charged (e.g., a first polarity, a positive polarity) and negatively charged (e.g., a second polarity, a negative polarity) capacitor may represent two logic states, respectively. DRAM or FeRAM architectures may use such designs, and the capacitor employed may include a dielectric material with linear or para-electric polarization properties as an insulator. In some examples, different levels of charge of a capacitor may represent different logic states, which, in some examples, may support more than two logic states in a respective memory cell105. In some examples, such as FeRAM architectures, a memory cell105may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between terminals of the capacitor. Different levels or polarities of polarization of a ferroelectric capacitor may represent different logic states (e.g., supporting two or more logic states in a respective memory cell105). In some examples, a memory cell105may include or otherwise be associated with a configurable material, which may be referred to as a material memory element, a material storage element, a material portion, and others. The configurable material may have one or more variable and configurable characteristics or properties (e.g., material states) that may represent different logic states. For example, a configurable material may take different forms, different atomic configurations, different degrees of crystallinity, different atomic distributions, or otherwise maintain different characteristics that may be leveraged to represent one logic state or another. In some examples, such characteristics may be associated with different electrical resistances, different threshold characteristics, or other properties that are detectable or distinguishable during a read operation to identify a logic state written to or stored by the configurable material. In some cases, a configurable material of a memory cell105may be associated with a threshold voltage. For example, electrical current may flow through the configurable material when a voltage greater than the threshold voltage is applied across the memory cell105, and electrical current may not flow through the configurable material, or may flow through the configurable material at a rate below some level (e.g., according to a leakage rate), when a voltage less than the threshold voltage is applied across the memory cell105. Thus, a voltage applied to memory cells105may result in different current flow, or different perceived resistance, or a change in resistance (e.g., a thresholding or switching event) depending on whether a configurable material portion of the memory cell105was written with one logic state or another. Accordingly, the magnitude of current, or other characteristic (e.g., thresholding behavior, resistance breakdown behavior, snapback behavior) associated with the current that results from applying a read voltage to the memory cell105, may be used to determine a logic state written to or stored by memory cell105. In the example of memory device100, each row of memory cells105may be coupled with one or more word lines120(e.g., WL1through WLM), and each column of memory cells105may be coupled with one or more digit lines130(e.g., DL1through DLN). Each of the word lines120and digit lines130may be an example of an access line of the memory device100. In general, one memory cell105may be located at the intersection of (e.g., coupled with, coupled between) a word line120and a digit line130. This intersection may be referred to as an address of a memory cell105. A target or selected memory cell105may be a memory cell105located at the intersection of an energized or otherwise selected word line120and an energized or otherwise selected digit line130. In some architectures, a storage component of a memory cell105may be electrically isolated (e.g., selectively isolated) from a digit line130by a cell selection component, which, in some examples, may be referred to as a switching component or a selector device of or otherwise associated with the memory cell105. A word line120may be coupled with the cell selection component (e.g., via a control node or terminal of the cell selection component), and may control the cell selection component of the memory cell105. For example, the cell selection component may be a transistor and the word line120may be coupled with a gate of the transistor (e.g., where a gate node of the transistor may be a control node of the transistor). Activating a word line120may result in an electrical connection or closed circuit between a respective logic storing component of one or more memory cells105and one or more corresponding digit lines130. A digit line130may then be accessed to read from or write to the respective memory cell105. In some examples, memory cells105may also be coupled with one or more plate lines140(e.g., PL1through PLN). In some examples, each of the plate lines140may be independently addressable (e.g., supporting individual selection or biasing). In some examples, the plurality of plate lines140may represent or be otherwise functionally equivalent with a common plate, or other common node (e.g., a plate node common to each of the memory cells105in the memory array110). When a memory cell105employs a capacitor for storing a logic state, a digit line130may provide access to a first terminal or a first plate of the capacitor, and a plate line140may provide access to a second terminal or a second plate of the capacitor. Although the plurality of plate lines140of the memory device100are shown as substantially parallel with the plurality of digit lines130, in other examples, a plurality of plate lines140may be substantially parallel with the plurality of word lines120, or in any other configuration (e.g., a common planar conductor, a common plate layer). Access operations such as reading, writing, rewriting, and refreshing may be performed on a memory cell105by activating or selecting a word line120, a digit line130, or a plate line140coupled with the memory cell105, which may include applying a voltage, a charge, or a current to the respective access line. Upon selecting a memory cell105(e.g., in a read operation), a resulting signal may be used to determine the logic state stored by the memory cell105. For example, a memory cell105with a capacitive memory element storing a logic state may be selected, and the resulting flow of charge via an access line or resulting voltage of an access line may be detected to determine the programmed logic state stored by the memory cell105. Accessing memory cells105may be controlled using a row component125(e.g., a row decoder), a column component135(e.g., a column decoder), or a plate component145(e.g., a plate decoder), or a combination thereof. For example, a row component125may receive a row address from the memory controller170and activate the appropriate word line120based on the received row address. Similarly, a column component135may receive a column address from the memory controller170and activate the appropriate digit line130. In some examples, such access operations may be accompanied by a plate component145biasing one or more of the plate lines140(e.g., biasing one of the plate lines140, biasing some or all of the plate lines140, biasing a common plate). In some examples, the memory controller170may control operations (e.g., read operations, write operations, rewrite operations, refresh operations) of memory cells105using one or more components (e.g., row component125, column component135, plate component145, sense component150). In some cases, one or more of the row component125, the column component135, the plate component145, and the sense component150may be co-located or otherwise included with the memory controller170. The memory controller170may generate row and column address signals to activate a desired word line120and digit line130. The memory controller170may also generate or control various voltages or currents used during the operation of memory device100. A memory cell105may be read (e.g., sensed) by a sense component150when the memory cell105is accessed (e.g., in cooperation with the memory controller170) to determine a logic state written to or stored by the memory cell105. For example, the sense component150may be configured to evaluate a current or charge transfer through or from the memory cell105, or a voltage resulting from coupling the memory cell105with the sense component150, responsive to a read operation. The sense component150may provide an output signal indicative of the logic state read from the memory cell105to one or more components (e.g., to the column component135, the I/O component160, to the memory controller170). A sense component150may include various switching components, selection components, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify a difference in sensing signals (e.g., a difference between a read voltage and a reference voltage, a difference between a read current and a reference current, a difference between a read charge and a reference charge), which, in some examples, may be referred to as latching. In some examples, a sense component150may include a collection of components (e.g., circuit elements) that are repeated for each of a set of digit lines130connected to the sense component150. For example, a sense component150may include a separate sensing circuit (e.g., a separate or duplicated sense amplifier, a separate or duplicated signal development component) for each of a set of digit lines130coupled with the sense component150, such that a logic state may be separately detected for a respective memory cell105coupled with a respective one of the set of digit lines130. A memory cell105may be set, or written, by activating the relevant word line120, digit line130, or plate line140(e.g., via a memory controller170). In other words, a logic state may be stored in a memory cell105. A row component125, a column component135, or a plate component145may accept data, for example, via input/output component160, to be written to the memory cells105. In some examples, a write operation may be performed at least in part by a sense component150, or a write operation may be configured to bypass a sense component150. In the case of a capacitive memory element, a memory cell105may be written by applying a voltage to or across a capacitor, and then isolating the capacitor (e.g., isolating the capacitor from a voltage source used to write the memory cell105, floating the capacitor) to store a charge in the capacitor associated with a desired logic state. In the case of ferroelectric memory, a ferroelectric memory element (e.g., a ferroelectric capacitor) of a memory cell105may be written by applying a voltage with a magnitude sufficient to polarize the ferroelectric memory element (e.g., applying a saturation voltage) with a polarization associated with a desired logic state, and the ferroelectric memory element may be isolated (e.g., floating), or a zero net voltage or bias may be applied across the ferroelectric memory element (e.g., grounding, virtually grounding, or equalizing a voltage across the ferroelectric memory element). In the case of a material memory architecture, a memory cell105may be written by applying a current, voltage, or other heating or biasing to a material memory element to configure the material according to a corresponding logic state. In some examples, the memory device100may include multiple memory arrays110arranged in a stack of decks or levels relative to a substrate of the memory device100(e.g., a semiconductor substrate, a crystalline silicon substrate, a crystalline semiconductor substrate, a portion of a semiconductor wafer). In some cases, circuitry that supports accessing or operating the multiple memory arrays110(e.g., substrate-based circuitry, CMOS circuitry) may be located below the memory arrays110, which may refer to a location that is at least in part between the memory arrays110and the substrate. For example, one or more row components125, one or more column components135, one or more plate components145, one or more sense components150, or one or more I/O components160, or any combination thereof, may be located below the memory arrays110and above the substrate and, in some examples, may include transistors that are formed at least in part by doping portions of the substrate (e.g., substrate-based transistors, transistors having channels formed from doped crystalline silicon or other semiconductor). When scaling the memory device100with a greater quantity of decks or levels of memory arrays110, the area of a substrate used for supporting circuitry may increase, which may lead to scaling limitations (e.g., related to the limited area of a substrate to support circuitry for accessing a growing quantity of decks or levels of memory arrays110and, by extension, a growing quantity and area for such decoders or other supporting circuitry, related to routing challenges associated with locating certain circuitry below a stack of decks but not above the stack of decks), among other challenges. In accordance with examples as disclosed herein, the memory device100may include multiple memory arrays110arranged in a stack of decks formed above a substrate (e.g., a first substrate, a lower substrate), and substrate-based circuitry formed both above and below the stack of decks to support accessing or operating the memory arrays110. For example, the memory device100may include lower substrate-based circuitry formed in part by doping portions of a lower substrate to form a first (e.g., lower) set of transistors. Above the lower substrate-based circuitry, the memory device100may include the stack of decks and an upper substrate bonded above the stack of decks. Upper substrate-based circuitry may be formed at least in part by doping portions of the upper substrate to form a second (e.g., upper) set of transistors. The stack of decks may include a lower set of one or more decks that are coupled with the lower substrate-based circuitry and an upper set of one or more decks that are coupled with the upper substrate-based circuitry. A combination of lower substrate-based circuitry and upper substrate-based circuitry may support accessing or operating of the decks of memory cells in accordance with various techniques. For example, circuitry associated with a row component125, a column component135, a plate component145, or a sense component150, among other components or circuitry, may be divided between or distributed among lower substrate-based circuitry and upper substrate-based circuit, including various allocations of circuitry associated with operating certain decks of a stack of decks of memory arrays110. In some examples, circuitry that is common to or shared by each deck of the stack (e.g., one or more portions of an input/output component160, or a memory controller170, among other components or circuitry) may be coupled with lower substrate-based circuitry and upper substrate-based circuitry and, in some examples, may be formed above the upper substrate-based circuitry. Implementing substrate-based circuitry (e.g., CMOS circuitry) above and below a stack of decks of memory arrays110may increase an area available for substrate-based circuitry compared to memory devices that include a single level of substrate-based circuitry. Such techniques may support the memory device100leveraging substrate materials (e.g., crystalline semiconductor materials) for a greater quantity of components, or larger components, for circuitry such as sensing circuitry, decoding circuitry, or periphery circuitry, among other circuitry used for accessing or otherwise operating memory arrays of a memory device. In some examples, implementing such circuitry in multiple levels of substrate-based circuitry of a memory die may alleviate or mitigate area utilization challenges or routing challenges of a single substrate level, which may improve scaling in memory devices by supporting a greater quantity of decks for a given footprint. Accordingly, utilizing multiple levels of substrate-based circuitry may enable a greater scaling of decks, or improved scaling of memory storage, among other advantages. FIG.2illustrates an example of a transistor structure200that supports thin film transistor deck selection in a memory device in accordance with examples as disclosed herein. The transistor structure200illustrates an example of a transistor that is formed at least in part by portions of a substrate220(e.g., doped portions240of the substrate220), and may illustrate an arrangement of features for a transistor that is configured in a planar transistor arrangement. The substrate220may be a portion of a semiconductor chip, such as a silicon chip of a memory die (e.g., crystalline silicon, monocrystalline silicon), among other examples of substrate material. For illustrative purposes, aspects of the transistor structure200may be described with reference to an x-direction, a y-direction, and a z-direction (e.g., a height direction) of a coordinate system210. In some examples, the z-direction may be illustrative of a direction perpendicular to a surface of the substrate220(e.g., a surface in an xy-plane, a surface upon or over which other materials may be deposited), and each of the structures, illustrated by their respective cross section in an xz-plane, may extend for some distance (e.g., length) in the y-direction. The transistor structure200illustrates an example of a transistor channel, electrically coupled between a terminal270-a-1and a terminal270-a-2, that may include one or more doped portions240of the substrate220. In various examples, one of the terminals270-a-1or270-a-2may be referred to as a source terminal, and the other of the terminals270-a-1or270-a-2may be referred to as a drain terminal, where such a designation may be based on a configuration or relative biasing of a circuit that includes the transistor structure200. The channel (which may also be referred to as the channel portion) of a transistor may include or refer to one or more portions of the transistor structure that are operable to open or close a conductive path (e.g., to modulate a conductivity, to form a channel, to open a channel, to close a channel) between a source and drain (e.g., between the terminal270-a-1and the terminal270-a-2) based at least in part on a voltage of a gate (e.g., a gate terminal, a gate portion250). In other words, a channel portion of a transistor structure may be configured to be activated, deactivated, made conductive, or made non-conductive, based at least in part on a voltage of a gate portion, such as gate portion250. In some examples of transistor structure200(e.g., a planar transistor arrangement), the channel portion formed by one or more doped portions240of the substrate220may support a conductive path in a generally horizontal or in-plane direction (e.g., along the x-direction, within an xy-plane, in a direction within or parallel to a surface of the substrate220). In some examples, the gate portion250may be physically separated from the channel portion (e.g., separated from the substrate220, separated from one or more of the doped portions240) by a gate insulation portion260(e.g., a gate dielectric). Each of the terminals270may be in contact with or otherwise coupled with (e.g., electrically, physically) a respective doped portion240-a, and each of the terminals270and the gate portion250may be formed from an electrically conductive material such as a metal or metal alloy, or a polycrystalline semiconductor (e.g., polysilicon). In some examples, the transistor structure200may be operable as an n-type or n-channel transistor, where applying a relatively positive voltage to the gate portion250that is above a threshold voltage (e.g., an applied voltage having a positive magnitude, relative to a source terminal, that is greater than a threshold voltage) activates the channel portion or otherwise enables a conductive path between the terminals270-a-1and270-a-2(e.g., along a direction generally aligned with the x-direction within the substrate220). In such examples, the doped portions240-amay refer to portions having n-type doping or n-type semiconductor, and doped portion240-bmay refer to portions having p-type doping or p-type semiconductor (e.g., a channel portion having an NPN configuration along the x-direction or channel direction). In some examples, the transistor structure200may be operable as a p-type or p-channel transistor, where applying a relatively negative voltage to the gate portion250that is above a threshold voltage (e.g., an applied voltage having a negative magnitude, relative to a source terminal, that is greater than a threshold voltage) activates the channel portion or otherwise enables a conductive path between the terminals270-a-1and270-a-2. In such examples, the doped portions240-amay refer to portions having p-type doping or p-type semiconductor, and doped portion240-bmay refer to portions having n-type doping or n-type semiconductor (e.g., a channel portion having a PNP configuration along the x-direction or channel direction). In some examples, circuitry operable to support access operations on memory cells105(e.g., a row component125, a column component135, a plate component145, a sense component150, a memory controller170, or various combinations thereof) may be formed from respective sets of transistors each having the arrangement of the transistor structure200, where each of the transistors may have a channel portion formed by respective doped portions240of a substrate220. In some examples, such transistors may leverage a crystalline semiconductor material of the substrate220, or another form of semiconductor material, for various performance characteristics or manufacturing characteristics of such a material or an arrangement. Some examples of such an arrangement may be implemented in a complementary metal-oxide-semiconductor (CMOS) configuration, which may refer to various examples of a complementary and symmetrical pair of a p-type transistor and an n-type transistor (e.g., for logic functions). However, such structures or arrangements of substrate-based transistors may be limited by an available area of the substrate220(e.g., under a memory array110or stack of levels or decks of memory arrays110). In accordance with examples as disclosed herein, a memory device100may include multiple levels of circuitry formed using multiple substrates220. For example, the memory device100may include a first substrate220below a stack of decks of memory arrays110and a second substrate220above the stack of decks. Circuitry operable to support access operations on the stack of decks may include a first set of transistors formed at least in part by doped portions of the first substrate220and a second set of transistors formed at least in part by doped portions of the second substrate220, where transistors of the first set and second set may include the arrangement of the transistor structure200. In some examples, the first set of transistors, or the second set of transistors, or both may include transistors arranged in a CMOS configuration (e.g., in examples of a memory device100including CMOS circuitry located above and below a stack of memory arrays110for accessing the stack of memory arrays110). FIG.3illustrates a layout of a memory device100-athat supports transistor configurations for multi-deck memory devices in accordance with examples as disclosed herein. The memory device100-amay be an example of a memory device100described with reference toFIG.1, and may include multiple levels of substrate-based circuitry (e.g., CMOS circuitry) for accessing and operating multiple decks or levels of memory arrays110-a. For illustrative purposes, aspects of the memory device100-amay be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system301. In some examples, the z-direction may be illustrative of a direction perpendicular to a surface of a substrate220(e.g., a surface in an xy-plane, a surface upon or over which other materials may be deposited), and each of the related regions, illustrated by their respective cross-section in an xz-plane, may extend for some distance along the y-direction. In some examples, the x-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells105), and the y-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells105), or vice versa. Each of the illustrative regions of the memory device100-amay be associated with a region of components or circuitry that may be formed using various techniques. In some examples, functional components such as transistors in various configurations or arrangements within the illustrative regions may be interconnected by routing conductors (e.g., metal conductors) of the respective regions, which may include various arrangements of through-silicon vias (TSVs) or socket conductors that may be aligned along the z-direction, or various arrangements of in-plane conductors that may be aligned in one or more directions parallel to an xy-plane, or combinations thereof. Such interconnection may be associated with signal routing, or power or voltage distribution, among other functions. The memory device100-amay include a lower substrate circuitry region305, which may include first (e.g., lower) substrate-based circuitry (e.g., first CMOS circuitry). The first substrate-based circuitry may include transistors formed at least in part by doping portions of a lower substrate220of the memory device100-a(e.g., a semiconductor substrate, a crystalline silicon substrate, a crystalline semiconductor substrate, a portion of a semiconductor wafer). A substrate220of the lower substrate circuitry region305may be a base or initial substrate220of the memory device100-a, upon which other components or circuitry are formed, and over which another substrate220may be added (e.g., bonded). In some examples, transistors of the lower substrate circuitry region305may include transistors formed or configured in accordance with the transistor structure200, including such transistors in a CMOS arrangement. Above the lower substrate circuitry region305, the memory device100-amay include a stack of decks315-a, where each deck315-amay be located at a different position along the z-direction. The memory device100-aillustrates an example that includes four decks315-a(e.g., decks315-a-1through315-a-4), but a memory device100in accordance with examples as disclosed herein may include any quantity of two or more decks315. Each deck315-amay include a respective memory array110-a, which may include a plurality of memory cells105that are distributed in an xy-plane. In some examples, memory cells105of a memory array110-amay be arranged in rows that are aligned along the x-direction and columns that are aligned along the y-direction. Each of the memory arrays110-amay include respective word lines120(e.g., along the x-direction), digit lines130(e.g., along the y-direction), and plate lines140(e.g., where applicable) for accessing the respective memory cells105, among other circuitry. The memory arrays110-aof the memory device100-amay include memory cells105in accordance with various memory architectures. In some examples, memory cells105of a memory array110-amay each include a respective storage component (e.g., a capacitor) and a respective cell selection component (e.g., a cell selection transistor). In some examples (e.g., in an FeRAM application), capacitors of the memory cells105may be ferroelectric capacitors operable to store a charge or polarization corresponding to a logic state. A ferroelectric material used in a ferroelectric capacitor may be characterized by an electric polarization where the material maintains a non-zero electric charge in the absence of an electric field. In some examples, memory cells105of the memory arrays110-amay include storage elements of different memory architectures, such as linear capacitors (e.g., in a DRAM application), transistors (e.g., in a NAND application, in an SRAM application), or material memory elements (e.g., in a RRAM application or a PCM application, which may include chalcogenide storage elements, resistive storage elements, thresholding storage elements), among other types of storage elements. In some examples, the decks315-amay include various transistors, such as cell selection transistors of or associated with the memory cells105of the respective memory arrays110-a, among other examples. Transistors of the decks315-amay be formed in accordance with various thin film manufacturing techniques, including deposition of polycrystalline semiconductor materials (e.g., polysilicon) over the lower substrate circuitry region305. In some examples, transistors of the decks315-amay include vertical transistors, which may support a respective channel formed at least in part along the z-direction. Above the decks315-a, the memory device100-amay include an upper substrate circuitry region320, which may include second (e.g., upper) substrate-based circuitry (e.g., second CMOS circuitry). The second substrate-based circuitry may include transistors formed at least in part by doping portions of an upper substrate220(e.g., a second substrate) of the memory device100-a. A substrate220of the upper substrate circuitry region320may be a substrate220that is bonded or otherwise deposited over the decks315-a, such as a second portion of crystalline semiconductor (e.g., a portion of a semiconductor wafer, a second portion of monocrystalline silicon). In some examples, transistors of the upper substrate circuitry region320may include transistors formed or configured in accordance with the transistor structure200, including such transistors in a CMOS arrangement. Above the upper substrate circuitry region320, the memory device100-amay include a backend circuitry region340. The backend circuitry region340may include backend circuitry used to route signals for communication with a host device coupled to the memory device100-a, among other signals. The backend circuitry region340may include various circuitry for communicating signals with both the upper substrate circuitry region320and the lower substrate circuitry region305. In some examples, the backend circuitry may include metallic interconnects (e.g., copper interconnects). Above the backend circuitry region340, the memory device100-amay include an I/O circuitry region350. The I/O circuitry region350may include one or more pads360-a(e.g., pads360-a-1through360-a-n, conductive interfaces) that support various coupling or electronic communication between the memory device100-a(e.g., the backend circuitry region340) and a host device (e.g., for signaling associated with read or write commands, among other signaling). In some examples, the pads360-amay be associated with signaling of one or more channels (e.g., data channels, control channels) for communicating information, commands, or diagnostic information between the memory device100-aand a host device. In some examples, the pads360-amay be configured for supplying power or voltages to various components of the memory device100-a, among other purposes. Although the I/O circuitry region350and backend circuitry region340are illustrated as separate regions, in some examples, one or more aspects of an I/O circuitry region350and a backend circuitry region340may be combined in a single region (not shown), such as a single or combined region for interfacing between components of the memory device100-a(e.g., the memory arrays110-a) and a device or system outside the memory device100-a. In some examples, the memory device100-amay include a backend interconnect region330above the lower substrate circuitry region305, which may support interconnection between the lower substrate circuitry region305and the upper substrate circuitry region320, or interconnection between the lower substrate circuitry region305and the backend circuitry region340, or both. The memory device100-amay use circuitry of the lower substrate circuitry region305and the upper substrate circuitry region320to access and operate memory cells105of the memory arrays110-a. In some examples, circuitry of the lower substrate circuitry region305, or circuitry of the upper substrate circuitry region320, or both may include circuitry for performing sense operations, circuitry for performing access operations, circuitry for performing decoding operations, or circuitry for performing I/O operations, or a combination thereof, among other operations. For example, circuitry of the lower substrate circuitry region305, or circuitry of the upper substrate circuitry region320, or both may include one or more portions of a row component125, a column component135, or a plate component145, such as decoders, buffers, multiplexers, or drivers (e.g., word line drivers, sub-word line drivers, digit line drivers, sub-digit line drivers, plate line drivers, sub-plate line drivers, among other drivers), among other circuitry configured to address, decode, or bias access lines of one or more memory arrays110-aof the memory device100-a. Additionally or alternatively, circuitry of the circuitry of the lower substrate circuitry region305, or circuitry of the upper substrate circuitry region320, or both may include one or more portions of a sense component150, such as one or more sense amplifiers, or one or more signal development components, among other circuitry for sensing or writing to memory cells105of the memory device100-a. In some examples, subsets of transistors of the lower substrate circuitry region305, or of the upper substrate circuitry region320, or both may be dedicated or allocated for a given purpose (e.g., function, operation). For example, sensing circuitry may include a subset of transistors that are configured to support sense operations, access circuitry (e.g., row access circuitry, column access circuitry, plate access circuitry) may include a subset of transistors that are configured to support activating or biasing access lines, decoding circuitry may include a subset of transistors that are configured to support decoding operations, I/O circuitry may include a subset of transistors that are configured to support I/O operations, and so on. That is, transistors of the lower substrate circuitry region305, or of the upper substrate circuitry region320, or both may be divided into various subsets of transistors that each support different operations and functions of the memory device100-a. In some examples, one or more portions of the lower substrate circuitry region305may be dedicated or allocated to supporting operation of some memory arrays110-aof the memory device100-abut not others, and one or more portions of the upper substrate circuitry region320may be dedicated or allocated to supporting operation of some memory arrays110-aof the memory device100-abut not others. For example, the decks315-amay be divided into a first set310-a(e.g., a lower set, including decks315-a-1and315-a-2) and a second set310-b(e.g., an upper set, including decks315-a-3and315-a-4). In some examples, a division of the decks315into sets310may refer to how decks315are coupled to substrate-based circuitry of the memory device100-a. For example, a set310-amay refer to any quantity of decks315-athat are coupled at least in part to lower substrate-based circuitry and a set310-bmay refer to any quantity of decks315-athat are coupled at least in part to upper substrate-based circuitry. Although the example of memory device100-aillustrates two sets310having a same quantity of decks315-a, in some examples, a memory device100may include sets310having different quantities of decks315. The components and circuitry of the memory device100-amay be coupled through various interconnection regions370. Each of the interconnection regions370may illustrate portions of the memory device100-athat support electrical coupling or interconnection along at least the z-direction between components or circuitry of the illustrated regions. For example, each interconnection region370may include various arrangements of TSVs or socket conductors that may be aligned along the z-direction. In some examples, the interconnection regions370may include various arrangements of in-plane conductors (e.g., in-plane routing between or among interconnections along the z-direction) that may be aligned in one or more directions parallel to an xy-plane, or combinations thereof. The interconnection region370-amay illustrate an example of a coupling between each of the memory arrays110-aand the lower substrate circuitry region305and the upper substrate circuitry region320. In some examples, the interconnection region370-amay be an example of a word line socket region which may be used to select and activate one or more word lines of each of the decks315-a,315-b,315-c, and315-d. For example, the interconnection region370-amay include interconnects that couple word lines of decks315-a-1through315-a-4to decoders (e.g., row components125) and/or word line drivers (e.g., sub-word line drivers) included in the lower substrate circuitry region305, in the upper substrate circuitry region320, or both. Although the interconnection region370-aillustrates coupling between the memory arrays110-aand both the lower substrate circuitry region305and the upper substrate circuitry region320, in some examples, an interconnection region370-amay be implemented for coupling between the memory arrays110-aand one of the lower substrate circuitry region305or the upper substrate circuitry region320, but not both (e.g., in examples where CMOS or other circuitry of a row component125, common to all of the memory arrays110-a, is located in one of the lower substrate circuitry region305or the upper substrate circuitry region320). The interconnection regions370-bmay illustrate examples of a coupling between memory arrays110-aof a set310and one of the lower substrate circuitry region305or the upper substrate circuitry region320. In some examples, interconnection regions370-bmay be examples of a digit line socket region, which may be used to select and activate one or more digit lines of the decks315-a. For example, the memory device100-amay include an interconnection region370-b-1that couples digit lines of decks315-a-1and315-a-2of the set310-ato decoders (e.g., column components135), digit line drivers (sub-digit line drivers), sense amplifiers, or a combination thereof, of the lower substrate circuitry region305. In some examples, the memory device100-amay include an interconnection region370-b-2that includes interconnects that couple digit lines of decks315-a-3and315-a-4of the set310-bto such circuitry of the upper substrate circuitry region320. The interconnection region370-cmay illustrate an example of a coupling between the lower substrate circuitry region305and the upper substrate circuitry region320. For example, the upper substrate circuitry region320may include pad logic or other CMOS circuitry associated with functionality for all of decks315-a-1through315-a-4, which may be coupled with decks315-a-1and315-a-2via the interconnection region370-cand via the lower substrate circuitry region305. Locating such pad logic or other shared CMOS circuitry in the upper substrate circuitry region320may provide favorable proximity to components or circuitry of the backend circuitry region340, or may reduce area utilization of a lower substrate220of the lower substrate circuitry region305for favorable scaling or routing flexibility, or both, among other advantages. The interconnection region370-dmay illustrate an example of a coupling between the lower substrate circuitry region305and the backend circuitry region340, and the interconnection region370-emay illustrate an example of an interconnection between the upper substrate circuitry region320and the backend circuitry region340. The interconnection region370-fmay illustrate an example of a coupling between the backend circuitry region340and the I/O circuitry region350. By including both the lower substrate circuitry region305and the upper substrate circuitry region320, the memory device100-amay support a distribution of substrate-based circuitry or CMOS circuitry for accessing and operating a stack or multiple decks315-abetween two substrates, which may reduce the area or footprint of each substrate220that is occupied by such circuitry. A distribution of circuitry between such regions may enable greater scaling of the memory device100-a(e.g., using a greater quantity of decks315-a) within a given area or footprint. Moreover, in some examples, pad logic or other circuitry associated with both the lower set310-aand the upper set310-bmay be included the upper substrate-based circuitry (e.g., rather than be distributed between the upper substrate-based circuitry and the lower substrate-based circuitry, or included entirely in the lower substrate-based circuitry), which may support allocating more of a lower substrate for other purposes, such as interconnect circuitry that supports an increased quantity of decks315-a. FIGS.4through8illustrate examples of operations for forming a memory device that supports transistor configurations for multi-deck memory devices in accordance with examples as disclosed herein. For example,FIGS.4through8may illustrate aspects of a sequence of operations that may support manufacturing a memory device100-ato include multiple levels of substrate-based or CMOS circuitry. Each of the figures may be described with reference to an x-direction, a y-direction, and a z-direction of the coordinate system301. Operations illustrated in and described with reference toFIGS.4through8may be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations such as deposition or bonding, subtractive operations such as etching, trenching, planarizing, or polishing, and supporting operations such as masking, photolithography, or aligning, among other operations that support the described techniques. FIG.4illustrates a portion of the memory device100-aafter a first set of manufacturing operations, including the formation of the lower substrate circuitry region305, the decks315-a-1and315-a-2of the set310-a, and a portion430of the backend interconnect region330. Forming the lower substrate circuitry region305may include forming various circuitry for operating or accessing at least the decks315-aof the set310-a, which may include portions of a row component125(e.g., a row decoder, a word line driver), a column component135(e.g., a column decoder, a digit line driver), or a sense component150(e.g., sense amplifiers), among other components or circuitry. In some examples, forming the lower substrate circuitry region305may omit forming some components or circuitry for operating the decks315-aof the set310-a(e.g., I/O circuitry, pad logic), because such circuitry may be located elsewhere in the memory device100-a(e.g., in the upper substrate circuitry region320). Forming the lower substrate circuitry region305may include doping portions of a substrate220(e.g., a first substrate) to form a lower set of transistors, which may include forming transistor structures200described with reference toFIG.2. In some examples, at least some of such transistors may be arranged in a CMOS configuration. In some examples, the deck315-a-1may be formed over the lower substrate circuitry region305, which may be followed by forming the deck315-a-2over the deck315-a-1. In some examples, formation of the decks315-a-1and315-a-2may be accompanied by aspects of forming the portion430of the backend interconnect region330. Forming the decks315-aof the set310-amay include various operations for forming the respective memory arrays110-a, such as forming memory cells105(e.g., capacitors, transistors, material memory elements, or other storage elements that may be distributed in an xy-plane), word lines120(e.g., aligned along the x-direction), digit lines130(e.g., aligned along the y-direction), and plate lines140or other plate configurations (e.g., where applicable), among other components or circuitry of the respective memory array110-a. In some examples, forming the decks315-amay include forming transistors, such as cell selection transistors, among transistors for other purposes. Such transistors may be referred to as thin film transistors, and may include transistors having a vertical channel configuration (e.g., vertical transistors). In some examples, forming vertical transistors of the decks315-amay include forming doped semiconductor pillars that are aligned along the z-direction. For example, to support an n-type transistor, a pillar may include at least a p-type semiconductor portion, or may include a stack (e.g., along the z-direction) of an n-type semiconductor, a p-type semiconductor, and an n-type semiconductor (e.g., in an NPN arrangement along the z-direction), among other constituent materials or arrangements. To support a p-type transistor, a pillar may include at least an n-type semiconductor portion, or may include a stack (e.g., along the z-direction) of a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor (e.g., in an PNP arrangement in the z-direction), among other constituent materials or arrangements. Semiconductor pillars for transistors of the decks315-a(e.g., TFTs), among other portions of the memory device100-a, may be formed according to various techniques. In some examples, one or more layers or stacks of layers of doped semiconductor material (e.g., polycrystalline semiconductor) may be deposited in the respective deck315-a, and portions of the deposited layers located between respective pillars (e.g., along the x-direction, along the y-direction) may be etched away or trenched to form the respective pillars. Additionally or alternatively, in some examples, holes or trenches may be etched through a material of the respective deck315-a(e.g., along or through the z-direction, through a dielectric material, through a gate dielectric material) and material for the pillars (e.g., one or more doped semiconductor materials, one or more electrode materials) may be deposited in the etched holes or trenches. Forming the lower substrate circuitry region305, the decks315-a-1and315-a-2of the set310-a, and the portion430of the backend interconnect region330may include forming interconnection regions370, or portions470thereof, which may include various additive or subtractive operations performed during the formation of the lower substrate circuitry region305, the decks315-a-1and315-a-2, or the portion430. For example, forming circuitry of the interconnection region370-b-1(e.g., a first digit line socket region) may include forming TSVs between digit lines of the memory arrays110-a-1and110-a-2and circuitry of the lower substrate circuitry region305(e.g., column decoders, sense amplifiers). Further, forming circuitry of the portion470-aof the interconnection region370-a(e.g., a word line socket region) may include forming TSVs between word lines120of the memory arrays110-a-1and110-a-2and circuitry of the lower substrate circuitry region305, or for later coupling with circuitry of the upper substrate circuitry region320, or both (e.g., row decoders). Forming circuitry of the portions470-cand470-dof the interconnection regions370-cand370-dmay include forming TSVs in contact with circuitry of the lower substrate circuitry region305, and may provide such functionality as power, voltage, or signal distribution between the lower substrate circuitry region305and the upper substrate circuitry region320or the backend circuitry region340, respectively. In some examples, aspects of forming the interconnection region370-b-1and the portions470-a,470-c, and470-dmay include concurrent operations, including one or more additive or subtractive operations for forming TSVs in two or more such regions. FIG.5illustrates a portion of the memory device100-aafter a second set of manufacturing operations, including the formation of the decks315-a-3and315-a-4of the set310-b, and a portion530of the backend interconnect region330. In some examples, the deck315-a-3may be formed over the deck315-a-2, which may be followed by forming the deck315-a-4over the deck315-a-3. In some examples, formation of the decks315-a-3and315-a-4may be accompanied by aspects of forming the portion530of the backend interconnect region330. Forming the decks315-aof the set310-bmay include various operations for forming the respective memory arrays110-a, including operations described with reference to the formation of memory arrays110-a-1and110-a-2. Forming the decks315-a-3and315-a-4of the set310-b, and the portion530of the backend interconnect region330may include forming interconnection regions370, or portions470thereof, which may include various additive or subtractive operations performed during the formation of the decks315-a-3and315-a-4or the portion530. For example, forming circuitry of the portion570-b-2of the interconnection region370-b-2(e.g., a second digit line socket region) may include forming TSVs for coupling between digit lines of the memory arrays110-a-3and110-a-4and circuitry of the upper substrate circuitry region320(e.g., column decoders, sense amplifiers, to be formed in later operations). Further, forming circuitry of the portion570-aof the interconnection region370-a(e.g., the word line socket region) may include forming TSVs between word lines120of the memory arrays110-a-3and110-a-4and circuitry of the lower substrate circuitry region305(e.g., via the portion470-aformed in preceding operations), or for later coupling with circuitry of the upper substrate circuitry region320, or both. Forming circuitry of the portions570-cand570-dof the interconnection regions370-cand370-dmay include forming TSVs in contact with TSVs of the portion430formed in preceding operations. In some examples, aspects of forming the portions570-a,570-b-2,570-c, and570-dmay include concurrent operations, including one or more additive or subtractive operations for forming TSVs in two or more such regions. In some examples, prior to forming the deck513-a-3and the portion530, a metal layer505may be formed above the deck315-a-2and the portion430of the backend interconnect region330, which may provide in-plane conductors (e.g., in an xy-plane) for coupling between two or more of the interconnection regions370-a,370-c, or370-d. In some examples, the metal layer505may provide further flexibility for routing power, voltage, or signaling between various components of the memory device100-a. The metal layer505may be formed by depositing a metal over the set310-aand the portion430. In some cases, a mask may be used to deposit the metal layer505such that conductive portions are in contact with interconnects of the two or more of the portions470-a,470-c, or470-d. In some examples, forming the metal layer505may include depositing a metal layer that is subsequently etched to form a set of portions of the metal layer505in contact with the interconnects of the two or more of the portions470-a,470-c, or470-d. In some examples, the metal layer505may be omitted. FIGS.6A and6Billustrates a portion of the memory device100-aafter a third set of manufacturing operations, including the bonding of an upper substrate (e.g., a second substrate220). FIG.6Aillustrates an example of a material stack605that may support an upper substrate in the memory device100-a. The material stack605may include a donor wafer portion610and a silicon layer620. In some examples, the material stack605may include an interface615between the donor wafer portion610and the silicon layer, which may provide a weakened portion between the donor wafer portion610and the silicon layer620that is leveraged for later processing. In some examples, the interface615may include a same material as the donor wafer portion610and the silicon layer620(e.g., a crystalline or monocrystalline silicon), which may be weakened by hydrogen ion implantation. In some examples, the material stack605may include an oxide layer625, which may be leveraged to support various bonding techniques. FIG.6Billustrates an example of depositing a second substrate for the memory device100-athat may be supported by the material stack605. For example, the material stack605may be bonded to the manufactured portion of the memory device100-a, which may include a bonding over or in contact with the top deck315-a(e.g., deck315-a-4) and the portion530of the backend interconnect region330. In some examples, before such bonding, an oxide layer650may be formed over a top surface of the deck315-a-4and the portion530, to which the oxide layer625of the material stack605may be bonded (e.g., after flipping the material stack605). Thus, in some examples, the material stack may be bonded above the deck315-a-4and the portion530using an oxide-to-oxide bonding operation. After bonding the material stack605, portions of the material stack605may be removed (e.g., along the z-direction, parallel to the xy-plane, including at least the donor wafer portion610). For example, a top surface of the material stack605may be thinned by a buffing operation, a chemical mechanical planarization or polishing operation, among other operations that remove the donor wafer portion610, or the donor wafer portion and the interface615. Accordingly, an exposed top portion of the memory device100-aafter such operations may be a portion of the silicon layer620of the material stack605, which may be an example of an upper substrate220with which upper substrate-base circuitry (e.g., CMOS circuitry) may be formed. Although the example ofFIGS.6A and6Billustrate an example for wafer-on-wafer oxide bonding, an upper substrate220may be formed or deposited in the memory device100-ain accordance with other techniques. For example, some implementations may include various techniques for silicon-over-insulator or silicon layer transfer, where, in some examples, transistors leveraging such a substrate may be configured with polycrystalline semiconductor transistors with equivalent channel quality, or other performance characteristic, similar to transistors of the lower substrate circuitry region (e.g., transistors leveraging a monocrystalline semiconductor substrate). FIG.7illustrates a portion of the memory device100-aafter a fourth set of manufacturing operations, including the formation of the voids710through the silicon layer620and the oxide layers625and650. The voids710may be formed by way of etching or other material removal operations through the respective layers, and may expose top surfaces of the top deck315-dand the portion530between various substrate portions715. In some examples, the voids710may be aligned above the portions570of interconnection regions370, which may support routing of power, voltage, or signal conductors through a level or height along the z-direction of the silicon layer620. Accordingly, some voids may support routing interconnections with components or circuitry of the upper substrate circuitry region320(e.g., substrate-based transistors, transistors in a CMOS configuration). In some examples, a portion of the silicon layer620located outside the upper substrate circuitry region320may be etched or otherwise removed, including a portion that overlaps the backend interconnect region330. In some examples, the voids710may be aligned above features that support registration or alignment of subsequent operations of formation for the memory device100-a, where such features may be dedicated for registration or alignment (e.g., fiducials), or may be operational or functional features of the top deck315-a-1, or the portion530, or both that support such alignment or registration. By supporting registration or alignment after the deposition of the silicon layer620, subsequent operations may be performed with or over the silicon layer620with improved alignment (e.g., feature-to-feature alignment, relative to features of the memory device100-athat have already been formed) compared to an alignment between features already formed on a material stack605and features of the memory device100-athat are already formed (e.g., related to a bonding alignment accuracy). FIG.8illustrates an example of the memory device100-aafter a fifth set of manufacturing operations, including the formation of the upper substrate circuitry region320, the backend circuitry region340, and the I/O circuitry region350. Forming the upper substrate circuitry region320may include forming various circuitry for operating or accessing at least the decks315-aof the set310-b, which may include portions of a row component125, a column component135, or a sense component150, among other components or circuitry. In some examples, forming the upper substrate circuitry region320may include forming some components or circuitry for operating each of the decks315-aof the sets310-aand310-b, such as pad logic or other circuitry that may be common to or applicable to all of the decks315-a-1through315-a-4. Forming the upper substrate circuitry region320may include doping portions of a substrate220(e.g., a second substrate, substrate portions715) to form an upper set of transistors, which may include forming transistor structures200described with reference toFIG.2. In some examples, at least some of such transistors may be arranged in a CMOS configuration. In some examples, an additional metallization layer may be formed over the transistors formed using the substrate portions715, which may support denser interconnection routing above such transistors. In some examples, forming the upper substrate circuitry region320may include forming interconnections with the memory arrays110-a-1through110-a-4, with the lower substrate circuitry region305, or various combinations thereof, which may include aspects of completing the interconnection regions370-a,370-b-2, or370-c, or a combination thereof which may include various additive or subtractive operations performed during the formation of the upper substrate circuitry region320. For example, completing circuitry of the interconnection region370-b-2(e.g., a second digit line socket region) may include forming TSVs coupled with digit lines of the memory arrays110-a-3and110-a-4(e.g., through a void710). Further, completing circuitry of the interconnection region370-a(e.g., a word line socket region) may include forming TSVs coupled with word lines120of at least the memory arrays110-a-3and110-a-3or, in some examples, with word lines120of all of the memory arrays110-a-1through110-a-4, or with the circuitry of the lower substrate circuitry region305, or both. In some examples, completing circuitry of the interconnection region370-cmay include forming TSVs coupled with circuitry of the lower substrate circuitry region305. In some examples, aspects of completing the interconnection regions370-a,370-b-2, and370-cmay include concurrent operations, including one or more additive or subtractive operations for forming TSVs in two or more such regions. The fifth set of operations may also include various operations for forming the backend circuitry region340and I/O circuitry region, which may include completing formation of the interconnection region370-a, forming the interconnection regions370-eand370-f, and forming the pads360-a-1through360-a-n. Forming the backend circuitry region340and the I/O circuitry region350may include forming various interconnecting conductors (e.g., copper interconnects, pads for packaging) for supporting communication of power, voltage, or signaling related to the operation of the memory arrays110-a. In some examples, the operations may further include coating or encapsulating the memory device100-ain a dielectric or other isolating material, such as a plastic or resin material, which may be formed such that the pads360-a-1through360-a-nare exposed and operable for coupling with a host device. FIG.9shows a flowchart illustrating a method900that supports transistor configurations for multi-deck memory devices in accordance with examples as disclosed herein. The operations of method900may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using special-purpose hardware. At905, the method may include forming, based at least in part on doping portions of a first silicon substrate, a first plurality of transistors (e.g., of a lower substrate circuitry region305). The operations of905may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through4. At910, the method may include forming a first deck of memory cells (e.g., a lower deck315-a) above the first silicon substrate and coupled with the first plurality of transistors (e.g., via an interconnection region370-a, via an interconnection region370-b-1). The operations of910may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through4. At915, the method may include forming a second deck of memory cells (e.g., an upper deck315-a) above the first deck of memory cells. The operations of915may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through3and5. At920, the method may include bonding a second silicon substrate (e.g., a material stack605, a silicon layer620) above the second deck of memory cells. The operations of920may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through3,6A, and6B. At925, the method may include forming, based at least in part on doping portions of the second silicon substrate after bonding the second silicon substrate above the second deck of memory cells, a second plurality of transistors (e.g., of an upper substrate circuitry region320) coupled with the second deck of memory cells. The operations of925may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through3and6A through8. In some examples, an apparatus as described herein may be manufactured (e.g., fabricated) according to a method or methods, such as the method900. A system for manufacturing the apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming, based at least in part on doping portions of a first silicon substrate, a first plurality of transistors, forming a first deck of memory cells above the first silicon substrate and coupled with the first plurality of transistors, forming a second deck of memory cells above the first deck of memory cells, bonding a second silicon substrate above the second deck of memory cells, and forming, based at least in part on doping portions of the second silicon substrate after bonding the second silicon substrate above the second deck of memory cells, a second plurality of transistors coupled with the second deck of memory cells. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for etching through the second silicon substrate to form a plurality of second silicon substrate portions (e.g., substrate portions715) and forming the second plurality of transistors based at least in part on doping the second silicon substrate portions. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for registering an orientation of one or more operations after the etching based at least in part on registration features located below the second silicon substrate and aligned between the second silicon substrate portions (e.g., aligned with one or more voids710). In some examples of the method900and the system for manufacturing described herein, forming the first deck of memory cells may include operations, features, circuitry, logic, means, or instructions for forming a stack of decks of memory cells (e.g., of a set310-a) above the first silicon substrate, the stack of decks of memory cells including the first deck of memory cells and coupled with the first plurality of transistors. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming a metal layer (e.g., a metal layer505) above the stack of decks of memory cells, the second deck of memory cells formed above the metal layer. In some examples of the method900and the system for manufacturing described herein, forming the second deck of memory cells may include operations, features, circuitry, logic, means, or instructions for forming a stack of decks of memory cells (e.g., of a set310-b) above the first deck of memory cells, the stack of decks of memory cells including the second deck of memory cells and coupled with the second plurality of transistors. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, before bonding the second silicon substrate, a first oxide material (e.g., of an oxide layer650) above the second deck of memory cells and forming, before bonding the second silicon substrate, a second oxide material (e.g., of an oxide layer625) in contact with the second silicon substrate, where bonding the second silicon substrate above the second deck of memory cells includes bonding the first oxide material to the second oxide material. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, above the second silicon substrate, I/O circuitry (e.g., of an I/O circuitry region350, of a backend circuitry region340) coupled with the second plurality of transistors (e.g., via an interconnection region370-e). In some examples of the method900and the system for manufacturing described herein, the I/O circuitry may be operable for communication with the first deck of memory cells (e.g., via an interconnection region370-f, or an interconnection region370-d, or an interconnection region370-c, among other interconnection regions370) and the second deck of memory cells (e.g., via an interconnection region370-f, or an interconnection region370-e, among other interconnection regions370). Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, above the second silicon substrate and after forming the second plurality of transistors, backend circuitry (e.g., of a backend circuitry region340) coupled with the second plurality of transistors (e.g., via an interconnection region370-e). Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, above the first silicon substrate, a plurality of interconnects (e.g., of an interconnection region370-d, an interconnection region370-e, or a combination thereof), where the plurality of interconnects couples the backend circuitry with the first plurality of transistors and the second plurality of transistors. Some examples of the method900and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, on the second silicon substrate, a metal layer (e.g., over substrate-based transistors of an upper substrate circuitry region320). FIG.10shows a flowchart illustrating a method1000that supports transistor configurations for multi-deck memory devices in accordance with examples as disclosed herein. The operations of method1000may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using special-purpose hardware. At1005, the method may include forming first circuitry (e.g., of a lower substrate circuitry region305) for accessing a plurality of memory cells, the first circuitry including a first plurality of transistors formed at least in part by doping portions of a first semiconductor substrate. The operations of1005may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through4. At1010, the method may include forming the plurality of memory cells according to a stack of decks of memory cells (e.g., a stack of decks315-a) above the first semiconductor substrate. The operations of1010may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through5. At1015, the method may include bonding a second semiconductor substrate (e.g., a substrate220, a silicon layer620) above the stack of decks of memory cells. The operations of1015may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through3,6A, and6B. At1020, the method may include forming second circuitry (e.g., of an upper substrate circuitry region320) for accessing the plurality of memory cells, the second circuitry including a second plurality of transistors formed at least in part by doping portions of the second semiconductor substrate after bonding the second semiconductor substrate above the stack of decks of memory cells. The operations of1020may be performed in accordance with examples and techniques as disclosed herein, including one or more aspects described with reference toFIGS.1through3and6A through8. In some examples, an apparatus as described herein may be manufactured (e.g., fabricated) according to a method or methods, such as the method1000. A system for manufacturing the apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming first circuitry for accessing a plurality of memory cells, the first circuitry including a first plurality of transistors formed at least in part by doping portions of a first semiconductor substrate, forming the plurality of memory cells according to a stack of decks of memory cells above the first semiconductor substrate, bonding a second semiconductor substrate above the stack of decks of memory cells, and forming second circuitry for accessing the plurality of memory cells, the second circuitry including a second plurality of transistors formed at least in part by doping portions of the second semiconductor substrate after bonding the second semiconductor substrate above the stack of decks of memory cells. Some examples of the method1000and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for etching through portions of the second semiconductor substrate to form a plurality of voids (e.g., voids710) to the stack of decks of memory cells, where the second plurality of transistors may be formed on remaining portions of the second semiconductor substrate (e.g., substrate portions715). Some examples of the method1000and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming a first oxide material (e.g., of an oxide layer650) above a top deck of memory cells of the stack of decks of memory cells and forming a second oxide material (e.g., of an oxide layer625) in contact with the second semiconductor substrate, where bonding the second semiconductor substrate above the stack of decks of memory cells includes bonding the first oxide material to the second oxide material. Some examples of the method1000and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, above and coupled with the second circuitry, backend circuitry (e.g., of a backend circuitry region340) associated with the plurality of memory cells and forming, above the backend circuitry, I/O circuitry (e.g., of an I/O circuitry region350) associated with the plurality of memory cells that is coupled with the first circuitry and the second circuitry. Some examples of the method1000and the system for manufacturing described herein may further include operations, features, circuitry, logic, means, or instructions for forming, above the first semiconductor substrate, interconnect circuitry associated with the plurality of memory cells that couples the backend circuitry to the first circuitry (e.g., via an interconnection region370-d) and the second circuitry (e.g., via an interconnection region370-e). In some examples of the method1000and the system for manufacturing described herein, the first plurality of transistors, or the second plurality of transistors, or both include a CMOS configuration. In some examples of the method1000and the system for manufacturing described herein, the first circuitry includes circuitry for performing sense operations on a first subset of decks of the stack of decks, circuitry for performing access operations on the first subset of decks, circuitry for performing decoding operations on the first subset of decks, or circuitry for performing I/O operations on the first subset of decks, or a combination thereof and the second circuitry includes circuitry for performing sense operations on a second subset of decks of the stack of decks, circuitry for performing access operations on the second subset of decks, circuitry for performing decoding operations on the second subset of decks, or circuitry for performing I/O operations on the second subset of decks, or a combination thereof. It should be noted that the methods described herein are possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined. An apparatus is described. The apparatus may include a first silicon substrate (e.g., a substrate220), a first plurality of transistors (e.g., of a lower substrate circuitry region305) formed at least in part by doped portions of the first silicon substrate, a first deck of memory cells (e.g., a lower deck315-a) above and coupled with the first plurality of transistors (e.g., via an interconnection region370-aor an interconnection region370-b-1), a second deck of memory cells (e.g., an upper deck315-a) above the first deck of memory cells, a second silicon substrate above the second deck of memory cells, and a second plurality of transistors (e.g., of an upper substrate circuitry region320) formed at least in part by doped portions of the second silicon substrate and coupled with the second deck of memory cells (e.g., via an interconnection region370-a, via an interconnection region370-b-2). In some examples of the apparatus, the first silicon substrate and the second silicon substrate each include crystalline silicon. In some examples of the apparatus, the second silicon substrate may include an oxide layer (e.g., of an oxide layer625) over the crystalline silicon of the second silicon substrate, and the second silicon substrate may be bonded over the second deck of memory cells based at least in part on the oxide layer. In some examples, the apparatus may include a first stack of decks of memory cells (e.g., of a set310-a) above the first silicon substrate and coupled with the first plurality of transistors, the first stack of decks of memory cells including the first deck of memory cells. In some examples, the apparatus may include a second stack of decks of memory cells (e.g., of a set310-b) above the first silicon substrate and coupled with the second plurality of transistors, the second stack of decks of memory cells including the second deck of memory cells. In some examples, the apparatus may include I/O circuitry (e.g., of an I/O circuitry region350, of a backend circuitry region340) above the second plurality of transistors and operable for communication with the first deck of memory cells and the second deck of memory cells. In some examples, the apparatus may include a plurality of interconnects (e.g., of an interconnection region370-c, of an interconnection region370-a) between the first plurality of transistors and the second plurality of transistors, where the plurality of interconnects couple the I/O circuitry with the first plurality of transistors and the second plurality of transistors. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths. The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors. The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other while the switch is open. When a controller isolates two components from one another, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow. The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, and/or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels. As used herein, the term “electrode” may refer to an electrical conductor, and in some examples, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of the memory array. The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means. A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate. The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label. The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.” Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media. The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein. | 95,107 |
11862629 | DETAILED DESCRIPTION According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrode is provided on a side opposite to the first electrode. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. A potential of the third electrically conductive portion is set to be the same as a potential of the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion. The fourth electrode is provided on a side opposite to the third electrode. The fourth electrically conductive portion is electrically connected to the fourth electrode and the second electrically conductive portion. A potential of the fourth electrically conductive portion is set to be the same as a potential of the second electrically conductive portion. Embodiments of the invention will now be described with reference to the drawings. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated. In the drawings and the specification of the application, components similar to those described thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate. In the following descriptions and drawings, notations of n+, n, n−and p+, p represent relative height of an impurity concentration in conductive types. That is, the notation with “+” shows a relatively higher impurity concentration than an impurity concentration for the notation without any of “+” and “−”. The notation with “−” shows a relatively lower impurity concentration than the impurity concentration for the notation without any of them. These notations represent relative height of a net impurity concentration after mutual compensation of these impurities when respective regions include both of a p-type impurity and an n-type impurity. The embodiments described below may be implemented by reversing the p-type and the n-type of the semiconductor regions. First Embodiment FIG.1is a cross-sectional view illustrating a semiconductor device according to a first embodiment. The semiconductor device100illustrated inFIG.1includes a semiconductor chip10(a first semiconductor chip), a semiconductor chip20(an example of a second semiconductor chip), a first metal plate41, a second metal plate42, a metal plate43, and a housing44(a frame). An XYZ orthogonal coordinate system is used in the description of the embodiments recited below. In the first embodiment, the direction from the first metal plate41toward the second metal plate42is taken as a Z-direction. Two mutually-orthogonal directions perpendicular to the Z-direction are taken as an X-direction and a Y-direction. In the description, the direction from the first metal plate41toward the second metal plate42is called “up;” and the reverse direction is called “down.” These directions are based on the relative positional relationship between the first metal plate41and the second metal plate42and are independent of the direction of gravity. The first metal plate41and the second metal plate42spread along the X-direction and the Y-direction and are separated from each other in the Z-direction. The first metal plate41includes a first electrically conductive portion41aand a third electrically conductive portion41c. The upper surfaces of the first electrically conductive portion41aand the third electrically conductive portion41cprotrude upward higher than the upper surfaces of the other portions. The semiconductor chip10is provided on the first electrically conductive portion41a. The semiconductor chip20is provided on the third electrically conductive portion41c. The second metal plate42includes a second electrically conductive portion42band a fourth electrically conductive portion42d. The lower surfaces of the second electrically conductive portion42band the fourth electrically conductive portion42dprotrude downward lower than the lower surfaces of the other portions. The second electrically conductive portion42bis provided on the semiconductor chip10. The fourth electrically conductive portion42dis provided on the semiconductor chip20. A lower surface electrode and an upper surface electrode of the semiconductor chip10are electrically connected respectively to the first electrically conductive portion41aand the second electrically conductive portion42b. A lower surface electrode and an upper surface electrode of the semiconductor chip20are electrically connected respectively to the third electrically conductive portion41cand the fourth electrically conductive portion42d. The semiconductor device100may include multiple thermal compensation plates45and multiple thermal compensation plates46as illustrated inFIG.1. The multiple thermal compensation plates45are provided respectively between the first electrically conductive portion41aand the semiconductor chip10and between the third electrically conductive portion41cand the semiconductor chip20. The multiple thermal compensation plates46are provided respectively between the semiconductor chip10and the second electrically conductive portion42band between the semiconductor chip20and the fourth electrically conductive portion42d. The semiconductor chip10and the semiconductor chip20are electrically connected to the first metal plate41and the second metal plate42via the thermal compensation plates45and46. For example, the semiconductor device100includes multiple semiconductor chips10and multiple semiconductor chips20. The first metal plate41includes multiple first electrically conductive portions41aand multiple third electrically conductive portions41c. The second metal plate42includes multiple second electrically conductive portions42band multiple fourth electrically conductive portions42d. The multiple semiconductor chips10are provided respectively between the multiple first electrically conductive portions41aand the multiple second electrically conductive portions42b. The multiple semiconductor chips20are provided respectively between the multiple third electrically conductive portions41cand the multiple fourth electrically conductive portions42d. The housing44is a member having a ring configuration and is provided around the multiple semiconductor chips10and the multiple semiconductor chips20. The housing44includes an insulating ceramic such as alumina, etc. Multiple protrusions44aare provided at the outer perimeter of the housing44. The insulative property (the creepage distance) between the first metal plate41and the second metal plate42can be improved by providing the protrusions44a. The first metal plate41and the second metal plate42respectively include a fringe41kand a fringe42k. The fringe41kand the fringe42kare fixed by brazing respectively at the outer perimeter of the first metal plate41and the outer perimeter of the second metal plate42. The housing44is interposed between the fringe41kof the first metal plate41and the fringe42kof the second metal plate42and is fixed by brazing to these fringes. The semiconductor chip10and the semiconductor chip20further include other upper surface electrodes. These upper surface electrodes are electrically connected to the metal plate43via pins43a. The metal plate43is a member having a flat plate configuration spreading along the X-direction and the Y-direction. The metal plate43is provided inside the housing44. The metal plate43is electrically connected to a terminal43bdrawn outside the housing44. The multiple semiconductor chips10and the multiple semiconductor chips20are surrounded and sealed with the first metal plate41, the second metal plate42, and the housing44. For example, an inert gas is filled into the surrounded space. By pressing the first metal plate41and the second metal plate42in directions approaching each other, the semiconductor chips10and the semiconductor chips20are closely adhered to the first metal plate41and the second metal plate42; and good electrical contact is obtained. The first metal plate41and the second metal plate42include a metal having high electrical conductivity and thermal conductivity such as copper, etc. Materials that have thermal expansion coefficients near those of the semiconductor chip10and the semiconductor chip20are used in the thermal compensation plates45and46. For example, in the case where the semiconductor chip10and the semiconductor chip20include silicon, the thermal compensation plates45and46include molybdenum. The fringe41kand the fringe42kinclude, for example, an iron-nickel alloy. FIG.2is a cross-sectional view illustrating an example of the semiconductor chip10of the semiconductor device according to the first embodiment. The semiconductor chip10is an RC-IGBT. As illustrated inFIG.2, the semiconductor chip10includes a collector electrode11, an emitter electrode12, a gate pad13, a semiconductor portion14, a gate electrode15, and an electrically conductive portion16. The collector electrode11is provided at the lower surface of the semiconductor chip10and is electrically connected to the first electrically conductive portion41avia the thermal compensation plate45. The emitter electrode12is provided at the upper surface of the semiconductor chip10and is electrically connected to the second electrically conductive portion42bvia the thermal compensation plate46. The gate pad13is provided at the upper surface of the semiconductor chip10and is electrically connected to the metal plate43via the pin43a. The semiconductor portion14is provided between the collector electrode11and the emitter electrode12and between the collector electrode11and the gate pad13. The semiconductor portion14includes, for example, a p+-type collector region14a, an n+-type cathode region14b, an n-type buffer region14c, an n−-type drift region14d, a p-type base region14e, an n+-type emitter region14f, a p-type anode region14g, and a p+-type anode region14h. The p+-type collector region14aand the n+-type cathode region14bare provided on the collector electrode11and are electrically connected to the collector electrode11. The n-type buffer region14cis provided on the p+-type collector region14aand the n+-type cathode region14band around the p+-type collector region14aand the n+-type cathode region14b. The n−-type drift region14dis provided on the n-type buffer region14c. The p-type base region14eis provided on the n−-type drift region14dand is positioned on the p+-type collector region14a. The p-type anode region14gis provided on the n−-type drift region14dand is positioned on the n+-type cathode region14b. The n+-type emitter region14fis provided selectively on the p-type base region14e. The p+-type anode region14his provided selectively on the p-type anode region14g. For example, the gate electrode15and the electrically conductive portion16are provided inside the semiconductor portion14. The gate electrode15opposes the p-type base region14ewith a gate insulating layer15ainterposed. The electrically conductive portion16opposes the p-type anode region14gwith an insulating layer16ainterposed. The emitter electrode12is electrically connected to the p-type base region14e, the n+-type emitter region14f, the p-type anode region14g, the p+-type anode region14h, and the electrically conductive portion16. The gate pad13is electrically connected to the gate electrode15. The surface of the semiconductor portion14around the p-type base region14eand the p-type anode region14gis covered with an insulating layer17. The gate pad13is provided on the semiconductor portion14with the insulating layer17interposed. The region of the semiconductor chip10where the p+-type collector region14a, the p-type base region14e, the n+-type emitter region14f, and the gate electrode15are provided functions as an IGBT. The region where the n+-type cathode region14b, the p-type anode region14g, and the p+-type anode region14hare provided functions as a diode. FIG.3is a cross-sectional view illustrating an example of the semiconductor chip20of the semiconductor device according to the first embodiment. The semiconductor chip20is an IGBT. As illustrated inFIG.3, the semiconductor chip20includes a collector electrode21(an example of a third electrode), an emitter electrode22(an example of a fourth electrode), a gate pad23, a semiconductor portion24, and a gate electrode25. The collector electrode21is provided at the lower surface of the semiconductor chip20and is electrically connected to the third electrically conductive portion41cvia the thermal compensation plate45. The emitter electrode22is provided at the upper surface of the semiconductor chip20and is electrically connected to the fourth electrically conductive portion42dvia the thermal compensation plate46. The gate pad23is provided at the upper surface of the semiconductor chip20and is electrically connected to the metal plate43via the pin43a. The semiconductor portion24is provided respectively between the collector electrode21and the emitter electrode22and between the collector electrode21and the gate pad23. The semiconductor portion24includes, for example, a p+-type collector region24a, an n-type buffer region24c, an n−-type drift region24d, a p-type base region24e, and an n+-type emitter region24f. The p+-type collector region24ais provided on the collector electrode21and is electrically connected to the collector electrode21. The n-type buffer region24cis provided on the p+-type collector region24aand around the p+-type collector region24a. The n−-type drift region24dis provided on the n-type buffer region24c. The p-type base region24eis provided on the n−-type drift region24d. The n+-type emitter region24fis provided selectively on the p-type base region24e. For example, the gate electrode25is provided inside the semiconductor portion24. The gate electrode25opposes the p-type base region24ewith a gate insulating layer25ainterposed. The emitter electrode22is electrically connected to the p-type base region24eand the n+-type emitter region24f. The gate pad23is electrically connected to the gate electrode25. The surface of the semiconductor portion24around the p-type base region24eis covered with an insulating layer27. The gate pad23is provided on the semiconductor portion24with the insulating layer27interposed. Material examples of the components of the semiconductor chip10and the semiconductor chip20will now be described. The collector electrode11, the collector electrode21, the emitter electrode12, the emitter electrode22, the gate pad13, and the gate pad23include a metal such as aluminum, nickel, copper, etc. The semiconductor portion14and the semiconductor portion24include silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case where silicon is used as the semiconductor material, arsenic, phosphorus, or antimony is used as an n-type impurity. Boron is used as a p-type impurity. The gate electrode15, the gate electrode25, and the electrically conductive portion16include an electrically conductive material such as polysilicon, etc. The gate insulating layer15a, the gate insulating layer25a, the insulating layer16a, the insulating layer17, and the insulating layer27include an insulating material such as silicon oxide, etc. Operations of the semiconductor device100will now be described. When a voltage that is a threshold or more is applied to the gate electrode15via the metal plate43, a channel is formed at the gate insulating layer15avicinity of the p-type base region14e. For example, a voltage that is positive with respect to the second metal plate42is applied to the first metal plate41. In other words, a voltage that is positive with respect to the emitter electrode12is applied to the collector electrode11. When the channel is formed in this state, electrons flow through the channel from the emitter electrode12to the n−-type drift region14dand are ejected from the collector electrode11. Holes flow through the p+-type collector region14afrom the collector electrode11to the n−-type drift region14dand are ejected from the emitter electrode12. A current flows in the semiconductor chip10; and the semiconductor chip10is set to the ON-state. This is similar for the semiconductor chip20as well. A voltage that is the threshold or more is applied to the gate electrode25via the metal plate43in a state in which a voltage that is positive with respect to the emitter electrode22is applied to the collector electrode21. A current flows in the semiconductor chip20; and the semiconductor chip20is set to the ON-state. When the semiconductor chip10and the semiconductor chip20are in the ON-state, conductivity modulation occurs in the n−-type drift region14dand the n−-type drift region24ddue to the injected electrons and holes; and the electrical resistance greatly decreases. By switching the semiconductor chip10and the semiconductor chip20to the ON-state in the state in which the voltage that is positive with respect to the second metal plate42is applied to the first metal plate41, a current flows from the first metal plate41toward the second metal plate42. For example, a bridge circuit is configured using the multiple semiconductor devices100. In the bridge circuit, when one semiconductor device100is switched from the ON-state to the OFF-state, an induced electromotive force is applied to the second metal plate42of another semiconductor device100. The semiconductor chip10includes a diode. When the induced electromotive force is applied to the emitter electrode12via the second metal plate42, holes flow from the emitter electrode12to the n−-type drift region14dthrough the p-type anode region14gand the p+-type anode region14hand are ejected from the collector electrode11. Electrons flow from the collector electrode11to the n−-type drift region14dthrough the n+-type cathode region14band are ejected from the emitter electrode12. In other words, a freewheeling current flows in the forward direction of the diode of the semiconductor chip10. At this time, conductivity modulation occurs in the n−-type drift region14ddue to the injected electrons and holes; and the electrical resistance greatly decreases. FIG.4is a plan view illustrating an arrangement of the semiconductor chips of the semiconductor device according to the first embodiment.FIG.1is an A-A′ cross-sectional view ofFIG.4. InFIG.4, the semiconductor chips10and the semiconductor chips20are marked with mutually-different hatching. As illustrated inFIG.4, for example, the number of the semiconductor chips20is less than the number of the semiconductor chips10. The semiconductor chips20are provided at positions surrounded with the multiple semiconductor chips10. The multiple semiconductor chips20are provided to be adjacent to each other. The semiconductor chips10include both IGBT regions and FRD regions. The semiconductor chips20include only IGBT regions. In other words, when the semiconductor device100is in the ON-state, the regions where the current flows in the semiconductor chips10are narrower than the regions where the current flows in the semiconductor chips20. Therefore, compared to the semiconductor chips20, the current density is higher and the heat generation is larger in the semiconductor chips10. Accordingly, to suppress the temperature increase of the semiconductor device100due to heat generation when operating, it is desirable for the semiconductor chips10to be provided further on the outer perimeter side of the semiconductor device100than the semiconductor chips20so that the heat of the semiconductor chips10is released more efficiently to the outside. Effects of the first embodiment will now be described with reference to a semiconductor device according to a reference example. FIG.5is a plan view illustrating the semiconductor device according to the reference example. FIG.6is a graph illustrating a characteristic of the semiconductor device according to the reference example. FIGS.7A and7Bare cross-sectional views illustrating operations of the semiconductor device according to the reference example. In the semiconductor device100raccording to the reference example illustrated inFIG.5, only the semiconductor chips10are provided; and the semiconductor chips20are not provided. InFIG.6, the horizontal axis is a voltage VCwith respect to the emitter electrode12applied to the collector electrode11. The vertical axis is a current IONflowing from the collector electrode11toward the emitter electrode12in the ON-state. In the case of the semiconductor device100raccording to the reference example, when the voltage VCincreases to some magnitude, the voltage VCabruptly decreases as the current IONincreases as in the portion surrounded with the dotted line ofFIG.6. This phenomenon is called snapback. The snapback illustrated inFIG.6occurs because the semiconductor chips10are RC-IGBTs. When the semiconductor chip10is in the ON-state and when a voltage having a sufficient magnitude is applied to the collector electrode11, the holes and the electrons are injected into the n−-type drift region14dfrom the collector electrode11and the emitter electrode12as described above. Thereby, conductivity modulation occurs in the n−-type drift region14d; and the electrical resistance of the semiconductor device100rdecreases greatly. When the voltage that is applied to the collector electrode11in the ON-state is low, the potential difference between the p+-type collector region14aand the n-type buffer region14cdoes not reach or exceed the built-in potential; and the holes are not injected into the n−-type drift region14dfrom the p+-type collector region14a. As a result, only the electrons from the emitter electrode12are injected. The electrons are ejected to the collector electrode11through the n−-type drift region14dand the n+-type cathode region14bas illustrated by the arrows ofFIG.7A. In other words, an operation of MOS mode occurs instead of an IGBT operation in the semiconductor chip10. Subsequently, when the voltage that is applied to the collector electrode11increases, the potential difference between the p+-type collector region14aand the n-type buffer region14creaches or exceeds the built-in potential. As illustrated inFIG.7B, the holes are injected into the n−-type drift region14dfrom the p+-type collector region14a; and the electrical resistance of the semiconductor device100rdecreases. The current IONincreases; the voltage VCdecreases; and snapback such as that illustrated inFIG.6occurs. By using the RC-IGBT semiconductor chip10, it is unnecessary to separately provide the semiconductor chip of the IGBT and the semiconductor chip of the diode when configuring the semiconductor device. Therefore, the semiconductor device can be downsized. On the other hand, in the case where the semiconductor chip10is used, the operation of MOS mode illustrated inFIG.7Amay occur. The power consumption of this operation is large compared to that of the operation of the IGBT illustrated inFIG.7B. In the case where the operation of MOS mode occurs, the power consumption of the semiconductor device increases. The semiconductor device100according to the first embodiment includes the semiconductor chip20in addition to the semiconductor chip10. The semiconductor chip20is an IGBT. As illustrated inFIG.3, at the lower surface of the semiconductor portion24of the semiconductor chip20, the p+-type collector region24ais provided; and an n+-type semiconductor region is not provided. In the semiconductor chip20, a path where the electrons flow such as that of the semiconductor chip10illustrated inFIG.7Adoes not exist. An operation of MOS mode in the semiconductor chip20is suppressed. In the case where the electrons do not flow from the emitter electrode22to the collector electrode21, the potential difference between the collector electrode21and the emitter electrode22increases by that amount. Thereby, the potential difference between the p+-type collector region24aand the n−-type drift region24ddecreases. As a result, in the semiconductor chip20, the holes are injected into the n−-type drift region24dfrom the p+-type collector region24aalso in the state in which the voltage applied to the collector electrode21is low; and an IGBT operation occurs. The current flows mainly in the semiconductor chip20having the low electrical resistance; and the operation of MOS mode of the semiconductor chip10is suppressed. Subsequently, when the voltage VCincreases, an IGBT operation occurs in the semiconductor chip10as well. According to the semiconductor device100according to the embodiment, the occurrence of an operation of MOS mode such as that of the semiconductor device100raccording to the reference example in the ON-state can be suppressed. FIG.8AandFIG.8Bare graphs illustrating characteristics of the semiconductor device according to the first embodiment. InFIG.8AandFIG.8B, the horizontal axis is the voltage VC; and the vertical axis is the current ION.FIG.8Aillustrates the characteristics of the semiconductor chip10and the semiconductor chip20.FIG.8Billustrates the characteristic of the entire semiconductor device100. As illustrated inFIG.8AandFIG.8B, the characteristic of the semiconductor device100is substantially the combination of the portions of the characteristics of the semiconductor chip10and the semiconductor chip20, the portions having lower resistances. According to the first embodiment as illustrated inFIG.8B, the occurrence of the operation of MOS mode and the snapback of the semiconductor device100is suppressed. Thereby, the power consumption of the semiconductor device100can be reduced. FIG.9A,FIG.9B, andFIG.10are cross-sectional views illustrating other examples of the semiconductor chip10of the semiconductor device according to the first embodiment. The specific configuration of the semiconductor chip10is modifiable as appropriate as long as the semiconductor chip10can operate as an RC-IGBT. For example, as illustrated inFIG.9A, the multiple p+-type collector regions14aand the multiple n+-type cathode regions14bmay be provided alternately in the X-direction or the Y-direction on the collector electrode11. The p-type anode region14g, the p+-type anode region14h, and the electrically conductive portion16may not be provided on the upper surface side of the semiconductor portion14. In the case where a voltage that is positive with respect to the collector electrode11is applied to the emitter electrode12, the current flows from the emitter electrode12to the collector electrode11through a body diode made of the n−-type drift region14dand the p-type base region14e. As illustrated inFIG.9B, the gate electrode15may be provided on the semiconductor portion14with the gate insulating layer15ainterposed. The gate electrode15opposes the n−-type drift region14d, the p-type base region14e, and the n+-type emitter region14fwith the gate insulating layer15ainterposed in the Z-direction. Similarly for the semiconductor chip20as well, the specific configuration is modifiable as appropriate as long as the semiconductor chip20can operate as an IGBT. For example, similarly to the example ofFIG.9B, the gate electrode25may be provided on the semiconductor portion24with the gate insulating layer25ainterposed. The semiconductor chip10may include a Schottky barrier diode instead of the p-n junction diode. For example, as illustrated inFIG.10, a Schottky contact may be provided between the emitter electrode12and a portion of the n−-type drift region14d. The Schottky contact is positioned above the n+-type cathode region14b. In such a case, the emitter electrode12includes, for example, a metal having a large work function such as Al, AlSi, etc. FIG.11AtoFIG.12are plan views illustrating arrangements of the semiconductor chips of the semiconductor device according to the first embodiment. FIG.11AtoFIG.12illustrate arrangement examples of the semiconductor chips that are different fromFIG.4. As illustrated inFIG.11A, the multiple semiconductor chips20may be provided to be separated from each other at the outer perimeter of the semiconductor device100. As illustrated inFIG.11B, the semiconductor chips20may be provided at both the center and the outer perimeter of the semiconductor device100. Or, as illustrated inFIG.12, the multiple semiconductor chips20may be provided to be separated from each other at middle portions between the center and the outer perimeter of the semiconductor device100. In these arrangements as well, the occurrence of the operation of MOS mode and the snapback of the semiconductor device100is suppressed; and it is possible to reduce the power consumption of the semiconductor device100. Second Embodiment FIG.13is a cross-sectional view illustrating a semiconductor device according to a second embodiment. As illustrated inFIG.13, instead of the semiconductor chip20, the semiconductor device200according to the second embodiment includes a semiconductor chip30(another example of the second semiconductor chip). The semiconductor chip30is provided between the third electrically conductive portion41cand the fourth electrically conductive portion42dand is electrically connected to the third electrically conductive portion41cand the fourth electrically conductive portion42d. FIG.14is a cross-sectional view illustrating an example of the semiconductor chip of the semiconductor device according to the second embodiment. The semiconductor chip30is a diode. For example, as illustrated inFIG.14, the semiconductor chip30includes a cathode electrode31(another example of the third electrode), an anode electrode32(another example of the fourth electrode), and a semiconductor portion34. The cathode electrode31is provided at the lower surface of the semiconductor chip30and is electrically connected to the third electrically conductive portion41cvia the thermal compensation plate45. The anode electrode32is provided at the upper surface of the semiconductor chip30and is electrically connected to the fourth electrically conductive portion42dvia the thermal compensation plate46. In other words, the semiconductor chip30is connected in anti-parallel with the semiconductor chip10. The semiconductor chip30does not include a gate electrode or a gate pad. Therefore, the semiconductor chip30is not connected to the metal plate43. The semiconductor portion34is provided between the cathode electrode31and the anode electrode32. The semiconductor portion34includes, for example, an n+-type cathode region34b, an n−-type drift region34d, a p-type anode region34g, and a p+-type anode region34h. The n+-type cathode region34bis provided on the cathode electrode31and is electrically connected to the cathode electrode31. The n−-type drift region34dis provided on the n+-type cathode region34b. The p-type anode region34gis provided on the n−-type drift region34d. The p+-type anode region34his provided selectively on the p-type anode region34g. The anode electrode32is electrically connected to the p-type anode region34gand the p+-type anode region34h. The surface of the semiconductor portion34around the p-type anode region34gis covered with an insulating layer37. The cathode electrode31and the anode electrode32include a metal such as aluminum, nickel, copper, etc. The semiconductor portion34includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. The insulating layer37includes an insulating material such as silicon oxide, etc. FIG.15is a plan view illustrating an arrangement of the semiconductor chips of the semiconductor device according to the second embodiment.FIG.13is a B-B′ cross-sectional view ofFIG.15. InFIG.15, the semiconductor chips10and the semiconductor chips30are marked with mutually-different hatching. As illustrated inFIG.15, for example, the number of the semiconductor chips30is less than the number of the semiconductor chips10. The semiconductor chips30are provided at positions surrounded with the multiple semiconductor chips10. The multiple semiconductor chips30are provided to be adjacent to each other. Similarly to the semiconductor device100, the temperature increase of the semiconductor device200during operation can be suppressed by providing the semiconductor chips10further on the outer perimeter side of the semiconductor device200than the semiconductor chips30. Effects of the second embodiment will now be described with reference to the semiconductor device according to the reference example. FIG.16is a graph illustrating a characteristic of the semiconductor device according to the reference example. FIGS.17A and17Bare cross-sectional views illustrating operations of the semiconductor device according to the reference example. The case is considered where a bridge circuit is configured using multiple semiconductor devices100raccording to the reference example illustrated inFIG.5. In the bridge circuit, when one semiconductor device100ris switched from the ON-state to the OFF-state, an induced electromotive force is applied to the second metal plate42(the emitter electrode12) of another semiconductor device100r. A freewheeling current flows in the semiconductor chips10due to the induced electromotive force.FIG.16illustrates the characteristic of the semiconductor device100rat this time. InFIG.16, the horizontal axis is a voltage VEwith respect to the collector electrode11applied to the emitter electrode12. The vertical axis is a freewheeling current IFflowing from the emitter electrode12toward the collector electrode11. In the case of the semiconductor device100raccording to the reference example, snapback occurs as in the portion surrounded with the dotted line ofFIG.16when the voltage VEincreases to some magnitude. In the snapback, the current IFincreases; and the voltage VEdecreases abruptly. The snapback illustrated inFIG.16occurs because the semiconductor chip10is an RC-IGBT. When the induced electromotive force is applied to the emitter electrode12of the semiconductor chip10, there are cases where the potential of the gate electrode15is the threshold or more due to noise generated by the gate electrode15, etc. In such a case, as illustrated inFIG.17A, electrons flow through the channel of the p-type base region14efrom the collector electrode11to the emitter electrode12. When the electrons flow from the collector electrode11to the emitter electrode12, a large potential difference between the collector electrode11and the emitter electrode12is not generated easily. The potential difference between the n−-type drift region14dand the p-type anode region14gdoes not reach or exceed the built-in potential easily. As a result, holes are not injected into the n−-type drift region14d; and conductivity modulation does not occur in the n−-type drift region14d. An operation of MOS mode occurs instead of a diode operation in the semiconductor chip10. Subsequently, when the voltage VEincreases, the potential difference between the n−-type drift region14dand the p-type anode region14greaches or exceeds the built-in potential. As illustrated inFIG.17B, the holes are injected from the p-type anode region14g; and the electrical resistance of the semiconductor device100rdecreases. The current IFincreases; the voltage VEdecreases; and snapback such as that illustrated inFIG.16occurs. The power consumption of the operation of MOS mode illustrated inFIG.17Ais large compared to that of the diode operation illustrated inFIG.17B. Accordingly, the power consumption of the semiconductor device increases when the operation of MOS mode occurs. The semiconductor device200according to the second embodiment includes the semiconductor chip30in addition to the semiconductor chip10. The semiconductor chip30is a diode. As illustrated inFIG.14, the semiconductor chip30has a structure in which holes are injected during operation. An operation of MOS mode such as that illustrated inFIG.17Adoes not occur in the semiconductor chip30. When the electrons do not flow from the cathode electrode31to the anode electrode32, the potential difference between the cathode electrode31and the anode electrode32increases by that amount. The potential difference between the n−-type drift region34dand the p-type anode region34gdecreases. As a result, in the semiconductor chip30, the holes are injected from the p-type anode region34ginto the n−-type drift region34deven in the state in which the voltage applied to the semiconductor device200is low; and conductivity modulation occurs. The current flows mainly through the semiconductor chip30having the low electrical resistance; and the operation of MOS mode of the semiconductor chip10is suppressed. Subsequently, as the voltage VEincreases, the holes are injected into the n−-type drift region14din the semiconductor chip10as well; and conductivity modulation occurs. According to the semiconductor device200according to the embodiment, the occurrence of an operation of MOS mode such as that of the semiconductor device100raccording to the reference example when the freewheeling current flows can be suppressed. FIG.18AandFIG.18Bare graphs illustrating characteristics of the semiconductor device according to the second embodiment. InFIG.18AandFIG.18B, the horizontal axis is the voltage VE; and the vertical axis is the current IF.FIG.18Aillustrates the characteristics of the semiconductor chip10and the semiconductor chip30.FIG.18Billustrates the characteristic of the entire semiconductor device200. As illustrated inFIG.18AandFIG.18B, the characteristic of the semiconductor device200is substantially the combination of the portions of the characteristics of the semiconductor chip10and the semiconductor chip30, the portions having lower resistances. According to the second embodiment as illustrated inFIG.18B, the occurrence of the operation of MOS mode and the snapback of the semiconductor device200is suppressed; and it is possible to reduce the power consumption of the semiconductor device200. The semiconductor chip30may be a Schottky barrier diode instead of the p-n junction diode illustrated inFIG.14. In such a case, the anode electrode32includes a metal having a large work function such as Al, AlSi, etc.; and the n−-type drift region34dand the anode electrode32have a Schottky contact. FIG.19AtoFIG.20are plan views illustrating arrangements of the semiconductor chips of the semiconductor device according to the second embodiment. Arrangement examples of the semiconductor chips that are different from that ofFIG.13are illustrated inFIG.19AtoFIG.20. As illustrated inFIG.19A, the multiple semiconductor chips30may be provided to be separated from each other at the outer perimeter of the semiconductor device200. As illustrated inFIG.19B, the semiconductor chips30may be provided at both the center and the outer perimeter of the semiconductor device200. Or, as illustrated inFIG.20, the multiple semiconductor chips30may be provided to be separated from each other at middle portions between the center and the outer perimeter of the semiconductor device200. In these arrangements as well, the occurrence of the operation of MOS mode and the snapback of the semiconductor device200is suppressed; and it is possible to reduce the power consumption of the semiconductor device200. Third Embodiment FIG.21is a cross-sectional view illustrating a semiconductor device according to a third embodiment. As illustrated inFIG.21, the semiconductor device300according to the third embodiment includes the semiconductor chip10, the semiconductor chip20, and the semiconductor chip30. The first metal plate41includes the first electrically conductive portion41a, the third electrically conductive portion41c, and a fifth electrically conductive portion41e. The second metal plate42includes the second electrically conductive portion42b, the fourth electrically conductive portion42d, and a sixth electrically conductive portion42f. The collector electrode11(the first electrode) and the emitter electrode12(the second electrode) of the semiconductor chip10(the first semiconductor chip) are electrically connected respectively to the first electrically conductive portion41aand the second electrically conductive portion42b. The collector electrode21(the third electrode) and the emitter electrode22(the fourth electrode) of the semiconductor chip20(the second semiconductor chip) are electrically connected respectively to the third electrically conductive portion41cand the fourth electrically conductive portion42d. The cathode electrode31(the fifth electrode) and the anode electrode32(the sixth electrode) of the semiconductor chip30(a third semiconductor chip) are electrically connected respectively to the fifth electrically conductive portion41eand the sixth electrically conductive portion42f. By providing the semiconductor chips10to30, the occurrence of the snapback illustrated in bothFIG.6and FIG.16can be suppressed. In other words, according to the semiconductor device300according to the third embodiment, the power consumption in the ON-state in which the current flows from the first metal plate41toward the second metal plate42can be reduced; and the power consumption in the freewheeling state in which the current flows from the second metal plate42toward the first metal plate41can be reduced. FIG.22is a plan view illustrating an arrangement of the semiconductor chips of the semiconductor device according to the third embodiment. The semiconductor chips10to30are marked with mutually-different hatching inFIG.22. In the example illustrated inFIG.22, the arrangement of the semiconductor chips20and30is different from the example illustrated inFIG.21. In the semiconductor device300, for example, as illustrated inFIG.22, the number of the semiconductor chips10is more than the number of the semiconductor chips20and more than the number of the semiconductor chips30. The semiconductor chips20and the semiconductor chips30are provided at positions surrounded with the multiple semiconductor chips10. By providing the semiconductor chips10further on the outer perimeter side of the semiconductor device300than the semiconductor chips20and the semiconductor chips30, similarly to the semiconductor device100, the temperature increase of the semiconductor device300during operation can be suppressed. Modification FIGS.23A and23Bare cross-sectional views illustrating semiconductor chips of a semiconductor device according to a modification of the third embodiment. FIG.23AandFIG.23Brespectively illustrate the semiconductor chip20and the semiconductor chip30. In the semiconductor device according to the modification, all of the semiconductor chips10to30are RC-IGBTs. For example, the structure of the semiconductor chip10is the same as the structure illustrated inFIG.2. In the semiconductor chip20, for example, as illustrated inFIG.23A, the semiconductor portion24includes the p+-type collector region24a, an n+-type cathode region24b, the n-type buffer region24c, the n−-type drift region24d, the p-type base region24e, the n+-type emitter region24f, a p-type anode region24g, and a p+-type anode region24h. An electrically conductive portion26opposes the p-type anode region24gwith an insulating layer26ainterposed. For example, as illustrated inFIG.23B, the semiconductor chip30includes a collector electrode31c, an emitter electrode32e, a gate pad33, the semiconductor portion34, a gate electrode35, and an electrically conductive portion36. The collector electrode31cand the emitter electrode32eare electrically connected respectively to the fifth electrically conductive portion41eand the sixth electrically conductive portion42f. The gate pad33is electrically connected to the gate electrode35and is electrically connected to the metal plate43via the pin43a. The semiconductor portion34includes, for example, a p+-type collector region34a, the n+-type cathode region34b, an n-type buffer region34c, the n−-type drift region34d, a p-type base region34e, an n+-type emitter region34f, the p-type anode region34g, and the p+-type anode region34h. The functions of the components of the semiconductor portion34are respectively substantially the same as the functions of the components of the semiconductor portion14. Although all of the semiconductor chips10to30are RC-IGBTs, the ratios of the surface area of the region operating as the IGBT and the surface area of the region operating as the diode are different from each other. For example, the ratio of the surface area of the p+-type collector region14aand the surface area of the n+-type cathode region14bof the semiconductor chip10, the ratio of the surface area of the p+-type collector region24aand the surface area of the n+-type cathode region24bof the semiconductor chip20, and the ratio of the surface area of the p+-type collector region34aand the surface area of the n+-type cathode region34bof the semiconductor chip30are different from each other. For example, in the semiconductor chip20, compared to the semiconductor chip10, the surface area of the IGBT is large; and the surface area of the diode is small. In other words, the semiconductor chip20operates as an IGBT more easily than does the semiconductor chip10. In the semiconductor chip30, compared to the semiconductor chip10, the surface area of the diode is large; and the surface area of the IGBT is small. The semiconductor chip30operates as a diode more easily than does the semiconductor chip10. When the semiconductor chips10to30are set to the ON-state, operations of MOS mode such as that illustrated inFIG.7Aoccur in the semiconductor chips10to30. In the semiconductor chip20, because the surface area of the diode is small, the potential difference between the p+-type collector region24aand the n-type buffer region24cdecreases more easily than in the semiconductor chip10and the semiconductor chip30. Therefore, in the semiconductor chip20, the IGBT operation occurs faster than in the semiconductor chip10and the semiconductor chip30. As a result, the snapback in the ON-state is suppressed. Similarly, when the semiconductor chips10to30are in the freewheeling state, operations of MOS mode such as that illustrated inFIG.17Aoccur in the semiconductor chips10to30. In the semiconductor chip30, because the surface area of the IGBT is small, the potential difference between the n−-type drift region14dand the p-type anode region14gdecreases more easily than in the semiconductor chip10and the semiconductor chip20. Therefore, in the semiconductor chip30, the diode operation occurs faster than in the semiconductor chip10and the semiconductor chip20. As a result, the snapback in the freewheeling state is suppressed. According to the semiconductor device according to the modification, similarly to the semiconductor device300, the snapback in the ON-state and the freewheeling state can be suppressed; and the power consumption can be reduced. The structures of the semiconductor chips of the modification are applicable similarly to the semiconductor devices according to the first embodiment and the second embodiment. In other words, in the semiconductor device100according to the first embodiment, the semiconductor chip20may have the structure illustrated inFIG.23Ainstead of the structure illustrated inFIG.3. In the semiconductor device200according to the second embodiment, the semiconductor chip30may have the structure illustrated inFIG.23Binstead of the structure illustrated inFIG.14. Even in such cases, the snapback in the ON-state or the freewheeling state can be suppressed; and the power consumption can be reduced. To reduce the power consumption further, it is desirable for the semiconductor chip20to have only the function of the IGBT. It is desirable for the semiconductor chip30to have only the function of the diode. FIG.24AtoFIG.26Bare plan views illustrating arrangements of the semiconductor chips of the semiconductor device according to the third embodiment. FIG.24AtoFIG.26Billustrate arrangement examples of the semiconductor chips that are different from the one ofFIG.22. As illustrated inFIG.24A, the multiple semiconductor chips20may be provided at the center of the semiconductor device300; and the multiple semiconductor chips30may be provided to be separated from each other at the outer perimeter of the semiconductor device300. As illustrated inFIG.24B, the multiple semiconductor chips30may be provided at the center of the semiconductor device300; and the multiple semiconductor chips20may be provided to be separated from each other at the outer perimeter of the semiconductor device300. As illustrated inFIG.25A, the multiple semiconductor chips20may be provided to be separated from each other at the outer perimeter of the semiconductor device300; and the multiple semiconductor chips30may be provided to be separated from each other at middle portions between the center and the outer perimeter of the semiconductor device300. As illustrated inFIG.25B, the multiple semiconductor chips30may be provided to be separated from each other at the outer perimeter of the semiconductor device300; and the multiple semiconductor chips20may be provided to be separated from each other at middle portions between the center and the outer perimeter of the semiconductor device300. As illustrated inFIG.26A, the multiple semiconductor chips20and the multiple semiconductor chips30may be provided to be separated from each other at the outer perimeter of the semiconductor device300. As illustrated inFIG.26B, the multiple semiconductor chips20and the multiple semiconductor chips30may be provided to be separated from each other at middle portions between the center and the outer perimeter of the semiconductor device300. Fourth Embodiment FIG.27andFIG.28are perspective views illustrating a semiconductor device according to a fourth embodiment. FIG.29AandFIG.29Bare respectively a C-C′ cross-sectional view and a D-D′ cross-sectional view ofFIG.28. A sealing portion55and a third terminal73are not illustrated inFIG.28to illustrate the internal structure of the semiconductor device. As illustrated inFIG.27, the semiconductor device400includes a first substrate51, the sealing portion55, a first terminal71, a second terminal72, and the third terminal73. The sealing portion55seals the components mounted on the first substrate51. The first to third terminals71to73are terminals for electrically connecting the semiconductor device400to an external power supply and are exposed outside the sealing portion55. As illustrated inFIG.28, the semiconductor device400further includes the semiconductor chip10, the semiconductor chip20, the semiconductor chip30, a second substrate52, a first metal layer61, a second metal layer62, and a third metal layer63. The semiconductor chip10is an RC-IGBT. The semiconductor chip20is an IGBT. The semiconductor chip30is a diode connected in anti-parallel with the semiconductor chip10and the semiconductor chip20. The first substrate51has a first surface51aparallel to the X-direction and the Y-direction. The multiple second substrates52are provided to be separated from each other on the first surface51aof the first substrate51. The multiple first metal layers61, the second metal layer62, and the multiple third metal layers63are provided to be separated from each other on the second substrate52. These metal layers may be provided on the first substrate51directly without interposing the second substrate52. In the example illustrated inFIG.28, the semiconductor chips10and one of the semiconductor chip20or the semiconductor chip30are provided on each of the first metal layers61. The semiconductor chips10to30may be provided on each of the first metal layers61. In other words, each of the first metal layers61includes a first electrically conductive portion61aelectrically connected to the semiconductor chip10and at least one of a third electrically conductive portion61celectrically connected to the semiconductor chip20or a fifth electrically conductive portion61eelectrically connected to the semiconductor chip30. The numbers of the semiconductor chips10to30provided on the first metal layer61are arbitrary. A pair of first metal layers61, the second metal layer62, and a pair of semiconductor chips10that are provided on the second substrate52are illustrated inFIG.29A. As illustrated inFIG.29A, each of the first metal layers61includes the first electrically conductive portion61a. The semiconductor chip10is provided on the first electrically conductive portion61a; and the collector electrode11is electrically connected to the first electrically conductive portion61a. The second metal layer62includes a second electrically conductive portion62b. The emitter electrode12is electrically connected to the second electrically conductive portion62b. The gate pad13is electrically connected to the third metal layer63. A pair of first metal layers61and the second metal layer62are illustrated inFIG.29B. These metal layers are the same as the metal layers illustrated inFIG.29A. As illustrated inFIG.29B, one of the pair of first metal layers61includes the third electrically conductive portion61cin addition to the first electrically conductive portion61a. The other one of the pair of first metal layers61includes the fifth electrically conductive portion61ein addition to the first electrically conductive portion61a. The second metal layer62includes a fourth electrically conductive portion62dand a sixth electrically conductive portion62fin addition to the second electrically conductive portion62b. The semiconductor chip20is provided on the third electrically conductive portion61c; and the collector electrode21is electrically connected to the third electrically conductive portion61c. The emitter electrode22is electrically connected to the fourth electrically conductive portion62d. The gate pad23is electrically connected to the third metal layer63. The semiconductor chip30is provided on the fifth electrically conductive portion61eof the first metal layer61; and the cathode electrode31is electrically connected to the fifth electrically conductive portion61e. The anode electrode32is electrically connected to the other sixth electrically conductive portion62fof the second metal layer62recited above. In the example illustrated inFIG.28toFIG.29B, a portion of the multiple first metal layers61includes the first electrically conductive portion61aand the third electrically conductive portion61c; and the semiconductor chip10and the semiconductor chip20are provided on the portion of the multiple first metal layers61. Another portion of the multiple first metal layers61includes the first electrically conductive portion61aand the fifth electrically conductive portion61e; and the semiconductor chip10and the semiconductor chip30are provided on the other portion of the multiple first metal layers61. As illustrated inFIG.28, the multiple first metal layers61that are electrically connected to the semiconductor chips10to30are electrically connected to each other by the first terminal71. The first electrically conductive portion61a, the third electrically conductive portion61c, and the fifth electrically conductive portion61eare electrically connected to each other and are set to the same potential. The multiple second metal layers62are electrically connected to each other by the second terminal72. The second electrically conductive portion62b, the fourth electrically conductive portion62d, and the sixth electrically conductive portion62fare electrically connected to each other and are set to the same potential. The multiple third metal layers63are electrically connected to the third terminal73via a not-illustrated printed circuit board. The first substrate51includes an insulating material such as AlSiC, etc. The second substrate52includes an insulating material such as AlN, etc. The sealing portion55includes an insulating resin such as a silicone resin, etc. The first metal layer61, the second metal layer62, and the third metal layer63include a metal material such as copper, etc. The first terminal71, the second terminal72, and the third terminal73include a metal material such as copper, etc. As described above, the semiconductor device400includes the RC-IGBT semiconductor chip10, the IGBT semiconductor chip20, and the diode semiconductor chip30. According to the embodiment, similarly to the third embodiment, the occurrence of the snapback in the ON-state and the freewheeling state can be suppressed; and the power consumption of the semiconductor device can be reduced. FIG.30andFIG.31are plan views illustrating arrangements of the semiconductor chips of the semiconductor device according to the fourth embodiment. The arrangement of the semiconductor chips of the semiconductor device illustrated inFIG.28is schematically illustrated inFIG.30. For example, on one first metal layer61, the semiconductor chip20or the semiconductor chip30is provided further on the outer perimeter side of the semiconductor device400than the semiconductor chips10. Specifically, the semiconductor device400has a center C1in the X-direction (a first direction) and one end E1in the X-direction. A portion of the multiple semiconductor chips10, a portion of the multiple semiconductor chips20, and a portion of the multiple semiconductor chips30are provided between the center C1and the end E1. In these semiconductor chips, the distance in the X-direction between the end E1and the semiconductor chip20or the semiconductor chip30is shorter than the distance in the X-direction between the semiconductor chip10and the end E1. Or, as illustrated inFIG.31, on one first metal layer61, the semiconductor chip10may be provided further on the outer perimeter side of the semiconductor device400than the semiconductor chip20or the semiconductor chip30. The distance in the X-direction between the semiconductor chip10and the end E1may be shorter than the distance in the X-direction between the end E1and the semiconductor chip20or the semiconductor chip30. According to this configuration, the heat of the semiconductor chip10having larger heat generation can be released outside the semiconductor device400efficiently; and the temperature increase of the semiconductor device400can be suppressed. In the semiconductor chip20, heat is generated only in the ON-state. In the semiconductor chip30, heat is generated only in the freewheeling state. In the case where the multiple semiconductor chips20and the multiple semiconductor chips30are provided in the semiconductor device400, it is desirable for the semiconductor chips20to be separated from each other and for the semiconductor chips30to be separated from each other. For example, as illustrated inFIG.28,FIG.30, andFIG.31, on the two second substrates52adjacent to each other in the X-direction, it is desirable for the multiple semiconductor chips20to be positioned at opposite corners. It is desirable for the multiple semiconductor chips30to be positioned at other opposite corners. The semiconductor chip20and the semiconductor chip30oppose each other in the Y-direction. According to this configuration, the increase of the temperature of the semiconductor device400locally in the ON-state or the freewheeling state can be suppressed. It is possible to confirm the relative levels of the impurity concentrations of the semiconductor regions in the embodiments described above, for example, using a SCM (scanning capacitance microscope). The carrier concentrations of the semiconductor regions may be considered to be equal to the activated impurity concentrations of the semiconductor regions. Accordingly, the relative levels of the carrier concentrations of the semiconductor regions can be confirmed using SCM. It is possible to measure the impurity concentrations of the semiconductor regions, for example, using a SIMS (secondary ion mass spectrometer). While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Moreover, above-mentioned embodiments can be combined mutually and can be carried out. | 61,643 |
11862630 | DETAILED DESCRIPTION Embodiments described herein provide control transistors connected in a common electrode (e.g., source) configuration or implemented as a common electrode (e.g., source) bi-directional switch monolithically integrated with a main bi-directional switch. The monolithically integrated control transistors are configured to hold the semiconductor substrate of the bi-directional switch at a desired voltage during the on-state of the bi-directional switch, functioning as a discharge circuit that provides a discharge path for the semiconductor substrate. The gates of the monolithically integrated control transistors can be connected together and floating, disconnected from one another and each floating, connected together and connected to the sources of the bi-directional switch through respective diodes, or disconnected from each other and connected to the sources of the bi-directional switch through respective diodes. In each case, no additional gate drivers, auxiliary supplies or control components are required to ensure proper operation of the monolithically integrated control transistors, thus providing a fundamentally passive solution for holding the semiconductor substrate of the bi-directional switch at a desired voltage during the on-state of the bi-directional switch. While the discharge circuit described herein may be monolithically integrated with the main bi-directional switch, the discharge circuit instead may be external to (i.e. not integrated with) the main bi-directional switch. In this case, the electrical connections described herein between the discharge circuit and the main bi-directional switch may be formed through respective terminals of separate dies and/or packages which include the discharge circuit and the main bi-directional switch. Die-to-die, die-to-package, and package-to-package terminal connections are well known in the semiconductor device arts and can be implemented e.g. by wire bonds, metal clips, metal ribbons, solder bumps, die stacking, package stacking, etc., and hence no further explanation is given herein to such terminal connections. FIG.1illustrates a circuit schematic of an embodiment of a semiconductor device that includes a main bi-directional switch100and a discharge circuit102for providing a substrate discharge path during off-to-on switching of the bi-directional switch100. The main bi-directional switch100is formed on a semiconductor substrate which is schematically represented by the node labeled ‘SUB’ inFIG.1. The main bi-directional switch100has first and second gates G1, G2, first and second sources S1, S2, and a common drain. The first source S1of the main bi-directional switch100is electrically connected to a first voltage terminal Vss1. The second source S2of the main bi-directional switch100is electrically connected to a second voltage terminal Vss2. The main bi-directional switch100has four primary operational states: OFF/OFF in which both gates G1, G2of the main bi-directional switch100are off; ON/ON in which both gates G1, G2of the main bi-directional switch100are on; ON/OFF in which the first gate G1of the main bi-directional switch100is on and the second gate G2of the main bi-directional switch100is off; and OFF/ON in which the first gate G1of the main bi-directional switch100is off and the second gate G2of the main bi-directional switch100is on. The typical operation of a bi-directional switch includes transitioning from ON/OFF to ON/ON, and from OFF/ON to ON/ON. The current flow direction depends on the polarity across the first and second voltage terminals Vss1, Vss2. The current flow direction can be reversed by changing the polarity. The main bi-directional switch100is schematically represented by main transistors Q1and Q2inFIG.1. Main transistors Q1and Q2share a common drain, and have sources S1, S2at opposite ends of the main bi-directional switch100in the case of a lateral device. According to the embodiment shown inFIG.1, first and second substrate diodes Sb1and Sb2are monolithically integrated with the main bi-directional switch100. The anode of the first substrate diode Sb1and the anode of the second substrate diode Sb2are connected to the semiconductor substrate. The cathode of the first substrate diode Sb1is connected to the first source S1of the main bi-directional switch100, and the cathode of the second substrate diode Sb2is connected to the second source S2of the main bi-directional switch100. The discharge circuit102that provides a discharge path for the semiconductor substrate during the off-to-on switching of the main bi-directional switch100includes a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch100. For example, a pair of individual transistors or the auxiliary bi-directional switch is schematically represented by control transistors Q3and Q4inFIG.1. Control transistors Q3and Q4are connected to the semiconductor substrate in a common electrode (e.g., source) configuration. More particularly, the individual transistors or the auxiliary bi-directional switch represented by control transistors Q3and Q4inFIG.1includes a first electrode (e.g., drain) D3connected to the first source S1of the main bi-directional switch100, a second electrode (e.g., drain) D4connected to the second source S2of the main bi-directional switch100, a common electrode (e.g., source) S3/S4connected to the semiconductor substrate, and first and second gates G3, G4each decoupled from gate drive circuitry. Gates G3and G4are tied together and floating. Since the first and second gates G3, G4of the control transistors Q3and Q4are each decoupled from gate drive circuitry, the first and the second gates G3, G4of the discharge circuit102are controlled at least passively and based on the state of the main bi-directional switch100. In the off-state (ON/OFF or OFF/ON), the gates G1and G2of the main bi-directional switches100are on and off, respectively, and the main bi-directional switch100is in a blocking state. Under this condition, a relatively high voltage is applied at the first voltage terminal Vss1, control transistors Q3and Q4are not conducting, and most of the source voltage appears across main transistor Q2and control transistor Q3. If instead the source voltage is applied at the second voltage terminal Vss2, control transistors Q3and Q4are still not conducting and most of the source voltage appears across main transistor Q1and control transistor Q4. When the main bi-directional switch100transitions from the off-state (ON/OFF or OFF/ON) to the on-state (ON/ON), a current channel forms in the main bi-directional switch100and practically no voltage drop occurs across the switch100. Some of the stored charge in main transistors Q1and Q2and control transistor Q3or Q4discharges through main transistors Q1and Q2. In addition, the other stored charge discharges through control transistors Q3and Q4since both are on instantaneously or almost instantaneously during the off-to-on switching. For example, when the source voltage of the first voltage terminal Vss1changes from high positive voltage to low positive voltage, in other words, when Q2switches from off to on and Q1remains on, the gates G3, G4of control transistors Q3and Q4become more positive with respect to their common source terminal S3/S4which causes control transistors Q3and Q4to turn on, thereby providing a discharge path for the stored charge in the semiconductor substrate and de-biasing the substrate to 0V or close to 0V. As previously explained herein, the gates G3, G4of the control transistors Q3, Q4may be connected together and floating or disconnected from one another and each floating. The state of the gates G3, G4of the control transistors Q3, Q4is based on the state of the main bi-directional switch100.FIG.1illustrates the embodiment in which the gates G3, G4of the control transistors Q3, Q4are connected together and floating. FIG.2illustrates a circuit schematic of another embodiment of the semiconductor device in which the gates G3, G4of the control transistors Q3, Q4that form the individual transistors or the auxiliary bi-directional switch of the discharge circuit102are disconnected from one another and each floating. FIG.3illustrates the dynamic behavior of the semiconductor substrate potential (V_SUB) of the main bi-directional switch100for the discharge circuit gate configurations shown inFIGS.1and2. Without the discharge circuit102, the substrate potential would swing to a high negative voltage, going from OFF/ON state (or ON/OFF—either G1or G2ON and the other gate is OFF) to ON/ON state (both G1and G2are ON). The discharge circuit102shown inFIGS.1and2has a common electrode (e.g., source) connection to the semiconductor substrate which controls reliably the voltage on the substrate together with the back-to-back diodes during the operation of the main bi-directional switches. In the case when gate G1is ON and gate G2is OFF, a high voltage (e.g. 200 V) applied at the first voltage terminal Vss1is shared between substrate diode Sb1and control transistor Q3with very small drop across substrate diode Sb2, which keeps the semiconductor substrate at a lower voltage. As gate G2is switched ON while keeping gate G1ON, the control transistors Q3and Q4inFIGS.1and2each become conducting since the voltage of the common electrode (e.g., source) is sufficiently highly negative compared to that of their gates to turn on the control transistors Q3and Q4, pulling the semiconductor substrate down to the lower source potentials of the first and/or second sources S1, S2as the negative charge stored in the substrate is discharged through control transistors Q3, Q4. During the nanosecond interval where the control transistors Q3and Q4switch from OFF to ON, the semiconductor substrate potential tries to go negative, but quickly recovers to the desired voltage or close to 0V through the discharge path of control transistors Q3and/or Q4. While the semiconductor substrate experiences a negative voltage during this short interval (e.g. about 100 ns or less), the negative voltage excursion is significantly shorter than what the substrate would have otherwise experienced if the discharge circuit102were omitted. In the case without the discharge circuit, the substrate would be biased negatively at about half the full source voltage and the substrate diodes Sb1and Sb2would remain in a blocking state, preventing the substrate from fully discharging since there is no discharge path. With the discharge circuit102monolithically integrated with the main bi-directional switch100, both control transistors Q3and Q4act like diodes during the off-state (OFF/OFF, OFF/ON and ON/OFF). The potential of the semiconductor substrate for the common drain main bi-directional switch100tries to go negative as the bi-directional switch100transitions from the ON/OFF state or the OFF/ON state to ON/ON, but the control transistors Q3and Q4of the discharge circuit102respond almost immediately and discharge the charge stored in the substrate through the control transistors Q3and/or Q4. In some embodiments in which the main bi-directional switch100and the discharge circuit102are monolithically integrated in GaN technology, it can take approximately about 90 ns (about 11 MHz) or less for the control transistors Q3and Q4to switch ON and discharge the charge stored in the substrate through control transistors Q3and Q4. One voltage terminal (e.g., Vss1) can be a higher potential with respect to the other terminal (e.g., Vss2) and vice-versa. In each case, the discharge circuit102is configured to automatically discharge the charge stored at the semiconductor substrate to the sources S1and S2responsive to the main bi-directional switch100transitioning from the ON/OFF state or the OFF/ON state to the ON/ON state. In the embodiments shown inFIGS.1and2, the gates G3, G4of control transistors Q3, Q4that form the individual transistors or the auxiliary bi-directional switch of the discharge circuit102are floating and self-defined based on the floating potentials of the substrate and the control transistor gate. FIG.4illustrates a circuit schematic of yet another embodiment of a semiconductor device that includes the main bi-directional switch100and the discharge circuit102. The embodiment shown inFIG.4is similar to the embodiments shown inFIGS.1and2. Different, however, a first auxiliary diode GD1and a second auxiliary diode GD2are also monolithically integrated with the main bi-directional switch100. The anode of the first auxiliary diode GD1is connected to the gate G3of control transistor Q3of the discharge circuit102. The cathode of the first auxiliary diode GD1is connected to the first source S1of the main bi-directional switch100. The anode of the second auxiliary diode GD2is similarly connected to the gate G4of control transistor Q4of the discharge circuit102. The cathode of the second auxiliary diode GD2is connected to the second source S2of the main bi-directional switch100. Further according to this embodiment, the gate G3of control transistor Q3of the discharge circuit102is interposed between the first drain D3and the common source S3/S4of the discharge circuit102. The gate G4of control transistor Q4of the discharge circuit102is interposed between the common source S3/S4and the second drain D4of the discharge circuit102. With the configuration shown inFIG.4, the gates G3, G4of the control transistors Q3, Q4are connected respectively to the first and second voltage terminals Vss1and Vss2through the corresponding auxiliary diodes GD1and GD2. The auxiliary diodes GD1and GD2can be simple diodes or FETs connected in diode mode (gate-source shorted together), as explained in more detail later herein. Similar to the embodiments shown inFIGS.1and2, there no additional gate drivers, auxiliary supplies or control components are required for the embodiment shown inFIG.4. FIG.5illustrates the dynamic behavior of the semiconductor substrate potential (V_SUB) of the main bi-directional switch100for the discharge circuit gate configuration shown inFIG.4. When gate G1is ON, gate G2is OFF and a relatively high voltage is applied at the first voltage terminal Vss1, the high voltage being shared between substrate diode Sb1, control transistor Q3and auxiliary diode GD1. A very low voltage occurs across control transistor Q4, substrate diode Sb2and auxiliary diode GD2. When gate G2is turned ON, control transistors Q3and Q4with auxiliary diodes GD1and GD2ensure a momentary or almost momentary short or near short between the semiconductor substrate and the second source S2, thus leading to discharging and keeping the substrate stable at lower potential closer to 0V. During the off-to-on switching, the configurations shown inFIGS.1,2and4each have a characteristic signature of a brief negative voltage spike at the semiconductor substrate as shown inFIGS.3and5, which occurs momentarily before the semiconductor substrate potential of the main bi-directional switch100stabilizes to a small value. As explained above, the negative voltage excursion experienced by the semiconductor substrate is significantly shorter than what the substrate would have otherwise experienced if the discharge circuit102were omitted. FIG.6illustrates a circuit schematic of still another embodiment of a semiconductor device that includes the main bi-directional switch100and the discharge circuit102. The embodiment shown inFIG.6is similar to the embodiment shown inFIG.4. Different, however, the anode connections of the auxiliary diodes GD1, GD2are reversed. That is, the anode of the first auxiliary diode GD1is connected to the gate G4of control transistor Q4of the discharge circuit102instead of the gate G3of control transistor Q3. The anode of the second auxiliary diode GD2is connected to the gate G3of control transistor Q3of the discharge circuit102instead of the gate G4of control transistor Q4. It is believed that the auxiliary diode configuration shown inFIG.6eliminates or significantly reduces the characteristic signature of a brief negative voltage spike at the semiconductor substrate before the semiconductor substrate of the main bi-directional switch100stabilizes to a small value. FIG.7illustrates a circuit schematic of another embodiment of a semiconductor device that includes the main bi-directional switch100and the discharge circuit102. The embodiment shown inFIG.7is similar to the embodiment shown inFIG.6. Different, however, the substrate diodes Sb1and Sb2are omitted. According to this embodiment, the semiconductor device that includes the discharge circuit102monolithically integrated with the main bi-directional switch100is devoid of diode connections between the first source S1of the main bi-directional switch100and the semiconductor substrate, and between the second source S2of the main bi-directional switch100and the semiconductor substrate. FIG.8illustrates the dynamic behavior of the semiconductor substrate potential (V_SUB) of the main bi-directional switch100for the discharge circuit gate configurations shown inFIGS.6and7. The dynamic characteristic behavior of the semiconductor substrate with the discharge circuit control transistors Q3, Q4can be suppressed without impacting the stability of the semiconductor substrate. When voltage terminal Vss1is at high voltage, the auxiliary diode GD1is in series with control transistor Q4and the auxiliary diode GD2is in series with control transistor Q3. Control transistors Q3and/or Q4turn on for a short time during the off-to-on switching. With this configuration, the negative voltage spike at the semiconductor substrate at the beginning of the turn ON of the main bi-directional switch100is effectively eliminated. In each of the circuit configurations shown inFIGS.1,2,4,6and7, the discharge circuit102is monolithically integrated with the main bi-directional switch100of the semiconductor device. The discharge circuit102is connected in a common source configuration to the semiconductor substrate of the main bi-directional switch100. The gates G3, G4of the monolithically integrated control transistors Q3, Q4can be connected together and floating, disconnected from one another and each floating, connected together and connected to the sources of the main bi-directional switch100through respective diodes, or disconnected from each other and connected to the sources of the main bi-directional switch100through respective diodes. Described next are various device embodiments of the main bi-directional switch100and monolithically integrated discharge circuit102. FIG.9illustrates a cross-sectional view of an embodiment of the main bi-directional switch100, implemented as part of a compound semiconductor device in III-nitride technology such as GaN high electron mobility transistor (HEMT). The main bi-directional switch100is formed on a semiconductor substrate200such as a Si substrate or one or more epitaxially-grown or implanted Si layers on Si substrate. A III-nitride buffer region202(e.g., GaN) is formed over the semiconductor substrate200, a III-nitride channel region203(e.g., GaN) is formed over the III-nitride buffer region202, and a III-nitride barrier region204(e.g., AlGaN) is formed over the III-nitride channel region203. The HEMT can be a normally-on device in which the channel is uninterrupted along the gate absent a gate voltage, or a normally-off device in which the channel is interrupted along the gate absent a gate voltage. For example, in the case of a normally-off device, the HEMT may include a p-doped III-nitride layer205between the gates G1, G2and the underlying III-nitride barrier region204. In the case of a normally-on device, the p-doped III-nitride layer205between the gates G1, G2and the underlying III-nitride barrier region204may be omitted. The presence of polarization charges and strain effects in a GaN-based heterostructure body due to spontaneous and piezoelectric polarization yield a two-dimensional charge carrier gas in the heterostructure body characterized by very high carrier density and carrier mobility. This two-dimensional charge carrier gas, such as a 2DEG (two-dimensional electron gas) or 2DHG (two-dimensional hole gas), forms the conductive channel of the main bi-directional switch100near the interface between the III-nitride barrier204, e.g., a GaN alloy barrier such as AlGaN, InAlGaN, InAlN, etc. and the III-nitride channel region203(e.g., GaN channel layer). A thin, e.g. 1-2 nm, AlN layer can be provided between the III-nitride channel region203and the GaN alloy barrier204to minimize alloy scattering and enhance 2DEG mobility. The III-nitride buffer, channel and barrier regions202,203,204can be manufactured on a semiconductor substrate200such as a Si, SiC or sapphire substrate, on which a nucleation (seed) layer such as an AlN layer can be formed for providing thermal and lattice matching to the III-nitride buffer region202and/or III-nitride channel region203. The compound semiconductor device may also have AlInN/AlN/GaN barrier/spacer/channel layer/buffer layer structures. In general, the compound semiconductor device can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects. The transistors labeled Q1and Q2inFIGS.1,2,4,6and7represent the main bi-directional switch100. Transistors Q1and Q2can be implemented as first and second gates G1, G2, first and second sources S1, S2, and a common drain formed in the III-nitride heterostructure body202/203/204. The common drain is positioned between the gates G1, G2. When the high voltage is applied to source S1, the drain of the main bi-directional switch100is formed by gate G1and source S1. Conversely, when the high voltage is applied to source S2, the drain of the main bi-directional switch100is formed by gate G2and source S2. By spacing source S1the same distance to gate G1as source S2is spaced to gate G2, the main bi-directional switch100is symmetric.FIG.9also schematically illustrates the substrate diodes Sb1, Sb2shown inFIGS.1,2,4and6. A substrate electrode206such as a backside metallization layer may be provided to form an ohmic connection with the backside of the substrate200. FIGS.10A and10Billustrate respective cross-sectional views of embodiments of the substrate diodes Sb1, Sb2shown inFIGS.1,2,4and6. The substrate diodes Sb1, Sb2are monolithically integrated with the main bi-directional switch100, which is out of view inFIGS.10A and10B. Each substrate diode Sb1, Sb2can be a GaN diode that includes a p-doped region (e.g., pGaN) with an electrode208such as the anode (A), a two-dimensional electron gas (2DEG) and another electrode210such as the cathode (K). The 2DEG can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped regions on the III-nitride barrier region204can be formed by doping or growing the III-nitride channel region203with an appropriate dopant species such as magnesium. Since the anodes of the substrate diodes Sb1, Sb2are (electrically) connected to the semiconductor substrate200as shown inFIGS.1,2,4and6, the p-doped regions with their electrodes can be formed as separate regions which are electrically connected together or as a single p-doped region with its single electrode. Since both anode electrodes208are electrically connected together, a single common electrode208′ may be used as shown inFIG.10Binstead of two separate electrodes208as shown inFIG.10A. FIGS.11A and11Billustrate respective cross-sectional views of embodiments of the substrate diodes Sb1, Sb2shown inFIGS.1,2,4and6. According to the embodiments shown inFIGS.11A and11B, the substrate diodes Sb1, Sb2are each implemented as a GaN transistor having its gate electrode212connected to one of its power electrodes214(e.g., source). The electrode214connected to the gate acts as the anode and the other electrode216is defined as the cathode. The anodes (A) and the gates (G) of the substrate diodes Sb1, Sb2are (electrically) connected to the semiconductor substrate200, and the p-doped anode regions can be formed as separate regions which are electrically connected together. Each cathode (K) of the substrate diodes Sb1, Sb2is connected to Vss1or Vss2, respectively. Since both electrodes214tied to the gates (G) in the substrate diodes Sb1and Sb2are electrically connected, a single common electrode214′ may be used as shown inFIG.11Binstead of two separate electrodes214as shown inFIG.11A. FIG.12illustrates a cross-sectional view of the circuit embodiment shown inFIG.7, implemented as part of a compound semiconductor device in a III-nitride technology such as GaN. Similar toFIG.9, the main bi-directional switch100is formed on a semiconductor substrate200such as a Si substrate or one or more epitaxially-grown or implanted Si layers on Si substrate. A III-nitride buffer region202is formed over the semiconductor substrate200, a III-nitride channel region203(e.g., GaN) is formed over the III-nitride buffer region202, and a III-nitride barrier region204is formed over the III-nitride channel region203. Transistors Q1and Q2shown inFIG.7can be implemented as first and second gates G1, G2, first and second sources S1, S2, and a common drain. The common drain is positioned between the gates G1, G2. By spacing source S1the same distance to gate G1as source S2is spaced to gate G2, the main bi-directional switch100is symmetric.FIG.12also schematically illustrates the discharge circuit102and corresponding auxiliary diodes GD1, GD2shown inFIG.7. FIGS.13A and13Billustrate respective cross-sectional views of embodiments of the auxiliary diodes GD1, GD2shown inFIG.4. The auxiliary diodes GD1, GD2are monolithically integrated with the main bi-directional switch100and the discharge circuit102, which are out of view inFIGS.13A and13B. Each auxiliary diode GD1, GD2can be a GaN diode that includes a p-doped region205(e.g., pGaN) with one electrode218as the anode (A) and another electrode220on III-nitride barrier204(i.e., AlGaN) as the cathode (K). A two-dimensional electron gas (2DEG) can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped anode regions205on the III-nitride barrier region204can be formed by doping or growing a III-nitride layer with an appropriate dopant species such as magnesium. Since the anode (A) of each auxiliary diode GD1, GD2is (electrically) connected to one of the gates G3/G4of the control transistors Q3, Q4as shown inFIG.4, the p-doped anode region205of each auxiliary diode GD1, GD2can be formed as two separate regions with two separate electrodes218which are electrically connected together as shown inFIG.13A, or instead as a single p-doped region205′ and corresponding single electrode218′ as shown inFIG.13B. FIGS.14A and14Billustrate respective cross-sectional views of embodiments of the auxiliary diodes GD1, GD2shown inFIG.4. According to the embodiments shown inFIGS.14A and14B, the auxiliary diodes GD1, GD2are each implemented as a GaN transistor having a gate (G) electrode220connected to a first electrode222(e.g., source). The other electrode224of each GaN transistor is defined as the cathode (K). The source region of each auxiliary diode GD1, GD2can be formed as separate electrodes222which are electrically connected together as shown inFIG.14A, or instead as a single electrode222′ as shown inFIG.14B. Similarly, the p-doped regions205and gate electrodes220of each auxiliary diode GD1, GD2can be formed as separate gate regions which are electrically connected together or as a single gate region. FIG.15illustrates a cross-sectional view of an embodiment of the auxiliary diodes GD1, GD2shown inFIGS.4,6,7, and12. The auxiliary diodes GD1, GD2are monolithically integrated with the main bi-directional switch100and the discharge circuit102, which are out of view inFIG.15. Each auxiliary diode GD1, GD2can be a GaN diode that includes a p-doped region205(e.g., pGaN) with one electrode226as the anode (A) and another electrode228on the III-nitride barrier region204(e.g., AlGaN) as the cathode (K). A two-dimensional electron gas (2DEG) can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped anode region205on the III-nitride barrier region204can be formed by growing a III-nitride layer with an appropriate dopant species such as magnesium. FIG.16illustrates a cross-sectional view of another embodiment of the auxiliary diodes GD1, GD2shown inFIGS.4,6,7and12. According to this embodiment, the auxiliary diode GD1, GD2are each implemented as a GaN transistor having a gate (G) electrode230connected to one electrode232(e.g., source). The other electrode234of each GaN transistor is defined as the cathode (K). FIGS.17A and17Billustrate respective cross-sectional views of embodiments of the control transistors Q3, Q4that form the monolithically integrated discharge circuit102shown inFIGS.1,2,4,6,7and12. According to the embodiments shown inFIGS.17A and17B, the control transistors Q3, Q4are implemented as individual GaN transistors or as an auxiliary bi-directional GaN switch monolithically integrated with the main bi-directional switch100which is out of view onFIG.17. Both gates G3and G4are connected together inFIG.1and floating, and are separate and floating inFIG.2. Gates G3and G4are connected to the corresponding anode of auxiliary diodes GD1and GD2, respectively, inFIG.4and are disconnected to the corresponding anode of auxiliary diodes GD1and GD2, respectively, inFIGS.6,7, and12. Transistors Q3and Q4of the discharge circuit102can be implemented as first and second gates G3, G4, first and second drains D3, D4, and a common source S3/S4formed in the III-nitride heterostructure body202/203/204. The common source S3/S4is positioned between the gates G3, G4. The gates G3, G4of the control transistors Q3, Q4are each decoupled from gate drive circuitry as previously described herein. Hence, the gates G3, G4of the discharge circuit102are controlled at least passively (and possibly actively) and based on the state of the main bi-directional switch100. The common source region S3/S4can be formed as separate electrodes236which are electrically connected together as shown inFIG.17A, or instead as a single electrode236′ as shown inFIG.17B. FIG.18illustrates a cross-sectional view of the circuit embodiment shown inFIG.6, implemented as part of a compound semiconductor device in III-nitride technology such as GaN. Similar toFIG.9, the main bi-directional switch100is formed on a semiconductor substrate200such as a Si substrate and one or more optional buffer layers. A III-nitride buffer region202is formed over the semiconductor substrate200, a III-nitride channel region203(e.g., GaN) is formed over the III-nitride buffer region202, and a III-nitride barrier region204is formed over the III-nitride channel region203. The main transistors Q1and Q2shown inFIG.6can be implemented as first and second gates G1, G2, first and second sources S1, S2, and a common drain. The common drain is positioned between the gates G1, G2.FIG.18also schematically illustrates the discharge circuit102with the auxiliary diodes GD1, GD2and the substrate diodes Sb1, Sb2shown inFIG.6. As previously explained herein, the substrate diodes Sb1, Sb2and the auxiliary diodes GD1, GD2shown inFIGS.6and18can each be monolithically integrated with the main bi-directional switch100and the discharge circuit102, e.g., as shown inFIGS.13A through16. For example, each substrate diode Sb1and Sb2shown inFIGS.6and18can be a GaN diode that includes a p-doped region (e.g., pGaN) with an electrode (Anode, A) and a two-dimensional electron hole gas (2DEG) with another electrode (Cathode, K). The 2DEG can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped regions205on the III-nitride barrier region204can be formed by doping a III-nitride layer203with an appropriate dopant species such as magnesium. Since the anodes of the substrate diodes Sb1, Sb2are (electrically) connected to the semiconductor substrate200as shown inFIGS.6and18, the p-doped regions with their electrodes can be formed as separate regions which are electrically connected together or as a single p-doped region with its single electrode. In another embodiment, the substrate diodes Sb1, Sb2are each implemented as a GaN transistor having its gate (G) connected to one of its electrodes. The electrode connected to the gate acts as the anode and the other electrode is defined as the cathode. Both anodes are electrically connected to each other while each cathode is connected to Vss1or Vss2, e.g., shown inFIG.6. Since both electrodes tied to the gates in the substrate gated diodes Sb1and Sb2are electrically connected, a single common electrode can be used instead of two separate electrodes. Each auxiliary diode GD1, GD2may include a p-doped region205(e.g., pGaN) with its electrode as the anode and another electrode on the III-nitride barrier region204(e.g., AlGaN) as the cathode. A two-dimensional electron gas (2DEG) can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped anode regions205on the III-nitride barrier region204can be formed by growing a III-nitride layer with an appropriate dopant species such as magnesium. In yet another embodiment, the auxiliary diode GD1, GD2may be each implemented as a GaN transistor having its gate (G) connected to its electrodes (e.g., source). Since the anode of each auxiliary diode GD1, GD2is (electrically) connected to one of the gates G3/G4of the control transistors Q3, Q4e.g. as shown inFIGS.6and18, the p-doped anode region205of each auxiliary diode GD1, GD2may be formed as two separate regions. Similar to the control transistors Q3, Q4that form the monolithically integrated discharge circuit102shown inFIGS.6and18, the control transistors Q3, Q4may be implemented as a pair of individual GaN transistors or an auxiliary bi-directional GaN switch monolithically integrated with the main bi-directional switch100, e.g., as shown inFIGS.17A and17B. For example, the control transistors Q3and Q4of the discharge circuit102can be implemented as first and second gates G3, G4, first and second drains D3, D4, and a common source S3/S4formed in the III-nitride heterostructure body202/203/204. The common source S3/S4is positioned between the gates G3, G4. The gates G3, G4of the control transistors Q3, Q4are each decoupled from gate drive circuitry as previously described herein. Hence, the gates G3, G4of the discharge circuit102are controlled at least passively (and possibly actively) and based on the state of the main bi-directional switch100. The common source region S3/S4can be formed as separate electrodes which are electrically connected together or as a single electrode. FIG.19illustrates a cross-sectional view of the circuit embodiment shown inFIG.1, implemented as part of a compound semiconductor device in III-nitride technology such as GaN. Similar toFIG.9, the main bi-directional switch100is formed on a semiconductor substrate200such as a Si substrate or one or more epitaxially-grown or implanted Si layers on Si substrate. A III-nitride buffer region202is formed over the semiconductor substrate200, a III-nitride channel region203(e.g., GaN) is formed over the III-nitride buffer region202, and a III-nitride barrier region204is formed over III-nitride channel region203. The main transistors Q1and Q2shown inFIG.1can be implemented as first and second gates G1, G2, first and second sources S1, S2, and a common drain. The common drain is positioned between the gates G1, G2.FIG.19also schematically illustrates the discharge circuit102and the substrate diodes Sb1, Sb2shown inFIG.1. As previously explained herein, the substrate diodes Sb1, Sb2shown inFIGS.1and19can be a GaN diode that includes a p-doped region205(e.g., pGaN) with an electrode (Anode, A) and a two-dimensional electron hole gas (2DEG) with another electrode (Cathode, K), e.g., as shown inFIGS.10A and10B. The 2DEG can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped regions205on the III-nitride barrier region204can be formed by doping a III-nitride layer203with an appropriate dopant species such as magnesium. Since the anodes of the substrate diodes Sb1, Sb2are (electrically) connected to the semiconductor substrate200as shown inFIG.1, the p-doped anode regions can be formed as separate regions which are electrically connected together e.g. as shown inFIG.10A, or as a single p-doped region e.g. as shown inFIG.10B. The substrate diodes Sb1, Sb2can instead be implemented as respective GaN transistors each having its gate (G) connected to its source (S), e.g., as shown inFIGS.11A and11B. Since the anodes and the gates of the substrate diodes Sb1, Sb2are (electrically) connected to the semiconductor substrate200, the p-doped anode regions205can be formed as separate regions which are electrically connected together or as a single p-doped region. Similarly, the control transistors Q3, Q4that form the monolithically integrated discharge circuit102shown inFIGS.1and24can be implemented as first and second gates G3, G4, first and second drains D3, D4, and a common source S3/S4formed in the III-nitride heterostructure body202/203/204, e.g., as shown inFIGS.17A and17B. The common source S3/S4is positioned between the gates G3, G4. The gates G3, G4of the control transistors Q3and Q4are each decoupled from gate drive circuitry as previously described herein. Hence, the gates G3, G4of the discharge circuit102are controlled at least passively (and possibly actively) and based on the state of the main bi-directional switch100. The common source region S3/S4can be formed as separate electrodes which are electrically connected together or as a single electrode. The gates G3, G4of the monolithically integrated control transistors Q3, Q4are connected together may be floating. This connection can be formed by a metal line, for example. The connection can be omitted so that the gates G3, G4of the monolithically integrated control transistors Q3, Q4are disconnected from one another and each floating, for example as shown inFIG.2. FIG.20illustrates a cross-sectional view of the circuit embodiment shown inFIG.4, implemented as part of a compound semiconductor device in III-nitride technology such as GaN. Similar toFIG.9, the main bi-directional switch100is formed on a semiconductor substrate200such as a Si substrate and one or more optional buffer layers. A III-nitride buffer region202is formed over the semiconductor substrate200, a III-nitride channel region203(e.g., GaN) is formed over the III-nitride buffer region202, and a III-nitride barrier region204is formed over the III-nitride channel region203. Transistors Q1and Q2show inFIG.4can be implemented as first and second gates G1, G2, first and second sources S1, S2, and a common drain. The common drain is positioned between the gates G1, G2.FIG.20also schematically illustrates the discharge circuit102, the substrate diodes Sb1, Sb2and the auxiliary diodes GD1, GD2shown inFIG.4. Each diode Sb1, Sb2, GD1, GD2is monolithically integrated with the main bi-directional switch100and the discharge circuit102, and can be a p-doped region205(e.g., pGaN) with an electrode (Anode, A) and a two-dimensional electron gas (2DEG) with another electrode (Cathode, K), e.g., as shown inFIGS.10A and10Bfor the substrate diodes Sb1, Sb2andFIGS.13A and13Bfor the auxiliary diodes GD1, GD2. The 2DEG can be formed by spontaneous and piezoelectric polarization between the III-nitride channel region203and the III-nitride barrier region204in a diode region of the device. The p-doped regions205on the III-nitride barrier region204can be formed by doping a III-nitride layer203with an appropriate dopant species such as magnesium. The anode of each auxiliary diode GD1, GD2is (electrically) connected to one of the gates G3/G4of the control transistors Q3, Q4as shown inFIGS.4and20. The p-doped anode region of each auxiliary diode GD1, GD2can be formed as two separate regions which are electrically connected together or as a single p-doped region. In the case of the substrate diodes Sb1, Sb2, the anodes are (electrically) connected to the semiconductor substrate200as shown inFIG.4and can be formed as separate p-doped regions which are electrically connected together or as a single p-doped region. Each diode Sb1, Sb2, GD1, GD2can be implemented as a GaN transistor having its gate (G) connected to its source (S), e.g., as shown inFIGS.11A and11Bfor the substrate diodes Sb1, Sb2andFIGS.14A and14Bfor the auxiliary diodes GD1, GD2. The anodes of the substrate diodes Sb1, Sb2and the auxiliary diodes GD1, GD2are (electrically) connected to the semiconductor substrate200. The gate regions of the substrate diodes Sb1, Sb2and the auxiliary diodes GD1, GD2are formed as separate regions which are electrically connected together. The control transistors Q3, Q4that form the monolithically integrated discharge circuit102shown inFIGS.4and20can be implemented as first and second gates G3, G4, first and second drains D3, D4, and a common source S3/S4formed in the III-nitride heterostructure body202/203/204, e.g., as shown inFIGS.17A and17B. The common source S3/S4is positioned between the gates G3, G4. The gates G3, G4of the control transistors Q3and Q4are each decoupled from gate drive circuitry as previously described herein. Hence, the gates G3, G4of the discharge circuit102are controlled at least passively (and possibly actively) and based on the state of the main bi-directional switch100. The common source region S3/S4can be formed as separate electrodes which are electrically connected together or as a single electrode. The control transistors Q3and Q4of the monolithically integrated discharge circuit102can be high ohmic devices i.e. devices having a higher Rdson (on-state resistance) than the transistors Q1, Q2of the main bi-directional switch100. By using high ohmic devices, significant active area or change to the overall design is not required to monolithically integrate the discharge circuit102with the main bi-directional switch100. For example, the control transistors Q3and Q4of the discharge circuit102may have an Rdson greater than 1 Ohm, and/or the size of control transistors Q3and Q4may be between 1/50 and 1/100 the size of the main bi-directional switch100. The main bi-directional switch100and monolithically integrated discharge circuit102can form part of a power circuit, wherein the main bi-directional switch100enables bi-directional current flow within the power circuit. For example, the power circuit can be a bridgeless PFC (power factor correction) stage, a solar microinverter, an AC-DC converter, an AC-AC converter, an AC flyback converter, etc. Still other types of power circuits having bi-directional current flow can use the main bi-directional switch100and monolithically integrated discharge circuit102. FIG.21illustrates a cross-sectional view of an embodiment of the main bi-directional switch100, implemented as part of a compound semiconductor device in III-nitride technology such as GaN high electron mobility transistor (HEMT). The embodiment shown inFIG.21is similar to the embodiment shown inFIG.9. In addition, substrate control circuitry300is also shown which is electrically connected to the substrate200. FIG.22illustrates a top plan view of a semiconductor die (chip)400that includes the compound semiconductor device shown inFIG.21. The semiconductor die400also includes respective gate electrodes402,404for providing points of external electrical connection to the gates (G1, G2) of the transistors Q1, Q2of the main bi-directional switch100, and respective source electrodes406,408for providing points of external electrical connection to the sources (S1, S2) of the transistors Q1, Q2of the main bi-directional switch100. The transistors Q1, Q2of the main bi-directional switch100are implemented in an active device area410of the semiconductor die400. The semiconductor die400further includes a substrate electrode206for providing a point of external electrical connection to the semiconductor substrate200. The electrodes206,402,404,406,408may be provided as one or more patterned metallization layers of the semiconductor die400. FIG.23illustrates a cross-sectional view of another embodiment of the main bi-directional switch100, implemented as part of a compound semiconductor device in III-nitride technology such as GaN high electron mobility transistor (HEMT). The embodiment shown inFIG.23is similar to the embodiment shown inFIG.21. Different, however, the substrate diodes Sb1and Sb2are omitted. FIG.24illustrates a top plan view of a semiconductor die (chip)500that includes the compound semiconductor device shown inFIG.23. The semiconductor die500also includes respective gate electrodes402,404for providing points of external electrical connection to the gates (G1, G2) of the transistors Q1, Q2of the main bi-directional switch100, and respective source electrodes406,408for providing points of external electrical connection to the sources (S1, S2) of the transistors Q1, Q2of the main bi-directional switch100, as explained above. The semiconductor die400further includes a substrate electrode206for providing a point of external electrical connection to the semiconductor substrate200, as explained above. Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description. As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents. | 47,425 |
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